1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _HXGE_PFC_HW_H 27 #define _HXGE_PFC_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define PFC_BASE_ADDR 0X0200000 36 37 #define PFC_VLAN_TABLE (PFC_BASE_ADDR + 0x0) 38 #define PFC_VLAN_CTRL (PFC_BASE_ADDR + 0x9000) 39 #define PFC_MAC_ADDR (PFC_BASE_ADDR + 0x10000) 40 #define PFC_MAC_ADDR_MASK (PFC_BASE_ADDR + 0x10080) 41 #define PFC_HASH_TABLE (PFC_BASE_ADDR + 0x10100) 42 #define PFC_L2_CLASS_CONFIG (PFC_BASE_ADDR + 0x20000) 43 #define PFC_L3_CLASS_CONFIG (PFC_BASE_ADDR + 0x20030) 44 #define PFC_TCAM_KEY0 (PFC_BASE_ADDR + 0x20090) 45 #define PFC_TCAM_KEY1 (PFC_BASE_ADDR + 0x20098) 46 #define PFC_TCAM_MASK0 (PFC_BASE_ADDR + 0x200B0) 47 #define PFC_TCAM_MASK1 (PFC_BASE_ADDR + 0x200B8) 48 #define PFC_TCAM_CTRL (PFC_BASE_ADDR + 0x200D0) 49 #define PFC_CONFIG (PFC_BASE_ADDR + 0x20100) 50 #define TCP_CTRL_MASK (PFC_BASE_ADDR + 0x20108) 51 #define SRC_HASH_VAL (PFC_BASE_ADDR + 0x20110) 52 #define PFC_INT_STATUS (PFC_BASE_ADDR + 0x30000) 53 #define PFC_DBG_INT_STATUS (PFC_BASE_ADDR + 0x30008) 54 #define PFC_INT_MASK (PFC_BASE_ADDR + 0x30100) 55 #define PFC_DROP_LOG (PFC_BASE_ADDR + 0x30200) 56 #define PFC_DROP_LOG_MASK (PFC_BASE_ADDR + 0x30208) 57 #define PFC_VLAN_PAR_ERR_LOG (PFC_BASE_ADDR + 0x30210) 58 #define PFC_TCAM_PAR_ERR_LOG (PFC_BASE_ADDR + 0x30218) 59 #define PFC_BAD_CS_COUNTER (PFC_BASE_ADDR + 0x30220) 60 #define PFC_DROP_COUNTER (PFC_BASE_ADDR + 0x30228) 61 #define PFC_AUTO_INIT (PFC_BASE_ADDR + 0x30300) 62 63 64 /* 65 * Register: PfcVlanTable 66 * VLAN Table Registers 67 * Description: VLAN membership table. CPU programs in the VLANs that 68 * it wants to belong to. A blade may be a member of multiple VLANs. 69 * Bits [31:0] of the first entry corresponds to vlan members [31:0], 70 * bits [31:0] of the second entry corresponds to vlan members 71 * [63:32] and so on. 72 * Fields: 73 * Odd parities of member[31:24], member[23:16], member[17:8], 74 * member[7:0]. These parity bits are ignored when parEn in the 75 * VLAN Control register is set to '0'. 76 * Set to 1 to indicate that blade is a member of the VLAN IDs 77 * (32 to 0) * entry number 78 */ 79 typedef union { 80 uint64_t value; 81 struct { 82 #if defined(_BIG_ENDIAN) 83 uint64_t rsrvd:28; 84 uint64_t parity:4; 85 uint64_t member:32; 86 #else 87 uint64_t member:32; 88 uint64_t parity:4; 89 uint64_t rsrvd:28; 90 #endif 91 } bits; 92 } pfc_vlan_table_t; 93 94 95 /* 96 * Register: PfcVlanCtrl 97 * VLAN Control Register 98 * Description: VLAN control register. Controls VLAN table properties 99 * and implicit VLAN properties for non-VLAN tagged packets. 100 * Fields: 101 * VLAN table parity debug write enable. When set to 1, software 102 * writes the parity bits together with the data during a VLAN 103 * table write. Otherwise, hardware automatically generates the 104 * parity bits from the data. 105 * Set to 1 to indicate the implicit VLAN ID is valid for use in 106 * non-VLAN tagged packets filtering 107 * Implicit VLAN ID for non-VLAN tagged packets 108 */ 109 typedef union { 110 uint64_t value; 111 struct { 112 #if defined(_BIG_ENDIAN) 113 uint64_t rsrvd:50; 114 uint64_t par_en:1; 115 uint64_t valid:1; 116 uint64_t id:12; 117 #else 118 uint64_t id:12; 119 uint64_t valid:1; 120 uint64_t par_en:1; 121 uint64_t rsrvd:50; 122 #endif 123 } bits; 124 } pfc_vlan_ctrl_t; 125 126 127 /* 128 * Register: PfcMacAddr 129 * MAC Address 130 * Description: MAC Address - Contains a station's 48 bit MAC 131 * address. The first register corresponds to MAC address 0, the 132 * second register corresponds to MAC address 1 and so on. For a MAC 133 * address of format aa-bb-cc-dd-ee-ff, addr[47:0] corresponds to 134 * "aabbccddeeff". When used in conjunction with the MAC address 135 * filter mask registers, these registers can be used to construct 136 * either a unicast or multicast address. An address is considered 137 * matched if (DA & ~mask) == (MAC address & ~mask) 138 * Fields: 139 * 48 bits of stations's MAC address 140 */ 141 typedef union { 142 uint64_t value; 143 struct { 144 #if defined(_BIG_ENDIAN) 145 uint64_t rsrvd:16; 146 uint64_t addr:48; 147 #else 148 uint64_t addr:48; 149 uint64_t rsrvd:16; 150 #endif 151 } bits; 152 } pfc_mac_addr_t; 153 154 155 /* 156 * Register: PfcMacAddrMask 157 * MAC Address Filter 158 * Description: MAC Address Filter Mask - Contains the station's 48 159 * bit MAC address filter mask. The first register corresponds to MAC 160 * address 0 filter mask, the second register corresponds to MAC 161 * address 1 filter mask and so on. These filter masks cover MAC 162 * address bits 47:0 in the same order as the address registers 163 * Fields: 164 * 48 bits of stations's MAC address filter mask 165 */ 166 typedef union { 167 uint64_t value; 168 struct { 169 #if defined(_BIG_ENDIAN) 170 uint64_t rsrvd:16; 171 uint64_t mask:48; 172 #else 173 uint64_t mask:48; 174 uint64_t rsrvd:16; 175 #endif 176 } bits; 177 } pfc_mac_addr_mask_t; 178 179 180 /* 181 * Register: PfcHashTable 182 * MAC Multicast Hash Filter 183 * Description: MAC multicast hash table filter. The multicast 184 * destination address is used to perform Ethernet CRC-32 hashing 185 * with seed value 0xffffFfff. Bits 47:40 of the hash result are used 186 * to index one bit of this multicast hash table. If the bit is '1', 187 * the multicast hash matches. 188 * Fields: 189 * 16 bits of 256 bit hash table. First entry contains bits 190 * [15:0], last entry contains bits [255:240] 191 */ 192 typedef union { 193 uint64_t value; 194 struct { 195 #if defined(_BIG_ENDIAN) 196 uint64_t rsrvd:48; 197 uint64_t hash_val:16; 198 #else 199 uint64_t hash_val:16; 200 uint64_t rsrvd:48; 201 #endif 202 } bits; 203 } pfc_hash_table_t; 204 205 206 /* 207 * Register: PfcL2ClassConfig 208 * L2 Class Configuration 209 * Description: Programmable EtherType for class codes 2 and 3. The 210 * first register is class 2, and the second class 3 211 * Fields: 212 * Set to 1 to indicate that the entry is valid for use in 213 * classification 214 * EtherType value 215 */ 216 typedef union { 217 uint64_t value; 218 struct { 219 #if defined(_BIG_ENDIAN) 220 uint64_t rsrvd:47; 221 uint64_t valid:1; 222 uint64_t etype:16; 223 #else 224 uint64_t etype:16; 225 uint64_t valid:1; 226 uint64_t rsrvd:47; 227 #endif 228 } bits; 229 } pfc_l2_class_config_t; 230 231 232 /* 233 * Register: PfcL3ClassConfig 234 * L3 Class Configuration 235 * Description: Configuration for class codes 0x8-0xF. PFC can be set 236 * to discard certain classes of traffic, or to not initiate a TCAM 237 * match for that class 238 * Fields: 239 * Set to 1 to discard all packets of this class code 240 * Set to 1 to indicate that packets of this class should be sent 241 * to the TCAM for perfect match 242 */ 243 typedef union { 244 uint64_t value; 245 struct { 246 #if defined(_BIG_ENDIAN) 247 uint64_t rsrvd:60; 248 uint64_t discard:1; 249 uint64_t tsel:1; 250 uint64_t rsrvd1:2; 251 #else 252 uint64_t rsrvd1:2; 253 uint64_t tsel:1; 254 uint64_t discard:1; 255 uint64_t rsrvd:60; 256 #endif 257 } bits; 258 } pfc_l3_class_config_t; 259 260 261 /* 262 * Register: PfcTcamKey0 263 * TCAM Key 0 264 * Description: TCAM key value. Holds bit 63:0 of the TCAM key 265 * Fields: 266 * bits 63:0 of tcam key 267 */ 268 typedef union { 269 uint64_t value; 270 struct { 271 #if defined(_BIG_ENDIAN) 272 uint64_t key:64; 273 #else 274 uint64_t key:64; 275 #endif 276 } bits; 277 } pfc_tcam_key0_t; 278 279 280 /* 281 * Register: PfcTcamKey1 282 * TCAM Key 1 283 * Description: TCAM key value. Holds bit 99:64 of the TCAM key 284 * Fields: 285 * bits 99:64 of tcam key 286 */ 287 typedef union { 288 uint64_t value; 289 struct { 290 #if defined(_BIG_ENDIAN) 291 uint64_t rsrvd:28; 292 uint64_t key:36; 293 #else 294 uint64_t key:36; 295 uint64_t rsrvd:28; 296 #endif 297 } bits; 298 } pfc_tcam_key1_t; 299 300 301 /* 302 * Register: PfcTcamMask0 303 * TCAM Mask 0 304 * Description: TCAM mask value. Holds bit 63:0 of the TCAM mask 305 * Fields: 306 * bits 63:0 of tcam mask 307 */ 308 typedef union { 309 uint64_t value; 310 struct { 311 #if defined(_BIG_ENDIAN) 312 uint64_t mask:64; 313 #else 314 uint64_t mask:64; 315 #endif 316 } bits; 317 } pfc_tcam_mask0_t; 318 319 320 /* 321 * Register: PfcTcamMask1 322 * TCAM Mask 1 323 * Description: TCAM mask value. Holds bit 99:64 of the TCAM mask 324 * Fields: 325 * bits 99:64 of tcam mask 326 */ 327 typedef union { 328 uint64_t value; 329 struct { 330 #if defined(_BIG_ENDIAN) 331 uint64_t rsrvd:28; 332 uint64_t mask:36; 333 #else 334 uint64_t mask:36; 335 uint64_t rsrvd:28; 336 #endif 337 } bits; 338 } pfc_tcam_mask1_t; 339 340 341 /* 342 * Register: PfcTcamCtrl 343 * TCAM Control 344 * Description: TCAM and TCAM lookup memory access control register. 345 * Controls how TCAM and result lookup table are accessed by blade 346 * CPU. For a TCAM write, the data in the TCAM key and mask registers 347 * will be written to the TCAM. A compare will initiate a TCAM match 348 * with the data stored in the TCAM key register. The match bit is 349 * toggled, and the matching address is reported in the addr field. 350 * For an access to the TCAM result lookup memory, the TCAM 0 key 351 * register is used for the read/write data. 352 * Fields: 353 * TCAM lookup table debug parity bit write enable. When a '1' is 354 * written, software writes the parity bit together with the data 355 * during a TCAM result lookup write. Otherwise, hardware 356 * automatically generates the parity bit from the data. 357 * 3'b000 = TCAM write 3'b001 = reserved 3'b010 = TCAM compare 358 * 3'b011 = reserved 3'b100 = TCAM result lookup write 3'b101 = 359 * TCAM result lookup read 3'b110 = reserved 3'b111 = reserved 360 * Status of read/write/compare operation. When a zero is 361 * written, hardware initiates access. Hardware writes a '1' to 362 * the bit when it completes 363 * Set to 1 if there is a TCAM match for compare command. Zero 364 * otherwise 365 * Address location for access of TCAM or RAM (valid values 366 * 0-42). For a compare, the location of the match is written 367 * here by hardware. 368 */ 369 typedef union { 370 uint64_t value; 371 struct { 372 #if defined(_BIG_ENDIAN) 373 uint64_t rsrvd:45; 374 uint64_t par_en:1; 375 uint64_t cmd:3; 376 uint64_t status:1; 377 uint64_t match:1; 378 uint64_t rsrvd1:5; 379 uint64_t addr:8; 380 #else 381 uint64_t addr:8; 382 uint64_t rsrvd1:5; 383 uint64_t match:1; 384 uint64_t status:1; 385 uint64_t cmd:3; 386 uint64_t par_en:1; 387 uint64_t rsrvd:45; 388 #endif 389 } bits; 390 } pfc_tcam_ctrl_t; 391 392 393 /* 394 * Register: PfcConfig 395 * PFC General Configuration 396 * Description: PFC configuration options that are under the control 397 * of a blade CPU 398 * Fields: 399 * MAC address enable mask. Each bit corresponds to one MAC 400 * adress (lsb = addr0). With 16 MAC addresses, only the lower 16 401 * bits are valid. 402 * default DMA channel number 403 * force TCP/UDP checksum result to always match 404 * Enable for TCP/UDP checksum. If not enabled, the result will 405 * never match. 406 * Enable TCAM matching. If TCAM matching is not enabled, traffic 407 * will be sent to the default DMA channel. 408 * Enable L2 Multicast hash 409 */ 410 typedef union { 411 uint64_t value; 412 struct { 413 #if defined(_BIG_ENDIAN) 414 uint64_t rsrvd:24; 415 uint64_t mac_addr_en:32; 416 uint64_t default_dma:4; 417 uint64_t force_cs_en:1; 418 uint64_t tcp_cs_en:1; 419 uint64_t tcam_en:1; 420 uint64_t l2_hash_en:1; 421 #else 422 uint64_t l2_hash_en:1; 423 uint64_t tcam_en:1; 424 uint64_t tcp_cs_en:1; 425 uint64_t force_cs_en:1; 426 uint64_t default_dma:4; 427 uint64_t mac_addr_en:32; 428 uint64_t rsrvd:24; 429 #endif 430 } bits; 431 } pfc_config_t; 432 433 434 /* 435 * Register: TcpCtrlMask 436 * TCP control bits mask 437 * Description: Mask of TCP control bits to forward onto downstream 438 * blocks The TCP packet's control bits are masked, and then bitwise 439 * OR'd to produce a signal to the Rx DMA. Normally, all bits are 440 * masked off except the TCP SYN bit. The Rx DMA uses this bitwise OR 441 * for statistics. When discard = 1, the packet will be dropped if 442 * the bitwise OR = 1. 443 * Fields: 444 * Drop the packet if bitwise OR of the TCP control bits masked 445 * on = 1 446 * TCP end of data flag 447 * TCP SYN flag 448 * TCP reset flag 449 * TCP push flag 450 * TCP ack flag 451 * TCP urgent flag 452 */ 453 typedef union { 454 uint64_t value; 455 struct { 456 #if defined(_BIG_ENDIAN) 457 uint64_t rsrvd:57; 458 uint64_t discard:1; 459 uint64_t fin:1; 460 uint64_t syn:1; 461 uint64_t rst:1; 462 uint64_t psh:1; 463 uint64_t ack:1; 464 uint64_t urg:1; 465 #else 466 uint64_t urg:1; 467 uint64_t ack:1; 468 uint64_t psh:1; 469 uint64_t rst:1; 470 uint64_t syn:1; 471 uint64_t fin:1; 472 uint64_t discard:1; 473 uint64_t rsrvd:57; 474 #endif 475 } bits; 476 } tcp_ctrl_mask_t; 477 478 479 /* 480 * Register: SrcHashVal 481 * Source hash Seed Value 482 * Hash CRC seed value 483 */ 484 typedef union { 485 uint64_t value; 486 struct { 487 #if defined(_BIG_ENDIAN) 488 uint64_t rsrvd:32; 489 uint64_t seed:32; 490 #else 491 uint64_t seed:32; 492 uint64_t rsrvd:32; 493 #endif 494 } bits; 495 } src_hash_val_t; 496 497 498 /* 499 * Register: PfcIntStatus 500 * PFC Interrupt Status 501 * Description: PFC interrupt status register 502 * Fields: 503 * triggered when packet drop log captured a drop. Part of LDF 0. 504 * Write 1 to clear. 505 * TCAM result lookup table parity error. Part of LDF 0. Write 1 506 * to clear. 507 * VLAN table parity error. Part of LDF 0. Write 1 to clear. 508 */ 509 typedef union { 510 uint64_t value; 511 struct { 512 #if defined(_BIG_ENDIAN) 513 uint64_t rsrvd:61; 514 uint64_t pkt_drop:1; 515 uint64_t tcam_parity_err:1; 516 uint64_t vlan_parity_err:1; 517 #else 518 uint64_t vlan_parity_err:1; 519 uint64_t tcam_parity_err:1; 520 uint64_t pkt_drop:1; 521 uint64_t rsrvd:61; 522 #endif 523 } bits; 524 } pfc_int_status_t; 525 526 527 /* 528 * Register: PfcDbgIntStatus 529 * PFC Debug Interrupt Status 530 * Description: PFC debug interrupt status mirror register. This 531 * debug register triggers the same interrupts as those in the PFC 532 * Interrupt Status register. Interrupts in this mirror register are 533 * subject to the filtering of the PFC Interrupt Mask register. 534 * Fields: 535 * Packet drop. Part of LDF 0. 536 * TCAM result lookup table parity error. Part of LDF 0. 537 * VLAN table parity error. Part of LDF 0. 538 */ 539 typedef union { 540 uint64_t value; 541 struct { 542 #if defined(_BIG_ENDIAN) 543 uint64_t rsrvd:61; 544 uint64_t pkt_drop:1; 545 uint64_t tcam_parity_err:1; 546 uint64_t vlan_parity_err:1; 547 #else 548 uint64_t vlan_parity_err:1; 549 uint64_t tcam_parity_err:1; 550 uint64_t pkt_drop:1; 551 uint64_t rsrvd:61; 552 #endif 553 } bits; 554 } pfc_dbg_int_status_t; 555 556 557 /* 558 * Register: PfcIntMask 559 * PFC Interrupt Mask 560 * Description: PFC interrupt status mask register 561 * Fields: 562 * mask for pktDrop capture; 563 * TCAM result lookup table parity error mask; 564 * VLAN table parity error mask; 565 */ 566 typedef union { 567 uint64_t value; 568 struct { 569 #if defined(_BIG_ENDIAN) 570 uint64_t rsrvd:61; 571 uint64_t pkt_drop_mask:1; 572 uint64_t tcam_parity_err_mask:1; 573 uint64_t vlan_parity_err_mask:1; 574 #else 575 uint64_t vlan_parity_err_mask:1; 576 uint64_t tcam_parity_err_mask:1; 577 uint64_t pkt_drop_mask:1; 578 uint64_t rsrvd:61; 579 #endif 580 } bits; 581 } pfc_int_mask_t; 582 583 584 /* 585 * Register: PfcDropLog 586 * Packet Drop Log 587 * Description: Packet drop log. Log for capturing packet drops. Log 588 * is re-armed when associated interrupt bit is cleared. 589 * Fields: 590 * drop because bitwise OR of the tcp control bits masked on = 1 591 * drop because L2 address did not match 592 * drop because class code indicated drop 593 * drop because TCAM result indicated drop 594 * drop because blade was not a member of VLAN 595 */ 596 typedef union { 597 uint64_t value; 598 struct { 599 #if defined(_BIG_ENDIAN) 600 uint64_t rsrvd:59; 601 uint64_t tcp_ctrl_drop:1; 602 uint64_t l2_addr_drop:1; 603 uint64_t class_code_drop:1; 604 uint64_t tcam_drop:1; 605 uint64_t vlan_drop:1; 606 #else 607 uint64_t vlan_drop:1; 608 uint64_t tcam_drop:1; 609 uint64_t class_code_drop:1; 610 uint64_t l2_addr_drop:1; 611 uint64_t tcp_ctrl_drop:1; 612 uint64_t rsrvd:59; 613 #endif 614 } bits; 615 } pfc_drop_log_t; 616 617 618 /* 619 * Register: PfcDropLogMask 620 * Packet Drop Log Mask 621 * Description: Mask for logging packet drop. If the drop type is 622 * masked off, it will not trigger the drop log to capture the packet 623 * drop 624 * Fields: 625 * mask drop because bitwise OR of the tcp control bits masked on 626 * = 1 627 * mask drop because L2 address did not match 628 * mask drop because class code indicated 629 * mask drop because TCAM result indicated drop 630 * mask drop because blade was not a member of VLAN 631 */ 632 typedef union { 633 uint64_t value; 634 struct { 635 #if defined(_BIG_ENDIAN) 636 uint64_t rsrvd:59; 637 uint64_t tcp_ctrl_drop_mask:1; 638 uint64_t l2_addr_drop_mask:1; 639 uint64_t class_code_drop_mask:1; 640 uint64_t tcam_drop_mask:1; 641 uint64_t vlan_drop_mask:1; 642 #else 643 uint64_t vlan_drop_mask:1; 644 uint64_t tcam_drop_mask:1; 645 uint64_t class_code_drop_mask:1; 646 uint64_t l2_addr_drop_mask:1; 647 uint64_t tcp_ctrl_drop_mask:1; 648 uint64_t rsrvd:59; 649 #endif 650 } bits; 651 } pfc_drop_log_mask_t; 652 653 654 /* 655 * Register: PfcVlanParErrLog 656 * VLAN Parity Error Log 657 * Description: Log of parity errors in VLAN table. 658 * Fields: 659 * address of parity error. Log is cleared when corresponding 660 * interrupt bit is cleared by writing '1'. 661 */ 662 typedef union { 663 uint64_t value; 664 struct { 665 #if defined(_BIG_ENDIAN) 666 uint64_t rsrvd:52; 667 uint64_t addr:12; 668 #else 669 uint64_t addr:12; 670 uint64_t rsrvd:52; 671 #endif 672 } bits; 673 } pfc_vlan_par_err_log_t; 674 675 676 /* 677 * Register: PfcTcamParErrLog 678 * TCAM Parity Error Log 679 * Description: Log of parity errors in TCAM result lookup table. 680 * Fields: 681 * address of parity error. Log is cleared when corresponding 682 * interrupt bit is cleared by writing '1'. 683 */ 684 typedef union { 685 uint64_t value; 686 struct { 687 #if defined(_BIG_ENDIAN) 688 uint64_t rsrvd:56; 689 uint64_t addr:8; 690 #else 691 uint64_t addr:8; 692 uint64_t rsrvd:56; 693 #endif 694 } bits; 695 } pfc_tcam_par_err_log_t; 696 697 698 /* 699 * Register: PfcBadCsCounter 700 * PFC Bad Checksum Counter 701 * Description: Count number of bad TCP/UDP checksum. Only counted if 702 * L2 adddress matched 703 * Fields: 704 * count of number of bad TCP/UDP checksums received. Clear on 705 * read 706 */ 707 typedef union { 708 uint64_t value; 709 struct { 710 #if defined(_BIG_ENDIAN) 711 uint64_t rsrvd:32; 712 uint64_t bad_cs_count:32; 713 #else 714 uint64_t bad_cs_count:32; 715 uint64_t rsrvd:32; 716 #endif 717 } bits; 718 } pfc_bad_cs_counter_t; 719 720 721 /* 722 * Register: PfcDropCounter 723 * PFC Drop Counter 724 * Description: Count number of packets dropped due to VLAN 725 * membership, class code, TCP control bits, or TCAM results Only 726 * counted if L2 address matched. 727 * Fields: 728 * Count of number of packets dropped due to VLAN, TCAM results. 729 * Clear on read 730 */ 731 typedef union { 732 uint64_t value; 733 struct { 734 #if defined(_BIG_ENDIAN) 735 uint64_t rsrvd:32; 736 uint64_t drop_count:32; 737 #else 738 uint64_t drop_count:32; 739 uint64_t rsrvd:32; 740 #endif 741 } bits; 742 } pfc_drop_counter_t; 743 744 745 /* 746 * Register: PfcAutoInit 747 * PFC Auto Init 748 * Description: PFC Auto Initialization. Writing to this register 749 * triggers the auto initialization of the blade's TCAM entries with 750 * 100 bits of '0' for both key and mask. TCAM lookup is disabled 751 * during auto initialization. 752 * Fields: 753 * TCAM auto initialization status. 0=busy, 1=done. 754 */ 755 typedef union { 756 uint64_t value; 757 struct { 758 #if defined(_BIG_ENDIAN) 759 uint64_t rsrvd:63; 760 uint64_t auto_init_status:1; 761 #else 762 uint64_t auto_init_status:1; 763 uint64_t rsrvd:63; 764 #endif 765 } bits; 766 } pfc_auto_init_t; 767 768 769 #ifdef __cplusplus 770 } 771 #endif 772 773 #endif /* _HXGE_PFC_HW_H */ 774