1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _HXGE_PFC_HW_H 27 #define _HXGE_PFC_HW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #define PFC_BASE_ADDR 0X0200000 34 35 #define PFC_VLAN_TABLE (PFC_BASE_ADDR + 0x0) 36 #define PFC_VLAN_CTRL (PFC_BASE_ADDR + 0x9000) 37 #define PFC_MAC_ADDR (PFC_BASE_ADDR + 0x10000) 38 #define PFC_MAC_ADDR_MASK (PFC_BASE_ADDR + 0x10080) 39 #define PFC_HASH_TABLE (PFC_BASE_ADDR + 0x10100) 40 #define PFC_L2_CLASS_CONFIG (PFC_BASE_ADDR + 0x20000) 41 #define PFC_L3_CLASS_CONFIG (PFC_BASE_ADDR + 0x20030) 42 #define PFC_TCAM_KEY0 (PFC_BASE_ADDR + 0x20090) 43 #define PFC_TCAM_KEY1 (PFC_BASE_ADDR + 0x20098) 44 #define PFC_TCAM_MASK0 (PFC_BASE_ADDR + 0x200B0) 45 #define PFC_TCAM_MASK1 (PFC_BASE_ADDR + 0x200B8) 46 #define PFC_TCAM_CTRL (PFC_BASE_ADDR + 0x200D0) 47 #define PFC_CONFIG (PFC_BASE_ADDR + 0x20100) 48 #define TCP_CTRL_MASK (PFC_BASE_ADDR + 0x20108) 49 #define SRC_HASH_VAL (PFC_BASE_ADDR + 0x20110) 50 #define PFC_INT_STATUS (PFC_BASE_ADDR + 0x30000) 51 #define PFC_DBG_INT_STATUS (PFC_BASE_ADDR + 0x30008) 52 #define PFC_INT_MASK (PFC_BASE_ADDR + 0x30100) 53 #define PFC_DROP_LOG (PFC_BASE_ADDR + 0x30200) 54 #define PFC_DROP_LOG_MASK (PFC_BASE_ADDR + 0x30208) 55 #define PFC_VLAN_PAR_ERR_LOG (PFC_BASE_ADDR + 0x30210) 56 #define PFC_TCAM_PAR_ERR_LOG (PFC_BASE_ADDR + 0x30218) 57 #define PFC_BAD_CS_COUNTER (PFC_BASE_ADDR + 0x30220) 58 #define PFC_DROP_COUNTER (PFC_BASE_ADDR + 0x30228) 59 #define PFC_AUTO_INIT (PFC_BASE_ADDR + 0x30300) 60 61 62 /* 63 * Register: PfcVlanTable 64 * VLAN Table Registers 65 * Description: VLAN membership table. CPU programs in the VLANs that 66 * it wants to belong to. A blade may be a member of multiple VLANs. 67 * Bits [31:0] of the first entry corresponds to vlan members [31:0], 68 * bits [31:0] of the second entry corresponds to vlan members 69 * [63:32] and so on. 70 * Fields: 71 * Odd parities of member[31:24], member[23:16], member[17:8], 72 * member[7:0]. These parity bits are ignored when parEn in the 73 * VLAN Control register is set to '0'. 74 * Set to 1 to indicate that blade is a member of the VLAN IDs 75 * (32 to 0) * entry number 76 */ 77 typedef union { 78 uint64_t value; 79 struct { 80 #if defined(_BIG_ENDIAN) 81 uint32_t rsrvd:28; 82 uint32_t parity:4; 83 uint32_t member:32; 84 #else 85 uint32_t member:32; 86 uint32_t parity:4; 87 uint32_t rsrvd:28; 88 #endif 89 } bits; 90 } pfc_vlan_table_t; 91 92 93 /* 94 * Register: PfcVlanCtrl 95 * VLAN Control Register 96 * Description: VLAN control register. Controls VLAN table properties 97 * and implicit VLAN properties for non-VLAN tagged packets. 98 * Fields: 99 * VLAN table parity debug write enable. When set to 1, software 100 * writes the parity bits together with the data during a VLAN 101 * table write. Otherwise, hardware automatically generates the 102 * parity bits from the data. 103 * Set to 1 to indicate the implicit VLAN ID is valid for use in 104 * non-VLAN tagged packets filtering 105 * Implicit VLAN ID for non-VLAN tagged packets 106 */ 107 typedef union { 108 uint64_t value; 109 struct { 110 #if defined(_BIG_ENDIAN) 111 uint32_t rsrvd:32; 112 uint32_t rsrvd_l:18; 113 uint32_t par_en:1; 114 uint32_t valid:1; 115 uint32_t id:12; 116 #else 117 uint32_t id:12; 118 uint32_t valid:1; 119 uint32_t par_en:1; 120 uint32_t rsrvd_l:18; 121 uint32_t rsrvd:32; 122 #endif 123 } bits; 124 } pfc_vlan_ctrl_t; 125 126 127 /* 128 * Register: PfcMacAddr 129 * MAC Address 130 * Description: MAC Address - Contains a station's 48 bit MAC 131 * address. The first register corresponds to MAC address 0, the 132 * second register corresponds to MAC address 1 and so on. For a MAC 133 * address of format aa-bb-cc-dd-ee-ff, addr[47:0] corresponds to 134 * "aabbccddeeff". When used in conjunction with the MAC address 135 * filter mask registers, these registers can be used to construct 136 * either a unicast or multicast address. An address is considered 137 * matched if (DA & ~mask) == (MAC address & ~mask) 138 * Fields: 139 * 48 bits of stations's MAC address 140 */ 141 typedef union { 142 uint64_t value; 143 struct { 144 #if defined(_BIG_ENDIAN) 145 uint32_t rsrvd:16; 146 uint32_t addr:16; 147 uint32_t addr_l:32; 148 #else 149 uint32_t addr_l:32; 150 uint32_t addr:16; 151 uint32_t rsrvd:16; 152 #endif 153 } bits; 154 } pfc_mac_addr_t; 155 156 157 /* 158 * Register: PfcMacAddrMask 159 * MAC Address Filter 160 * Description: MAC Address Filter Mask - Contains the station's 48 161 * bit MAC address filter mask. The first register corresponds to MAC 162 * address 0 filter mask, the second register corresponds to MAC 163 * address 1 filter mask and so on. These filter masks cover MAC 164 * address bits 47:0 in the same order as the address registers 165 * Fields: 166 * 48 bits of stations's MAC address filter mask 167 */ 168 typedef union { 169 uint64_t value; 170 struct { 171 #if defined(_BIG_ENDIAN) 172 uint32_t rsrvd:16; 173 uint32_t mask:16; 174 uint32_t mask_l:32; 175 #else 176 uint32_t mask_l:32; 177 uint32_t mask:16; 178 uint32_t rsrvd:16; 179 #endif 180 } bits; 181 } pfc_mac_addr_mask_t; 182 183 184 /* 185 * Register: PfcHashTable 186 * MAC Multicast Hash Filter 187 * Description: MAC multicast hash table filter. The multicast 188 * destination address is used to perform Ethernet CRC-32 hashing 189 * with seed value 0xffffFfff. Bits 47:40 of the hash result are used 190 * to index one bit of this multicast hash table. If the bit is '1', 191 * the multicast hash matches. 192 * Fields: 193 * 16 bits of 256 bit hash table. First entry contains bits 194 * [15:0], last entry contains bits [255:240] 195 */ 196 typedef union { 197 uint64_t value; 198 struct { 199 #if defined(_BIG_ENDIAN) 200 uint32_t rsrvd:32; 201 uint32_t rsrvd_l:16; 202 uint32_t hash_val:16; 203 #else 204 uint32_t hash_val:16; 205 uint32_t rsrvd_l:16; 206 uint32_t rsrvd:32; 207 #endif 208 } bits; 209 } pfc_hash_table_t; 210 211 212 /* 213 * Register: PfcL2ClassConfig 214 * L2 Class Configuration 215 * Description: Programmable EtherType for class codes 2 and 3. The 216 * first register is class 2, and the second class 3 217 * Fields: 218 * Set to 1 to indicate that the entry is valid for use in 219 * classification 220 * EtherType value 221 */ 222 typedef union { 223 uint64_t value; 224 struct { 225 #if defined(_BIG_ENDIAN) 226 uint32_t rsrvd:32; 227 uint32_t rsrvd_l:15; 228 uint32_t valid:1; 229 uint32_t etype:16; 230 #else 231 uint32_t etype:16; 232 uint32_t valid:1; 233 uint32_t rsrvd_l:15; 234 uint32_t rsrvd:32; 235 #endif 236 } bits; 237 } pfc_l2_class_config_t; 238 239 240 /* 241 * Register: PfcL3ClassConfig 242 * L3 Class Configuration 243 * Description: Configuration for class codes 0x8-0xF. PFC can be set 244 * to discard certain classes of traffic, or to not initiate a TCAM 245 * match for that class 246 * Fields: 247 * Set to 1 to discard all packets of this class code 248 * Set to 1 to indicate that packets of this class should be sent 249 * to the TCAM for perfect match 250 */ 251 typedef union { 252 uint64_t value; 253 struct { 254 #if defined(_BIG_ENDIAN) 255 uint32_t rsrvd:32; 256 uint32_t rsrvd_l:28; 257 uint32_t discard:1; 258 uint32_t tsel:1; 259 uint32_t rsrvd1:2; 260 #else 261 uint32_t rsrvd1:2; 262 uint32_t tsel:1; 263 uint32_t discard:1; 264 uint32_t rsrvd_l:28; 265 uint32_t rsrvd:32; 266 #endif 267 } bits; 268 } pfc_l3_class_config_t; 269 270 271 /* 272 * Register: PfcTcamKey0 273 * TCAM Key 0 274 * Description: TCAM key value. Holds bit 63:0 of the TCAM key 275 * Fields: 276 * bits 63:0 of tcam key 277 */ 278 typedef union { 279 uint64_t value; 280 struct { 281 #if defined(_BIG_ENDIAN) 282 uint32_t key:32; 283 uint32_t key_l:32; 284 #else 285 uint32_t key_l:32; 286 uint32_t key:32; 287 #endif 288 } bits; 289 } pfc_tcam_key0_t; 290 291 292 /* 293 * Register: PfcTcamKey1 294 * TCAM Key 1 295 * Description: TCAM key value. Holds bit 99:64 of the TCAM key 296 * Fields: 297 * bits 99:64 of tcam key 298 */ 299 typedef union { 300 uint64_t value; 301 struct { 302 #if defined(_BIG_ENDIAN) 303 uint32_t rsrvd:28; 304 uint32_t key:4; 305 uint32_t key_l:32; 306 #else 307 uint32_t key_l:32; 308 uint32_t key:4; 309 uint32_t rsrvd:28; 310 #endif 311 } bits; 312 } pfc_tcam_key1_t; 313 314 315 /* 316 * Register: PfcTcamMask0 317 * TCAM Mask 0 318 * Description: TCAM mask value. Holds bit 63:0 of the TCAM mask 319 * Fields: 320 * bits 63:0 of tcam mask 321 */ 322 typedef union { 323 uint64_t value; 324 struct { 325 #if defined(_BIG_ENDIAN) 326 uint32_t mask:32; 327 uint32_t mask_l:32; 328 #else 329 uint32_t mask_l:32; 330 uint32_t mask:32; 331 #endif 332 } bits; 333 } pfc_tcam_mask0_t; 334 335 336 /* 337 * Register: PfcTcamMask1 338 * TCAM Mask 1 339 * Description: TCAM mask value. Holds bit 99:64 of the TCAM mask 340 * Fields: 341 * bits 99:64 of tcam mask 342 */ 343 typedef union { 344 uint64_t value; 345 struct { 346 #if defined(_BIG_ENDIAN) 347 uint32_t rsrvd:28; 348 uint32_t mask:4; 349 uint32_t mask_l:32; 350 #else 351 uint32_t mask_l:32; 352 uint32_t mask:4; 353 uint32_t rsrvd:28; 354 #endif 355 } bits; 356 } pfc_tcam_mask1_t; 357 358 359 /* 360 * Register: PfcTcamCtrl 361 * TCAM Control 362 * Description: TCAM and TCAM lookup memory access control register. 363 * Controls how TCAM and result lookup table are accessed by blade 364 * CPU. For a TCAM write, the data in the TCAM key and mask registers 365 * will be written to the TCAM. A compare will initiate a TCAM match 366 * with the data stored in the TCAM key register. The match bit is 367 * toggled, and the matching address is reported in the addr field. 368 * For an access to the TCAM result lookup memory, the TCAM 0 key 369 * register is used for the read/write data. 370 * Fields: 371 * TCAM lookup table debug parity bit write enable. When a '1' is 372 * written, software writes the parity bit together with the data 373 * during a TCAM result lookup write. Otherwise, hardware 374 * automatically generates the parity bit from the data. 375 * 3'b000 = TCAM write 3'b001 = reserved 3'b010 = TCAM compare 376 * 3'b011 = reserved 3'b100 = TCAM result lookup write 3'b101 = 377 * TCAM result lookup read 3'b110 = reserved 3'b111 = reserved 378 * Status of read/write/compare operation. When a zero is 379 * written, hardware initiates access. Hardware writes a '1' to 380 * the bit when it completes 381 * Set to 1 if there is a TCAM match for compare command. Zero 382 * otherwise 383 * Address location for access of TCAM or RAM (valid values 384 * 0-42). For a compare, the location of the match is written 385 * here by hardware. 386 */ 387 typedef union { 388 uint64_t value; 389 struct { 390 #if defined(_BIG_ENDIAN) 391 uint32_t rsrvd:32; 392 uint32_t rsrvd_l:13; 393 uint32_t par_en:1; 394 uint32_t cmd:3; 395 uint32_t status:1; 396 uint32_t match:1; 397 uint32_t rsrvd1:5; 398 uint32_t addr:8; 399 #else 400 uint32_t addr:8; 401 uint32_t rsrvd1:5; 402 uint32_t match:1; 403 uint32_t status:1; 404 uint32_t cmd:3; 405 uint32_t par_en:1; 406 uint32_t rsrvd_l:13; 407 uint32_t rsrvd:32; 408 #endif 409 } bits; 410 } pfc_tcam_ctrl_t; 411 412 413 /* 414 * Register: PfcConfig 415 * PFC General Configuration 416 * Description: PFC configuration options that are under the control 417 * of a blade CPU 418 * Fields: 419 * MAC address enable mask. Each bit corresponds to one MAC 420 * adress (lsb = addr0). With 16 MAC addresses, only the lower 16 421 * bits are valid. 422 * default DMA channel number 423 * force TCP/UDP checksum result to always match 424 * Enable for TCP/UDP checksum. If not enabled, the result will 425 * never match. 426 * Enable TCAM matching. If TCAM matching is not enabled, traffic 427 * will be sent to the default DMA channel. 428 * Enable L2 Multicast hash 429 */ 430 typedef union { 431 uint64_t value; 432 struct { 433 #if defined(_BIG_ENDIAN) 434 uint32_t rsrvd:24; 435 uint32_t mac_addr_en:8; 436 uint32_t mac_addr_en_l:24; 437 uint32_t default_dma:4; 438 uint32_t force_cs_en:1; 439 uint32_t tcp_cs_en:1; 440 uint32_t tcam_en:1; 441 uint32_t l2_hash_en:1; 442 #else 443 uint32_t l2_hash_en:1; 444 uint32_t tcam_en:1; 445 uint32_t tcp_cs_en:1; 446 uint32_t force_cs_en:1; 447 uint32_t default_dma:4; 448 uint32_t mac_addr_en_l:24; 449 uint32_t mac_addr_en:8; 450 uint32_t rsrvd:24; 451 #endif 452 } bits; 453 } pfc_config_t; 454 455 456 /* 457 * Register: TcpCtrlMask 458 * TCP control bits mask 459 * Description: Mask of TCP control bits to forward onto downstream 460 * blocks The TCP packet's control bits are masked, and then bitwise 461 * OR'd to produce a signal to the Rx DMA. Normally, all bits are 462 * masked off except the TCP SYN bit. The Rx DMA uses this bitwise OR 463 * for statistics. When discard = 1, the packet will be dropped if 464 * the bitwise OR = 1. 465 * Fields: 466 * Drop the packet if bitwise OR of the TCP control bits masked 467 * on = 1 468 * TCP end of data flag 469 * TCP SYN flag 470 * TCP reset flag 471 * TCP push flag 472 * TCP ack flag 473 * TCP urgent flag 474 */ 475 typedef union { 476 uint64_t value; 477 struct { 478 #if defined(_BIG_ENDIAN) 479 uint32_t rsrvd:32; 480 uint32_t rsrvd_l:25; 481 uint32_t discard:1; 482 uint32_t fin:1; 483 uint32_t syn:1; 484 uint32_t rst:1; 485 uint32_t psh:1; 486 uint32_t ack:1; 487 uint32_t urg:1; 488 #else 489 uint32_t urg:1; 490 uint32_t ack:1; 491 uint32_t psh:1; 492 uint32_t rst:1; 493 uint32_t syn:1; 494 uint32_t fin:1; 495 uint32_t discard:1; 496 uint32_t rsrvd_l:25; 497 uint32_t rsrvd:32; 498 #endif 499 } bits; 500 } tcp_ctrl_mask_t; 501 502 503 /* 504 * Register: SrcHashVal 505 * Source hash Seed Value 506 * Hash CRC seed value 507 */ 508 typedef union { 509 uint64_t value; 510 struct { 511 #if defined(_BIG_ENDIAN) 512 uint32_t rsrvd:32; 513 uint32_t seed:32; 514 #else 515 uint32_t seed:32; 516 uint32_t rsrvd:32; 517 #endif 518 } bits; 519 } src_hash_val_t; 520 521 522 /* 523 * Register: PfcIntStatus 524 * PFC Interrupt Status 525 * Description: PFC interrupt status register 526 * Fields: 527 * triggered when packet drop log captured a drop. Part of LDF 0. 528 * Write 1 to clear. 529 * TCAM result lookup table parity error. Part of LDF 0. Write 1 530 * to clear. 531 * VLAN table parity error. Part of LDF 0. Write 1 to clear. 532 */ 533 typedef union { 534 uint64_t value; 535 struct { 536 #if defined(_BIG_ENDIAN) 537 uint32_t rsrvd:32; 538 uint32_t rsrvd_l:29; 539 uint32_t pkt_drop:1; 540 uint32_t tcam_parity_err:1; 541 uint32_t vlan_parity_err:1; 542 #else 543 uint32_t vlan_parity_err:1; 544 uint32_t tcam_parity_err:1; 545 uint32_t pkt_drop:1; 546 uint32_t rsrvd_l:29; 547 uint32_t rsrvd:32; 548 #endif 549 } bits; 550 } pfc_int_status_t; 551 552 553 /* 554 * Register: PfcDbgIntStatus 555 * PFC Debug Interrupt Status 556 * Description: PFC debug interrupt status mirror register. This 557 * debug register triggers the same interrupts as those in the PFC 558 * Interrupt Status register. Interrupts in this mirror register are 559 * subject to the filtering of the PFC Interrupt Mask register. 560 * Fields: 561 * Packet drop. Part of LDF 0. 562 * TCAM result lookup table parity error. Part of LDF 0. 563 * VLAN table parity error. Part of LDF 0. 564 */ 565 typedef union { 566 uint64_t value; 567 struct { 568 #if defined(_BIG_ENDIAN) 569 uint32_t rsrvd:32; 570 uint32_t rsrvd_l:29; 571 uint32_t pkt_drop:1; 572 uint32_t tcam_parity_err:1; 573 uint32_t vlan_parity_err:1; 574 #else 575 uint32_t vlan_parity_err:1; 576 uint32_t tcam_parity_err:1; 577 uint32_t pkt_drop:1; 578 uint32_t rsrvd_l:29; 579 uint32_t rsrvd:32; 580 #endif 581 } bits; 582 } pfc_dbg_int_status_t; 583 584 585 /* 586 * Register: PfcIntMask 587 * PFC Interrupt Mask 588 * Description: PFC interrupt status mask register 589 * Fields: 590 * mask for pktDrop capture; 591 * TCAM result lookup table parity error mask; 592 * VLAN table parity error mask; 593 */ 594 typedef union { 595 uint64_t value; 596 struct { 597 #if defined(_BIG_ENDIAN) 598 uint32_t rsrvd:32; 599 uint32_t rsrvd_l:29; 600 uint32_t pkt_drop_mask:1; 601 uint32_t tcam_parity_err_mask:1; 602 uint32_t vlan_parity_err_mask:1; 603 #else 604 uint32_t vlan_parity_err_mask:1; 605 uint32_t tcam_parity_err_mask:1; 606 uint32_t pkt_drop_mask:1; 607 uint32_t rsrvd_l:29; 608 uint32_t rsrvd:32; 609 #endif 610 } bits; 611 } pfc_int_mask_t; 612 613 614 /* 615 * Register: PfcDropLog 616 * Packet Drop Log 617 * Description: Packet drop log. Log for capturing packet drops. Log 618 * is re-armed when associated interrupt bit is cleared. 619 * Fields: 620 * drop because bitwise OR of the tcp control bits masked on = 1 621 * drop because L2 address did not match 622 * drop because class code indicated drop 623 * drop because TCAM result indicated drop 624 * drop because blade was not a member of VLAN 625 */ 626 typedef union { 627 uint64_t value; 628 struct { 629 #if defined(_BIG_ENDIAN) 630 uint32_t rsrvd:32; 631 uint32_t rsrvd_l:27; 632 uint32_t tcp_ctrl_drop:1; 633 uint32_t l2_addr_drop:1; 634 uint32_t class_code_drop:1; 635 uint32_t tcam_drop:1; 636 uint32_t vlan_drop:1; 637 #else 638 uint32_t vlan_drop:1; 639 uint32_t tcam_drop:1; 640 uint32_t class_code_drop:1; 641 uint32_t l2_addr_drop:1; 642 uint32_t tcp_ctrl_drop:1; 643 uint32_t rsrvd_l:27; 644 uint32_t rsrvd:32; 645 #endif 646 } bits; 647 } pfc_drop_log_t; 648 649 650 /* 651 * Register: PfcDropLogMask 652 * Packet Drop Log Mask 653 * Description: Mask for logging packet drop. If the drop type is 654 * masked off, it will not trigger the drop log to capture the packet 655 * drop 656 * Fields: 657 * mask drop because bitwise OR of the tcp control bits masked on 658 * = 1 659 * mask drop because L2 address did not match 660 * mask drop because class code indicated 661 * mask drop because TCAM result indicated drop 662 * mask drop because blade was not a member of VLAN 663 */ 664 typedef union { 665 uint64_t value; 666 struct { 667 #if defined(_BIG_ENDIAN) 668 uint32_t rsrvd:32; 669 uint32_t rsrvd_l:27; 670 uint32_t tcp_ctrl_drop_mask:1; 671 uint32_t l2_addr_drop_mask:1; 672 uint32_t class_code_drop_mask:1; 673 uint32_t tcam_drop_mask:1; 674 uint32_t vlan_drop_mask:1; 675 #else 676 uint32_t vlan_drop_mask:1; 677 uint32_t tcam_drop_mask:1; 678 uint32_t class_code_drop_mask:1; 679 uint32_t l2_addr_drop_mask:1; 680 uint32_t tcp_ctrl_drop_mask:1; 681 uint32_t rsrvd_l:27; 682 uint32_t rsrvd:32; 683 #endif 684 } bits; 685 } pfc_drop_log_mask_t; 686 687 688 /* 689 * Register: PfcVlanParErrLog 690 * VLAN Parity Error Log 691 * Description: Log of parity errors in VLAN table. 692 * Fields: 693 * address of parity error. Log is cleared when corresponding 694 * interrupt bit is cleared by writing '1'. 695 */ 696 typedef union { 697 uint64_t value; 698 struct { 699 #if defined(_BIG_ENDIAN) 700 uint32_t rsrvd:32; 701 uint32_t rsrvd_l:20; 702 uint32_t addr:12; 703 #else 704 uint32_t addr:12; 705 uint32_t rsrvd_l:20; 706 uint32_t rsrvd:32; 707 #endif 708 } bits; 709 } pfc_vlan_par_err_log_t; 710 711 712 /* 713 * Register: PfcTcamParErrLog 714 * TCAM Parity Error Log 715 * Description: Log of parity errors in TCAM result lookup table. 716 * Fields: 717 * address of parity error. Log is cleared when corresponding 718 * interrupt bit is cleared by writing '1'. 719 */ 720 typedef union { 721 uint64_t value; 722 struct { 723 #if defined(_BIG_ENDIAN) 724 uint32_t rsrvd:32; 725 uint32_t rsrvd_l:24; 726 uint32_t addr:8; 727 #else 728 uint32_t addr:8; 729 uint32_t rsrvd_l:24; 730 uint32_t rsrvd:32; 731 #endif 732 } bits; 733 } pfc_tcam_par_err_log_t; 734 735 736 /* 737 * Register: PfcBadCsCounter 738 * PFC Bad Checksum Counter 739 * Description: Count number of bad TCP/UDP checksum. Only counted if 740 * L2 adddress matched 741 * Fields: 742 * count of number of bad TCP/UDP checksums received. Clear on 743 * read 744 */ 745 typedef union { 746 uint64_t value; 747 struct { 748 #if defined(_BIG_ENDIAN) 749 uint32_t rsrvd:32; 750 uint32_t bad_cs_count:32; 751 #else 752 uint32_t bad_cs_count:32; 753 uint32_t rsrvd:32; 754 #endif 755 } bits; 756 } pfc_bad_cs_counter_t; 757 758 759 /* 760 * Register: PfcDropCounter 761 * PFC Drop Counter 762 * Description: Count number of packets dropped due to VLAN 763 * membership, class code, TCP control bits, or TCAM results Only 764 * counted if L2 address matched. 765 * Fields: 766 * Count of number of packets dropped due to VLAN, TCAM results. 767 * Clear on read 768 */ 769 typedef union { 770 uint64_t value; 771 struct { 772 #if defined(_BIG_ENDIAN) 773 uint32_t rsrvd:32; 774 uint32_t drop_count:32; 775 #else 776 uint32_t drop_count:32; 777 uint32_t rsrvd:32; 778 #endif 779 } bits; 780 } pfc_drop_counter_t; 781 782 783 /* 784 * Register: PfcAutoInit 785 * PFC Auto Init 786 * Description: PFC Auto Initialization. Writing to this register 787 * triggers the auto initialization of the blade's TCAM entries with 788 * 100 bits of '0' for both key and mask. TCAM lookup is disabled 789 * during auto initialization. 790 * Fields: 791 * TCAM auto initialization status. 0=busy, 1=done. 792 */ 793 typedef union { 794 uint64_t value; 795 struct { 796 #if defined(_BIG_ENDIAN) 797 uint32_t rsrvd:32; 798 uint32_t rsrvd_l:31; 799 uint32_t auto_init_status:1; 800 #else 801 uint32_t auto_init_status:1; 802 uint32_t rsrvd_l:31; 803 uint32_t rsrvd:32; 804 #endif 805 } bits; 806 } pfc_auto_init_t; 807 808 809 #ifdef __cplusplus 810 } 811 #endif 812 813 #endif /* _HXGE_PFC_HW_H */ 814