13dec9fcdSqs148142 /* 23dec9fcdSqs148142 * CDDL HEADER START 33dec9fcdSqs148142 * 43dec9fcdSqs148142 * The contents of this file are subject to the terms of the 53dec9fcdSqs148142 * Common Development and Distribution License (the "License"). 63dec9fcdSqs148142 * You may not use this file except in compliance with the License. 73dec9fcdSqs148142 * 83dec9fcdSqs148142 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 93dec9fcdSqs148142 * or http://www.opensolaris.org/os/licensing. 103dec9fcdSqs148142 * See the License for the specific language governing permissions 113dec9fcdSqs148142 * and limitations under the License. 123dec9fcdSqs148142 * 133dec9fcdSqs148142 * When distributing Covered Code, include this CDDL HEADER in each 143dec9fcdSqs148142 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 153dec9fcdSqs148142 * If applicable, add the following below this CDDL HEADER, with the 163dec9fcdSqs148142 * fields enclosed by brackets "[]" replaced with your own identifying 173dec9fcdSqs148142 * information: Portions Copyright [yyyy] [name of copyright owner] 183dec9fcdSqs148142 * 193dec9fcdSqs148142 * CDDL HEADER END 203dec9fcdSqs148142 */ 213dec9fcdSqs148142 /* 223dec9fcdSqs148142 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 233dec9fcdSqs148142 * Use is subject to license terms. 243dec9fcdSqs148142 */ 253dec9fcdSqs148142 263dec9fcdSqs148142 #ifndef _HXGE_PFC_HW_H 273dec9fcdSqs148142 #define _HXGE_PFC_HW_H 283dec9fcdSqs148142 293dec9fcdSqs148142 #ifdef __cplusplus 303dec9fcdSqs148142 extern "C" { 313dec9fcdSqs148142 #endif 323dec9fcdSqs148142 333dec9fcdSqs148142 #define PFC_BASE_ADDR 0X0200000 343dec9fcdSqs148142 353dec9fcdSqs148142 #define PFC_VLAN_TABLE (PFC_BASE_ADDR + 0x0) 363dec9fcdSqs148142 #define PFC_VLAN_CTRL (PFC_BASE_ADDR + 0x9000) 373dec9fcdSqs148142 #define PFC_MAC_ADDR (PFC_BASE_ADDR + 0x10000) 383dec9fcdSqs148142 #define PFC_MAC_ADDR_MASK (PFC_BASE_ADDR + 0x10080) 393dec9fcdSqs148142 #define PFC_HASH_TABLE (PFC_BASE_ADDR + 0x10100) 403dec9fcdSqs148142 #define PFC_L2_CLASS_CONFIG (PFC_BASE_ADDR + 0x20000) 413dec9fcdSqs148142 #define PFC_L3_CLASS_CONFIG (PFC_BASE_ADDR + 0x20030) 423dec9fcdSqs148142 #define PFC_TCAM_KEY0 (PFC_BASE_ADDR + 0x20090) 433dec9fcdSqs148142 #define PFC_TCAM_KEY1 (PFC_BASE_ADDR + 0x20098) 443dec9fcdSqs148142 #define PFC_TCAM_MASK0 (PFC_BASE_ADDR + 0x200B0) 453dec9fcdSqs148142 #define PFC_TCAM_MASK1 (PFC_BASE_ADDR + 0x200B8) 463dec9fcdSqs148142 #define PFC_TCAM_CTRL (PFC_BASE_ADDR + 0x200D0) 473dec9fcdSqs148142 #define PFC_CONFIG (PFC_BASE_ADDR + 0x20100) 483dec9fcdSqs148142 #define TCP_CTRL_MASK (PFC_BASE_ADDR + 0x20108) 493dec9fcdSqs148142 #define SRC_HASH_VAL (PFC_BASE_ADDR + 0x20110) 503dec9fcdSqs148142 #define PFC_INT_STATUS (PFC_BASE_ADDR + 0x30000) 513dec9fcdSqs148142 #define PFC_DBG_INT_STATUS (PFC_BASE_ADDR + 0x30008) 523dec9fcdSqs148142 #define PFC_INT_MASK (PFC_BASE_ADDR + 0x30100) 533dec9fcdSqs148142 #define PFC_DROP_LOG (PFC_BASE_ADDR + 0x30200) 543dec9fcdSqs148142 #define PFC_DROP_LOG_MASK (PFC_BASE_ADDR + 0x30208) 553dec9fcdSqs148142 #define PFC_VLAN_PAR_ERR_LOG (PFC_BASE_ADDR + 0x30210) 563dec9fcdSqs148142 #define PFC_TCAM_PAR_ERR_LOG (PFC_BASE_ADDR + 0x30218) 573dec9fcdSqs148142 #define PFC_BAD_CS_COUNTER (PFC_BASE_ADDR + 0x30220) 583dec9fcdSqs148142 #define PFC_DROP_COUNTER (PFC_BASE_ADDR + 0x30228) 593dec9fcdSqs148142 #define PFC_AUTO_INIT (PFC_BASE_ADDR + 0x30300) 603dec9fcdSqs148142 613dec9fcdSqs148142 623dec9fcdSqs148142 /* 633dec9fcdSqs148142 * Register: PfcVlanTable 643dec9fcdSqs148142 * VLAN Table Registers 653dec9fcdSqs148142 * Description: VLAN membership table. CPU programs in the VLANs that 663dec9fcdSqs148142 * it wants to belong to. A blade may be a member of multiple VLANs. 673dec9fcdSqs148142 * Bits [31:0] of the first entry corresponds to vlan members [31:0], 683dec9fcdSqs148142 * bits [31:0] of the second entry corresponds to vlan members 693dec9fcdSqs148142 * [63:32] and so on. 703dec9fcdSqs148142 * Fields: 713dec9fcdSqs148142 * Odd parities of member[31:24], member[23:16], member[17:8], 723dec9fcdSqs148142 * member[7:0]. These parity bits are ignored when parEn in the 733dec9fcdSqs148142 * VLAN Control register is set to '0'. 743dec9fcdSqs148142 * Set to 1 to indicate that blade is a member of the VLAN IDs 753dec9fcdSqs148142 * (32 to 0) * entry number 763dec9fcdSqs148142 */ 773dec9fcdSqs148142 typedef union { 783dec9fcdSqs148142 uint64_t value; 793dec9fcdSqs148142 struct { 803dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 81*fe930412Sqs148142 uint32_t rsrvd:28; 82*fe930412Sqs148142 uint32_t parity:4; 83*fe930412Sqs148142 uint32_t member:32; 843dec9fcdSqs148142 #else 85*fe930412Sqs148142 uint32_t member:32; 86*fe930412Sqs148142 uint32_t parity:4; 87*fe930412Sqs148142 uint32_t rsrvd:28; 883dec9fcdSqs148142 #endif 893dec9fcdSqs148142 } bits; 903dec9fcdSqs148142 } pfc_vlan_table_t; 913dec9fcdSqs148142 923dec9fcdSqs148142 933dec9fcdSqs148142 /* 943dec9fcdSqs148142 * Register: PfcVlanCtrl 953dec9fcdSqs148142 * VLAN Control Register 963dec9fcdSqs148142 * Description: VLAN control register. Controls VLAN table properties 973dec9fcdSqs148142 * and implicit VLAN properties for non-VLAN tagged packets. 983dec9fcdSqs148142 * Fields: 993dec9fcdSqs148142 * VLAN table parity debug write enable. When set to 1, software 1003dec9fcdSqs148142 * writes the parity bits together with the data during a VLAN 1013dec9fcdSqs148142 * table write. Otherwise, hardware automatically generates the 1023dec9fcdSqs148142 * parity bits from the data. 1033dec9fcdSqs148142 * Set to 1 to indicate the implicit VLAN ID is valid for use in 1043dec9fcdSqs148142 * non-VLAN tagged packets filtering 1053dec9fcdSqs148142 * Implicit VLAN ID for non-VLAN tagged packets 1063dec9fcdSqs148142 */ 1073dec9fcdSqs148142 typedef union { 1083dec9fcdSqs148142 uint64_t value; 1093dec9fcdSqs148142 struct { 1103dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 111*fe930412Sqs148142 uint32_t rsrvd:32; 112*fe930412Sqs148142 uint32_t rsrvd_l:18; 113*fe930412Sqs148142 uint32_t par_en:1; 114*fe930412Sqs148142 uint32_t valid:1; 115*fe930412Sqs148142 uint32_t id:12; 1163dec9fcdSqs148142 #else 117*fe930412Sqs148142 uint32_t id:12; 118*fe930412Sqs148142 uint32_t valid:1; 119*fe930412Sqs148142 uint32_t par_en:1; 120*fe930412Sqs148142 uint32_t rsrvd_l:18; 121*fe930412Sqs148142 uint32_t rsrvd:32; 1223dec9fcdSqs148142 #endif 1233dec9fcdSqs148142 } bits; 1243dec9fcdSqs148142 } pfc_vlan_ctrl_t; 1253dec9fcdSqs148142 1263dec9fcdSqs148142 1273dec9fcdSqs148142 /* 1283dec9fcdSqs148142 * Register: PfcMacAddr 1293dec9fcdSqs148142 * MAC Address 1303dec9fcdSqs148142 * Description: MAC Address - Contains a station's 48 bit MAC 1313dec9fcdSqs148142 * address. The first register corresponds to MAC address 0, the 1323dec9fcdSqs148142 * second register corresponds to MAC address 1 and so on. For a MAC 1333dec9fcdSqs148142 * address of format aa-bb-cc-dd-ee-ff, addr[47:0] corresponds to 1343dec9fcdSqs148142 * "aabbccddeeff". When used in conjunction with the MAC address 1353dec9fcdSqs148142 * filter mask registers, these registers can be used to construct 1363dec9fcdSqs148142 * either a unicast or multicast address. An address is considered 1373dec9fcdSqs148142 * matched if (DA & ~mask) == (MAC address & ~mask) 1383dec9fcdSqs148142 * Fields: 1393dec9fcdSqs148142 * 48 bits of stations's MAC address 1403dec9fcdSqs148142 */ 1413dec9fcdSqs148142 typedef union { 1423dec9fcdSqs148142 uint64_t value; 1433dec9fcdSqs148142 struct { 1443dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 145*fe930412Sqs148142 uint32_t rsrvd:16; 146*fe930412Sqs148142 uint32_t addr:16; 147*fe930412Sqs148142 uint32_t addr_l:32; 1483dec9fcdSqs148142 #else 149*fe930412Sqs148142 uint32_t addr_l:32; 150*fe930412Sqs148142 uint32_t addr:16; 151*fe930412Sqs148142 uint32_t rsrvd:16; 1523dec9fcdSqs148142 #endif 1533dec9fcdSqs148142 } bits; 1543dec9fcdSqs148142 } pfc_mac_addr_t; 1553dec9fcdSqs148142 1563dec9fcdSqs148142 1573dec9fcdSqs148142 /* 1583dec9fcdSqs148142 * Register: PfcMacAddrMask 1593dec9fcdSqs148142 * MAC Address Filter 1603dec9fcdSqs148142 * Description: MAC Address Filter Mask - Contains the station's 48 1613dec9fcdSqs148142 * bit MAC address filter mask. The first register corresponds to MAC 1623dec9fcdSqs148142 * address 0 filter mask, the second register corresponds to MAC 1633dec9fcdSqs148142 * address 1 filter mask and so on. These filter masks cover MAC 1643dec9fcdSqs148142 * address bits 47:0 in the same order as the address registers 1653dec9fcdSqs148142 * Fields: 1663dec9fcdSqs148142 * 48 bits of stations's MAC address filter mask 1673dec9fcdSqs148142 */ 1683dec9fcdSqs148142 typedef union { 1693dec9fcdSqs148142 uint64_t value; 1703dec9fcdSqs148142 struct { 1713dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 172*fe930412Sqs148142 uint32_t rsrvd:16; 173*fe930412Sqs148142 uint32_t mask:16; 174*fe930412Sqs148142 uint32_t mask_l:32; 1753dec9fcdSqs148142 #else 176*fe930412Sqs148142 uint32_t mask_l:32; 177*fe930412Sqs148142 uint32_t mask:16; 178*fe930412Sqs148142 uint32_t rsrvd:16; 1793dec9fcdSqs148142 #endif 1803dec9fcdSqs148142 } bits; 1813dec9fcdSqs148142 } pfc_mac_addr_mask_t; 1823dec9fcdSqs148142 1833dec9fcdSqs148142 1843dec9fcdSqs148142 /* 1853dec9fcdSqs148142 * Register: PfcHashTable 1863dec9fcdSqs148142 * MAC Multicast Hash Filter 1873dec9fcdSqs148142 * Description: MAC multicast hash table filter. The multicast 1883dec9fcdSqs148142 * destination address is used to perform Ethernet CRC-32 hashing 1893dec9fcdSqs148142 * with seed value 0xffffFfff. Bits 47:40 of the hash result are used 1903dec9fcdSqs148142 * to index one bit of this multicast hash table. If the bit is '1', 1913dec9fcdSqs148142 * the multicast hash matches. 1923dec9fcdSqs148142 * Fields: 1933dec9fcdSqs148142 * 16 bits of 256 bit hash table. First entry contains bits 1943dec9fcdSqs148142 * [15:0], last entry contains bits [255:240] 1953dec9fcdSqs148142 */ 1963dec9fcdSqs148142 typedef union { 1973dec9fcdSqs148142 uint64_t value; 1983dec9fcdSqs148142 struct { 1993dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 200*fe930412Sqs148142 uint32_t rsrvd:32; 201*fe930412Sqs148142 uint32_t rsrvd_l:16; 202*fe930412Sqs148142 uint32_t hash_val:16; 2033dec9fcdSqs148142 #else 204*fe930412Sqs148142 uint32_t hash_val:16; 205*fe930412Sqs148142 uint32_t rsrvd_l:16; 206*fe930412Sqs148142 uint32_t rsrvd:32; 2073dec9fcdSqs148142 #endif 2083dec9fcdSqs148142 } bits; 2093dec9fcdSqs148142 } pfc_hash_table_t; 2103dec9fcdSqs148142 2113dec9fcdSqs148142 2123dec9fcdSqs148142 /* 2133dec9fcdSqs148142 * Register: PfcL2ClassConfig 2143dec9fcdSqs148142 * L2 Class Configuration 2153dec9fcdSqs148142 * Description: Programmable EtherType for class codes 2 and 3. The 2163dec9fcdSqs148142 * first register is class 2, and the second class 3 2173dec9fcdSqs148142 * Fields: 2183dec9fcdSqs148142 * Set to 1 to indicate that the entry is valid for use in 2193dec9fcdSqs148142 * classification 2203dec9fcdSqs148142 * EtherType value 2213dec9fcdSqs148142 */ 2223dec9fcdSqs148142 typedef union { 2233dec9fcdSqs148142 uint64_t value; 2243dec9fcdSqs148142 struct { 2253dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 226*fe930412Sqs148142 uint32_t rsrvd:32; 227*fe930412Sqs148142 uint32_t rsrvd_l:15; 228*fe930412Sqs148142 uint32_t valid:1; 229*fe930412Sqs148142 uint32_t etype:16; 2303dec9fcdSqs148142 #else 231*fe930412Sqs148142 uint32_t etype:16; 232*fe930412Sqs148142 uint32_t valid:1; 233*fe930412Sqs148142 uint32_t rsrvd_l:15; 234*fe930412Sqs148142 uint32_t rsrvd:32; 2353dec9fcdSqs148142 #endif 2363dec9fcdSqs148142 } bits; 2373dec9fcdSqs148142 } pfc_l2_class_config_t; 2383dec9fcdSqs148142 2393dec9fcdSqs148142 2403dec9fcdSqs148142 /* 2413dec9fcdSqs148142 * Register: PfcL3ClassConfig 2423dec9fcdSqs148142 * L3 Class Configuration 2433dec9fcdSqs148142 * Description: Configuration for class codes 0x8-0xF. PFC can be set 2443dec9fcdSqs148142 * to discard certain classes of traffic, or to not initiate a TCAM 2453dec9fcdSqs148142 * match for that class 2463dec9fcdSqs148142 * Fields: 2473dec9fcdSqs148142 * Set to 1 to discard all packets of this class code 2483dec9fcdSqs148142 * Set to 1 to indicate that packets of this class should be sent 2493dec9fcdSqs148142 * to the TCAM for perfect match 2503dec9fcdSqs148142 */ 2513dec9fcdSqs148142 typedef union { 2523dec9fcdSqs148142 uint64_t value; 2533dec9fcdSqs148142 struct { 2543dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 255*fe930412Sqs148142 uint32_t rsrvd:32; 256*fe930412Sqs148142 uint32_t rsrvd_l:28; 257*fe930412Sqs148142 uint32_t discard:1; 258*fe930412Sqs148142 uint32_t tsel:1; 259*fe930412Sqs148142 uint32_t rsrvd1:2; 2603dec9fcdSqs148142 #else 261*fe930412Sqs148142 uint32_t rsrvd1:2; 262*fe930412Sqs148142 uint32_t tsel:1; 263*fe930412Sqs148142 uint32_t discard:1; 264*fe930412Sqs148142 uint32_t rsrvd_l:28; 265*fe930412Sqs148142 uint32_t rsrvd:32; 2663dec9fcdSqs148142 #endif 2673dec9fcdSqs148142 } bits; 2683dec9fcdSqs148142 } pfc_l3_class_config_t; 2693dec9fcdSqs148142 2703dec9fcdSqs148142 2713dec9fcdSqs148142 /* 2723dec9fcdSqs148142 * Register: PfcTcamKey0 2733dec9fcdSqs148142 * TCAM Key 0 2743dec9fcdSqs148142 * Description: TCAM key value. Holds bit 63:0 of the TCAM key 2753dec9fcdSqs148142 * Fields: 2763dec9fcdSqs148142 * bits 63:0 of tcam key 2773dec9fcdSqs148142 */ 2783dec9fcdSqs148142 typedef union { 2793dec9fcdSqs148142 uint64_t value; 2803dec9fcdSqs148142 struct { 2813dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 282*fe930412Sqs148142 uint32_t key:32; 283*fe930412Sqs148142 uint32_t key_l:32; 2843dec9fcdSqs148142 #else 285*fe930412Sqs148142 uint32_t key_l:32; 286*fe930412Sqs148142 uint32_t key:32; 2873dec9fcdSqs148142 #endif 2883dec9fcdSqs148142 } bits; 2893dec9fcdSqs148142 } pfc_tcam_key0_t; 2903dec9fcdSqs148142 2913dec9fcdSqs148142 2923dec9fcdSqs148142 /* 2933dec9fcdSqs148142 * Register: PfcTcamKey1 2943dec9fcdSqs148142 * TCAM Key 1 2953dec9fcdSqs148142 * Description: TCAM key value. Holds bit 99:64 of the TCAM key 2963dec9fcdSqs148142 * Fields: 2973dec9fcdSqs148142 * bits 99:64 of tcam key 2983dec9fcdSqs148142 */ 2993dec9fcdSqs148142 typedef union { 3003dec9fcdSqs148142 uint64_t value; 3013dec9fcdSqs148142 struct { 3023dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 303*fe930412Sqs148142 uint32_t rsrvd:28; 304*fe930412Sqs148142 uint32_t key:4; 305*fe930412Sqs148142 uint32_t key_l:32; 3063dec9fcdSqs148142 #else 307*fe930412Sqs148142 uint32_t key_l:32; 308*fe930412Sqs148142 uint32_t key:4; 309*fe930412Sqs148142 uint32_t rsrvd:28; 3103dec9fcdSqs148142 #endif 3113dec9fcdSqs148142 } bits; 3123dec9fcdSqs148142 } pfc_tcam_key1_t; 3133dec9fcdSqs148142 3143dec9fcdSqs148142 3153dec9fcdSqs148142 /* 3163dec9fcdSqs148142 * Register: PfcTcamMask0 3173dec9fcdSqs148142 * TCAM Mask 0 3183dec9fcdSqs148142 * Description: TCAM mask value. Holds bit 63:0 of the TCAM mask 3193dec9fcdSqs148142 * Fields: 3203dec9fcdSqs148142 * bits 63:0 of tcam mask 3213dec9fcdSqs148142 */ 3223dec9fcdSqs148142 typedef union { 3233dec9fcdSqs148142 uint64_t value; 3243dec9fcdSqs148142 struct { 3253dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 326*fe930412Sqs148142 uint32_t mask:32; 327*fe930412Sqs148142 uint32_t mask_l:32; 3283dec9fcdSqs148142 #else 329*fe930412Sqs148142 uint32_t mask_l:32; 330*fe930412Sqs148142 uint32_t mask:32; 3313dec9fcdSqs148142 #endif 3323dec9fcdSqs148142 } bits; 3333dec9fcdSqs148142 } pfc_tcam_mask0_t; 3343dec9fcdSqs148142 3353dec9fcdSqs148142 3363dec9fcdSqs148142 /* 3373dec9fcdSqs148142 * Register: PfcTcamMask1 3383dec9fcdSqs148142 * TCAM Mask 1 3393dec9fcdSqs148142 * Description: TCAM mask value. Holds bit 99:64 of the TCAM mask 3403dec9fcdSqs148142 * Fields: 3413dec9fcdSqs148142 * bits 99:64 of tcam mask 3423dec9fcdSqs148142 */ 3433dec9fcdSqs148142 typedef union { 3443dec9fcdSqs148142 uint64_t value; 3453dec9fcdSqs148142 struct { 3463dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 347*fe930412Sqs148142 uint32_t rsrvd:28; 348*fe930412Sqs148142 uint32_t mask:4; 349*fe930412Sqs148142 uint32_t mask_l:32; 3503dec9fcdSqs148142 #else 351*fe930412Sqs148142 uint32_t mask_l:32; 352*fe930412Sqs148142 uint32_t mask:4; 353*fe930412Sqs148142 uint32_t rsrvd:28; 3543dec9fcdSqs148142 #endif 3553dec9fcdSqs148142 } bits; 3563dec9fcdSqs148142 } pfc_tcam_mask1_t; 3573dec9fcdSqs148142 3583dec9fcdSqs148142 3593dec9fcdSqs148142 /* 3603dec9fcdSqs148142 * Register: PfcTcamCtrl 3613dec9fcdSqs148142 * TCAM Control 3623dec9fcdSqs148142 * Description: TCAM and TCAM lookup memory access control register. 3633dec9fcdSqs148142 * Controls how TCAM and result lookup table are accessed by blade 3643dec9fcdSqs148142 * CPU. For a TCAM write, the data in the TCAM key and mask registers 3653dec9fcdSqs148142 * will be written to the TCAM. A compare will initiate a TCAM match 3663dec9fcdSqs148142 * with the data stored in the TCAM key register. The match bit is 3673dec9fcdSqs148142 * toggled, and the matching address is reported in the addr field. 3683dec9fcdSqs148142 * For an access to the TCAM result lookup memory, the TCAM 0 key 3693dec9fcdSqs148142 * register is used for the read/write data. 3703dec9fcdSqs148142 * Fields: 3713dec9fcdSqs148142 * TCAM lookup table debug parity bit write enable. When a '1' is 3723dec9fcdSqs148142 * written, software writes the parity bit together with the data 3733dec9fcdSqs148142 * during a TCAM result lookup write. Otherwise, hardware 3743dec9fcdSqs148142 * automatically generates the parity bit from the data. 3753dec9fcdSqs148142 * 3'b000 = TCAM write 3'b001 = reserved 3'b010 = TCAM compare 3763dec9fcdSqs148142 * 3'b011 = reserved 3'b100 = TCAM result lookup write 3'b101 = 3773dec9fcdSqs148142 * TCAM result lookup read 3'b110 = reserved 3'b111 = reserved 3783dec9fcdSqs148142 * Status of read/write/compare operation. When a zero is 3793dec9fcdSqs148142 * written, hardware initiates access. Hardware writes a '1' to 3803dec9fcdSqs148142 * the bit when it completes 3813dec9fcdSqs148142 * Set to 1 if there is a TCAM match for compare command. Zero 3823dec9fcdSqs148142 * otherwise 3833dec9fcdSqs148142 * Address location for access of TCAM or RAM (valid values 3843dec9fcdSqs148142 * 0-42). For a compare, the location of the match is written 3853dec9fcdSqs148142 * here by hardware. 3863dec9fcdSqs148142 */ 3873dec9fcdSqs148142 typedef union { 3883dec9fcdSqs148142 uint64_t value; 3893dec9fcdSqs148142 struct { 3903dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 391*fe930412Sqs148142 uint32_t rsrvd:32; 392*fe930412Sqs148142 uint32_t rsrvd_l:13; 393*fe930412Sqs148142 uint32_t par_en:1; 394*fe930412Sqs148142 uint32_t cmd:3; 395*fe930412Sqs148142 uint32_t status:1; 396*fe930412Sqs148142 uint32_t match:1; 397*fe930412Sqs148142 uint32_t rsrvd1:5; 398*fe930412Sqs148142 uint32_t addr:8; 3993dec9fcdSqs148142 #else 400*fe930412Sqs148142 uint32_t addr:8; 401*fe930412Sqs148142 uint32_t rsrvd1:5; 402*fe930412Sqs148142 uint32_t match:1; 403*fe930412Sqs148142 uint32_t status:1; 404*fe930412Sqs148142 uint32_t cmd:3; 405*fe930412Sqs148142 uint32_t par_en:1; 406*fe930412Sqs148142 uint32_t rsrvd_l:13; 407*fe930412Sqs148142 uint32_t rsrvd:32; 4083dec9fcdSqs148142 #endif 4093dec9fcdSqs148142 } bits; 4103dec9fcdSqs148142 } pfc_tcam_ctrl_t; 4113dec9fcdSqs148142 4123dec9fcdSqs148142 4133dec9fcdSqs148142 /* 4143dec9fcdSqs148142 * Register: PfcConfig 4153dec9fcdSqs148142 * PFC General Configuration 4163dec9fcdSqs148142 * Description: PFC configuration options that are under the control 4173dec9fcdSqs148142 * of a blade CPU 4183dec9fcdSqs148142 * Fields: 4193dec9fcdSqs148142 * MAC address enable mask. Each bit corresponds to one MAC 4203dec9fcdSqs148142 * adress (lsb = addr0). With 16 MAC addresses, only the lower 16 4213dec9fcdSqs148142 * bits are valid. 4223dec9fcdSqs148142 * default DMA channel number 4233dec9fcdSqs148142 * force TCP/UDP checksum result to always match 4243dec9fcdSqs148142 * Enable for TCP/UDP checksum. If not enabled, the result will 4253dec9fcdSqs148142 * never match. 4263dec9fcdSqs148142 * Enable TCAM matching. If TCAM matching is not enabled, traffic 4273dec9fcdSqs148142 * will be sent to the default DMA channel. 4283dec9fcdSqs148142 * Enable L2 Multicast hash 4293dec9fcdSqs148142 */ 4303dec9fcdSqs148142 typedef union { 4313dec9fcdSqs148142 uint64_t value; 4323dec9fcdSqs148142 struct { 4333dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 434*fe930412Sqs148142 uint32_t rsrvd:24; 435*fe930412Sqs148142 uint32_t mac_addr_en:8; 436*fe930412Sqs148142 uint32_t mac_addr_en_l:24; 437*fe930412Sqs148142 uint32_t default_dma:4; 438*fe930412Sqs148142 uint32_t force_cs_en:1; 439*fe930412Sqs148142 uint32_t tcp_cs_en:1; 440*fe930412Sqs148142 uint32_t tcam_en:1; 441*fe930412Sqs148142 uint32_t l2_hash_en:1; 4423dec9fcdSqs148142 #else 443*fe930412Sqs148142 uint32_t l2_hash_en:1; 444*fe930412Sqs148142 uint32_t tcam_en:1; 445*fe930412Sqs148142 uint32_t tcp_cs_en:1; 446*fe930412Sqs148142 uint32_t force_cs_en:1; 447*fe930412Sqs148142 uint32_t default_dma:4; 448*fe930412Sqs148142 uint32_t mac_addr_en_l:24; 449*fe930412Sqs148142 uint32_t mac_addr_en:8; 450*fe930412Sqs148142 uint32_t rsrvd:24; 4513dec9fcdSqs148142 #endif 4523dec9fcdSqs148142 } bits; 4533dec9fcdSqs148142 } pfc_config_t; 4543dec9fcdSqs148142 4553dec9fcdSqs148142 4563dec9fcdSqs148142 /* 4573dec9fcdSqs148142 * Register: TcpCtrlMask 4583dec9fcdSqs148142 * TCP control bits mask 4593dec9fcdSqs148142 * Description: Mask of TCP control bits to forward onto downstream 4603dec9fcdSqs148142 * blocks The TCP packet's control bits are masked, and then bitwise 4613dec9fcdSqs148142 * OR'd to produce a signal to the Rx DMA. Normally, all bits are 4623dec9fcdSqs148142 * masked off except the TCP SYN bit. The Rx DMA uses this bitwise OR 4633dec9fcdSqs148142 * for statistics. When discard = 1, the packet will be dropped if 4643dec9fcdSqs148142 * the bitwise OR = 1. 4653dec9fcdSqs148142 * Fields: 4663dec9fcdSqs148142 * Drop the packet if bitwise OR of the TCP control bits masked 4673dec9fcdSqs148142 * on = 1 4683dec9fcdSqs148142 * TCP end of data flag 4693dec9fcdSqs148142 * TCP SYN flag 4703dec9fcdSqs148142 * TCP reset flag 4713dec9fcdSqs148142 * TCP push flag 4723dec9fcdSqs148142 * TCP ack flag 4733dec9fcdSqs148142 * TCP urgent flag 4743dec9fcdSqs148142 */ 4753dec9fcdSqs148142 typedef union { 4763dec9fcdSqs148142 uint64_t value; 4773dec9fcdSqs148142 struct { 4783dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 479*fe930412Sqs148142 uint32_t rsrvd:32; 480*fe930412Sqs148142 uint32_t rsrvd_l:25; 481*fe930412Sqs148142 uint32_t discard:1; 482*fe930412Sqs148142 uint32_t fin:1; 483*fe930412Sqs148142 uint32_t syn:1; 484*fe930412Sqs148142 uint32_t rst:1; 485*fe930412Sqs148142 uint32_t psh:1; 486*fe930412Sqs148142 uint32_t ack:1; 487*fe930412Sqs148142 uint32_t urg:1; 4883dec9fcdSqs148142 #else 489*fe930412Sqs148142 uint32_t urg:1; 490*fe930412Sqs148142 uint32_t ack:1; 491*fe930412Sqs148142 uint32_t psh:1; 492*fe930412Sqs148142 uint32_t rst:1; 493*fe930412Sqs148142 uint32_t syn:1; 494*fe930412Sqs148142 uint32_t fin:1; 495*fe930412Sqs148142 uint32_t discard:1; 496*fe930412Sqs148142 uint32_t rsrvd_l:25; 497*fe930412Sqs148142 uint32_t rsrvd:32; 4983dec9fcdSqs148142 #endif 4993dec9fcdSqs148142 } bits; 5003dec9fcdSqs148142 } tcp_ctrl_mask_t; 5013dec9fcdSqs148142 5023dec9fcdSqs148142 5033dec9fcdSqs148142 /* 5043dec9fcdSqs148142 * Register: SrcHashVal 5053dec9fcdSqs148142 * Source hash Seed Value 5063dec9fcdSqs148142 * Hash CRC seed value 5073dec9fcdSqs148142 */ 5083dec9fcdSqs148142 typedef union { 5093dec9fcdSqs148142 uint64_t value; 5103dec9fcdSqs148142 struct { 5113dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 512*fe930412Sqs148142 uint32_t rsrvd:32; 513*fe930412Sqs148142 uint32_t seed:32; 5143dec9fcdSqs148142 #else 515*fe930412Sqs148142 uint32_t seed:32; 516*fe930412Sqs148142 uint32_t rsrvd:32; 5173dec9fcdSqs148142 #endif 5183dec9fcdSqs148142 } bits; 5193dec9fcdSqs148142 } src_hash_val_t; 5203dec9fcdSqs148142 5213dec9fcdSqs148142 5223dec9fcdSqs148142 /* 5233dec9fcdSqs148142 * Register: PfcIntStatus 5243dec9fcdSqs148142 * PFC Interrupt Status 5253dec9fcdSqs148142 * Description: PFC interrupt status register 5263dec9fcdSqs148142 * Fields: 5273dec9fcdSqs148142 * triggered when packet drop log captured a drop. Part of LDF 0. 5283dec9fcdSqs148142 * Write 1 to clear. 5293dec9fcdSqs148142 * TCAM result lookup table parity error. Part of LDF 0. Write 1 5303dec9fcdSqs148142 * to clear. 5313dec9fcdSqs148142 * VLAN table parity error. Part of LDF 0. Write 1 to clear. 5323dec9fcdSqs148142 */ 5333dec9fcdSqs148142 typedef union { 5343dec9fcdSqs148142 uint64_t value; 5353dec9fcdSqs148142 struct { 5363dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 537*fe930412Sqs148142 uint32_t rsrvd:32; 538*fe930412Sqs148142 uint32_t rsrvd_l:29; 539*fe930412Sqs148142 uint32_t pkt_drop:1; 540*fe930412Sqs148142 uint32_t tcam_parity_err:1; 541*fe930412Sqs148142 uint32_t vlan_parity_err:1; 5423dec9fcdSqs148142 #else 543*fe930412Sqs148142 uint32_t vlan_parity_err:1; 544*fe930412Sqs148142 uint32_t tcam_parity_err:1; 545*fe930412Sqs148142 uint32_t pkt_drop:1; 546*fe930412Sqs148142 uint32_t rsrvd_l:29; 547*fe930412Sqs148142 uint32_t rsrvd:32; 5483dec9fcdSqs148142 #endif 5493dec9fcdSqs148142 } bits; 5503dec9fcdSqs148142 } pfc_int_status_t; 5513dec9fcdSqs148142 5523dec9fcdSqs148142 5533dec9fcdSqs148142 /* 5543dec9fcdSqs148142 * Register: PfcDbgIntStatus 5553dec9fcdSqs148142 * PFC Debug Interrupt Status 5563dec9fcdSqs148142 * Description: PFC debug interrupt status mirror register. This 5573dec9fcdSqs148142 * debug register triggers the same interrupts as those in the PFC 5583dec9fcdSqs148142 * Interrupt Status register. Interrupts in this mirror register are 5593dec9fcdSqs148142 * subject to the filtering of the PFC Interrupt Mask register. 5603dec9fcdSqs148142 * Fields: 5613dec9fcdSqs148142 * Packet drop. Part of LDF 0. 5623dec9fcdSqs148142 * TCAM result lookup table parity error. Part of LDF 0. 5633dec9fcdSqs148142 * VLAN table parity error. Part of LDF 0. 5643dec9fcdSqs148142 */ 5653dec9fcdSqs148142 typedef union { 5663dec9fcdSqs148142 uint64_t value; 5673dec9fcdSqs148142 struct { 5683dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 569*fe930412Sqs148142 uint32_t rsrvd:32; 570*fe930412Sqs148142 uint32_t rsrvd_l:29; 571*fe930412Sqs148142 uint32_t pkt_drop:1; 572*fe930412Sqs148142 uint32_t tcam_parity_err:1; 573*fe930412Sqs148142 uint32_t vlan_parity_err:1; 5743dec9fcdSqs148142 #else 575*fe930412Sqs148142 uint32_t vlan_parity_err:1; 576*fe930412Sqs148142 uint32_t tcam_parity_err:1; 577*fe930412Sqs148142 uint32_t pkt_drop:1; 578*fe930412Sqs148142 uint32_t rsrvd_l:29; 579*fe930412Sqs148142 uint32_t rsrvd:32; 5803dec9fcdSqs148142 #endif 5813dec9fcdSqs148142 } bits; 5823dec9fcdSqs148142 } pfc_dbg_int_status_t; 5833dec9fcdSqs148142 5843dec9fcdSqs148142 5853dec9fcdSqs148142 /* 5863dec9fcdSqs148142 * Register: PfcIntMask 5873dec9fcdSqs148142 * PFC Interrupt Mask 5883dec9fcdSqs148142 * Description: PFC interrupt status mask register 5893dec9fcdSqs148142 * Fields: 5903dec9fcdSqs148142 * mask for pktDrop capture; 5913dec9fcdSqs148142 * TCAM result lookup table parity error mask; 5923dec9fcdSqs148142 * VLAN table parity error mask; 5933dec9fcdSqs148142 */ 5943dec9fcdSqs148142 typedef union { 5953dec9fcdSqs148142 uint64_t value; 5963dec9fcdSqs148142 struct { 5973dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 598*fe930412Sqs148142 uint32_t rsrvd:32; 599*fe930412Sqs148142 uint32_t rsrvd_l:29; 600*fe930412Sqs148142 uint32_t pkt_drop_mask:1; 601*fe930412Sqs148142 uint32_t tcam_parity_err_mask:1; 602*fe930412Sqs148142 uint32_t vlan_parity_err_mask:1; 6033dec9fcdSqs148142 #else 604*fe930412Sqs148142 uint32_t vlan_parity_err_mask:1; 605*fe930412Sqs148142 uint32_t tcam_parity_err_mask:1; 606*fe930412Sqs148142 uint32_t pkt_drop_mask:1; 607*fe930412Sqs148142 uint32_t rsrvd_l:29; 608*fe930412Sqs148142 uint32_t rsrvd:32; 6093dec9fcdSqs148142 #endif 6103dec9fcdSqs148142 } bits; 6113dec9fcdSqs148142 } pfc_int_mask_t; 6123dec9fcdSqs148142 6133dec9fcdSqs148142 6143dec9fcdSqs148142 /* 6153dec9fcdSqs148142 * Register: PfcDropLog 6163dec9fcdSqs148142 * Packet Drop Log 6173dec9fcdSqs148142 * Description: Packet drop log. Log for capturing packet drops. Log 6183dec9fcdSqs148142 * is re-armed when associated interrupt bit is cleared. 6193dec9fcdSqs148142 * Fields: 6203dec9fcdSqs148142 * drop because bitwise OR of the tcp control bits masked on = 1 6213dec9fcdSqs148142 * drop because L2 address did not match 6223dec9fcdSqs148142 * drop because class code indicated drop 6233dec9fcdSqs148142 * drop because TCAM result indicated drop 6243dec9fcdSqs148142 * drop because blade was not a member of VLAN 6253dec9fcdSqs148142 */ 6263dec9fcdSqs148142 typedef union { 6273dec9fcdSqs148142 uint64_t value; 6283dec9fcdSqs148142 struct { 6293dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 630*fe930412Sqs148142 uint32_t rsrvd:32; 631*fe930412Sqs148142 uint32_t rsrvd_l:27; 632*fe930412Sqs148142 uint32_t tcp_ctrl_drop:1; 633*fe930412Sqs148142 uint32_t l2_addr_drop:1; 634*fe930412Sqs148142 uint32_t class_code_drop:1; 635*fe930412Sqs148142 uint32_t tcam_drop:1; 636*fe930412Sqs148142 uint32_t vlan_drop:1; 6373dec9fcdSqs148142 #else 638*fe930412Sqs148142 uint32_t vlan_drop:1; 639*fe930412Sqs148142 uint32_t tcam_drop:1; 640*fe930412Sqs148142 uint32_t class_code_drop:1; 641*fe930412Sqs148142 uint32_t l2_addr_drop:1; 642*fe930412Sqs148142 uint32_t tcp_ctrl_drop:1; 643*fe930412Sqs148142 uint32_t rsrvd_l:27; 644*fe930412Sqs148142 uint32_t rsrvd:32; 6453dec9fcdSqs148142 #endif 6463dec9fcdSqs148142 } bits; 6473dec9fcdSqs148142 } pfc_drop_log_t; 6483dec9fcdSqs148142 6493dec9fcdSqs148142 6503dec9fcdSqs148142 /* 6513dec9fcdSqs148142 * Register: PfcDropLogMask 6523dec9fcdSqs148142 * Packet Drop Log Mask 6533dec9fcdSqs148142 * Description: Mask for logging packet drop. If the drop type is 6543dec9fcdSqs148142 * masked off, it will not trigger the drop log to capture the packet 6553dec9fcdSqs148142 * drop 6563dec9fcdSqs148142 * Fields: 6573dec9fcdSqs148142 * mask drop because bitwise OR of the tcp control bits masked on 6583dec9fcdSqs148142 * = 1 6593dec9fcdSqs148142 * mask drop because L2 address did not match 6603dec9fcdSqs148142 * mask drop because class code indicated 6613dec9fcdSqs148142 * mask drop because TCAM result indicated drop 6623dec9fcdSqs148142 * mask drop because blade was not a member of VLAN 6633dec9fcdSqs148142 */ 6643dec9fcdSqs148142 typedef union { 6653dec9fcdSqs148142 uint64_t value; 6663dec9fcdSqs148142 struct { 6673dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 668*fe930412Sqs148142 uint32_t rsrvd:32; 669*fe930412Sqs148142 uint32_t rsrvd_l:27; 670*fe930412Sqs148142 uint32_t tcp_ctrl_drop_mask:1; 671*fe930412Sqs148142 uint32_t l2_addr_drop_mask:1; 672*fe930412Sqs148142 uint32_t class_code_drop_mask:1; 673*fe930412Sqs148142 uint32_t tcam_drop_mask:1; 674*fe930412Sqs148142 uint32_t vlan_drop_mask:1; 6753dec9fcdSqs148142 #else 676*fe930412Sqs148142 uint32_t vlan_drop_mask:1; 677*fe930412Sqs148142 uint32_t tcam_drop_mask:1; 678*fe930412Sqs148142 uint32_t class_code_drop_mask:1; 679*fe930412Sqs148142 uint32_t l2_addr_drop_mask:1; 680*fe930412Sqs148142 uint32_t tcp_ctrl_drop_mask:1; 681*fe930412Sqs148142 uint32_t rsrvd_l:27; 682*fe930412Sqs148142 uint32_t rsrvd:32; 6833dec9fcdSqs148142 #endif 6843dec9fcdSqs148142 } bits; 6853dec9fcdSqs148142 } pfc_drop_log_mask_t; 6863dec9fcdSqs148142 6873dec9fcdSqs148142 6883dec9fcdSqs148142 /* 6893dec9fcdSqs148142 * Register: PfcVlanParErrLog 6903dec9fcdSqs148142 * VLAN Parity Error Log 6913dec9fcdSqs148142 * Description: Log of parity errors in VLAN table. 6923dec9fcdSqs148142 * Fields: 6933dec9fcdSqs148142 * address of parity error. Log is cleared when corresponding 6943dec9fcdSqs148142 * interrupt bit is cleared by writing '1'. 6953dec9fcdSqs148142 */ 6963dec9fcdSqs148142 typedef union { 6973dec9fcdSqs148142 uint64_t value; 6983dec9fcdSqs148142 struct { 6993dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 700*fe930412Sqs148142 uint32_t rsrvd:32; 701*fe930412Sqs148142 uint32_t rsrvd_l:20; 702*fe930412Sqs148142 uint32_t addr:12; 7033dec9fcdSqs148142 #else 704*fe930412Sqs148142 uint32_t addr:12; 705*fe930412Sqs148142 uint32_t rsrvd_l:20; 706*fe930412Sqs148142 uint32_t rsrvd:32; 7073dec9fcdSqs148142 #endif 7083dec9fcdSqs148142 } bits; 7093dec9fcdSqs148142 } pfc_vlan_par_err_log_t; 7103dec9fcdSqs148142 7113dec9fcdSqs148142 7123dec9fcdSqs148142 /* 7133dec9fcdSqs148142 * Register: PfcTcamParErrLog 7143dec9fcdSqs148142 * TCAM Parity Error Log 7153dec9fcdSqs148142 * Description: Log of parity errors in TCAM result lookup table. 7163dec9fcdSqs148142 * Fields: 7173dec9fcdSqs148142 * address of parity error. Log is cleared when corresponding 7183dec9fcdSqs148142 * interrupt bit is cleared by writing '1'. 7193dec9fcdSqs148142 */ 7203dec9fcdSqs148142 typedef union { 7213dec9fcdSqs148142 uint64_t value; 7223dec9fcdSqs148142 struct { 7233dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 724*fe930412Sqs148142 uint32_t rsrvd:32; 725*fe930412Sqs148142 uint32_t rsrvd_l:24; 726*fe930412Sqs148142 uint32_t addr:8; 7273dec9fcdSqs148142 #else 728*fe930412Sqs148142 uint32_t addr:8; 729*fe930412Sqs148142 uint32_t rsrvd_l:24; 730*fe930412Sqs148142 uint32_t rsrvd:32; 7313dec9fcdSqs148142 #endif 7323dec9fcdSqs148142 } bits; 7333dec9fcdSqs148142 } pfc_tcam_par_err_log_t; 7343dec9fcdSqs148142 7353dec9fcdSqs148142 7363dec9fcdSqs148142 /* 7373dec9fcdSqs148142 * Register: PfcBadCsCounter 7383dec9fcdSqs148142 * PFC Bad Checksum Counter 7393dec9fcdSqs148142 * Description: Count number of bad TCP/UDP checksum. Only counted if 7403dec9fcdSqs148142 * L2 adddress matched 7413dec9fcdSqs148142 * Fields: 7423dec9fcdSqs148142 * count of number of bad TCP/UDP checksums received. Clear on 7433dec9fcdSqs148142 * read 7443dec9fcdSqs148142 */ 7453dec9fcdSqs148142 typedef union { 7463dec9fcdSqs148142 uint64_t value; 7473dec9fcdSqs148142 struct { 7483dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 749*fe930412Sqs148142 uint32_t rsrvd:32; 750*fe930412Sqs148142 uint32_t bad_cs_count:32; 7513dec9fcdSqs148142 #else 752*fe930412Sqs148142 uint32_t bad_cs_count:32; 753*fe930412Sqs148142 uint32_t rsrvd:32; 7543dec9fcdSqs148142 #endif 7553dec9fcdSqs148142 } bits; 7563dec9fcdSqs148142 } pfc_bad_cs_counter_t; 7573dec9fcdSqs148142 7583dec9fcdSqs148142 7593dec9fcdSqs148142 /* 7603dec9fcdSqs148142 * Register: PfcDropCounter 7613dec9fcdSqs148142 * PFC Drop Counter 7623dec9fcdSqs148142 * Description: Count number of packets dropped due to VLAN 7633dec9fcdSqs148142 * membership, class code, TCP control bits, or TCAM results Only 7643dec9fcdSqs148142 * counted if L2 address matched. 7653dec9fcdSqs148142 * Fields: 7663dec9fcdSqs148142 * Count of number of packets dropped due to VLAN, TCAM results. 7673dec9fcdSqs148142 * Clear on read 7683dec9fcdSqs148142 */ 7693dec9fcdSqs148142 typedef union { 7703dec9fcdSqs148142 uint64_t value; 7713dec9fcdSqs148142 struct { 7723dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 773*fe930412Sqs148142 uint32_t rsrvd:32; 774*fe930412Sqs148142 uint32_t drop_count:32; 7753dec9fcdSqs148142 #else 776*fe930412Sqs148142 uint32_t drop_count:32; 777*fe930412Sqs148142 uint32_t rsrvd:32; 7783dec9fcdSqs148142 #endif 7793dec9fcdSqs148142 } bits; 7803dec9fcdSqs148142 } pfc_drop_counter_t; 7813dec9fcdSqs148142 7823dec9fcdSqs148142 7833dec9fcdSqs148142 /* 7843dec9fcdSqs148142 * Register: PfcAutoInit 7853dec9fcdSqs148142 * PFC Auto Init 7863dec9fcdSqs148142 * Description: PFC Auto Initialization. Writing to this register 7873dec9fcdSqs148142 * triggers the auto initialization of the blade's TCAM entries with 7883dec9fcdSqs148142 * 100 bits of '0' for both key and mask. TCAM lookup is disabled 7893dec9fcdSqs148142 * during auto initialization. 7903dec9fcdSqs148142 * Fields: 7913dec9fcdSqs148142 * TCAM auto initialization status. 0=busy, 1=done. 7923dec9fcdSqs148142 */ 7933dec9fcdSqs148142 typedef union { 7943dec9fcdSqs148142 uint64_t value; 7953dec9fcdSqs148142 struct { 7963dec9fcdSqs148142 #if defined(_BIG_ENDIAN) 797*fe930412Sqs148142 uint32_t rsrvd:32; 798*fe930412Sqs148142 uint32_t rsrvd_l:31; 799*fe930412Sqs148142 uint32_t auto_init_status:1; 8003dec9fcdSqs148142 #else 801*fe930412Sqs148142 uint32_t auto_init_status:1; 802*fe930412Sqs148142 uint32_t rsrvd_l:31; 803*fe930412Sqs148142 uint32_t rsrvd:32; 8043dec9fcdSqs148142 #endif 8053dec9fcdSqs148142 } bits; 8063dec9fcdSqs148142 } pfc_auto_init_t; 8073dec9fcdSqs148142 8083dec9fcdSqs148142 8093dec9fcdSqs148142 #ifdef __cplusplus 8103dec9fcdSqs148142 } 8113dec9fcdSqs148142 #endif 8123dec9fcdSqs148142 8133dec9fcdSqs148142 #endif /* _HXGE_PFC_HW_H */ 814