1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _HXGE_PFC_H 28 #define _HXGE_PFC_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* 0 and 4095 are reserved */ 35 #define VLAN_ID_MIN 1 36 #define VLAN_ID_MAX 4094 37 #define VLAN_ID_IMPLICIT 0 38 39 #define HXGE_MAC_DEFAULT_ADDR_SLOT 0 40 41 #define HASH_BITS 8 42 #define NMCFILTER_BITS (1 << HASH_BITS) 43 #define HASH_REG_WIDTH 16 44 #define NMCFILTER_REGS (NMCFILTER_BITS / HASH_REG_WIDTH) 45 /* Number of multicast filter regs */ 46 #define MAC_MAX_HASH_ENTRY NMCFILTER_REGS 47 48 #define REG_PIO_WRITE64(handle, offset, value) \ 49 HXGE_REG_WR64((handle), (offset), (value)) 50 #define REG_PIO_READ64(handle, offset, val_p) \ 51 HXGE_REG_RD64((handle), (offset), (val_p)) 52 53 #define TCAM_CTL_RWC_TCAM_WR 0x0 54 #define TCAM_CTL_RWC_TCAM_CMP 0x2 55 #define TCAM_CTL_RWC_RAM_WR 0x4 56 #define TCAM_CTL_RWC_RAM_RD 0x5 57 #define TCAM_CTL_RWC_RWC_STAT 0x1 58 #define TCAM_CTL_RWC_RWC_MATCH 0x1 59 60 #define WRITE_TCAM_REG_CTL(handle, ctl) \ 61 REG_PIO_WRITE64(handle, PFC_TCAM_CTRL, ctl) 62 63 #define READ_TCAM_REG_CTL(handle, val_p) \ 64 REG_PIO_READ64(handle, PFC_TCAM_CTRL, val_p) 65 66 #define WRITE_TCAM_REG_KEY0(handle, key) \ 67 REG_PIO_WRITE64(handle, PFC_TCAM_KEY0, key) 68 #define WRITE_TCAM_REG_KEY1(handle, key) \ 69 REG_PIO_WRITE64(handle, PFC_TCAM_KEY1, key) 70 #define WRITE_TCAM_REG_MASK0(handle, mask) \ 71 REG_PIO_WRITE64(handle, PFC_TCAM_MASK0, mask) 72 #define WRITE_TCAM_REG_MASK1(handle, mask) \ 73 REG_PIO_WRITE64(handle, PFC_TCAM_MASK1, mask) 74 75 #define READ_TCAM_REG_KEY0(handle, val_p) \ 76 REG_PIO_READ64(handle, PFC_TCAM_KEY0, val_p) 77 #define READ_TCAM_REG_KEY1(handle, val_p) \ 78 REG_PIO_READ64(handle, PFC_TCAM_KEY1, val_p) 79 #define READ_TCAM_REG_MASK0(handle, val_p) \ 80 REG_PIO_READ64(handle, PFC_TCAM_MASK0, val_p) 81 #define READ_TCAM_REG_MASK1(handle, val_p) \ 82 REG_PIO_READ64(handle, PFC_TCAM_MASK1, val_p) 83 84 typedef union _hxge_tcam_res_t { 85 uint64_t value; 86 struct { 87 #if defined(_BIG_ENDIAN) 88 uint32_t padding:32; 89 uint32_t padding_l:2; 90 uint32_t reserved:15; 91 uint32_t parity:1; 92 uint32_t hit_count:4; 93 uint32_t channel_d:2; 94 uint32_t channel_c:2; 95 uint32_t channel_b:2; 96 uint32_t channel_a:2; 97 uint32_t source_hash:1; 98 uint32_t discard:1; 99 #else 100 uint32_t discard:1; 101 uint32_t source_hash:1; 102 uint32_t channel_a:2; 103 uint32_t channel_b:2; 104 uint32_t channel_c:2; 105 uint32_t channel_d:2; 106 uint32_t hit_count:4; 107 uint32_t parity:1; 108 uint32_t reserved:15; 109 uint32_t padding_l:2; 110 uint32_t padding:32; 111 #endif 112 } bits; 113 } hxge_tcam_res_t, *p_hxge_tcam_res_t; 114 115 typedef struct tcam_reg { 116 #if defined(_BIG_ENDIAN) 117 uint64_t reg1; /* 99:64 */ 118 uint64_t reg0; /* 63:0 */ 119 #else 120 uint64_t reg0; /* 63:0 */ 121 uint64_t reg1; /* 99:64 */ 122 #endif 123 } hxge_tcam_reg_t; 124 125 typedef struct hxge_tcam_ipv4_S { 126 #if defined(_BIG_ENDIAN) 127 uint32_t class_code:4; /* 99:96 */ 128 uint32_t class_code_l:1; /* 95:95 */ 129 uint32_t blade_id:4; /* 94:91 */ 130 uint32_t rsrvd2:2; /* 90:89 */ 131 uint32_t noport:1; /* 88 */ 132 uint32_t protocol:8; /* 87:80 */ 133 uint32_t l4_hdr:16; /* 79:64 */ 134 uint32_t l4_hdr_l:16; /* 63:48 */ 135 uint32_t rsrvd:16; /* 47:32 */ 136 uint32_t ip_daddr; /* 31:0 */ 137 #else 138 uint32_t ip_daddr; /* 31:0 */ 139 uint32_t rsrvd:16; /* 47:32 */ 140 uint32_t l4_hdr_l:16; /* 63:48 */ 141 uint32_t l4_hdr:16; /* 79:64 */ 142 uint32_t protocol:8; /* 87:80 */ 143 uint32_t noport:1; /* 88 */ 144 uint32_t rsrvd2:2; /* 90:89 */ 145 uint32_t blade_id:4; /* 94:91 */ 146 uint32_t class_code_l:1; /* 95:95 */ 147 uint32_t class_code:4; /* 99:96 */ 148 #endif 149 } hxge_tcam_ipv4_t; 150 151 typedef struct hxge_tcam_ipv6_S { 152 #if defined(_BIG_ENDIAN) 153 uint32_t class_code:4; /* 99:96 */ 154 uint32_t class_code_l:1; /* 95:95 */ 155 uint32_t blade_id:4; /* 94:91 */ 156 uint32_t rsrvd2:3; /* 90:88 */ 157 uint32_t protocol:8; /* 87:80 */ 158 uint32_t l4_hdr:16; /* 79:64 */ 159 uint32_t l4_hdr_l:16; /* 63:48 */ 160 uint32_t rsrvd:16; /* 47:32 */ 161 uint32_t rsrvd_l:32; /* 31:0 */ 162 #else 163 uint32_t rsrvd_l:32; /* 31:0 */ 164 uint32_t rsrvd:16; /* 47:32 */ 165 uint32_t l4_hdr_l:16; /* 63:48 */ 166 uint32_t l4_hdr:16; /* 79:64 */ 167 uint32_t protocol:8; /* 87:80 */ 168 uint32_t rsrvd2:3; /* 90:88 */ 169 uint32_t blade_id:4; /* 94:91 */ 170 uint32_t class_code_l:1; /* 95:95 */ 171 uint32_t class_code:4; /* 99:96 */ 172 #endif 173 } hxge_tcam_ipv6_t; 174 175 typedef struct hxge_tcam_enet_S { 176 #if defined(_BIG_ENDIAN) 177 uint8_t class_code:4; /* 99:96 */ 178 uint8_t class_code_l:1; /* 95:95 */ 179 uint8_t blade_id:4; /* 94:91 */ 180 uint8_t rsrvd:3; /* 90:88 */ 181 uint8_t eframe[11]; /* 87:0 */ 182 #else 183 uint8_t eframe[11]; /* 87:0 */ 184 uint8_t rsrvd:3; /* 90:88 */ 185 uint8_t blade_id:4; /* 94:91 */ 186 uint8_t class_code_l:1; /* 95:95 */ 187 uint8_t class_code:4; /* 99:96 */ 188 #endif 189 } hxge_tcam_ether_t; 190 191 typedef struct hxge_tcam_spread_S { 192 #if defined(_BIG_ENDIAN) 193 uint32_t unused:28; /* 127:100 */ 194 uint32_t class_code:4; /* 99:96 */ 195 uint32_t class_code_l:1; /* 95:95 */ 196 uint32_t blade_id:4; /* 94:91 */ 197 uint32_t wild1:27; /* 90:64 */ 198 uint32_t wild; /* 63:32 */ 199 uint32_t wild_l; /* 31:0 */ 200 #else 201 uint32_t wild_l; /* 31:0 */ 202 uint32_t wild; /* 63:32 */ 203 uint32_t wild1:27; /* 90:64 */ 204 uint32_t blade_id:4; /* 94:91 */ 205 uint32_t class_code_l:1; /* 95:95 */ 206 uint32_t class_code:4; /* 99:96 */ 207 uint32_t unused:28; /* 127:100 */ 208 #endif 209 } hxge_tcam_spread_t; 210 211 typedef struct hxge_tcam_entry_S { 212 union _hxge_tcam_entry { 213 hxge_tcam_ipv4_t ipv4; 214 hxge_tcam_ipv6_t ipv6; 215 hxge_tcam_ether_t enet; 216 hxge_tcam_reg_t regs; 217 hxge_tcam_spread_t spread; 218 } key, mask; 219 hxge_tcam_res_t match_action; 220 uint16_t ether_type; 221 } hxge_tcam_entry_t; 222 223 #define key_reg0 key.regs.reg0 224 #define key_reg1 key.regs.reg1 225 #define mask_reg0 mask.regs.reg0 226 #define mask_reg1 mask.regs.reg1 227 228 #define key0 key.regs.reg0 229 #define key1 key.regs.reg1 230 #define mask0 mask.regs.reg0 231 #define mask1 mask.regs.reg1 232 233 #define ip4_class_key key.ipv4.class_code 234 #define ip4_class_key_l key.ipv4.class_code_l 235 #define ip4_blade_id_key key.ipv4.blade_id 236 #define ip4_noport_key key.ipv4.noport 237 #define ip4_proto_key key.ipv4.protocol 238 #define ip4_l4_hdr_key key.ipv4.l4_hdr 239 #define ip4_l4_hdr_key_l key.ipv4.l4_hdr_l 240 #define ip4_dest_key key.ipv4.ip_daddr 241 242 #define ip4_class_mask mask.ipv4.class_code 243 #define ip4_class_mask_l mask.ipv4.class_code_l 244 #define ip4_blade_id_mask mask.ipv4.blade_id 245 #define ip4_noport_mask mask.ipv4.noport 246 #define ip4_proto_mask mask.ipv4.protocol 247 #define ip4_l4_hdr_mask mask.ipv4.l4_hdr 248 #define ip4_l4_hdr_mask_l mask.ipv4.l4_hdr_l 249 #define ip4_dest_mask mask.ipv4.ip_daddr 250 251 #define ip6_class_key key.ipv6.class_code 252 #define ip6_class_key_l key.ipv6.class_code_l 253 #define ip6_blade_id_key key.ipv6.blade_id 254 #define ip6_proto_key key.ipv6.protocol 255 #define ip6_l4_hdr_key key.ipv6.l4_hdr 256 #define ip6_l4_hdr_key_l key.ipv6.l4_hdr_l 257 258 #define ip6_class_mask mask.ipv6.class_code 259 #define ip6_class_mask_l mask.ipv6.class_code_l 260 #define ip6_blade_id_mask mask.ipv6.blade_id 261 #define ip6_proto_mask mask.ipv6.protocol 262 #define ip6_l4_hdr_mask mask.ipv6.l4_hdr 263 #define ip6_l4_hdr_mask_l mask.ipv6.l4_hdr_l 264 265 #define ether_class_key key.enet.class_code 266 #define ether_class_key_l key.enet.class_code_l 267 #define ether_blade_id_key key.enet.blade_id 268 #define ether_ethframe_key key.enet.eframe 269 270 #define ether_class_mask mask.enet.class_code 271 #define ether_class_mask_l mask.enet.class_code_l 272 #define ether_blade_id_mask mask.enet.blade_id 273 #define ether_ethframe_mask mask.enet.eframe 274 275 typedef struct _pfc_errlog { 276 uint32_t tcp_ctrl_drop; /* pfc_drop_log */ 277 uint32_t l2_addr_drop; 278 uint32_t class_code_drop; 279 uint32_t tcam_drop; 280 uint32_t vlan_drop; 281 282 uint32_t vlan_par_err_log; /* pfc_vlan_par_err_log */ 283 uint32_t tcam_par_err_log; /* pfc_tcam_par_err_log */ 284 } pfc_errlog_t, *p_pfc_errlog_t; 285 286 typedef struct _pfc_stats { 287 uint32_t pkt_drop; /* pfc_int_status */ 288 uint32_t tcam_parity_err; 289 uint32_t vlan_parity_err; 290 291 uint32_t bad_cs_count; /* pfc_bad_cs_counter */ 292 uint32_t drop_count; /* pfc_drop_counter */ 293 pfc_errlog_t errlog; 294 } hxge_pfc_stats_t, *p_hxge_pfc_stats_t; 295 296 typedef enum pfc_tcam_class { 297 TCAM_CLASS_INVALID = 0, 298 TCAM_CLASS_DUMMY = 1, 299 TCAM_CLASS_ETYPE_1 = 2, 300 TCAM_CLASS_ETYPE_2, 301 TCAM_CLASS_RESERVED_4, 302 TCAM_CLASS_RESERVED_5, 303 TCAM_CLASS_RESERVED_6, 304 TCAM_CLASS_RESERVED_7, 305 TCAM_CLASS_TCP_IPV4, 306 TCAM_CLASS_UDP_IPV4, 307 TCAM_CLASS_AH_ESP_IPV4, 308 TCAM_CLASS_SCTP_IPV4, 309 TCAM_CLASS_TCP_IPV6, 310 TCAM_CLASS_UDP_IPV6, 311 TCAM_CLASS_AH_ESP_IPV6, 312 TCAM_CLASS_SCTP_IPV6, 313 TCAM_CLASS_ARP, 314 TCAM_CLASS_RARP, 315 TCAM_CLASS_DUMMY_12, 316 TCAM_CLASS_DUMMY_13, 317 TCAM_CLASS_DUMMY_14, 318 TCAM_CLASS_DUMMY_15, 319 TCAM_CLASS_MAX 320 } tcam_class_t; 321 322 typedef struct _tcam_key_cfg_t { 323 boolean_t lookup_enable; 324 boolean_t discard; 325 } tcam_key_cfg_t; 326 327 typedef struct _hash_filter_t { 328 uint_t hash_ref_cnt; 329 uint16_t hash_filter_regs[NMCFILTER_REGS]; 330 uint32_t hash_bit_ref_cnt[NMCFILTER_BITS]; 331 } hash_filter_t, *p_hash_filter_t; 332 333 #define HXGE_ETHER_FLOWS (FLOW_ETHER_DHOST | FLOW_ETHER_SHOST | \ 334 FLOW_ETHER_TYPE) 335 #define HXGE_VLAN_FLOWS (FLOW_ETHER_TPID | FLOW_ETHER_TCI) 336 #define HXGE_ETHERNET_FLOWS (HXGE_ETHER_FLOWS | HXGE_VLAN_FLOWS) 337 #define HXGE_PORT_FLOWS (FLOW_ULP_PORT_REMOTE | FLOW_ULP_PORT_LOCAL) 338 #define HXGE_ADDR_FLOWS (FLOW_IP_REMOTE | FLOW_IP_LOCAL) 339 #define HXGE_IP_FLOWS (FLOW_IP_VERSION | FLOW_IP_PROTOCOL | \ 340 HXGE_PORT_FLOWS | HXGE_ADDR_FLOWS) 341 #define HXGE_SUPPORTED_FLOWS (HXGE_ETHERNET_FLOWS | HXGE_IP_FLOWS) 342 343 #define CLS_CODE_MASK 0x1f 344 #define BLADE_ID_MASK 0xf 345 #define PID_MASK 0xff 346 #define IP_PORT_MASK 0xffff 347 348 #define IP_ADDR_SA_MASK 0xFFFFFFFF 349 #define IP_ADDR_DA_MASK IP_ADDR_SA_MASK 350 #define L4PT_SPI_MASK IP_ADDR_SA_MASK 351 352 #define BLADE_ID_OFFSET 127 /* Last entry in HCR_REG */ 353 354 #ifdef __cplusplus 355 } 356 #endif 357 358 #endif /* !_HXGE_PFC_H */ 359