1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _HXGE_PEU_HW_H 27 #define _HXGE_PEU_HW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #define PIO_LDSV_BASE_ADDR 0X800000 34 #define PIO_BASE_ADDR 0X000000 35 #define PIO_LDMASK_BASE_ADDR 0XA00000 36 37 #define DEVICE_VENDOR_ID (PIO_BASE_ADDR + 0x0) 38 #define STATUS_COMMAND (PIO_BASE_ADDR + 0x4) 39 #define CLASSCODE_REV_ID (PIO_BASE_ADDR + 0x8) 40 #define BIST_HDRTYP_LATTMR_CASHLSZ (PIO_BASE_ADDR + 0xC) 41 #define PIO_BAR0 (PIO_BASE_ADDR + 0x10) 42 #define PIO_BAR1 (PIO_BASE_ADDR + 0x14) 43 #define MSIX_BAR0 (PIO_BASE_ADDR + 0x18) 44 #define MSIX_BAR1 (PIO_BASE_ADDR + 0x1C) 45 #define VIRT_BAR0 (PIO_BASE_ADDR + 0x20) 46 #define VIRT_BAR1 (PIO_BASE_ADDR + 0x24) 47 #define CIS_PTR (PIO_BASE_ADDR + 0x28) 48 #define SUB_VENDOR_ID (PIO_BASE_ADDR + 0x2C) 49 #define EXP_ROM_BAR (PIO_BASE_ADDR + 0x30) 50 #define CAP_PTR (PIO_BASE_ADDR + 0x34) 51 #define INT_LINE (PIO_BASE_ADDR + 0x3C) 52 #define PM_CAP (PIO_BASE_ADDR + 0x40) 53 #define PM_CTRL_STAT (PIO_BASE_ADDR + 0x44) 54 #define MSI_CAP (PIO_BASE_ADDR + 0x50) 55 #define MSI_LO_ADDR (PIO_BASE_ADDR + 0x54) 56 #define MSI_HI_ADDR (PIO_BASE_ADDR + 0x58) 57 #define MSI_DATA (PIO_BASE_ADDR + 0x5C) 58 #define MSI_MASK (PIO_BASE_ADDR + 0x60) 59 #define MSI_PEND (PIO_BASE_ADDR + 0x64) 60 #define MSIX_CAP (PIO_BASE_ADDR + 0x70) 61 #define MSIX_TAB_OFF (PIO_BASE_ADDR + 0x74) 62 #define MSIX_PBA_OFF (PIO_BASE_ADDR + 0x78) 63 #define PCIE_CAP (PIO_BASE_ADDR + 0x80) 64 #define DEV_CAP (PIO_BASE_ADDR + 0x84) 65 #define DEV_STAT_CTRL (PIO_BASE_ADDR + 0x88) 66 #define LNK_CAP (PIO_BASE_ADDR + 0x8C) 67 #define LNK_STAT_CTRL (PIO_BASE_ADDR + 0x90) 68 #define VEN_CAP_HDR (PIO_BASE_ADDR + 0x94) 69 #define VEN_CTRL (PIO_BASE_ADDR + 0x98) 70 #define VEN_PRT_HDR (PIO_BASE_ADDR + 0x9C) 71 #define ACKLAT_REPLAY (PIO_BASE_ADDR + 0xA0) 72 #define OTH_MSG (PIO_BASE_ADDR + 0xA4) 73 #define FORCE_LINK (PIO_BASE_ADDR + 0xA8) 74 #define ACK_FREQ (PIO_BASE_ADDR + 0xAC) 75 #define LINK_CTRL (PIO_BASE_ADDR + 0xB0) 76 #define LANE_SKEW (PIO_BASE_ADDR + 0xB4) 77 #define SYMBOL_NUM (PIO_BASE_ADDR + 0xB8) 78 #define SYMB_TIM_RADM_FLT1 (PIO_BASE_ADDR + 0xBC) 79 #define RADM_FLT2 (PIO_BASE_ADDR + 0xC0) 80 #define CASCADE_DEB_REG0 (PIO_BASE_ADDR + 0xC8) 81 #define CASCADE_DEB_REG1 (PIO_BASE_ADDR + 0xCC) 82 #define TXP_FC_CREDIT_STAT (PIO_BASE_ADDR + 0xD0) 83 #define TXNP_FC_CREDIT_STAT (PIO_BASE_ADDR + 0xD4) 84 #define TXCPL_FC_CREDIT_STAT (PIO_BASE_ADDR + 0xD8) 85 #define QUEUE_STAT (PIO_BASE_ADDR + 0xDC) 86 #define GBT_DEBUG0 (PIO_BASE_ADDR + 0xE0) 87 #define GBT_DEBUG1 (PIO_BASE_ADDR + 0xE4) 88 #define GBT_DEBUG2 (PIO_BASE_ADDR + 0xE8) 89 #define GBT_DEBUG3 (PIO_BASE_ADDR + 0xEC) 90 #define PIPE_DEBUG0 (PIO_BASE_ADDR + 0xF0) 91 #define PIPE_DEBUG1 (PIO_BASE_ADDR + 0xF4) 92 #define PIPE_DEBUG2 (PIO_BASE_ADDR + 0xF8) 93 #define PIPE_DEBUG3 (PIO_BASE_ADDR + 0xFC) 94 #define PCIE_ENH_CAP_HDR (PIO_BASE_ADDR + 0x100) 95 #define UNC_ERR_STAT (PIO_BASE_ADDR + 0x104) 96 #define UNC_ERR_MASK (PIO_BASE_ADDR + 0x108) 97 #define UNC_ERR_SVRTY (PIO_BASE_ADDR + 0x10C) 98 #define CORR_ERR_STAT (PIO_BASE_ADDR + 0x110) 99 #define CORR_ERR_MASK (PIO_BASE_ADDR + 0x114) 100 #define ADV_CAP_CTRL (PIO_BASE_ADDR + 0x118) 101 #define HDR_LOG0 (PIO_BASE_ADDR + 0x11C) 102 #define HDR_LOG1 (PIO_BASE_ADDR + 0x120) 103 #define HDR_LOG2 (PIO_BASE_ADDR + 0x124) 104 #define HDR_LOG3 (PIO_BASE_ADDR + 0x128) 105 #define PIPE_RX_TX_CONTROL (PIO_BASE_ADDR + 0x1000) 106 #define PIPE_RX_TX_STATUS (PIO_BASE_ADDR + 0x1004) 107 #define PIPE_RX_TX_PWR_CNTL (PIO_BASE_ADDR + 0x1008) 108 #define PIPE_RX_TX_PARAM (PIO_BASE_ADDR + 0x1010) 109 #define PIPE_RX_TX_CLOCK (PIO_BASE_ADDR + 0x1014) 110 #define PIPE_GLUE_CNTL0 (PIO_BASE_ADDR + 0x1018) 111 #define PIPE_GLUE_CNTL1 (PIO_BASE_ADDR + 0x101C) 112 #define HCR_REG (PIO_BASE_ADDR + 0x2000) 113 #define BLOCK_RESET (PIO_BASE_ADDR + 0x8000) 114 #define TIMEOUT_CFG (PIO_BASE_ADDR + 0x8004) 115 #define HEART_CFG (PIO_BASE_ADDR + 0x8008) 116 #define HEART_TIMER (PIO_BASE_ADDR + 0x800C) 117 #define CIP_GP_CTRL (PIO_BASE_ADDR + 0x8010) 118 #define CIP_STATUS (PIO_BASE_ADDR + 0x8014) 119 #define CIP_LINK_STAT (PIO_BASE_ADDR + 0x801C) 120 #define EPC_STAT (PIO_BASE_ADDR + 0x8020) 121 #define EPC_DATA (PIO_BASE_ADDR + 0x8024) 122 #define SPC_STAT (PIO_BASE_ADDR + 0x8030) 123 #define HOST2SPI_INDACC_ADDR (PIO_BASE_ADDR + 0x8050) 124 #define HOST2SPI_INDACC_CTRL (PIO_BASE_ADDR + 0x8054) 125 #define HOST2SPI_INDACC_DATA (PIO_BASE_ADDR + 0x8058) 126 #define BT_CTRL0 (PIO_BASE_ADDR + 0x8080) 127 #define BT_DATA0 (PIO_BASE_ADDR + 0x8084) 128 #define BT_INTMASK0 (PIO_BASE_ADDR + 0x8088) 129 #define BT_CTRL1 (PIO_BASE_ADDR + 0x8090) 130 #define BT_DATA1 (PIO_BASE_ADDR + 0x8094) 131 #define BT_INTMASK1 (PIO_BASE_ADDR + 0x8098) 132 #define BT_CTRL2 (PIO_BASE_ADDR + 0x80A0) 133 #define BT_DATA2 (PIO_BASE_ADDR + 0x80A4) 134 #define BT_INTMASK2 (PIO_BASE_ADDR + 0x80A8) 135 #define BT_CTRL3 (PIO_BASE_ADDR + 0x80B0) 136 #define BT_DATA3 (PIO_BASE_ADDR + 0x80B4) 137 #define BT_INTMASK3 (PIO_BASE_ADDR + 0x80B8) 138 #define DEBUG_SEL (PIO_BASE_ADDR + 0x80C0) 139 #define INDACC_MEM0_CTRL (PIO_BASE_ADDR + 0x80C4) 140 #define INDACC_MEM0_DATA0 (PIO_BASE_ADDR + 0x80C8) 141 #define INDACC_MEM0_DATA1 (PIO_BASE_ADDR + 0x80CC) 142 #define INDACC_MEM0_DATA2 (PIO_BASE_ADDR + 0x80D0) 143 #define INDACC_MEM0_DATA3 (PIO_BASE_ADDR + 0x80D4) 144 #define INDACC_MEM0_PRTY (PIO_BASE_ADDR + 0x80D8) 145 #define INDACC_MEM1_CTRL (PIO_BASE_ADDR + 0x80DC) 146 #define INDACC_MEM1_DATA0 (PIO_BASE_ADDR + 0x80E0) 147 #define INDACC_MEM1_DATA1 (PIO_BASE_ADDR + 0x80E4) 148 #define INDACC_MEM1_DATA2 (PIO_BASE_ADDR + 0x80E8) 149 #define INDACC_MEM1_DATA3 (PIO_BASE_ADDR + 0x80EC) 150 #define INDACC_MEM1_PRTY (PIO_BASE_ADDR + 0x80F0) 151 #define PHY_DEBUG_TRAINING_VEC (PIO_BASE_ADDR + 0x80F4) 152 #define PEU_DEBUG_TRAINING_VEC (PIO_BASE_ADDR + 0x80F8) 153 #define PIPE_CFG0 (PIO_BASE_ADDR + 0x8120) 154 #define PIPE_CFG1 (PIO_BASE_ADDR + 0x8124) 155 #define CIP_BAR_MASK_CFG (PIO_BASE_ADDR + 0x8134) 156 #define CIP_BAR_MASK (PIO_BASE_ADDR + 0x8138) 157 #define CIP_LDSV0_STAT (PIO_BASE_ADDR + 0x8140) 158 #define CIP_LDSV1_STAT (PIO_BASE_ADDR + 0x8144) 159 #define PEU_INTR_STAT (PIO_BASE_ADDR + 0x8148) 160 #define PEU_INTR_MASK (PIO_BASE_ADDR + 0x814C) 161 #define PEU_INTR_STAT_MIRROR (PIO_BASE_ADDR + 0x8150) 162 #define CPL_HDRQ_PERR_LOC (PIO_BASE_ADDR + 0x8154) 163 #define CPL_DATAQ_PERR_LOC (PIO_BASE_ADDR + 0x8158) 164 #define RETR_PERR_LOC (PIO_BASE_ADDR + 0x815C) 165 #define RETR_SOT_PERR_LOC (PIO_BASE_ADDR + 0x8160) 166 #define P_HDRQ_PERR_LOC (PIO_BASE_ADDR + 0x8164) 167 #define P_DATAQ_PERR_LOC (PIO_BASE_ADDR + 0x8168) 168 #define NP_HDRQ_PERR_LOC (PIO_BASE_ADDR + 0x816C) 169 #define NP_DATAQ_PERR_LOC (PIO_BASE_ADDR + 0x8170) 170 #define MSIX_PERR_LOC (PIO_BASE_ADDR + 0x8174) 171 #define HCR_PERR_LOC (PIO_BASE_ADDR + 0x8178) 172 #define TDC_PIOACC_ERR_LOG (PIO_BASE_ADDR + 0x8180) 173 #define RDC_PIOACC_ERR_LOG (PIO_BASE_ADDR + 0x8184) 174 #define PFC_PIOACC_ERR_LOG (PIO_BASE_ADDR + 0x8188) 175 #define VMAC_PIOACC_ERR_LOG (PIO_BASE_ADDR + 0x818C) 176 #define LD_GRP_CTRL (PIO_BASE_ADDR + 0x8300) 177 #define DEV_ERR_STAT (PIO_BASE_ADDR + 0x8380) 178 #define DEV_ERR_MASK (PIO_BASE_ADDR + 0x8384) 179 #define LD_INTR_TIM_RES (PIO_BASE_ADDR + 0x8390) 180 #define LDSV0 (PIO_LDSV_BASE_ADDR + 0x0) 181 #define LDSV1 (PIO_LDSV_BASE_ADDR + 0x4) 182 #define LD_INTR_MASK (PIO_LDMASK_BASE_ADDR + 0x0) 183 #define LD_INTR_MGMT (PIO_LDMASK_BASE_ADDR + 0x4) 184 #define SID (PIO_LDMASK_BASE_ADDR + 0x8) 185 186 187 /* 188 * Register: DeviceVendorId 189 * Device ID and Vendor ID 190 * Description: Device ID/Vendor ID 191 * Fields: 192 * Device ID Register: dbi writeable 193 * Vendor ID Register (Sun Microsystem): dbi writeable 194 */ 195 typedef union { 196 uint32_t value; 197 struct { 198 #if defined(_BIG_ENDIAN) 199 uint32_t device_id:16; 200 uint32_t vendor_id:16; 201 #else 202 uint32_t vendor_id:16; 203 uint32_t device_id:16; 204 #endif 205 } bits; 206 } device_vendor_id_t; 207 208 209 /* 210 * Register: StatusCommand 211 * Status and Command 212 * Description: Status/Command 213 * Fields: 214 * The device detected a parity error. The device detects 215 * Poisoned TLP received regardless of Command Register Parity 216 * Error Enable/Response bit. 217 * The device signaled a system error with SERR#. The device 218 * detects a UE, is about to send a F/NF error message; and if 219 * the Command Register SERR# enable is set. 220 * A transaction initiated by this device was terminated due to a 221 * Master Abort (i.e. Unsupported Request Completion Status was 222 * received). 223 * A transaction initiated by this device was terminated due to a 224 * Target Abort (i.e. Completer Abort Completion Status was 225 * received). 226 * Set when Completer Abort Completion Status is sent back to the 227 * RC. The request violated hydra's programming rules. 228 * The slowest DEVSEL# timing for this target device (N/A in 229 * PCIE) 230 * Master Data Parity Error - set if all the following conditions 231 * are true: received a poisoned TLP header or sending a poisoned 232 * write request; and the parity error response bit in the 233 * command register is set. 234 * Fast Back-to-Back Capable (N/A in PCIE) 235 * 66 MHz Capable (N/A in PCIE) 236 * Capabilities List - presence of extended capability item. 237 * INTx Status 238 * INTx Assertion Disable 239 * Fast Back-to-Back Enable (N/A in PCIE) 240 * This device can drive the SERR# line. 241 * IDSEL Stepping/Wait Cycle Control (N/A in PCIE) 242 * This device can drive the PERR# line. 243 * VGA Palette Snoop (N/A in PCIE) 244 * The device can issue Memory Write-and-Invalidate commands (N/A 245 * in PCIE) 246 * This device monitors for PCI Special Cycles (N/A in PCIE) 247 * This device's bus master capability is enabled. 248 * This device responds to PCI memory accesses. 249 * This device responds to PCI IO accesses (No I/O space used in 250 * Hydra) 251 */ 252 typedef union { 253 uint32_t value; 254 struct { 255 #if defined(_BIG_ENDIAN) 256 uint32_t det_par_err:1; 257 uint32_t sig_serr:1; 258 uint32_t rcv_mstr_abrt:1; 259 uint32_t rcv_tgt_abrt:1; 260 uint32_t sig_tgt_abrt:1; 261 uint32_t devsel_timing:2; 262 uint32_t mstr_dpe:1; 263 uint32_t fast_b2b_cap:1; 264 uint32_t rsrvd:1; 265 uint32_t mhz_cap:1; 266 uint32_t cap_list:1; 267 uint32_t intx_stat:1; 268 uint32_t rsrvd1:3; 269 uint32_t rsrvd2:5; 270 uint32_t intx_dis:1; 271 uint32_t fast_b2b_en:1; 272 uint32_t serr_en:1; 273 uint32_t idsel_step:1; 274 uint32_t par_err_en:1; 275 uint32_t vga_snoop:1; 276 uint32_t mwi_en:1; 277 uint32_t special_cycle:1; 278 uint32_t bm_en:1; 279 uint32_t mem_sp_en:1; 280 uint32_t io_sp_en:1; 281 #else 282 uint32_t io_sp_en:1; 283 uint32_t mem_sp_en:1; 284 uint32_t bm_en:1; 285 uint32_t special_cycle:1; 286 uint32_t mwi_en:1; 287 uint32_t vga_snoop:1; 288 uint32_t par_err_en:1; 289 uint32_t idsel_step:1; 290 uint32_t serr_en:1; 291 uint32_t fast_b2b_en:1; 292 uint32_t intx_dis:1; 293 uint32_t rsrvd2:5; 294 uint32_t rsrvd1:3; 295 uint32_t intx_stat:1; 296 uint32_t cap_list:1; 297 uint32_t mhz_cap:1; 298 uint32_t rsrvd:1; 299 uint32_t fast_b2b_cap:1; 300 uint32_t mstr_dpe:1; 301 uint32_t devsel_timing:2; 302 uint32_t sig_tgt_abrt:1; 303 uint32_t rcv_tgt_abrt:1; 304 uint32_t rcv_mstr_abrt:1; 305 uint32_t sig_serr:1; 306 uint32_t det_par_err:1; 307 #endif 308 } bits; 309 } status_command_t; 310 311 312 /* 313 * Register: ClasscodeRevId 314 * Class Code, and Revision ID 315 * Description: Class Code/Revision ID 316 * Fields: 317 * Base Class (Network Controller): dbi writeable 318 * Sub Class (Ethernet Controller): dbi writeable 319 * Programming Interface: dbi writeable 320 * Revision ID: dbi writeable 321 */ 322 typedef union { 323 uint32_t value; 324 struct { 325 #if defined(_BIG_ENDIAN) 326 uint32_t base_class:8; 327 uint32_t sub_class:8; 328 uint32_t prog_if:8; 329 uint32_t rev_id:8; 330 #else 331 uint32_t rev_id:8; 332 uint32_t prog_if:8; 333 uint32_t sub_class:8; 334 uint32_t base_class:8; 335 #endif 336 } bits; 337 } classcode_rev_id_t; 338 339 340 /* 341 * Register: BistHdrtypLattmrCashlsz 342 * BIST, Header Type, Latency Timer, and Cache Line Size 343 * Description: BIST, Latency Timer etc 344 * Fields: 345 * BIST is not supported. Header Type Fields 346 * Multi-Function Device: dbi writeable 347 * Configuration Header Format. 0 = Type 0. 348 * Master Latency Timer. (N/A in PCIE) 349 * Cache line size for legacy compatibility (N/A in PCIE) 350 */ 351 typedef union { 352 uint32_t value; 353 struct { 354 #if defined(_BIG_ENDIAN) 355 uint32_t value:8; 356 uint32_t mult_func_dev:1; 357 uint32_t cfg_hdr_fmt:7; 358 uint32_t timer:8; 359 uint32_t cache_line_sz:8; 360 #else 361 uint32_t cache_line_sz:8; 362 uint32_t timer:8; 363 uint32_t cfg_hdr_fmt:7; 364 uint32_t mult_func_dev:1; 365 uint32_t value:8; 366 #endif 367 } bits; 368 } bist_hdrtyp_lattmr_cashlsz_t; 369 370 371 /* 372 * Register: PioBar0 373 * PIO BAR0 374 * Description: PIO BAR0 - For Hydra PIO space PIO BAR1 & PIO BAR0 375 * are together configured as a 64b BAR register (Synopsys core 376 * implementation dependent) where PIO BAR1 handles the upper address 377 * bits and PIO BAR0 handles the lower address bits. 378 * Fields: 379 * Base Address Relocation : indirect dbi writeable via bar0Mask 380 * register in EP core 381 * Base Address for PIO (16MB space) : indirect dbi writeable via 382 * bar0Mask register in EP core 383 * Prefetchable if memory BAR (PIOs not prefetchable): dbi 384 * writeable 385 * If memory BAR, then 32 or 64 bit BAR (00 = 32 bit, 10 = 64 386 * bit): dbi writeable 387 * I/O or Memory space indicator (0 = memory BAR): dbi writeable 388 */ 389 typedef union { 390 uint32_t value; 391 struct { 392 #if defined(_BIG_ENDIAN) 393 uint32_t base_addr_rel_lo:8; 394 uint32_t base_addr:20; 395 uint32_t pftch:1; 396 uint32_t type:2; 397 uint32_t mem_sp_ind:1; 398 #else 399 uint32_t mem_sp_ind:1; 400 uint32_t type:2; 401 uint32_t pftch:1; 402 uint32_t base_addr:20; 403 uint32_t base_addr_rel_lo:8; 404 #endif 405 } bits; 406 } pio_bar0_t; 407 408 409 /* 410 * Register: PioBar1 411 * PIO BAR1 412 * Description: PIO BAR1 413 * Fields: 414 * Base Address Relocation : indirect dbi writeable via bar0Mask 415 * register in EP core 416 */ 417 typedef union { 418 uint32_t value; 419 struct { 420 #if defined(_BIG_ENDIAN) 421 uint32_t base_addr_rel_hi:32; 422 #else 423 uint32_t base_addr_rel_hi:32; 424 #endif 425 } bits; 426 } pio_bar1_t; 427 428 429 /* 430 * Register: MsixBar0 431 * MSIX BAR0 432 * Description: MSIX BAR0 - For MSI-X Tables and PBA MSIX BAR1 & MSIX 433 * BAR0 are together configured as a 64b BAR register (Synopsys core 434 * implementation dependent) where MSIX BAR1 handles the upper 435 * address bits and MSIX BAR0 handles the lower address bits. 436 * Fields: 437 * Base Address Relocation : indirect dbi writeable via bar2Mask 438 * register in EP core 439 * Base Address for MSIX (16KB space) : indirect dbi writeable 440 * via bar2Mask register in EP core 441 * Prefetchable if memory BAR (Not prefetchable) : dbi writeable 442 * If memory BAR, then 32 or 64 bit BAR (00 = 32 bit, 10 = 64 443 * bit): dbi writeable 444 * I/O or Memory space indicator (0 = memory BAR) : dbi writeable 445 */ 446 typedef union { 447 uint32_t value; 448 struct { 449 #if defined(_BIG_ENDIAN) 450 uint32_t base_addr_rel_lo:18; 451 uint32_t base_addr:10; 452 uint32_t pftch:1; 453 uint32_t type:2; 454 uint32_t mem_sp_ind:1; 455 #else 456 uint32_t mem_sp_ind:1; 457 uint32_t type:2; 458 uint32_t pftch:1; 459 uint32_t base_addr:10; 460 uint32_t base_addr_rel_lo:18; 461 #endif 462 } bits; 463 } msix_bar0_t; 464 465 466 /* 467 * Register: MsixBar1 468 * MSIX BAR1 469 * Description: MSIX BAR1 470 * Fields: 471 * Base Address Relocation : indirect dbi writeable via bar2Mask 472 * register in EP core 473 */ 474 typedef union { 475 uint32_t value; 476 struct { 477 #if defined(_BIG_ENDIAN) 478 uint32_t base_addr_rel_hi:32; 479 #else 480 uint32_t base_addr_rel_hi:32; 481 #endif 482 } bits; 483 } msix_bar1_t; 484 485 486 /* 487 * Register: VirtBar0 488 * Virtualization BAR0 489 * Description: Virtualization BAR0 - Previously for Hydra 490 * Virtualization space This bar is no longer enabled and is not dbi 491 * writeable. VIRT BAR1 & VIRT BAR0 could be configured as a 64b BAR 492 * register (Synopsys core implementation dependent), but this is not 493 * used in hydra. 494 * Fields: 495 * Base Address Relocation 496 * Base Address for Virtualization (64KB space) 497 * Prefetchable if memory BAR (Not prefetchable) 498 * If memory BAR, then 32 or 64 bit BAR (00 = 32 bit, 10 = 64 499 * bit) 500 * I/O or Memory space indicator (0 = memory BAR) 501 */ 502 typedef union { 503 uint32_t value; 504 struct { 505 #if defined(_BIG_ENDIAN) 506 uint32_t base_addr_rel_lo:17; 507 uint32_t base_addr:11; 508 uint32_t pftch:1; 509 uint32_t type:2; 510 uint32_t mem_sp_ind:1; 511 #else 512 uint32_t mem_sp_ind:1; 513 uint32_t type:2; 514 uint32_t pftch:1; 515 uint32_t base_addr:11; 516 uint32_t base_addr_rel_lo:17; 517 #endif 518 } bits; 519 } virt_bar0_t; 520 521 522 /* 523 * Register: VirtBar1 524 * Virtualization BAR1 525 * Description: Previously for Virtualization BAR1 This bar is no 526 * longer enabled and is not dbi writeable. 527 * Fields: 528 * Base Address Relocation 529 */ 530 typedef union { 531 uint32_t value; 532 struct { 533 #if defined(_BIG_ENDIAN) 534 uint32_t base_addr_rel_hi:32; 535 #else 536 uint32_t base_addr_rel_hi:32; 537 #endif 538 } bits; 539 } virt_bar1_t; 540 541 542 /* 543 * Register: CisPtr 544 * CardBus CIS Pointer 545 * Description: CardBus CIS Pointer 546 * Fields: 547 * CardBus CIS Pointer: dbi writeable 548 */ 549 typedef union { 550 uint32_t value; 551 struct { 552 #if defined(_BIG_ENDIAN) 553 uint32_t cis_ptr:32; 554 #else 555 uint32_t cis_ptr:32; 556 #endif 557 } bits; 558 } cis_ptr_t; 559 560 561 /* 562 * Register: SubVendorId 563 * Subsystem ID and Vendor ID 564 * Description: Subsystem ID and Vendor ID 565 * Fields: 566 * Subsystem ID as assigned by PCI-SIG : dbi writeable 567 * Subsystem Vendor ID as assigned by PCI-SIG : dbi writeable 568 */ 569 typedef union { 570 uint32_t value; 571 struct { 572 #if defined(_BIG_ENDIAN) 573 uint32_t dev_id:16; 574 uint32_t vendor_id:16; 575 #else 576 uint32_t vendor_id:16; 577 uint32_t dev_id:16; 578 #endif 579 } bits; 580 } sub_vendor_id_t; 581 582 583 /* 584 * Register: ExpRomBar 585 * Expansion ROM BAR 586 * Description: Expansion ROM BAR - For Hydra EEPROM space 587 * Fields: 588 * Base Address Relocatable : indirect dbi writeable via 589 * romBarMask register in EP core 590 * Base Address for ROM (2MB) : indirect dbi writeable via 591 * romBarMask register in EP core 592 * ROM Enable: dbi writeable 593 */ 594 typedef union { 595 uint32_t value; 596 struct { 597 #if defined(_BIG_ENDIAN) 598 uint32_t base_addr_rel:11; 599 uint32_t base_addr:10; 600 uint32_t rsrvd:10; 601 uint32_t rom_en:1; 602 #else 603 uint32_t rom_en:1; 604 uint32_t rsrvd:10; 605 uint32_t base_addr:10; 606 uint32_t base_addr_rel:11; 607 #endif 608 } bits; 609 } exp_rom_bar_t; 610 611 612 /* 613 * Register: CapPtr 614 * Capabilities Pointer 615 * Description: Capabilities Pointer 616 * Fields: 617 * Pointer to PM Capability structure : dbi writeable 618 */ 619 typedef union { 620 uint32_t value; 621 struct { 622 #if defined(_BIG_ENDIAN) 623 uint32_t rsrvd:24; 624 uint32_t pm_ptr:8; 625 #else 626 uint32_t pm_ptr:8; 627 uint32_t rsrvd:24; 628 #endif 629 } bits; 630 } cap_ptr_t; 631 632 633 /* 634 * Register: IntLine 635 * Interrupt Line 636 * Description: Interrupt Line 637 * Fields: 638 * Max Latency (N/A in PCIE) 639 * Minimum Grant (N/A in PCIE) 640 * Interrupt pin: dbi writeable 641 * Interrupt Line 642 */ 643 typedef union { 644 uint32_t value; 645 struct { 646 #if defined(_BIG_ENDIAN) 647 uint32_t max_lat:8; 648 uint32_t min_gnt:8; 649 uint32_t int_pin:8; 650 uint32_t int_line:8; 651 #else 652 uint32_t int_line:8; 653 uint32_t int_pin:8; 654 uint32_t min_gnt:8; 655 uint32_t max_lat:8; 656 #endif 657 } bits; 658 } int_line_t; 659 660 661 /* 662 * Register: PmCap 663 * Power Management Capability 664 * Description: Power Management Capability 665 * Fields: 666 * PME Support (N/A in Hydra): dbi writeable 667 * D2 Support (N/A in Hydra): dbi writeable 668 * D1 Support (N/A in Hydra): dbi writeable 669 * Aux Current (N/A in Hydra): dbi writeable 670 * Device Specific Initialization: dbi writeable 671 * PME Clock (N/A in PCIE) 672 * PM Spec Version: dbi writeable 673 * Next Capability Pointer: dbi writeable 674 * Power Management Capability ID: dbi writeable 675 */ 676 typedef union { 677 uint32_t value; 678 struct { 679 #if defined(_BIG_ENDIAN) 680 uint32_t pme_supt:5; 681 uint32_t d2_supt:1; 682 uint32_t d1_supt:1; 683 uint32_t aux_curr:3; 684 uint32_t dev_spec_init:1; 685 uint32_t rsrvd:1; 686 uint32_t pme_clk:1; 687 uint32_t pm_ver:3; 688 uint32_t nxt_cap_ptr:8; 689 uint32_t pm_id:8; 690 #else 691 uint32_t pm_id:8; 692 uint32_t nxt_cap_ptr:8; 693 uint32_t pm_ver:3; 694 uint32_t pme_clk:1; 695 uint32_t rsrvd:1; 696 uint32_t dev_spec_init:1; 697 uint32_t aux_curr:3; 698 uint32_t d1_supt:1; 699 uint32_t d2_supt:1; 700 uint32_t pme_supt:5; 701 #endif 702 } bits; 703 } pm_cap_t; 704 705 706 /* 707 * Register: PmCtrlStat 708 * Power Management Control and Status 709 * Description: Power Management Control and Status 710 * Fields: 711 * Data for additional info (N/A) 712 * Bus Power and Clock Control Enable (N/A in PCIE) 713 * B2/B3 Support (N/A in PCIE) 714 * Indicates if PME event occured 715 * Data Scale (N/A) 716 * Data Select (N/A) 717 * PME Enable (Sticky) 718 * Power State 719 */ 720 typedef union { 721 uint32_t value; 722 struct { 723 #if defined(_BIG_ENDIAN) 724 uint32_t pwr_data:8; 725 uint32_t pwr_clk_en:1; 726 uint32_t b2_b3_supt:1; 727 uint32_t rsrvd:6; 728 uint32_t pme_stat:1; 729 uint32_t data_scale:2; 730 uint32_t data_sel:4; 731 uint32_t pme_en:1; 732 uint32_t rsrvd1:6; 733 uint32_t pwr_st:2; 734 #else 735 uint32_t pwr_st:2; 736 uint32_t rsrvd1:6; 737 uint32_t pme_en:1; 738 uint32_t data_sel:4; 739 uint32_t data_scale:2; 740 uint32_t pme_stat:1; 741 uint32_t rsrvd:6; 742 uint32_t b2_b3_supt:1; 743 uint32_t pwr_clk_en:1; 744 uint32_t pwr_data:8; 745 #endif 746 } bits; 747 } pm_ctrl_stat_t; 748 749 750 /* 751 * Register: MsiCap 752 * MSI Capability 753 * Description: MSI Capability 754 * Fields: 755 * Mask and Pending bits available 756 * 64-bit Address Capable 757 * Multiple Messages Enabled 758 * Multiple Message Capable (32 messages = 0x5) 759 * MSI Enabled (if enabled, INTx must be diabled) 760 * Next Capability Pointer: dbi writeable 761 * MSI Capability ID 762 */ 763 typedef union { 764 uint32_t value; 765 struct { 766 #if defined(_BIG_ENDIAN) 767 uint32_t rsrvd:7; 768 uint32_t vect_mask:1; 769 uint32_t msi64_en:1; 770 uint32_t mult_msg_en:3; 771 uint32_t mult_msg_cap:3; 772 uint32_t msi_en:1; 773 uint32_t nxt_cap_ptr:8; 774 uint32_t msi_cap_id:8; 775 #else 776 uint32_t msi_cap_id:8; 777 uint32_t nxt_cap_ptr:8; 778 uint32_t msi_en:1; 779 uint32_t mult_msg_cap:3; 780 uint32_t mult_msg_en:3; 781 uint32_t msi64_en:1; 782 uint32_t vect_mask:1; 783 uint32_t rsrvd:7; 784 #endif 785 } bits; 786 } msi_cap_t; 787 788 789 /* 790 * Register: MsiLoAddr 791 * MSI Low Address 792 * Description: MSI Low Address 793 * Fields: 794 * Lower 32 bit Address 795 */ 796 typedef union { 797 uint32_t value; 798 struct { 799 #if defined(_BIG_ENDIAN) 800 uint32_t lo_addr:30; 801 uint32_t rsrvd:2; 802 #else 803 uint32_t rsrvd:2; 804 uint32_t lo_addr:30; 805 #endif 806 } bits; 807 } msi_lo_addr_t; 808 809 810 /* 811 * Register: MsiHiAddr 812 * MSI High Address 813 * Description: MSI High Address 814 * Fields: 815 * Upper 32 bit Address (only if msi64En = 1) 816 */ 817 typedef union { 818 uint32_t value; 819 struct { 820 #if defined(_BIG_ENDIAN) 821 uint32_t hi_addr:32; 822 #else 823 uint32_t hi_addr:32; 824 #endif 825 } bits; 826 } msi_hi_addr_t; 827 828 829 /* 830 * Register: MsiData 831 * MSI Data 832 * Description: MSI Data 833 * Fields: 834 * MSI Data. Depending on the value for multMsgEn in the MSI 835 * Capability Register which determines the number of allocated 836 * vectors, bits [4:0] may be replaced with msiVector[4:0] bits 837 * to generate up to 32 MSI messages. # allocated vectors Actual 838 * messageData[4:0] ------------------- ------------------------ 839 * 1 DATA[4:0] (no replacement) 2 {DATA[4:1], msiVector[0]} 4 840 * {DATA[4:2], msiVector[1:0]} 8 {DATA[4:3], msiVector[2:0]} 16 841 * {DATA[4], msiVector[3:0]} 32 msiVector[4:0] (full replacement) 842 */ 843 typedef union { 844 uint32_t value; 845 struct { 846 #if defined(_BIG_ENDIAN) 847 uint32_t rsrvd:16; 848 uint32_t data:16; 849 #else 850 uint32_t data:16; 851 uint32_t rsrvd:16; 852 #endif 853 } bits; 854 } msi_data_t; 855 856 857 /* 858 * Register: MsiMask 859 * MSI Mask 860 * Description: MSI Mask 861 * Fields: 862 * per vector MSI Mask bits 863 */ 864 typedef union { 865 uint32_t value; 866 struct { 867 #if defined(_BIG_ENDIAN) 868 uint32_t mask:32; 869 #else 870 uint32_t mask:32; 871 #endif 872 } bits; 873 } msi_mask_t; 874 875 876 /* 877 * Register: MsiPend 878 * MSI Pending 879 * Description: MSI Pending 880 * Fields: 881 * per vector MSI Pending bits 882 */ 883 typedef union { 884 uint32_t value; 885 struct { 886 #if defined(_BIG_ENDIAN) 887 uint32_t pend:32; 888 #else 889 uint32_t pend:32; 890 #endif 891 } bits; 892 } msi_pend_t; 893 894 895 /* 896 * Register: MsixCap 897 * MSIX Capability 898 * Description: MSIX Capability 899 * Fields: 900 * MSIX Enable (if enabled, MSI and INTx must be disabled) 901 * Function Mask (1 = all vectors masked regardless of per vector 902 * mask, 0 = each vector's mask 903 * Table Size (0x1F = 32 entries): dbi writeable 904 * Next Capability Pointer: dbi writeable 905 * MSIX Capability ID 906 */ 907 typedef union { 908 uint32_t value; 909 struct { 910 #if defined(_BIG_ENDIAN) 911 uint32_t msix_en:1; 912 uint32_t func_mask:1; 913 uint32_t rsrvd:3; 914 uint32_t tab_sz:11; 915 uint32_t nxt_cap_ptr:8; 916 uint32_t msix_cap_id:8; 917 #else 918 uint32_t msix_cap_id:8; 919 uint32_t nxt_cap_ptr:8; 920 uint32_t tab_sz:11; 921 uint32_t rsrvd:3; 922 uint32_t func_mask:1; 923 uint32_t msix_en:1; 924 #endif 925 } bits; 926 } msix_cap_t; 927 928 929 /* 930 * Register: MsixTabOff 931 * MSIX Table Offset 932 * Description: MSIX Table Offset 933 * Fields: 934 * Table Offset (Base address of MSIX Table = msixTabBir.BAR + 935 * msixTabOff) : dbi writeable 936 * Table BAR Indicator (0x2 = BAR2 at loc 0x18) : dbi writeable 937 */ 938 typedef union { 939 uint32_t value; 940 struct { 941 #if defined(_BIG_ENDIAN) 942 uint32_t msix_tab_off:29; 943 uint32_t msix_tab_bir:3; 944 #else 945 uint32_t msix_tab_bir:3; 946 uint32_t msix_tab_off:29; 947 #endif 948 } bits; 949 } msix_tab_off_t; 950 951 952 /* 953 * Register: MsixPbaOff 954 * MSIX PBA Offset 955 * Description: MSIX PBA Offset 956 * Fields: 957 * Pending Bit Array (PBA) Offset (Base address of MSIX Table = 958 * msixTabBir.BAR + msixPbaOff); msixPbaOff is quad-aligned, i.e. 959 * starts at 0x2000 (half-way in MSI-X bar space. : dbi writeable 960 * Pending Bit Array (PBA) BAR Indicator (0x2 = BAR2 at loc 0x18) 961 * : dbi writeable 962 */ 963 typedef union { 964 uint32_t value; 965 struct { 966 #if defined(_BIG_ENDIAN) 967 uint32_t msix_pba_off:29; 968 uint32_t msix_pba_bir:3; 969 #else 970 uint32_t msix_pba_bir:3; 971 uint32_t msix_pba_off:29; 972 #endif 973 } bits; 974 } msix_pba_off_t; 975 976 977 /* 978 * Register: PcieCap 979 * PCIE Capability 980 * Description: PCIE Capability 981 * Fields: 982 * Interrupt Message Number (updated by HW) 983 * Slot Implemented (Endpoint must be 0) 984 * PCIE Express Device Port Type (Endpoint) 985 * PCIE Express Capability Version 986 * Next Capability Pointer: dbi writeable 987 * PCI Express Capability ID 988 */ 989 typedef union { 990 uint32_t value; 991 struct { 992 #if defined(_BIG_ENDIAN) 993 uint32_t rsrvd:2; 994 uint32_t int_msg_num:5; 995 uint32_t pcie_slt_imp:1; 996 uint32_t pcie_dev_type:4; 997 uint32_t pcie_cap_ver:4; 998 uint32_t nxt_cap_ptr:8; 999 uint32_t pcie_cap_id:8; 1000 #else 1001 uint32_t pcie_cap_id:8; 1002 uint32_t nxt_cap_ptr:8; 1003 uint32_t pcie_cap_ver:4; 1004 uint32_t pcie_dev_type:4; 1005 uint32_t pcie_slt_imp:1; 1006 uint32_t int_msg_num:5; 1007 uint32_t rsrvd:2; 1008 #endif 1009 } bits; 1010 } pcie_cap_t; 1011 1012 1013 /* 1014 * Register: DevCap 1015 * Device Capability 1016 * Description: Device Capability 1017 * Fields: 1018 * Slot Power Limit Scale (Msg from RC) Hydra can capture 1019 * Received setSlotPowerLimit message; values in this field are 1020 * ignored as no power scaling is possible. 1021 * Slot Power Limit Value (Msg from RC) Hydra can capture 1022 * Received setSlotPowerLimit message; values in this field are 1023 * ignored as no power scaling is possible. 1024 * Introduced in PCIe 1.1 specification. : dbi writeable 1025 * L1 Acceptable Latency (4 - 8 us) : dbi writeable 1026 * LOs Acceptable Latency (2 - 4 us) : dbi writeable 1027 * Extended Tag Field Support (N/A) : dbi writeable 1028 * Phantom Function Supported (N/A) : dbi writeable 1029 * Maximum Payload Size supported (Hydra = 1KB) : dbi writeable 1030 */ 1031 typedef union { 1032 uint32_t value; 1033 struct { 1034 #if defined(_BIG_ENDIAN) 1035 uint32_t rsrvd:4; 1036 uint32_t slt_pwr_lmt_scle:2; 1037 uint32_t slt_pwr_lmt_val:8; 1038 uint32_t rsrvd1:2; 1039 uint32_t role_based_err:1; 1040 uint32_t rsrvd2:3; 1041 uint32_t l1_lat:3; 1042 uint32_t los_lat:3; 1043 uint32_t ext_tag:1; 1044 uint32_t phant_func:2; 1045 uint32_t max_mtu:3; 1046 #else 1047 uint32_t max_mtu:3; 1048 uint32_t phant_func:2; 1049 uint32_t ext_tag:1; 1050 uint32_t los_lat:3; 1051 uint32_t l1_lat:3; 1052 uint32_t rsrvd2:3; 1053 uint32_t role_based_err:1; 1054 uint32_t rsrvd1:2; 1055 uint32_t slt_pwr_lmt_val:8; 1056 uint32_t slt_pwr_lmt_scle:2; 1057 uint32_t rsrvd:4; 1058 #endif 1059 } bits; 1060 } dev_cap_t; 1061 1062 1063 /* 1064 * Register: DevStatCtrl 1065 * Device Status and Control 1066 * Description: Device Control 1067 * Fields: 1068 * Transaction Pending (1 if NP request not completed) 1069 * Auxilliary Power Detected (1 if detected) 1070 * Unsupported Request Detect 1071 * Fatal Error Detected 1072 * Non-Fatal Error Detected 1073 * Correctable Error Detected ----- Control Fields 1074 * Introduced in PCIe 1.1 specification. 1075 * Maximum Read Request Size (default = 512B) for the device as a 1076 * requester. 3'b000: 128 Bytes 3'b001: 256 Bytes 3'b010: 512 1077 * Bytes 3'b011: 1K Bytes 3'b100: 2K Bytes 3'b101: 4K Bytes 1078 * 3'b110: Reserved 3'b111: Reserved 1079 * No Snoop Enable This bit indicates the device "could", not 1080 * that it does. Both this bit and the hydra specific peuCip 1081 * register bit must be set for the value of this bit to impact 1082 * the TLP header no snoop attribute. When both are set, hydra 1083 * sets the no snoop attribute on all initiated TLPs. Software 1084 * must guarantee the No Snoop attribute is used in the system 1085 * correctly. 1086 * Auxilliary Power PM Enable 1087 * Phantom Function enable 1088 * Extended Tag Field Enable 1089 * Maximum Payload Size. 3-bit value has the same encodings as 1090 * the maxRdSz field. 1091 * Relaxed Ordering Enable This bit indicates the device "could", 1092 * not that it does. Both this bit and the hydra specific peuCip 1093 * register bit must be set for the value of this bit to impact 1094 * the TLP header relaxed ordering attribute. When both are set, 1095 * packet operations set the relaxed ordering attribute. Mailbox 1096 * updates always set the relaxed ordering attribute to 0, 1097 * regardless of this bit. When this bit is 0, the default 1098 * Sun4u/Sun4v ordering model is used. 1099 * Unsupported Request Report Enable 1100 * Fatal Error Report Enable 1101 * Non-Fatal Error Report Enable 1102 * Correctable Error Report Enable 1103 */ 1104 typedef union { 1105 uint32_t value; 1106 struct { 1107 #if defined(_BIG_ENDIAN) 1108 uint32_t rsrvd:10; 1109 uint32_t trans_pend:1; 1110 uint32_t aux_pwr_det:1; 1111 uint32_t unsup_req_det:1; 1112 uint32_t fat_err_det:1; 1113 uint32_t nf_err_det:1; 1114 uint32_t corr_err_det:1; 1115 uint32_t pcie2pcix_brdg:1; 1116 uint32_t max_rd_sz:3; 1117 uint32_t no_snoop_en:1; 1118 uint32_t aux_pwr_pm_en:1; 1119 uint32_t phant_func_en:1; 1120 uint32_t ext_tag_en:1; 1121 uint32_t max_pld_sz:3; 1122 uint32_t rlx_ord_en:1; 1123 uint32_t unsup_req_en:1; 1124 uint32_t fat_err_en:1; 1125 uint32_t nf_err_en:1; 1126 uint32_t corr_err_en:1; 1127 #else 1128 uint32_t corr_err_en:1; 1129 uint32_t nf_err_en:1; 1130 uint32_t fat_err_en:1; 1131 uint32_t unsup_req_en:1; 1132 uint32_t rlx_ord_en:1; 1133 uint32_t max_pld_sz:3; 1134 uint32_t ext_tag_en:1; 1135 uint32_t phant_func_en:1; 1136 uint32_t aux_pwr_pm_en:1; 1137 uint32_t no_snoop_en:1; 1138 uint32_t max_rd_sz:3; 1139 uint32_t pcie2pcix_brdg:1; 1140 uint32_t corr_err_det:1; 1141 uint32_t nf_err_det:1; 1142 uint32_t fat_err_det:1; 1143 uint32_t unsup_req_det:1; 1144 uint32_t aux_pwr_det:1; 1145 uint32_t trans_pend:1; 1146 uint32_t rsrvd:10; 1147 #endif 1148 } bits; 1149 } dev_stat_ctrl_t; 1150 1151 1152 /* 1153 * Register: LnkCap 1154 * Link Capability 1155 * Description: Link Capability 1156 * Fields: 1157 * Port Number : dbi writeable 1158 * Introduced in PCIe 1.1 specification. 1159 * Introduced in PCIe 1.1 specification. 1160 * Default Clock Power Management (N/A) Introduced in PCIe 1.1 1161 * specification. : dbi writeable 1162 * Default L1 Exit Latency (32us to 64us => 0x6) : dbi writeable 1163 * Default L0s Exit Latency (1us to 2us => 0x5) : dbi writeable 1164 * Active Link PM Support (only L0s = 1) : dbi writeable 1165 * Maximum Link Width (x8) : dbi writeable 1166 * Maximum Link Speed (2.5 Gbps = 1) : dbi writeable 1167 */ 1168 typedef union { 1169 uint32_t value; 1170 struct { 1171 #if defined(_BIG_ENDIAN) 1172 uint32_t prt_num:8; 1173 uint32_t rsrvd:3; 1174 uint32_t def_dll_act_rptg:1; 1175 uint32_t def_surpise_down:1; 1176 uint32_t def_clk_pm_cap:1; 1177 uint32_t def_l1_lat:3; 1178 uint32_t def_l0s_lat:3; 1179 uint32_t as_lnk_pm_supt:2; 1180 uint32_t max_lnk_wid:6; 1181 uint32_t max_lnk_spd:4; 1182 #else 1183 uint32_t max_lnk_spd:4; 1184 uint32_t max_lnk_wid:6; 1185 uint32_t as_lnk_pm_supt:2; 1186 uint32_t def_l0s_lat:3; 1187 uint32_t def_l1_lat:3; 1188 uint32_t def_clk_pm_cap:1; 1189 uint32_t def_surpise_down:1; 1190 uint32_t def_dll_act_rptg:1; 1191 uint32_t rsrvd:3; 1192 uint32_t prt_num:8; 1193 #endif 1194 } bits; 1195 } lnk_cap_t; 1196 1197 1198 /* 1199 * Register: LnkStatCtrl 1200 * Link Status and Control 1201 * Description: Link Control 1202 * Fields: 1203 * Slot Clock Configuration (0 = using independent clock; pg 266 1204 * PCIe 1.1) : dbi writeable 1205 * Link Training (N/A for EP) 1206 * Training Error (N/A for EP) 1207 * Negotiated Link Width (Max negotiated: x8) 1208 * Negotiated Link Speed (Max negotiated: 1 = 2.5 Gbps) ----- 1209 * Control Fields 1210 * Introduced in PCIe 1.1. 1211 * Extended Synch 1212 * Common Clock Configuration 1213 * Retrain Link (N/A for EP) 1214 * Link Disable (N/A for EP) 1215 * Read Completion Boundary (128B) 1216 * Active State Link PM Control 1217 */ 1218 typedef union { 1219 uint32_t value; 1220 struct { 1221 #if defined(_BIG_ENDIAN) 1222 uint32_t rsrvd:2; 1223 uint32_t dll_active:1; 1224 uint32_t slt_clk_cfg:1; 1225 uint32_t lnk_train:1; 1226 uint32_t train_err:1; 1227 uint32_t lnk_wid:6; 1228 uint32_t lnk_spd:4; 1229 uint32_t rsrvd1:7; 1230 uint32_t en_clkpwr_mg:1; 1231 uint32_t ext_sync:1; 1232 uint32_t com_clk_cfg:1; 1233 uint32_t retrain_lnk:1; 1234 uint32_t lnk_dis:1; 1235 uint32_t rd_cmpl_bndy:1; 1236 uint32_t rsrvd2:1; 1237 uint32_t aspm_ctrl:2; 1238 #else 1239 uint32_t aspm_ctrl:2; 1240 uint32_t rsrvd2:1; 1241 uint32_t rd_cmpl_bndy:1; 1242 uint32_t lnk_dis:1; 1243 uint32_t retrain_lnk:1; 1244 uint32_t com_clk_cfg:1; 1245 uint32_t ext_sync:1; 1246 uint32_t en_clkpwr_mg:1; 1247 uint32_t rsrvd1:7; 1248 uint32_t lnk_spd:4; 1249 uint32_t lnk_wid:6; 1250 uint32_t train_err:1; 1251 uint32_t lnk_train:1; 1252 uint32_t slt_clk_cfg:1; 1253 uint32_t dll_active:1; 1254 uint32_t rsrvd:2; 1255 #endif 1256 } bits; 1257 } lnk_stat_ctrl_t; 1258 1259 1260 /* 1261 * Register: VenCapHdr 1262 * Vendor Specific Capability Header 1263 * Description: Vendor Specific Capability Header 1264 * Fields: 1265 * Length 1266 * Next Capbility Pointer 1267 * Vendor Specific Capbility ID 1268 */ 1269 typedef union { 1270 uint32_t value; 1271 struct { 1272 #if defined(_BIG_ENDIAN) 1273 uint32_t rsrvd:8; 1274 uint32_t len:8; 1275 uint32_t nxt_cap_ptr:8; 1276 uint32_t ven_cap_id:8; 1277 #else 1278 uint32_t ven_cap_id:8; 1279 uint32_t nxt_cap_ptr:8; 1280 uint32_t len:8; 1281 uint32_t rsrvd:8; 1282 #endif 1283 } bits; 1284 } ven_cap_hdr_t; 1285 1286 1287 /* 1288 * Register: VenCtrl 1289 * Vendor Specific Control 1290 * Description: Vendor Specific Control 1291 * Fields: 1292 * PCIe spec absolute minimum is 50usec - (likely ~10ms). PCIe 1293 * spec absolute max is 50msec. Default set for 22.2 msec via 1294 * adding time as follows: Bit 23: 3.21 secs <---POR 0 Bit 22: 1295 * 201.3 msec <---POR 0 Bit 21: 100.8 msec <---POR 0 Bit 20: 25.2 1296 * msec <---POR 0 Bit 19: 12.6 msec <---POR 1 Bit 18: 6.3 msec 1297 * <---POR 1 Bit 17: 3.3 msec <---POR 1 Bit 16: if 0: 1298 * Baseline0=50usec; else Baseline1(use for 1299 * simulation-only)=804nsec 1300 * Interrupt Control Mode (00 = Reserved, 01 = INTx emulation, 10 1301 * = Reserved [Neptune INTx pins], 11 = Reserved [Neptune INTx 1302 * emulation + pins] 1303 */ 1304 typedef union { 1305 uint32_t value; 1306 struct { 1307 #if defined(_BIG_ENDIAN) 1308 uint32_t rsrvd:8; 1309 uint32_t eic_xtd_cpl_timout:8; 1310 uint32_t rsrvd1:14; 1311 uint32_t legacy_int_ctrl:2; 1312 #else 1313 uint32_t legacy_int_ctrl:2; 1314 uint32_t rsrvd1:14; 1315 uint32_t eic_xtd_cpl_timout:8; 1316 uint32_t rsrvd:8; 1317 #endif 1318 } bits; 1319 } ven_ctrl_t; 1320 1321 1322 /* 1323 * Register: VenPrtHdr 1324 * Vendor Specific Port Logic Header 1325 * Description: Vendor Specific Port Logic Header 1326 * Fields: 1327 * Length 1328 * Next Capbility Pointer (END, no more) 1329 * Vendor Specific Capbility ID 1330 */ 1331 typedef union { 1332 uint32_t value; 1333 struct { 1334 #if defined(_BIG_ENDIAN) 1335 uint32_t rsrvd:8; 1336 uint32_t len:8; 1337 uint32_t nxt_cap_ptr:8; 1338 uint32_t ven_cap_id:8; 1339 #else 1340 uint32_t ven_cap_id:8; 1341 uint32_t nxt_cap_ptr:8; 1342 uint32_t len:8; 1343 uint32_t rsrvd:8; 1344 #endif 1345 } bits; 1346 } ven_prt_hdr_t; 1347 1348 1349 /* 1350 * Register: AcklatReplay 1351 * Ack Latency and Replay Timer register 1352 * Description: Ack Latency/Replay Timer 1353 * Fields: 1354 * Replay Time limit = 16'd12429/`cxNb where cxNb=1. 1355 * Round Trip Latency Time limit = 9d'4143/`cxNb where cxNb=1. 1356 */ 1357 typedef union { 1358 uint32_t value; 1359 struct { 1360 #if defined(_BIG_ENDIAN) 1361 uint32_t rep_tim:16; 1362 uint32_t ack_tim:16; 1363 #else 1364 uint32_t ack_tim:16; 1365 uint32_t rep_tim:16; 1366 #endif 1367 } bits; 1368 } acklat_replay_t; 1369 1370 1371 /* 1372 * Register: OthMsg 1373 * Other Message Register 1374 * Description: Other Message Register 1375 * Fields: 1376 * Message to send/Data to corrupt LCRC 1377 */ 1378 typedef union { 1379 uint32_t value; 1380 struct { 1381 #if defined(_BIG_ENDIAN) 1382 uint32_t oth_msg:32; 1383 #else 1384 uint32_t oth_msg:32; 1385 #endif 1386 } bits; 1387 } oth_msg_t; 1388 1389 1390 /* 1391 * Register: ForceLink 1392 * Port Force Link 1393 * Description: Other Message Register 1394 * Fields: 1395 * LinkState that the EP core will be forced to when ForceLink 1396 * (bit[15]) is set 1397 * Forces Link to the specified LinkState field below. Write this 1398 * bit to generate a pulse to the ltssm. It clears itself once 1399 * the pulse is generated. Read will always return 0. 1400 * Link Number - N/A for Endpoint 1401 */ 1402 typedef union { 1403 uint32_t value; 1404 struct { 1405 #if defined(_BIG_ENDIAN) 1406 uint32_t rsrvd:10; 1407 uint32_t link_state:6; 1408 uint32_t force_link:1; 1409 uint32_t rsrvd1:7; 1410 uint32_t link_num:8; 1411 #else 1412 uint32_t link_num:8; 1413 uint32_t rsrvd1:7; 1414 uint32_t force_link:1; 1415 uint32_t link_state:6; 1416 uint32_t rsrvd:10; 1417 #endif 1418 } bits; 1419 } force_link_t; 1420 1421 1422 /* 1423 * Register: AckFreq 1424 * ACK Frequency Register 1425 * Description: ACK Frequency Register 1426 * Fields: 1427 * NFTS = 115. 1428 * NFTS = 115. 1429 */ 1430 typedef union { 1431 uint32_t value; 1432 struct { 1433 #if defined(_BIG_ENDIAN) 1434 uint32_t rsrvd:2; 1435 uint32_t l1_entr_latency:3; 1436 uint32_t los_entr_latency:3; 1437 uint32_t cx_comm_nfts:8; 1438 uint32_t nfts:8; 1439 uint32_t def_ack_freq:8; 1440 #else 1441 uint32_t def_ack_freq:8; 1442 uint32_t nfts:8; 1443 uint32_t cx_comm_nfts:8; 1444 uint32_t los_entr_latency:3; 1445 uint32_t l1_entr_latency:3; 1446 uint32_t rsrvd:2; 1447 #endif 1448 } bits; 1449 } ack_freq_t; 1450 1451 1452 /* 1453 * Register: LinkCtrl 1454 * Port Link Control 1455 * Description: Port Link Control 1456 * Fields: 1457 * 8 lanes 1458 * When set, this bit is only set for 1 cycle. A write of 0 has 1459 * no effect. 1460 */ 1461 typedef union { 1462 uint32_t value; 1463 struct { 1464 #if defined(_BIG_ENDIAN) 1465 uint32_t rsrvd:4; 1466 uint32_t rsrvd1:2; 1467 uint32_t corrupt_lcrc:1; 1468 uint32_t rsrvd2:1; 1469 uint32_t rsrvd3:2; 1470 uint32_t link_mode_en:6; 1471 uint32_t rsrvd4:4; 1472 uint32_t rsrvd5:4; 1473 uint32_t fast_link_mode:1; 1474 uint32_t rsrvd6:1; 1475 uint32_t dll_link_en:1; 1476 uint32_t rsrvd7:1; 1477 uint32_t reset_assert:1; 1478 uint32_t lpbk_en:1; 1479 uint32_t scram_dis:1; 1480 uint32_t oth_msg_req:1; 1481 #else 1482 uint32_t oth_msg_req:1; 1483 uint32_t scram_dis:1; 1484 uint32_t lpbk_en:1; 1485 uint32_t reset_assert:1; 1486 uint32_t rsrvd7:1; 1487 uint32_t dll_link_en:1; 1488 uint32_t rsrvd6:1; 1489 uint32_t fast_link_mode:1; 1490 uint32_t rsrvd5:4; 1491 uint32_t rsrvd4:4; 1492 uint32_t link_mode_en:6; 1493 uint32_t rsrvd3:2; 1494 uint32_t rsrvd2:1; 1495 uint32_t corrupt_lcrc:1; 1496 uint32_t rsrvd1:2; 1497 uint32_t rsrvd:4; 1498 #endif 1499 } bits; 1500 } link_ctrl_t; 1501 1502 1503 /* 1504 * Register: LaneSkew 1505 * Lane Skew Register 1506 * Description: Lane Skew Register 1507 * Fields: 1508 * prevents EP core from sending Ack/Nack DLLPs 1509 * prevents EP core from sending FC DLLPs 1510 */ 1511 typedef union { 1512 uint32_t value; 1513 struct { 1514 #if defined(_BIG_ENDIAN) 1515 uint32_t dis_lane_to_lane_deskew:1; 1516 uint32_t rsrvd:5; 1517 uint32_t ack_nack_dis:1; 1518 uint32_t flow_control_dis:1; 1519 uint32_t tx_lane_skew:24; 1520 #else 1521 uint32_t tx_lane_skew:24; 1522 uint32_t flow_control_dis:1; 1523 uint32_t ack_nack_dis:1; 1524 uint32_t rsrvd:5; 1525 uint32_t dis_lane_to_lane_deskew:1; 1526 #endif 1527 } bits; 1528 } lane_skew_t; 1529 1530 1531 /* 1532 * Register: SymbolNum 1533 * Symbol Number Register 1534 * Description: Symbol Number Register 1535 * Fields: 1536 * Timer modifier for Flow control Watch Dog timer 1537 * Timer modifier for Ack/Nack latency timer 1538 * Timer modifier for Replay timer 1539 * Note: rtl uses defaultNSkipSymbols 1540 * Note: rtl initialized using defaultNTs1Symbols 1541 */ 1542 typedef union { 1543 uint32_t value; 1544 struct { 1545 #if defined(_BIG_ENDIAN) 1546 uint32_t rsrvd:3; 1547 uint32_t fc_wdog_tim_mod:5; 1548 uint32_t ack_nack_tim_mod:5; 1549 uint32_t rep_tim_mod:5; 1550 uint32_t rsrvd1:3; 1551 uint32_t num_skip_symb:3; 1552 uint32_t rsrvd2:4; 1553 uint32_t num_ts_symb:4; 1554 #else 1555 uint32_t num_ts_symb:4; 1556 uint32_t rsrvd2:4; 1557 uint32_t num_skip_symb:3; 1558 uint32_t rsrvd1:3; 1559 uint32_t rep_tim_mod:5; 1560 uint32_t ack_nack_tim_mod:5; 1561 uint32_t fc_wdog_tim_mod:5; 1562 uint32_t rsrvd:3; 1563 #endif 1564 } bits; 1565 } symbol_num_t; 1566 1567 1568 /* 1569 * Register: SymbTimRadmFlt1 1570 * Symbol Timer Register / RADM Filter Mask Register 1 1571 * Description: Symbol Timer / RADM Filter Mask 1 1572 * Fields: 1573 * No masking errors while filtering 1574 */ 1575 typedef union { 1576 uint32_t value; 1577 struct { 1578 #if defined(_BIG_ENDIAN) 1579 uint32_t mask_radm_flt:16; 1580 uint32_t dis_fc_wdog:1; 1581 uint32_t rsrvd:4; 1582 uint32_t skip_interval:11; 1583 #else 1584 uint32_t skip_interval:11; 1585 uint32_t rsrvd:4; 1586 uint32_t dis_fc_wdog:1; 1587 uint32_t mask_radm_flt:16; 1588 #endif 1589 } bits; 1590 } symb_tim_radm_flt1_t; 1591 1592 1593 /* 1594 * Register: RadmFlt2 1595 * RADM Filter Mask Register 2 1596 * Description: RADM Filter Mask Register 2 1597 * Fields: 1598 * [31:2] = Reserved [1]=0=Vendor MSG Type0 dropped & treated as 1599 * UR, [0]=0=Vendor MSG Type1 silently dropped. 1600 */ 1601 typedef union { 1602 uint32_t value; 1603 struct { 1604 #if defined(_BIG_ENDIAN) 1605 uint32_t mask_radm_flt:32; 1606 #else 1607 uint32_t mask_radm_flt:32; 1608 #endif 1609 } bits; 1610 } radm_flt2_t; 1611 1612 1613 /* 1614 * Register: CascadeDebReg0 1615 * Cascade core (EP) Debug Register 0 1616 * Description: Debug Register 0 EP Core SII Interface bus : 1617 * cxplDebugInfo[31:0] 1618 * Fields: 1619 */ 1620 typedef union { 1621 uint32_t value; 1622 struct { 1623 #if defined(_BIG_ENDIAN) 1624 uint32_t rmlh_ts_link_ctrl:4; 1625 uint32_t rmlh_ts_lane_num_is_k237:1; 1626 uint32_t rmlh_ts_link_num_is_k237:1; 1627 uint32_t rmlh_rcvd_idle_bit0:1; 1628 uint32_t rmlh_rcvd_idle_bit1:1; 1629 uint32_t mac_phy_txdata:16; 1630 uint32_t mac_phy_txdatak:2; 1631 uint32_t rsrvd:1; 1632 uint32_t xmlh_ltssm_state:5; 1633 #else 1634 uint32_t xmlh_ltssm_state:5; 1635 uint32_t rsrvd:1; 1636 uint32_t mac_phy_txdatak:2; 1637 uint32_t mac_phy_txdata:16; 1638 uint32_t rmlh_rcvd_idle_bit1:1; 1639 uint32_t rmlh_rcvd_idle_bit0:1; 1640 uint32_t rmlh_ts_link_num_is_k237:1; 1641 uint32_t rmlh_ts_lane_num_is_k237:1; 1642 uint32_t rmlh_ts_link_ctrl:4; 1643 #endif 1644 } bits; 1645 } cascade_deb_reg0_t; 1646 1647 1648 /* 1649 * Register: CascadeDebReg1 1650 * Cascade Core (EP) Debug Register 1 1651 * Description: Debug Register 1 EP Core SII Interface bus : 1652 * cxplDebugInfo[63:32] 1653 * Fields: 1654 * PCIe Link status. 0=down, 1=up 1655 */ 1656 typedef union { 1657 uint32_t value; 1658 struct { 1659 #if defined(_BIG_ENDIAN) 1660 uint32_t xmlh_scrambler_disable:1; 1661 uint32_t xmlh_link_disable:1; 1662 uint32_t xmlh_link_in_training:1; 1663 uint32_t xmlh_rcvr_revrs_pol_en:1; 1664 uint32_t xmlh_training_rst_n:1; 1665 uint32_t rsrvd:4; 1666 uint32_t mac_phy_txdetectrx_loopback:1; 1667 uint32_t mac_phy_txelecidle_bit0:1; 1668 uint32_t mac_phy_txcompliance_bit0:1; 1669 uint32_t app_init_rst:1; 1670 uint32_t rsrvd1:3; 1671 uint32_t rmlh_rs_link_num:8; 1672 uint32_t rmlh_link_mode:3; 1673 uint32_t xmlh_link_up:1; 1674 uint32_t rmlh_inskip_rcv:1; 1675 uint32_t rmlh_ts1_rcvd:1; 1676 uint32_t rmlh_ts2_rcvd:1; 1677 uint32_t rmlh_rcvd_lane_rev:1; 1678 #else 1679 uint32_t rmlh_rcvd_lane_rev:1; 1680 uint32_t rmlh_ts2_rcvd:1; 1681 uint32_t rmlh_ts1_rcvd:1; 1682 uint32_t rmlh_inskip_rcv:1; 1683 uint32_t xmlh_link_up:1; 1684 uint32_t rmlh_link_mode:3; 1685 uint32_t rmlh_rs_link_num:8; 1686 uint32_t rsrvd1:3; 1687 uint32_t app_init_rst:1; 1688 uint32_t mac_phy_txcompliance_bit0:1; 1689 uint32_t mac_phy_txelecidle_bit0:1; 1690 uint32_t mac_phy_txdetectrx_loopback:1; 1691 uint32_t rsrvd:4; 1692 uint32_t xmlh_training_rst_n:1; 1693 uint32_t xmlh_rcvr_revrs_pol_en:1; 1694 uint32_t xmlh_link_in_training:1; 1695 uint32_t xmlh_link_disable:1; 1696 uint32_t xmlh_scrambler_disable:1; 1697 #endif 1698 } bits; 1699 } cascade_deb_reg1_t; 1700 1701 1702 /* 1703 * Register: TxpFcCreditStat 1704 * Transmit Posted FC Credit Status 1705 * Description: Transmit Posted FC Credit Status 1706 * Fields: 1707 */ 1708 typedef union { 1709 uint32_t value; 1710 struct { 1711 #if defined(_BIG_ENDIAN) 1712 uint32_t rsrvd:12; 1713 uint32_t txp_fc_hdr_credit_stat:8; 1714 uint32_t txp_fc_data_credit_stat:12; 1715 #else 1716 uint32_t txp_fc_data_credit_stat:12; 1717 uint32_t txp_fc_hdr_credit_stat:8; 1718 uint32_t rsrvd:12; 1719 #endif 1720 } bits; 1721 } txp_fc_credit_stat_t; 1722 1723 1724 /* 1725 * Register: TxnpFcCreditStat 1726 * Transmit Non-Posted FC Credit Status 1727 * Description: Transmit Non-Posted FC Credit Status 1728 * Fields: 1729 */ 1730 typedef union { 1731 uint32_t value; 1732 struct { 1733 #if defined(_BIG_ENDIAN) 1734 uint32_t rsrvd:12; 1735 uint32_t txnp_fc_hdr_credit_stat:8; 1736 uint32_t txnp_fc_data_credit_stat:12; 1737 #else 1738 uint32_t txnp_fc_data_credit_stat:12; 1739 uint32_t txnp_fc_hdr_credit_stat:8; 1740 uint32_t rsrvd:12; 1741 #endif 1742 } bits; 1743 } txnp_fc_credit_stat_t; 1744 1745 1746 /* 1747 * Register: TxcplFcCreditStat 1748 * Transmit Completion FC Credit Status 1749 * Description: Transmit Completion FC Credit Status 1750 * Fields: 1751 */ 1752 typedef union { 1753 uint32_t value; 1754 struct { 1755 #if defined(_BIG_ENDIAN) 1756 uint32_t rsrvd:12; 1757 uint32_t txcpl_fc_hdr_credit_stat:8; 1758 uint32_t txcpl_fc_data_credit_stat:12; 1759 #else 1760 uint32_t txcpl_fc_data_credit_stat:12; 1761 uint32_t txcpl_fc_hdr_credit_stat:8; 1762 uint32_t rsrvd:12; 1763 #endif 1764 } bits; 1765 } txcpl_fc_credit_stat_t; 1766 1767 1768 /* 1769 * Register: QueueStat 1770 * Queue Status 1771 * Description: Queue Status 1772 * Fields: 1773 */ 1774 typedef union { 1775 uint32_t value; 1776 struct { 1777 #if defined(_BIG_ENDIAN) 1778 uint32_t rsrvd:29; 1779 uint32_t rx_queue_not_empty:1; 1780 uint32_t tx_rbuf_not_empty:1; 1781 uint32_t tx_fc_credit_not_ret:1; 1782 #else 1783 uint32_t tx_fc_credit_not_ret:1; 1784 uint32_t tx_rbuf_not_empty:1; 1785 uint32_t rx_queue_not_empty:1; 1786 uint32_t rsrvd:29; 1787 #endif 1788 } bits; 1789 } queue_stat_t; 1790 1791 1792 /* 1793 * Register: GbtDebug0 1794 * GBT Debug, Status register 1795 * Description: This register returns bits [31:0] of the PIPE core's 1796 * gbtDebug bus 1797 * Fields: 1798 * [6] & [22] = rxclkO will always read 1'b0 [7] & [23] = 1799 * tbcout10O will always read 1'b0 1800 * The value specified here is the Power On Reset value as given 1801 * in spec. except for the clock bits which are hardwired to 1802 * 1'b0. 1803 * The gbtDebug[0:15] bus is provided for each lane as an output 1804 * from the pcieGbtopWrapper.v module. These signals are not 1805 * required for manufacturing test and may be left unconnected. 1806 * The cw00041130PipeParam.vh bus width is the number of lanes 1807 * multiplied by 16. lane0 is bits[15:0], lane1 is bits[31:16], 1808 * lane2 is bits[47:32], lane3 is bits[63:48], lane4 is 1809 * bits[79:64], lane5 is bits[95:80], lane6 is bits[111:96], 1810 * lane7 is bits[127:112]. 1811 * Refer to section 4.2.2.4, Gigablaze Debug Signals section. 1812 * (pgs 4.27 - 4.28) in the following document : 1813 * /home/cadtools/cores/lsi/cw000411/cw00041131/prod/docs/manuals/ 1814 * cw000411TechMan.pdf 1815 * lane0 is bits[15:0], which is gbtDebug0[15:0] lane1 is 1816 * bits[31:16], which is gbtDebug0[31:16] 1817 * 1818 * ------------------------------------------------------------------------- 1819 * Signal Bit Reset Description 1820 * ------------------------------------------------------------------------- 1821 * gbtResetRbcI [16n+15] [15] 1 Reset receiver bit clock 1822 * gbtResetTbc20I [16n+14] [14] 1 Reset transmit 20-bit clock 1823 * gbtResetRI [16n+13] [13] 1 Reset receiver logic gbtResetTI 1824 * [16n+12] [12] 1 Reset transmit logic reserved [16n+11:16n+8] 1825 * [11:8] 0 reserved gbtTbcout10 [16n+7] [7] 1 transmit clock 1826 * 10-bit gbtRxclkO [16n+6] [6] 0 receiver PLL clock gbtRxpresO 1827 * [16n+5] [5] 0 receiver detect present gbtRxpresvalidO [16n+4] 1828 * [4] 0 gbtRxpresO is valid gbtRxlosO [16n+3] [3] 1 raw receiver 1829 * loss-of-signal gbtPassnO [16n+2] [2] 1 GigaBlaze BIST pass 1830 * active low reserved [16n+1] [1] 0 reserved reserved [16n] [0] 1831 * 0 reserved 1832 * ------------------------------------------------------------------------- 1833 */ 1834 typedef union { 1835 uint32_t value; 1836 struct { 1837 #if defined(_BIG_ENDIAN) 1838 uint32_t data:32; 1839 #else 1840 uint32_t data:32; 1841 #endif 1842 } bits; 1843 } gbt_debug0_t; 1844 1845 1846 /* 1847 * Register: GbtDebug1 1848 * GBT Debug, Status register 1849 * Description: This register returns bits [63:32] of the PIPE core's 1850 * gbtDebug bus 1851 * Fields: 1852 * [6] & [22] = rxclkO will always read 1'b0 [7] & [23] = 1853 * tbcout10O will always read 1'b0 1854 * The value specified here is the Power On Reset value as given 1855 * in spec. except for the clock bits which are hardwired to 1856 * 1'b0. 1857 * The gbtDebug[0:15] bus is provided for each lane as an output 1858 * from the pcieGbtopWrapper.v module. These signals are not 1859 * required for manufacturing test and may be left unconnected. 1860 * The cw00041130PipeParam.vh bus width is the number of lanes 1861 * multiplied by 16. 1862 * Refer to section 4.2.2.4, Gigablaze Debug Signals section. 1863 * (pgs 4.27 - 4.28) in the following document : 1864 * /home/cadtools/cores/lsi/cw000411/cw00041131/prod/docs/manuals/ 1865 * cw000411TechMan.pdf 1866 * lane2 is bits[47:32], which is gbtDebug1[15:0] lane3 is 1867 * bits[63:48], which is gbtDebug1[31:16] 1868 * 1869 * ------------------------------------------------------------------------- 1870 * Signal Bit Reset Description 1871 * ------------------------------------------------------------------------- 1872 * gbtResetRbcI [16n+15] [15] 1 Reset receiver bit clock 1873 * gbtResetTbc20I [16n+14] [14] 1 Reset transmit 20-bit clock 1874 * gbtResetRI [16n+13] [13] 1 Reset receiver logic gbtResetTI 1875 * [16n+12] [12] 1 Reset transmit logic reserved [16n+11:16n+8] 1876 * [11:8] 0 reserved gbtTbcout10 [16n+7] [7] 1 transmit clock 1877 * 10-bit gbtRxclkO [16n+6] [6] 0 receiver PLL clock gbtRxpresO 1878 * [16n+5] [5] 0 receiver detect present gbtRxpresvalidO [16n+4] 1879 * [4] 0 gbtRxpresO is valid gbtRxlosO [16n+3] [3] 1 raw receiver 1880 * loss-of-signal gbtPassnO [16n+2] [2] 1 GigaBlaze BIST pass 1881 * active low reserved [16n+1] [1] 0 reserved reserved [16n] [0] 1882 * 0 reserved 1883 * ------------------------------------------------------------------------- 1884 */ 1885 typedef union { 1886 uint32_t value; 1887 struct { 1888 #if defined(_BIG_ENDIAN) 1889 uint32_t data:32; 1890 #else 1891 uint32_t data:32; 1892 #endif 1893 } bits; 1894 } gbt_debug1_t; 1895 1896 1897 /* 1898 * Register: GbtDebug2 1899 * GBT Debug, Status register 1900 * Description: This register returns bits [95:64] of the PIPE core's 1901 * gbtDebug bus 1902 * Fields: 1903 * [6] & [22] = rxclkO will always read 1'b0 [7] & [23] = 1904 * tbcout10O will always read 1'b0 1905 * The value specified here is the Power On Reset value as given 1906 * in spec. except for the clock bits which are hardwired to 1907 * 1'b0. 1908 * The gbtDebug[0:15] bus is provided for each lane as an output 1909 * from the pcieGbtopWrapper.v module. These signals are not 1910 * required for manufacturing test and may be left unconnected. 1911 * The cw00041130PipeParam.vh bus width is the number of lanes 1912 * multiplied by 16. 1913 * Refer to section 4.2.2.4, Gigablaze Debug Signals section. 1914 * (pgs 4.27 - 4.28) in the following document : 1915 * /home/cadtools/cores/lsi/cw000411/cw00041131/prod/docs/manuals/ 1916 * cw000411TechMan.pdf 1917 * lane4 is bits[79:64], which is gbtDebug2[15:0] lane5 is 1918 * bits[95:80], which is gbtDebug2[31:16] 1919 * 1920 * ------------------------------------------------------------------------- 1921 * Signal Bit Reset Description 1922 * ------------------------------------------------------------------------- 1923 * gbtResetRbcI [16n+15] [15] 1 Reset receiver bit clock 1924 * gbtResetTbc20I [16n+14] [14] 1 Reset transmit 20-bit clock 1925 * gbtResetRI [16n+13] [13] 1 Reset receiver logic gbtResetTI 1926 * [16n+12] [12] 1 Reset transmit logic reserved [16n+11:16n+8] 1927 * [11:8] 0 reserved gbtTbcout10 [16n+7] [7] 1 transmit clock 1928 * 10-bit gbtRxclkO [16n+6] [6] 0 receiver PLL clock gbtRxpresO 1929 * [16n+5] [5] 0 receiver detect present gbtRxpresvalidO [16n+4] 1930 * [4] 0 gbtRxpresO is valid gbtRxlosO [16n+3] [3] 1 raw receiver 1931 * loss-of-signal gbtPassnO [16n+2] [2] 1 GigaBlaze BIST pass 1932 * active low reserved [16n+1] [1] 0 reserved reserved [16n] [0] 1933 * 0 reserved 1934 * ------------------------------------------------------------------------- 1935 */ 1936 typedef union { 1937 uint32_t value; 1938 struct { 1939 #if defined(_BIG_ENDIAN) 1940 uint32_t data:32; 1941 #else 1942 uint32_t data:32; 1943 #endif 1944 } bits; 1945 } gbt_debug2_t; 1946 1947 1948 /* 1949 * Register: GbtDebug3 1950 * GBT Debug, Status register 1951 * Description: This register returns bits [127:96] of the PIPE 1952 * core's gbtDebug bus 1953 * Fields: 1954 * [6] & [22] = rxclkO will always read 1'b0 [7] & [23] = 1955 * tbcout10O will always read 1'b0 1956 * The value specified here is the Power On Reset value as given 1957 * in spec. except for the clock bits which are hardwired to 1958 * 1'b0. 1959 * The gbtDebug[0:15] bus is provided for each lane as an output 1960 * from the pcieGbtopWrapper.v module. These signals are not 1961 * required for manufacturing test and may be left unconnected. 1962 * The cw00041130PipeParam.vh bus width is the number of lanes 1963 * multiplied by 16. 1964 * Refer to section 4.2.2.4, Gigablaze Debug Signals section. 1965 * (pgs 4.27 - 4.28) in the following document : 1966 * /home/cadtools/cores/lsi/cw000411/cw00041131/prod/docs/manuals/ 1967 * cw000411TechMan.pdf 1968 * lane6 is bits[111:96], which is gbtDebug3[15:0] lane7 is 1969 * bits[127:112], which is gbtDebug3[31:16] 1970 * 1971 * ------------------------------------------------------------------------- 1972 * Signal Bit Reset Description 1973 * ------------------------------------------------------------------------- 1974 * gbtResetRbcI [16n+15] [15] 1 Reset receiver bit clock 1975 * gbtResetTbc20I [16n+14] [14] 1 Reset transmit 20-bit clock 1976 * gbtResetRI [16n+13] [13] 1 Reset receiver logic gbtResetTI 1977 * [16n+12] [12] 1 Reset transmit logic reserved [16n+11:16n+8] 1978 * [11:8] 0 reserved gbtTbcout10 [16n+7] [7] 1 transmit clock 1979 * 10-bit gbtRxclkO [16n+6] [6] 0 receiver PLL clock gbtRxpresO 1980 * [16n+5] [5] 0 receiver detect present gbtRxpresvalidO [16n+4] 1981 * [4] 0 gbtRxpresO is valid gbtRxlosO [16n+3] [3] 1 raw receiver 1982 * loss-of-signal gbtPassnO [16n+2] [2] 1 GigaBlaze BIST pass 1983 * active low reserved [16n+1] [1] 0 reserved reserved [16n] [0] 1984 * 0 reserved 1985 * ------------------------------------------------------------------------- 1986 */ 1987 typedef union { 1988 uint32_t value; 1989 struct { 1990 #if defined(_BIG_ENDIAN) 1991 uint32_t data:32; 1992 #else 1993 uint32_t data:32; 1994 #endif 1995 } bits; 1996 } gbt_debug3_t; 1997 1998 1999 /* 2000 * Register: PipeDebug0 2001 * PIPE Debug, status register 2002 * Description: This register returns bits [31:0] of the PIPE core's 2003 * gbtDebug bus 2004 * Fields: 2005 * The value specified here is the Power On Reset value as given 2006 * in spec. 2007 * This 16-bit debug bus reports operating conditions for the 2008 * PIPE. The pipeDebug[0:15] bus is provided for each lane. lane0 2009 * is bits[15:0], lane1 is bits[31:16], lane2 is bits[47:32], 2010 * lane3 is bits[63:48], lane4 is bits[79:64], lane5 is 2011 * bits[95:80], lane6 is bits[111:96], lane7 is bits[127:112]. 2012 * Refer to section 4.2.1.5 Single-Lane PIPE Debug Signals in 2013 * the following document : 2014 * /home/cadtools/cores/lsi/cw000411/cw00041131/prod/docs/manuals/ 2015 * cw000411TechMan.pdf 2016 * lane0 is bit[15:0], which is pipeDebug0[15:0] lane1 is 2017 * bit[31:16], which is pipeDebug0[31:16] 2018 * 2019 * ------------------------------------------------------------------------- 2020 * pipeDebug Signal or Condition Description Reset 2021 * ------------------------------------------------------------------------- 2022 * [15] efifoOverflow or EFIFO overflow or 0 efifoUnderflow EFIFO 2023 * underflow occurred 2024 * [14] skipInsert or EFIFO skip inserted or 0 skipDelete 2025 * deleted 0 2026 * [13] fifordData[12] == Skip flag read by EFIFO. 0 skipFlag 2027 * Used with skipcharflag to verify EFIFO depth. 2028 * [12] skipcharflag Skip flag written by EFIFO 0 2029 * [11:8] efifoDepth[3:0] Indicates EFIFO depth 0000 2030 * [7] efifoEios Detected EFIFO 0 electrical-idle ordered-set 2031 * output 2032 * [6] efifoBytesync EFIFO output byte 0 synchronization 2033 * [5] rxinvalid 8b/10b error or 0 or code violation 2034 * [4] rxinitdone Receiver bit-init done. 0 Synchronous with 2035 * pipeClk. 2036 * [3] txinitdone Transmitter-bit init done. 0 Synchronous with 2037 * pipeClk. 2038 * [2] filteredrxlos Filtered loss of signal used 1 to generate 2039 * p2lRxelectidle. Synchronous with pipeClk. 2040 * [1] rxdetectInt Receiver detected 0 2041 * [0] pipeMasterDoneOut Receiver detection valid 0 2042 * 2043 */ 2044 typedef union { 2045 uint32_t value; 2046 struct { 2047 #if defined(_BIG_ENDIAN) 2048 uint32_t data:32; 2049 #else 2050 uint32_t data:32; 2051 #endif 2052 } bits; 2053 } pipe_debug0_t; 2054 2055 2056 /* 2057 * Register: PipeDebug1 2058 * PIPE Debug, status register 2059 * Description: This register returns bits [63:32] of the PIPE core's 2060 * gbtDebug bus 2061 * Fields: 2062 * The value specified here is the Power On Reset value as given 2063 * in spec. 2064 * This 16-bit debug bus reports operating conditions for the 2065 * PIPE. The pipeDebug[0:15] bus is provided for each lane. lane0 2066 * is bits[15:0], lane1 is bits[31:16], lane2 is bits[47:32], 2067 * lane3 is bits[63:48], lane4 is bits[79:64], lane5 is 2068 * bits[95:80], lane6 is bits[111:96], lane7 is bits[127:112]. 2069 * Refer to section 4.2.1.5 Single-Lane PIPE Debug Signals in 2070 * the following document : 2071 * /home/cadtools/cores/lsi/cw000411/cw00041131/prod/docs/manuals/ 2072 * cw000411TechMan.pdf 2073 * lane2 is bits[47:32], which is pipeDebug1[15:0] lane3 is 2074 * bits[63:48], which is pipeDebug1[31:16] 2075 * 2076 * ------------------------------------------------------------------------- 2077 * pipeDebug Signal or Condition Description Reset 2078 * ------------------------------------------------------------------------- 2079 * [15] efifoOverflow or EFIFO overflow or 0 efifoUnderflow EFIFO 2080 * underflow occurred 2081 * [14] skipInsert or EFIFO skip inserted or 0 skipDelete 2082 * deleted 0 2083 * [13] fifordData[12] == Skip flag read by EFIFO. 0 skipFlag 2084 * Used with skipcharflag to verify EFIFO depth. 2085 * [12] skipcharflag Skip flag written by EFIFO 0 2086 * [11:8] efifoDepth[3:0] Indicates EFIFO depth 0000 2087 * [7] efifoEios Detected EFIFO 0 electrical-idle ordered-set 2088 * output 2089 * [6] efifoBytesync EFIFO output byte 0 synchronization 2090 * [5] rxinvalid 8b/10b error or 0 or code violation 2091 * [4] rxinitdone Receiver bit-init done. 0 Synchronous with 2092 * pipeClk. 2093 * [3] txinitdone Transmitter-bit init done. 0 Synchronous with 2094 * pipeClk. 2095 * [2] filteredrxlos Filtered loss of signal used 1 to generate 2096 * p2lRxelectidle. Synchronous with pipeClk. 2097 * [1] rxdetectInt Receiver detected 0 2098 * [0] pipeMasterDoneOut Receiver detection valid 0 2099 * 2100 */ 2101 typedef union { 2102 uint32_t value; 2103 struct { 2104 #if defined(_BIG_ENDIAN) 2105 uint32_t data:32; 2106 #else 2107 uint32_t data:32; 2108 #endif 2109 } bits; 2110 } pipe_debug1_t; 2111 2112 2113 /* 2114 * Register: PipeDebug2 2115 * PIPE Debug, status register 2116 * The value specified here is the Power On Reset value as given 2117 * in spec. 2118 * This 16-bit debug bus reports operating conditions for the 2119 * PIPE. The pipeDebug[0:15] bus is provided for each lane. lane0 2120 * is bits[15:0], lane1 is bits[31:16], lane2 is bits[47:32], 2121 * lane3 is bits[63:48], lane4 is bits[79:64], lane5 is 2122 * bits[95:80], lane6 is bits[111:96], lane7 is bits[127:112]. 2123 * Refer to section 4.2.1.5 Single-Lane PIPE Debug Signals in 2124 * the following document : 2125 * /home/cadtools/cores/lsi/cw000411/cw00041131/prod/docs/manuals/ 2126 * cw000411TechMan.pdf 2127 * lane4 is bits[79:64], which is pipeDebug2[15:0] lane5 is 2128 * bits[95:80], which is pipeDebug2[31:16] 2129 * 2130 * ------------------------------------------------------------------------- 2131 * pipeDebug Signal or Condition Description Reset 2132 * ------------------------------------------------------------------------- 2133 * [15] efifoOverflow or EFIFO overflow or 0 efifoUnderflow EFIFO 2134 * underflow occurred 2135 * [14] skipInsert or EFIFO skip inserted or 0 skipDelete 2136 * deleted 0 2137 * [13] fifordData[12] == Skip flag read by EFIFO. 0 skipFlag 2138 * Used with skipcharflag to verify EFIFO depth. 2139 * [12] skipcharflag Skip flag written by EFIFO 0 2140 * [11:8] efifoDepth[3:0] Indicates EFIFO depth 0000 2141 * [7] efifoEios Detected EFIFO 0 electrical-idle ordered-set 2142 * output 2143 * [6] efifoBytesync EFIFO output byte 0 synchronization 2144 * [5] rxinvalid 8b/10b error or 0 or code violation 2145 * [4] rxinitdone Receiver bit-init done. 0 Synchronous with 2146 * pipeClk. 2147 * [3] txinitdone Transmitter-bit init done. 0 Synchronous with 2148 * pipeClk. 2149 * [2] filteredrxlos Filtered loss of signal used 1 to generate 2150 * p2lRxelectidle. Synchronous with pipeClk. 2151 * [1] rxdetectInt Receiver detected 0 2152 * [0] pipeMasterDoneOut Receiver detection valid 0 2153 * 2154 */ 2155 typedef union { 2156 uint32_t value; 2157 struct { 2158 #if defined(_BIG_ENDIAN) 2159 uint32_t data:32; 2160 #else 2161 uint32_t data:32; 2162 #endif 2163 } bits; 2164 } pipe_debug2_t; 2165 2166 2167 /* 2168 * Register: PipeDebug3 2169 * PIPE Debug, status register 2170 * Description: This register returns bits [127:96] of the PIPE 2171 * core's gbtDebug bus 2172 * Fields: 2173 * The value specified here is the Power On Reset value as given 2174 * in spec. 2175 * This 16-bit debug bus reports operating conditions for the 2176 * PIPE. The pipeDebug[0:15] bus is provided for each lane. lane0 2177 * is bits[15:0], lane1 is bits[31:16], lane2 is bits[47:32], 2178 * lane3 is bits[63:48], lane4 is bits[79:64], lane5 is 2179 * bits[95:80], lane6 is bits[111:96], lane7 is bits[127:112]. 2180 * Refer to section 4.2.1.5 Single-Lane PIPE Debug Signals in 2181 * the following document : 2182 * /home/cadtools/cores/lsi/cw000411/cw00041131/prod/docs/manuals/ 2183 * cw000411TechMan.pdf 2184 * lane6 is bits[111:96], which is pipeDebug3[15:0] lane7 is 2185 * bits[127:112], which is pipeDebug3[31:16] 2186 * 2187 * ------------------------------------------------------------------------- 2188 * pipeDebug Signal or Condition Description Reset 2189 * ------------------------------------------------------------------------- 2190 * [15] efifoOverflow or EFIFO overflow or 0 efifoUnderflow EFIFO 2191 * underflow occurred 2192 * [14] skipInsert or EFIFO skip inserted or 0 skipDelete 2193 * deleted 0 2194 * [13] fifordData[12] == Skip flag read by EFIFO. 0 skipFlag 2195 * Used with skipcharflag to verify EFIFO depth. 2196 * [12] skipcharflag Skip flag written by EFIFO 0 2197 * [11:8] efifoDepth[3:0] Indicates EFIFO depth 0000 2198 * [7] efifoEios Detected EFIFO 0 electrical-idle ordered-set 2199 * output 2200 * [6] efifoBytesync EFIFO output byte 0 synchronization 2201 * [5] rxinvalid 8b/10b error or 0 or code violation 2202 * [4] rxinitdone Receiver bit-init done. 0 Synchronous with 2203 * pipeClk. 2204 * [3] txinitdone Transmitter-bit init done. 0 Synchronous with 2205 * pipeClk. 2206 * [2] filteredrxlos Filtered loss of signal used 1 to generate 2207 * p2lRxelectidle. Synchronous with pipeClk. 2208 * [1] rxdetectInt Receiver detected 0 2209 * [0] pipeMasterDoneOut Receiver detection valid 0 2210 * 2211 */ 2212 typedef union { 2213 uint32_t value; 2214 struct { 2215 #if defined(_BIG_ENDIAN) 2216 uint32_t data:32; 2217 #else 2218 uint32_t data:32; 2219 #endif 2220 } bits; 2221 } pipe_debug3_t; 2222 2223 2224 /* 2225 * Register: PcieEnhCapHdr 2226 * PCIE Enhanced Capability Header 2227 * Description: PCIE Enhanced Capability Header 2228 * Fields: 2229 * Next Capability Offset (END, no more) 2230 * Capability Version 2231 * PCI Express Enhanced Capability ID (0x1 = Advanced Error 2232 * Reporting) 2233 */ 2234 typedef union { 2235 uint32_t value; 2236 struct { 2237 #if defined(_BIG_ENDIAN) 2238 uint32_t nxt_cap_offset:12; 2239 uint32_t cap_ver:4; 2240 uint32_t pcie_enh_cap_id:16; 2241 #else 2242 uint32_t pcie_enh_cap_id:16; 2243 uint32_t cap_ver:4; 2244 uint32_t nxt_cap_offset:12; 2245 #endif 2246 } bits; 2247 } pcie_enh_cap_hdr_t; 2248 2249 2250 /* 2251 * Register: UncErrStat 2252 * Uncorrectable Error Status 2253 * Description: Uncorrectable Error Status 2254 * Fields: 2255 * Unsupported Request Error 2256 * ECRC Error 2257 * Malformed TLP 2258 * Reciever Overflow 2259 * Unexpected Completion 2260 * Completion Abort 2261 * Completion Timeout 2262 * Flow Control Protocol Error 2263 * Poisoned TLP 2264 * Introduced in PCIe 1.1 specification. 2265 * Data Link Protocol Error 2266 */ 2267 typedef union { 2268 uint32_t value; 2269 struct { 2270 #if defined(_BIG_ENDIAN) 2271 uint32_t rsrvd:11; 2272 uint32_t unsup_req_err:1; 2273 uint32_t ecrc_err:1; 2274 uint32_t bad_tlp:1; 2275 uint32_t rcv_ovfl:1; 2276 uint32_t unexp_cpl:1; 2277 uint32_t cpl_abrt:1; 2278 uint32_t cpl_tmout:1; 2279 uint32_t fc_err:1; 2280 uint32_t psn_tlp:1; 2281 uint32_t rsrvd1:6; 2282 uint32_t surprise_down_err:1; 2283 uint32_t dlp_err:1; 2284 uint32_t rsrvd2:4; 2285 #else 2286 uint32_t rsrvd2:4; 2287 uint32_t dlp_err:1; 2288 uint32_t surprise_down_err:1; 2289 uint32_t rsrvd1:6; 2290 uint32_t psn_tlp:1; 2291 uint32_t fc_err:1; 2292 uint32_t cpl_tmout:1; 2293 uint32_t cpl_abrt:1; 2294 uint32_t unexp_cpl:1; 2295 uint32_t rcv_ovfl:1; 2296 uint32_t bad_tlp:1; 2297 uint32_t ecrc_err:1; 2298 uint32_t unsup_req_err:1; 2299 uint32_t rsrvd:11; 2300 #endif 2301 } bits; 2302 } unc_err_stat_t; 2303 2304 2305 /* 2306 * Register: UncErrMask 2307 * Uncorrectable Error Mask 2308 * Description: Uncorrectable Error Mask 2309 * Fields: 2310 * Unsupported Request Error 2311 * ECRC Error 2312 * Malformed TLP 2313 * Reciever Overflow 2314 * Unexpected Completion 2315 * Completion Abort 2316 * Completion Timeout 2317 * Flow Control Protocol Error 2318 * Poisoned TLP 2319 * Introduced in PCIe 1.1 2320 * Data Link Protocol Error 2321 */ 2322 typedef union { 2323 uint32_t value; 2324 struct { 2325 #if defined(_BIG_ENDIAN) 2326 uint32_t rsrvd:11; 2327 uint32_t unsup_req_err:1; 2328 uint32_t ecrc_err:1; 2329 uint32_t bad_tlp:1; 2330 uint32_t rcv_ovfl:1; 2331 uint32_t unexp_cpl:1; 2332 uint32_t cpl_abrt:1; 2333 uint32_t cpl_tmout:1; 2334 uint32_t fc_err:1; 2335 uint32_t psn_tlp:1; 2336 uint32_t rsrvd1:6; 2337 uint32_t surprise_down_err:1; 2338 uint32_t dlp_err:1; 2339 uint32_t rsrvd2:4; 2340 #else 2341 uint32_t rsrvd2:4; 2342 uint32_t dlp_err:1; 2343 uint32_t surprise_down_err:1; 2344 uint32_t rsrvd1:6; 2345 uint32_t psn_tlp:1; 2346 uint32_t fc_err:1; 2347 uint32_t cpl_tmout:1; 2348 uint32_t cpl_abrt:1; 2349 uint32_t unexp_cpl:1; 2350 uint32_t rcv_ovfl:1; 2351 uint32_t bad_tlp:1; 2352 uint32_t ecrc_err:1; 2353 uint32_t unsup_req_err:1; 2354 uint32_t rsrvd:11; 2355 #endif 2356 } bits; 2357 } unc_err_mask_t; 2358 2359 2360 /* 2361 * Register: UncErrSvrty 2362 * Uncorrectable Error Severity 2363 * Description: Uncorrectable Error Severity 2364 * Fields: 2365 * Unsupported Request Error 2366 * ECRC Error 2367 * Malformed TLP 2368 * Reciever Overflow 2369 * Unexpected Completion 2370 * Completion Abort 2371 * Completion Timeout 2372 * Flow Control Protocol Error 2373 * Poisoned TLP 2374 * Introduced in PCIe 1.1 specification. Not supported; use PCIe 2375 * default. 2376 * Data Link Protocol Error 2377 */ 2378 typedef union { 2379 uint32_t value; 2380 struct { 2381 #if defined(_BIG_ENDIAN) 2382 uint32_t rsrvd:11; 2383 uint32_t unsup_req_err:1; 2384 uint32_t ecrc_err:1; 2385 uint32_t bad_tlp:1; 2386 uint32_t rcv_ovfl:1; 2387 uint32_t unexp_cpl:1; 2388 uint32_t cpl_abrt:1; 2389 uint32_t cpl_tmout:1; 2390 uint32_t fc_err:1; 2391 uint32_t psn_tlp:1; 2392 uint32_t rsrvd1:6; 2393 uint32_t surprise_down_err:1; 2394 uint32_t dlp_err:1; 2395 uint32_t rsrvd2:4; 2396 #else 2397 uint32_t rsrvd2:4; 2398 uint32_t dlp_err:1; 2399 uint32_t surprise_down_err:1; 2400 uint32_t rsrvd1:6; 2401 uint32_t psn_tlp:1; 2402 uint32_t fc_err:1; 2403 uint32_t cpl_tmout:1; 2404 uint32_t cpl_abrt:1; 2405 uint32_t unexp_cpl:1; 2406 uint32_t rcv_ovfl:1; 2407 uint32_t bad_tlp:1; 2408 uint32_t ecrc_err:1; 2409 uint32_t unsup_req_err:1; 2410 uint32_t rsrvd:11; 2411 #endif 2412 } bits; 2413 } unc_err_svrty_t; 2414 2415 2416 /* 2417 * Register: CorrErrStat 2418 * Correctable Error Status 2419 * Description: Correctable Error Status 2420 * Fields: 2421 * Advisory Non-Fatal Error Introduced in PCIe 1.1 specification. 2422 * Reply Timer Timeout 2423 * Replay Number Rollover 2424 * Bad DLLP 2425 * Bad TLP 2426 * Receive Error 2427 */ 2428 typedef union { 2429 uint32_t value; 2430 struct { 2431 #if defined(_BIG_ENDIAN) 2432 uint32_t rsrvd:18; 2433 uint32_t adv_nf_err:1; 2434 uint32_t rply_tmr_tmout:1; 2435 uint32_t rsrvd1:3; 2436 uint32_t rply_rlovr:1; 2437 uint32_t bad_dllp:1; 2438 uint32_t bad_tlp:1; 2439 uint32_t rsrvd2:5; 2440 uint32_t rcv_err:1; 2441 #else 2442 uint32_t rcv_err:1; 2443 uint32_t rsrvd2:5; 2444 uint32_t bad_tlp:1; 2445 uint32_t bad_dllp:1; 2446 uint32_t rply_rlovr:1; 2447 uint32_t rsrvd1:3; 2448 uint32_t rply_tmr_tmout:1; 2449 uint32_t adv_nf_err:1; 2450 uint32_t rsrvd:18; 2451 #endif 2452 } bits; 2453 } corr_err_stat_t; 2454 2455 2456 /* 2457 * Register: CorrErrMask 2458 * Correctable Error Mask 2459 * Description: Correctable Error Mask 2460 * Fields: 2461 * Advisory Non Fatal Error Mask 2462 * Reply Timer Timeout 2463 * Replay Number Rollover 2464 * Bad DLLP 2465 * Bad TLP 2466 * Receive Error 2467 */ 2468 typedef union { 2469 uint32_t value; 2470 struct { 2471 #if defined(_BIG_ENDIAN) 2472 uint32_t rsrvd:18; 2473 uint32_t adv_nf_err_mask:1; 2474 uint32_t rply_tmr_tmout:1; 2475 uint32_t rsrvd1:3; 2476 uint32_t rply_rlovr:1; 2477 uint32_t bad_dllp:1; 2478 uint32_t bad_tlp:1; 2479 uint32_t rsrvd2:5; 2480 uint32_t rcv_err:1; 2481 #else 2482 uint32_t rcv_err:1; 2483 uint32_t rsrvd2:5; 2484 uint32_t bad_tlp:1; 2485 uint32_t bad_dllp:1; 2486 uint32_t rply_rlovr:1; 2487 uint32_t rsrvd1:3; 2488 uint32_t rply_tmr_tmout:1; 2489 uint32_t adv_nf_err_mask:1; 2490 uint32_t rsrvd:18; 2491 #endif 2492 } bits; 2493 } corr_err_mask_t; 2494 2495 2496 /* 2497 * Register: AdvCapCtrl 2498 * Advanced Capability and Control 2499 * Description: Advanced Capability and Control 2500 * Fields: 2501 * ECRC Check Enable 2502 * ECRC Check Capable 2503 * ECRC Generation Enable 2504 * ECRC Generation Capability 2505 * First Error Pointer 2506 */ 2507 typedef union { 2508 uint32_t value; 2509 struct { 2510 #if defined(_BIG_ENDIAN) 2511 uint32_t rsrvd:23; 2512 uint32_t ecrc_chk_en:1; 2513 uint32_t ecrc_chk_cap:1; 2514 uint32_t ecrc_gen_en:1; 2515 uint32_t ecrc_gen_cap:1; 2516 uint32_t st_err_ptr:5; 2517 #else 2518 uint32_t st_err_ptr:5; 2519 uint32_t ecrc_gen_cap:1; 2520 uint32_t ecrc_gen_en:1; 2521 uint32_t ecrc_chk_cap:1; 2522 uint32_t ecrc_chk_en:1; 2523 uint32_t rsrvd:23; 2524 #endif 2525 } bits; 2526 } adv_cap_ctrl_t; 2527 2528 2529 /* 2530 * Register: HdrLog0 2531 * Header Log0 2532 * Description: Header Log0 2533 * Fields: 2534 * First DW of TLP header with error 2535 */ 2536 typedef union { 2537 uint32_t value; 2538 struct { 2539 #if defined(_BIG_ENDIAN) 2540 uint32_t data:32; 2541 #else 2542 uint32_t data:32; 2543 #endif 2544 } bits; 2545 } hdr_log0_t; 2546 2547 2548 /* 2549 * Register: HdrLog1 2550 * Header Log1 2551 * Description: Header Log1 2552 * Fields: 2553 * Second DW of TLP header with error 2554 */ 2555 typedef union { 2556 uint32_t value; 2557 struct { 2558 #if defined(_BIG_ENDIAN) 2559 uint32_t data:32; 2560 #else 2561 uint32_t data:32; 2562 #endif 2563 } bits; 2564 } hdr_log1_t; 2565 2566 2567 /* 2568 * Register: HdrLog2 2569 * Header Log2 2570 * Description: Header Log2 2571 * Fields: 2572 * Third DW of TLP header with error 2573 */ 2574 typedef union { 2575 uint32_t value; 2576 struct { 2577 #if defined(_BIG_ENDIAN) 2578 uint32_t data:32; 2579 #else 2580 uint32_t data:32; 2581 #endif 2582 } bits; 2583 } hdr_log2_t; 2584 2585 2586 /* 2587 * Register: HdrLog3 2588 * Header Log3 2589 * Description: Header Log3 2590 * Fields: 2591 * Fourth DW of TLP header with error 2592 */ 2593 typedef union { 2594 uint32_t value; 2595 struct { 2596 #if defined(_BIG_ENDIAN) 2597 uint32_t data:32; 2598 #else 2599 uint32_t data:32; 2600 #endif 2601 } bits; 2602 } hdr_log3_t; 2603 2604 2605 /* 2606 * Register: PipeRxTxControl 2607 * Pipe Rx/Tx Control 2608 * 00 : ewrap : Enable wrapback test mode 01 : padLoopback : 2609 * Enable Pad Serial Loopback test mode 10 : revLoopback : Enable 2610 * Reverse Loopback test mode 11 : efifoLoopback : Enable PCI 2611 * Express Slave loop back 2612 * 100 : Clock generator test x10 : Vil/Vih test x01 : Vih/Vil 2613 * test x11 : No-error test. A full test of the transceiver 111 : 2614 * Forced-error test. A full test of the transceiver with forced 2615 * errors 2616 * 1 : selects 20-bit mode 0 : selects 10-bit mode 2617 * 1 : selects Tx 20-bit fifo mode 2618 * 00 : 52 us (470 cycles) 01 : 53 us (720 cycles) 10 : 54 us 2619 * (970 cycles) 11 : 55 us (1220 cycles) 2620 * 1 : selects 20-bit mode 0 : selects 10-bit mode 2621 * 1 : Enable receiver reference clocks 2622 */ 2623 typedef union { 2624 uint32_t value; 2625 struct { 2626 #if defined(_BIG_ENDIAN) 2627 uint32_t rsrvd:1; 2628 uint32_t loopback:1; 2629 uint32_t loopback_mode_sel:2; 2630 uint32_t rsrvd1:1; 2631 uint32_t en_bist:3; 2632 uint32_t tdws20:1; 2633 uint32_t tdenfifo:1; 2634 uint32_t rxpreswin:2; 2635 uint32_t rdws20:1; 2636 uint32_t enstretch:1; 2637 uint32_t rsrvd2:18; 2638 #else 2639 uint32_t rsrvd2:18; 2640 uint32_t enstretch:1; 2641 uint32_t rdws20:1; 2642 uint32_t rxpreswin:2; 2643 uint32_t tdenfifo:1; 2644 uint32_t tdws20:1; 2645 uint32_t en_bist:3; 2646 uint32_t rsrvd1:1; 2647 uint32_t loopback_mode_sel:2; 2648 uint32_t loopback:1; 2649 uint32_t rsrvd:1; 2650 #endif 2651 } bits; 2652 } pipe_rx_tx_control_t; 2653 2654 2655 /* 2656 * Register: PipeRxTxStatus 2657 * Pipe Rx/Tx Status 2658 */ 2659 typedef union { 2660 uint32_t value; 2661 struct { 2662 #if defined(_BIG_ENDIAN) 2663 uint32_t rsrvd:32; 2664 #else 2665 uint32_t rsrvd:32; 2666 #endif 2667 } bits; 2668 } pipe_rx_tx_status_t; 2669 2670 2671 /* 2672 * Register: PipeRxTxPwrCntl 2673 * Pipe Rx/Tx Power Control 2674 * 1 : power down termination trimming circuit 0 : normal 2675 * operation 2676 * Power down PECL Clock buffer 1 : when a bit is 1, power down 2677 * associated clock buffer cell 0 : normal operation 2678 * Power down Transmit PLL 1 : when a bit is 1, power down 2679 * associated Tx PLL circuit 0 : normal operation 2680 * Power down Differential O/P Clock buffer 1 : when a bit is 1, 2681 * power down associated differntial clock buffer that drives 2682 * gbtClkoutN/p 0 : normal operation 2683 * Power down Transmitter Analog section 1 : when a bit is 1, 2684 * power down analog section of the associated Transmitter and 2685 * the Tx buffer 0 : normal operation 2686 * Power down RxLOS 1 : when a bit is 1, it powers down the Rx 2687 * LOS circuitry for the associated serdes lanes 0 : normal 2688 * operation 2689 * Power down Receiver Analog section 1 : when a bit is 1, power 2690 * down analog section of the associated Receiver and the Tx 2691 * buffer 0 : normal operation 2692 */ 2693 typedef union { 2694 uint32_t value; 2695 struct { 2696 #if defined(_BIG_ENDIAN) 2697 uint32_t rsrvd:1; 2698 uint32_t pdrtrim:1; 2699 uint32_t pdownpecl:2; 2700 uint32_t pdownpll:2; 2701 uint32_t pdclkout:2; 2702 uint32_t pdownt:8; 2703 uint32_t pdrxlos:8; 2704 uint32_t pdownr:8; 2705 #else 2706 uint32_t pdownr:8; 2707 uint32_t pdrxlos:8; 2708 uint32_t pdownt:8; 2709 uint32_t pdclkout:2; 2710 uint32_t pdownpll:2; 2711 uint32_t pdownpecl:2; 2712 uint32_t pdrtrim:1; 2713 uint32_t rsrvd:1; 2714 #endif 2715 } bits; 2716 } pipe_rx_tx_pwr_cntl_t; 2717 2718 2719 /* 2720 * Register: PipeRxTxParam 2721 * Pipe Rx/Tx Parameter 2722 * Tx Driver Emphasis 2723 * Serial output Slew Rate Control 2724 * Tx Voltage Mux control 2725 * Tx Voltage Pulse control 2726 * Output Swing setting 2727 * Transmitter Clock generator pole adjust 2728 * Transmitter Clock generator zero adjust 2729 * Receiver Clock generator pole adjust 2730 * Receiver Clock generator zero adjust 2731 * Bias Control for factory testing and debugging 2732 * Receiver LOS Threshold adjustment. This value is determined by 2733 * LSI. 2734 * Receiver Input Equalizer control 2735 */ 2736 typedef union { 2737 uint32_t value; 2738 struct { 2739 #if defined(_BIG_ENDIAN) 2740 uint32_t rsrvd:1; 2741 uint32_t emph:3; 2742 uint32_t rsrvd1:1; 2743 uint32_t risefall:3; 2744 uint32_t vmuxlo:2; 2745 uint32_t vpulselo:2; 2746 uint32_t vtxlo:4; 2747 uint32_t tp:2; 2748 uint32_t tz:2; 2749 uint32_t rp:2; 2750 uint32_t rz:2; 2751 uint32_t biascntl:1; 2752 uint32_t losadj:3; 2753 uint32_t rxeq:4; 2754 #else 2755 uint32_t rxeq:4; 2756 uint32_t losadj:3; 2757 uint32_t biascntl:1; 2758 uint32_t rz:2; 2759 uint32_t rp:2; 2760 uint32_t tz:2; 2761 uint32_t tp:2; 2762 uint32_t vtxlo:4; 2763 uint32_t vpulselo:2; 2764 uint32_t vmuxlo:2; 2765 uint32_t risefall:3; 2766 uint32_t rsrvd1:1; 2767 uint32_t emph:3; 2768 uint32_t rsrvd:1; 2769 #endif 2770 } bits; 2771 } pipe_rx_tx_param_t; 2772 2773 2774 /* 2775 * Register: PipeRxTxClock 2776 * Pipe Rx/Tx Clock 2777 * Reverse Loopback clock select 00 : gbtRbcAO 01 : gbtRbcBO 10 : 2778 * gbtRbcCO 11 : gbtRbcDO 2779 * Select Master Clock 100 : All lanes 000 : Lane A 001 : Lane B 2780 * 010 : Lane C 011 : Lane D 2781 * Transmit PLL Divider control 2782 * Transmit Data rate control 2783 * Receiver PLL Frequency control 2784 * Bit rate control to enable bit doubling feature 2785 * Reset Transmitter lane 2786 * Reset Receiver lane 2787 */ 2788 typedef union { 2789 uint32_t value; 2790 struct { 2791 #if defined(_BIG_ENDIAN) 2792 uint32_t rsrvd:2; 2793 uint32_t revlbrefsel:2; 2794 uint32_t rsrvd1:1; 2795 uint32_t tdmaster:3; 2796 uint32_t fbdivt:3; 2797 uint32_t half_ratet:1; 2798 uint32_t fbdivr:3; 2799 uint32_t half_rater:1; 2800 uint32_t txreset:8; 2801 uint32_t rxreset:8; 2802 #else 2803 uint32_t rxreset:8; 2804 uint32_t txreset:8; 2805 uint32_t half_rater:1; 2806 uint32_t fbdivr:3; 2807 uint32_t half_ratet:1; 2808 uint32_t fbdivt:3; 2809 uint32_t tdmaster:3; 2810 uint32_t rsrvd1:1; 2811 uint32_t revlbrefsel:2; 2812 uint32_t rsrvd:2; 2813 #endif 2814 } bits; 2815 } pipe_rx_tx_clock_t; 2816 2817 2818 /* 2819 * Register: PipeGlueCntl0 2820 * Pipe Glue Control 0 2821 * Lock to Bitstream Initialization Time 2822 * RXLOS Test bit 2823 * Electrical Idle Ordered set enable 2824 * Enable RxLOS 2825 * Enable Fast resync 2826 * RxLOS Sample Interval 2827 * RxLOS threshold 2828 */ 2829 typedef union { 2830 uint32_t value; 2831 struct { 2832 #if defined(_BIG_ENDIAN) 2833 uint32_t bitlocktime:16; 2834 uint32_t rxlos_test:1; 2835 uint32_t eiosenable:1; 2836 uint32_t rxlosenable:1; 2837 uint32_t fastresync:1; 2838 uint32_t samplerate:4; 2839 uint32_t thresholdcount:8; 2840 #else 2841 uint32_t thresholdcount:8; 2842 uint32_t samplerate:4; 2843 uint32_t fastresync:1; 2844 uint32_t rxlosenable:1; 2845 uint32_t eiosenable:1; 2846 uint32_t rxlos_test:1; 2847 uint32_t bitlocktime:16; 2848 #endif 2849 } bits; 2850 } pipe_glue_cntl0_t; 2851 2852 2853 /* 2854 * Register: PipeGlueCntl1 2855 * Pipe Glue Control 1 2856 * Receiver Trim Resistance Configuration 2857 * Transmitter Trim Resistance Configuration 2858 * Auto Trim Enable 2859 * 50 Ohm Termination Enable 2860 * Customer select for reference clock frequency 2861 * EFIFO Same clock select 2862 * EFIFO start depth 2863 * Lock to refclk initialization time 2864 */ 2865 typedef union { 2866 uint32_t value; 2867 struct { 2868 #if defined(_BIG_ENDIAN) 2869 uint32_t termrcfg:2; 2870 uint32_t termtcfg:2; 2871 uint32_t rtrimen:1; 2872 uint32_t ref50:1; 2873 uint32_t freq_sel:1; 2874 uint32_t same_sel:1; 2875 uint32_t rsrvd:1; 2876 uint32_t start_efifo:3; 2877 uint32_t rsrvd1:2; 2878 uint32_t inittime:18; 2879 #else 2880 uint32_t inittime:18; 2881 uint32_t rsrvd1:2; 2882 uint32_t start_efifo:3; 2883 uint32_t rsrvd:1; 2884 uint32_t same_sel:1; 2885 uint32_t freq_sel:1; 2886 uint32_t ref50:1; 2887 uint32_t rtrimen:1; 2888 uint32_t termtcfg:2; 2889 uint32_t termrcfg:2; 2890 #endif 2891 } bits; 2892 } pipe_glue_cntl1_t; 2893 2894 2895 /* 2896 * Register: HcrReg 2897 * HCR Registers 2898 * Description: Hydra Specific Configuration Registers for use by 2899 * software. These registers are loaded with the SPROM contents at 2900 * power on. A maximum of 128 DWords has been assigned for s/w to 2901 * use. This space generally stores the following informations : MAC 2902 * Address Number of MAC addresses MAC Phy Type Other data fields are 2903 * upto the software to use. 2904 * 2905 * Fields: 2906 * Hydra specific configuration controlled by software 2907 */ 2908 typedef union { 2909 uint32_t value; 2910 struct { 2911 #if defined(_BIG_ENDIAN) 2912 uint32_t hcr_val:32; 2913 #else 2914 uint32_t hcr_val:32; 2915 #endif 2916 } bits; 2917 } hcr_reg_t; 2918 2919 2920 /* 2921 * Register: BlockReset 2922 * Block Reset 2923 * Description: Soft resets to modules. Blade domain modules are 2924 * reset by setting the corresponding block reset to 1. Shared domain 2925 * resets are sent to SPI for processing and corresponding action by 2926 * SPI. Shared domains are reset only if all the blades have 2927 * requested a reset for that block. Below is an example scenario : 2928 * s/w initiates the reset by writing '1' to the dpmRst bit dpmRst 2929 * bit remains '1' until dpmRstStat is detected to be 1. Once 2930 * dpmRstStat is detected to be 1, even if s/w writes 1 to this bit 2931 * again no new reset will be initiated to the shared domain, ie, 2932 * DPM. dpmRstStat is driven by external i/f (shared domain status 2933 * provided by SPI) dpmRstStat bit will show '1' as long as the input 2934 * stays at 1 or until s/w reads the status and is cleared only after 2935 * s/w reads it and if dpmRstStat is 0 by then. 2936 * If Host wants to reset entire Hydra it should do so through the 2937 * mailbox. In this case, the message interprettation is upto the 2938 * software. Writing a '1' to any of these bits generates a single 2939 * pulse to the SP module which then controls the reset of the 2940 * respective block. 2941 * 2942 * Fields: 2943 * 1 : indicates that an active reset has been applied to the SP 2944 * based on the request from all of the blades. Clears on Read 2945 * provided the reset to SP has been deasserted by then by SPI. 2946 * Setting to 1 allows this blade to request Service Processor 2947 * (Shared) reset. However, SP reset can only occur if all blades 2948 * agree. The success of reset request is indicated by spRstStat 2949 * = 1 which is wired-AND of request from all the blades. Current 2950 * request can be removed by writing a '0' to this bit. This bit 2951 * clears automatically on detecting spRstStat = 1. 2952 * Enable blade to service processor (Shared) reset voter 2953 * registration = 1, disabled = 0 2954 * Issue power reset to the EP Core Clears to 0, writing 0 has no 2955 * effect. 2956 * Issue core reset to the EP Core Clears to 0, writing 0 has no 2957 * effect. 2958 * Issue system reset (sysPor) to the PIPE Core This issues reset 2959 * to the EP core, PCIe domains of Tdc, Rdc, and CIP. This shuts 2960 * down the PCIe clock until Pipe core comes out of reset. The 2961 * status of the Pipe core can be read by reading out the 2962 * cipLinkStat register's pipe core status and pcie reset status 2963 * bits. Clears to 0, writing 0 has no effect. 2964 * 1 : indicates that an active reset has been applied to the 2965 * NMAC based on the request from all of the blades. Clears on 2966 * Read provided the reset to NMAC has been deasserted by then by 2967 * SPI. 2968 * 1 : indicates that an active reset has been applied to the TDP 2969 * based on the request from all of the blades. Clears on Read 2970 * provided the reset to TDP has been deasserted by then by SPI. 2971 * 1 : indicates that an active reset has been applied to the DPM 2972 * based on the request from all of the blades. Clears on Read 2973 * provided the reset to DPM has been deasserted by then by SPI. 2974 * This bit is effective only if sharedVoterEn (bit 24 of this 2975 * reg) has been enabled. Writing '1' sends a request to SP to 2976 * reset NMAC if sharedVoterEn=1. Intended for backdoor access. 2977 * The success of reset request is indicated by nmacRstStat = 1 2978 * which is wired-AND of request from all the blades. This also 2979 * means that the reset request is successful only if all the 2980 * blades requested for reset of this block. Current request can 2981 * be removed by writing a '0' to this bit. This bit clears 2982 * automatically on detecting nmacRstStat = 1. 2983 * This bit is effective only if sharedVoterEn (bit 24 of this 2984 * reg) has been enabled. Writing '1' sends a request to SP to 2985 * reset TDP if sharedVoterEn=1. Intended for backdoor access. 2986 * Intended for backdoor access. The success of reset request is 2987 * indicated by tdpRstStat = 1 which is wired-AND of request from 2988 * all the blades. This also means that the reset request is 2989 * successful only if all the blades requested for reset of this 2990 * block. Current request can be removed by writing a '0' to this 2991 * bit. This bit clears automatically on detecting tdpRstStat = 2992 * 1. 2993 * This bit is effective only if sharedVoterEn (bit 24 of this 2994 * reg) has been enabled. Writing '1' sends a request to SP to 2995 * reset DPM if sharedVoterEn=1. Intended for backdoor access. 2996 * Intended for backdoor access. The success of reset request is 2997 * indicated by dpmRstStat = 1 which is wired-AND of request from 2998 * all the blades. This also means that the reset request is 2999 * successful only if all the blades requested for reset of this 3000 * block. Current request can be removed by writing a '0' to this 3001 * bit. This bit clears automatically on detecting dpmRstStat = 3002 * 1. 3003 * Setting to 1 generates tdcCoreReset and tdcPcieReset to the 3004 * TDC block. The reset will stay asserted for atleast 4 clock 3005 * cycles. Clears to 0, writing 0 has no effect. 3006 * Setting to 1 generates rdcCoreReset and rdcPcieReset to the 3007 * RDC block. The reset will stay asserted for atleast 4 clock 3008 * cycles. Clears to 0, writing 0 has no effect. 3009 * Setting to 1 generates reset to the PFC block. The reset will 3010 * stay asserted for atleast 4 clock cycles. Clears to 0, writing 3011 * 0 has no effect. 3012 * Setting to 1 generates reset to the VMAC block. The reset will 3013 * stay asserted for atleast 4 clock cycles. Clears to 0, writing 3014 * 0 has no effect. 3015 */ 3016 typedef union { 3017 uint32_t value; 3018 struct { 3019 #if defined(_BIG_ENDIAN) 3020 uint32_t rsrvd:13; 3021 uint32_t sp_rst_stat:1; 3022 uint32_t sp_rst:1; 3023 uint32_t shared_voter_en:1; 3024 uint32_t epcore_pwr_rst:1; 3025 uint32_t epcore_core_rst:1; 3026 uint32_t pipe_sys_rst:1; 3027 uint32_t nmac_rst_stat:1; 3028 uint32_t tdp_rst_stat:1; 3029 uint32_t dpm_rst_stat:1; 3030 uint32_t rsrvd1:1; 3031 uint32_t nmac_rst:1; 3032 uint32_t tdp_rst:1; 3033 uint32_t dpm_rst:1; 3034 uint32_t rsrvd2:1; 3035 uint32_t tdc_rst:1; 3036 uint32_t rdc_rst:1; 3037 uint32_t pfc_rst:1; 3038 uint32_t vmac_rst:1; 3039 uint32_t rsrvd3:1; 3040 #else 3041 uint32_t rsrvd3:1; 3042 uint32_t vmac_rst:1; 3043 uint32_t pfc_rst:1; 3044 uint32_t rdc_rst:1; 3045 uint32_t tdc_rst:1; 3046 uint32_t rsrvd2:1; 3047 uint32_t dpm_rst:1; 3048 uint32_t tdp_rst:1; 3049 uint32_t nmac_rst:1; 3050 uint32_t rsrvd1:1; 3051 uint32_t dpm_rst_stat:1; 3052 uint32_t tdp_rst_stat:1; 3053 uint32_t nmac_rst_stat:1; 3054 uint32_t pipe_sys_rst:1; 3055 uint32_t epcore_core_rst:1; 3056 uint32_t epcore_pwr_rst:1; 3057 uint32_t shared_voter_en:1; 3058 uint32_t sp_rst:1; 3059 uint32_t sp_rst_stat:1; 3060 uint32_t rsrvd:13; 3061 #endif 3062 } bits; 3063 } block_reset_t; 3064 3065 3066 /* 3067 * Register: TimeoutCfg 3068 * PIO Timeout Configuration 3069 * Description: PIO Timeout Configuration register to control wait 3070 * time for a PIO access to complete. The timer resolution is in 250 3071 * MHz clock. 3072 * Fields: 3073 * Programmable timeout counter value for PIO clients who did not 3074 * ack a transaction in time. Minimum value should be 64. 3075 * Timeout enable for PIO access to clients. 1 = enable. 3076 */ 3077 typedef union { 3078 uint32_t value; 3079 struct { 3080 #if defined(_BIG_ENDIAN) 3081 uint32_t rsrvd:21; 3082 uint32_t tmout_cnt:10; 3083 uint32_t tmout_en:1; 3084 #else 3085 uint32_t tmout_en:1; 3086 uint32_t tmout_cnt:10; 3087 uint32_t rsrvd:21; 3088 #endif 3089 } bits; 3090 } timeout_cfg_t; 3091 3092 3093 /* 3094 * Register: HeartCfg 3095 * PIO Heartbeat Config 3096 * Description: PIO Blade presence indication : Heartbeat 3097 * configuration The timer resolution is in 250 MHz clock. 3098 * Fields: 3099 * Heartbeat countdown 250Mhz clock divider which serves as 3100 * resolution for the heartTimer. 3101 * Heartbeat countdown enable 3102 */ 3103 typedef union { 3104 uint32_t value; 3105 struct { 3106 #if defined(_BIG_ENDIAN) 3107 uint32_t divider:28; 3108 uint32_t rsrvd:3; 3109 uint32_t en:1; 3110 #else 3111 uint32_t en:1; 3112 uint32_t rsrvd:3; 3113 uint32_t divider:28; 3114 #endif 3115 } bits; 3116 } heart_cfg_t; 3117 3118 3119 /* 3120 * Register: HeartTimer 3121 * PIO Heartbeat Timer 3122 * Description: PIO Blade presence indication : Heartbeat timer The 3123 * timer resolution is in 250 MHz clock. 3124 * Fields: 3125 * Number of heartCfg.divider ticks of the 250Mhz clock before 3126 * blade presence expires. This register decrements for every 3127 * heartCfg.divider number of 250MHz clock cycles. It expires to 3128 * 0 and so must be written periodically to reset the timer back 3129 * to the required value. This counter does not have any effect 3130 * on CIP functionality. 3131 */ 3132 typedef union { 3133 uint32_t value; 3134 struct { 3135 #if defined(_BIG_ENDIAN) 3136 uint32_t timer:32; 3137 #else 3138 uint32_t timer:32; 3139 #endif 3140 } bits; 3141 } heart_timer_t; 3142 3143 3144 /* 3145 * Register: CipGpCtrl 3146 * CIP General Purpose Control Register 3147 */ 3148 typedef union { 3149 uint32_t value; 3150 struct { 3151 #if defined(_BIG_ENDIAN) 3152 uint32_t rsrvd:30; 3153 uint32_t dma_override_relaxord:1; 3154 uint32_t dma_override_nosnoop:1; 3155 #else 3156 uint32_t dma_override_nosnoop:1; 3157 uint32_t dma_override_relaxord:1; 3158 uint32_t rsrvd:30; 3159 #endif 3160 } bits; 3161 } cip_gp_ctrl_t; 3162 3163 3164 /* 3165 * Register: CipStatus 3166 * CIP Status 3167 * Description: This register returns CIP block's current logic 3168 * status 3169 * Fields: 3170 * Current state of the cipEpc state machine 00 : epIdle ( wait 3171 * for EEPROM request from SP or Host ) 01 : waitAck0 ( wait for 3172 * ack from EEPROM for the first 16 bit read of the DW access ) 3173 * 11 : waitAck1 ( wait for ack from EEPROM for the second 16 bit 3174 * read of the DW access ) 10 : UNDEFINED ( Undefined/Unused 3175 * state; EPC is never expected to be in this state ) 3176 * Current state of the cipSpc state machine 000 : spReset ( wait 3177 * for Power-On SPROM download to start) 001 : getAddr ( Get 3178 * CfgReg Address ) 010 : getData ( Get CfgReg Data ) 011 : 3179 * ignoreData ( Address phase had an error, so ignore the Data 3180 * coming in ) 100 : idleCyc ( Idle cycle following an AHB 3181 * Address phase ) 101 : waitAck0 ( Wait for ack from EP Core 3182 * during SPROM Download ) 110 : waitAck1 ( Wait for ack from EP 3183 * Core during register read/write ) 111 : NORMAL ( SPROM 3184 * Download/Register read/write access completed and wait for 3185 * SP/Host initiated PCI/AHB/HCR read/write ) 3186 * PCI Bus Number as reported by EP core 3187 * PCI Bus Device Number as reported by EP core 3188 * 1: current csr access in progress is Local CIP csr access 3189 * 1: current csr access in progress is Blade Domain csr access 3190 * 1: a 64 bit blade domain access is in progress as two 32 bit 3191 * accesses 3192 * 1: indicates config values were downloaded from SPROM 3193 * 1: indicates non-zero number of HCR config values downloaded 3194 * from SPROM 3195 * 1: indicates non-zero number of PCI config values downloaded 3196 * from SPROM 3197 * 1: indicates non-zero number of Pipe config values downloaded 3198 * from SPROM 3199 */ 3200 typedef union { 3201 uint32_t value; 3202 struct { 3203 #if defined(_BIG_ENDIAN) 3204 uint32_t rsrvd:7; 3205 uint32_t cip_epc_sm:2; 3206 uint32_t cip_spc_sm:3; 3207 uint32_t pbus_num:8; 3208 uint32_t pbus_dev_num:5; 3209 uint32_t loc_csr_access:1; 3210 uint32_t bd_csr_access:1; 3211 uint32_t d64_in_progress:1; 3212 uint32_t spc_dnld_done:1; 3213 uint32_t hcr_nz_cfg:1; 3214 uint32_t pci_nz_cfg:1; 3215 uint32_t pipe_nz_cfg:1; 3216 #else 3217 uint32_t pipe_nz_cfg:1; 3218 uint32_t pci_nz_cfg:1; 3219 uint32_t hcr_nz_cfg:1; 3220 uint32_t spc_dnld_done:1; 3221 uint32_t d64_in_progress:1; 3222 uint32_t bd_csr_access:1; 3223 uint32_t loc_csr_access:1; 3224 uint32_t pbus_dev_num:5; 3225 uint32_t pbus_num:8; 3226 uint32_t cip_spc_sm:3; 3227 uint32_t cip_epc_sm:2; 3228 uint32_t rsrvd:7; 3229 #endif 3230 } bits; 3231 } cip_status_t; 3232 3233 3234 /* 3235 * Register: CipLinkStat 3236 * Link Status Register 3237 * Description: This register returns the Link status 3238 * Fields: 3239 * NMAC XPCS-2 Link Status 3240 * NMAC XPCS-1 Link Status 3241 * NMAC XPCS-0 Link Status 3242 * '1' indicates that pipe core went down suddenly when its reset 3243 * sources are at deactivated level. When this happens, the PCIe 3244 * domain logics are reset including the EP core, TDC/RDC PCIe 3245 * domains. All these logics, EP Core, and the pipe core are held 3246 * at reset until s/w writes 1 to this bit to clear status which 3247 * will also bring the PCIe domain out of reset 3248 * pipe core clock & reset status 1: core is up & running, ie, 3249 * PIPE core is out of reset and clock is ON 3250 * PCIe domain reset status 1: PCIe domain logics including EP 3251 * core are out of reset; This also implies that PCIe clock is up 3252 * and running 3253 * EP Core XDM Link State 3254 * EP Core RDM Link State 3255 * EP Core LTSSM State 3256 */ 3257 typedef union { 3258 uint32_t value; 3259 struct { 3260 #if defined(_BIG_ENDIAN) 3261 uint32_t rsrvd:13; 3262 uint32_t xpcs2_link_up:1; 3263 uint32_t xpcs1_link_up:1; 3264 uint32_t xpcs0_link_up:1; 3265 uint32_t rsrvd1:6; 3266 uint32_t surprise_pipedn:1; 3267 uint32_t pipe_core_stable:1; 3268 uint32_t pcie_domain_stable:1; 3269 uint32_t xmlh_link_up:1; 3270 uint32_t rdlh_link_up:1; 3271 uint32_t xmlh_ltssm_state:5; 3272 #else 3273 uint32_t xmlh_ltssm_state:5; 3274 uint32_t rdlh_link_up:1; 3275 uint32_t xmlh_link_up:1; 3276 uint32_t pcie_domain_stable:1; 3277 uint32_t pipe_core_stable:1; 3278 uint32_t surprise_pipedn:1; 3279 uint32_t rsrvd1:6; 3280 uint32_t xpcs0_link_up:1; 3281 uint32_t xpcs1_link_up:1; 3282 uint32_t xpcs2_link_up:1; 3283 uint32_t rsrvd:13; 3284 #endif 3285 } bits; 3286 } cip_link_stat_t; 3287 3288 3289 /* 3290 * Register: EpcStat 3291 * EEPROM PIO Status 3292 * Description: EEPROM PIO Status The Host may initiate access to the 3293 * EEPROM either thru this register or directly by TRGT1 interfaces 3294 * using ROM BAR access. Note that since the EEPROM can be accessed 3295 * by either Host or SP, access must be granted to the PEU using the 3296 * SPI PROM Control Register eepromPeuEn bit for proper operation. 3297 * All EEPROM accesses initiated from either the Host or SP are 3298 * always acknowledged. If a Host access is not acknowledged, then 3299 * check the SPI PROM Control Register eepromPeuEn bit to make sure 3300 * the PEU to EEPROM access has been enabled. Meanwhile, Host read 3301 * and write accesses through the TRGT1 interface may be held up 3302 * waiting for the acknowledgement. Thus, in order to recover from 3303 * any faulty/stuck condition due to the blocked EEPROM accesses, the 3304 * SP should configure the epcGotoNormal bit in the epcStat register. 3305 * When Host accesses are stuck, only the SP can write into this bit 3306 * to recover from this condition. 3307 * The EEPROM is 1M x 16 bits or 2M bytes. The read address in bits 3308 * [22:2] is byte address. The EEPROM access can only be DW access. 3309 * While accessing through these registers, the lower 2 bits of the 3310 * specified address is ignored resulting in a DW access to the 3311 * EEPROM controller. While accessing through the ROM BAR range, only 3312 * DW accesses are accepted and all other accesses will result in 3313 * error status returned to the host. 3314 * The read will initiate two reads to the EPC and the accumulated 3315 * 32 bit data is returned to the Host either via the Client2 bus or 3316 * in the epcData register depending on the cause of the transaction. 3317 * This means, a read addr=0,1,2,3 will return data from EPC 3318 * locations 0 & 1 which are 16 bits each, and a read to addr=4,5,6,7 3319 * will return data from EPC locations 2,3 which are 16 bits each. 3320 * Some examples for the address translation : 1) when Host gives 3321 * address 0x0000, it means to get bytes 0,1,2, and 3 from the 3322 * EEPROM. These bytes are stored at locations 0x0000 (bytes 0,1) and 3323 * 0x0001 (bytes 2,3) in EEPROM. Hence PEU will present address 3324 * 0x0000 followed by 0x0001 to the EEPROM. 3325 * 2) when Host gives address 0x0004, it means to get bytes 4,5,6, 3326 * and 7 from the EEPROM. These bytes are stored at locations 0x0002 3327 * (bytes 4,5) and 0x0003 (bytes 6,7) in EEPROM. Hence PEU will 3328 * present address 0x0002 followed by 0x0003 to the EEPROM. 3329 * etc .. 3330 * 3331 * Fields: 3332 * Force the EPC state machine to go to epIdle state. This bit is 3333 * used to force the EPC to skip the reading of the EEPROM and 3334 * goto the epIdle state which is normal state for EPC. The bit 3335 * is auto-cleared after switching to the epIdle state. Both SP 3336 * and HOST can write into this bit. However care must be taken 3337 * writing '1' into this bit since setting this bit will flush 3338 * out any pending EEPROM access request from Host. Hence, this 3339 * bit should be used only if the EPC State machine (cipEpcSm 3340 * bits in cipStatus register) is stuck at a non-zero state. 3341 * EEPROM Byte Address for read operation This field can be 3342 * updated only if there is no pending EEPROM read access. 3343 * Software should poll bit 0 of this register (epcRdInit) to 3344 * make sure that it is '0' before writing into this. If polled 3345 * epcRdInit value is '1', then write to epcAddr field is 3346 * ignored. This is to safe-guard the epcAddr value which is 3347 * being read out the EEPROM. 3348 * Read access completion status; set to '0' for successful 3349 * completion by EPC set to '1' to indicate read access error 3350 * from EPC 3351 * Note: Currently, the EEPROM controller in Hydra does not 3352 * return any error condition, ie, epcPeuErr = 1'b0 always. And 3353 * so, for the PIO read access by the Host, the epcStat register 3354 * in PEU will always show that the access was successful. For 3355 * EEPROM read initiated through the ROM BAR by the Host, CIP 3356 * will always return Successful Completion status to the Host. 3357 * Any error situation is reported only in the Status Register 3358 * within the EEPROM device. For access information about this 3359 * register, please refer to the EEPROM/SPI PRMs. 3360 * 3361 * Read Initiate. SW writes 1 to this bit to initiate a EEPROM 3362 * read. Clears to 0 on updating the epcData reg. Writing 0 has 3363 * no effect. 3364 */ 3365 typedef union { 3366 uint32_t value; 3367 struct { 3368 #if defined(_BIG_ENDIAN) 3369 uint32_t epc_goto_normal:1; 3370 uint32_t rsrvd:8; 3371 uint32_t epc_addr:21; 3372 uint32_t epc_cpl_stat:1; 3373 uint32_t epc_rd_init:1; 3374 #else 3375 uint32_t epc_rd_init:1; 3376 uint32_t epc_cpl_stat:1; 3377 uint32_t epc_addr:21; 3378 uint32_t rsrvd:8; 3379 uint32_t epc_goto_normal:1; 3380 #endif 3381 } bits; 3382 } epc_stat_t; 3383 3384 3385 /* 3386 * Register: EpcData 3387 * EEPROM PIO Data 3388 * Description: EEPROM PIO Data The data returned from EEPROM 3389 * controller for the EEPROM access initiated by the EEPROM PIO 3390 * Status register is returned in this register. 3391 * Fields: 3392 * EEPROM Read Data; valid when rdInit transitioned from 1 to 0. 3393 */ 3394 typedef union { 3395 uint32_t value; 3396 struct { 3397 #if defined(_BIG_ENDIAN) 3398 uint32_t eeprom_data:32; 3399 #else 3400 uint32_t eeprom_data:32; 3401 #endif 3402 } bits; 3403 } epc_data_t; 3404 3405 3406 /* 3407 * Register: SpcStat 3408 * SPROM PIO Status 3409 * Description: SPROM PIO Status 3410 * Fields: 3411 * Force the SPC state machine to go to NORMAL state. This bit is 3412 * used to force the SPC to skip the downloading of the SPROM 3413 * contents into the EP/Pipe/Hcr registers. Setting this bit will 3414 * make CIP to drop any pending requests to the DBI/AHB buses. 3415 * The bit is auto-cleared after switching to the Normal state. 3416 * This bit can not be used to terminate a pio access to 3417 * PCI/PIPE/HCR registers. If a pio access to these registers is 3418 * not responded to, by the respective block, then the pio access 3419 * will automatically timeout. The timeout value is specified by 3420 * the timeoutCfg:tmoutCnt value 3421 */ 3422 typedef union { 3423 uint32_t value; 3424 struct { 3425 #if defined(_BIG_ENDIAN) 3426 uint32_t rsrvd:29; 3427 uint32_t spc_goto_normal:1; 3428 uint32_t rsrvd1:2; 3429 #else 3430 uint32_t rsrvd1:2; 3431 uint32_t spc_goto_normal:1; 3432 uint32_t rsrvd:29; 3433 #endif 3434 } bits; 3435 } spc_stat_t; 3436 3437 3438 /* 3439 * Register: Host2spiIndaccAddr 3440 * HOST -> SPI Shared Domain Read Address 3441 * Description: Read address set by Host for indirect access to 3442 * shared domain address space The decoding of the address is as 3443 * follows: [23:20] - block select [19:0] - register offset from base 3444 * address of block 3445 * Fields: 3446 * Address in Shared domain 3447 */ 3448 typedef union { 3449 uint32_t value; 3450 struct { 3451 #if defined(_BIG_ENDIAN) 3452 uint32_t rsrvd:8; 3453 uint32_t addr:24; 3454 #else 3455 uint32_t addr:24; 3456 uint32_t rsrvd:8; 3457 #endif 3458 } bits; 3459 } host2spi_indacc_addr_t; 3460 3461 3462 /* 3463 * Register: Host2spiIndaccCtrl 3464 * HOST -> SPI Shared Domain Read Control 3465 * Description: Control word set by Host for indirect access to the 3466 * shared domain address space Writing to this register initiates the 3467 * indirect access to the shared domain. 3468 * The Host may read or write to a shared domain region data as 3469 * below : Host updates the host2spiIndaccAddr register with address 3470 * of the shared domain reg. For writes, Host updates the 3471 * host2spiIndaccData register with write data Host then writes to 3472 * bit 0 of host2spiIndaccCtrl register to '1' or '0' to initiate the 3473 * read or write access; 1 : write command, 0 : read command Host 3474 * should then poll bit 1 of host2spiIndaccCtrl register for the 3475 * access status. 1 : access is done, 0 : access is in progress 3476 * (busy) Host should then check bit 2 of host2spiIndaccCtrl register 3477 * to know if the command was successful; 1 : access error, 0 : 3478 * access successful For reads, Host then reads the 3479 * host2spiIndaccData register for the read data. 3480 * This register can be written into only when there is no pending 3481 * access, ie, indaccCtrl.cplStat=1. Writes when indaccCtrl.cplStat=0 3482 * is ignored. 3483 * 3484 * Fields: 3485 * command completion status; 0 : successful completion of 3486 * command by SPI 1 : access error from SPI 3487 * command progress status; 0 : access is in progress (busy) 1 : 3488 * access is done 3489 * 1 : Initiate a write access 0 : Initiate a read access 3490 */ 3491 typedef union { 3492 uint32_t value; 3493 struct { 3494 #if defined(_BIG_ENDIAN) 3495 uint32_t rsrvd:29; 3496 uint32_t err_stat:1; 3497 uint32_t cpl_stat:1; 3498 uint32_t rd_wr_cmd:1; 3499 #else 3500 uint32_t rd_wr_cmd:1; 3501 uint32_t cpl_stat:1; 3502 uint32_t err_stat:1; 3503 uint32_t rsrvd:29; 3504 #endif 3505 } bits; 3506 } host2spi_indacc_ctrl_t; 3507 3508 3509 /* 3510 * Register: Host2spiIndaccData 3511 * HOST -> SPI Shared Domain Read/Write Data 3512 * Description: For indirect read access by the Host, this register 3513 * returns the data returned from the Shared Domain For indirect 3514 * write access by the Host, the host should update this register 3515 * with the writeData for the Shared Domain, before writing to the 3516 * host2spiIndaccCtrl register to initiate the access. 3517 * This register can be written into only when there is no pending 3518 * access, ie, indaccCtrl.cplStat=1. Writes when indaccCtrl.cplStat=0 3519 * is ignored. 3520 * 3521 * Fields: 3522 * Shared domain read/write data 3523 */ 3524 typedef union { 3525 uint32_t value; 3526 struct { 3527 #if defined(_BIG_ENDIAN) 3528 uint32_t data:32; 3529 #else 3530 uint32_t data:32; 3531 #endif 3532 } bits; 3533 } host2spi_indacc_data_t; 3534 3535 3536 /* 3537 * Register: BtCtrl0 3538 * Mailbox Control & Access status 0 3539 * Description: Host (blade) <-> SP Block Transfer mailbox control 3540 * and access status register 0. 3541 * Host is allowed 8 bits read/write access to this register ; To do 3542 * the same, it should provide the btCtrl0 address, data on 3543 * hostDataBus[7:0], and assert hostBen[0], SPI is allowed 8 bits 3544 * read/write access to this register ; To do the same, it should 3545 * provide the btCtrl0 address, data on spiDataBus[7:0], and no need 3546 * of spiBen 3547 * 3548 * Fields: 3549 * The SP sets/clears this bit to indicate if it is busy and can 3550 * not accept any other request; write 1 to toggle the bit; Read 3551 * Only by Host. 3552 * The Host sets/clears this bit to indicate if it is busy and 3553 * can not accept any other request; Read Only by SP. 3554 * Reserved for definition by platform. Typical usage could be 3555 * "heartbeat" mechanism from/to the host. The host sets OEM0 to 3556 * interrupt the SP and then polls it to be cleared by SP 3557 * The SP sets this bit when it has detected and queued an SMS 3558 * message in the SP2HOST buffer that must be reported to the 3559 * HOST. The Host clears this bit by writing a 1 to it. This bit 3560 * may generate an intrpt to Host depending on the sp2hostIntEn 3561 * bit. Writing 0 has no effect 3562 * The SP writes 1 to this bit after it has finished writing a 3563 * message into the SP2HOST buffer. The Host clears this bit by 3564 * writing 1 to it after it has set the hostBusy bit This bit may 3565 * generate an intrpt to Host depending on the sp2hostIntEn bit. 3566 * Writing 0 has no effect 3567 * The Host writes 1 to this bit to generate an interrupt to SP 3568 * after it has finished writing a message into the HOST2SP 3569 * buffer. The SP clears this bit by writing 1 to it after it has 3570 * set the spBusy bit. Writing 0 has no effect 3571 * The host writes 1 to clear the read pointer to the BT SP2HOST 3572 * buffer; the SP writes 1 to clear the read pointer to the BT 3573 * HOST2SP buffer. This bit is always read back as 0; writing 0 3574 * has no effect. 3575 * The host writes 1 to clear the write pointer to the BT HOST2SP 3576 * buffer; the SP writes 1 to clear the write pointer to the BT 3577 * SP2HOST buffer. This bit is always read back as 0; writing 0 3578 * has no effect. 3579 */ 3580 typedef union { 3581 uint32_t value; 3582 struct { 3583 #if defined(_BIG_ENDIAN) 3584 uint32_t rsrvd:24; 3585 uint32_t sp_busy:1; 3586 uint32_t host_busy:1; 3587 uint32_t oem0:1; 3588 uint32_t sms_atn:1; 3589 uint32_t sp2host_atn:1; 3590 uint32_t host2sp_atn:1; 3591 uint32_t clr_rd_ptr:1; 3592 uint32_t clr_wr_ptr:1; 3593 #else 3594 uint32_t clr_wr_ptr:1; 3595 uint32_t clr_rd_ptr:1; 3596 uint32_t host2sp_atn:1; 3597 uint32_t sp2host_atn:1; 3598 uint32_t sms_atn:1; 3599 uint32_t oem0:1; 3600 uint32_t host_busy:1; 3601 uint32_t sp_busy:1; 3602 uint32_t rsrvd:24; 3603 #endif 3604 } bits; 3605 } bt_ctrl0_t; 3606 3607 3608 /* 3609 * Register: BtData0 3610 * Mailbox Data 0 3611 * Description: Host (blade) <-> SP mailbox data register 0. 3612 * Host is allowed a 32 bits read/write access to this register ; To 3613 * do the same, it should provide the btData0 address, data on 3614 * hostDataBus[31:0], and assert hostBen[1], SPI is allowed only 8 3615 * bits read/write access to this register ; To do the same, it 3616 * should provide the btData0 address, data on spiDataBus[7:0], and 3617 * no need of spiBen 3618 * All references to the mail box control bits in this register 3619 * refer to btCtrl0. When spBusy=0 && host2spAtn=0, data is written 3620 * by the host and read by the SP. When hostBusy=0 && sp2hostAtn=0, 3621 * data is written by the SP and read by the Host. 3622 * 3623 * Fields: 3624 * Bits 7:0 of message data to send to SP/HOST 3625 */ 3626 typedef union { 3627 uint32_t value; 3628 struct { 3629 #if defined(_BIG_ENDIAN) 3630 uint32_t rsrvd:24; 3631 uint32_t data:8; 3632 #else 3633 uint32_t data:8; 3634 uint32_t rsrvd:24; 3635 #endif 3636 } bits; 3637 } bt_data0_t; 3638 3639 3640 /* 3641 * Register: BtIntmask0 3642 * Mailbox Interrupt Mask & Status 0 3643 * Description: Host (blade) <-> SP Block Transfer Interrupt Mask and 3644 * Status register 0 3645 * Host is allowed 8 bits read/write access to this register ; To do 3646 * the same, it should provide the btIntmask0 address, data on 3647 * hostDataBus[23:16], and assert hostBen[2], SPI is allowed 8 bits 3648 * read only access to this register ; To do the same, it should 3649 * provide the btIntmask0 address and no need of spiBen 3650 * All references to the mail box control bits in this register 3651 * refer to btCtrl0 3652 * Fields: 3653 * The host writes 1 to reset the entire mailbox 0 accesses for 3654 * error recovery; resets both SP and HOST write and read 3655 * pointers. Writing 0 has no effect. This is non-sticky. Always 3656 * read back as 0. 3657 * Reserved for definition by platform manufacturer for BIOS/SMI 3658 * Handler use. Generic IPMI software must write this bit as 0 3659 * and ignore the value on read 3660 * Reserved for definition by platform manufacturer for BIOS/SMI 3661 * Handler use. Generic IPMI software must write this bit as 0 3662 * and ignore the value on read 3663 * Reserved for definition by platform manufacturer for BIOS/SMI 3664 * Handler use. Generic IPMI software must write this bit as 0 3665 * and ignore the value on read 3666 * SP to HOST Interrupt status This bit reflects the state of the 3667 * intrpt line to the Host. O/S driver should write 1 to clear. 3668 * SP to HOST Interrupt Enable The interrupt is generated if 3669 * sp2hIrqEn is 1 and either sp2hostAtn or smsAtn is 1 3670 */ 3671 typedef union { 3672 uint32_t value; 3673 struct { 3674 #if defined(_BIG_ENDIAN) 3675 uint32_t rsrvd:24; 3676 uint32_t mb_master_reset:1; 3677 uint32_t rsrvd1:2; 3678 uint32_t oem3:1; 3679 uint32_t oem2:1; 3680 uint32_t oem1:1; 3681 uint32_t sp2h_irq:1; 3682 uint32_t sp2h_irq_en:1; 3683 #else 3684 uint32_t sp2h_irq_en:1; 3685 uint32_t sp2h_irq:1; 3686 uint32_t oem1:1; 3687 uint32_t oem2:1; 3688 uint32_t oem3:1; 3689 uint32_t rsrvd1:2; 3690 uint32_t mb_master_reset:1; 3691 uint32_t rsrvd:24; 3692 #endif 3693 } bits; 3694 } bt_intmask0_t; 3695 3696 3697 /* 3698 * Register: BtCtrl1 3699 * Mailbox Control & Access status 1 3700 * Description: Host (blade) <-> SP Block Transfer mailbox control 3701 * and access status register 1. 3702 * Host is allowed 8 bits read/write access to this register ; To do 3703 * the same, it should provide the btCtrl1 address, data on 3704 * hostDataBus[7:0], and assert hostBen[0], SPI is allowed 8 bits 3705 * read/write access to this register ; To do the same, it should 3706 * provide the btCtrl1 address, data on spiDataBus[7:0], and no need 3707 * of spiBen 3708 * 3709 * Fields: 3710 * The SP sets/clears this bit to indicate that it is busy and 3711 * can not accept any other request; write 1 to toggle the bit; 3712 * Read only by Host. 3713 * The Host sets/clears this bit to indicate that it is busy and 3714 * can not accept any other request; Read only by SP. 3715 * Reserved for definition by platform. Typical usage could be 3716 * "heartbeat" mechanism from/to the host. The host sets OEM0 to 3717 * interrupt the SP and then polls it to be cleared by SP 3718 * The SP sets this bit when it has detected and queued an SMS 3719 * message in the SP2HOST buffer that must be reported to the 3720 * HOST. The Host clears this bit by writing a 1 to it. This bit 3721 * may generate an intrpt to Host depending on the sp2hostIntEn 3722 * bit. Writing 0 has no effect 3723 * The SP writes 1 to this bit after it has finished writing a 3724 * message into the SP2HOST buffer. The Host clears this bit by 3725 * writing 1 to it after it has set the hostBusy bit This bit may 3726 * generate an intrpt to Host depending on the sp2hostIntEn bit. 3727 * Writing 0 has no effect 3728 * The Host writes 1 to this bit to generate an interrupt to SP 3729 * after it has finished writing a message into the HOST2SP 3730 * buffer. The SP clears this bit by writing 1 to it after it has 3731 * set the spBusy bit. Writing 0 has no effect 3732 * The host writes 1 to clear the read pointer to the BT SP2HOST 3733 * buffer; the SP writes 1 to clear the read pointer to the BT 3734 * HOST2SP buffer. This bit is always read back as 0; writing 0 3735 * has no effect. 3736 * The host writes 1 to clear the write pointer to the BT HOST2SP 3737 * buffer; the SP writes 1 to clear the write pointer to the BT 3738 * SP2HOST buffer. This bit is always read back as 0; writing 0 3739 * has no effect. 3740 */ 3741 typedef union { 3742 uint32_t value; 3743 struct { 3744 #if defined(_BIG_ENDIAN) 3745 uint32_t rsrvd:24; 3746 uint32_t sp_busy:1; 3747 uint32_t host_busy:1; 3748 uint32_t oem0:1; 3749 uint32_t sms_atn:1; 3750 uint32_t sp2host_atn:1; 3751 uint32_t host2sp_atn:1; 3752 uint32_t clr_rd_ptr:1; 3753 uint32_t clr_wr_ptr:1; 3754 #else 3755 uint32_t clr_wr_ptr:1; 3756 uint32_t clr_rd_ptr:1; 3757 uint32_t host2sp_atn:1; 3758 uint32_t sp2host_atn:1; 3759 uint32_t sms_atn:1; 3760 uint32_t oem0:1; 3761 uint32_t host_busy:1; 3762 uint32_t sp_busy:1; 3763 uint32_t rsrvd:24; 3764 #endif 3765 } bits; 3766 } bt_ctrl1_t; 3767 3768 3769 /* 3770 * Register: BtData1 3771 * Mailbox Data 1 3772 * Description: Host (blade) <-> SP mailbox data register 1. 3773 * Host is allowed a 32 bits read/write access to this register ; To 3774 * do the same, it should provide the btData1 address, data on 3775 * hostDataBus[31:0], and assert hostBen[1], SPI is allowed only 8 3776 * bits read/write access to this register ; To do the same, it 3777 * should provide the btData1 address, data on spiDataBus[7:0], and 3778 * no need of spiBen 3779 * All references to the mail box control bits in this register 3780 * refer to btCtrl1. When spBusy=0 && host2spAtn=0, data is written 3781 * by the host and read by the SP. When hostBusy=0 && sp2hostAtn=0, 3782 * data is written by the SP and read by the Host. 3783 * Fields: 3784 * Bits 31:0 of message data to send to SP/HOST 3785 */ 3786 typedef union { 3787 uint32_t value; 3788 struct { 3789 #if defined(_BIG_ENDIAN) 3790 uint32_t rsrvd:24; 3791 uint32_t data:8; 3792 #else 3793 uint32_t data:8; 3794 uint32_t rsrvd:24; 3795 #endif 3796 } bits; 3797 } bt_data1_t; 3798 3799 3800 /* 3801 * Register: BtIntmask1 3802 * Mailbox Interrupt Mask & Status 1 3803 * Description: Host (blade) <-> SP Block Transfer Interrupt Mask and 3804 * Status register 1 3805 * Host is allowed 8 bits read/write access to this register ; To do 3806 * the same, it should provide the btIntmask1 address, data on 3807 * hostDataBus[23:16], and assert hostBen[2], SPI is allowed 8 bits 3808 * read only access to this register ; To do the same, it should 3809 * provide the btIntmask1 address and no need of spiBen 3810 * All references to the mail box control bits in this register 3811 * refer to btCtrl1 3812 * Fields: 3813 * The host writes 1 to reset the entire mailbox 1 accesses for 3814 * error recovery; resets both SP and HOST write and read 3815 * pointers. Writing 0 has no effect. This is non-sticky. Always 3816 * read back as 0. 3817 * Reserved for definition by platform manufacturer for BIOS/SMI 3818 * Handler use. Generic IPMI software must write this bit as 0 3819 * and ignore the value on read 3820 * Reserved for definition by platform manufacturer for BIOS/SMI 3821 * Handler use. Generic IPMI software must write this bit as 0 3822 * and ignore the value on read 3823 * Reserved for definition by platform manufacturer for BIOS/SMI 3824 * Handler use. Generic IPMI software must write this bit as 0 3825 * and ignore the value on read 3826 * SP to HOST Interrupt status This bit reflects the state of the 3827 * intrpt line to the Host. O/S driver should write 1 to clear. 3828 * SP to HOST Interrupt Enable The interrupt is generated if 3829 * sp2hIrqEn is 1 and either sp2hostAtn or smsAtn is 1 3830 */ 3831 typedef union { 3832 uint32_t value; 3833 struct { 3834 #if defined(_BIG_ENDIAN) 3835 uint32_t rsrvd:24; 3836 uint32_t mb_master_reset:1; 3837 uint32_t rsrvd1:2; 3838 uint32_t oem3:1; 3839 uint32_t oem2:1; 3840 uint32_t oem1:1; 3841 uint32_t sp2h_irq:1; 3842 uint32_t sp2h_irq_en:1; 3843 #else 3844 uint32_t sp2h_irq_en:1; 3845 uint32_t sp2h_irq:1; 3846 uint32_t oem1:1; 3847 uint32_t oem2:1; 3848 uint32_t oem3:1; 3849 uint32_t rsrvd1:2; 3850 uint32_t mb_master_reset:1; 3851 uint32_t rsrvd:24; 3852 #endif 3853 } bits; 3854 } bt_intmask1_t; 3855 3856 3857 /* 3858 * Register: BtCtrl2 3859 * Mailbox Control & Access status 2 3860 * Description: Host (blade) <-> SP Block Transfer mailbox control 3861 * and access status register 2. 3862 * Host is allowed 8 bits read/write access to this register ; To do 3863 * the same, it should provide the btCtrl2 address, data on 3864 * hostDataBus[7:0], and assert hostBen[0], SPI is allowed 8 bits 3865 * read/write access to this register ; To do the same, it should 3866 * provide the btCtrl2 address, data on spiDataBus[7:0], and no need 3867 * of spiBen 3868 * 3869 * Fields: 3870 * The SP sets/clears this bit to indicate that it is busy and 3871 * can not accept any other request; write 1 to toggle the bit; 3872 * Read only by Host. 3873 * The Host sets/clears this bit to indicate that it is busy and 3874 * can not accept any other request; Read only by SP. 3875 * Reserved for definition by platform. Typical usage could be 3876 * "heartbeat" mechanism from/to the host. The host sets OEM0 to 3877 * interrupt the SP and then polls it to be cleared by SP 3878 * The SP sets this bit when it has detected and queued an SMS 3879 * message in the SP2HOST buffer that must be reported to the 3880 * HOST. The Host clears this bit by writing a 1 to it. This bit 3881 * may generate an intrpt to Host depending on the sp2hostIntEn 3882 * bit. Writing 0 has no effect 3883 * The SP writes 1 to this bit after it has finished writing a 3884 * message into the SP2HOST buffer. The Host clears this bit by 3885 * writing 1 to it after it has set the hostBusy bit This bit may 3886 * generate an intrpt to Host depending on the sp2hostIntEn bit. 3887 * Writing 0 has no effect 3888 * The Host writes 1 to this bit to generate an interrupt to SP 3889 * after it has finished writing a message into the HOST2SP 3890 * buffer. The SP clears this bit by writing 1 to it after it has 3891 * set the spBusy bit. Writing 0 has no effect 3892 * The host writes 1 to clear the read pointer to the BT SP2HOST 3893 * buffer; the SP writes 1 to clear the read pointer to the BT 3894 * HOST2SP buffer. This bit is always read back as 0; writing 0 3895 * has no effect. 3896 * The host writes 1 to clear the write pointer to the BT HOST2SP 3897 * buffer; the SP writes 1 to clear the write pointer to the BT 3898 * SP2HOST buffer. This bit is always read back as 0; writing 0 3899 * has no effect. 3900 */ 3901 typedef union { 3902 uint32_t value; 3903 struct { 3904 #if defined(_BIG_ENDIAN) 3905 uint32_t rsrvd:24; 3906 uint32_t sp_busy:1; 3907 uint32_t host_busy:1; 3908 uint32_t oem0:1; 3909 uint32_t sms_atn:1; 3910 uint32_t sp2host_atn:1; 3911 uint32_t host2sp_atn:1; 3912 uint32_t clr_rd_ptr:1; 3913 uint32_t clr_wr_ptr:1; 3914 #else 3915 uint32_t clr_wr_ptr:1; 3916 uint32_t clr_rd_ptr:1; 3917 uint32_t host2sp_atn:1; 3918 uint32_t sp2host_atn:1; 3919 uint32_t sms_atn:1; 3920 uint32_t oem0:1; 3921 uint32_t host_busy:1; 3922 uint32_t sp_busy:1; 3923 uint32_t rsrvd:24; 3924 #endif 3925 } bits; 3926 } bt_ctrl2_t; 3927 3928 3929 /* 3930 * Register: BtData2 3931 * Mailbox Data 2 3932 * Description: Host (blade) <-> SP mailbox data register 2. All 3933 * references to the mail box control bits in this register refer to 3934 * btCtrl2. 3935 * Host is allowed a 32 bits read/write access to this register ; To 3936 * do the same, it should provide the btData2 address, data on 3937 * hostDataBus[31:0], and assert hostBen[1], SPI is allowed only 8 3938 * bits read/write access to this register ; To do the same, it 3939 * should provide the btData2 address, data on spiDataBus[7:0], and 3940 * no need of spiBen 3941 * When spBusy=0 && host2spAtn=0, data is written by the host and 3942 * read by the SP. When hostBusy=0 && sp2hostAtn=0, data is written 3943 * by the SP and read by the Host. 3944 * Fields: 3945 * Bits 31:0 of message data to send to SP/HOST 3946 */ 3947 typedef union { 3948 uint32_t value; 3949 struct { 3950 #if defined(_BIG_ENDIAN) 3951 uint32_t rsrvd:24; 3952 uint32_t data:8; 3953 #else 3954 uint32_t data:8; 3955 uint32_t rsrvd:24; 3956 #endif 3957 } bits; 3958 } bt_data2_t; 3959 3960 3961 /* 3962 * Register: BtIntmask2 3963 * Mailbox Interrupt Mask & Status 2 3964 * Description: Host (blade) <-> SP Block Transfer Interrupt Mask and 3965 * Status register 2 3966 * Host is allowed 8 bits read/write access to this register ; To do 3967 * the same, it should provide the btIntmask2 address, data on 3968 * hostDataBus[23:16], and assert hostBen[2], SPI is allowed 8 bits 3969 * read only access to this register ; To do the same, it should 3970 * provide the btIntmask2 address and no need of spiBen 3971 * All references to the mail box control bits in this register 3972 * refer to btCtrl2 3973 * Fields: 3974 * The host writes 1 to reset the entire mailbox 2 accesses for 3975 * error recovery; resets both SP and HOST write and read 3976 * pointers. Writing 0 has no effect. This is non-sticky. Always 3977 * read back as 0. 3978 * Reserved for definition by platform manufacturer for BIOS/SMI 3979 * Handler use. Generic IPMI software must write this bit as 0 3980 * and ignore the value on read 3981 * Reserved for definition by platform manufacturer for BIOS/SMI 3982 * Handler use. Generic IPMI software must write this bit as 0 3983 * and ignore the value on read 3984 * Reserved for definition by platform manufacturer for BIOS/SMI 3985 * Handler use. Generic IPMI software must write this bit as 0 3986 * and ignore the value on read 3987 * SP to HOST Interrupt status This bit reflects the state of the 3988 * intrpt line to the Host. O/S driver should write 1 to clear. 3989 * SP to HOST Interrupt Enable The interrupt is generated if 3990 * sp2hIrqEn is 1 and either sp2hostAtn or smsAtn is 1 3991 */ 3992 typedef union { 3993 uint32_t value; 3994 struct { 3995 #if defined(_BIG_ENDIAN) 3996 uint32_t rsrvd:24; 3997 uint32_t mb_master_reset:1; 3998 uint32_t rsrvd1:2; 3999 uint32_t oem3:1; 4000 uint32_t oem2:1; 4001 uint32_t oem1:1; 4002 uint32_t sp2h_irq:1; 4003 uint32_t sp2h_irq_en:1; 4004 #else 4005 uint32_t sp2h_irq_en:1; 4006 uint32_t sp2h_irq:1; 4007 uint32_t oem1:1; 4008 uint32_t oem2:1; 4009 uint32_t oem3:1; 4010 uint32_t rsrvd1:2; 4011 uint32_t mb_master_reset:1; 4012 uint32_t rsrvd:24; 4013 #endif 4014 } bits; 4015 } bt_intmask2_t; 4016 4017 4018 /* 4019 * Register: BtCtrl3 4020 * Mailbox Control & Access status 3 4021 * Description: Host (blade) <-> SP Block Transfer mailbox control 4022 * and access status register 3. 4023 * Host is allowed 8 bits read/write access to this register ; To do 4024 * the same, it should provide the btCtrl3 address, data on 4025 * hostDataBus[7:0], and assert hostBen[0], SPI is allowed 8 bits 4026 * read/write access to this register ; To do the same, it should 4027 * provide the btCtrl3 address, data on spiDataBus[7:0], and no need 4028 * of spiBen 4029 * 4030 * Fields: 4031 * The SP sets/clears this bit to indicate that it is busy and 4032 * can not accept any other request; write 1 to toggle the bit; 4033 * Read only by Host. 4034 * The Host sets/clears this bit to indicate that it is busy and 4035 * can not accept any other request; Read only by SP. 4036 * Reserved for definition by platform. Typical usage could be 4037 * "heartbeat" mechanism from/to the host. The host sets OEM0 to 4038 * interrupt the SP and then polls it to be cleared by SP 4039 * The SP sets this bit when it has detected and queued an SMS 4040 * message in the SP2HOST buffer that must be reported to the 4041 * HOST. The Host clears this bit by writing a 1 to it. This bit 4042 * may generate an intrpt to Host depending on the sp2hostIntEn 4043 * bit. Writing 0 has no effect 4044 * The SP writes 1 to this bit after it has finished writing a 4045 * message into the SP2HOST buffer. The Host clears this bit by 4046 * writing 1 to it after it has set the hostBusy bit This bit may 4047 * generate an intrpt to Host depending on the sp2hostIntEn bit. 4048 * Writing 0 has no effect 4049 * The Host writes 1 to this bit to generate an interrupt to SP 4050 * after it has finished writing a message into the HOST2SP 4051 * buffer. The SP clears this bit by writing 1 to it after it has 4052 * set the spBusy bit. Writing 0 has no effect 4053 * The host writes 1 to clear the read pointer to the BT SP2HOST 4054 * buffer; the SP writes 1 to clear the read pointer to the BT 4055 * HOST2SP buffer. This bit is always read back as 0; writing 0 4056 * has no effect. 4057 * The host writes 1 to clear the write pointer to the BT HOST2SP 4058 * buffer; the SP writes 1 to clear the write pointer to the BT 4059 * SP2HOST buffer. This bit is always read back as 0; writing 0 4060 * has no effect. 4061 */ 4062 typedef union { 4063 uint32_t value; 4064 struct { 4065 #if defined(_BIG_ENDIAN) 4066 uint32_t rsrvd:24; 4067 uint32_t sp_busy:1; 4068 uint32_t host_busy:1; 4069 uint32_t oem0:1; 4070 uint32_t sms_atn:1; 4071 uint32_t sp2host_atn:1; 4072 uint32_t host2sp_atn:1; 4073 uint32_t clr_rd_ptr:1; 4074 uint32_t clr_wr_ptr:1; 4075 #else 4076 uint32_t clr_wr_ptr:1; 4077 uint32_t clr_rd_ptr:1; 4078 uint32_t host2sp_atn:1; 4079 uint32_t sp2host_atn:1; 4080 uint32_t sms_atn:1; 4081 uint32_t oem0:1; 4082 uint32_t host_busy:1; 4083 uint32_t sp_busy:1; 4084 uint32_t rsrvd:24; 4085 #endif 4086 } bits; 4087 } bt_ctrl3_t; 4088 4089 4090 /* 4091 * Register: BtData3 4092 * Mailbox Data 3 4093 * Description: Host (blade) <-> SP mailbox data register 3. 4094 * Host is allowed a 32 bits read/write access to this register ; To 4095 * do the same, it should provide the btData3 address, data on 4096 * hostDataBus[31:0], and assert hostBen[1], SPI is allowed only 8 4097 * bits read/write access to this register ; To do the same, it 4098 * should provide the btData3 address, data on spiDataBus[7:0], and 4099 * no need of spiBen 4100 * All references to the mail box control bits in this register 4101 * refer to btCtrl3. When spBusy=0 && host2spAtn=0, data is written 4102 * by the host and read by the SP. When hostBusy=0 && sp2hostAtn=0, 4103 * data is written by the SP and read by the Host. 4104 * Fields: 4105 * Bits 31:0 of message data to send to SP/HOST 4106 */ 4107 typedef union { 4108 uint32_t value; 4109 struct { 4110 #if defined(_BIG_ENDIAN) 4111 uint32_t rsrvd:24; 4112 uint32_t data:8; 4113 #else 4114 uint32_t data:8; 4115 uint32_t rsrvd:24; 4116 #endif 4117 } bits; 4118 } bt_data3_t; 4119 4120 4121 /* 4122 * Register: BtIntmask3 4123 * Mailbox Interrupt Mask & Status 3 4124 * Description: Host (blade) <-> SP Block Transfer Interrupt Mask and 4125 * Status register 3 4126 * Host is allowed 8 bits read/write access to this register ; To do 4127 * the same, it should provide the btIntmask3 address, data on 4128 * hostDataBus[23:16], and assert hostBen[2], SPI is allowed 8 bits 4129 * read only access to this register ; To do the same, it should 4130 * provide the btIntmask3 address and no need of spiBen 4131 * All references to the mail box control bits in this register 4132 * refer to btCtrl3 4133 * Fields: 4134 * The host writes 1 to reset the entire mailbox 3 accesses for 4135 * error recovery; resets both SP and HOST write and read 4136 * pointers. Writing 0 has no effect. This is non-sticky. Always 4137 * read back as 0. 4138 * Reserved for definition by platform manufacturer for BIOS/SMI 4139 * Handler use. Generic IPMI software must write this bit as 0 4140 * and ignore the value on read 4141 * Reserved for definition by platform manufacturer for BIOS/SMI 4142 * Handler use. Generic IPMI software must write this bit as 0 4143 * and ignore the value on read 4144 * Reserved for definition by platform manufacturer for BIOS/SMI 4145 * Handler use. Generic IPMI software must write this bit as 0 4146 * and ignore the value on read 4147 * SP to HOST Interrupt status This bit reflects the state of the 4148 * intrpt line to the Host. O/S driver should write 1 to clear. 4149 * SP to HOST Interrupt Enable The interrupt is generated if 4150 * sp2hIrqEn is 1 and either sp2hostAtn or smsAtn is 1 4151 */ 4152 typedef union { 4153 uint32_t value; 4154 struct { 4155 #if defined(_BIG_ENDIAN) 4156 uint32_t rsrvd:24; 4157 uint32_t mb_master_reset:1; 4158 uint32_t rsrvd1:2; 4159 uint32_t oem3:1; 4160 uint32_t oem2:1; 4161 uint32_t oem1:1; 4162 uint32_t sp2h_irq:1; 4163 uint32_t sp2h_irq_en:1; 4164 #else 4165 uint32_t sp2h_irq_en:1; 4166 uint32_t sp2h_irq:1; 4167 uint32_t oem1:1; 4168 uint32_t oem2:1; 4169 uint32_t oem3:1; 4170 uint32_t rsrvd1:2; 4171 uint32_t mb_master_reset:1; 4172 uint32_t rsrvd:24; 4173 #endif 4174 } bits; 4175 } bt_intmask3_t; 4176 4177 4178 /* 4179 * Register: DebugSel 4180 * CIP Debug Data Select 4181 * Description: Selects the debug data signals from the CIP blocks 4182 * Fields: 4183 * Selects up to 16 groups of gbtDebug/pipeDebug on 4184 * peuPhyVdbgDebugPort[31:0] 4185 * Selects the high DW of the debug data - default is PCIe link 4186 * status 4187 * Selects the low DW of the debug data 4188 */ 4189 typedef union { 4190 uint32_t value; 4191 struct { 4192 #if defined(_BIG_ENDIAN) 4193 uint32_t rsrvd:12; 4194 uint32_t phy_dbug_sel:4; 4195 uint32_t rsrvd1:3; 4196 uint32_t cip_hdbug_sel:5; 4197 uint32_t rsrvd2:3; 4198 uint32_t cip_ldbug_sel:5; 4199 #else 4200 uint32_t cip_ldbug_sel:5; 4201 uint32_t rsrvd2:3; 4202 uint32_t cip_hdbug_sel:5; 4203 uint32_t rsrvd1:3; 4204 uint32_t phy_dbug_sel:4; 4205 uint32_t rsrvd:12; 4206 #endif 4207 } bits; 4208 } debug_sel_t; 4209 4210 4211 /* 4212 * Register: IndaccMem0Ctrl 4213 * CIP Mem0 Debug ctrl 4214 * Description: Debug data signals from the CIP blocks 4215 * Fields: 4216 * 1: rd/wr access is done 0: rd/wr access is in progress 4217 * 1: pkt injection is done 0: pkt injection is in progress 4218 * Ingress pkt injection enable: write to 1 for single pkt 4219 * injection. Must be 0 when enabling diagnostic rd/wr access to 4220 * memories. 4221 * 1: Diagnostic rd/wr access to memories enabled 0: Diagnostic 4222 * rd/wr access to memories disabled Must be 0 when enabling pkt 4223 * injection. 4224 * 1: read, 0: write 4225 * This bit is read/writable only if mem0Diagen=1 or if 4226 * mem0Diagen bit is also written with '1' along with enabling 4227 * this bit. Else, the write will not have any effect. 1: Apply 4228 * the parity mask provided in the Prty register 0: Do not apply 4229 * the parity mask provided in the Prty register 4230 * 0 : select npdataq memory 1 : select nphdrq memory 2 : select 4231 * pdataq memory 3 : select phdrq memory 4 : select cpldataq 4232 * memory 5 : select cplhdrq memory 4233 */ 4234 typedef union { 4235 uint32_t value; 4236 struct { 4237 #if defined(_BIG_ENDIAN) 4238 uint32_t mem0_access_status:1; 4239 uint32_t rsrvd:5; 4240 uint32_t mem0_pktinj_stat:1; 4241 uint32_t mem0_pktinj_en:1; 4242 uint32_t rsrvd1:1; 4243 uint32_t mem0_diagen:1; 4244 uint32_t mem0_command:1; 4245 uint32_t mem0_prty_wen:1; 4246 uint32_t rsrvd2:1; 4247 uint32_t mem0_sel:3; 4248 uint32_t mem0_addr:16; 4249 #else 4250 uint32_t mem0_addr:16; 4251 uint32_t mem0_sel:3; 4252 uint32_t rsrvd2:1; 4253 uint32_t mem0_prty_wen:1; 4254 uint32_t mem0_command:1; 4255 uint32_t mem0_diagen:1; 4256 uint32_t rsrvd1:1; 4257 uint32_t mem0_pktinj_en:1; 4258 uint32_t mem0_pktinj_stat:1; 4259 uint32_t rsrvd:5; 4260 uint32_t mem0_access_status:1; 4261 #endif 4262 } bits; 4263 } indacc_mem0_ctrl_t; 4264 4265 4266 /* 4267 * Register: IndaccMem0Data0 4268 * CIP Mem0 Debug Data0 4269 * Description: Debug data signals from the CIP blocks 4270 * Fields: 4271 * When pktInjectionEnable is 0: Data[31:0] from/for the memory 4272 * selected by mem0Sel bits from mem0Ctrl This data is written to 4273 * the memory when indaccMem0Ctrl register is written with the 4274 * write command When indaccMem0Ctrl register is written with the 4275 * read command, this register will hold the Data[31:0] returned 4276 * from the memory When pktInjectionEnable is 1: 4277 * debugData0Reg[31:0] is used in the following ways: [17:16] = 4278 * radmTrgt1Fmt[1:0]: 2'b00 3DW MRd 2'b01 4DW MRd 2'b10 3DW MWr 4279 * 2'b11 4DW MWr [13:12] = radmTrgt1DwLen[1:0]: 2'b01 1DW 2'b10 4280 * 2DW [11:8] = radmTrgt1LastBe[3:0]: 4'b0000 1DW 4'b1111 2DW [7] 4281 * = radmTrgt1RomInRange 1'b0 PIO Access 1'b1 EEPROM Access [6:4] 4282 * = radmTrgt1InMembarRange[2:0] 3'b000 PIO Access 3'b010 MSIX 4283 * Ram/PBA Table Access [1:0] = radmTrgt1Dwen[1:0] 2'b01 4284 * 1DW->last DW is at radmTrgt1Data[31:0] 2'b11 2DW->last DW is 4285 * at radmTrgt1Data[63:32] 4286 */ 4287 typedef union { 4288 uint32_t value; 4289 struct { 4290 #if defined(_BIG_ENDIAN) 4291 uint32_t mem0_data0:32; 4292 #else 4293 uint32_t mem0_data0:32; 4294 #endif 4295 } bits; 4296 } indacc_mem0_data0_t; 4297 4298 4299 /* 4300 * Register: IndaccMem0Data1 4301 * CIP Mem0 Debug Data1 4302 * Description: Debug data signals from the CIP blocks 4303 * Fields: 4304 * When pktInjectionEnable is 0: Data[63:32] from/for the memory 4305 * selected by mem0Sel bits from mem0Ctrl This data is written to 4306 * the memory when indaccMem0Ctrl register is written with the 4307 * write command When indaccMem0Ctrl register is written with the 4308 * read command, this register will hold the Data[63:32] returned 4309 * from the memory When pktInjectionEnable is 1: 4310 * debugData1Reg[31:0] is used as radmTrgt1Addr[31:0]. 4311 */ 4312 typedef union { 4313 uint32_t value; 4314 struct { 4315 #if defined(_BIG_ENDIAN) 4316 uint32_t mem0_data1:32; 4317 #else 4318 uint32_t mem0_data1:32; 4319 #endif 4320 } bits; 4321 } indacc_mem0_data1_t; 4322 4323 4324 /* 4325 * Register: IndaccMem0Data2 4326 * CIP Mem0 Debug Data2 4327 * Description: Debug data signals from the CIP blocks 4328 * Fields: 4329 * When pktInjectionEnable is 0: Data[95:64] from/for the memory 4330 * selected by mem0Sel bits from mem0Ctrl This data is written to 4331 * the memory when indaccMem0Ctrl register is written with the 4332 * write command When indaccMem0Ctrl register is written with the 4333 * read command, this register will hold the Data[95:64] returned 4334 * from the memory When pktInjectionEnable is 1: 4335 * debugData2Reg[31:0] is used as radmTrgt1Data[63:32]. Allows up 4336 * to QW=2DW access. 4337 */ 4338 typedef union { 4339 uint32_t value; 4340 struct { 4341 #if defined(_BIG_ENDIAN) 4342 uint32_t mem0_data2:32; 4343 #else 4344 uint32_t mem0_data2:32; 4345 #endif 4346 } bits; 4347 } indacc_mem0_data2_t; 4348 4349 4350 /* 4351 * Register: IndaccMem0Data3 4352 * CIP Mem0 Debug Data3 4353 * Description: Debug data signals from the CIP blocks 4354 * Fields: 4355 * When pktInjectionEnable is 0: Data[127:96] from/for the memory 4356 * selected by mem0Sel bits from mem0Ctrl This data is written to 4357 * the memory when indaccMem0Ctrl register is written with the 4358 * write command When indaccMem0Ctrl register is written with the 4359 * read command, this register will hold the Data[127:96] 4360 * returned from the memory When pktInjectionEnable is 1: 4361 * debugData3Reg[31:0] is used as radmTrgt1Data[31:0]. 4362 */ 4363 typedef union { 4364 uint32_t value; 4365 struct { 4366 #if defined(_BIG_ENDIAN) 4367 uint32_t mem0_data3:32; 4368 #else 4369 uint32_t mem0_data3:32; 4370 #endif 4371 } bits; 4372 } indacc_mem0_data3_t; 4373 4374 4375 /* 4376 * Register: IndaccMem0Prty 4377 * CIP Mem0 Debug Parity 4378 * Description: Debug data signals from the CIP blocks 4379 * Fields: 4380 * parity mask bits for the memory selected by mem0Sel bits from 4381 * mem0Ctrl to inject parity error These bits serve two purposes 4382 * regarding memory parity : - During indirect write access to 4383 * the memories, the value in this register is applied as mask to 4384 * the actual parity if prtyWen bit of the indaccCtrl register 4385 * has been enabled. The masked parity and data are written into 4386 * the specified memory location. - During indirect read access 4387 * to the memories, the value in this register is overwritten 4388 * with the parity value read from the memory location. If the 4389 * parity mask had been set and enabled to be written into this 4390 * location it will generate parity error for that memory 4391 * location 4392 */ 4393 typedef union { 4394 uint32_t value; 4395 struct { 4396 #if defined(_BIG_ENDIAN) 4397 uint32_t rsrvd:18; 4398 uint32_t mem0_parity:14; 4399 #else 4400 uint32_t mem0_parity:14; 4401 uint32_t rsrvd:18; 4402 #endif 4403 } bits; 4404 } indacc_mem0_prty_t; 4405 4406 4407 /* 4408 * Register: IndaccMem1Ctrl 4409 * CIP Mem1 Debug ctrl 4410 * Description: Debug data signals from the CIP blocks 4411 * Fields: 4412 * 1: rd/wr access is done 0: rd/wr access is in progress 4413 * 1: client pkt injection is done 0: client pkt injection is in 4414 * progress 4415 * 1: client1 pkt injection 0: client0 pkt injection 4416 * Mutually exclusive: Either client0 or client1 egress pkt 4417 * injection enable: write to 1 for single pkt injection. Must be 4418 * 0 when enabling diagnostic rd/wr access to memories. 4419 * 1: Diagnostic rd/wr access enabled 0: Diagnostic rd/wr access 4420 * disabled Must be 0 when enabling pkt injection. 4421 * 1: read, 0: write 4422 * This bit is read/writable only if mem1Diagen=1 or if 4423 * mem1Diagen bit is also written with '1' along with enabling 4424 * this bit. Else, the write will not have any effect. 1: Apply 4425 * the parity mask provided in the Prty register 0: Do not apply 4426 * the parity mask provided in the Prty register 4427 * 0 : select retry sot memory 1 : select retry buffer memory 2 : 4428 * select msix memory 3 : select hcr cfg memory 4429 */ 4430 typedef union { 4431 uint32_t value; 4432 struct { 4433 #if defined(_BIG_ENDIAN) 4434 uint32_t mem1_access_status:1; 4435 uint32_t rsrvd:4; 4436 uint32_t mem1_pktinj_stat:1; 4437 uint32_t mem1_pktinj_client:1; 4438 uint32_t mem1_pktinj_en:1; 4439 uint32_t rsrvd1:1; 4440 uint32_t mem1_diagen:1; 4441 uint32_t mem1_command:1; 4442 uint32_t mem1_prty_wen:1; 4443 uint32_t rsrvd2:2; 4444 uint32_t mem1_sel:2; 4445 uint32_t mem1_addr:16; 4446 #else 4447 uint32_t mem1_addr:16; 4448 uint32_t mem1_sel:2; 4449 uint32_t rsrvd2:2; 4450 uint32_t mem1_prty_wen:1; 4451 uint32_t mem1_command:1; 4452 uint32_t mem1_diagen:1; 4453 uint32_t rsrvd1:1; 4454 uint32_t mem1_pktinj_en:1; 4455 uint32_t mem1_pktinj_client:1; 4456 uint32_t mem1_pktinj_stat:1; 4457 uint32_t rsrvd:4; 4458 uint32_t mem1_access_status:1; 4459 #endif 4460 } bits; 4461 } indacc_mem1_ctrl_t; 4462 4463 4464 /* 4465 * Register: IndaccMem1Data0 4466 * CIP Mem1 Debug Data0 4467 * Description: Debug data signals from the CIP blocks 4468 * Fields: 4469 * When pktInjectionEnable is 0: Data[31:0] from/for the memory 4470 * selected by mem1Sel bits from mem1Ctrl This data is written to 4471 * the memory when indaccMem1Ctrl register is written with the 4472 * write command When indaccMem1Ctrl register is written with the 4473 * read command, this register will hold the Data[31:0] returned 4474 * from the memory 4475 * When pktInjectionEnable is 1: debugData0Reg[31:0] is used in 4476 * the following ways: [27:26] = tdcPeuTlp0[or 4477 * rdcPeuTlp1]_fmt[1:0]: 2'b00 3DW MRd 2'b01 4DW MRd 2'b10 3DW 4478 * MWr 2'b11 4DW MWr [25:13] = tdcPeuTlp0[or 4479 * rdcPeuTlp1]_byteLen[12:0]: Note MWr must be limited to 4B = 4480 * 13'b0000000000001. [12:8] = tdcPeuTlp0[or 4481 * rdcPeuTlp1]_tid[4:0]: 5 lsb of tid (TAG ID) [7:0] = 4482 * tdcPeuTlp0[or rdcPeuTlp1]_byteEn[7:0]: [7:4] = last DW byte 4483 * enables [3:0] = first DW byte enables 4484 */ 4485 typedef union { 4486 uint32_t value; 4487 struct { 4488 #if defined(_BIG_ENDIAN) 4489 uint32_t mem1_data0:32; 4490 #else 4491 uint32_t mem1_data0:32; 4492 #endif 4493 } bits; 4494 } indacc_mem1_data0_t; 4495 4496 4497 /* 4498 * Register: IndaccMem1Data1 4499 * CIP Mem1 Debug Data1 4500 * Description: Debug data signals from the CIP blocks 4501 * Fields: 4502 * When pktInjectionEnable is 0: Data[63:32] from/for the memory 4503 * selected by mem1Sel bits from mem1Ctrl This data is written to 4504 * the memory when indaccMem1Ctrl register is written with the 4505 * write command When indaccMem1Ctrl register is written with the 4506 * read command, this register will hold the Data[63:32] returned 4507 * from the memory 4508 * When pktInjectionEnable is 1: debugData1Reg[31:0] is used as 4509 * tdcPeuTlp0[or rdcPeuTlp1]_addr[63:32] high address bits. 4510 */ 4511 typedef union { 4512 uint32_t value; 4513 struct { 4514 #if defined(_BIG_ENDIAN) 4515 uint32_t mem1_data1:32; 4516 #else 4517 uint32_t mem1_data1:32; 4518 #endif 4519 } bits; 4520 } indacc_mem1_data1_t; 4521 4522 4523 /* 4524 * Register: IndaccMem1Data2 4525 * CIP Mem1 Debug Data2 4526 * Description: Debug data signals from the CIP blocks 4527 * Fields: 4528 * When pktInjectionEnable is 0: Data[95:64] from/for the memory 4529 * selected by mem1Sel bits from mem1Ctrl This data is written to 4530 * the memory when indaccMem1Ctrl register is written with the 4531 * write command When indaccMem1Ctrl register is written with the 4532 * read command, this register will hold the Data[95:64] returned 4533 * from the memory 4534 * When pktInjectionEnable is 1: debugData2Reg[31:0] is used as 4535 * tdcPeuTlp0[or rdcPeuTlp1]_addr[31:0] low address bits. 4536 */ 4537 typedef union { 4538 uint32_t value; 4539 struct { 4540 #if defined(_BIG_ENDIAN) 4541 uint32_t mem1_data2:32; 4542 #else 4543 uint32_t mem1_data2:32; 4544 #endif 4545 } bits; 4546 } indacc_mem1_data2_t; 4547 4548 4549 /* 4550 * Register: IndaccMem1Data3 4551 * CIP Mem1 Debug Data3 4552 * Description: Debug data signals from the CIP blocks 4553 * Fields: 4554 * When pktInjectionEnable is 0: Data[127:96] from/for the memory 4555 * selected by mem1Sel bits from mem1Ctrl This data is written to 4556 * the memory when indaccMem1Ctrl register is written with the 4557 * write command When indaccMem1Ctrl register is written with the 4558 * read command, this register will hold the Data[127:96] 4559 * returned from the memory 4560 * When pktInjectionEnable is 1: debugData3Reg[31:0] is used as 4561 * tdcPeuTlp0[or rdcPeuTlp1]_data[31:0] Limited for MWr to 1 DW. 4562 */ 4563 typedef union { 4564 uint32_t value; 4565 struct { 4566 #if defined(_BIG_ENDIAN) 4567 uint32_t mem1_data3:32; 4568 #else 4569 uint32_t mem1_data3:32; 4570 #endif 4571 } bits; 4572 } indacc_mem1_data3_t; 4573 4574 4575 /* 4576 * Register: IndaccMem1Prty 4577 * CIP Mem1 Debug Parity 4578 * Description: Debug data signals from the CIP blocks 4579 * Fields: 4580 * parity mask bits for the memory selected by mem1Sel bits from 4581 * mem1Ctrl to inject parity error These bits serve two purposes 4582 * regarding memory parity : - During indirect write access to 4583 * the memories, the value in this register is applied as mask to 4584 * the actual parity if prtyWen bit of the indaccCtrl register 4585 * has been enabled. The masked parity and data are written into 4586 * the specified memory location. - During indirect read access 4587 * to the memories, the value in this register is overwritten 4588 * with the parity value read from the memory location. If the 4589 * parity mask had been set and enabled to be written into this 4590 * location it will generate parity error for that memory 4591 * location 4592 */ 4593 typedef union { 4594 uint32_t value; 4595 struct { 4596 #if defined(_BIG_ENDIAN) 4597 uint32_t rsrvd:20; 4598 uint32_t mem1_parity:12; 4599 #else 4600 uint32_t mem1_parity:12; 4601 uint32_t rsrvd:20; 4602 #endif 4603 } bits; 4604 } indacc_mem1_prty_t; 4605 4606 4607 /* 4608 * Register: PhyDebugTrainingVec 4609 * peuPhy Debug Training Vector 4610 * Description: peuPhy Debug Training Vector register. 4611 * Fields: 4612 * Hard-coded value for peuPhy wrt global debug training block 4613 * signatures. 4614 * Blade Number, the value read depends on the blade this block 4615 * resides 4616 * debug training vector the sub-group select value of 0 selects 4617 * this vector 4618 */ 4619 typedef union { 4620 uint32_t value; 4621 struct { 4622 #if defined(_BIG_ENDIAN) 4623 uint32_t dbg_msb:1; 4624 uint32_t bld_num:3; 4625 uint32_t phydbg_training_vec:28; 4626 #else 4627 uint32_t phydbg_training_vec:28; 4628 uint32_t bld_num:3; 4629 uint32_t dbg_msb:1; 4630 #endif 4631 } bits; 4632 } phy_debug_training_vec_t; 4633 4634 4635 /* 4636 * Register: PeuDebugTrainingVec 4637 * PEU Debug Training Vector 4638 * Description: PEU Debug Training Vector register. 4639 * Fields: 4640 * Hard-coded value for PEU (VNMy - core clk domain) wrt global 4641 * debug training block signatures. 4642 * Blade Number, the value read depends on the blade this block 4643 * resides 4644 * debug training vector the sub-group select value of 0 selects 4645 * this vector 4646 * Hard-coded value for PEU (VNMy - core clk domain) wrt global 4647 * debug training block signatures. 4648 * Blade Number, the value read depends on the blade this block 4649 * resides 4650 * debug training vector the sub-group select value of 0 selects 4651 * this vector 4652 */ 4653 typedef union { 4654 uint32_t value; 4655 struct { 4656 #if defined(_BIG_ENDIAN) 4657 uint32_t dbgmsb_upper:1; 4658 uint32_t bld_num_upper:3; 4659 uint32_t peudbg_upper_training_vec:12; 4660 uint32_t dbgmsb_lower:1; 4661 uint32_t bld_num_lower:3; 4662 uint32_t peudbg_lower_training_vec:12; 4663 #else 4664 uint32_t peudbg_lower_training_vec:12; 4665 uint32_t bld_num_lower:3; 4666 uint32_t dbgmsb_lower:1; 4667 uint32_t peudbg_upper_training_vec:12; 4668 uint32_t bld_num_upper:3; 4669 uint32_t dbgmsb_upper:1; 4670 #endif 4671 } bits; 4672 } peu_debug_training_vec_t; 4673 4674 4675 /* 4676 * Register: PipeCfg0 4677 * PIPE Configuration 4678 * Description: These are controls signals for the pipe core and are 4679 * used to define the PIPE core configuration with PipeCfg1 reg value 4680 * (0x08124) 4681 * Fields: 4682 * If this bit is 1 when pipe reset is released, then the value 4683 * on the pipe core's input port 'pipeParameter' is loaded into 4684 * the Pipe Core's internal Rx/Tx Parameter register which is 4685 * pipeRxTxParam at addr 0x01010. Note that it is software's 4686 * responsibility to program the pipeParameter (Pipe Cfg1) 4687 * register correctly: e.g. LOSADJ must be 0x1. 4688 */ 4689 typedef union { 4690 uint32_t value; 4691 struct { 4692 #if defined(_BIG_ENDIAN) 4693 uint32_t rsrvd:21; 4694 uint32_t pipe_serdes_x1:1; 4695 uint32_t pipe_force_ewrap:1; 4696 uint32_t pipe_force_loopback:1; 4697 uint32_t pipe_force_parm:1; 4698 uint32_t pipe_freq_sel:1; 4699 uint32_t pipe_p1_pdown:1; 4700 uint32_t pipe_p1_pdtx:1; 4701 uint32_t pipe_same_sel:1; 4702 uint32_t pipe_system_clk:1; 4703 uint32_t gbt_term_i:2; 4704 #else 4705 uint32_t gbt_term_i:2; 4706 uint32_t pipe_system_clk:1; 4707 uint32_t pipe_same_sel:1; 4708 uint32_t pipe_p1_pdtx:1; 4709 uint32_t pipe_p1_pdown:1; 4710 uint32_t pipe_freq_sel:1; 4711 uint32_t pipe_force_parm:1; 4712 uint32_t pipe_force_loopback:1; 4713 uint32_t pipe_force_ewrap:1; 4714 uint32_t pipe_serdes_x1:1; 4715 uint32_t rsrvd:21; 4716 #endif 4717 } bits; 4718 } pipe_cfg0_t; 4719 4720 4721 /* 4722 * Register: PipeCfg1 4723 * PIPE Configuration 4724 * Description: These values define the PIPE core configuration and 4725 * is presented on the Pipe core's input port 'pipeParameter'. 4726 * The value on the pipe core's input 'pipeParameter' is loaded into 4727 * the pipe core's internal Rx/Tx Parameter register, which is 4728 * pipeRxTxParam at addr 0x01010, by forcing the pipeForceParm bit of 4729 * the Pipe Cfg0 Register at address 0x08120. 4730 * 4731 * Fields: 4732 * Tx Driver Emphasis 4733 * Serial output Slew Rate Control 4734 * Tx Voltage Mux control 4735 * Tx Voltage Pulse control 4736 * Output Swing setting 4737 * Transmitter Clock generator pole adjust 4738 * Transmitter Clock generator zero adjust 4739 * Receiver Clock generator pole adjust 4740 * Receiver Clock generator zero adjust 4741 * Bias Control for factory testing and debugging 4742 * Receiver LOS Threshold adjustment. LSI suggests this POR 4743 * default value must be 0x1 (which is the POR default value of 4744 * the Pipe Rx/Tx Parameter Register). 4745 * Receiver Input Equalizer control 4746 */ 4747 typedef union { 4748 uint32_t value; 4749 struct { 4750 #if defined(_BIG_ENDIAN) 4751 uint32_t rsrvd:1; 4752 uint32_t emph:3; 4753 uint32_t rsrvd1:1; 4754 uint32_t risefall:3; 4755 uint32_t vmuxlo:2; 4756 uint32_t vpulselo:2; 4757 uint32_t vtxlo:4; 4758 uint32_t tp:2; 4759 uint32_t tz:2; 4760 uint32_t rp:2; 4761 uint32_t rz:2; 4762 uint32_t biascntl:1; 4763 uint32_t losadj:3; 4764 uint32_t rxeq:4; 4765 #else 4766 uint32_t rxeq:4; 4767 uint32_t losadj:3; 4768 uint32_t biascntl:1; 4769 uint32_t rz:2; 4770 uint32_t rp:2; 4771 uint32_t tz:2; 4772 uint32_t tp:2; 4773 uint32_t vtxlo:4; 4774 uint32_t vpulselo:2; 4775 uint32_t vmuxlo:2; 4776 uint32_t risefall:3; 4777 uint32_t rsrvd1:1; 4778 uint32_t emph:3; 4779 uint32_t rsrvd:1; 4780 #endif 4781 } bits; 4782 } pipe_cfg1_t; 4783 4784 4785 /* 4786 * Register: CipBarMaskCfg 4787 * BAR Mask Config 4788 * Description: To write to the BAR MASK registers in the EP Core PCI 4789 * Config registers This register should be initialised before 4790 * writing the value to into the cipBarMask register. The lower 3 4791 * bits define the BAR register number whose mask value has to be 4792 * over written with the values that will be written into the 4793 * cipBarMask register. [2:0] = 0 thru 5 selects bar0Mask thru 4794 * bar5Mask registers = 6,7 selects Expansion romBarMask register 4795 * Hydra's configuration for the BARs is as below : BAR1, BAR0 : 4796 * Forms 64 bit PIO BAR. BAR1 handles the upper address bits BAR0 4797 * handles the lower address bits BAR3, BAR2 : Forms 64 bit MSIX BAR 4798 * BAR3 handles the upper address bits BAR2 handles the lower address 4799 * bits BAR5, BAR4 : Not used and so disabled. Hence, user writes 4800 * will not have any effect. romBar : Expansion romBar 4801 * 4802 * Fields: 4803 * 0 : bar0Mask 1 : bar1Mask 2 : bar2Mask 3 : bar3Mask 4 : 4804 * bar4Mask 5 : bar5Mask 6, 7 ; romBarMask 4805 */ 4806 typedef union { 4807 uint32_t value; 4808 struct { 4809 #if defined(_BIG_ENDIAN) 4810 uint32_t rsrvd:29; 4811 uint32_t data:3; 4812 #else 4813 uint32_t data:3; 4814 uint32_t rsrvd:29; 4815 #endif 4816 } bits; 4817 } cip_bar_mask_cfg_t; 4818 4819 4820 /* 4821 * Register: CipBarMask 4822 * BAR Mask 4823 * Description: Value to write to the BAR MASK registers in the EP 4824 * Core PCI Config registers The lower 3 bits of cipMaskCfg register 4825 * define the BAR register number Write to this register will 4826 * initiate the DBI access to the EP Core. The cipBarMaskCfg register 4827 * should be setup before writing to this register. [31:1] = Mask 4828 * value [0] = 1: BAR is enabled; 0: BAR is disabled. Note that the 4829 * BAR must be enabled ([0] == 1) before the Mask value will be 4830 * written into the actual bar mask register. If the BAR is disabled 4831 * ([0]==0), two writes to this register are required before the Mask 4832 * value is written into the actual bar mask register. Refer to EP 4833 * core data book for more details. 4834 * 4835 * Fields: 4836 */ 4837 typedef union { 4838 uint32_t value; 4839 struct { 4840 #if defined(_BIG_ENDIAN) 4841 uint32_t data:32; 4842 #else 4843 uint32_t data:32; 4844 #endif 4845 } bits; 4846 } cip_bar_mask_t; 4847 4848 4849 /* 4850 * Register: CipLdsv0Stat 4851 * LDSV0 Status (for debug purpose) 4852 * Description: Returns the status of LDSV0 Flags regardless of their 4853 * group 4854 * 4855 * Fields: 4856 */ 4857 typedef union { 4858 uint32_t value; 4859 struct { 4860 #if defined(_BIG_ENDIAN) 4861 uint32_t data:32; 4862 #else 4863 uint32_t data:32; 4864 #endif 4865 } bits; 4866 } cip_ldsv0_stat_t; 4867 4868 4869 /* 4870 * Register: CipLdsv1Stat 4871 * LDSV1 Status (for debug purpose) 4872 * Description: Returns the status of LDSV1 Flags regardless of their 4873 * group 4874 * 4875 * Fields: 4876 */ 4877 typedef union { 4878 uint32_t value; 4879 struct { 4880 #if defined(_BIG_ENDIAN) 4881 uint32_t data:32; 4882 #else 4883 uint32_t data:32; 4884 #endif 4885 } bits; 4886 } cip_ldsv1_stat_t; 4887 4888 4889 /* 4890 * Register: PeuIntrStat 4891 * PEU Interrupt Status 4892 * Description: Returns the parity error status of all of the PEU 4893 * RAMs, and external (to peu) block pio access errors. External 4894 * block pio access errors could be due to either host or SPI 4895 * initiated accesses. These fields are RO and can be cleared only 4896 * through a cip reset All these errors feed to devErrStat.peuErr1 4897 * which in turn feed to LDSV1.devErr1 4898 * Partity Error bits: These bits log the very first parity error 4899 * detected in a particular memory. The corresponding memory location 4900 * is logged in respective perrLoc registers. External Block PIO 4901 * Access Error bits: These bits log the very first error that 4902 * resulted in access error. The corresponding address is logged in 4903 * respective accErrLog registers. 4904 * These bits can be set by writing a '1' to the corresponding 4905 * mirror bit in the peuIntrStatMirror register. 4906 * Note: PEU RAM Parity Errors and their corresponding interrupt: 4907 * When these bits are set and the device error status interrupt is 4908 * not masked, the PEU attempts to send the corresponding interrupt 4909 * back to the RC. Depending on which ram is impacted and the 4910 * corresponding logic impacted in the EP core, a coherent interrupt 4911 * message may not be sent in all cases. For the times when the EP 4912 * core is unable to send an interrupt, the SPI interface is to be 4913 * used for error diagnosis as the PEU interrupt status is logged 4914 * regardless of whether the interrupt is sent to the RC. The 4915 * following data was collected via simulation: -Parity error 4916 * impacted rams that likely will be able to send an interrupt: 4917 * npDataq, pDataq, cplDataq, hcr. -Parity error impacted rams that 4918 * may not be able to send an interrupt: npHdrq, pHdrq, cplHdrq, MSIx 4919 * table, retryram, retrysot. 4920 * 4921 * Fields: 4922 * Error indication from SPROM Controller for Sprom Download 4923 * access This error indicates that a parity error was detected 4924 * from SRAM. For more details, please refer to SPROM Controller 4925 * PRM. 4926 * Error indication from TDC for PIO access The error location 4927 * and type are logged in tdcPioaccErrLog 4928 * Error indication from RDC for PIO access The error location 4929 * and type are logged in rdcPioaccErrLog 4930 * Error indication from PFC for PIO access The error location 4931 * and type are logged in pfcPioaccErrLog 4932 * Error indication from VMAC for PIO access The error location 4933 * and type are logged in vmacPioaccErrLog 4934 * memory in PCIe data path and value unknown until packet flow 4935 * starts. 4936 * memory in PCIe data path and value unknown until packet flow 4937 * starts. 4938 * memory in PCIe data path and value unknown until packet flow 4939 * starts. 4940 * memory in PCIe data path and value unknown until packet flow 4941 * starts. 4942 * memory in PCIe data path and value unknown until packet flow 4943 * starts. 4944 * memory in PCIe data path and value unknown until packet flow 4945 * starts. 4946 * memory in PCIe data path and value unknown until packet flow 4947 * starts. 4948 * memory in PCIe data path and value unknown until packet flow 4949 * starts. 4950 */ 4951 typedef union { 4952 uint32_t value; 4953 struct { 4954 #if defined(_BIG_ENDIAN) 4955 uint32_t rsrvd:11; 4956 uint32_t spc_acc_err:1; 4957 uint32_t tdc_pioacc_err:1; 4958 uint32_t rdc_pioacc_err:1; 4959 uint32_t pfc_pioacc_err:1; 4960 uint32_t vmac_pioacc_err:1; 4961 uint32_t rsrvd1:6; 4962 uint32_t cpl_hdrq_parerr:1; 4963 uint32_t cpl_dataq_parerr:1; 4964 uint32_t retryram_xdlh_parerr:1; 4965 uint32_t retrysotram_xdlh_parerr:1; 4966 uint32_t p_hdrq_parerr:1; 4967 uint32_t p_dataq_parerr:1; 4968 uint32_t np_hdrq_parerr:1; 4969 uint32_t np_dataq_parerr:1; 4970 uint32_t eic_msix_parerr:1; 4971 uint32_t hcr_parerr:1; 4972 #else 4973 uint32_t hcr_parerr:1; 4974 uint32_t eic_msix_parerr:1; 4975 uint32_t np_dataq_parerr:1; 4976 uint32_t np_hdrq_parerr:1; 4977 uint32_t p_dataq_parerr:1; 4978 uint32_t p_hdrq_parerr:1; 4979 uint32_t retrysotram_xdlh_parerr:1; 4980 uint32_t retryram_xdlh_parerr:1; 4981 uint32_t cpl_dataq_parerr:1; 4982 uint32_t cpl_hdrq_parerr:1; 4983 uint32_t rsrvd1:6; 4984 uint32_t vmac_pioacc_err:1; 4985 uint32_t pfc_pioacc_err:1; 4986 uint32_t rdc_pioacc_err:1; 4987 uint32_t tdc_pioacc_err:1; 4988 uint32_t spc_acc_err:1; 4989 uint32_t rsrvd:11; 4990 #endif 4991 } bits; 4992 } peu_intr_stat_t; 4993 4994 4995 /* 4996 * Register: PeuIntrMask 4997 * Parity Error Status Mask 4998 * Description: Masks for interrupt generation for block and parity 4999 * error in the PEU RAMs For the VNM errors (spc, tdc, rdc, pfc, & 5000 * vmac), note that the interrupt message to the host will be delayed 5001 * from the actual moment that the error is detected until the host 5002 * does a PIO access and this mask is cleared. 5003 * 5004 * Fields: 5005 * 1: Mask interrupt generation for access error from SPROM 5006 * Controller 5007 * 1: Mask interrupt generation for PIO access error from TDC 5008 * 1: Mask interrupt generation for PIO access error from RDC 5009 * 1: Mask interrupt generation for PIO access error from PFC 5010 * 1: Mask interrupt generation for PIO access error from VMAC 5011 * 1: Mask interrupt generation for parity error from Completion 5012 * Header Q memory 5013 * 1: Mask interrupt generation for parity error from Completion 5014 * Data Q memory 5015 * 1: Mask interrupt generation for parity error from Retry 5016 * memory 5017 * 1: Mask interrupt generation for parity error from Retry SOT 5018 * memory 5019 * 1: Mask interrupt generation for parity error from Posted 5020 * Header Q memory 5021 * 1: Mask interrupt generation for parity error from Posted Data 5022 * Q memory 5023 * 1: Mask interrupt generation for parity error from Non-Posted 5024 * Header Q memory 5025 * 1: Mask interrupt generation for parity error from Non-Posted 5026 * Data Q memory 5027 * 1: Mask interrupt generation for parity error from MSIX memory 5028 * 1: Mask interrupt generation for parity error from HCR memory 5029 */ 5030 typedef union { 5031 uint32_t value; 5032 struct { 5033 #if defined(_BIG_ENDIAN) 5034 uint32_t rsrvd:11; 5035 uint32_t spc_acc_err_mask:1; 5036 uint32_t tdc_pioacc_err_mask:1; 5037 uint32_t rdc_pioacc_err_mask:1; 5038 uint32_t pfc_pioacc_err_mask:1; 5039 uint32_t vmac_pioacc_err_mask:1; 5040 uint32_t rsrvd1:6; 5041 uint32_t cpl_hdrq_parerr_mask:1; 5042 uint32_t cpl_dataq_parerr_mask:1; 5043 uint32_t retryram_xdlh_parerr_mask:1; 5044 uint32_t retrysotram_xdlh_parerr_mask:1; 5045 uint32_t p_hdrq_parerr_mask:1; 5046 uint32_t p_dataq_parerr_mask:1; 5047 uint32_t np_hdrq_parerr_mask:1; 5048 uint32_t np_dataq_parerr_mask:1; 5049 uint32_t eic_msix_parerr_mask:1; 5050 uint32_t hcr_parerr_mask:1; 5051 #else 5052 uint32_t hcr_parerr_mask:1; 5053 uint32_t eic_msix_parerr_mask:1; 5054 uint32_t np_dataq_parerr_mask:1; 5055 uint32_t np_hdrq_parerr_mask:1; 5056 uint32_t p_dataq_parerr_mask:1; 5057 uint32_t p_hdrq_parerr_mask:1; 5058 uint32_t retrysotram_xdlh_parerr_mask:1; 5059 uint32_t retryram_xdlh_parerr_mask:1; 5060 uint32_t cpl_dataq_parerr_mask:1; 5061 uint32_t cpl_hdrq_parerr_mask:1; 5062 uint32_t rsrvd1:6; 5063 uint32_t vmac_pioacc_err_mask:1; 5064 uint32_t pfc_pioacc_err_mask:1; 5065 uint32_t rdc_pioacc_err_mask:1; 5066 uint32_t tdc_pioacc_err_mask:1; 5067 uint32_t spc_acc_err_mask:1; 5068 uint32_t rsrvd:11; 5069 #endif 5070 } bits; 5071 } peu_intr_mask_t; 5072 5073 5074 /* 5075 * Register: PeuIntrStatMirror 5076 * Parity Error Status Mirror 5077 * Description: Mirror bits for Parity error generation in the PEU 5078 * RAMs When set, the corresponding parity error is generated ; this 5079 * will cause an interrupt to occur if the respective mask bit is not 5080 * set. As the mirror of the Parity Error Status Register, clearing 5081 * of the status bits is controlled by how the Parity Error Status 5082 * Register is cleared. These bits cannot be cleared by writing 0 to 5083 * this register. 5084 * 5085 * Fields: 5086 */ 5087 typedef union { 5088 uint32_t value; 5089 struct { 5090 #if defined(_BIG_ENDIAN) 5091 uint32_t rsrvd:11; 5092 uint32_t spc_acc_err_mirror:1; 5093 uint32_t tdc_pioacc_err_mirror:1; 5094 uint32_t rdc_pioacc_err_mirror:1; 5095 uint32_t pfc_pioacc_err_mirror:1; 5096 uint32_t vmac_pioacc_err_mirror:1; 5097 uint32_t rsrvd1:6; 5098 uint32_t cpl_hdrq_parerr_mirror:1; 5099 uint32_t cpl_dataq_parerr_mirror:1; 5100 uint32_t retryram_xdlh_parerr_mirror:1; 5101 uint32_t retrysotram_xdlh_parerr_mirror:1; 5102 uint32_t p_hdrq_parerr_mirror:1; 5103 uint32_t p_dataq_parerr_mirror:1; 5104 uint32_t np_hdrq_parerr_mirror:1; 5105 uint32_t np_dataq_parerr_mirror:1; 5106 uint32_t eic_msix_parerr_mirror:1; 5107 uint32_t hcr_parerr_mirror:1; 5108 #else 5109 uint32_t hcr_parerr_mirror:1; 5110 uint32_t eic_msix_parerr_mirror:1; 5111 uint32_t np_dataq_parerr_mirror:1; 5112 uint32_t np_hdrq_parerr_mirror:1; 5113 uint32_t p_dataq_parerr_mirror:1; 5114 uint32_t p_hdrq_parerr_mirror:1; 5115 uint32_t retrysotram_xdlh_parerr_mirror:1; 5116 uint32_t retryram_xdlh_parerr_mirror:1; 5117 uint32_t cpl_dataq_parerr_mirror:1; 5118 uint32_t cpl_hdrq_parerr_mirror:1; 5119 uint32_t rsrvd1:6; 5120 uint32_t vmac_pioacc_err_mirror:1; 5121 uint32_t pfc_pioacc_err_mirror:1; 5122 uint32_t rdc_pioacc_err_mirror:1; 5123 uint32_t tdc_pioacc_err_mirror:1; 5124 uint32_t spc_acc_err_mirror:1; 5125 uint32_t rsrvd:11; 5126 #endif 5127 } bits; 5128 } peu_intr_stat_mirror_t; 5129 5130 5131 /* 5132 * Register: CplHdrqPerrLoc 5133 * Completion Header Queue Parity Error Location 5134 * Description: Returns the location of the first parity error 5135 * detected in Completion Header Q 5136 * 5137 * Fields: 5138 */ 5139 typedef union { 5140 uint32_t value; 5141 struct { 5142 #if defined(_BIG_ENDIAN) 5143 uint32_t rsrvd:16; 5144 uint32_t cpl_hdrq_parerr_loc:16; 5145 #else 5146 uint32_t cpl_hdrq_parerr_loc:16; 5147 uint32_t rsrvd:16; 5148 #endif 5149 } bits; 5150 } cpl_hdrq_perr_loc_t; 5151 5152 5153 /* 5154 * Register: CplDataqPerrLoc 5155 * Completion Data Queue Parity Error Location 5156 * Description: Returns the location of the first parity error 5157 * detected in Completion Data Q 5158 * 5159 * Fields: 5160 */ 5161 typedef union { 5162 uint32_t value; 5163 struct { 5164 #if defined(_BIG_ENDIAN) 5165 uint32_t rsrvd:16; 5166 uint32_t cpl_dataq_parerr_loc:16; 5167 #else 5168 uint32_t cpl_dataq_parerr_loc:16; 5169 uint32_t rsrvd:16; 5170 #endif 5171 } bits; 5172 } cpl_dataq_perr_loc_t; 5173 5174 5175 /* 5176 * Register: RetrPerrLoc 5177 * Retry RAM Parity Error Location 5178 * Description: Returns the location of the first parity error 5179 * detected in Retry RAM 5180 * 5181 * Fields: 5182 */ 5183 typedef union { 5184 uint32_t value; 5185 struct { 5186 #if defined(_BIG_ENDIAN) 5187 uint32_t rsrvd:16; 5188 uint32_t retr_parerr_loc:16; 5189 #else 5190 uint32_t retr_parerr_loc:16; 5191 uint32_t rsrvd:16; 5192 #endif 5193 } bits; 5194 } retr_perr_loc_t; 5195 5196 5197 /* 5198 * Register: RetrSotPerrLoc 5199 * Retry SOT RAM Parity Error Location 5200 * Description: Returns the location of the first parity error 5201 * detected in Retry RAM SOT 5202 * 5203 * Fields: 5204 */ 5205 typedef union { 5206 uint32_t value; 5207 struct { 5208 #if defined(_BIG_ENDIAN) 5209 uint32_t rsrvd:16; 5210 uint32_t retr_sot_parerr_loc:16; 5211 #else 5212 uint32_t retr_sot_parerr_loc:16; 5213 uint32_t rsrvd:16; 5214 #endif 5215 } bits; 5216 } retr_sot_perr_loc_t; 5217 5218 5219 /* 5220 * Register: PHdrqPerrLoc 5221 * Posted Header Queue Parity Error Location 5222 * Description: Returns the location of the first parity error 5223 * detected in Posted Header Q 5224 * 5225 * Fields: 5226 */ 5227 typedef union { 5228 uint32_t value; 5229 struct { 5230 #if defined(_BIG_ENDIAN) 5231 uint32_t rsrvd:16; 5232 uint32_t p_hdrq_parerr_loc:16; 5233 #else 5234 uint32_t p_hdrq_parerr_loc:16; 5235 uint32_t rsrvd:16; 5236 #endif 5237 } bits; 5238 } p_hdrq_perr_loc_t; 5239 5240 5241 /* 5242 * Register: PDataqPerrLoc 5243 * Posted Data Queue Parity Error Location 5244 * Description: Returns the location of the first parity error 5245 * detected in Posted Data Q 5246 * 5247 * Fields: 5248 */ 5249 typedef union { 5250 uint32_t value; 5251 struct { 5252 #if defined(_BIG_ENDIAN) 5253 uint32_t rsrvd:16; 5254 uint32_t p_dataq_parerr_loc:16; 5255 #else 5256 uint32_t p_dataq_parerr_loc:16; 5257 uint32_t rsrvd:16; 5258 #endif 5259 } bits; 5260 } p_dataq_perr_loc_t; 5261 5262 5263 /* 5264 * Register: NpHdrqPerrLoc 5265 * Non-Posted Header Queue Parity Error Location 5266 * Description: Returns the location of the first parity error 5267 * detected in Non-Posted Header Q 5268 * 5269 * Fields: 5270 */ 5271 typedef union { 5272 uint32_t value; 5273 struct { 5274 #if defined(_BIG_ENDIAN) 5275 uint32_t rsrvd:16; 5276 uint32_t np_hdrq_parerr_loc:16; 5277 #else 5278 uint32_t np_hdrq_parerr_loc:16; 5279 uint32_t rsrvd:16; 5280 #endif 5281 } bits; 5282 } np_hdrq_perr_loc_t; 5283 5284 5285 /* 5286 * Register: NpDataqPerrLoc 5287 * Non-Posted Data Queue Parity Error Location 5288 * Description: Returns the location of the first parity error 5289 * detected in Non-Posted Data Q 5290 * 5291 * Fields: 5292 */ 5293 typedef union { 5294 uint32_t value; 5295 struct { 5296 #if defined(_BIG_ENDIAN) 5297 uint32_t rsrvd:16; 5298 uint32_t np_dataq_parerr_loc:16; 5299 #else 5300 uint32_t np_dataq_parerr_loc:16; 5301 uint32_t rsrvd:16; 5302 #endif 5303 } bits; 5304 } np_dataq_perr_loc_t; 5305 5306 5307 /* 5308 * Register: MsixPerrLoc 5309 * MSIX Parity Error Location 5310 * Description: Returns the location of the first parity error 5311 * detected in MSIX memory 5312 * 5313 * Fields: 5314 */ 5315 typedef union { 5316 uint32_t value; 5317 struct { 5318 #if defined(_BIG_ENDIAN) 5319 uint32_t rsrvd:16; 5320 uint32_t eic_msix_parerr_loc:16; 5321 #else 5322 uint32_t eic_msix_parerr_loc:16; 5323 uint32_t rsrvd:16; 5324 #endif 5325 } bits; 5326 } msix_perr_loc_t; 5327 5328 5329 /* 5330 * Register: HcrPerrLoc 5331 * HCR Memory Parity Error Location 5332 * Description: Returns the location of the first parity error 5333 * detected in HCR Memory 5334 * 5335 * Fields: 5336 */ 5337 typedef union { 5338 uint32_t value; 5339 struct { 5340 #if defined(_BIG_ENDIAN) 5341 uint32_t rsrvd:16; 5342 uint32_t hcr_parerr_loc:16; 5343 #else 5344 uint32_t hcr_parerr_loc:16; 5345 uint32_t rsrvd:16; 5346 #endif 5347 } bits; 5348 } hcr_perr_loc_t; 5349 5350 5351 /* 5352 * Register: TdcPioaccErrLog 5353 * TDC PIO Access Error Location 5354 * Description: Returns the location of the first transaction 5355 * location that resulted in error 5356 * 5357 * Fields: 5358 * Type of access error 0 : Block returned error condition 1 : 5359 * Transaction resulted in time out by CIP 5360 * Transaction Location that resulted in error 5361 */ 5362 typedef union { 5363 uint32_t value; 5364 struct { 5365 #if defined(_BIG_ENDIAN) 5366 uint32_t rsrvd:11; 5367 uint32_t tdc_pioacc_err_type:1; 5368 uint32_t tdc_pioacc_err_loc:20; 5369 #else 5370 uint32_t tdc_pioacc_err_loc:20; 5371 uint32_t tdc_pioacc_err_type:1; 5372 uint32_t rsrvd:11; 5373 #endif 5374 } bits; 5375 } tdc_pioacc_err_log_t; 5376 5377 5378 /* 5379 * Register: RdcPioaccErrLog 5380 * RDC PIO Access Error Location 5381 * Description: Returns the location of the first transaction 5382 * location that resulted in error 5383 * 5384 * Fields: 5385 * Type of access error 0 : Block returned error condition 1 : 5386 * Transaction resulted in time out by CIP 5387 * Transaction Location that resulted in error 5388 */ 5389 typedef union { 5390 uint32_t value; 5391 struct { 5392 #if defined(_BIG_ENDIAN) 5393 uint32_t rsrvd:11; 5394 uint32_t rdc_pioacc_err_type:1; 5395 uint32_t rdc_pioacc_err_loc:20; 5396 #else 5397 uint32_t rdc_pioacc_err_loc:20; 5398 uint32_t rdc_pioacc_err_type:1; 5399 uint32_t rsrvd:11; 5400 #endif 5401 } bits; 5402 } rdc_pioacc_err_log_t; 5403 5404 5405 /* 5406 * Register: PfcPioaccErrLog 5407 * PFC PIO Access Error Location 5408 * Description: Returns the location of the first transaction 5409 * location that resulted in error 5410 * 5411 * Fields: 5412 * Type of access error 0 : Block returned error condition 1 : 5413 * Transaction resulted in time out by CIP 5414 * Transaction Location that resulted in error 5415 */ 5416 typedef union { 5417 uint32_t value; 5418 struct { 5419 #if defined(_BIG_ENDIAN) 5420 uint32_t rsrvd:11; 5421 uint32_t pfc_pioacc_err_type:1; 5422 uint32_t pfc_pioacc_err_loc:20; 5423 #else 5424 uint32_t pfc_pioacc_err_loc:20; 5425 uint32_t pfc_pioacc_err_type:1; 5426 uint32_t rsrvd:11; 5427 #endif 5428 } bits; 5429 } pfc_pioacc_err_log_t; 5430 5431 5432 /* 5433 * Register: VmacPioaccErrLog 5434 * VMAC PIO Access Error Location 5435 * Description: Returns the location of the first transaction 5436 * location that resulted in error 5437 * 5438 * Fields: 5439 * Type of access error 0 : Block returned error condition 1 : 5440 * Transaction resulted in time out by CIP 5441 * Transaction Location that resulted in error 5442 */ 5443 typedef union { 5444 uint32_t value; 5445 struct { 5446 #if defined(_BIG_ENDIAN) 5447 uint32_t rsrvd:11; 5448 uint32_t vmac_pioacc_err_type:1; 5449 uint32_t vmac_pioacc_err_loc:20; 5450 #else 5451 uint32_t vmac_pioacc_err_loc:20; 5452 uint32_t vmac_pioacc_err_type:1; 5453 uint32_t rsrvd:11; 5454 #endif 5455 } bits; 5456 } vmac_pioacc_err_log_t; 5457 5458 5459 /* 5460 * Register: LdGrpCtrl 5461 * Logical Device Group Control 5462 * Description: LD Group assignment 5463 * Fields: 5464 * Logical device group number of this logical device 5465 */ 5466 typedef union { 5467 uint32_t value; 5468 struct { 5469 #if defined(_BIG_ENDIAN) 5470 uint32_t rsrvd:27; 5471 uint32_t num:5; 5472 #else 5473 uint32_t num:5; 5474 uint32_t rsrvd:27; 5475 #endif 5476 } bits; 5477 } ld_grp_ctrl_t; 5478 5479 5480 /* 5481 * Register: DevErrStat 5482 * Device Error Status 5483 * Description: Device Error Status logs errors that cannot be 5484 * attributed to a given dma channel. It does not duplicate errors 5485 * already observable via specific block logical device groups. 5486 * Device Error Status bits [31:16] feed LDSV0.devErr0 Device Error 5487 * Status bits [15:0] feed LDSV1.devErr1 5488 * Fields: 5489 * Set to 1 if Reorder Buffer/Reorder Table has a single bit 5490 * ecc/parity error. This error condition is asserted by TDC to 5491 * PEU. 5492 * Set to 1 if RX Ctrl or Data FIFO has a single bit ecc error. 5493 * This error condition is asserted by RDC to PEU. 5494 * Set to 1 if any of the external block accesses have resulted 5495 * in error or if a parity error was detected in the SPROM 5496 * internal ram. Refer to peuIntrStat for the errors that 5497 * contribute to this bit. 5498 * Set to 1 if Reorder Buffer/Reorder Table has a double bit 5499 * ecc/parity error. This error condition is asserted by TDC to 5500 * PEU. 5501 * Set to 1 if RX Ctrl or Data FIFO has a double bit ecc error. 5502 * This error condition is asserted by RDC to PEU. 5503 * Set to 1 if any PEU ram (MSI-X, retrybuf/sot, p/np/cpl queues) 5504 * has a parity error Refer to peuIntrStat for the errors that 5505 * contribute to this bit. 5506 */ 5507 typedef union { 5508 uint32_t value; 5509 struct { 5510 #if defined(_BIG_ENDIAN) 5511 uint32_t rsrvd:13; 5512 uint32_t tdc_err0:1; 5513 uint32_t rdc_err0:1; 5514 uint32_t rsrvd1:1; 5515 uint32_t rsrvd2:12; 5516 uint32_t vnm_pio_err1:1; 5517 uint32_t tdc_err1:1; 5518 uint32_t rdc_err1:1; 5519 uint32_t peu_err1:1; 5520 #else 5521 uint32_t peu_err1:1; 5522 uint32_t rdc_err1:1; 5523 uint32_t tdc_err1:1; 5524 uint32_t vnm_pio_err1:1; 5525 uint32_t rsrvd2:12; 5526 uint32_t rsrvd1:1; 5527 uint32_t rdc_err0:1; 5528 uint32_t tdc_err0:1; 5529 uint32_t rsrvd:13; 5530 #endif 5531 } bits; 5532 } dev_err_stat_t; 5533 5534 5535 /* 5536 * Register: DevErrMask 5537 * Device Error Mask 5538 * Description: Device Error Mask (gates devErrStat) 5539 * Fields: 5540 * Mask for TDC error0 5541 * Mask for RDC error0 5542 * Mask for VNM PIO Access error 5543 * Mask for TDC error1 5544 * Mask for RDC error1 5545 * Mask for PEU memories parity error 5546 */ 5547 typedef union { 5548 uint32_t value; 5549 struct { 5550 #if defined(_BIG_ENDIAN) 5551 uint32_t rsrvd:13; 5552 uint32_t tdc_mask0:1; 5553 uint32_t rdc_mask0:1; 5554 uint32_t rsrvd1:1; 5555 uint32_t rsrvd2:12; 5556 uint32_t vnm_pio_mask1:1; 5557 uint32_t tdc_mask1:1; 5558 uint32_t rdc_mask1:1; 5559 uint32_t peu_mask1:1; 5560 #else 5561 uint32_t peu_mask1:1; 5562 uint32_t rdc_mask1:1; 5563 uint32_t tdc_mask1:1; 5564 uint32_t vnm_pio_mask1:1; 5565 uint32_t rsrvd2:12; 5566 uint32_t rsrvd1:1; 5567 uint32_t rdc_mask0:1; 5568 uint32_t tdc_mask0:1; 5569 uint32_t rsrvd:13; 5570 #endif 5571 } bits; 5572 } dev_err_mask_t; 5573 5574 5575 /* 5576 * Register: LdIntrTimRes 5577 * Logical Device Interrupt Timer Resolution 5578 * Description: Logical Device Interrupt Timer Resolution 5579 * Fields: 5580 * Timer resolution in 250 MHz cycles 5581 */ 5582 typedef union { 5583 uint32_t value; 5584 struct { 5585 #if defined(_BIG_ENDIAN) 5586 uint32_t rsrvd:12; 5587 uint32_t res:20; 5588 #else 5589 uint32_t res:20; 5590 uint32_t rsrvd:12; 5591 #endif 5592 } bits; 5593 } ld_intr_tim_res_t; 5594 5595 5596 /* 5597 * Register: LDSV0 5598 * Logical Device State Vector 0 5599 * Description: Logical Device State Vector 0 5600 * Fields: 5601 * Interrupt from mail box3 to HOST 5602 * Interrupt from mail box2 to HOST 5603 * Interrupt from mail box1 to HOST 5604 * Interrupt from mail box0 to HOST 5605 * Flag0 bits for Network MAC 5606 * Flag0 bits for Virtual MAC 5607 * Flag0 bits for Tx DMA channels 3-0 5608 * Flag0 bits for Rx DMA channels 3-0 5609 */ 5610 typedef union { 5611 uint32_t value; 5612 struct { 5613 #if defined(_BIG_ENDIAN) 5614 uint32_t dev_err0:1; 5615 uint32_t rsrvd:7; 5616 uint32_t mbox3_irq:1; 5617 uint32_t mbox2_irq:1; 5618 uint32_t mbox1_irq:1; 5619 uint32_t mbox0_irq:1; 5620 uint32_t rsrvd1:1; 5621 uint32_t nmac_f0:1; 5622 uint32_t pfc_f0:1; 5623 uint32_t vmac_f0:1; 5624 uint32_t rsrvd2:4; 5625 uint32_t tdc_f0:4; 5626 uint32_t rsrvd3:4; 5627 uint32_t rdc_f0:4; 5628 #else 5629 uint32_t rdc_f0:4; 5630 uint32_t rsrvd3:4; 5631 uint32_t tdc_f0:4; 5632 uint32_t rsrvd2:4; 5633 uint32_t vmac_f0:1; 5634 uint32_t pfc_f0:1; 5635 uint32_t nmac_f0:1; 5636 uint32_t rsrvd1:1; 5637 uint32_t mbox0_irq:1; 5638 uint32_t mbox1_irq:1; 5639 uint32_t mbox2_irq:1; 5640 uint32_t mbox3_irq:1; 5641 uint32_t rsrvd:7; 5642 uint32_t dev_err0:1; 5643 #endif 5644 } bits; 5645 } ldsv0_t; 5646 5647 5648 /* 5649 * Register: LDSV1 5650 * Logical Device State Vector 1 5651 * Description: Logical Device State Vector 1 5652 * Fields: 5653 * Flag1 bits for Network MAC 5654 * Flag1 bits for Tx DMA channels 3-0 5655 * Flag1 bits for Rx DMA channels 3-0 5656 */ 5657 typedef union { 5658 uint32_t value; 5659 struct { 5660 #if defined(_BIG_ENDIAN) 5661 uint32_t dev_err1:1; 5662 uint32_t rsrvd:7; 5663 uint32_t rsrvd1:5; 5664 uint32_t nmac_f1:1; 5665 uint32_t rsrvd2:1; 5666 uint32_t rsrvd3:1; 5667 uint32_t rsrvd4:4; 5668 uint32_t tdc_f1:4; 5669 uint32_t rsrvd5:4; 5670 uint32_t rdc_f1:4; 5671 #else 5672 uint32_t rdc_f1:4; 5673 uint32_t rsrvd5:4; 5674 uint32_t tdc_f1:4; 5675 uint32_t rsrvd4:4; 5676 uint32_t rsrvd3:1; 5677 uint32_t rsrvd2:1; 5678 uint32_t nmac_f1:1; 5679 uint32_t rsrvd1:5; 5680 uint32_t rsrvd:7; 5681 uint32_t dev_err1:1; 5682 #endif 5683 } bits; 5684 } ldsv1_t; 5685 5686 5687 /* 5688 * Register: LdIntrMask 5689 * Logical Device Interrupt Mask 5690 * Description: Logical Device Interrupt Mask 5691 * Fields: 5692 * Flag1 mask for logical device N (0-31) 5693 * Flag0 mask for logical device N (0-31) 5694 */ 5695 typedef union { 5696 uint32_t value; 5697 struct { 5698 #if defined(_BIG_ENDIAN) 5699 uint32_t rsrvd:30; 5700 uint32_t ldf1_mask:1; 5701 uint32_t ldf0_mask:1; 5702 #else 5703 uint32_t ldf0_mask:1; 5704 uint32_t ldf1_mask:1; 5705 uint32_t rsrvd:30; 5706 #endif 5707 } bits; 5708 } ld_intr_mask_t; 5709 5710 5711 /* 5712 * Register: LdIntrMgmt 5713 * Logical Device Interrupt Management 5714 * Description: Logical Device Interrupt Management 5715 * Fields: 5716 * SW arms the logical device for interrupt. Cleared by HW after 5717 * interrupt issued. (1 = arm) 5718 * Timer set by SW. Hardware counts down. 5719 */ 5720 typedef union { 5721 uint32_t value; 5722 struct { 5723 #if defined(_BIG_ENDIAN) 5724 uint32_t arm:1; 5725 uint32_t rsrvd:25; 5726 uint32_t timer:6; 5727 #else 5728 uint32_t timer:6; 5729 uint32_t rsrvd:25; 5730 uint32_t arm:1; 5731 #endif 5732 } bits; 5733 } ld_intr_mgmt_t; 5734 5735 5736 /* 5737 * Register: SID 5738 * System Interrupt Data 5739 * Description: System Interrupt Data (MSI Vectors) 5740 * Fields: 5741 * Data sent along with the interrupt 5742 */ 5743 typedef union { 5744 uint32_t value; 5745 struct { 5746 #if defined(_BIG_ENDIAN) 5747 uint32_t rsrvd:27; 5748 uint32_t data:5; 5749 #else 5750 uint32_t data:5; 5751 uint32_t rsrvd:27; 5752 #endif 5753 } bits; 5754 } sid_t; 5755 5756 5757 #ifdef __cplusplus 5758 } 5759 #endif 5760 5761 #endif /* _HXGE_PEU_HW_H */ 5762