1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_HXGE_HXGE_H 27 #define _SYS_HXGE_HXGE_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <hxge_vmac.h> 36 #include <hxge_pfc.h> 37 #include <hxge_classify.h> 38 39 /* 40 * HXGE diagnostics IOCTLS. 41 */ 42 #define HXGE_IOC ((((('N' << 8) + 'X') << 8) + 'G') << 8) 43 44 #define HXGE_GET64 (HXGE_IOC|1) 45 #define HXGE_PUT64 (HXGE_IOC|2) 46 #define HXGE_GET_TX_RING_SZ (HXGE_IOC|3) 47 #define HXGE_GET_TX_DESC (HXGE_IOC|4) 48 #define HXGE_GLOBAL_RESET (HXGE_IOC|5) 49 #define HXGE_TX_SIDE_RESET (HXGE_IOC|6) 50 #define HXGE_RX_SIDE_RESET (HXGE_IOC|7) 51 #define HXGE_RESET_MAC (HXGE_IOC|8) 52 #define HXGE_RTRACE (HXGE_IOC|9) 53 #define HXGE_GET_TCAM (HXGE_IOC|10) 54 #define HXGE_PUT_TCAM (HXGE_IOC|11) 55 56 #define HXGE_OK 0 57 #define HXGE_ERROR 0x40000000 58 #define HXGE_DDI_FAILED 0x20000000 59 60 /* 61 * Definitions for module_info. 62 */ 63 #define HXGE_DRIVER_NAME "hxge" /* module name */ 64 #define HXGE_CHECK_TIMER (5000) 65 66 typedef enum { 67 param_instance, 68 69 param_accept_jumbo, 70 param_rxdma_rbr_size, 71 param_rxdma_rcr_size, 72 param_rxdma_intr_time, 73 param_rxdma_intr_pkts, 74 param_vlan_ids, 75 param_implicit_vlan_id, 76 param_tcam_enable, 77 78 param_hash_init_value, 79 param_class_cfg_ether_usr1, 80 param_class_cfg_ether_usr2, 81 param_class_opt_ipv4_tcp, 82 param_class_opt_ipv4_udp, 83 param_class_opt_ipv4_ah, 84 param_class_opt_ipv4_sctp, 85 param_class_opt_ipv6_tcp, 86 param_class_opt_ipv6_udp, 87 param_class_opt_ipv6_ah, 88 param_class_opt_ipv6_sctp, 89 param_hxge_debug_flag, 90 param_hpi_debug_flag, 91 param_dump_ptrs, 92 param_end 93 } hxge_param_index_t; 94 95 96 #define HXGE_PARAM_READ 0x00000001ULL 97 #define HXGE_PARAM_WRITE 0x00000002ULL 98 #define HXGE_PARAM_SHARED 0x00000004ULL 99 #define HXGE_PARAM_PRIV 0x00000008ULL 100 #define HXGE_PARAM_RW HXGE_PARAM_READ | HXGE_PARAM_WRITE 101 #define HXGE_PARAM_RWS HXGE_PARAM_RW | HXGE_PARAM_SHARED 102 #define HXGE_PARAM_RWP HXGE_PARAM_RW | HXGE_PARAM_PRIV 103 104 #define HXGE_PARAM_RXDMA 0x00000010ULL 105 #define HXGE_PARAM_TXDMA 0x00000020ULL 106 #define HXGE_PARAM_MAC 0x00000040ULL 107 108 #define HXGE_PARAM_CMPLX 0x00010000ULL 109 #define HXGE_PARAM_NDD_WR_OK 0x00020000ULL 110 #define HXGE_PARAM_INIT_ONLY 0x00040000ULL 111 #define HXGE_PARAM_INIT_CONFIG 0x00080000ULL 112 113 #define HXGE_PARAM_READ_PROP 0x00100000ULL 114 #define HXGE_PARAM_PROP_ARR32 0x00200000ULL 115 #define HXGE_PARAM_PROP_ARR64 0x00400000ULL 116 #define HXGE_PARAM_PROP_STR 0x00800000ULL 117 118 #define HXGE_PARAM_DONT_SHOW 0x80000000ULL 119 120 #define HXGE_PARAM_ARRAY_CNT_MASK 0x0000ffff00000000ULL 121 #define HXGE_PARAM_ARRAY_CNT_SHIFT 32ULL 122 #define HXGE_PARAM_ARRAY_ALLOC_MASK 0xffff000000000000ULL 123 #define HXGE_PARAM_ARRAY_ALLOC_SHIFT 48ULL 124 125 typedef struct _hxge_param_t { 126 int (*getf)(); 127 int (*setf)(); /* null for read only */ 128 uint64_t type; /* R/W/ Common/Port/ .... */ 129 uint64_t minimum; 130 uint64_t maximum; 131 uint64_t value; /* for array params, pointer to value array */ 132 uint64_t old_value; /* for array params, pointer to old_value array */ 133 char *fcode_name; 134 char *name; 135 } hxge_param_t, *p_hxge_param_t; 136 137 138 typedef enum { 139 hxge_lb_normal, 140 hxge_lb_mac10g 141 } hxge_lb_t; 142 143 enum hxge_mac_state { 144 HXGE_MAC_STOPPED = 0, 145 HXGE_MAC_STARTED 146 }; 147 148 typedef struct _filter_t { 149 uint32_t all_phys_cnt; 150 uint32_t all_multicast_cnt; 151 uint32_t all_sap_cnt; 152 } filter_t, *p_filter_t; 153 154 typedef struct _hxge_port_stats_t { 155 hxge_lb_t lb_mode; 156 uint32_t poll_mode; 157 } hxge_port_stats_t, *p_hxge_port_stats_t; 158 159 160 typedef struct _hxge_peu_sys_stats { 161 uint32_t spc_acc_err; 162 uint32_t tdc_pioacc_err; 163 uint32_t rdc_pioacc_err; 164 uint32_t pfc_pioacc_err; 165 uint32_t vmac_pioacc_err; 166 uint32_t cpl_hdrq_parerr; 167 uint32_t cpl_dataq_parerr; 168 uint32_t retryram_xdlh_parerr; 169 uint32_t retrysotram_xdlh_parerr; 170 uint32_t p_hdrq_parerr; 171 uint32_t p_dataq_parerr; 172 uint32_t np_hdrq_parerr; 173 uint32_t np_dataq_parerr; 174 uint32_t eic_msix_parerr; 175 uint32_t hcr_parerr; 176 } hxge_peu_sys_stats_t, *p_hxge_peu_sys_stats_t; 177 178 179 typedef struct _hxge_stats_t { 180 /* 181 * Overall structure size 182 */ 183 size_t stats_size; 184 185 kstat_t *ksp; 186 kstat_t *rdc_ksp[HXGE_MAX_RDCS]; 187 kstat_t *tdc_ksp[HXGE_MAX_TDCS]; 188 kstat_t *rdc_sys_ksp; 189 kstat_t *tdc_sys_ksp; 190 kstat_t *pfc_ksp; 191 kstat_t *vmac_ksp; 192 kstat_t *port_ksp; 193 kstat_t *mmac_ksp; 194 kstat_t *peu_sys_ksp; 195 196 hxge_mac_stats_t mac_stats; 197 hxge_vmac_stats_t vmac_stats; /* VMAC Statistics */ 198 199 hxge_rx_ring_stats_t rdc_stats[HXGE_MAX_RDCS]; /* per rdc stats */ 200 hxge_rdc_sys_stats_t rdc_sys_stats; /* RDC system stats */ 201 202 hxge_tx_ring_stats_t tdc_stats[HXGE_MAX_TDCS]; /* per tdc stats */ 203 hxge_tdc_sys_stats_t tdc_sys_stats; /* TDC system stats */ 204 205 hxge_pfc_stats_t pfc_stats; /* pfc stats */ 206 hxge_port_stats_t port_stats; /* port stats */ 207 hxge_mmac_stats_t mmac_stats; /* Multi mac. stats */ 208 209 hxge_peu_sys_stats_t peu_sys_stats; /* PEU system stats */ 210 } hxge_stats_t, *p_hxge_stats_t; 211 212 typedef struct _hxge_intr_t { 213 boolean_t intr_registered; /* interrupts are registered */ 214 boolean_t intr_enabled; /* interrupts are enabled */ 215 boolean_t niu_msi_enable; /* debug or configurable? */ 216 uint8_t nldevs; /* # of logical devices */ 217 int intr_types; /* interrupt types supported */ 218 int intr_type; /* interrupt type to add */ 219 int msi_intx_cnt; /* # msi/intx ints returned */ 220 int intr_added; /* # ints actually needed */ 221 int intr_cap; /* interrupt capabilities */ 222 size_t intr_size; /* size of array to allocate */ 223 ddi_intr_handle_t *htable; /* For array of interrupts */ 224 /* Add interrupt number for each interrupt vector */ 225 int pri; 226 } hxge_intr_t, *p_hxge_intr_t; 227 228 typedef struct _hxge_ldgv_t { 229 uint8_t ndma_ldvs; 230 uint8_t nldvs; 231 uint8_t start_ldg; 232 uint8_t maxldgs; 233 uint8_t maxldvs; 234 uint8_t ldg_intrs; 235 uint32_t tmres; 236 p_hxge_ldg_t ldgp; 237 p_hxge_ldv_t ldvp; 238 p_hxge_ldv_t ldvp_syserr; 239 } hxge_ldgv_t, *p_hxge_ldgv_t; 240 241 /* 242 * Hydra Device instance state information. 243 * Each instance is dynamically allocated on first attach. 244 */ 245 struct _hxge_t { 246 dev_info_t *dip; /* device instance */ 247 dev_info_t *p_dip; /* Parent's device instance */ 248 int instance; /* instance number */ 249 uint32_t drv_state; /* driver state bit flags */ 250 uint64_t hxge_debug_level; /* driver state bit flags */ 251 kmutex_t genlock[1]; 252 enum hxge_mac_state hxge_mac_state; 253 ddi_softintr_t resched_id; /* reschedule callback */ 254 boolean_t resched_needed; 255 boolean_t resched_running; 256 257 p_dev_regs_t dev_regs; 258 hpi_handle_t hpi_handle; 259 hpi_handle_t hpi_pci_handle; 260 hpi_handle_t hpi_reg_handle; 261 hpi_handle_t hpi_msi_handle; 262 263 hxge_vmac_t vmac; 264 hxge_classify_t classifier; 265 266 mac_handle_t mach; /* mac module handle */ 267 268 p_hxge_stats_t statsp; 269 uint32_t param_count; 270 p_hxge_param_t param_arr; 271 hxge_hw_list_t *hxge_hw_p; /* pointer to per Hydra */ 272 uint8_t nrdc; 273 uint8_t rdc[HXGE_MAX_RDCS]; 274 uint8_t ntdc; 275 uint8_t tdc[HXGE_MAX_TDCS]; 276 277 hxge_intr_t hxge_intr_type; 278 hxge_dma_pt_cfg_t pt_config; 279 hxge_class_pt_cfg_t class_config; 280 281 /* Logical device and group data structures. */ 282 p_hxge_ldgv_t ldgvp; 283 284 caddr_t param_list; /* Parameter list */ 285 286 ether_addr_st factaddr; /* factory mac address */ 287 ether_addr_st ouraddr; /* individual address */ 288 kmutex_t ouraddr_lock; /* lock to protect to uradd */ 289 290 ddi_iblock_cookie_t interrupt_cookie; 291 292 /* 293 * Blocks of memory may be pre-allocated by the 294 * partition manager or the driver. They may include 295 * blocks for configuration and buffers. The idea is 296 * to preallocate big blocks of contiguous areas in 297 * system memory (i.e. with IOMMU). These blocks then 298 * will be broken up to a fixed number of blocks with 299 * each block having the same block size (4K, 8K, 16K or 300 * 32K) in the case of buffer blocks. For systems that 301 * do not support DVMA, more than one big block will be 302 * allocated. 303 */ 304 uint32_t rx_default_block_size; 305 hxge_rx_block_size_t rx_bksize_code; 306 307 p_hxge_dma_pool_t rx_buf_pool_p; 308 p_hxge_dma_pool_t rx_cntl_pool_p; 309 310 p_hxge_dma_pool_t tx_buf_pool_p; 311 p_hxge_dma_pool_t tx_cntl_pool_p; 312 313 /* Receive buffer block ring and completion ring. */ 314 p_rx_rbr_rings_t rx_rbr_rings; 315 p_rx_rcr_rings_t rx_rcr_rings; 316 p_rx_mbox_areas_t rx_mbox_areas_p; 317 318 uint32_t start_rdc; 319 uint32_t max_rdcs; 320 321 /* Transmit descriptors rings */ 322 p_tx_rings_t tx_rings; 323 p_tx_mbox_areas_t tx_mbox_areas_p; 324 325 uint32_t start_tdc; 326 uint32_t max_tdcs; 327 uint32_t tdc_mask; 328 329 ddi_dma_handle_t dmasparehandle; 330 331 ulong_t sys_page_sz; 332 ulong_t sys_page_mask; 333 int suspended; 334 335 filter_t filter; /* Current instance filter */ 336 p_hash_filter_t hash_filter; /* Multicast hash filter. */ 337 krwlock_t filter_lock; /* Lock to protect filters. */ 338 339 ulong_t sys_burst_sz; 340 timeout_id_t hxge_timerid; 341 uint8_t msg_min; 342 343 uint16_t intr_timeout; 344 uint16_t intr_threshold; 345 346 rtrace_t rtrace; 347 int fm_capabilities; /* FMA capabilities */ 348 349 uint32_t hxge_port_rbr_size; 350 uint32_t hxge_port_rcr_size; 351 uint32_t hxge_port_tx_ring_size; 352 hxge_mmac_t hxge_mmac_info; 353 }; 354 355 /* 356 * Driver state flags. 357 */ 358 #define STATE_REGS_MAPPED 0x000000001 /* device registers mapped */ 359 #define STATE_KSTATS_SETUP 0x000000002 /* kstats allocated */ 360 #define STATE_NODE_CREATED 0x000000004 /* device node created */ 361 #define STATE_HW_CONFIG_CREATED 0x000000008 /* hardware properties */ 362 #define STATE_HW_INITIALIZED 0x000000010 /* hardware initialized */ 363 364 typedef struct _hxge_port_kstat_t { 365 /* 366 * Transciever state informations. 367 */ 368 kstat_named_t cap_autoneg; 369 kstat_named_t cap_10gfdx; 370 371 /* 372 * Link partner capabilities. 373 */ 374 kstat_named_t lp_cap_autoneg; 375 kstat_named_t lp_cap_10gfdx; 376 377 /* 378 * Shared link setup. 379 */ 380 kstat_named_t link_speed; 381 kstat_named_t link_duplex; 382 kstat_named_t link_up; 383 384 /* 385 * Lets the user know the MTU currently in use by 386 * the physical MAC port. 387 */ 388 kstat_named_t lb_mode; 389 390 kstat_named_t tx_max_pend; 391 kstat_named_t rx_jumbo_pkts; 392 393 /* 394 * Misc MAC statistics. 395 */ 396 kstat_named_t ifspeed; 397 kstat_named_t promisc; 398 } hxge_port_kstat_t, *p_hxge_port_kstat_t; 399 400 typedef struct _hxge_rdc_kstat { 401 /* 402 * Receive DMA channel statistics. 403 * This structure needs to be consistent with hxge_rdc_stat_index_t 404 * in hxge_kstat.c 405 */ 406 kstat_named_t ipackets; 407 kstat_named_t rbytes; 408 kstat_named_t errors; 409 kstat_named_t jumbo_pkts; 410 411 kstat_named_t rcr_unknown_err; 412 kstat_named_t rcr_sha_par_err; 413 kstat_named_t rbr_pre_par_err; 414 kstat_named_t rbr_pre_emty; 415 416 kstat_named_t rcr_shadow_full; 417 kstat_named_t rbr_tmout; 418 kstat_named_t peu_resp_err; 419 420 kstat_named_t ctrl_fifo_ecc_err; 421 kstat_named_t data_fifo_ecc_err; 422 423 kstat_named_t rcrfull; 424 kstat_named_t rbr_empty; 425 kstat_named_t rbrfull; 426 427 kstat_named_t rcr_to; 428 kstat_named_t rcr_thresh; 429 } hxge_rdc_kstat_t, *p_hxge_rdc_kstat_t; 430 431 typedef struct _hxge_rdc_sys_kstat { 432 /* 433 * Receive DMA system statistics. 434 * This structure needs to be consistent with hxge_rdc_sys_stat_idx_t 435 * in hxge_kstat.c 436 */ 437 kstat_named_t ctrl_fifo_sec; 438 kstat_named_t ctrl_fifo_ded; 439 kstat_named_t data_fifo_sec; 440 kstat_named_t data_fifo_ded; 441 } hxge_rdc_sys_kstat_t, *p_hxge_rdc_sys_kstat_t; 442 443 typedef struct _hxge_tdc_kstat { 444 /* 445 * Transmit DMA channel statistics. 446 * This structure needs to be consistent with hxge_tdc_stats_index_t 447 * in hxge_kstat.c 448 */ 449 kstat_named_t opackets; 450 kstat_named_t obytes; 451 kstat_named_t obytes_with_pad; 452 kstat_named_t oerrors; 453 kstat_named_t tx_inits; 454 kstat_named_t tx_no_buf; 455 456 kstat_named_t peu_resp_err; 457 kstat_named_t pkt_size_err; 458 kstat_named_t tx_rng_oflow; 459 kstat_named_t pkt_size_hdr_err; 460 kstat_named_t runt_pkt_drop_err; 461 kstat_named_t pref_par_err; 462 kstat_named_t tdr_pref_cpl_to; 463 kstat_named_t pkt_cpl_to; 464 kstat_named_t invalid_sop; 465 kstat_named_t unexpected_sop; 466 467 kstat_named_t count_hdr_size_err; 468 kstat_named_t count_runt; 469 kstat_named_t count_abort; 470 471 kstat_named_t tx_starts; 472 kstat_named_t tx_no_desc; 473 kstat_named_t tx_dma_bind_fail; 474 kstat_named_t tx_hdr_pkts; 475 kstat_named_t tx_ddi_pkts; 476 kstat_named_t tx_jumbo_pkts; 477 kstat_named_t tx_max_pend; 478 kstat_named_t tx_marks; 479 } hxge_tdc_kstat_t, *p_hxge_tdc_kstat_t; 480 481 typedef struct _hxge_tdc_sys_kstat { 482 /* 483 * Transmit DMA system statistics. 484 * This structure needs to be consistent with hxge_tdc_sys_stat_idx_t 485 * in hxge_kstat.c 486 */ 487 kstat_named_t reord_tbl_par_err; 488 kstat_named_t reord_buf_ded_err; 489 kstat_named_t reord_buf_sec_err; 490 } hxge_tdc_sys_kstat_t, *p_hxge_tdc_sys_kstat_t; 491 492 typedef struct _hxge_vmac_kstat { 493 /* 494 * VMAC statistics. 495 * This structure needs to be consistent with hxge_vmac_stat_index_t 496 * in hxge_kstat.c 497 */ 498 kstat_named_t tx_frame_cnt; 499 kstat_named_t tx_byte_cnt; 500 501 kstat_named_t rx_frame_cnt; 502 kstat_named_t rx_byte_cnt; 503 kstat_named_t rx_drop_frame_cnt; 504 kstat_named_t rx_drop_byte_cnt; 505 kstat_named_t rx_crc_cnt; 506 kstat_named_t rx_pause_cnt; 507 kstat_named_t rx_bcast_fr_cnt; 508 kstat_named_t rx_mcast_fr_cnt; 509 } hxge_vmac_kstat_t, *p_hxge_vmac_kstat_t; 510 511 typedef struct _hxge_pfc_kstat { 512 /* 513 * This structure needs to be consistent with hxge_pfc_stat_index_t 514 * in hxge_kstat.c 515 */ 516 kstat_named_t pfc_pkt_drop; 517 kstat_named_t pfc_tcam_parity_err; 518 kstat_named_t pfc_vlan_parity_err; 519 kstat_named_t pfc_bad_cs_count; 520 kstat_named_t pfc_drop_count; 521 kstat_named_t pfc_tcp_ctrl_drop; 522 kstat_named_t pfc_l2_addr_drop; 523 kstat_named_t pfc_class_code_drop; 524 kstat_named_t pfc_tcam_drop; 525 kstat_named_t pfc_vlan_drop; 526 } hxge_pfc_kstat_t, *p_hxge_pfc_kstat_t; 527 528 typedef struct _hxge_mmac_kstat { 529 /* 530 * This structure needs to be consistent with hxge_mmac_stat_index_t 531 * in hxge_kstat.c 532 */ 533 kstat_named_t mmac_max_addr_cnt; 534 kstat_named_t mmac_avail_addr_cnt; 535 kstat_named_t mmac_addr1; 536 kstat_named_t mmac_addr2; 537 kstat_named_t mmac_addr3; 538 kstat_named_t mmac_addr4; 539 kstat_named_t mmac_addr5; 540 kstat_named_t mmac_addr6; 541 kstat_named_t mmac_addr7; 542 kstat_named_t mmac_addr8; 543 kstat_named_t mmac_addr9; 544 kstat_named_t mmac_addr10; 545 kstat_named_t mmac_addr11; 546 kstat_named_t mmac_addr12; 547 kstat_named_t mmac_addr13; 548 kstat_named_t mmac_addr14; 549 kstat_named_t mmac_addr15; 550 kstat_named_t mmac_addr16; 551 } hxge_mmac_kstat_t, *p_hxge_mmac_kstat_t; 552 553 typedef struct _hxge_peu_sys_kstat { 554 /* 555 * This structure needs to be consistent with hxge_peu_sys_stat_idx_t 556 * in hxge_kstat.c 557 */ 558 kstat_named_t spc_acc_err; 559 kstat_named_t tdc_pioacc_err; 560 kstat_named_t rdc_pioacc_err; 561 kstat_named_t pfc_pioacc_err; 562 kstat_named_t vmac_pioacc_err; 563 kstat_named_t cpl_hdrq_parerr; 564 kstat_named_t cpl_dataq_parerr; 565 kstat_named_t retryram_xdlh_parerr; 566 kstat_named_t retrysotram_xdlh_parerr; 567 kstat_named_t p_hdrq_parerr; 568 kstat_named_t p_dataq_parerr; 569 kstat_named_t np_hdrq_parerr; 570 kstat_named_t np_dataq_parerr; 571 kstat_named_t eic_msix_parerr; 572 kstat_named_t hcr_parerr; 573 } hxge_peu_sys_kstat_t, *p_hxge_peu_sys_kstat_t; 574 575 /* 576 * Prototype definitions. 577 */ 578 hxge_status_t hxge_init(p_hxge_t); 579 void hxge_uninit(p_hxge_t); 580 void hxge_get64(p_hxge_t hxgep, p_mblk_t mp); 581 void hxge_put64(p_hxge_t hxgep, p_mblk_t mp); 582 583 typedef void (*fptrv_t)(); 584 timeout_id_t hxge_start_timer(p_hxge_t hxgep, fptrv_t func, int msec); 585 void hxge_stop_timer(p_hxge_t hxgep, timeout_id_t timerid); 586 587 #ifdef __cplusplus 588 } 589 #endif 590 591 #endif /* _SYS_HXGE_HXGE_H */ 592