10219346bSGarrett D'Amore /* 20219346bSGarrett D'Amore * CDDL HEADER START 30219346bSGarrett D'Amore * 40219346bSGarrett D'Amore * The contents of this file are subject to the terms of the 50219346bSGarrett D'Amore * Common Development and Distribution License (the "License"). 60219346bSGarrett D'Amore * You may not use this file except in compliance with the License. 70219346bSGarrett D'Amore * 80219346bSGarrett D'Amore * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 90219346bSGarrett D'Amore * or http://www.opensolaris.org/os/licensing. 100219346bSGarrett D'Amore * See the License for the specific language governing permissions 110219346bSGarrett D'Amore * and limitations under the License. 120219346bSGarrett D'Amore * 130219346bSGarrett D'Amore * When distributing Covered Code, include this CDDL HEADER in each 140219346bSGarrett D'Amore * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 150219346bSGarrett D'Amore * If applicable, add the following below this CDDL HEADER, with the 160219346bSGarrett D'Amore * fields enclosed by brackets "[]" replaced with your own identifying 170219346bSGarrett D'Amore * information: Portions Copyright [yyyy] [name of copyright owner] 180219346bSGarrett D'Amore * 190219346bSGarrett D'Amore * CDDL HEADER END 200219346bSGarrett D'Amore */ 210219346bSGarrett D'Amore /* 220219346bSGarrett D'Amore * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 230219346bSGarrett D'Amore * Use is subject to license terms. 240219346bSGarrett D'Amore */ 250219346bSGarrett D'Amore 260219346bSGarrett D'Amore #ifndef _SYS_HME_H 270219346bSGarrett D'Amore #define _SYS_HME_H 280219346bSGarrett D'Amore 290219346bSGarrett D'Amore #ifdef __cplusplus 300219346bSGarrett D'Amore extern "C" { 310219346bSGarrett D'Amore #endif 320219346bSGarrett D'Amore 330219346bSGarrett D'Amore #ifdef _KERNEL 340219346bSGarrett D'Amore 350219346bSGarrett D'Amore /* default IPG settings */ 360219346bSGarrett D'Amore #define IPG1 8 370219346bSGarrett D'Amore #define IPG2 4 380219346bSGarrett D'Amore 390219346bSGarrett D'Amore /* 400219346bSGarrett D'Amore * Declarations and definitions specific to the 410219346bSGarrett D'Amore * FEPS 10/100 Mbps Ethernet (hme) device. 420219346bSGarrett D'Amore */ 430219346bSGarrett D'Amore 440219346bSGarrett D'Amore /* 450219346bSGarrett D'Amore * Per-Stream instance state information. 460219346bSGarrett D'Amore * 470219346bSGarrett D'Amore * Each instance is dynamically allocated at open() and free'd 480219346bSGarrett D'Amore * at close(). Each per-Stream instance points to at most one 490219346bSGarrett D'Amore * per-device structure using the sb_hmep field. All instances 500219346bSGarrett D'Amore * are threaded together into one list of active instances 510219346bSGarrett D'Amore * ordered on minor device number. 520219346bSGarrett D'Amore */ 530219346bSGarrett D'Amore 540219346bSGarrett D'Amore #define HME_2P0_REVID 0xa0 /* hme - feps. */ 550219346bSGarrett D'Amore #define HME_2P1_REVID 0x20 560219346bSGarrett D'Amore #define HME_2P1_REVID_OBP 0x21 570219346bSGarrett D'Amore #define HME_1C0_REVID 0xc0 /* cheerio 1.0, hme 2.0 equiv. */ 580219346bSGarrett D'Amore #define HME_2C0_REVID 0xc1 /* cheerio 2.0, hme 2.2 equiv. */ 590219346bSGarrett D'Amore #define HME_REV_VERS_MASK 0x0f /* Mask to retain bits for cheerio ver */ 600219346bSGarrett D'Amore 610219346bSGarrett D'Amore typedef struct { 620219346bSGarrett D'Amore ddi_dma_handle_t dmah; 630219346bSGarrett D'Amore ddi_acc_handle_t acch; 640219346bSGarrett D'Amore caddr_t kaddr; 650219346bSGarrett D'Amore uint32_t paddr; 660219346bSGarrett D'Amore } hmebuf_t; 670219346bSGarrett D'Amore 680219346bSGarrett D'Amore /* 690219346bSGarrett D'Amore * HME Device Channel instance state information. 700219346bSGarrett D'Amore * 710219346bSGarrett D'Amore * Each instance is dynamically allocated on first attach. 720219346bSGarrett D'Amore */ 730219346bSGarrett D'Amore struct hme { 740219346bSGarrett D'Amore mac_handle_t hme_mh; /* GLDv3 handle */ 75*06673d9bSGarrett D'Amore mii_handle_t hme_mii; 760219346bSGarrett D'Amore dev_info_t *dip; /* associated dev_info */ 770219346bSGarrett D'Amore int instance; /* instance */ 780219346bSGarrett D'Amore ulong_t pagesize; /* btop(9F) */ 790219346bSGarrett D'Amore 800219346bSGarrett D'Amore int hme_mifpoll_enable; 810219346bSGarrett D'Amore int hme_frame_enable; 820219346bSGarrett D'Amore int hme_lance_mode_enable; 830219346bSGarrett D'Amore int hme_rxcv_enable; 840219346bSGarrett D'Amore 85*06673d9bSGarrett D'Amore uint32_t hme_lance_mode; 86*06673d9bSGarrett D'Amore uint32_t hme_ipg0; 87*06673d9bSGarrett D'Amore uint32_t hme_ipg1; 88*06673d9bSGarrett D'Amore uint32_t hme_ipg2; 89*06673d9bSGarrett D'Amore 900219346bSGarrett D'Amore uint_t hme_burstsizes; /* binary encoded val */ 910219346bSGarrett D'Amore uint32_t hme_config; /* Config reg store */ 920219346bSGarrett D'Amore 930219346bSGarrett D'Amore int hme_phy_failure; /* phy failure type */ 940219346bSGarrett D'Amore 950219346bSGarrett D'Amore int hme_64bit_xfer; /* 64-bit Sbus xfers */ 960219346bSGarrett D'Amore int hme_phyad; 970219346bSGarrett D'Amore 980219346bSGarrett D'Amore int hme_nlasttries; 990219346bSGarrett D'Amore int hme_cheerio_mode; 1000219346bSGarrett D'Amore 1010219346bSGarrett D'Amore struct ether_addr hme_factaddr; /* factory mac address */ 1020219346bSGarrett D'Amore struct ether_addr hme_ouraddr; /* individual address */ 1030219346bSGarrett D'Amore uint32_t hme_addrflags; /* address flags */ 1040219346bSGarrett D'Amore uint32_t hme_flags; /* misc. flags */ 1050219346bSGarrett D'Amore boolean_t hme_wantw; /* xmit: out of resources */ 1060219346bSGarrett D'Amore boolean_t hme_started; /* mac layer started */ 1070219346bSGarrett D'Amore 1080219346bSGarrett D'Amore uint8_t hme_devno; 1090219346bSGarrett D'Amore 1100219346bSGarrett D'Amore uint16_t hme_ladrf[4]; /* 64 bit multicast filter */ 1110219346bSGarrett D'Amore uint32_t hme_ladrf_refcnt[64]; 1120219346bSGarrett D'Amore boolean_t hme_promisc; 1130219346bSGarrett D'Amore uint32_t hme_multi; /* refcount on mcast addrs */ 1140219346bSGarrett D'Amore 1150219346bSGarrett D'Amore struct hme_global *hme_globregp; /* HME global regs */ 1160219346bSGarrett D'Amore struct hme_etx *hme_etxregp; /* HME ETX regs */ 1170219346bSGarrett D'Amore struct hme_erx *hme_erxregp; /* HME ERX regs */ 1180219346bSGarrett D'Amore struct hme_bmac *hme_bmacregp; /* BigMAC registers */ 1190219346bSGarrett D'Amore struct hme_mif *hme_mifregp; /* HME transceiver */ 1200219346bSGarrett D'Amore unsigned char *hme_romp; /* fcode rom pointer */ 1210219346bSGarrett D'Amore 1220219346bSGarrett D'Amore kmutex_t hme_xmitlock; /* protect xmit-side fields */ 1230219346bSGarrett D'Amore kmutex_t hme_intrlock; /* protect intr-side fields */ 1240219346bSGarrett D'Amore ddi_iblock_cookie_t hme_cookie; /* interrupt cookie */ 1250219346bSGarrett D'Amore 1260219346bSGarrett D'Amore struct hme_rmd *hme_rmdp; /* receive descriptor ring start */ 1270219346bSGarrett D'Amore struct hme_tmd *hme_tmdp; /* transmit descriptor ring start */ 1280219346bSGarrett D'Amore 1290219346bSGarrett D'Amore ddi_dma_handle_t hme_rmd_dmah; 1300219346bSGarrett D'Amore ddi_acc_handle_t hme_rmd_acch; 1310219346bSGarrett D'Amore caddr_t hme_rmd_kaddr; 1320219346bSGarrett D'Amore uint32_t hme_rmd_paddr; 1330219346bSGarrett D'Amore 1340219346bSGarrett D'Amore ddi_dma_handle_t hme_tmd_dmah; 1350219346bSGarrett D'Amore ddi_acc_handle_t hme_tmd_acch; 1360219346bSGarrett D'Amore caddr_t hme_tmd_kaddr; 1370219346bSGarrett D'Amore uint32_t hme_tmd_paddr; 1380219346bSGarrett D'Amore 1390219346bSGarrett D'Amore uint64_t hme_rxindex; 1400219346bSGarrett D'Amore uint64_t hme_txindex; 1410219346bSGarrett D'Amore uint64_t hme_txreclaim; 1420219346bSGarrett D'Amore 1430219346bSGarrett D'Amore hmebuf_t *hme_tbuf; /* hmebuf associated with TMD */ 1440219346bSGarrett D'Amore hmebuf_t *hme_rbuf; /* hmebuf associated with RMD */ 1450219346bSGarrett D'Amore 1460219346bSGarrett D'Amore ddi_device_acc_attr_t hme_dev_attr; 1470219346bSGarrett D'Amore ddi_acc_handle_t hme_globregh; /* HME global regs */ 1480219346bSGarrett D'Amore ddi_acc_handle_t hme_etxregh; /* HME ETX regs */ 1490219346bSGarrett D'Amore ddi_acc_handle_t hme_erxregh; /* HME ERX regs */ 1500219346bSGarrett D'Amore ddi_acc_handle_t hme_bmacregh; /* BigMAC registers */ 1510219346bSGarrett D'Amore ddi_acc_handle_t hme_mifregh; /* HME transceiver */ 1520219346bSGarrett D'Amore ddi_acc_handle_t hme_romh; /* rom handle */ 1530219346bSGarrett D'Amore 1540219346bSGarrett D'Amore ddi_acc_handle_t pci_config_handle; /* HME PCI config */ 1550219346bSGarrett D'Amore 1560219346bSGarrett D'Amore /* 1570219346bSGarrett D'Amore * DDI dma handle, kernel virtual base, 1580219346bSGarrett D'Amore * and io virtual base of IOPB area. 1590219346bSGarrett D'Amore */ 1600219346bSGarrett D'Amore ddi_dma_handle_t hme_iopbhandle; 1610219346bSGarrett D'Amore ulong_t hme_iopbkbase; 1620219346bSGarrett D'Amore uint32_t hme_iopbiobase; 1630219346bSGarrett D'Amore 1640219346bSGarrett D'Amore kstat_t *hme_ksp; /* kstat pointer */ 1650219346bSGarrett D'Amore kstat_t *hme_intrstats; /* kstat interrupt counter */ 1660219346bSGarrett D'Amore 1670219346bSGarrett D'Amore uint64_t hme_ipackets; 1680219346bSGarrett D'Amore uint64_t hme_rbytes; 1690219346bSGarrett D'Amore uint64_t hme_ierrors; 1700219346bSGarrett D'Amore uint64_t hme_opackets; 1710219346bSGarrett D'Amore uint64_t hme_obytes; 1720219346bSGarrett D'Amore uint64_t hme_oerrors; 1730219346bSGarrett D'Amore uint64_t hme_multircv; /* # multicast packets received */ 1740219346bSGarrett D'Amore uint64_t hme_multixmt; /* # multicast packets for xmit */ 1750219346bSGarrett D'Amore uint64_t hme_brdcstrcv; /* # broadcast packets received */ 1760219346bSGarrett D'Amore uint64_t hme_brdcstxmt; /* # broadcast packets for xmit */ 1770219346bSGarrett D'Amore uint64_t hme_oflo; 1780219346bSGarrett D'Amore uint64_t hme_uflo; 1790219346bSGarrett D'Amore uint64_t hme_norcvbuf; /* # rcv packets discarded */ 1800219346bSGarrett D'Amore uint64_t hme_noxmtbuf; /* # xmit packets discarded */ 1810219346bSGarrett D'Amore uint64_t hme_duplex; 1820219346bSGarrett D'Amore uint64_t hme_align_errors; 1830219346bSGarrett D'Amore uint64_t hme_coll; 1840219346bSGarrett D'Amore uint64_t hme_fcs_errors; 1850219346bSGarrett D'Amore uint64_t hme_defer_xmts; 1860219346bSGarrett D'Amore uint64_t hme_sqe_errors; 1870219346bSGarrett D'Amore uint64_t hme_excol; 1880219346bSGarrett D'Amore uint64_t hme_fstcol; 1890219346bSGarrett D'Amore uint64_t hme_tlcol; 1900219346bSGarrett D'Amore uint64_t hme_toolong_errors; 1910219346bSGarrett D'Amore uint64_t hme_runt; 1920219346bSGarrett D'Amore uint64_t hme_carrier_errors; 1930219346bSGarrett D'Amore uint64_t hme_jab; 1940219346bSGarrett D'Amore 1950219346bSGarrett D'Amore uint32_t hme_cvc; 1960219346bSGarrett D'Amore uint32_t hme_lenerr; 1970219346bSGarrett D'Amore uint32_t hme_buff; 1980219346bSGarrett D'Amore uint32_t hme_missed; 1990219346bSGarrett D'Amore uint32_t hme_nocanput; 2000219346bSGarrett D'Amore uint32_t hme_allocbfail; 2010219346bSGarrett D'Amore uint32_t hme_babl; 2020219346bSGarrett D'Amore uint32_t hme_tmder; 2030219346bSGarrett D'Amore uint32_t hme_txlaterr; 2040219346bSGarrett D'Amore uint32_t hme_rxlaterr; 2050219346bSGarrett D'Amore uint32_t hme_slvparerr; 2060219346bSGarrett D'Amore uint32_t hme_txparerr; 2070219346bSGarrett D'Amore uint32_t hme_rxparerr; 2080219346bSGarrett D'Amore uint32_t hme_slverrack; 2090219346bSGarrett D'Amore uint32_t hme_txerrack; 2100219346bSGarrett D'Amore uint32_t hme_rxerrack; 2110219346bSGarrett D'Amore uint32_t hme_txtagerr; 2120219346bSGarrett D'Amore uint32_t hme_rxtagerr; 2130219346bSGarrett D'Amore uint32_t hme_eoperr; 2140219346bSGarrett D'Amore uint32_t hme_notmds; 2150219346bSGarrett D'Amore uint32_t hme_notbufs; 2160219346bSGarrett D'Amore uint32_t hme_norbufs; 2170219346bSGarrett D'Amore 2180219346bSGarrett D'Amore /* 2190219346bSGarrett D'Amore * check if transmitter is hung 2200219346bSGarrett D'Amore */ 2210219346bSGarrett D'Amore uint32_t hme_starts; 2220219346bSGarrett D'Amore uint32_t hme_txhung; 2230219346bSGarrett D'Amore time_t hme_msg_time; 2240219346bSGarrett D'Amore 2250219346bSGarrett D'Amore /* 2260219346bSGarrett D'Amore * Debuging kstats 2270219346bSGarrett D'Amore */ 2280219346bSGarrett D'Amore uint32_t inits; 2290219346bSGarrett D'Amore uint32_t phyfail; 2300219346bSGarrett D'Amore uint32_t asic_rev; 2310219346bSGarrett D'Amore }; 2320219346bSGarrett D'Amore 2330219346bSGarrett D'Amore /* flags */ 2340219346bSGarrett D'Amore #define HMERUNNING 0x01 /* chip is initialized */ 2350219346bSGarrett D'Amore #define HMESUSPENDED 0x08 /* suspended interface */ 2360219346bSGarrett D'Amore #define HMEINITIALIZED 0x10 /* interface initialized */ 2370219346bSGarrett D'Amore 2380219346bSGarrett D'Amore /* Mac address flags */ 2390219346bSGarrett D'Amore 2400219346bSGarrett D'Amore #define HME_FACTADDR_PRESENT 0x01 /* factory MAC id present */ 2410219346bSGarrett D'Amore #define HME_FACTADDR_USE 0x02 /* use factory MAC id */ 2420219346bSGarrett D'Amore 2430219346bSGarrett D'Amore struct hmekstat { 2440219346bSGarrett D'Amore struct kstat_named hk_cvc; /* code violation errors */ 2450219346bSGarrett D'Amore struct kstat_named hk_lenerr; /* rx len errors */ 2460219346bSGarrett D'Amore struct kstat_named hk_buff; /* buff errors */ 2470219346bSGarrett D'Amore struct kstat_named hk_missed; /* missed/dropped packets */ 2480219346bSGarrett D'Amore struct kstat_named hk_nocanput; /* nocanput errors */ 2490219346bSGarrett D'Amore struct kstat_named hk_allocbfail; /* allocb failures */ 2500219346bSGarrett D'Amore struct kstat_named hk_babl; /* runt errors */ 2510219346bSGarrett D'Amore struct kstat_named hk_tmder; /* tmd errors */ 2520219346bSGarrett D'Amore struct kstat_named hk_txlaterr; /* tx late errors */ 2530219346bSGarrett D'Amore struct kstat_named hk_rxlaterr; /* rx late errors */ 2540219346bSGarrett D'Amore struct kstat_named hk_slvparerr; /* slave parity errors */ 2550219346bSGarrett D'Amore struct kstat_named hk_txparerr; /* tx parity errors */ 2560219346bSGarrett D'Amore struct kstat_named hk_rxparerr; /* rx parity errors */ 2570219346bSGarrett D'Amore struct kstat_named hk_slverrack; /* slave error acks */ 2580219346bSGarrett D'Amore struct kstat_named hk_txerrack; /* tx error acks */ 2590219346bSGarrett D'Amore struct kstat_named hk_rxerrack; /* rx error acks */ 2600219346bSGarrett D'Amore struct kstat_named hk_txtagerr; /* tx tag error */ 2610219346bSGarrett D'Amore struct kstat_named hk_rxtagerr; /* rx tag error */ 2620219346bSGarrett D'Amore struct kstat_named hk_eoperr; /* eop error */ 2630219346bSGarrett D'Amore struct kstat_named hk_notmds; /* tmd errors */ 2640219346bSGarrett D'Amore struct kstat_named hk_notbufs; /* tx buf errors */ 2650219346bSGarrett D'Amore struct kstat_named hk_norbufs; /* rx buf errors */ 2660219346bSGarrett D'Amore 2670219346bSGarrett D'Amore struct kstat_named hk_inits; /* global inits */ 2680219346bSGarrett D'Amore struct kstat_named hk_phyfail; /* phy failures */ 2690219346bSGarrett D'Amore 2700219346bSGarrett D'Amore struct kstat_named hk_asic_rev; /* asic_rev */ 2710219346bSGarrett D'Amore }; 2720219346bSGarrett D'Amore 2730219346bSGarrett D'Amore #define HMEDRAINTIME (400000) /* # microseconds xmit drain */ 2740219346bSGarrett D'Amore 2750219346bSGarrett D'Amore #define ROUNDUP(a, n) (((a) + ((n) - 1)) & ~((n) - 1)) 2760219346bSGarrett D'Amore #define ROUNDUP2(a, n) (uchar_t *)((((uintptr_t)(a)) + ((n) - 1)) & ~((n) - 1)) 2770219346bSGarrett D'Amore 2780219346bSGarrett D'Amore /* 2790219346bSGarrett D'Amore * Xmit/receive buffer structure. 2800219346bSGarrett D'Amore * This structure is organized to meet the following requirements: 2810219346bSGarrett D'Amore * - bb_buf starts on an HMEBURSTSIZE boundary. 2820219346bSGarrett D'Amore * - hmebuf is an even multiple of HMEBURSTSIZE 2830219346bSGarrett D'Amore * - bb_buf[] is large enough to contain max VLAN frame (1522) plus 2840219346bSGarrett D'Amore * (3 x HMEBURSTSIZE) rounded up to the next HMEBURSTSIZE 2850219346bSGarrett D'Amore * XXX What about another 128 bytes (HMEC requirement). 2860219346bSGarrett D'Amore * Fast aligned copy requires both the source and destination 2870219346bSGarrett D'Amore * addresses have the same offset from some N-byte boundary. 2880219346bSGarrett D'Amore */ 2890219346bSGarrett D'Amore #define HMEBURSTSIZE (64) 2900219346bSGarrett D'Amore #define HMEBURSTMASK (HMEBURSTSIZE - 1) 2910219346bSGarrett D'Amore #define HMEBUFSIZE (1728) 2920219346bSGarrett D'Amore 2930219346bSGarrett D'Amore /* 2940219346bSGarrett D'Amore * Define offset from start of bb_buf[] to point receive descriptor. 2950219346bSGarrett D'Amore * Requirements: 2960219346bSGarrett D'Amore * - must be 14 bytes back of a 4-byte boundary so the start of 2970219346bSGarrett D'Amore * the network packet is 4-byte aligned. 2980219346bSGarrett D'Amore * - leave some headroom for others 2990219346bSGarrett D'Amore */ 3000219346bSGarrett D'Amore #define HMEHEADROOM (34) 3010219346bSGarrett D'Amore 3020219346bSGarrett D'Amore /* Offset for the first byte in the receive buffer */ 3030219346bSGarrett D'Amore #define HME_FSTBYTE_OFFSET 2 3040219346bSGarrett D'Amore 3050219346bSGarrett D'Amore #endif /* _KERNEL */ 3060219346bSGarrett D'Amore 3070219346bSGarrett D'Amore #ifdef __cplusplus 3080219346bSGarrett D'Amore } 3090219346bSGarrett D'Amore #endif 3100219346bSGarrett D'Amore 3110219346bSGarrett D'Amore #endif /* _SYS_HME_H */ 312