1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright 2012 David Höppner. All rights reserved. 24 * Copyright (c) 2017, Joyent, Inc. 25 */ 26 27 #ifndef _E1000G_SW_H 28 #define _E1000G_SW_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* 35 * ********************************************************************** 36 * Module Name: * 37 * e1000g_sw.h * 38 * * 39 * Abstract: * 40 * This header file contains Software-related data structures * 41 * definitions. * 42 * * 43 * ********************************************************************** 44 */ 45 46 #include <sys/types.h> 47 #include <sys/conf.h> 48 #include <sys/debug.h> 49 #include <sys/stropts.h> 50 #include <sys/stream.h> 51 #include <sys/strsun.h> 52 #include <sys/strlog.h> 53 #include <sys/kmem.h> 54 #include <sys/stat.h> 55 #include <sys/kstat.h> 56 #include <sys/modctl.h> 57 #include <sys/errno.h> 58 #include <sys/mac_provider.h> 59 #include <sys/mac_ether.h> 60 #include <sys/vlan.h> 61 #include <sys/ddi.h> 62 #include <sys/sunddi.h> 63 #include <sys/disp.h> 64 #include <sys/pci.h> 65 #include <sys/sdt.h> 66 #include <sys/ethernet.h> 67 #include <sys/pattr.h> 68 #include <sys/strsubr.h> 69 #include <sys/netlb.h> 70 #include <inet/common.h> 71 #include <inet/ip.h> 72 #include <inet/tcp.h> 73 #include <inet/mi.h> 74 #include <inet/nd.h> 75 #include <sys/ddifm.h> 76 #include <sys/fm/protocol.h> 77 #include <sys/fm/util.h> 78 #include <sys/fm/io/ddi.h> 79 #include "e1000_api.h" 80 #include "e1000_illumos.h" 81 82 /* Driver states */ 83 #define E1000G_UNKNOWN 0x00 84 #define E1000G_INITIALIZED 0x01 85 #define E1000G_STARTED 0x02 86 #define E1000G_SUSPENDED 0x04 87 #define E1000G_ERROR 0x80 88 89 #define JUMBO_FRAG_LENGTH 4096 90 91 #define LAST_RAR_ENTRY (E1000_RAR_ENTRIES - 1) 92 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 93 #define MCAST_ALLOC_SIZE 256 94 95 /* 96 * MAX_COOKIES = max_LSO_packet_size(65535 + ethernet_header_len)/page_size 97 * + one for cross page split 98 * MAX_TX_DESC_PER_PACKET = MAX_COOKIES + one for the context descriptor + 99 * two for the workaround of the 82546 chip 100 */ 101 #define MAX_COOKIES 18 102 #define MAX_TX_DESC_PER_PACKET 21 103 104 /* 105 * constants used in setting flow control thresholds 106 */ 107 #define E1000_PBA_MASK 0xffff 108 #define E1000_PBA_SHIFT 10 109 #define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 110 #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 111 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 112 113 #define MAX_NUM_TX_DESCRIPTOR 4096 114 #define MAX_NUM_RX_DESCRIPTOR 4096 115 #define MAX_NUM_RX_FREELIST 4096 116 #define MAX_NUM_TX_FREELIST 4096 117 #define MAX_RX_LIMIT_ON_INTR 4096 118 #define MAX_RX_INTR_DELAY 65535 119 #define MAX_RX_INTR_ABS_DELAY 65535 120 #define MAX_TX_INTR_DELAY 65535 121 #define MAX_TX_INTR_ABS_DELAY 65535 122 #define MAX_INTR_THROTTLING 65535 123 #define MAX_RX_BCOPY_THRESHOLD E1000_RX_BUFFER_SIZE_2K 124 #define MAX_TX_BCOPY_THRESHOLD E1000_TX_BUFFER_SIZE_2K 125 #define MAX_MCAST_NUM 8192 126 127 #define MIN_NUM_TX_DESCRIPTOR 80 128 #define MIN_NUM_RX_DESCRIPTOR 80 129 #define MIN_NUM_RX_FREELIST 64 130 #define MIN_NUM_TX_FREELIST 80 131 #define MIN_RX_LIMIT_ON_INTR 16 132 #define MIN_RX_INTR_DELAY 0 133 #define MIN_RX_INTR_ABS_DELAY 0 134 #define MIN_TX_INTR_DELAY 0 135 #define MIN_TX_INTR_ABS_DELAY 0 136 #define MIN_INTR_THROTTLING 0 137 #define MIN_RX_BCOPY_THRESHOLD 0 138 #define MIN_TX_BCOPY_THRESHOLD ETHERMIN 139 #define MIN_MCAST_NUM 8 140 141 #define DEFAULT_NUM_RX_DESCRIPTOR 2048 142 #define DEFAULT_NUM_TX_DESCRIPTOR 2048 143 #define DEFAULT_NUM_RX_FREELIST 4096 144 #define DEFAULT_NUM_TX_FREELIST 2304 145 #define DEFAULT_JUMBO_NUM_RX_DESC 1024 146 #define DEFAULT_JUMBO_NUM_TX_DESC 1024 147 #define DEFAULT_JUMBO_NUM_RX_BUF 2048 148 #define DEFAULT_JUMBO_NUM_TX_BUF 1152 149 #define DEFAULT_RX_LIMIT_ON_INTR 128 150 #define RX_FREELIST_INCREASE_SIZE 512 151 152 #ifdef __sparc 153 #define MAX_INTR_PER_SEC 7100 154 #define MIN_INTR_PER_SEC 3000 155 #define DEFAULT_INTR_PACKET_LOW 5 156 #define DEFAULT_INTR_PACKET_HIGH 128 157 #else 158 #define MAX_INTR_PER_SEC 15000 159 #define MIN_INTR_PER_SEC 4000 160 #define DEFAULT_INTR_PACKET_LOW 10 161 #define DEFAULT_INTR_PACKET_HIGH 48 162 #endif 163 164 #define DEFAULT_RX_INTR_DELAY 0 165 #define DEFAULT_RX_INTR_ABS_DELAY 64 166 #define DEFAULT_TX_INTR_DELAY 64 167 #define DEFAULT_TX_INTR_ABS_DELAY 64 168 #define DEFAULT_INTR_THROTTLING_HIGH 1000000000/(MIN_INTR_PER_SEC*256) 169 #define DEFAULT_INTR_THROTTLING_LOW 1000000000/(MAX_INTR_PER_SEC*256) 170 #define DEFAULT_INTR_THROTTLING DEFAULT_INTR_THROTTLING_LOW 171 172 #define DEFAULT_RX_BCOPY_THRESHOLD 128 173 #define DEFAULT_TX_BCOPY_THRESHOLD 512 174 #define DEFAULT_TX_UPDATE_THRESHOLD 256 175 #define DEFAULT_TX_NO_RESOURCE MAX_TX_DESC_PER_PACKET 176 177 #define DEFAULT_TX_INTR_ENABLE 1 178 #define DEFAULT_FLOW_CONTROL 3 179 #define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */ 180 /* which is normally 0x040 */ 181 #define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */ 182 #define DEFAULT_MSI_ENABLE 1 /* MSI Enable */ 183 #define DEFAULT_TX_HCKSUM_ENABLE 1 /* Hardware checksum enable */ 184 #define DEFAULT_LSO_ENABLE 1 /* LSO enable */ 185 #define DEFAULT_MEM_WORKAROUND_82546 1 /* 82546 memory workaround */ 186 187 #define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */ 188 #define RX_DRAIN_TIME (200) /* # milliseconds recv drain */ 189 190 #define TX_STALL_TIME_2S (200) /* in unit of tick */ 191 #define TX_STALL_TIME_8S (800) /* in unit of tick */ 192 193 /* 194 * The size of the receive/transmite buffers 195 */ 196 #define E1000_RX_BUFFER_SIZE_2K (2048) 197 #define E1000_RX_BUFFER_SIZE_4K (4096) 198 #define E1000_RX_BUFFER_SIZE_8K (8192) 199 #define E1000_RX_BUFFER_SIZE_16K (16384) 200 201 #define E1000_TX_BUFFER_SIZE_2K (2048) 202 #define E1000_TX_BUFFER_SIZE_4K (4096) 203 #define E1000_TX_BUFFER_SIZE_8K (8192) 204 #define E1000_TX_BUFFER_SIZE_16K (16384) 205 206 #define E1000_TX_BUFFER_OEVRRUN_THRESHOLD (2015) 207 208 #define E1000G_RX_NORMAL 0x0 209 #define E1000G_RX_STOPPED 0x1 210 211 #define E1000G_CHAIN_NO_LIMIT 0 212 213 /* 214 * definitions for smartspeed workaround 215 */ 216 #define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */ 217 /* or 30 seconds */ 218 #define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */ 219 /* or 6 seconds */ 220 221 /* 222 * Definitions for module_info. 223 */ 224 #define WSNAME "e1000g" /* module name */ 225 226 /* 227 * Defined for IP header alignment. We also need to preserve space for 228 * VLAN tag (4 bytes) 229 */ 230 #define E1000G_IPALIGNROOM 2 231 232 /* 233 * bit flags for 'attach_progress' which is a member variable in struct e1000g 234 */ 235 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 236 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 237 #define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */ 238 #define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */ 239 #define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */ 240 #define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */ 241 #define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */ 242 #define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */ 243 #define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */ 244 /* 0200 used to be PROGRESS_NDD. Now unused */ 245 #define ATTACH_PROGRESS_MAC 0x0400 /* MAC registered */ 246 #define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */ 247 #define ATTACH_PROGRESS_FMINIT 0x1000 /* FMA initiated */ 248 249 /* 250 * Speed and Duplex Settings 251 */ 252 #define GDIAG_10_HALF 1 253 #define GDIAG_10_FULL 2 254 #define GDIAG_100_HALF 3 255 #define GDIAG_100_FULL 4 256 #define GDIAG_1000_FULL 6 257 #define GDIAG_ANY 7 258 259 /* 260 * Coexist Workaround RP: 07/04/03 261 * 82544 Workaround : Co-existence 262 */ 263 #define MAX_TX_BUF_SIZE (8 * 1024) 264 265 /* 266 * Defines for Jumbo Frame 267 */ 268 #define FRAME_SIZE_UPTO_2K 2048 269 #define FRAME_SIZE_UPTO_4K 4096 270 #define FRAME_SIZE_UPTO_8K 8192 271 #define FRAME_SIZE_UPTO_16K 16384 272 #define FRAME_SIZE_UPTO_9K 9234 273 274 #define DEFAULT_MTU ETHERMTU 275 #define MAXIMUM_MTU_4K 4096 276 #define MAXIMUM_MTU_9K 9216 277 278 #define DEFAULT_FRAME_SIZE \ 279 (DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 280 #define MAXIMUM_FRAME_SIZE \ 281 (MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 282 283 #define E1000_LSO_MAXLEN 65535 284 #define E1000_LSO_FIRST_DESC_ALIGNMENT_BOUNDARY_4K 4096 285 #define E1000_LSO_FIRST_DESC_ALIGNMENT 128 286 287 /* Defines for Tx stall check */ 288 #define E1000G_STALL_WATCHDOG_COUNT 8 289 290 #define MAX_TX_LINK_DOWN_TIMEOUT 8 291 292 /* Defines for DVMA */ 293 #ifdef __sparc 294 #define E1000G_DEFAULT_DVMA_PAGE_NUM 2 295 #endif 296 297 /* 298 * Loopback definitions 299 */ 300 #define E1000G_LB_NONE 0 301 #define E1000G_LB_EXTERNAL_1000 1 302 #define E1000G_LB_EXTERNAL_100 2 303 #define E1000G_LB_EXTERNAL_10 3 304 #define E1000G_LB_INTERNAL_PHY 4 305 306 /* 307 * Private dip list definitions 308 */ 309 #define E1000G_PRIV_DEVI_ATTACH 0x0 310 #define E1000G_PRIV_DEVI_DETACH 0x1 311 312 /* 313 * Tx descriptor LENGTH field mask 314 */ 315 #define E1000G_TBD_LENGTH_MASK 0x000fffff 316 317 #define E1000G_IS_VLAN_PACKET(ptr) \ 318 ((((struct ether_vlan_header *)(uintptr_t)ptr)->ether_tpid) == \ 319 htons(ETHERTYPE_VLAN)) 320 321 /* 322 * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. 323 */ 324 #define QUEUE_INIT_LIST(_LH) \ 325 (_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0 326 327 /* 328 * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty. 329 */ 330 #define IS_QUEUE_EMPTY(_LH) \ 331 ((_LH)->Flink == (PSINGLE_LIST_LINK)0) 332 333 /* 334 * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does 335 * not remove the head from the queue. 336 */ 337 #define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink)) 338 339 /* 340 * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue. 341 */ 342 #define QUEUE_REMOVE_HEAD(_LH) \ 343 { \ 344 PSINGLE_LIST_LINK ListElem; \ 345 if (ListElem = (_LH)->Flink) \ 346 { \ 347 if (!((_LH)->Flink = ListElem->Flink)) \ 348 (_LH)->Blink = (PSINGLE_LIST_LINK) 0; \ 349 } \ 350 } 351 352 /* 353 * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list), 354 * and return it (this differs from QUEUE_REMOVE_HEAD only in 355 * the 1st line). 356 */ 357 #define QUEUE_POP_HEAD(_LH) \ 358 (PSINGLE_LIST_LINK)(_LH)->Flink; \ 359 { \ 360 PSINGLE_LIST_LINK ListElem; \ 361 ListElem = (_LH)->Flink; \ 362 if (ListElem) \ 363 { \ 364 (_LH)->Flink = ListElem->Flink; \ 365 if (!(_LH)->Flink) \ 366 (_LH)->Blink = (PSINGLE_LIST_LINK)0; \ 367 } \ 368 } 369 370 /* 371 * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not 372 * remove the tail from the queue. 373 */ 374 #define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink)) 375 376 /* 377 * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue 378 */ 379 #define QUEUE_PUSH_TAIL(_LH, _E) \ 380 if ((_LH)->Blink) \ 381 { \ 382 ((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \ 383 (PSINGLE_LIST_LINK)(_E); \ 384 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 385 } else { \ 386 (_LH)->Flink = \ 387 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 388 } \ 389 (_E)->Flink = (PSINGLE_LIST_LINK)0; 390 391 /* 392 * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue. 393 */ 394 #define QUEUE_PUSH_HEAD(_LH, _E) \ 395 if (!((_E)->Flink = (_LH)->Flink)) \ 396 { \ 397 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 398 } \ 399 (_LH)->Flink = (PSINGLE_LIST_LINK)(_E); 400 401 /* 402 * QUEUE_GET_NEXT -- Macro which returns the next element linked to the 403 * current element. 404 */ 405 #define QUEUE_GET_NEXT(_LH, _E) \ 406 (PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \ 407 (0) : ((_E)->Flink)) 408 409 /* 410 * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue 411 */ 412 #define QUEUE_APPEND(_LH1, _LH2) \ 413 if ((_LH2)->Flink) { \ 414 if ((_LH1)->Flink) { \ 415 ((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \ 416 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 417 } else { \ 418 (_LH1)->Flink = \ 419 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 420 } \ 421 (_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \ 422 } 423 424 425 #define QUEUE_SWITCH(_LH1, _LH2) \ 426 if ((_LH2)->Flink) { \ 427 (_LH1)->Flink = (_LH2)->Flink; \ 428 (_LH1)->Blink = (_LH2)->Blink; \ 429 (_LH2)->Flink = (_LH2)->Blink = (PSINGLE_LIST_LINK)0; \ 430 } 431 432 /* 433 * Property lookups 434 */ 435 #define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 436 DDI_PROP_DONTPASS, (n)) 437 #define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 438 DDI_PROP_DONTPASS, (n), -1) 439 440 #ifdef E1000G_DEBUG 441 /* 442 * E1000G-specific ioctls ... 443 */ 444 #define E1000G_IOC ((((((('E' << 4) + '1') << 4) \ 445 + 'K') << 4) + 'G') << 4) 446 447 /* 448 * These diagnostic IOCTLS are enabled only in DEBUG drivers 449 */ 450 #define E1000G_IOC_REG_PEEK (E1000G_IOC | 1) 451 #define E1000G_IOC_REG_POKE (E1000G_IOC | 2) 452 #define E1000G_IOC_CHIP_RESET (E1000G_IOC | 3) 453 454 #define E1000G_PP_SPACE_REG 0 /* PCI memory space */ 455 #define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */ 456 457 typedef struct { 458 uint64_t pp_acc_size; /* It's 1, 2, 4 or 8 */ 459 uint64_t pp_acc_space; /* See #defines below */ 460 uint64_t pp_acc_offset; /* See regs definition */ 461 uint64_t pp_acc_data; /* output for peek */ 462 /* input for poke */ 463 } e1000g_peekpoke_t; 464 #endif /* E1000G_DEBUG */ 465 466 /* 467 * (Internal) return values from ioctl subroutines 468 */ 469 enum ioc_reply { 470 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 471 IOC_DONE, /* OK, reply sent */ 472 IOC_ACK, /* OK, just send ACK */ 473 IOC_REPLY /* OK, just send reply */ 474 }; 475 476 /* 477 * Named Data (ND) Parameter Management Structure 478 */ 479 typedef struct { 480 uint32_t ndp_info; 481 uint32_t ndp_min; 482 uint32_t ndp_max; 483 uint32_t ndp_val; 484 struct e1000g *ndp_instance; 485 char *ndp_name; 486 } nd_param_t; 487 488 /* 489 * The entry of the private dip list 490 */ 491 typedef struct _private_devi_list { 492 dev_info_t *priv_dip; 493 uint32_t flag; 494 uint32_t pending_rx_count; 495 struct _private_devi_list *prev; 496 struct _private_devi_list *next; 497 } private_devi_list_t; 498 499 /* 500 * A structure that points to the next entry in the queue. 501 */ 502 typedef struct _SINGLE_LIST_LINK { 503 struct _SINGLE_LIST_LINK *Flink; 504 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK; 505 506 /* 507 * A "ListHead" structure that points to the head and tail of a queue 508 */ 509 typedef struct _LIST_DESCRIBER { 510 struct _SINGLE_LIST_LINK *volatile Flink; 511 struct _SINGLE_LIST_LINK *volatile Blink; 512 } LIST_DESCRIBER, *PLIST_DESCRIBER; 513 514 enum e1000g_bar_type { 515 E1000G_BAR_CONFIG = 0, 516 E1000G_BAR_IO, 517 E1000G_BAR_MEM32, 518 E1000G_BAR_MEM64 519 }; 520 521 typedef struct { 522 enum e1000g_bar_type type; 523 int rnumber; 524 } bar_info_t; 525 526 /* 527 * Address-Length pair structure that stores descriptor info 528 */ 529 typedef struct _sw_desc { 530 uint64_t address; 531 uint32_t length; 532 } sw_desc_t, *p_sw_desc_t; 533 534 typedef struct _desc_array { 535 sw_desc_t descriptor[4]; 536 uint32_t elements; 537 } desc_array_t, *p_desc_array_t; 538 539 typedef enum { 540 USE_NONE, 541 USE_BCOPY, 542 USE_DVMA, 543 USE_DMA 544 } dma_type_t; 545 546 typedef struct _dma_buffer { 547 caddr_t address; 548 uint64_t dma_address; 549 ddi_acc_handle_t acc_handle; 550 ddi_dma_handle_t dma_handle; 551 size_t size; 552 size_t len; 553 } dma_buffer_t, *p_dma_buffer_t; 554 555 /* 556 * Transmit Control Block (TCB), Ndis equiv of SWPacket This 557 * structure stores the additional information that is 558 * associated with every packet to be transmitted. It stores the 559 * message block pointer and the TBD addresses associated with 560 * the m_blk and also the link to the next tcb in the chain 561 */ 562 typedef struct _tx_sw_packet { 563 /* Link to the next tx_sw_packet in the list */ 564 SINGLE_LIST_LINK Link; 565 mblk_t *mp; 566 uint32_t num_desc; 567 uint32_t num_mblk_frag; 568 dma_type_t dma_type; 569 dma_type_t data_transfer_type; 570 ddi_dma_handle_t tx_dma_handle; 571 dma_buffer_t tx_buf[1]; 572 sw_desc_t desc[MAX_TX_DESC_PER_PACKET]; 573 int64_t tickstamp; 574 } tx_sw_packet_t, *p_tx_sw_packet_t; 575 576 /* 577 * This structure is similar to the rx_sw_packet structure used 578 * for Ndis. This structure stores information about the 2k 579 * aligned receive buffer into which the FX1000 DMA's frames. 580 * This structure is maintained as a linked list of many 581 * receiver buffer pointers. 582 */ 583 typedef struct _rx_sw_packet { 584 /* Link to the next rx_sw_packet_t in the list */ 585 SINGLE_LIST_LINK Link; 586 struct _rx_sw_packet *next; 587 uint32_t ref_cnt; 588 mblk_t *mp; 589 caddr_t rx_data; 590 dma_type_t dma_type; 591 frtn_t free_rtn; 592 dma_buffer_t rx_buf[1]; 593 } rx_sw_packet_t, *p_rx_sw_packet_t; 594 595 typedef struct _mblk_list { 596 mblk_t *head; 597 mblk_t *tail; 598 } mblk_list_t, *p_mblk_list_t; 599 600 typedef struct _context_data { 601 uint32_t ether_header_size; 602 uint32_t cksum_flags; 603 uint32_t cksum_start; 604 uint32_t cksum_stuff; 605 uint16_t mss; 606 uint8_t hdr_len; 607 uint32_t pay_len; 608 boolean_t lso_flag; 609 } context_data_t; 610 611 typedef union _e1000g_ether_addr { 612 struct { 613 uint32_t high; 614 uint32_t low; 615 } reg; 616 struct { 617 uint8_t set; 618 uint8_t redundant; 619 uint8_t addr[ETHERADDRL]; 620 } mac; 621 } e1000g_ether_addr_t; 622 623 typedef struct _e1000g_stat { 624 kstat_named_t reset_count; /* Reset Count */ 625 626 kstat_named_t rx_error; /* Rx Error in Packet */ 627 kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ 628 kstat_named_t rx_size_error; /* Rx Size Error */ 629 630 kstat_named_t tx_no_desc; /* Tx No Desc */ 631 kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ 632 kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ 633 kstat_named_t tx_over_size; /* Tx Pkt Too Long */ 634 kstat_named_t tx_reschedule; /* Tx Reschedule */ 635 636 #ifdef E1000G_DEBUG 637 kstat_named_t rx_none; /* Rx No Incoming Data */ 638 kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */ 639 kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */ 640 kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */ 641 642 kstat_named_t tx_under_size; /* Tx Packet Under Size */ 643 kstat_named_t tx_empty_frags; /* Tx Empty Frags */ 644 kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */ 645 kstat_named_t tx_recycle; /* Tx Recycle */ 646 kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ 647 kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */ 648 kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */ 649 kstat_named_t tx_copy; /* Tx Send Copy */ 650 kstat_named_t tx_bind; /* Tx Send Bind */ 651 kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */ 652 kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ 653 kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ 654 #endif 655 656 kstat_named_t Symerrs; /* Symbol Error Count */ 657 kstat_named_t Mpc; /* Missed Packet Count */ 658 kstat_named_t Rlec; /* Receive Length Error Count */ 659 kstat_named_t Xonrxc; /* XON Received Count */ 660 kstat_named_t Xontxc; /* XON Xmitted Count */ 661 kstat_named_t Xoffrxc; /* XOFF Received Count */ 662 kstat_named_t Xofftxc; /* Xoff Xmitted Count */ 663 kstat_named_t Fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 664 #ifdef E1000G_DEBUG 665 kstat_named_t Prc64; /* Packets Received - 64b */ 666 kstat_named_t Prc127; /* Packets Received - 65-127b */ 667 kstat_named_t Prc255; /* Packets Received - 127-255b */ 668 kstat_named_t Prc511; /* Packets Received - 256-511b */ 669 kstat_named_t Prc1023; /* Packets Received - 511-1023b */ 670 kstat_named_t Prc1522; /* Packets Received - 1024-1522b */ 671 #endif 672 kstat_named_t Gprc; /* Good Packets Received Count */ 673 kstat_named_t Gptc; /* Good Packets Xmitted Count */ 674 kstat_named_t Gorl; /* Good Octets Recvd Lo Count */ 675 kstat_named_t Gorh; /* Good Octets Recvd Hi Count */ 676 kstat_named_t Gotl; /* Good Octets Xmitd Lo Count */ 677 kstat_named_t Goth; /* Good Octets Xmitd Hi Count */ 678 kstat_named_t Rfc; /* Receive Frag Count */ 679 #ifdef E1000G_DEBUG 680 kstat_named_t Ptc64; /* Packets Xmitted (64b) */ 681 kstat_named_t Ptc127; /* Packets Xmitted (64-127b) */ 682 kstat_named_t Ptc255; /* Packets Xmitted (128-255b) */ 683 kstat_named_t Ptc511; /* Packets Xmitted (255-511b) */ 684 kstat_named_t Ptc1023; /* Packets Xmitted (512-1023b) */ 685 kstat_named_t Ptc1522; /* Packets Xmitted (1024-1522b */ 686 #endif 687 kstat_named_t Tncrs; /* Transmit with no CRS */ 688 kstat_named_t Tsctc; /* TCP seg contexts xmit count */ 689 kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */ 690 } e1000g_stat_t, *p_e1000g_stat_t; 691 692 typedef struct _e1000g_tx_ring { 693 kmutex_t tx_lock; 694 kmutex_t freelist_lock; 695 kmutex_t usedlist_lock; 696 /* 697 * Descriptor queue definitions 698 */ 699 ddi_dma_handle_t tbd_dma_handle; 700 ddi_acc_handle_t tbd_acc_handle; 701 struct e1000_tx_desc *tbd_area; 702 uint64_t tbd_dma_addr; 703 struct e1000_tx_desc *tbd_first; 704 struct e1000_tx_desc *tbd_last; 705 struct e1000_tx_desc *tbd_oldest; 706 struct e1000_tx_desc *tbd_next; 707 uint32_t tbd_avail; 708 /* 709 * Software packet structures definitions 710 */ 711 p_tx_sw_packet_t packet_area; 712 LIST_DESCRIBER used_list; 713 LIST_DESCRIBER free_list; 714 /* 715 * TCP/UDP Context Data Information 716 */ 717 context_data_t pre_context; 718 /* 719 * Timer definitions for 82547 720 */ 721 timeout_id_t timer_id_82547; 722 boolean_t timer_enable_82547; 723 /* 724 * reschedule when tx resource is available 725 */ 726 boolean_t resched_needed; 727 clock_t resched_timestamp; 728 mblk_list_t mblks; 729 /* 730 * Statistics 731 */ 732 uint32_t stat_no_swpkt; 733 uint32_t stat_no_desc; 734 uint32_t stat_send_fail; 735 uint32_t stat_reschedule; 736 uint32_t stat_timer_reschedule; 737 uint32_t stat_over_size; 738 #ifdef E1000G_DEBUG 739 uint32_t stat_under_size; 740 uint32_t stat_exceed_frags; 741 uint32_t stat_empty_frags; 742 uint32_t stat_recycle; 743 uint32_t stat_recycle_intr; 744 uint32_t stat_recycle_retry; 745 uint32_t stat_recycle_none; 746 uint32_t stat_copy; 747 uint32_t stat_bind; 748 uint32_t stat_multi_copy; 749 uint32_t stat_multi_cookie; 750 uint32_t stat_lack_desc; 751 uint32_t stat_lso_header_fail; 752 #endif 753 /* 754 * Pointer to the adapter 755 */ 756 struct e1000g *adapter; 757 } e1000g_tx_ring_t, *pe1000g_tx_ring_t; 758 759 typedef struct _e1000g_rx_data { 760 kmutex_t freelist_lock; 761 kmutex_t recycle_lock; 762 /* 763 * Descriptor queue definitions 764 */ 765 ddi_dma_handle_t rbd_dma_handle; 766 ddi_acc_handle_t rbd_acc_handle; 767 struct e1000_rx_desc *rbd_area; 768 uint64_t rbd_dma_addr; 769 struct e1000_rx_desc *rbd_first; 770 struct e1000_rx_desc *rbd_last; 771 struct e1000_rx_desc *rbd_next; 772 /* 773 * Software packet structures definitions 774 */ 775 p_rx_sw_packet_t packet_area; 776 LIST_DESCRIBER recv_list; 777 LIST_DESCRIBER free_list; 778 LIST_DESCRIBER recycle_list; 779 uint32_t flag; 780 781 uint32_t pending_count; 782 uint32_t avail_freepkt; 783 uint32_t recycle_freepkt; 784 uint32_t rx_mblk_len; 785 mblk_t *rx_mblk; 786 mblk_t *rx_mblk_tail; 787 788 private_devi_list_t *priv_devi_node; 789 struct _e1000g_rx_ring *rx_ring; 790 } e1000g_rx_data_t; 791 792 typedef struct _e1000g_rx_ring { 793 e1000g_rx_data_t *rx_data; 794 795 kmutex_t rx_lock; 796 797 mac_ring_handle_t mrh; 798 mac_ring_handle_t mrh_init; 799 uint64_t ring_gen_num; 800 boolean_t poll_flag; 801 802 /* 803 * Statistics 804 */ 805 uint32_t stat_error; 806 uint32_t stat_allocb_fail; 807 uint32_t stat_exceed_pkt; 808 uint32_t stat_size_error; 809 uint32_t stat_crc_only_pkt; 810 #ifdef E1000G_DEBUG 811 uint32_t stat_none; 812 uint32_t stat_multi_desc; 813 uint32_t stat_no_freepkt; 814 #endif 815 /* 816 * Pointer to the adapter 817 */ 818 struct e1000g *adapter; 819 } e1000g_rx_ring_t, *pe1000g_rx_ring_t; 820 821 typedef struct e1000g { 822 int instance; 823 dev_info_t *dip; 824 dev_info_t *priv_dip; 825 private_devi_list_t *priv_devi_node; 826 mac_handle_t mh; 827 mac_resource_handle_t mrh; 828 struct e1000_hw shared; 829 struct e1000g_osdep osdep; 830 831 uint32_t e1000g_state; 832 boolean_t e1000g_promisc; 833 boolean_t strip_crc; 834 boolean_t rx_buffer_setup; 835 boolean_t esb2_workaround; 836 link_state_t link_state; 837 uint64_t link_speed; 838 uint32_t link_duplex; 839 uint32_t master_latency_timer; 840 uint32_t smartspeed; /* smartspeed w/a counter */ 841 uint32_t init_count; 842 uint32_t reset_count; 843 boolean_t reset_flag; 844 uint32_t stall_threshold; 845 boolean_t stall_flag; 846 uint32_t attach_progress; /* attach tracking */ 847 uint32_t loopback_mode; 848 uint32_t pending_rx_count; 849 850 uint32_t align_errors; 851 uint32_t brdcstrcv; 852 uint32_t brdcstxmt; 853 uint32_t carrier_errors; 854 uint32_t collisions; 855 uint32_t defer_xmts; 856 uint32_t ex_collisions; 857 uint32_t fcs_errors; 858 uint32_t first_collisions; 859 uint32_t ipackets; 860 uint32_t jabber_errors; 861 uint32_t macrcv_errors; 862 uint32_t macxmt_errors; 863 uint32_t multi_collisions; 864 uint32_t multircv; 865 uint32_t multixmt; 866 uint32_t norcvbuf; 867 uint32_t oerrors; 868 uint32_t opackets; 869 uint32_t sqe_errors; 870 uint32_t toolong_errors; 871 uint32_t tooshort_errors; 872 uint32_t tx_late_collisions; 873 uint64_t obytes; 874 uint64_t rbytes; 875 876 uint32_t tx_desc_num; 877 uint32_t tx_freelist_num; 878 uint32_t rx_desc_num; 879 uint32_t rx_freelist_num; 880 uint32_t rx_freelist_limit; 881 uint32_t tx_buffer_size; 882 uint32_t rx_buffer_size; 883 884 uint32_t tx_link_down_timeout; 885 uint32_t tx_bcopy_thresh; 886 uint32_t rx_limit_onintr; 887 uint32_t rx_bcopy_thresh; 888 uint32_t rx_buf_align; 889 uint32_t desc_align; 890 891 boolean_t intr_adaptive; 892 boolean_t tx_intr_enable; 893 uint32_t tx_intr_delay; 894 uint32_t tx_intr_abs_delay; 895 uint32_t rx_intr_delay; 896 uint32_t rx_intr_abs_delay; 897 uint32_t intr_throttling_rate; 898 899 uint32_t tx_desc_num_flag:1, 900 rx_desc_num_flag:1, 901 tx_buf_num_flag:1, 902 rx_buf_num_flag:1, 903 pad_to_32:28; 904 905 uint32_t default_mtu; 906 uint32_t max_mtu; 907 uint32_t max_frame_size; 908 uint32_t min_frame_size; 909 910 boolean_t watchdog_timer_enabled; 911 boolean_t watchdog_timer_started; 912 timeout_id_t watchdog_tid; 913 boolean_t link_complete; 914 timeout_id_t link_tid; 915 916 e1000g_rx_ring_t rx_ring[1]; 917 e1000g_tx_ring_t tx_ring[1]; 918 mac_group_handle_t rx_group; 919 920 /* 921 * Rx and Tx packet count for interrupt adaptive setting 922 */ 923 uint32_t rx_pkt_cnt; 924 uint32_t tx_pkt_cnt; 925 926 /* 927 * The watchdog_lock must be held when updateing the 928 * timeout fields in struct e1000g, that is, 929 * watchdog_tid, watchdog_timer_started. 930 */ 931 kmutex_t watchdog_lock; 932 /* 933 * The link_lock protects the link_complete and link_tid 934 * fields in struct e1000g. 935 */ 936 kmutex_t link_lock; 937 /* 938 * The chip_lock assures that the Rx/Tx process must be 939 * stopped while other functions change the hardware 940 * configuration of e1000g card, such as e1000g_reset(), 941 * e1000g_reset_hw() etc are executed. 942 */ 943 krwlock_t chip_lock; 944 945 boolean_t unicst_init; 946 uint32_t unicst_avail; 947 uint32_t unicst_total; 948 e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 949 950 uint32_t mcast_count; 951 uint32_t mcast_max_num; 952 uint32_t mcast_alloc_count; 953 struct ether_addr *mcast_table; 954 955 ulong_t sys_page_sz; 956 #ifdef __sparc 957 uint_t dvma_page_num; 958 #endif 959 960 boolean_t msi_enable; 961 boolean_t tx_hcksum_enable; 962 boolean_t lso_enable; 963 boolean_t lso_premature_issue; 964 boolean_t mem_workaround_82546; 965 int intr_type; 966 int intr_cnt; 967 int intr_cap; 968 size_t intr_size; 969 uint_t intr_pri; 970 ddi_intr_handle_t *htable; 971 972 int tx_softint_pri; 973 ddi_softint_handle_t tx_softint_handle; 974 975 kstat_t *e1000g_ksp; 976 977 boolean_t poll_mode; 978 979 uint16_t phy_ctrl; /* contents of PHY_CTRL */ 980 uint16_t phy_status; /* contents of PHY_STATUS */ 981 uint16_t phy_an_adv; /* contents of PHY_AUTONEG_ADV */ 982 uint16_t phy_an_exp; /* contents of PHY_AUTONEG_EXP */ 983 uint16_t phy_ext_status; /* contents of PHY_EXT_STATUS */ 984 uint16_t phy_1000t_ctrl; /* contents of PHY_1000T_CTRL */ 985 uint16_t phy_1000t_status; /* contents of PHY_1000T_STATUS */ 986 uint16_t phy_lp_able; /* contents of PHY_LP_ABILITY */ 987 988 /* 989 * LED Controls 990 */ 991 kmutex_t e1000g_led_lock; 992 boolean_t e1000g_led_setup; 993 boolean_t e1000g_emul_blink; 994 boolean_t e1000g_emul_state; 995 ddi_periodic_t e1000g_blink; 996 997 /* 998 * FMA capabilities 999 */ 1000 int fm_capabilities; 1001 1002 uint32_t param_en_1000fdx:1, 1003 param_en_1000hdx:1, 1004 param_en_100fdx:1, 1005 param_en_100hdx:1, 1006 param_en_10fdx:1, 1007 param_en_10hdx:1, 1008 param_autoneg_cap:1, 1009 param_pause_cap:1, 1010 param_asym_pause_cap:1, 1011 param_1000fdx_cap:1, 1012 param_1000hdx_cap:1, 1013 param_100t4_cap:1, 1014 param_100fdx_cap:1, 1015 param_100hdx_cap:1, 1016 param_10fdx_cap:1, 1017 param_10hdx_cap:1, 1018 param_adv_autoneg:1, 1019 param_adv_pause:1, 1020 param_adv_asym_pause:1, 1021 param_adv_1000fdx:1, 1022 param_adv_1000hdx:1, 1023 param_adv_100t4:1, 1024 param_adv_100fdx:1, 1025 param_adv_100hdx:1, 1026 param_adv_10fdx:1, 1027 param_adv_10hdx:1, 1028 param_lp_autoneg:1, 1029 param_lp_pause:1, 1030 param_lp_asym_pause:1, 1031 param_lp_1000fdx:1, 1032 param_lp_1000hdx:1, 1033 param_lp_100t4:1; 1034 1035 uint32_t param_lp_100fdx:1, 1036 param_lp_100hdx:1, 1037 param_lp_10fdx:1, 1038 param_lp_10hdx:1, 1039 param_pad_to_32:28; 1040 1041 } e1000g_t; 1042 1043 1044 /* 1045 * Function prototypes 1046 */ 1047 void e1000g_free_priv_devi_node(private_devi_list_t *devi_node); 1048 void e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data); 1049 void e1000g_free_rx_data(e1000g_rx_data_t *rx_data); 1050 int e1000g_alloc_dma_resources(struct e1000g *Adapter); 1051 void e1000g_release_dma_resources(struct e1000g *Adapter); 1052 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet, boolean_t full_release); 1053 void e1000g_tx_setup(struct e1000g *Adapter); 1054 void e1000g_rx_setup(struct e1000g *Adapter); 1055 int e1000g_increase_rx_packets(e1000g_rx_data_t *rx_data); 1056 1057 int e1000g_recycle(e1000g_tx_ring_t *tx_ring); 1058 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet); 1059 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring); 1060 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2); 1061 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp); 1062 mblk_t *e1000g_receive(e1000g_rx_ring_t *rx_ring, mblk_t **tail, uint_t sz); 1063 void e1000g_rxfree_func(p_rx_sw_packet_t packet); 1064 1065 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val); 1066 int e1000g_init_stats(struct e1000g *Adapter); 1067 int e1000g_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 1068 void e1000_tbi_adjust_stats(struct e1000g *Adapter, 1069 uint32_t frame_len, uint8_t *mac_addr); 1070 1071 void e1000g_clear_interrupt(struct e1000g *Adapter); 1072 void e1000g_mask_interrupt(struct e1000g *Adapter); 1073 void e1000g_clear_all_interrupts(struct e1000g *Adapter); 1074 void e1000g_clear_tx_interrupt(struct e1000g *Adapter); 1075 void e1000g_mask_tx_interrupt(struct e1000g *Adapter); 1076 void phy_spd_state(struct e1000_hw *hw, boolean_t enable); 1077 void e1000_destroy_hw_mutex(struct e1000_hw *hw); 1078 void e1000_enable_pciex_master(struct e1000_hw *hw); 1079 int e1000g_check_acc_handle(ddi_acc_handle_t handle); 1080 int e1000g_check_dma_handle(ddi_dma_handle_t handle); 1081 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail); 1082 void e1000g_set_fma_flags(int dma_flag); 1083 int e1000g_reset_link(struct e1000g *Adapter); 1084 1085 /* 1086 * Functions for working around various problems, these used to be from the 1087 * common code. 1088 */ 1089 s32 e1000_fifo_workaround_82547(struct e1000_hw *hw, u16 length); 1090 void e1000_update_tx_fifo_head_82547(struct e1000_hw *hw, u32 length); 1091 void e1000_set_ttl_workaround_state_82541(struct e1000_hw *hw, bool state); 1092 bool e1000_ttl_workaround_enabled_82541(struct e1000_hw *hw); 1093 s32 e1000_igp_ttl_workaround_82547(struct e1000_hw *hw); 1094 1095 /* 1096 * I219 specific workarounds 1097 */ 1098 #define PCICFG_DESC_RING_STATUS 0xe4 1099 #define FLUSH_DESC_REQUIRED 0x100 1100 extern void e1000g_flush_rx_ring(struct e1000g *); 1101 extern void e1000g_flush_tx_ring(struct e1000g *); 1102 1103 /* 1104 * Global variables 1105 */ 1106 extern boolean_t e1000g_force_detach; 1107 extern uint32_t e1000g_mblks_pending; 1108 extern kmutex_t e1000g_rx_detach_lock; 1109 extern private_devi_list_t *e1000g_private_devi_list; 1110 extern int e1000g_poll_mode; 1111 1112 #ifdef __cplusplus 1113 } 1114 #endif 1115 1116 #endif /* _E1000G_SW_H */ 1117