1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 25 /* 26 * Copyright 2012 DEY Storage Systems, Inc. All rights reserved. 27 * Copyright 2013 Nexenta Systems, Inc. All rights reserved. 28 * Copyright (c) 2018, Joyent, Inc. 29 */ 30 31 /* 32 * ********************************************************************** 33 * * 34 * Module Name: * 35 * e1000g_main.c * 36 * * 37 * Abstract: * 38 * This file contains the interface routines for the solaris OS. * 39 * It has all DDI entry point routines and GLD entry point routines. * 40 * * 41 * This file also contains routines that take care of initialization * 42 * uninit routine and interrupt routine. * 43 * * 44 * ********************************************************************** 45 */ 46 47 #include <sys/dlpi.h> 48 #include <sys/mac.h> 49 #include "e1000g_sw.h" 50 #include "e1000g_debug.h" 51 52 static char ident[] = "Intel PRO/1000 Ethernet"; 53 /* LINTED E_STATIC_UNUSED */ 54 static char e1000g_version[] = "Driver Ver. 5.3.24"; 55 56 /* 57 * Proto types for DDI entry points 58 */ 59 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 60 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 61 static int e1000g_quiesce(dev_info_t *); 62 63 /* 64 * init and intr routines prototype 65 */ 66 static int e1000g_resume(dev_info_t *); 67 static int e1000g_suspend(dev_info_t *); 68 static uint_t e1000g_intr_pciexpress(caddr_t, caddr_t); 69 static uint_t e1000g_intr(caddr_t, caddr_t); 70 static void e1000g_intr_work(struct e1000g *, uint32_t); 71 #pragma inline(e1000g_intr_work) 72 static int e1000g_init(struct e1000g *); 73 static int e1000g_start(struct e1000g *, boolean_t); 74 static void e1000g_stop(struct e1000g *, boolean_t); 75 static int e1000g_m_start(void *); 76 static void e1000g_m_stop(void *); 77 static int e1000g_m_promisc(void *, boolean_t); 78 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 79 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 80 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 81 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 82 uint_t, const void *); 83 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 84 uint_t, void *); 85 static void e1000g_m_propinfo(void *, const char *, mac_prop_id_t, 86 mac_prop_info_handle_t); 87 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 88 const void *); 89 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, void *); 90 static void e1000g_init_locks(struct e1000g *); 91 static void e1000g_destroy_locks(struct e1000g *); 92 static int e1000g_identify_hardware(struct e1000g *); 93 static int e1000g_regs_map(struct e1000g *); 94 static int e1000g_set_driver_params(struct e1000g *); 95 static void e1000g_set_bufsize(struct e1000g *); 96 static int e1000g_register_mac(struct e1000g *); 97 static boolean_t e1000g_rx_drain(struct e1000g *); 98 static boolean_t e1000g_tx_drain(struct e1000g *); 99 static void e1000g_init_unicst(struct e1000g *); 100 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int); 101 static int e1000g_alloc_rx_data(struct e1000g *); 102 static void e1000g_release_multicast(struct e1000g *); 103 static void e1000g_pch_limits(struct e1000g *); 104 static uint32_t e1000g_mtu2maxframe(uint32_t); 105 106 /* 107 * Local routines 108 */ 109 static boolean_t e1000g_reset_adapter(struct e1000g *); 110 static void e1000g_tx_clean(struct e1000g *); 111 static void e1000g_rx_clean(struct e1000g *); 112 static void e1000g_link_timer(void *); 113 static void e1000g_local_timer(void *); 114 static boolean_t e1000g_link_check(struct e1000g *); 115 static boolean_t e1000g_stall_check(struct e1000g *); 116 static void e1000g_smartspeed(struct e1000g *); 117 static void e1000g_get_conf(struct e1000g *); 118 static boolean_t e1000g_get_prop(struct e1000g *, char *, int, int, int, 119 int *); 120 static void enable_watchdog_timer(struct e1000g *); 121 static void disable_watchdog_timer(struct e1000g *); 122 static void start_watchdog_timer(struct e1000g *); 123 static void restart_watchdog_timer(struct e1000g *); 124 static void stop_watchdog_timer(struct e1000g *); 125 static void stop_link_timer(struct e1000g *); 126 static void stop_82547_timer(e1000g_tx_ring_t *); 127 static void e1000g_force_speed_duplex(struct e1000g *); 128 static void e1000g_setup_max_mtu(struct e1000g *); 129 static void e1000g_get_max_frame_size(struct e1000g *); 130 static boolean_t is_valid_mac_addr(uint8_t *); 131 static void e1000g_unattach(dev_info_t *, struct e1000g *); 132 static int e1000g_get_bar_info(dev_info_t *, int, bar_info_t *); 133 #ifdef E1000G_DEBUG 134 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 135 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 136 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 137 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 138 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 139 struct iocblk *, mblk_t *); 140 #endif 141 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 142 struct iocblk *, mblk_t *); 143 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 144 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 145 static void e1000g_set_internal_loopback(struct e1000g *); 146 static void e1000g_set_external_loopback_1000(struct e1000g *); 147 static void e1000g_set_external_loopback_100(struct e1000g *); 148 static void e1000g_set_external_loopback_10(struct e1000g *); 149 static int e1000g_add_intrs(struct e1000g *); 150 static int e1000g_intr_add(struct e1000g *, int); 151 static int e1000g_rem_intrs(struct e1000g *); 152 static int e1000g_enable_intrs(struct e1000g *); 153 static int e1000g_disable_intrs(struct e1000g *); 154 static boolean_t e1000g_link_up(struct e1000g *); 155 #ifdef __sparc 156 static boolean_t e1000g_find_mac_address(struct e1000g *); 157 #endif 158 static void e1000g_get_phy_state(struct e1000g *); 159 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 160 const void *impl_data); 161 static void e1000g_fm_init(struct e1000g *Adapter); 162 static void e1000g_fm_fini(struct e1000g *Adapter); 163 static void e1000g_param_sync(struct e1000g *); 164 static void e1000g_get_driver_control(struct e1000_hw *); 165 static void e1000g_release_driver_control(struct e1000_hw *); 166 static void e1000g_restore_promisc(struct e1000g *Adapter); 167 168 char *e1000g_priv_props[] = { 169 "_tx_bcopy_threshold", 170 "_tx_interrupt_enable", 171 "_tx_intr_delay", 172 "_tx_intr_abs_delay", 173 "_rx_bcopy_threshold", 174 "_max_num_rcv_packets", 175 "_rx_intr_delay", 176 "_rx_intr_abs_delay", 177 "_intr_throttling_rate", 178 "_intr_adaptive", 179 "_adv_pause_cap", 180 "_adv_asym_pause_cap", 181 NULL 182 }; 183 184 static struct cb_ops cb_ws_ops = { 185 nulldev, /* cb_open */ 186 nulldev, /* cb_close */ 187 nodev, /* cb_strategy */ 188 nodev, /* cb_print */ 189 nodev, /* cb_dump */ 190 nodev, /* cb_read */ 191 nodev, /* cb_write */ 192 nodev, /* cb_ioctl */ 193 nodev, /* cb_devmap */ 194 nodev, /* cb_mmap */ 195 nodev, /* cb_segmap */ 196 nochpoll, /* cb_chpoll */ 197 ddi_prop_op, /* cb_prop_op */ 198 NULL, /* cb_stream */ 199 D_MP | D_HOTPLUG, /* cb_flag */ 200 CB_REV, /* cb_rev */ 201 nodev, /* cb_aread */ 202 nodev /* cb_awrite */ 203 }; 204 205 static struct dev_ops ws_ops = { 206 DEVO_REV, /* devo_rev */ 207 0, /* devo_refcnt */ 208 NULL, /* devo_getinfo */ 209 nulldev, /* devo_identify */ 210 nulldev, /* devo_probe */ 211 e1000g_attach, /* devo_attach */ 212 e1000g_detach, /* devo_detach */ 213 nodev, /* devo_reset */ 214 &cb_ws_ops, /* devo_cb_ops */ 215 NULL, /* devo_bus_ops */ 216 ddi_power, /* devo_power */ 217 e1000g_quiesce /* devo_quiesce */ 218 }; 219 220 static struct modldrv modldrv = { 221 &mod_driverops, /* Type of module. This one is a driver */ 222 ident, /* Discription string */ 223 &ws_ops, /* driver ops */ 224 }; 225 226 static struct modlinkage modlinkage = { 227 MODREV_1, &modldrv, NULL 228 }; 229 230 /* Access attributes for register mapping */ 231 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 232 DDI_DEVICE_ATTR_V1, 233 DDI_STRUCTURE_LE_ACC, 234 DDI_STRICTORDER_ACC, 235 DDI_FLAGERR_ACC 236 }; 237 238 #define E1000G_M_CALLBACK_FLAGS \ 239 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO) 240 241 static mac_callbacks_t e1000g_m_callbacks = { 242 E1000G_M_CALLBACK_FLAGS, 243 e1000g_m_stat, 244 e1000g_m_start, 245 e1000g_m_stop, 246 e1000g_m_promisc, 247 e1000g_m_multicst, 248 NULL, 249 e1000g_m_tx, 250 NULL, 251 e1000g_m_ioctl, 252 e1000g_m_getcapab, 253 NULL, 254 NULL, 255 e1000g_m_setprop, 256 e1000g_m_getprop, 257 e1000g_m_propinfo 258 }; 259 260 /* 261 * Global variables 262 */ 263 uint32_t e1000g_jumbo_mtu = MAXIMUM_MTU_9K; 264 uint32_t e1000g_mblks_pending = 0; 265 /* 266 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 267 * Here we maintain a private dev_info list if e1000g_force_detach is 268 * enabled. If we force the driver to detach while there are still some 269 * rx buffers retained in the upper layer, we have to keep a copy of the 270 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 271 * structure will be freed after the driver is detached. However when we 272 * finally free those rx buffers released by the upper layer, we need to 273 * refer to the dev_info to free the dma buffers. So we save a copy of 274 * the dev_info for this purpose. On x86 platform, we assume this copy 275 * of dev_info is always valid, but on SPARC platform, it could be invalid 276 * after the system board level DR operation. For this reason, the global 277 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 278 */ 279 #ifdef __sparc 280 boolean_t e1000g_force_detach = B_FALSE; 281 #else 282 boolean_t e1000g_force_detach = B_TRUE; 283 #endif 284 private_devi_list_t *e1000g_private_devi_list = NULL; 285 286 /* 287 * The mutex e1000g_rx_detach_lock is defined to protect the processing of 288 * the private dev_info list, and to serialize the processing of rx buffer 289 * freeing and rx buffer recycling. 290 */ 291 kmutex_t e1000g_rx_detach_lock; 292 /* 293 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 294 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 295 * If there are many e1000g instances, the system may run out of DVMA 296 * resources during the initialization of the instances, then the flag will 297 * be changed to "USE_DMA". Because different e1000g instances are initialized 298 * in parallel, we need to use this lock to protect the flag. 299 */ 300 krwlock_t e1000g_dma_type_lock; 301 302 /* 303 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 304 * Based on the information from Intel, the 82546 chipset has some hardware 305 * problem. When one port is being reset and the other port is trying to 306 * access the eeprom, it could cause system hang or panic. To workaround this 307 * hardware problem, we use a global mutex to prevent such operations from 308 * happening simultaneously on different instances. This workaround is applied 309 * to all the devices supported by this driver. 310 */ 311 kmutex_t e1000g_nvm_lock; 312 313 /* 314 * Loadable module configuration entry points for the driver 315 */ 316 317 /* 318 * _init - module initialization 319 */ 320 int 321 _init(void) 322 { 323 int status; 324 325 mac_init_ops(&ws_ops, WSNAME); 326 status = mod_install(&modlinkage); 327 if (status != DDI_SUCCESS) 328 mac_fini_ops(&ws_ops); 329 else { 330 mutex_init(&e1000g_rx_detach_lock, NULL, MUTEX_DRIVER, NULL); 331 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 332 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 333 } 334 335 return (status); 336 } 337 338 /* 339 * _fini - module finalization 340 */ 341 int 342 _fini(void) 343 { 344 int status; 345 346 if (e1000g_mblks_pending != 0) 347 return (EBUSY); 348 349 status = mod_remove(&modlinkage); 350 if (status == DDI_SUCCESS) { 351 mac_fini_ops(&ws_ops); 352 353 if (e1000g_force_detach) { 354 private_devi_list_t *devi_node; 355 356 mutex_enter(&e1000g_rx_detach_lock); 357 while (e1000g_private_devi_list != NULL) { 358 devi_node = e1000g_private_devi_list; 359 e1000g_private_devi_list = 360 e1000g_private_devi_list->next; 361 362 kmem_free(devi_node->priv_dip, 363 sizeof (struct dev_info)); 364 kmem_free(devi_node, 365 sizeof (private_devi_list_t)); 366 } 367 mutex_exit(&e1000g_rx_detach_lock); 368 } 369 370 mutex_destroy(&e1000g_rx_detach_lock); 371 rw_destroy(&e1000g_dma_type_lock); 372 mutex_destroy(&e1000g_nvm_lock); 373 } 374 375 return (status); 376 } 377 378 /* 379 * _info - module information 380 */ 381 int 382 _info(struct modinfo *modinfop) 383 { 384 return (mod_info(&modlinkage, modinfop)); 385 } 386 387 /* 388 * e1000g_attach - driver attach 389 * 390 * This function is the device-specific initialization entry 391 * point. This entry point is required and must be written. 392 * The DDI_ATTACH command must be provided in the attach entry 393 * point. When attach() is called with cmd set to DDI_ATTACH, 394 * all normal kernel services (such as kmem_alloc(9F)) are 395 * available for use by the driver. 396 * 397 * The attach() function will be called once for each instance 398 * of the device on the system with cmd set to DDI_ATTACH. 399 * Until attach() succeeds, the only driver entry points which 400 * may be called are open(9E) and getinfo(9E). 401 */ 402 static int 403 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 404 { 405 struct e1000g *Adapter; 406 struct e1000_hw *hw; 407 struct e1000g_osdep *osdep; 408 int instance; 409 410 switch (cmd) { 411 default: 412 e1000g_log(NULL, CE_WARN, 413 "Unsupported command send to e1000g_attach... "); 414 return (DDI_FAILURE); 415 416 case DDI_RESUME: 417 return (e1000g_resume(devinfo)); 418 419 case DDI_ATTACH: 420 break; 421 } 422 423 /* 424 * get device instance number 425 */ 426 instance = ddi_get_instance(devinfo); 427 428 /* 429 * Allocate soft data structure 430 */ 431 Adapter = 432 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 433 434 Adapter->dip = devinfo; 435 Adapter->instance = instance; 436 Adapter->tx_ring->adapter = Adapter; 437 Adapter->rx_ring->adapter = Adapter; 438 439 hw = &Adapter->shared; 440 osdep = &Adapter->osdep; 441 hw->back = osdep; 442 osdep->adapter = Adapter; 443 444 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 445 446 /* 447 * Initialize for fma support 448 */ 449 (void) e1000g_get_prop(Adapter, "fm-capable", 450 0, 0x0f, 451 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 452 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE, 453 &Adapter->fm_capabilities); 454 e1000g_fm_init(Adapter); 455 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 456 457 /* 458 * PCI Configure 459 */ 460 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 461 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 462 goto attach_fail; 463 } 464 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 465 466 /* 467 * Setup hardware 468 */ 469 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 470 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 471 goto attach_fail; 472 } 473 474 /* 475 * Map in the device registers. 476 */ 477 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 478 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 479 goto attach_fail; 480 } 481 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 482 483 /* 484 * Initialize driver parameters 485 */ 486 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 487 goto attach_fail; 488 } 489 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 490 491 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 492 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 493 goto attach_fail; 494 } 495 496 /* 497 * Disable ULP support 498 */ 499 (void) e1000_disable_ulp_lpt_lp(hw, TRUE); 500 501 /* 502 * Initialize interrupts 503 */ 504 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 505 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 506 goto attach_fail; 507 } 508 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 509 510 /* 511 * Initialize mutex's for this device. 512 * Do this before enabling the interrupt handler and 513 * register the softint to avoid the condition where 514 * interrupt handler can try using uninitialized mutex 515 */ 516 e1000g_init_locks(Adapter); 517 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 518 519 /* 520 * Initialize Driver Counters 521 */ 522 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 523 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 524 goto attach_fail; 525 } 526 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 527 528 /* 529 * Initialize chip hardware and software structures 530 */ 531 rw_enter(&Adapter->chip_lock, RW_WRITER); 532 if (e1000g_init(Adapter) != DDI_SUCCESS) { 533 rw_exit(&Adapter->chip_lock); 534 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 535 goto attach_fail; 536 } 537 rw_exit(&Adapter->chip_lock); 538 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 539 540 /* 541 * Register the driver to the MAC 542 */ 543 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 544 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 545 goto attach_fail; 546 } 547 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 548 549 /* 550 * Now that mutex locks are initialized, and the chip is also 551 * initialized, enable interrupts. 552 */ 553 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 554 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 555 goto attach_fail; 556 } 557 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 558 559 /* 560 * If e1000g_force_detach is enabled, in global private dip list, 561 * we will create a new entry, which maintains the priv_dip for DR 562 * supports after driver detached. 563 */ 564 if (e1000g_force_detach) { 565 private_devi_list_t *devi_node; 566 567 Adapter->priv_dip = 568 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 569 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 570 sizeof (struct dev_info)); 571 572 devi_node = 573 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 574 575 mutex_enter(&e1000g_rx_detach_lock); 576 devi_node->priv_dip = Adapter->priv_dip; 577 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 578 devi_node->pending_rx_count = 0; 579 580 Adapter->priv_devi_node = devi_node; 581 582 if (e1000g_private_devi_list == NULL) { 583 devi_node->prev = NULL; 584 devi_node->next = NULL; 585 e1000g_private_devi_list = devi_node; 586 } else { 587 devi_node->prev = NULL; 588 devi_node->next = e1000g_private_devi_list; 589 e1000g_private_devi_list->prev = devi_node; 590 e1000g_private_devi_list = devi_node; 591 } 592 mutex_exit(&e1000g_rx_detach_lock); 593 } 594 595 Adapter->e1000g_state = E1000G_INITIALIZED; 596 return (DDI_SUCCESS); 597 598 attach_fail: 599 e1000g_unattach(devinfo, Adapter); 600 return (DDI_FAILURE); 601 } 602 603 static int 604 e1000g_register_mac(struct e1000g *Adapter) 605 { 606 struct e1000_hw *hw = &Adapter->shared; 607 mac_register_t *mac; 608 int err; 609 610 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 611 return (DDI_FAILURE); 612 613 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 614 mac->m_driver = Adapter; 615 mac->m_dip = Adapter->dip; 616 mac->m_src_addr = hw->mac.addr; 617 mac->m_callbacks = &e1000g_m_callbacks; 618 mac->m_min_sdu = 0; 619 mac->m_max_sdu = Adapter->default_mtu; 620 mac->m_margin = VLAN_TAGSZ; 621 mac->m_priv_props = e1000g_priv_props; 622 mac->m_v12n = MAC_VIRT_LEVEL1; 623 624 err = mac_register(mac, &Adapter->mh); 625 mac_free(mac); 626 627 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 628 } 629 630 static int 631 e1000g_identify_hardware(struct e1000g *Adapter) 632 { 633 struct e1000_hw *hw = &Adapter->shared; 634 struct e1000g_osdep *osdep = &Adapter->osdep; 635 636 /* Get the device id */ 637 hw->vendor_id = 638 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 639 hw->device_id = 640 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 641 hw->revision_id = 642 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 643 hw->subsystem_device_id = 644 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 645 hw->subsystem_vendor_id = 646 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 647 648 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 649 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 650 "MAC type could not be set properly."); 651 return (DDI_FAILURE); 652 } 653 654 return (DDI_SUCCESS); 655 } 656 657 static int 658 e1000g_regs_map(struct e1000g *Adapter) 659 { 660 dev_info_t *devinfo = Adapter->dip; 661 struct e1000_hw *hw = &Adapter->shared; 662 struct e1000g_osdep *osdep = &Adapter->osdep; 663 off_t mem_size; 664 bar_info_t bar_info; 665 int offset, rnumber; 666 667 rnumber = ADAPTER_REG_SET; 668 /* Get size of adapter register memory */ 669 if (ddi_dev_regsize(devinfo, rnumber, &mem_size) != 670 DDI_SUCCESS) { 671 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 672 "ddi_dev_regsize for registers failed"); 673 return (DDI_FAILURE); 674 } 675 676 /* Map adapter register memory */ 677 if ((ddi_regs_map_setup(devinfo, rnumber, 678 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 679 &osdep->reg_handle)) != DDI_SUCCESS) { 680 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 681 "ddi_regs_map_setup for registers failed"); 682 goto regs_map_fail; 683 } 684 685 /* ICH needs to map flash memory */ 686 switch (hw->mac.type) { 687 case e1000_ich8lan: 688 case e1000_ich9lan: 689 case e1000_ich10lan: 690 case e1000_pchlan: 691 case e1000_pch2lan: 692 case e1000_pch_lpt: 693 rnumber = ICH_FLASH_REG_SET; 694 695 /* get flash size */ 696 if (ddi_dev_regsize(devinfo, rnumber, 697 &mem_size) != DDI_SUCCESS) { 698 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 699 "ddi_dev_regsize for ICH flash failed"); 700 goto regs_map_fail; 701 } 702 703 /* map flash in */ 704 if (ddi_regs_map_setup(devinfo, rnumber, 705 (caddr_t *)&hw->flash_address, 0, 706 mem_size, &e1000g_regs_acc_attr, 707 &osdep->ich_flash_handle) != DDI_SUCCESS) { 708 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 709 "ddi_regs_map_setup for ICH flash failed"); 710 goto regs_map_fail; 711 } 712 break; 713 case e1000_pch_spt: 714 case e1000_pch_cnp: 715 case e1000_pch_tgp: 716 /* 717 * On the SPT, the device flash is actually in BAR0, not a 718 * separate BAR. Therefore we end up setting the 719 * ich_flash_handle to be the same as the register handle. 720 * We mark the same to reduce the confusion in the other 721 * functions and macros. Though this does make the set up and 722 * tear-down path slightly more complicated. 723 */ 724 osdep->ich_flash_handle = osdep->reg_handle; 725 hw->flash_address = hw->hw_addr; 726 default: 727 break; 728 } 729 730 /* map io space */ 731 switch (hw->mac.type) { 732 case e1000_82544: 733 case e1000_82540: 734 case e1000_82545: 735 case e1000_82546: 736 case e1000_82541: 737 case e1000_82541_rev_2: 738 /* find the IO bar */ 739 rnumber = -1; 740 for (offset = PCI_CONF_BASE1; 741 offset <= PCI_CONF_BASE5; offset += 4) { 742 if (e1000g_get_bar_info(devinfo, offset, &bar_info) 743 != DDI_SUCCESS) 744 continue; 745 if (bar_info.type == E1000G_BAR_IO) { 746 rnumber = bar_info.rnumber; 747 break; 748 } 749 } 750 751 if (rnumber < 0) { 752 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 753 "No io space is found"); 754 goto regs_map_fail; 755 } 756 757 /* get io space size */ 758 if (ddi_dev_regsize(devinfo, rnumber, 759 &mem_size) != DDI_SUCCESS) { 760 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 761 "ddi_dev_regsize for io space failed"); 762 goto regs_map_fail; 763 } 764 765 /* map io space */ 766 if ((ddi_regs_map_setup(devinfo, rnumber, 767 (caddr_t *)&hw->io_base, 0, mem_size, 768 &e1000g_regs_acc_attr, 769 &osdep->io_reg_handle)) != DDI_SUCCESS) { 770 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 771 "ddi_regs_map_setup for io space failed"); 772 goto regs_map_fail; 773 } 774 break; 775 default: 776 hw->io_base = 0; 777 break; 778 } 779 780 return (DDI_SUCCESS); 781 782 regs_map_fail: 783 if (osdep->reg_handle != NULL) 784 ddi_regs_map_free(&osdep->reg_handle); 785 if (osdep->ich_flash_handle != NULL && hw->mac.type < e1000_pch_spt) 786 ddi_regs_map_free(&osdep->ich_flash_handle); 787 return (DDI_FAILURE); 788 } 789 790 static int 791 e1000g_set_driver_params(struct e1000g *Adapter) 792 { 793 struct e1000_hw *hw; 794 795 hw = &Adapter->shared; 796 797 /* Set MAC type and initialize hardware functions */ 798 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 799 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 800 "Could not setup hardware functions"); 801 return (DDI_FAILURE); 802 } 803 804 /* Get bus information */ 805 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 806 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 807 "Could not get bus information"); 808 return (DDI_FAILURE); 809 } 810 811 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 812 813 hw->mac.autoneg_failed = B_TRUE; 814 815 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 816 hw->phy.autoneg_wait_to_complete = B_FALSE; 817 818 /* Adaptive IFS related changes */ 819 hw->mac.adaptive_ifs = B_TRUE; 820 821 /* Enable phy init script for IGP phy of 82541/82547 */ 822 if ((hw->mac.type == e1000_82547) || 823 (hw->mac.type == e1000_82541) || 824 (hw->mac.type == e1000_82547_rev_2) || 825 (hw->mac.type == e1000_82541_rev_2)) 826 e1000_init_script_state_82541(hw, B_TRUE); 827 828 /* Enable the TTL workaround for 82541/82547 */ 829 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 830 831 #ifdef __sparc 832 Adapter->strip_crc = B_TRUE; 833 #else 834 Adapter->strip_crc = B_FALSE; 835 #endif 836 837 /* setup the maximum MTU size of the chip */ 838 e1000g_setup_max_mtu(Adapter); 839 840 /* Get speed/duplex settings in conf file */ 841 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 842 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 843 e1000g_force_speed_duplex(Adapter); 844 845 /* Get Jumbo Frames settings in conf file */ 846 e1000g_get_max_frame_size(Adapter); 847 848 /* Get conf file properties */ 849 e1000g_get_conf(Adapter); 850 851 /* enforce PCH limits */ 852 e1000g_pch_limits(Adapter); 853 854 /* Set Rx/Tx buffer size */ 855 e1000g_set_bufsize(Adapter); 856 857 /* Master Latency Timer */ 858 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 859 860 /* copper options */ 861 if (hw->phy.media_type == e1000_media_type_copper) { 862 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 863 hw->phy.disable_polarity_correction = B_FALSE; 864 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 865 } 866 867 /* The initial link state should be "unknown" */ 868 Adapter->link_state = LINK_STATE_UNKNOWN; 869 870 /* Initialize rx parameters */ 871 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 872 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 873 874 /* Initialize tx parameters */ 875 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 876 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 877 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 878 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 879 880 /* Initialize rx parameters */ 881 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 882 883 return (DDI_SUCCESS); 884 } 885 886 static void 887 e1000g_setup_max_mtu(struct e1000g *Adapter) 888 { 889 struct e1000_mac_info *mac = &Adapter->shared.mac; 890 struct e1000_phy_info *phy = &Adapter->shared.phy; 891 892 switch (mac->type) { 893 /* types that do not support jumbo frames */ 894 case e1000_ich8lan: 895 case e1000_82573: 896 case e1000_82583: 897 Adapter->max_mtu = ETHERMTU; 898 break; 899 /* ich9 supports jumbo frames except on one phy type */ 900 case e1000_ich9lan: 901 if (phy->type == e1000_phy_ife) 902 Adapter->max_mtu = ETHERMTU; 903 else 904 Adapter->max_mtu = MAXIMUM_MTU_9K; 905 break; 906 /* pch can do jumbo frames up to 4K */ 907 case e1000_pchlan: 908 Adapter->max_mtu = MAXIMUM_MTU_4K; 909 break; 910 /* pch2 can do jumbo frames up to 9K */ 911 case e1000_pch2lan: 912 case e1000_pch_lpt: 913 case e1000_pch_spt: 914 case e1000_pch_cnp: 915 case e1000_pch_tgp: 916 Adapter->max_mtu = MAXIMUM_MTU_9K; 917 break; 918 /* types with a special limit */ 919 case e1000_82571: 920 case e1000_82572: 921 case e1000_82574: 922 case e1000_80003es2lan: 923 case e1000_ich10lan: 924 if (e1000g_jumbo_mtu >= ETHERMTU && 925 e1000g_jumbo_mtu <= MAXIMUM_MTU_9K) { 926 Adapter->max_mtu = e1000g_jumbo_mtu; 927 } else { 928 Adapter->max_mtu = MAXIMUM_MTU_9K; 929 } 930 break; 931 /* default limit is 16K */ 932 default: 933 Adapter->max_mtu = FRAME_SIZE_UPTO_16K - 934 sizeof (struct ether_vlan_header) - ETHERFCSL; 935 break; 936 } 937 } 938 939 static void 940 e1000g_set_bufsize(struct e1000g *Adapter) 941 { 942 struct e1000_mac_info *mac = &Adapter->shared.mac; 943 uint64_t rx_size; 944 uint64_t tx_size; 945 946 dev_info_t *devinfo = Adapter->dip; 947 #ifdef __sparc 948 ulong_t iommu_pagesize; 949 #endif 950 /* Get the system page size */ 951 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 952 953 #ifdef __sparc 954 iommu_pagesize = dvma_pagesize(devinfo); 955 if (iommu_pagesize != 0) { 956 if (Adapter->sys_page_sz == iommu_pagesize) { 957 if (iommu_pagesize > 0x4000) 958 Adapter->sys_page_sz = 0x4000; 959 } else { 960 if (Adapter->sys_page_sz > iommu_pagesize) 961 Adapter->sys_page_sz = iommu_pagesize; 962 } 963 } 964 if (Adapter->lso_enable) { 965 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 966 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 967 } else { 968 Adapter->dvma_page_num = Adapter->max_frame_size / 969 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 970 } 971 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 972 #endif 973 974 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 975 976 if (Adapter->mem_workaround_82546 && 977 ((mac->type == e1000_82545) || 978 (mac->type == e1000_82546) || 979 (mac->type == e1000_82546_rev_3))) { 980 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 981 } else { 982 rx_size = Adapter->max_frame_size; 983 if ((rx_size > FRAME_SIZE_UPTO_2K) && 984 (rx_size <= FRAME_SIZE_UPTO_4K)) 985 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 986 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 987 (rx_size <= FRAME_SIZE_UPTO_8K)) 988 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 989 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 990 (rx_size <= FRAME_SIZE_UPTO_16K)) 991 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 992 else 993 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 994 } 995 Adapter->rx_buffer_size += E1000G_IPALIGNROOM; 996 997 tx_size = Adapter->max_frame_size; 998 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 999 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 1000 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 1001 (tx_size <= FRAME_SIZE_UPTO_8K)) 1002 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 1003 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 1004 (tx_size <= FRAME_SIZE_UPTO_16K)) 1005 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 1006 else 1007 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 1008 1009 /* 1010 * For Wiseman adapters we have an requirement of having receive 1011 * buffers aligned at 256 byte boundary. Since Livengood does not 1012 * require this and forcing it for all hardwares will have 1013 * performance implications, I am making it applicable only for 1014 * Wiseman and for Jumbo frames enabled mode as rest of the time, 1015 * it is okay to have normal frames...but it does involve a 1016 * potential risk where we may loose data if buffer is not 1017 * aligned...so all wiseman boards to have 256 byte aligned 1018 * buffers 1019 */ 1020 if (mac->type < e1000_82543) 1021 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 1022 else 1023 Adapter->rx_buf_align = 1; 1024 } 1025 1026 /* 1027 * e1000g_detach - driver detach 1028 * 1029 * The detach() function is the complement of the attach routine. 1030 * If cmd is set to DDI_DETACH, detach() is used to remove the 1031 * state associated with a given instance of a device node 1032 * prior to the removal of that instance from the system. 1033 * 1034 * The detach() function will be called once for each instance 1035 * of the device for which there has been a successful attach() 1036 * once there are no longer any opens on the device. 1037 * 1038 * Interrupts routine are disabled, All memory allocated by this 1039 * driver are freed. 1040 */ 1041 static int 1042 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 1043 { 1044 struct e1000g *Adapter; 1045 boolean_t rx_drain; 1046 1047 switch (cmd) { 1048 default: 1049 return (DDI_FAILURE); 1050 1051 case DDI_SUSPEND: 1052 return (e1000g_suspend(devinfo)); 1053 1054 case DDI_DETACH: 1055 break; 1056 } 1057 1058 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1059 if (Adapter == NULL) 1060 return (DDI_FAILURE); 1061 1062 rx_drain = e1000g_rx_drain(Adapter); 1063 if (!rx_drain && !e1000g_force_detach) 1064 return (DDI_FAILURE); 1065 1066 if (mac_unregister(Adapter->mh) != 0) { 1067 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 1068 return (DDI_FAILURE); 1069 } 1070 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 1071 1072 ASSERT(!(Adapter->e1000g_state & E1000G_STARTED)); 1073 1074 if (!e1000g_force_detach && !rx_drain) 1075 return (DDI_FAILURE); 1076 1077 e1000g_unattach(devinfo, Adapter); 1078 1079 return (DDI_SUCCESS); 1080 } 1081 1082 /* 1083 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 1084 */ 1085 void 1086 e1000g_free_priv_devi_node(private_devi_list_t *devi_node) 1087 { 1088 ASSERT(e1000g_private_devi_list != NULL); 1089 ASSERT(devi_node != NULL); 1090 1091 if (devi_node->prev != NULL) 1092 devi_node->prev->next = devi_node->next; 1093 if (devi_node->next != NULL) 1094 devi_node->next->prev = devi_node->prev; 1095 if (devi_node == e1000g_private_devi_list) 1096 e1000g_private_devi_list = devi_node->next; 1097 1098 kmem_free(devi_node->priv_dip, 1099 sizeof (struct dev_info)); 1100 kmem_free(devi_node, 1101 sizeof (private_devi_list_t)); 1102 } 1103 1104 static void 1105 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1106 { 1107 private_devi_list_t *devi_node; 1108 int result; 1109 1110 if (Adapter->e1000g_blink != NULL) { 1111 ddi_periodic_delete(Adapter->e1000g_blink); 1112 Adapter->e1000g_blink = NULL; 1113 } 1114 1115 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1116 (void) e1000g_disable_intrs(Adapter); 1117 } 1118 1119 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1120 (void) mac_unregister(Adapter->mh); 1121 } 1122 1123 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1124 (void) e1000g_rem_intrs(Adapter); 1125 } 1126 1127 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1128 (void) ddi_prop_remove_all(devinfo); 1129 } 1130 1131 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1132 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1133 } 1134 1135 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1136 stop_link_timer(Adapter); 1137 1138 mutex_enter(&e1000g_nvm_lock); 1139 result = e1000_reset_hw(&Adapter->shared); 1140 mutex_exit(&e1000g_nvm_lock); 1141 1142 if (result != E1000_SUCCESS) { 1143 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1144 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1145 } 1146 } 1147 1148 e1000g_release_multicast(Adapter); 1149 1150 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1151 if (Adapter->osdep.reg_handle != NULL) 1152 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1153 if (Adapter->osdep.ich_flash_handle != NULL && 1154 Adapter->shared.mac.type < e1000_pch_spt) 1155 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1156 if (Adapter->osdep.io_reg_handle != NULL) 1157 ddi_regs_map_free(&Adapter->osdep.io_reg_handle); 1158 } 1159 1160 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1161 if (Adapter->osdep.cfg_handle != NULL) 1162 pci_config_teardown(&Adapter->osdep.cfg_handle); 1163 } 1164 1165 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1166 e1000g_destroy_locks(Adapter); 1167 } 1168 1169 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1170 e1000g_fm_fini(Adapter); 1171 } 1172 1173 mutex_enter(&e1000g_rx_detach_lock); 1174 if (e1000g_force_detach && (Adapter->priv_devi_node != NULL)) { 1175 devi_node = Adapter->priv_devi_node; 1176 devi_node->flag |= E1000G_PRIV_DEVI_DETACH; 1177 1178 if (devi_node->pending_rx_count == 0) { 1179 e1000g_free_priv_devi_node(devi_node); 1180 } 1181 } 1182 mutex_exit(&e1000g_rx_detach_lock); 1183 1184 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1185 1186 /* 1187 * Another hotplug spec requirement, 1188 * run ddi_set_driver_private(devinfo, null); 1189 */ 1190 ddi_set_driver_private(devinfo, NULL); 1191 } 1192 1193 /* 1194 * Get the BAR type and rnumber for a given PCI BAR offset 1195 */ 1196 static int 1197 e1000g_get_bar_info(dev_info_t *dip, int bar_offset, bar_info_t *bar_info) 1198 { 1199 pci_regspec_t *regs; 1200 uint_t regs_length; 1201 int type, rnumber, rcount; 1202 1203 ASSERT((bar_offset >= PCI_CONF_BASE0) && 1204 (bar_offset <= PCI_CONF_BASE5)); 1205 1206 /* 1207 * Get the DDI "reg" property 1208 */ 1209 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 1210 DDI_PROP_DONTPASS, "reg", (int **)®s, 1211 ®s_length) != DDI_PROP_SUCCESS) { 1212 return (DDI_FAILURE); 1213 } 1214 1215 rcount = regs_length * sizeof (int) / sizeof (pci_regspec_t); 1216 /* 1217 * Check the BAR offset 1218 */ 1219 for (rnumber = 0; rnumber < rcount; ++rnumber) { 1220 if (PCI_REG_REG_G(regs[rnumber].pci_phys_hi) == bar_offset) { 1221 type = regs[rnumber].pci_phys_hi & PCI_ADDR_MASK; 1222 break; 1223 } 1224 } 1225 1226 ddi_prop_free(regs); 1227 1228 if (rnumber >= rcount) 1229 return (DDI_FAILURE); 1230 1231 switch (type) { 1232 case PCI_ADDR_CONFIG: 1233 bar_info->type = E1000G_BAR_CONFIG; 1234 break; 1235 case PCI_ADDR_IO: 1236 bar_info->type = E1000G_BAR_IO; 1237 break; 1238 case PCI_ADDR_MEM32: 1239 bar_info->type = E1000G_BAR_MEM32; 1240 break; 1241 case PCI_ADDR_MEM64: 1242 bar_info->type = E1000G_BAR_MEM64; 1243 break; 1244 default: 1245 return (DDI_FAILURE); 1246 } 1247 bar_info->rnumber = rnumber; 1248 return (DDI_SUCCESS); 1249 } 1250 1251 static void 1252 e1000g_init_locks(struct e1000g *Adapter) 1253 { 1254 e1000g_tx_ring_t *tx_ring; 1255 e1000g_rx_ring_t *rx_ring; 1256 1257 rw_init(&Adapter->chip_lock, NULL, 1258 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1259 mutex_init(&Adapter->link_lock, NULL, 1260 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1261 mutex_init(&Adapter->watchdog_lock, NULL, 1262 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1263 1264 tx_ring = Adapter->tx_ring; 1265 1266 mutex_init(&tx_ring->tx_lock, NULL, 1267 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1268 mutex_init(&tx_ring->usedlist_lock, NULL, 1269 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1270 mutex_init(&tx_ring->freelist_lock, NULL, 1271 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1272 1273 rx_ring = Adapter->rx_ring; 1274 1275 mutex_init(&rx_ring->rx_lock, NULL, 1276 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1277 1278 mutex_init(&Adapter->e1000g_led_lock, NULL, 1279 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1280 } 1281 1282 static void 1283 e1000g_destroy_locks(struct e1000g *Adapter) 1284 { 1285 e1000g_tx_ring_t *tx_ring; 1286 e1000g_rx_ring_t *rx_ring; 1287 1288 mutex_destroy(&Adapter->e1000g_led_lock); 1289 1290 tx_ring = Adapter->tx_ring; 1291 mutex_destroy(&tx_ring->tx_lock); 1292 mutex_destroy(&tx_ring->usedlist_lock); 1293 mutex_destroy(&tx_ring->freelist_lock); 1294 1295 rx_ring = Adapter->rx_ring; 1296 mutex_destroy(&rx_ring->rx_lock); 1297 1298 mutex_destroy(&Adapter->link_lock); 1299 mutex_destroy(&Adapter->watchdog_lock); 1300 rw_destroy(&Adapter->chip_lock); 1301 1302 /* destory mutex initialized in shared code */ 1303 e1000_destroy_hw_mutex(&Adapter->shared); 1304 } 1305 1306 static int 1307 e1000g_resume(dev_info_t *devinfo) 1308 { 1309 struct e1000g *Adapter; 1310 1311 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1312 if (Adapter == NULL) 1313 e1000g_log(Adapter, CE_PANIC, 1314 "Instance pointer is null\n"); 1315 1316 if (Adapter->dip != devinfo) 1317 e1000g_log(Adapter, CE_PANIC, 1318 "Devinfo is not the same as saved devinfo\n"); 1319 1320 rw_enter(&Adapter->chip_lock, RW_WRITER); 1321 1322 if (Adapter->e1000g_state & E1000G_STARTED) { 1323 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1324 rw_exit(&Adapter->chip_lock); 1325 /* 1326 * We note the failure, but return success, as the 1327 * system is still usable without this controller. 1328 */ 1329 e1000g_log(Adapter, CE_WARN, 1330 "e1000g_resume: failed to restart controller\n"); 1331 return (DDI_SUCCESS); 1332 } 1333 /* Enable and start the watchdog timer */ 1334 enable_watchdog_timer(Adapter); 1335 } 1336 1337 Adapter->e1000g_state &= ~E1000G_SUSPENDED; 1338 1339 rw_exit(&Adapter->chip_lock); 1340 1341 return (DDI_SUCCESS); 1342 } 1343 1344 static int 1345 e1000g_suspend(dev_info_t *devinfo) 1346 { 1347 struct e1000g *Adapter; 1348 1349 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1350 if (Adapter == NULL) 1351 return (DDI_FAILURE); 1352 1353 rw_enter(&Adapter->chip_lock, RW_WRITER); 1354 1355 Adapter->e1000g_state |= E1000G_SUSPENDED; 1356 1357 /* if the port isn't plumbed, we can simply return */ 1358 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 1359 rw_exit(&Adapter->chip_lock); 1360 return (DDI_SUCCESS); 1361 } 1362 1363 e1000g_stop(Adapter, B_FALSE); 1364 1365 rw_exit(&Adapter->chip_lock); 1366 1367 /* Disable and stop all the timers */ 1368 disable_watchdog_timer(Adapter); 1369 stop_link_timer(Adapter); 1370 stop_82547_timer(Adapter->tx_ring); 1371 1372 return (DDI_SUCCESS); 1373 } 1374 1375 static int 1376 e1000g_init(struct e1000g *Adapter) 1377 { 1378 uint32_t pba; 1379 uint32_t high_water; 1380 struct e1000_hw *hw; 1381 clock_t link_timeout; 1382 int result; 1383 1384 hw = &Adapter->shared; 1385 1386 /* 1387 * reset to put the hardware in a known state 1388 * before we try to do anything with the eeprom 1389 */ 1390 mutex_enter(&e1000g_nvm_lock); 1391 result = e1000_reset_hw(hw); 1392 mutex_exit(&e1000g_nvm_lock); 1393 1394 if (result != E1000_SUCCESS) { 1395 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1396 goto init_fail; 1397 } 1398 1399 mutex_enter(&e1000g_nvm_lock); 1400 result = e1000_validate_nvm_checksum(hw); 1401 if (result < E1000_SUCCESS) { 1402 /* 1403 * Some PCI-E parts fail the first check due to 1404 * the link being in sleep state. Call it again, 1405 * if it fails a second time its a real issue. 1406 */ 1407 result = e1000_validate_nvm_checksum(hw); 1408 } 1409 mutex_exit(&e1000g_nvm_lock); 1410 1411 if (result < E1000_SUCCESS) { 1412 e1000g_log(Adapter, CE_WARN, 1413 "Invalid NVM checksum. Please contact " 1414 "the vendor to update the NVM."); 1415 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1416 goto init_fail; 1417 } 1418 1419 result = 0; 1420 #ifdef __sparc 1421 /* 1422 * First, we try to get the local ethernet address from OBP. If 1423 * failed, then we get it from the EEPROM of NIC card. 1424 */ 1425 result = e1000g_find_mac_address(Adapter); 1426 #endif 1427 /* Get the local ethernet address. */ 1428 if (!result) { 1429 mutex_enter(&e1000g_nvm_lock); 1430 result = e1000_read_mac_addr(hw); 1431 mutex_exit(&e1000g_nvm_lock); 1432 } 1433 1434 if (result < E1000_SUCCESS) { 1435 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1436 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1437 goto init_fail; 1438 } 1439 1440 /* check for valid mac address */ 1441 if (!is_valid_mac_addr(hw->mac.addr)) { 1442 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1443 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1444 goto init_fail; 1445 } 1446 1447 /* Set LAA state for 82571 chipset */ 1448 e1000_set_laa_state_82571(hw, B_TRUE); 1449 1450 /* Master Latency Timer implementation */ 1451 if (Adapter->master_latency_timer) { 1452 pci_config_put8(Adapter->osdep.cfg_handle, 1453 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1454 } 1455 1456 if (hw->mac.type < e1000_82547) { 1457 /* 1458 * Total FIFO is 64K 1459 */ 1460 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1461 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1462 else 1463 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1464 } else if ((hw->mac.type == e1000_82571) || 1465 (hw->mac.type == e1000_82572) || 1466 (hw->mac.type == e1000_80003es2lan)) { 1467 /* 1468 * Total FIFO is 48K 1469 */ 1470 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1471 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1472 else 1473 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1474 } else if (hw->mac.type == e1000_82573) { 1475 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1476 } else if (hw->mac.type == e1000_82574) { 1477 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1478 pba = E1000_READ_REG(hw, E1000_PBA); 1479 } else if (hw->mac.type == e1000_ich8lan) { 1480 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1481 } else if (hw->mac.type == e1000_ich9lan) { 1482 pba = E1000_PBA_10K; 1483 } else if (hw->mac.type == e1000_ich10lan) { 1484 pba = E1000_PBA_10K; 1485 } else if (hw->mac.type == e1000_pchlan) { 1486 pba = E1000_PBA_26K; 1487 } else if (hw->mac.type == e1000_pch2lan) { 1488 pba = E1000_PBA_26K; 1489 } else if (hw->mac.type == e1000_pch_lpt) { 1490 pba = E1000_PBA_26K; 1491 } else if (hw->mac.type == e1000_pch_spt) { 1492 pba = E1000_PBA_26K; 1493 } else if (hw->mac.type == e1000_pch_cnp) { 1494 pba = E1000_PBA_26K; 1495 } else if (hw->mac.type == e1000_pch_tgp) { 1496 pba = E1000_PBA_26K; 1497 } else { 1498 /* 1499 * Total FIFO is 40K 1500 */ 1501 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1502 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1503 else 1504 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1505 } 1506 E1000_WRITE_REG(hw, E1000_PBA, pba); 1507 1508 /* 1509 * These parameters set thresholds for the adapter's generation(Tx) 1510 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1511 * settings. Flow control is enabled or disabled in the configuration 1512 * file. 1513 * High-water mark is set down from the top of the rx fifo (not 1514 * sensitive to max_frame_size) and low-water is set just below 1515 * high-water mark. 1516 * The high water mark must be low enough to fit one full frame above 1517 * it in the rx FIFO. Should be the lower of: 1518 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1519 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1520 * Rx FIFO size minus one full frame. 1521 */ 1522 high_water = min(((pba << 10) * 9 / 10), 1523 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 || 1524 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ? 1525 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1526 ((pba << 10) - Adapter->max_frame_size))); 1527 1528 hw->fc.high_water = high_water & 0xFFF8; 1529 hw->fc.low_water = hw->fc.high_water - 8; 1530 1531 if (hw->mac.type == e1000_80003es2lan) 1532 hw->fc.pause_time = 0xFFFF; 1533 else 1534 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1535 hw->fc.send_xon = B_TRUE; 1536 1537 /* 1538 * Reset the adapter hardware the second time. 1539 */ 1540 mutex_enter(&e1000g_nvm_lock); 1541 result = e1000_reset_hw(hw); 1542 mutex_exit(&e1000g_nvm_lock); 1543 1544 if (result != E1000_SUCCESS) { 1545 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1546 goto init_fail; 1547 } 1548 1549 /* disable wakeup control by default */ 1550 if (hw->mac.type >= e1000_82544) 1551 E1000_WRITE_REG(hw, E1000_WUC, 0); 1552 1553 /* 1554 * MWI should be disabled on 82546. 1555 */ 1556 if (hw->mac.type == e1000_82546) 1557 e1000_pci_clear_mwi(hw); 1558 else 1559 e1000_pci_set_mwi(hw); 1560 1561 /* 1562 * Configure/Initialize hardware 1563 */ 1564 mutex_enter(&e1000g_nvm_lock); 1565 result = e1000_init_hw(hw); 1566 mutex_exit(&e1000g_nvm_lock); 1567 1568 if (result < E1000_SUCCESS) { 1569 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1570 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1571 goto init_fail; 1572 } 1573 1574 /* 1575 * Restore LED settings to the default from EEPROM 1576 * to meet the standard for Sun platforms. 1577 */ 1578 (void) e1000_cleanup_led(hw); 1579 1580 /* Disable Smart Power Down */ 1581 phy_spd_state(hw, B_FALSE); 1582 1583 /* Make sure driver has control */ 1584 e1000g_get_driver_control(hw); 1585 1586 /* 1587 * Initialize unicast addresses. 1588 */ 1589 e1000g_init_unicst(Adapter); 1590 1591 /* 1592 * Setup and initialize the mctable structures. After this routine 1593 * completes Multicast table will be set 1594 */ 1595 e1000_update_mc_addr_list(hw, 1596 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 1597 msec_delay(5); 1598 1599 /* 1600 * Implement Adaptive IFS 1601 */ 1602 e1000_reset_adaptive(hw); 1603 1604 /* Setup Interrupt Throttling Register */ 1605 if (hw->mac.type >= e1000_82540) { 1606 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1607 } else 1608 Adapter->intr_adaptive = B_FALSE; 1609 1610 /* Start the timer for link setup */ 1611 if (hw->mac.autoneg) 1612 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1613 else 1614 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1615 1616 mutex_enter(&Adapter->link_lock); 1617 if (hw->phy.autoneg_wait_to_complete) { 1618 Adapter->link_complete = B_TRUE; 1619 } else { 1620 Adapter->link_complete = B_FALSE; 1621 Adapter->link_tid = timeout(e1000g_link_timer, 1622 (void *)Adapter, link_timeout); 1623 } 1624 mutex_exit(&Adapter->link_lock); 1625 1626 /* Save the state of the phy */ 1627 e1000g_get_phy_state(Adapter); 1628 1629 e1000g_param_sync(Adapter); 1630 1631 Adapter->init_count++; 1632 1633 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1634 goto init_fail; 1635 } 1636 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1637 goto init_fail; 1638 } 1639 1640 Adapter->poll_mode = e1000g_poll_mode; 1641 1642 return (DDI_SUCCESS); 1643 1644 init_fail: 1645 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1646 return (DDI_FAILURE); 1647 } 1648 1649 static int 1650 e1000g_alloc_rx_data(struct e1000g *Adapter) 1651 { 1652 e1000g_rx_ring_t *rx_ring; 1653 e1000g_rx_data_t *rx_data; 1654 1655 rx_ring = Adapter->rx_ring; 1656 1657 rx_data = kmem_zalloc(sizeof (e1000g_rx_data_t), KM_NOSLEEP); 1658 1659 if (rx_data == NULL) 1660 return (DDI_FAILURE); 1661 1662 rx_data->priv_devi_node = Adapter->priv_devi_node; 1663 rx_data->rx_ring = rx_ring; 1664 1665 mutex_init(&rx_data->freelist_lock, NULL, 1666 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1667 mutex_init(&rx_data->recycle_lock, NULL, 1668 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1669 1670 rx_ring->rx_data = rx_data; 1671 1672 return (DDI_SUCCESS); 1673 } 1674 1675 void 1676 e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data) 1677 { 1678 rx_sw_packet_t *packet, *next_packet; 1679 1680 if (rx_data == NULL) 1681 return; 1682 1683 packet = rx_data->packet_area; 1684 while (packet != NULL) { 1685 next_packet = packet->next; 1686 e1000g_free_rx_sw_packet(packet, B_TRUE); 1687 packet = next_packet; 1688 } 1689 rx_data->packet_area = NULL; 1690 } 1691 1692 void 1693 e1000g_free_rx_data(e1000g_rx_data_t *rx_data) 1694 { 1695 if (rx_data == NULL) 1696 return; 1697 1698 mutex_destroy(&rx_data->freelist_lock); 1699 mutex_destroy(&rx_data->recycle_lock); 1700 1701 kmem_free(rx_data, sizeof (e1000g_rx_data_t)); 1702 } 1703 1704 /* 1705 * Check if the link is up 1706 */ 1707 static boolean_t 1708 e1000g_link_up(struct e1000g *Adapter) 1709 { 1710 struct e1000_hw *hw = &Adapter->shared; 1711 boolean_t link_up = B_FALSE; 1712 1713 /* 1714 * get_link_status is set in the interrupt handler on link-status-change 1715 * or rx sequence error interrupt. get_link_status will stay 1716 * false until the e1000_check_for_link establishes link only 1717 * for copper adapters. 1718 */ 1719 switch (hw->phy.media_type) { 1720 case e1000_media_type_copper: 1721 if (hw->mac.get_link_status) { 1722 /* 1723 * SPT and newer devices need a bit of extra time before 1724 * we ask them. 1725 */ 1726 if (hw->mac.type >= e1000_pch_spt) 1727 msec_delay(50); 1728 (void) e1000_check_for_link(hw); 1729 if ((E1000_READ_REG(hw, E1000_STATUS) & 1730 E1000_STATUS_LU)) { 1731 link_up = B_TRUE; 1732 } else { 1733 link_up = !hw->mac.get_link_status; 1734 } 1735 } else { 1736 link_up = B_TRUE; 1737 } 1738 break; 1739 case e1000_media_type_fiber: 1740 (void) e1000_check_for_link(hw); 1741 link_up = (E1000_READ_REG(hw, E1000_STATUS) & 1742 E1000_STATUS_LU); 1743 break; 1744 case e1000_media_type_internal_serdes: 1745 (void) e1000_check_for_link(hw); 1746 link_up = hw->mac.serdes_has_link; 1747 break; 1748 } 1749 1750 return (link_up); 1751 } 1752 1753 static void 1754 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1755 { 1756 struct iocblk *iocp; 1757 struct e1000g *e1000gp; 1758 enum ioc_reply status; 1759 1760 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1761 iocp->ioc_error = 0; 1762 e1000gp = (struct e1000g *)arg; 1763 1764 ASSERT(e1000gp); 1765 if (e1000gp == NULL) { 1766 miocnak(q, mp, 0, EINVAL); 1767 return; 1768 } 1769 1770 rw_enter(&e1000gp->chip_lock, RW_READER); 1771 if (e1000gp->e1000g_state & E1000G_SUSPENDED) { 1772 rw_exit(&e1000gp->chip_lock); 1773 miocnak(q, mp, 0, EINVAL); 1774 return; 1775 } 1776 rw_exit(&e1000gp->chip_lock); 1777 1778 switch (iocp->ioc_cmd) { 1779 1780 case LB_GET_INFO_SIZE: 1781 case LB_GET_INFO: 1782 case LB_GET_MODE: 1783 case LB_SET_MODE: 1784 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1785 break; 1786 1787 1788 #ifdef E1000G_DEBUG 1789 case E1000G_IOC_REG_PEEK: 1790 case E1000G_IOC_REG_POKE: 1791 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1792 break; 1793 case E1000G_IOC_CHIP_RESET: 1794 e1000gp->reset_count++; 1795 if (e1000g_reset_adapter(e1000gp)) 1796 status = IOC_ACK; 1797 else 1798 status = IOC_INVAL; 1799 break; 1800 #endif 1801 default: 1802 status = IOC_INVAL; 1803 break; 1804 } 1805 1806 /* 1807 * Decide how to reply 1808 */ 1809 switch (status) { 1810 default: 1811 case IOC_INVAL: 1812 /* 1813 * Error, reply with a NAK and EINVAL or the specified error 1814 */ 1815 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1816 EINVAL : iocp->ioc_error); 1817 break; 1818 1819 case IOC_DONE: 1820 /* 1821 * OK, reply already sent 1822 */ 1823 break; 1824 1825 case IOC_ACK: 1826 /* 1827 * OK, reply with an ACK 1828 */ 1829 miocack(q, mp, 0, 0); 1830 break; 1831 1832 case IOC_REPLY: 1833 /* 1834 * OK, send prepared reply as ACK or NAK 1835 */ 1836 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1837 M_IOCACK : M_IOCNAK; 1838 qreply(q, mp); 1839 break; 1840 } 1841 } 1842 1843 /* 1844 * The default value of e1000g_poll_mode == 0 assumes that the NIC is 1845 * capable of supporting only one interrupt and we shouldn't disable 1846 * the physical interrupt. In this case we let the interrupt come and 1847 * we queue the packets in the rx ring itself in case we are in polling 1848 * mode (better latency but slightly lower performance and a very 1849 * high intrrupt count in mpstat which is harmless). 1850 * 1851 * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt 1852 * which can be disabled in poll mode. This gives better overall 1853 * throughput (compared to the mode above), shows very low interrupt 1854 * count but has slightly higher latency since we pick the packets when 1855 * the poll thread does polling. 1856 * 1857 * Currently, this flag should be enabled only while doing performance 1858 * measurement or when it can be guaranteed that entire NIC going 1859 * in poll mode will not harm any traffic like cluster heartbeat etc. 1860 */ 1861 int e1000g_poll_mode = 0; 1862 1863 /* 1864 * Called from the upper layers when driver is in polling mode to 1865 * pick up any queued packets. Care should be taken to not block 1866 * this thread. 1867 */ 1868 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup) 1869 { 1870 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)arg; 1871 mblk_t *mp = NULL; 1872 mblk_t *tail; 1873 struct e1000g *adapter; 1874 1875 adapter = rx_ring->adapter; 1876 1877 rw_enter(&adapter->chip_lock, RW_READER); 1878 1879 if (adapter->e1000g_state & E1000G_SUSPENDED) { 1880 rw_exit(&adapter->chip_lock); 1881 return (NULL); 1882 } 1883 1884 mutex_enter(&rx_ring->rx_lock); 1885 mp = e1000g_receive(rx_ring, &tail, bytes_to_pickup); 1886 mutex_exit(&rx_ring->rx_lock); 1887 rw_exit(&adapter->chip_lock); 1888 return (mp); 1889 } 1890 1891 static int 1892 e1000g_m_start(void *arg) 1893 { 1894 struct e1000g *Adapter = (struct e1000g *)arg; 1895 1896 rw_enter(&Adapter->chip_lock, RW_WRITER); 1897 1898 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1899 rw_exit(&Adapter->chip_lock); 1900 return (ECANCELED); 1901 } 1902 1903 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1904 rw_exit(&Adapter->chip_lock); 1905 return (ENOTACTIVE); 1906 } 1907 1908 Adapter->e1000g_state |= E1000G_STARTED; 1909 1910 rw_exit(&Adapter->chip_lock); 1911 1912 /* Enable and start the watchdog timer */ 1913 enable_watchdog_timer(Adapter); 1914 1915 return (0); 1916 } 1917 1918 static int 1919 e1000g_start(struct e1000g *Adapter, boolean_t global) 1920 { 1921 e1000g_rx_data_t *rx_data; 1922 1923 if (global) { 1924 if (e1000g_alloc_rx_data(Adapter) != DDI_SUCCESS) { 1925 e1000g_log(Adapter, CE_WARN, "Allocate rx data failed"); 1926 goto start_fail; 1927 } 1928 1929 /* Allocate dma resources for descriptors and buffers */ 1930 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1931 e1000g_log(Adapter, CE_WARN, 1932 "Alloc DMA resources failed"); 1933 goto start_fail; 1934 } 1935 Adapter->rx_buffer_setup = B_FALSE; 1936 } 1937 1938 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1939 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1940 e1000g_log(Adapter, CE_WARN, 1941 "Adapter initialization failed"); 1942 goto start_fail; 1943 } 1944 } 1945 1946 /* Setup and initialize the transmit structures */ 1947 e1000g_tx_setup(Adapter); 1948 msec_delay(5); 1949 1950 /* Setup and initialize the receive structures */ 1951 e1000g_rx_setup(Adapter); 1952 msec_delay(5); 1953 1954 /* Restore the e1000g promiscuous mode */ 1955 e1000g_restore_promisc(Adapter); 1956 1957 e1000g_mask_interrupt(Adapter); 1958 1959 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1960 1961 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1962 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1963 goto start_fail; 1964 } 1965 1966 return (DDI_SUCCESS); 1967 1968 start_fail: 1969 rx_data = Adapter->rx_ring->rx_data; 1970 1971 if (global) { 1972 e1000g_release_dma_resources(Adapter); 1973 e1000g_free_rx_pending_buffers(rx_data); 1974 e1000g_free_rx_data(rx_data); 1975 } 1976 1977 mutex_enter(&e1000g_nvm_lock); 1978 (void) e1000_reset_hw(&Adapter->shared); 1979 mutex_exit(&e1000g_nvm_lock); 1980 1981 return (DDI_FAILURE); 1982 } 1983 1984 /* 1985 * The I219 has the curious property that if the descriptor rings are not 1986 * emptied before resetting the hardware or before changing the device state 1987 * based on runtime power management, it'll cause the card to hang. This can 1988 * then only be fixed by a PCI reset. As such, for the I219 and it alone, we 1989 * have to flush the rings if we're in this state. 1990 */ 1991 static void 1992 e1000g_flush_desc_rings(struct e1000g *Adapter) 1993 { 1994 struct e1000_hw *hw = &Adapter->shared; 1995 u16 hang_state; 1996 u32 fext_nvm11, tdlen; 1997 1998 /* First, disable MULR fix in FEXTNVM11 */ 1999 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 2000 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 2001 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 2002 2003 /* do nothing if we're not in faulty state, or if the queue is empty */ 2004 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 2005 hang_state = pci_config_get16(Adapter->osdep.cfg_handle, 2006 PCICFG_DESC_RING_STATUS); 2007 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 2008 return; 2009 e1000g_flush_tx_ring(Adapter); 2010 2011 /* recheck, maybe the fault is caused by the rx ring */ 2012 hang_state = pci_config_get16(Adapter->osdep.cfg_handle, 2013 PCICFG_DESC_RING_STATUS); 2014 if (hang_state & FLUSH_DESC_REQUIRED) 2015 e1000g_flush_rx_ring(Adapter); 2016 2017 } 2018 2019 static void 2020 e1000g_m_stop(void *arg) 2021 { 2022 struct e1000g *Adapter = (struct e1000g *)arg; 2023 2024 /* Drain tx sessions */ 2025 (void) e1000g_tx_drain(Adapter); 2026 2027 rw_enter(&Adapter->chip_lock, RW_WRITER); 2028 2029 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2030 rw_exit(&Adapter->chip_lock); 2031 return; 2032 } 2033 Adapter->e1000g_state &= ~E1000G_STARTED; 2034 e1000g_stop(Adapter, B_TRUE); 2035 2036 rw_exit(&Adapter->chip_lock); 2037 2038 /* Disable and stop all the timers */ 2039 disable_watchdog_timer(Adapter); 2040 stop_link_timer(Adapter); 2041 stop_82547_timer(Adapter->tx_ring); 2042 } 2043 2044 static void 2045 e1000g_stop(struct e1000g *Adapter, boolean_t global) 2046 { 2047 private_devi_list_t *devi_node; 2048 e1000g_rx_data_t *rx_data; 2049 int result; 2050 2051 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 2052 2053 /* Stop the chip and release pending resources */ 2054 2055 /* Tell firmware driver is no longer in control */ 2056 e1000g_release_driver_control(&Adapter->shared); 2057 2058 e1000g_clear_all_interrupts(Adapter); 2059 2060 mutex_enter(&e1000g_nvm_lock); 2061 result = e1000_reset_hw(&Adapter->shared); 2062 mutex_exit(&e1000g_nvm_lock); 2063 2064 if (result != E1000_SUCCESS) { 2065 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 2066 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 2067 } 2068 2069 mutex_enter(&Adapter->link_lock); 2070 Adapter->link_complete = B_FALSE; 2071 mutex_exit(&Adapter->link_lock); 2072 2073 /* Release resources still held by the TX descriptors */ 2074 e1000g_tx_clean(Adapter); 2075 2076 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2077 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 2078 2079 /* Clean the pending rx jumbo packet fragment */ 2080 e1000g_rx_clean(Adapter); 2081 2082 /* 2083 * The I219, eg. the pch_spt, has bugs such that we must ensure that 2084 * rings are flushed before we do anything else. This must be done 2085 * before we release DMA resources. 2086 */ 2087 if (Adapter->shared.mac.type >= e1000_pch_spt) 2088 e1000g_flush_desc_rings(Adapter); 2089 2090 if (global) { 2091 e1000g_release_dma_resources(Adapter); 2092 2093 mutex_enter(&e1000g_rx_detach_lock); 2094 rx_data = Adapter->rx_ring->rx_data; 2095 rx_data->flag |= E1000G_RX_STOPPED; 2096 2097 if (rx_data->pending_count == 0) { 2098 e1000g_free_rx_pending_buffers(rx_data); 2099 e1000g_free_rx_data(rx_data); 2100 } else { 2101 devi_node = rx_data->priv_devi_node; 2102 if (devi_node != NULL) 2103 atomic_inc_32(&devi_node->pending_rx_count); 2104 else 2105 atomic_inc_32(&Adapter->pending_rx_count); 2106 } 2107 mutex_exit(&e1000g_rx_detach_lock); 2108 } 2109 2110 if (Adapter->link_state != LINK_STATE_UNKNOWN) { 2111 Adapter->link_state = LINK_STATE_UNKNOWN; 2112 if (!Adapter->reset_flag) 2113 mac_link_update(Adapter->mh, Adapter->link_state); 2114 } 2115 } 2116 2117 static void 2118 e1000g_rx_clean(struct e1000g *Adapter) 2119 { 2120 e1000g_rx_data_t *rx_data = Adapter->rx_ring->rx_data; 2121 2122 if (rx_data == NULL) 2123 return; 2124 2125 if (rx_data->rx_mblk != NULL) { 2126 freemsg(rx_data->rx_mblk); 2127 rx_data->rx_mblk = NULL; 2128 rx_data->rx_mblk_tail = NULL; 2129 rx_data->rx_mblk_len = 0; 2130 } 2131 } 2132 2133 static void 2134 e1000g_tx_clean(struct e1000g *Adapter) 2135 { 2136 e1000g_tx_ring_t *tx_ring; 2137 p_tx_sw_packet_t packet; 2138 mblk_t *mp; 2139 mblk_t *nmp; 2140 uint32_t packet_count; 2141 2142 tx_ring = Adapter->tx_ring; 2143 2144 /* 2145 * Here we don't need to protect the lists using 2146 * the usedlist_lock and freelist_lock, for they 2147 * have been protected by the chip_lock. 2148 */ 2149 mp = NULL; 2150 nmp = NULL; 2151 packet_count = 0; 2152 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 2153 while (packet != NULL) { 2154 if (packet->mp != NULL) { 2155 /* Assemble the message chain */ 2156 if (mp == NULL) { 2157 mp = packet->mp; 2158 nmp = packet->mp; 2159 } else { 2160 nmp->b_next = packet->mp; 2161 nmp = packet->mp; 2162 } 2163 /* Disconnect the message from the sw packet */ 2164 packet->mp = NULL; 2165 } 2166 2167 e1000g_free_tx_swpkt(packet); 2168 packet_count++; 2169 2170 packet = (p_tx_sw_packet_t) 2171 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 2172 } 2173 2174 if (mp != NULL) 2175 freemsgchain(mp); 2176 2177 if (packet_count > 0) { 2178 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 2179 QUEUE_INIT_LIST(&tx_ring->used_list); 2180 2181 /* Setup TX descriptor pointers */ 2182 tx_ring->tbd_next = tx_ring->tbd_first; 2183 tx_ring->tbd_oldest = tx_ring->tbd_first; 2184 2185 /* Setup our HW Tx Head & Tail descriptor pointers */ 2186 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 2187 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 2188 } 2189 } 2190 2191 static boolean_t 2192 e1000g_tx_drain(struct e1000g *Adapter) 2193 { 2194 int i; 2195 boolean_t done; 2196 e1000g_tx_ring_t *tx_ring; 2197 2198 tx_ring = Adapter->tx_ring; 2199 2200 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 2201 for (i = 0; i < TX_DRAIN_TIME; i++) { 2202 mutex_enter(&tx_ring->usedlist_lock); 2203 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 2204 mutex_exit(&tx_ring->usedlist_lock); 2205 2206 if (done) 2207 break; 2208 2209 msec_delay(1); 2210 } 2211 2212 return (done); 2213 } 2214 2215 static boolean_t 2216 e1000g_rx_drain(struct e1000g *Adapter) 2217 { 2218 int i; 2219 boolean_t done; 2220 2221 /* 2222 * Allow up to RX_DRAIN_TIME for pending received packets to complete. 2223 */ 2224 for (i = 0; i < RX_DRAIN_TIME; i++) { 2225 done = (Adapter->pending_rx_count == 0); 2226 2227 if (done) 2228 break; 2229 2230 msec_delay(1); 2231 } 2232 2233 return (done); 2234 } 2235 2236 static boolean_t 2237 e1000g_reset_adapter(struct e1000g *Adapter) 2238 { 2239 /* Disable and stop all the timers */ 2240 disable_watchdog_timer(Adapter); 2241 stop_link_timer(Adapter); 2242 stop_82547_timer(Adapter->tx_ring); 2243 2244 rw_enter(&Adapter->chip_lock, RW_WRITER); 2245 2246 if (Adapter->stall_flag) { 2247 Adapter->stall_flag = B_FALSE; 2248 Adapter->reset_flag = B_TRUE; 2249 } 2250 2251 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2252 rw_exit(&Adapter->chip_lock); 2253 return (B_TRUE); 2254 } 2255 2256 e1000g_stop(Adapter, B_FALSE); 2257 2258 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 2259 rw_exit(&Adapter->chip_lock); 2260 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2261 return (B_FALSE); 2262 } 2263 2264 rw_exit(&Adapter->chip_lock); 2265 2266 /* Enable and start the watchdog timer */ 2267 enable_watchdog_timer(Adapter); 2268 2269 return (B_TRUE); 2270 } 2271 2272 boolean_t 2273 e1000g_global_reset(struct e1000g *Adapter) 2274 { 2275 /* Disable and stop all the timers */ 2276 disable_watchdog_timer(Adapter); 2277 stop_link_timer(Adapter); 2278 stop_82547_timer(Adapter->tx_ring); 2279 2280 rw_enter(&Adapter->chip_lock, RW_WRITER); 2281 2282 e1000g_stop(Adapter, B_TRUE); 2283 2284 Adapter->init_count = 0; 2285 2286 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 2287 rw_exit(&Adapter->chip_lock); 2288 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2289 return (B_FALSE); 2290 } 2291 2292 rw_exit(&Adapter->chip_lock); 2293 2294 /* Enable and start the watchdog timer */ 2295 enable_watchdog_timer(Adapter); 2296 2297 return (B_TRUE); 2298 } 2299 2300 /* 2301 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 2302 * 2303 * This interrupt service routine is for PCI-Express adapters. 2304 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 2305 * bit is set. 2306 */ 2307 static uint_t 2308 e1000g_intr_pciexpress(caddr_t arg, caddr_t arg1 __unused) 2309 { 2310 struct e1000g *Adapter; 2311 uint32_t icr; 2312 2313 Adapter = (struct e1000g *)(uintptr_t)arg; 2314 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2315 2316 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2317 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2318 return (DDI_INTR_CLAIMED); 2319 } 2320 2321 if (icr & E1000_ICR_INT_ASSERTED) { 2322 /* 2323 * E1000_ICR_INT_ASSERTED bit was set: 2324 * Read(Clear) the ICR, claim this interrupt, 2325 * look for work to do. 2326 */ 2327 e1000g_intr_work(Adapter, icr); 2328 return (DDI_INTR_CLAIMED); 2329 } else { 2330 /* 2331 * E1000_ICR_INT_ASSERTED bit was not set: 2332 * Don't claim this interrupt, return immediately. 2333 */ 2334 return (DDI_INTR_UNCLAIMED); 2335 } 2336 } 2337 2338 /* 2339 * e1000g_intr - ISR for PCI/PCI-X chipsets 2340 * 2341 * This interrupt service routine is for PCI/PCI-X adapters. 2342 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 2343 * bit is set or not. 2344 */ 2345 static uint_t 2346 e1000g_intr(caddr_t arg, caddr_t arg1 __unused) 2347 { 2348 struct e1000g *Adapter; 2349 uint32_t icr; 2350 2351 Adapter = (struct e1000g *)(uintptr_t)arg; 2352 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2353 2354 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2355 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2356 return (DDI_INTR_CLAIMED); 2357 } 2358 2359 if (icr) { 2360 /* 2361 * Any bit was set in ICR: 2362 * Read(Clear) the ICR, claim this interrupt, 2363 * look for work to do. 2364 */ 2365 e1000g_intr_work(Adapter, icr); 2366 return (DDI_INTR_CLAIMED); 2367 } else { 2368 /* 2369 * No bit was set in ICR: 2370 * Don't claim this interrupt, return immediately. 2371 */ 2372 return (DDI_INTR_UNCLAIMED); 2373 } 2374 } 2375 2376 /* 2377 * e1000g_intr_work - actual processing of ISR 2378 * 2379 * Read(clear) the ICR contents and call appropriate interrupt 2380 * processing routines. 2381 */ 2382 static void 2383 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 2384 { 2385 struct e1000_hw *hw; 2386 hw = &Adapter->shared; 2387 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2388 2389 Adapter->rx_pkt_cnt = 0; 2390 Adapter->tx_pkt_cnt = 0; 2391 2392 rw_enter(&Adapter->chip_lock, RW_READER); 2393 2394 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2395 rw_exit(&Adapter->chip_lock); 2396 return; 2397 } 2398 /* 2399 * Here we need to check the "e1000g_state" flag within the chip_lock to 2400 * ensure the receive routine will not execute when the adapter is 2401 * being reset. 2402 */ 2403 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2404 rw_exit(&Adapter->chip_lock); 2405 return; 2406 } 2407 2408 if (icr & E1000_ICR_RXT0) { 2409 mblk_t *mp = NULL; 2410 mblk_t *tail = NULL; 2411 e1000g_rx_ring_t *rx_ring; 2412 2413 rx_ring = Adapter->rx_ring; 2414 mutex_enter(&rx_ring->rx_lock); 2415 /* 2416 * Sometimes with legacy interrupts, it possible that 2417 * there is a single interrupt for Rx/Tx. In which 2418 * case, if poll flag is set, we shouldn't really 2419 * be doing Rx processing. 2420 */ 2421 if (!rx_ring->poll_flag) 2422 mp = e1000g_receive(rx_ring, &tail, 2423 E1000G_CHAIN_NO_LIMIT); 2424 mutex_exit(&rx_ring->rx_lock); 2425 rw_exit(&Adapter->chip_lock); 2426 if (mp != NULL) 2427 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2428 mp, rx_ring->ring_gen_num); 2429 } else 2430 rw_exit(&Adapter->chip_lock); 2431 2432 if (icr & E1000_ICR_TXDW) { 2433 if (!Adapter->tx_intr_enable) 2434 e1000g_clear_tx_interrupt(Adapter); 2435 2436 /* Recycle the tx descriptors */ 2437 rw_enter(&Adapter->chip_lock, RW_READER); 2438 (void) e1000g_recycle(tx_ring); 2439 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 2440 rw_exit(&Adapter->chip_lock); 2441 2442 if (tx_ring->resched_needed && 2443 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 2444 tx_ring->resched_needed = B_FALSE; 2445 mac_tx_update(Adapter->mh); 2446 E1000G_STAT(tx_ring->stat_reschedule); 2447 } 2448 } 2449 2450 /* 2451 * The Receive Sequence errors RXSEQ and the link status change LSC 2452 * are checked to detect that the cable has been pulled out. For 2453 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 2454 * are an indication that cable is not connected. 2455 */ 2456 if ((icr & E1000_ICR_RXSEQ) || 2457 (icr & E1000_ICR_LSC) || 2458 (icr & E1000_ICR_GPI_EN1)) { 2459 boolean_t link_changed; 2460 timeout_id_t tid = 0; 2461 2462 stop_watchdog_timer(Adapter); 2463 2464 rw_enter(&Adapter->chip_lock, RW_WRITER); 2465 2466 /* 2467 * Because we got a link-status-change interrupt, force 2468 * e1000_check_for_link() to look at phy 2469 */ 2470 Adapter->shared.mac.get_link_status = B_TRUE; 2471 2472 /* e1000g_link_check takes care of link status change */ 2473 link_changed = e1000g_link_check(Adapter); 2474 2475 /* Get new phy state */ 2476 e1000g_get_phy_state(Adapter); 2477 2478 /* 2479 * If the link timer has not timed out, we'll not notify 2480 * the upper layer with any link state until the link is up. 2481 */ 2482 if (link_changed && !Adapter->link_complete) { 2483 if (Adapter->link_state == LINK_STATE_UP) { 2484 mutex_enter(&Adapter->link_lock); 2485 Adapter->link_complete = B_TRUE; 2486 tid = Adapter->link_tid; 2487 Adapter->link_tid = 0; 2488 mutex_exit(&Adapter->link_lock); 2489 } else { 2490 link_changed = B_FALSE; 2491 } 2492 } 2493 rw_exit(&Adapter->chip_lock); 2494 2495 if (link_changed) { 2496 if (tid != 0) 2497 (void) untimeout(tid); 2498 2499 /* 2500 * Workaround for esb2. Data stuck in fifo on a link 2501 * down event. Stop receiver here and reset in watchdog. 2502 */ 2503 if ((Adapter->link_state == LINK_STATE_DOWN) && 2504 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2505 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2506 E1000_WRITE_REG(hw, E1000_RCTL, 2507 rctl & ~E1000_RCTL_EN); 2508 e1000g_log(Adapter, CE_WARN, 2509 "ESB2 receiver disabled"); 2510 Adapter->esb2_workaround = B_TRUE; 2511 } 2512 if (!Adapter->reset_flag) 2513 mac_link_update(Adapter->mh, 2514 Adapter->link_state); 2515 if (Adapter->link_state == LINK_STATE_UP) 2516 Adapter->reset_flag = B_FALSE; 2517 } 2518 2519 start_watchdog_timer(Adapter); 2520 } 2521 } 2522 2523 static void 2524 e1000g_init_unicst(struct e1000g *Adapter) 2525 { 2526 struct e1000_hw *hw; 2527 int slot; 2528 2529 hw = &Adapter->shared; 2530 2531 if (Adapter->init_count == 0) { 2532 /* Initialize the multiple unicast addresses */ 2533 Adapter->unicst_total = min(hw->mac.rar_entry_count, 2534 MAX_NUM_UNICAST_ADDRESSES); 2535 2536 /* 2537 * The common code does not correctly calculate the number of 2538 * rar's that could be reserved by firmware for the pch_lpt and 2539 * pch_spt macs. The interface has one primary rar, and 11 2540 * additional ones. Those 11 additional ones are not always 2541 * available. According to the datasheet, we need to check a 2542 * few of the bits set in the FWSM register. If the value is 2543 * zero, everything is available. If the value is 1, none of the 2544 * additional registers are available. If the value is 2-7, only 2545 * that number are available. 2546 */ 2547 if (hw->mac.type >= e1000_pch_lpt) { 2548 uint32_t locked, rar; 2549 2550 locked = E1000_READ_REG(hw, E1000_FWSM) & 2551 E1000_FWSM_WLOCK_MAC_MASK; 2552 locked >>= E1000_FWSM_WLOCK_MAC_SHIFT; 2553 rar = 1; 2554 if (locked == 0) 2555 rar += 11; 2556 else if (locked == 1) 2557 rar += 0; 2558 else 2559 rar += locked; 2560 Adapter->unicst_total = min(rar, 2561 MAX_NUM_UNICAST_ADDRESSES); 2562 } 2563 2564 /* Workaround for an erratum of 82571 chipst */ 2565 if ((hw->mac.type == e1000_82571) && 2566 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2567 Adapter->unicst_total--; 2568 2569 /* VMware doesn't support multiple mac addresses properly */ 2570 if (hw->subsystem_vendor_id == 0x15ad) 2571 Adapter->unicst_total = 1; 2572 2573 Adapter->unicst_avail = Adapter->unicst_total; 2574 2575 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2576 /* Clear both the flag and MAC address */ 2577 Adapter->unicst_addr[slot].reg.high = 0; 2578 Adapter->unicst_addr[slot].reg.low = 0; 2579 } 2580 } else { 2581 /* Workaround for an erratum of 82571 chipst */ 2582 if ((hw->mac.type == e1000_82571) && 2583 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2584 (void) e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2585 2586 /* Re-configure the RAR registers */ 2587 for (slot = 0; slot < Adapter->unicst_total; slot++) 2588 if (Adapter->unicst_addr[slot].mac.set == 1) 2589 (void) e1000_rar_set(hw, 2590 Adapter->unicst_addr[slot].mac.addr, slot); 2591 } 2592 2593 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2594 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2595 } 2596 2597 static int 2598 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2599 int slot) 2600 { 2601 struct e1000_hw *hw; 2602 2603 hw = &Adapter->shared; 2604 2605 /* 2606 * The first revision of Wiseman silicon (rev 2.0) has an errata 2607 * that requires the receiver to be in reset when any of the 2608 * receive address registers (RAR regs) are accessed. The first 2609 * rev of Wiseman silicon also requires MWI to be disabled when 2610 * a global reset or a receive reset is issued. So before we 2611 * initialize the RARs, we check the rev of the Wiseman controller 2612 * and work around any necessary HW errata. 2613 */ 2614 if ((hw->mac.type == e1000_82542) && 2615 (hw->revision_id == E1000_REVISION_2)) { 2616 e1000_pci_clear_mwi(hw); 2617 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2618 msec_delay(5); 2619 } 2620 if (mac_addr == NULL) { 2621 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0); 2622 E1000_WRITE_FLUSH(hw); 2623 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0); 2624 E1000_WRITE_FLUSH(hw); 2625 /* Clear both the flag and MAC address */ 2626 Adapter->unicst_addr[slot].reg.high = 0; 2627 Adapter->unicst_addr[slot].reg.low = 0; 2628 } else { 2629 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, 2630 ETHERADDRL); 2631 (void) e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2632 Adapter->unicst_addr[slot].mac.set = 1; 2633 } 2634 2635 /* Workaround for an erratum of 82571 chipst */ 2636 if (slot == 0) { 2637 if ((hw->mac.type == e1000_82571) && 2638 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2639 if (mac_addr == NULL) { 2640 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2641 slot << 1, 0); 2642 E1000_WRITE_FLUSH(hw); 2643 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2644 (slot << 1) + 1, 0); 2645 E1000_WRITE_FLUSH(hw); 2646 } else { 2647 (void) e1000_rar_set(hw, (uint8_t *)mac_addr, 2648 LAST_RAR_ENTRY); 2649 } 2650 } 2651 2652 /* 2653 * If we are using Wiseman rev 2.0 silicon, we will have previously 2654 * put the receive in reset, and disabled MWI, to work around some 2655 * HW errata. Now we should take the receiver out of reset, and 2656 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2657 */ 2658 if ((hw->mac.type == e1000_82542) && 2659 (hw->revision_id == E1000_REVISION_2)) { 2660 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2661 msec_delay(1); 2662 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2663 e1000_pci_set_mwi(hw); 2664 e1000g_rx_setup(Adapter); 2665 } 2666 2667 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2668 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2669 return (EIO); 2670 } 2671 2672 return (0); 2673 } 2674 2675 static int 2676 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2677 { 2678 struct e1000_hw *hw = &Adapter->shared; 2679 struct ether_addr *newtable; 2680 size_t new_len; 2681 size_t old_len; 2682 int res = 0; 2683 2684 if ((multiaddr[0] & 01) == 0) { 2685 res = EINVAL; 2686 e1000g_log(Adapter, CE_WARN, "Illegal multicast address"); 2687 goto done; 2688 } 2689 2690 if (Adapter->mcast_count >= Adapter->mcast_max_num) { 2691 res = ENOENT; 2692 e1000g_log(Adapter, CE_WARN, 2693 "Adapter requested more than %d mcast addresses", 2694 Adapter->mcast_max_num); 2695 goto done; 2696 } 2697 2698 2699 if (Adapter->mcast_count == Adapter->mcast_alloc_count) { 2700 old_len = Adapter->mcast_alloc_count * 2701 sizeof (struct ether_addr); 2702 new_len = (Adapter->mcast_alloc_count + MCAST_ALLOC_SIZE) * 2703 sizeof (struct ether_addr); 2704 2705 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2706 if (newtable == NULL) { 2707 res = ENOMEM; 2708 e1000g_log(Adapter, CE_WARN, 2709 "Not enough memory to alloc mcast table"); 2710 goto done; 2711 } 2712 2713 if (Adapter->mcast_table != NULL) { 2714 bcopy(Adapter->mcast_table, newtable, old_len); 2715 kmem_free(Adapter->mcast_table, old_len); 2716 } 2717 Adapter->mcast_alloc_count += MCAST_ALLOC_SIZE; 2718 Adapter->mcast_table = newtable; 2719 } 2720 2721 bcopy(multiaddr, 2722 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2723 Adapter->mcast_count++; 2724 2725 /* 2726 * Update the MC table in the hardware 2727 */ 2728 e1000g_clear_interrupt(Adapter); 2729 2730 e1000_update_mc_addr_list(hw, 2731 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2732 2733 e1000g_mask_interrupt(Adapter); 2734 2735 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2736 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2737 res = EIO; 2738 } 2739 2740 done: 2741 return (res); 2742 } 2743 2744 static int 2745 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2746 { 2747 struct e1000_hw *hw = &Adapter->shared; 2748 struct ether_addr *newtable; 2749 size_t new_len; 2750 size_t old_len; 2751 unsigned i; 2752 2753 for (i = 0; i < Adapter->mcast_count; i++) { 2754 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2755 ETHERADDRL) == 0) { 2756 for (i++; i < Adapter->mcast_count; i++) { 2757 Adapter->mcast_table[i - 1] = 2758 Adapter->mcast_table[i]; 2759 } 2760 Adapter->mcast_count--; 2761 break; 2762 } 2763 } 2764 2765 if ((Adapter->mcast_alloc_count - Adapter->mcast_count) > 2766 MCAST_ALLOC_SIZE) { 2767 old_len = Adapter->mcast_alloc_count * 2768 sizeof (struct ether_addr); 2769 new_len = (Adapter->mcast_alloc_count - MCAST_ALLOC_SIZE) * 2770 sizeof (struct ether_addr); 2771 2772 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2773 if (newtable != NULL) { 2774 bcopy(Adapter->mcast_table, newtable, new_len); 2775 kmem_free(Adapter->mcast_table, old_len); 2776 2777 Adapter->mcast_alloc_count -= MCAST_ALLOC_SIZE; 2778 Adapter->mcast_table = newtable; 2779 } 2780 } 2781 2782 /* 2783 * Update the MC table in the hardware 2784 */ 2785 e1000g_clear_interrupt(Adapter); 2786 2787 e1000_update_mc_addr_list(hw, 2788 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2789 2790 e1000g_mask_interrupt(Adapter); 2791 2792 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2793 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2794 return (EIO); 2795 } 2796 2797 return (0); 2798 } 2799 2800 static void 2801 e1000g_release_multicast(struct e1000g *Adapter) 2802 { 2803 if (Adapter->mcast_table != NULL) { 2804 kmem_free(Adapter->mcast_table, 2805 Adapter->mcast_alloc_count * sizeof (struct ether_addr)); 2806 Adapter->mcast_table = NULL; 2807 } 2808 } 2809 2810 int 2811 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2812 { 2813 struct e1000g *Adapter = (struct e1000g *)arg; 2814 int result; 2815 2816 rw_enter(&Adapter->chip_lock, RW_WRITER); 2817 2818 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2819 result = ECANCELED; 2820 goto done; 2821 } 2822 2823 result = (add) ? multicst_add(Adapter, addr) 2824 : multicst_remove(Adapter, addr); 2825 2826 done: 2827 rw_exit(&Adapter->chip_lock); 2828 return (result); 2829 2830 } 2831 2832 int 2833 e1000g_m_promisc(void *arg, boolean_t on) 2834 { 2835 struct e1000g *Adapter = (struct e1000g *)arg; 2836 uint32_t rctl; 2837 2838 rw_enter(&Adapter->chip_lock, RW_WRITER); 2839 2840 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2841 rw_exit(&Adapter->chip_lock); 2842 return (ECANCELED); 2843 } 2844 2845 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2846 2847 if (on) 2848 rctl |= 2849 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2850 else 2851 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2852 2853 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2854 2855 Adapter->e1000g_promisc = on; 2856 2857 rw_exit(&Adapter->chip_lock); 2858 2859 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2860 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2861 return (EIO); 2862 } 2863 2864 return (0); 2865 } 2866 2867 /* 2868 * Entry points to enable and disable interrupts at the granularity of 2869 * a group. 2870 * Turns the poll_mode for the whole adapter on and off to enable or 2871 * override the ring level polling control over the hardware interrupts. 2872 */ 2873 static int 2874 e1000g_rx_group_intr_enable(mac_intr_handle_t arg) 2875 { 2876 struct e1000g *adapter = (struct e1000g *)arg; 2877 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2878 2879 /* 2880 * Later interrupts at the granularity of the this ring will 2881 * invoke mac_rx() with NULL, indicating the need for another 2882 * software classification. 2883 * We have a single ring usable per adapter now, so we only need to 2884 * reset the rx handle for that one. 2885 * When more RX rings can be used, we should update each one of them. 2886 */ 2887 mutex_enter(&rx_ring->rx_lock); 2888 rx_ring->mrh = NULL; 2889 adapter->poll_mode = B_FALSE; 2890 mutex_exit(&rx_ring->rx_lock); 2891 return (0); 2892 } 2893 2894 static int 2895 e1000g_rx_group_intr_disable(mac_intr_handle_t arg) 2896 { 2897 struct e1000g *adapter = (struct e1000g *)arg; 2898 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2899 2900 mutex_enter(&rx_ring->rx_lock); 2901 2902 /* 2903 * Later interrupts at the granularity of the this ring will 2904 * invoke mac_rx() with the handle for this ring; 2905 */ 2906 adapter->poll_mode = B_TRUE; 2907 rx_ring->mrh = rx_ring->mrh_init; 2908 mutex_exit(&rx_ring->rx_lock); 2909 return (0); 2910 } 2911 2912 /* 2913 * Entry points to enable and disable interrupts at the granularity of 2914 * a ring. 2915 * adapter poll_mode controls whether we actually proceed with hardware 2916 * interrupt toggling. 2917 */ 2918 static int 2919 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh) 2920 { 2921 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2922 struct e1000g *adapter = rx_ring->adapter; 2923 struct e1000_hw *hw = &adapter->shared; 2924 uint32_t intr_mask; 2925 2926 rw_enter(&adapter->chip_lock, RW_READER); 2927 2928 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2929 rw_exit(&adapter->chip_lock); 2930 return (0); 2931 } 2932 2933 mutex_enter(&rx_ring->rx_lock); 2934 rx_ring->poll_flag = 0; 2935 mutex_exit(&rx_ring->rx_lock); 2936 2937 /* Rx interrupt enabling for MSI and legacy */ 2938 intr_mask = E1000_READ_REG(hw, E1000_IMS); 2939 intr_mask |= E1000_IMS_RXT0; 2940 E1000_WRITE_REG(hw, E1000_IMS, intr_mask); 2941 E1000_WRITE_FLUSH(hw); 2942 2943 /* Trigger a Rx interrupt to check Rx ring */ 2944 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2945 E1000_WRITE_FLUSH(hw); 2946 2947 rw_exit(&adapter->chip_lock); 2948 return (0); 2949 } 2950 2951 static int 2952 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh) 2953 { 2954 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2955 struct e1000g *adapter = rx_ring->adapter; 2956 struct e1000_hw *hw = &adapter->shared; 2957 2958 rw_enter(&adapter->chip_lock, RW_READER); 2959 2960 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2961 rw_exit(&adapter->chip_lock); 2962 return (0); 2963 } 2964 mutex_enter(&rx_ring->rx_lock); 2965 rx_ring->poll_flag = 1; 2966 mutex_exit(&rx_ring->rx_lock); 2967 2968 /* Rx interrupt disabling for MSI and legacy */ 2969 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0); 2970 E1000_WRITE_FLUSH(hw); 2971 2972 rw_exit(&adapter->chip_lock); 2973 return (0); 2974 } 2975 2976 /* 2977 * e1000g_unicst_find - Find the slot for the specified unicast address 2978 */ 2979 static int 2980 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr) 2981 { 2982 int slot; 2983 2984 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2985 if ((Adapter->unicst_addr[slot].mac.set == 1) && 2986 (bcmp(Adapter->unicst_addr[slot].mac.addr, 2987 mac_addr, ETHERADDRL) == 0)) 2988 return (slot); 2989 } 2990 2991 return (-1); 2992 } 2993 2994 /* 2995 * Entry points to add and remove a MAC address to a ring group. 2996 * The caller takes care of adding and removing the MAC addresses 2997 * to the filter via these two routines. 2998 */ 2999 3000 static int 3001 e1000g_addmac(void *arg, const uint8_t *mac_addr) 3002 { 3003 struct e1000g *Adapter = (struct e1000g *)arg; 3004 int slot, err; 3005 3006 rw_enter(&Adapter->chip_lock, RW_WRITER); 3007 3008 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 3009 rw_exit(&Adapter->chip_lock); 3010 return (ECANCELED); 3011 } 3012 3013 if (e1000g_unicst_find(Adapter, mac_addr) != -1) { 3014 /* The same address is already in slot */ 3015 rw_exit(&Adapter->chip_lock); 3016 return (0); 3017 } 3018 3019 if (Adapter->unicst_avail == 0) { 3020 /* no slots available */ 3021 rw_exit(&Adapter->chip_lock); 3022 return (ENOSPC); 3023 } 3024 3025 /* Search for a free slot */ 3026 for (slot = 0; slot < Adapter->unicst_total; slot++) { 3027 if (Adapter->unicst_addr[slot].mac.set == 0) 3028 break; 3029 } 3030 ASSERT(slot < Adapter->unicst_total); 3031 3032 err = e1000g_unicst_set(Adapter, mac_addr, slot); 3033 if (err == 0) 3034 Adapter->unicst_avail--; 3035 3036 rw_exit(&Adapter->chip_lock); 3037 3038 return (err); 3039 } 3040 3041 static int 3042 e1000g_remmac(void *arg, const uint8_t *mac_addr) 3043 { 3044 struct e1000g *Adapter = (struct e1000g *)arg; 3045 int slot, err; 3046 3047 rw_enter(&Adapter->chip_lock, RW_WRITER); 3048 3049 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 3050 rw_exit(&Adapter->chip_lock); 3051 return (ECANCELED); 3052 } 3053 3054 slot = e1000g_unicst_find(Adapter, mac_addr); 3055 if (slot == -1) { 3056 rw_exit(&Adapter->chip_lock); 3057 return (EINVAL); 3058 } 3059 3060 ASSERT(Adapter->unicst_addr[slot].mac.set); 3061 3062 /* Clear this slot */ 3063 err = e1000g_unicst_set(Adapter, NULL, slot); 3064 if (err == 0) 3065 Adapter->unicst_avail++; 3066 3067 rw_exit(&Adapter->chip_lock); 3068 3069 return (err); 3070 } 3071 3072 static int 3073 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num) 3074 { 3075 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh; 3076 3077 mutex_enter(&rx_ring->rx_lock); 3078 rx_ring->ring_gen_num = mr_gen_num; 3079 mutex_exit(&rx_ring->rx_lock); 3080 return (0); 3081 } 3082 3083 /* 3084 * Callback funtion for MAC layer to register all rings. 3085 * 3086 * The hardware supports a single group with currently only one ring 3087 * available. 3088 * Though not offering virtualization ability per se, exposing the 3089 * group/ring still enables the polling and interrupt toggling. 3090 */ 3091 /* ARGSUSED */ 3092 void 3093 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index, 3094 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh) 3095 { 3096 struct e1000g *Adapter = (struct e1000g *)arg; 3097 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 3098 mac_intr_t *mintr; 3099 3100 /* 3101 * We advertised only RX group/rings, so the MAC framework shouldn't 3102 * ask for any thing else. 3103 */ 3104 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0); 3105 3106 rx_ring->mrh = rx_ring->mrh_init = rh; 3107 infop->mri_driver = (mac_ring_driver_t)rx_ring; 3108 infop->mri_start = e1000g_ring_start; 3109 infop->mri_stop = NULL; 3110 infop->mri_poll = e1000g_poll_ring; 3111 infop->mri_stat = e1000g_rx_ring_stat; 3112 3113 /* Ring level interrupts */ 3114 mintr = &infop->mri_intr; 3115 mintr->mi_handle = (mac_intr_handle_t)rx_ring; 3116 mintr->mi_enable = e1000g_rx_ring_intr_enable; 3117 mintr->mi_disable = e1000g_rx_ring_intr_disable; 3118 if (Adapter->msi_enable) 3119 mintr->mi_ddi_handle = Adapter->htable[0]; 3120 } 3121 3122 /* ARGSUSED */ 3123 static void 3124 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index, 3125 mac_group_info_t *infop, mac_group_handle_t gh) 3126 { 3127 struct e1000g *Adapter = (struct e1000g *)arg; 3128 mac_intr_t *mintr; 3129 3130 /* 3131 * We advertised a single RX ring. Getting a request for anything else 3132 * signifies a bug in the MAC framework. 3133 */ 3134 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0); 3135 3136 Adapter->rx_group = gh; 3137 3138 infop->mgi_driver = (mac_group_driver_t)Adapter; 3139 infop->mgi_start = NULL; 3140 infop->mgi_stop = NULL; 3141 infop->mgi_addmac = e1000g_addmac; 3142 infop->mgi_remmac = e1000g_remmac; 3143 infop->mgi_count = 1; 3144 3145 /* Group level interrupts */ 3146 mintr = &infop->mgi_intr; 3147 mintr->mi_handle = (mac_intr_handle_t)Adapter; 3148 mintr->mi_enable = e1000g_rx_group_intr_enable; 3149 mintr->mi_disable = e1000g_rx_group_intr_disable; 3150 } 3151 3152 static void 3153 e1000g_led_blink(void *arg) 3154 { 3155 e1000g_t *e1000g = arg; 3156 3157 mutex_enter(&e1000g->e1000g_led_lock); 3158 VERIFY(e1000g->e1000g_emul_blink); 3159 if (e1000g->e1000g_emul_state) { 3160 (void) e1000_led_on(&e1000g->shared); 3161 } else { 3162 (void) e1000_led_off(&e1000g->shared); 3163 } 3164 e1000g->e1000g_emul_state = !e1000g->e1000g_emul_state; 3165 mutex_exit(&e1000g->e1000g_led_lock); 3166 } 3167 3168 static int 3169 e1000g_led_set(void *arg, mac_led_mode_t mode, uint_t flags) 3170 { 3171 e1000g_t *e1000g = arg; 3172 3173 if (flags != 0) 3174 return (EINVAL); 3175 3176 if (mode != MAC_LED_DEFAULT && 3177 mode != MAC_LED_IDENT && 3178 mode != MAC_LED_OFF && 3179 mode != MAC_LED_ON) 3180 return (ENOTSUP); 3181 3182 mutex_enter(&e1000g->e1000g_led_lock); 3183 3184 if ((mode == MAC_LED_IDENT || mode == MAC_LED_OFF || 3185 mode == MAC_LED_ON) && 3186 !e1000g->e1000g_led_setup) { 3187 if (e1000_setup_led(&e1000g->shared) != E1000_SUCCESS) { 3188 mutex_exit(&e1000g->e1000g_led_lock); 3189 return (EIO); 3190 } 3191 3192 e1000g->e1000g_led_setup = B_TRUE; 3193 } 3194 3195 if (mode != MAC_LED_IDENT && e1000g->e1000g_blink != NULL) { 3196 ddi_periodic_t id = e1000g->e1000g_blink; 3197 e1000g->e1000g_blink = NULL; 3198 mutex_exit(&e1000g->e1000g_led_lock); 3199 ddi_periodic_delete(id); 3200 mutex_enter(&e1000g->e1000g_led_lock); 3201 } 3202 3203 switch (mode) { 3204 case MAC_LED_DEFAULT: 3205 if (e1000g->e1000g_led_setup) { 3206 if (e1000_cleanup_led(&e1000g->shared) != 3207 E1000_SUCCESS) { 3208 mutex_exit(&e1000g->e1000g_led_lock); 3209 return (EIO); 3210 } 3211 e1000g->e1000g_led_setup = B_FALSE; 3212 } 3213 break; 3214 case MAC_LED_IDENT: 3215 if (e1000g->e1000g_emul_blink) { 3216 if (e1000g->e1000g_blink != NULL) 3217 break; 3218 3219 /* 3220 * Note, we use a 200 ms period here as that's what 3221 * section 10.1.3 8254x Intel Manual (PCI/PCI-X Family 3222 * of Gigabit Ethernet Controllers Software Developer's 3223 * Manual) indicates that the optional blink hardware 3224 * operates at. 3225 */ 3226 e1000g->e1000g_blink = 3227 ddi_periodic_add(e1000g_led_blink, e1000g, 3228 200ULL * (NANOSEC / MILLISEC), DDI_IPL_0); 3229 } else if (e1000_blink_led(&e1000g->shared) != E1000_SUCCESS) { 3230 mutex_exit(&e1000g->e1000g_led_lock); 3231 return (EIO); 3232 } 3233 break; 3234 case MAC_LED_OFF: 3235 if (e1000_led_off(&e1000g->shared) != E1000_SUCCESS) { 3236 mutex_exit(&e1000g->e1000g_led_lock); 3237 return (EIO); 3238 } 3239 break; 3240 case MAC_LED_ON: 3241 if (e1000_led_on(&e1000g->shared) != E1000_SUCCESS) { 3242 mutex_exit(&e1000g->e1000g_led_lock); 3243 return (EIO); 3244 } 3245 break; 3246 default: 3247 mutex_exit(&e1000g->e1000g_led_lock); 3248 return (ENOTSUP); 3249 } 3250 3251 mutex_exit(&e1000g->e1000g_led_lock); 3252 return (0); 3253 3254 } 3255 3256 static boolean_t 3257 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 3258 { 3259 struct e1000g *Adapter = (struct e1000g *)arg; 3260 3261 switch (cap) { 3262 case MAC_CAPAB_HCKSUM: { 3263 uint32_t *txflags = cap_data; 3264 3265 if (Adapter->tx_hcksum_enable) 3266 *txflags = HCKSUM_IPHDRCKSUM | 3267 HCKSUM_INET_PARTIAL; 3268 else 3269 return (B_FALSE); 3270 break; 3271 } 3272 3273 case MAC_CAPAB_LSO: { 3274 mac_capab_lso_t *cap_lso = cap_data; 3275 3276 if (Adapter->lso_enable) { 3277 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 3278 cap_lso->lso_basic_tcp_ipv4.lso_max = 3279 E1000_LSO_MAXLEN; 3280 } else 3281 return (B_FALSE); 3282 break; 3283 } 3284 case MAC_CAPAB_RINGS: { 3285 mac_capab_rings_t *cap_rings = cap_data; 3286 3287 /* No TX rings exposed yet */ 3288 if (cap_rings->mr_type != MAC_RING_TYPE_RX) 3289 return (B_FALSE); 3290 3291 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC; 3292 cap_rings->mr_rnum = 1; 3293 cap_rings->mr_gnum = 1; 3294 cap_rings->mr_rget = e1000g_fill_ring; 3295 cap_rings->mr_gget = e1000g_fill_group; 3296 break; 3297 } 3298 case MAC_CAPAB_LED: { 3299 mac_capab_led_t *cap_led = cap_data; 3300 3301 cap_led->mcl_flags = 0; 3302 cap_led->mcl_modes = MAC_LED_DEFAULT; 3303 if (Adapter->shared.mac.ops.blink_led != NULL && 3304 Adapter->shared.mac.ops.blink_led != 3305 e1000_null_ops_generic) { 3306 cap_led->mcl_modes |= MAC_LED_IDENT; 3307 } 3308 3309 if (Adapter->shared.mac.ops.led_off != NULL && 3310 Adapter->shared.mac.ops.led_off != 3311 e1000_null_ops_generic) { 3312 cap_led->mcl_modes |= MAC_LED_OFF; 3313 } 3314 3315 if (Adapter->shared.mac.ops.led_on != NULL && 3316 Adapter->shared.mac.ops.led_on != 3317 e1000_null_ops_generic) { 3318 cap_led->mcl_modes |= MAC_LED_ON; 3319 } 3320 3321 /* 3322 * Some hardware doesn't support blinking natively as they're 3323 * missing the optional blink circuit. If they have both off and 3324 * on then we'll emulate it ourselves. 3325 */ 3326 if (((cap_led->mcl_modes & MAC_LED_IDENT) == 0) && 3327 ((cap_led->mcl_modes & MAC_LED_OFF) != 0) && 3328 ((cap_led->mcl_modes & MAC_LED_ON) != 0)) { 3329 cap_led->mcl_modes |= MAC_LED_IDENT; 3330 Adapter->e1000g_emul_blink = B_TRUE; 3331 } 3332 3333 cap_led->mcl_set = e1000g_led_set; 3334 break; 3335 } 3336 default: 3337 return (B_FALSE); 3338 } 3339 return (B_TRUE); 3340 } 3341 3342 static boolean_t 3343 e1000g_param_locked(mac_prop_id_t pr_num) 3344 { 3345 /* 3346 * All en_* parameters are locked (read-only) while 3347 * the device is in any sort of loopback mode ... 3348 */ 3349 switch (pr_num) { 3350 case MAC_PROP_EN_1000FDX_CAP: 3351 case MAC_PROP_EN_1000HDX_CAP: 3352 case MAC_PROP_EN_100FDX_CAP: 3353 case MAC_PROP_EN_100HDX_CAP: 3354 case MAC_PROP_EN_10FDX_CAP: 3355 case MAC_PROP_EN_10HDX_CAP: 3356 case MAC_PROP_AUTONEG: 3357 case MAC_PROP_FLOWCTRL: 3358 return (B_TRUE); 3359 } 3360 return (B_FALSE); 3361 } 3362 3363 /* 3364 * callback function for set/get of properties 3365 */ 3366 static int 3367 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3368 uint_t pr_valsize, const void *pr_val) 3369 { 3370 struct e1000g *Adapter = arg; 3371 struct e1000_hw *hw = &Adapter->shared; 3372 struct e1000_fc_info *fc = &Adapter->shared.fc; 3373 int err = 0; 3374 link_flowctrl_t flowctrl; 3375 uint32_t cur_mtu, new_mtu; 3376 3377 rw_enter(&Adapter->chip_lock, RW_WRITER); 3378 3379 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 3380 rw_exit(&Adapter->chip_lock); 3381 return (ECANCELED); 3382 } 3383 3384 if (Adapter->loopback_mode != E1000G_LB_NONE && 3385 e1000g_param_locked(pr_num)) { 3386 /* 3387 * All en_* parameters are locked (read-only) 3388 * while the device is in any sort of loopback mode. 3389 */ 3390 rw_exit(&Adapter->chip_lock); 3391 return (EBUSY); 3392 } 3393 3394 switch (pr_num) { 3395 case MAC_PROP_EN_1000FDX_CAP: 3396 if (hw->phy.media_type != e1000_media_type_copper) { 3397 err = ENOTSUP; 3398 break; 3399 } 3400 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 3401 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 3402 goto reset; 3403 case MAC_PROP_EN_100FDX_CAP: 3404 if (hw->phy.media_type != e1000_media_type_copper) { 3405 err = ENOTSUP; 3406 break; 3407 } 3408 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 3409 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 3410 goto reset; 3411 case MAC_PROP_EN_100HDX_CAP: 3412 if (hw->phy.media_type != e1000_media_type_copper) { 3413 err = ENOTSUP; 3414 break; 3415 } 3416 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 3417 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 3418 goto reset; 3419 case MAC_PROP_EN_10FDX_CAP: 3420 if (hw->phy.media_type != e1000_media_type_copper) { 3421 err = ENOTSUP; 3422 break; 3423 } 3424 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 3425 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 3426 goto reset; 3427 case MAC_PROP_EN_10HDX_CAP: 3428 if (hw->phy.media_type != e1000_media_type_copper) { 3429 err = ENOTSUP; 3430 break; 3431 } 3432 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 3433 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 3434 goto reset; 3435 case MAC_PROP_AUTONEG: 3436 if (hw->phy.media_type != e1000_media_type_copper) { 3437 err = ENOTSUP; 3438 break; 3439 } 3440 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 3441 goto reset; 3442 case MAC_PROP_FLOWCTRL: 3443 fc->send_xon = B_TRUE; 3444 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 3445 3446 switch (flowctrl) { 3447 default: 3448 err = EINVAL; 3449 break; 3450 case LINK_FLOWCTRL_NONE: 3451 fc->requested_mode = e1000_fc_none; 3452 break; 3453 case LINK_FLOWCTRL_RX: 3454 fc->requested_mode = e1000_fc_rx_pause; 3455 break; 3456 case LINK_FLOWCTRL_TX: 3457 fc->requested_mode = e1000_fc_tx_pause; 3458 break; 3459 case LINK_FLOWCTRL_BI: 3460 fc->requested_mode = e1000_fc_full; 3461 break; 3462 } 3463 reset: 3464 if (err == 0) { 3465 /* check PCH limits & reset the link */ 3466 e1000g_pch_limits(Adapter); 3467 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 3468 err = EINVAL; 3469 } 3470 break; 3471 case MAC_PROP_ADV_1000FDX_CAP: 3472 case MAC_PROP_ADV_1000HDX_CAP: 3473 case MAC_PROP_ADV_100FDX_CAP: 3474 case MAC_PROP_ADV_100HDX_CAP: 3475 case MAC_PROP_ADV_10FDX_CAP: 3476 case MAC_PROP_ADV_10HDX_CAP: 3477 case MAC_PROP_EN_1000HDX_CAP: 3478 case MAC_PROP_STATUS: 3479 case MAC_PROP_SPEED: 3480 case MAC_PROP_DUPLEX: 3481 err = ENOTSUP; /* read-only prop. Can't set this. */ 3482 break; 3483 case MAC_PROP_MTU: 3484 /* adapter must be stopped for an MTU change */ 3485 if (Adapter->e1000g_state & E1000G_STARTED) { 3486 err = EBUSY; 3487 break; 3488 } 3489 3490 cur_mtu = Adapter->default_mtu; 3491 3492 /* get new requested MTU */ 3493 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 3494 if (new_mtu == cur_mtu) { 3495 err = 0; 3496 break; 3497 } 3498 3499 if ((new_mtu < DEFAULT_MTU) || 3500 (new_mtu > Adapter->max_mtu)) { 3501 err = EINVAL; 3502 break; 3503 } 3504 3505 /* inform MAC framework of new MTU */ 3506 err = mac_maxsdu_update(Adapter->mh, new_mtu); 3507 3508 if (err == 0) { 3509 Adapter->default_mtu = new_mtu; 3510 Adapter->max_frame_size = 3511 e1000g_mtu2maxframe(new_mtu); 3512 3513 /* 3514 * check PCH limits & set buffer sizes to 3515 * match new MTU 3516 */ 3517 e1000g_pch_limits(Adapter); 3518 e1000g_set_bufsize(Adapter); 3519 3520 /* 3521 * decrease the number of descriptors and free 3522 * packets for jumbo frames to reduce tx/rx 3523 * resource consumption 3524 */ 3525 if (Adapter->max_frame_size >= 3526 (FRAME_SIZE_UPTO_4K)) { 3527 if (Adapter->tx_desc_num_flag == 0) 3528 Adapter->tx_desc_num = 3529 DEFAULT_JUMBO_NUM_TX_DESC; 3530 3531 if (Adapter->rx_desc_num_flag == 0) 3532 Adapter->rx_desc_num = 3533 DEFAULT_JUMBO_NUM_RX_DESC; 3534 3535 if (Adapter->tx_buf_num_flag == 0) 3536 Adapter->tx_freelist_num = 3537 DEFAULT_JUMBO_NUM_TX_BUF; 3538 3539 if (Adapter->rx_buf_num_flag == 0) 3540 Adapter->rx_freelist_limit = 3541 DEFAULT_JUMBO_NUM_RX_BUF; 3542 } else { 3543 if (Adapter->tx_desc_num_flag == 0) 3544 Adapter->tx_desc_num = 3545 DEFAULT_NUM_TX_DESCRIPTOR; 3546 3547 if (Adapter->rx_desc_num_flag == 0) 3548 Adapter->rx_desc_num = 3549 DEFAULT_NUM_RX_DESCRIPTOR; 3550 3551 if (Adapter->tx_buf_num_flag == 0) 3552 Adapter->tx_freelist_num = 3553 DEFAULT_NUM_TX_FREELIST; 3554 3555 if (Adapter->rx_buf_num_flag == 0) 3556 Adapter->rx_freelist_limit = 3557 DEFAULT_NUM_RX_FREELIST; 3558 } 3559 } 3560 break; 3561 case MAC_PROP_PRIVATE: 3562 err = e1000g_set_priv_prop(Adapter, pr_name, 3563 pr_valsize, pr_val); 3564 break; 3565 default: 3566 err = ENOTSUP; 3567 break; 3568 } 3569 rw_exit(&Adapter->chip_lock); 3570 return (err); 3571 } 3572 3573 static int 3574 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3575 uint_t pr_valsize, void *pr_val) 3576 { 3577 struct e1000g *Adapter = arg; 3578 struct e1000_fc_info *fc = &Adapter->shared.fc; 3579 int err = 0; 3580 link_flowctrl_t flowctrl; 3581 uint64_t tmp = 0; 3582 3583 switch (pr_num) { 3584 case MAC_PROP_DUPLEX: 3585 ASSERT(pr_valsize >= sizeof (link_duplex_t)); 3586 bcopy(&Adapter->link_duplex, pr_val, 3587 sizeof (link_duplex_t)); 3588 break; 3589 case MAC_PROP_SPEED: 3590 ASSERT(pr_valsize >= sizeof (uint64_t)); 3591 tmp = Adapter->link_speed * 1000000ull; 3592 bcopy(&tmp, pr_val, sizeof (tmp)); 3593 break; 3594 case MAC_PROP_AUTONEG: 3595 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 3596 break; 3597 case MAC_PROP_FLOWCTRL: 3598 ASSERT(pr_valsize >= sizeof (link_flowctrl_t)); 3599 switch (fc->current_mode) { 3600 case e1000_fc_none: 3601 flowctrl = LINK_FLOWCTRL_NONE; 3602 break; 3603 case e1000_fc_rx_pause: 3604 flowctrl = LINK_FLOWCTRL_RX; 3605 break; 3606 case e1000_fc_tx_pause: 3607 flowctrl = LINK_FLOWCTRL_TX; 3608 break; 3609 case e1000_fc_full: 3610 flowctrl = LINK_FLOWCTRL_BI; 3611 break; 3612 } 3613 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 3614 break; 3615 case MAC_PROP_ADV_1000FDX_CAP: 3616 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 3617 break; 3618 case MAC_PROP_EN_1000FDX_CAP: 3619 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 3620 break; 3621 case MAC_PROP_ADV_1000HDX_CAP: 3622 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 3623 break; 3624 case MAC_PROP_EN_1000HDX_CAP: 3625 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 3626 break; 3627 case MAC_PROP_ADV_100FDX_CAP: 3628 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 3629 break; 3630 case MAC_PROP_EN_100FDX_CAP: 3631 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 3632 break; 3633 case MAC_PROP_ADV_100HDX_CAP: 3634 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 3635 break; 3636 case MAC_PROP_EN_100HDX_CAP: 3637 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 3638 break; 3639 case MAC_PROP_ADV_10FDX_CAP: 3640 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 3641 break; 3642 case MAC_PROP_EN_10FDX_CAP: 3643 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 3644 break; 3645 case MAC_PROP_ADV_10HDX_CAP: 3646 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 3647 break; 3648 case MAC_PROP_EN_10HDX_CAP: 3649 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 3650 break; 3651 case MAC_PROP_ADV_100T4_CAP: 3652 case MAC_PROP_EN_100T4_CAP: 3653 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 3654 break; 3655 case MAC_PROP_PRIVATE: 3656 err = e1000g_get_priv_prop(Adapter, pr_name, 3657 pr_valsize, pr_val); 3658 break; 3659 default: 3660 err = ENOTSUP; 3661 break; 3662 } 3663 3664 return (err); 3665 } 3666 3667 static void 3668 e1000g_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3669 mac_prop_info_handle_t prh) 3670 { 3671 struct e1000g *Adapter = arg; 3672 struct e1000_hw *hw = &Adapter->shared; 3673 3674 switch (pr_num) { 3675 case MAC_PROP_DUPLEX: 3676 case MAC_PROP_SPEED: 3677 case MAC_PROP_ADV_1000FDX_CAP: 3678 case MAC_PROP_ADV_1000HDX_CAP: 3679 case MAC_PROP_ADV_100FDX_CAP: 3680 case MAC_PROP_ADV_100HDX_CAP: 3681 case MAC_PROP_ADV_10FDX_CAP: 3682 case MAC_PROP_ADV_10HDX_CAP: 3683 case MAC_PROP_ADV_100T4_CAP: 3684 case MAC_PROP_EN_100T4_CAP: 3685 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3686 break; 3687 3688 case MAC_PROP_EN_1000FDX_CAP: 3689 if (hw->phy.media_type != e1000_media_type_copper) { 3690 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3691 } else { 3692 mac_prop_info_set_default_uint8(prh, 3693 ((Adapter->phy_ext_status & 3694 IEEE_ESR_1000T_FD_CAPS) || 3695 (Adapter->phy_ext_status & 3696 IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0); 3697 } 3698 break; 3699 3700 case MAC_PROP_EN_100FDX_CAP: 3701 if (hw->phy.media_type != e1000_media_type_copper) { 3702 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3703 } else { 3704 mac_prop_info_set_default_uint8(prh, 3705 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 3706 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 3707 ? 1 : 0); 3708 } 3709 break; 3710 3711 case MAC_PROP_EN_100HDX_CAP: 3712 if (hw->phy.media_type != e1000_media_type_copper) { 3713 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3714 } else { 3715 mac_prop_info_set_default_uint8(prh, 3716 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 3717 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) 3718 ? 1 : 0); 3719 } 3720 break; 3721 3722 case MAC_PROP_EN_10FDX_CAP: 3723 if (hw->phy.media_type != e1000_media_type_copper) { 3724 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3725 } else { 3726 mac_prop_info_set_default_uint8(prh, 3727 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0); 3728 } 3729 break; 3730 3731 case MAC_PROP_EN_10HDX_CAP: 3732 if (hw->phy.media_type != e1000_media_type_copper) { 3733 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3734 } else { 3735 mac_prop_info_set_default_uint8(prh, 3736 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0); 3737 } 3738 break; 3739 3740 case MAC_PROP_EN_1000HDX_CAP: 3741 if (hw->phy.media_type != e1000_media_type_copper) 3742 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3743 break; 3744 3745 case MAC_PROP_AUTONEG: 3746 if (hw->phy.media_type != e1000_media_type_copper) { 3747 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3748 } else { 3749 mac_prop_info_set_default_uint8(prh, 3750 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) 3751 ? 1 : 0); 3752 } 3753 break; 3754 3755 case MAC_PROP_FLOWCTRL: 3756 mac_prop_info_set_default_link_flowctrl(prh, LINK_FLOWCTRL_BI); 3757 break; 3758 3759 case MAC_PROP_MTU: { 3760 struct e1000_mac_info *mac = &Adapter->shared.mac; 3761 struct e1000_phy_info *phy = &Adapter->shared.phy; 3762 uint32_t max; 3763 3764 /* some MAC types do not support jumbo frames */ 3765 if ((mac->type == e1000_ich8lan) || 3766 ((mac->type == e1000_ich9lan) && (phy->type == 3767 e1000_phy_ife))) { 3768 max = DEFAULT_MTU; 3769 } else { 3770 max = Adapter->max_mtu; 3771 } 3772 3773 mac_prop_info_set_range_uint32(prh, DEFAULT_MTU, max); 3774 break; 3775 } 3776 case MAC_PROP_PRIVATE: { 3777 char valstr[64]; 3778 int value; 3779 3780 if (strcmp(pr_name, "_adv_pause_cap") == 0 || 3781 strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3782 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3783 return; 3784 } else if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3785 value = DEFAULT_TX_BCOPY_THRESHOLD; 3786 } else if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3787 value = DEFAULT_TX_INTR_ENABLE; 3788 } else if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3789 value = DEFAULT_TX_INTR_DELAY; 3790 } else if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3791 value = DEFAULT_TX_INTR_ABS_DELAY; 3792 } else if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3793 value = DEFAULT_RX_BCOPY_THRESHOLD; 3794 } else if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3795 value = DEFAULT_RX_LIMIT_ON_INTR; 3796 } else if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3797 value = DEFAULT_RX_INTR_DELAY; 3798 } else if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3799 value = DEFAULT_RX_INTR_ABS_DELAY; 3800 } else if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3801 value = DEFAULT_INTR_THROTTLING; 3802 } else if (strcmp(pr_name, "_intr_adaptive") == 0) { 3803 value = 1; 3804 } else { 3805 return; 3806 } 3807 3808 (void) snprintf(valstr, sizeof (valstr), "%d", value); 3809 mac_prop_info_set_default_str(prh, valstr); 3810 break; 3811 } 3812 } 3813 } 3814 3815 /* ARGSUSED2 */ 3816 static int 3817 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 3818 uint_t pr_valsize, const void *pr_val) 3819 { 3820 int err = 0; 3821 long result; 3822 struct e1000_hw *hw = &Adapter->shared; 3823 3824 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3825 if (pr_val == NULL) { 3826 err = EINVAL; 3827 return (err); 3828 } 3829 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3830 if (result < MIN_TX_BCOPY_THRESHOLD || 3831 result > MAX_TX_BCOPY_THRESHOLD) 3832 err = EINVAL; 3833 else { 3834 Adapter->tx_bcopy_thresh = (uint32_t)result; 3835 } 3836 return (err); 3837 } 3838 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3839 if (pr_val == NULL) { 3840 err = EINVAL; 3841 return (err); 3842 } 3843 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3844 if (result < 0 || result > 1) 3845 err = EINVAL; 3846 else { 3847 Adapter->tx_intr_enable = (result == 1) ? 3848 B_TRUE: B_FALSE; 3849 if (Adapter->tx_intr_enable) 3850 e1000g_mask_tx_interrupt(Adapter); 3851 else 3852 e1000g_clear_tx_interrupt(Adapter); 3853 if (e1000g_check_acc_handle( 3854 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3855 ddi_fm_service_impact(Adapter->dip, 3856 DDI_SERVICE_DEGRADED); 3857 err = EIO; 3858 } 3859 } 3860 return (err); 3861 } 3862 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3863 if (pr_val == NULL) { 3864 err = EINVAL; 3865 return (err); 3866 } 3867 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3868 if (result < MIN_TX_INTR_DELAY || 3869 result > MAX_TX_INTR_DELAY) 3870 err = EINVAL; 3871 else { 3872 Adapter->tx_intr_delay = (uint32_t)result; 3873 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 3874 if (e1000g_check_acc_handle( 3875 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3876 ddi_fm_service_impact(Adapter->dip, 3877 DDI_SERVICE_DEGRADED); 3878 err = EIO; 3879 } 3880 } 3881 return (err); 3882 } 3883 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3884 if (pr_val == NULL) { 3885 err = EINVAL; 3886 return (err); 3887 } 3888 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3889 if (result < MIN_TX_INTR_ABS_DELAY || 3890 result > MAX_TX_INTR_ABS_DELAY) 3891 err = EINVAL; 3892 else { 3893 Adapter->tx_intr_abs_delay = (uint32_t)result; 3894 E1000_WRITE_REG(hw, E1000_TADV, 3895 Adapter->tx_intr_abs_delay); 3896 if (e1000g_check_acc_handle( 3897 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3898 ddi_fm_service_impact(Adapter->dip, 3899 DDI_SERVICE_DEGRADED); 3900 err = EIO; 3901 } 3902 } 3903 return (err); 3904 } 3905 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3906 if (pr_val == NULL) { 3907 err = EINVAL; 3908 return (err); 3909 } 3910 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3911 if (result < MIN_RX_BCOPY_THRESHOLD || 3912 result > MAX_RX_BCOPY_THRESHOLD) 3913 err = EINVAL; 3914 else 3915 Adapter->rx_bcopy_thresh = (uint32_t)result; 3916 return (err); 3917 } 3918 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3919 if (pr_val == NULL) { 3920 err = EINVAL; 3921 return (err); 3922 } 3923 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3924 if (result < MIN_RX_LIMIT_ON_INTR || 3925 result > MAX_RX_LIMIT_ON_INTR) 3926 err = EINVAL; 3927 else 3928 Adapter->rx_limit_onintr = (uint32_t)result; 3929 return (err); 3930 } 3931 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3932 if (pr_val == NULL) { 3933 err = EINVAL; 3934 return (err); 3935 } 3936 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3937 if (result < MIN_RX_INTR_DELAY || 3938 result > MAX_RX_INTR_DELAY) 3939 err = EINVAL; 3940 else { 3941 Adapter->rx_intr_delay = (uint32_t)result; 3942 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3943 if (e1000g_check_acc_handle( 3944 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3945 ddi_fm_service_impact(Adapter->dip, 3946 DDI_SERVICE_DEGRADED); 3947 err = EIO; 3948 } 3949 } 3950 return (err); 3951 } 3952 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3953 if (pr_val == NULL) { 3954 err = EINVAL; 3955 return (err); 3956 } 3957 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3958 if (result < MIN_RX_INTR_ABS_DELAY || 3959 result > MAX_RX_INTR_ABS_DELAY) 3960 err = EINVAL; 3961 else { 3962 Adapter->rx_intr_abs_delay = (uint32_t)result; 3963 E1000_WRITE_REG(hw, E1000_RADV, 3964 Adapter->rx_intr_abs_delay); 3965 if (e1000g_check_acc_handle( 3966 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3967 ddi_fm_service_impact(Adapter->dip, 3968 DDI_SERVICE_DEGRADED); 3969 err = EIO; 3970 } 3971 } 3972 return (err); 3973 } 3974 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3975 if (pr_val == NULL) { 3976 err = EINVAL; 3977 return (err); 3978 } 3979 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3980 if (result < MIN_INTR_THROTTLING || 3981 result > MAX_INTR_THROTTLING) 3982 err = EINVAL; 3983 else { 3984 if (hw->mac.type >= e1000_82540) { 3985 Adapter->intr_throttling_rate = 3986 (uint32_t)result; 3987 E1000_WRITE_REG(hw, E1000_ITR, 3988 Adapter->intr_throttling_rate); 3989 if (e1000g_check_acc_handle( 3990 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3991 ddi_fm_service_impact(Adapter->dip, 3992 DDI_SERVICE_DEGRADED); 3993 err = EIO; 3994 } 3995 } else 3996 err = EINVAL; 3997 } 3998 return (err); 3999 } 4000 if (strcmp(pr_name, "_intr_adaptive") == 0) { 4001 if (pr_val == NULL) { 4002 err = EINVAL; 4003 return (err); 4004 } 4005 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 4006 if (result < 0 || result > 1) 4007 err = EINVAL; 4008 else { 4009 if (hw->mac.type >= e1000_82540) { 4010 Adapter->intr_adaptive = (result == 1) ? 4011 B_TRUE : B_FALSE; 4012 } else { 4013 err = EINVAL; 4014 } 4015 } 4016 return (err); 4017 } 4018 return (ENOTSUP); 4019 } 4020 4021 static int 4022 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 4023 uint_t pr_valsize, void *pr_val) 4024 { 4025 int err = ENOTSUP; 4026 int value; 4027 4028 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 4029 value = Adapter->param_adv_pause; 4030 err = 0; 4031 goto done; 4032 } 4033 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 4034 value = Adapter->param_adv_asym_pause; 4035 err = 0; 4036 goto done; 4037 } 4038 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 4039 value = Adapter->tx_bcopy_thresh; 4040 err = 0; 4041 goto done; 4042 } 4043 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 4044 value = Adapter->tx_intr_enable; 4045 err = 0; 4046 goto done; 4047 } 4048 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 4049 value = Adapter->tx_intr_delay; 4050 err = 0; 4051 goto done; 4052 } 4053 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 4054 value = Adapter->tx_intr_abs_delay; 4055 err = 0; 4056 goto done; 4057 } 4058 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 4059 value = Adapter->rx_bcopy_thresh; 4060 err = 0; 4061 goto done; 4062 } 4063 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 4064 value = Adapter->rx_limit_onintr; 4065 err = 0; 4066 goto done; 4067 } 4068 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 4069 value = Adapter->rx_intr_delay; 4070 err = 0; 4071 goto done; 4072 } 4073 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 4074 value = Adapter->rx_intr_abs_delay; 4075 err = 0; 4076 goto done; 4077 } 4078 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 4079 value = Adapter->intr_throttling_rate; 4080 err = 0; 4081 goto done; 4082 } 4083 if (strcmp(pr_name, "_intr_adaptive") == 0) { 4084 value = Adapter->intr_adaptive; 4085 err = 0; 4086 goto done; 4087 } 4088 done: 4089 if (err == 0) { 4090 (void) snprintf(pr_val, pr_valsize, "%d", value); 4091 } 4092 return (err); 4093 } 4094 4095 /* 4096 * e1000g_get_conf - get configurations set in e1000g.conf 4097 * This routine gets user-configured values out of the configuration 4098 * file e1000g.conf. 4099 * 4100 * For each configurable value, there is a minimum, a maximum, and a 4101 * default. 4102 * If user does not configure a value, use the default. 4103 * If user configures below the minimum, use the minumum. 4104 * If user configures above the maximum, use the maxumum. 4105 */ 4106 static void 4107 e1000g_get_conf(struct e1000g *Adapter) 4108 { 4109 struct e1000_hw *hw = &Adapter->shared; 4110 boolean_t tbi_compatibility = B_FALSE; 4111 boolean_t is_jumbo = B_FALSE; 4112 int propval; 4113 /* 4114 * decrease the number of descriptors and free packets 4115 * for jumbo frames to reduce tx/rx resource consumption 4116 */ 4117 if (Adapter->max_frame_size >= FRAME_SIZE_UPTO_4K) { 4118 is_jumbo = B_TRUE; 4119 } 4120 4121 /* 4122 * get each configurable property from e1000g.conf 4123 */ 4124 4125 /* 4126 * NumTxDescriptors 4127 */ 4128 Adapter->tx_desc_num_flag = 4129 e1000g_get_prop(Adapter, "NumTxDescriptors", 4130 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 4131 is_jumbo ? DEFAULT_JUMBO_NUM_TX_DESC 4132 : DEFAULT_NUM_TX_DESCRIPTOR, &propval); 4133 Adapter->tx_desc_num = propval; 4134 4135 /* 4136 * NumRxDescriptors 4137 */ 4138 Adapter->rx_desc_num_flag = 4139 e1000g_get_prop(Adapter, "NumRxDescriptors", 4140 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 4141 is_jumbo ? DEFAULT_JUMBO_NUM_RX_DESC 4142 : DEFAULT_NUM_RX_DESCRIPTOR, &propval); 4143 Adapter->rx_desc_num = propval; 4144 4145 /* 4146 * NumRxFreeList 4147 */ 4148 Adapter->rx_buf_num_flag = 4149 e1000g_get_prop(Adapter, "NumRxFreeList", 4150 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 4151 is_jumbo ? DEFAULT_JUMBO_NUM_RX_BUF 4152 : DEFAULT_NUM_RX_FREELIST, &propval); 4153 Adapter->rx_freelist_limit = propval; 4154 4155 /* 4156 * NumTxPacketList 4157 */ 4158 Adapter->tx_buf_num_flag = 4159 e1000g_get_prop(Adapter, "NumTxPacketList", 4160 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 4161 is_jumbo ? DEFAULT_JUMBO_NUM_TX_BUF 4162 : DEFAULT_NUM_TX_FREELIST, &propval); 4163 Adapter->tx_freelist_num = propval; 4164 4165 /* 4166 * FlowControl 4167 */ 4168 hw->fc.send_xon = B_TRUE; 4169 (void) e1000g_get_prop(Adapter, "FlowControl", 4170 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL, &propval); 4171 hw->fc.requested_mode = propval; 4172 /* 4 is the setting that says "let the eeprom decide" */ 4173 if (hw->fc.requested_mode == 4) 4174 hw->fc.requested_mode = e1000_fc_default; 4175 4176 /* 4177 * Max Num Receive Packets on Interrupt 4178 */ 4179 (void) e1000g_get_prop(Adapter, "MaxNumReceivePackets", 4180 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 4181 DEFAULT_RX_LIMIT_ON_INTR, &propval); 4182 Adapter->rx_limit_onintr = propval; 4183 4184 /* 4185 * PHY master slave setting 4186 */ 4187 (void) e1000g_get_prop(Adapter, "SetMasterSlave", 4188 e1000_ms_hw_default, e1000_ms_auto, 4189 e1000_ms_hw_default, &propval); 4190 hw->phy.ms_type = propval; 4191 4192 /* 4193 * Parameter which controls TBI mode workaround, which is only 4194 * needed on certain switches such as Cisco 6500/Foundry 4195 */ 4196 (void) e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 4197 0, 1, DEFAULT_TBI_COMPAT_ENABLE, &propval); 4198 tbi_compatibility = (propval == 1); 4199 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 4200 4201 /* 4202 * MSI Enable 4203 */ 4204 (void) e1000g_get_prop(Adapter, "MSIEnable", 4205 0, 1, DEFAULT_MSI_ENABLE, &propval); 4206 Adapter->msi_enable = (propval == 1); 4207 4208 /* 4209 * Interrupt Throttling Rate 4210 */ 4211 (void) e1000g_get_prop(Adapter, "intr_throttling_rate", 4212 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 4213 DEFAULT_INTR_THROTTLING, &propval); 4214 Adapter->intr_throttling_rate = propval; 4215 4216 /* 4217 * Adaptive Interrupt Blanking Enable/Disable 4218 * It is enabled by default 4219 */ 4220 (void) e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1, 4221 &propval); 4222 Adapter->intr_adaptive = (propval == 1); 4223 4224 /* 4225 * Hardware checksum enable/disable parameter 4226 */ 4227 (void) e1000g_get_prop(Adapter, "tx_hcksum_enable", 4228 0, 1, DEFAULT_TX_HCKSUM_ENABLE, &propval); 4229 Adapter->tx_hcksum_enable = (propval == 1); 4230 /* 4231 * Checksum on/off selection via global parameters. 4232 * 4233 * If the chip is flagged as not capable of (correctly) 4234 * handling checksumming, we don't enable it on either 4235 * Rx or Tx side. Otherwise, we take this chip's settings 4236 * from the patchable global defaults. 4237 * 4238 * We advertise our capabilities only if TX offload is 4239 * enabled. On receive, the stack will accept checksummed 4240 * packets anyway, even if we haven't said we can deliver 4241 * them. 4242 */ 4243 switch (hw->mac.type) { 4244 case e1000_82540: 4245 case e1000_82544: 4246 case e1000_82545: 4247 case e1000_82545_rev_3: 4248 case e1000_82546: 4249 case e1000_82546_rev_3: 4250 case e1000_82571: 4251 case e1000_82572: 4252 case e1000_82573: 4253 case e1000_80003es2lan: 4254 break; 4255 /* 4256 * For the following Intel PRO/1000 chipsets, we have not 4257 * tested the hardware checksum offload capability, so we 4258 * disable the capability for them. 4259 * e1000_82542, 4260 * e1000_82543, 4261 * e1000_82541, 4262 * e1000_82541_rev_2, 4263 * e1000_82547, 4264 * e1000_82547_rev_2, 4265 */ 4266 default: 4267 Adapter->tx_hcksum_enable = B_FALSE; 4268 } 4269 4270 /* 4271 * Large Send Offloading(LSO) Enable/Disable 4272 * If the tx hardware checksum is not enabled, LSO should be 4273 * disabled. 4274 */ 4275 (void) e1000g_get_prop(Adapter, "lso_enable", 4276 0, 1, DEFAULT_LSO_ENABLE, &propval); 4277 Adapter->lso_enable = (propval == 1); 4278 4279 switch (hw->mac.type) { 4280 case e1000_82546: 4281 case e1000_82546_rev_3: 4282 if (Adapter->lso_enable) 4283 Adapter->lso_premature_issue = B_TRUE; 4284 /* FALLTHRU */ 4285 case e1000_82571: 4286 case e1000_82572: 4287 case e1000_82573: 4288 case e1000_80003es2lan: 4289 break; 4290 default: 4291 Adapter->lso_enable = B_FALSE; 4292 } 4293 4294 if (!Adapter->tx_hcksum_enable) { 4295 Adapter->lso_premature_issue = B_FALSE; 4296 Adapter->lso_enable = B_FALSE; 4297 } 4298 4299 /* 4300 * If mem_workaround_82546 is enabled, the rx buffer allocated by 4301 * e1000_82545, e1000_82546 and e1000_82546_rev_3 4302 * will not cross 64k boundary. 4303 */ 4304 (void) e1000g_get_prop(Adapter, "mem_workaround_82546", 4305 0, 1, DEFAULT_MEM_WORKAROUND_82546, &propval); 4306 Adapter->mem_workaround_82546 = (propval == 1); 4307 4308 /* 4309 * Max number of multicast addresses 4310 */ 4311 (void) e1000g_get_prop(Adapter, "mcast_max_num", 4312 MIN_MCAST_NUM, MAX_MCAST_NUM, hw->mac.mta_reg_count * 32, 4313 &propval); 4314 Adapter->mcast_max_num = propval; 4315 } 4316 4317 /* 4318 * e1000g_get_prop - routine to read properties 4319 * 4320 * Get a user-configure property value out of the configuration 4321 * file e1000g.conf. 4322 * 4323 * Caller provides name of the property, a default value, a minimum 4324 * value, a maximum value and a pointer to the returned property 4325 * value. 4326 * 4327 * Return B_TRUE if the configured value of the property is not a default 4328 * value, otherwise return B_FALSE. 4329 */ 4330 static boolean_t 4331 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 4332 char *propname, /* name of the property */ 4333 int minval, /* minimum acceptable value */ 4334 int maxval, /* maximim acceptable value */ 4335 int defval, /* default value */ 4336 int *propvalue) /* property value return to caller */ 4337 { 4338 int propval; /* value returned for requested property */ 4339 int *props; /* point to array of properties returned */ 4340 uint_t nprops; /* number of property value returned */ 4341 boolean_t ret = B_TRUE; 4342 4343 /* 4344 * get the array of properties from the config file 4345 */ 4346 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 4347 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 4348 /* got some properties, test if we got enough */ 4349 if (Adapter->instance < nprops) { 4350 propval = props[Adapter->instance]; 4351 } else { 4352 /* not enough properties configured */ 4353 propval = defval; 4354 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4355 "Not Enough %s values found in e1000g.conf" 4356 " - set to %d\n", 4357 propname, propval); 4358 ret = B_FALSE; 4359 } 4360 4361 /* free memory allocated for properties */ 4362 ddi_prop_free(props); 4363 4364 } else { 4365 propval = defval; 4366 ret = B_FALSE; 4367 } 4368 4369 /* 4370 * enforce limits 4371 */ 4372 if (propval > maxval) { 4373 propval = maxval; 4374 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4375 "Too High %s value in e1000g.conf - set to %d\n", 4376 propname, propval); 4377 } 4378 4379 if (propval < minval) { 4380 propval = minval; 4381 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4382 "Too Low %s value in e1000g.conf - set to %d\n", 4383 propname, propval); 4384 } 4385 4386 *propvalue = propval; 4387 return (ret); 4388 } 4389 4390 static boolean_t 4391 e1000g_link_check(struct e1000g *Adapter) 4392 { 4393 uint16_t speed, duplex, phydata; 4394 boolean_t link_changed = B_FALSE; 4395 struct e1000_hw *hw; 4396 uint32_t reg_tarc; 4397 4398 hw = &Adapter->shared; 4399 4400 if (e1000g_link_up(Adapter)) { 4401 /* 4402 * The Link is up, check whether it was marked as down earlier 4403 */ 4404 if (Adapter->link_state != LINK_STATE_UP) { 4405 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 4406 Adapter->link_speed = speed; 4407 Adapter->link_duplex = duplex; 4408 Adapter->link_state = LINK_STATE_UP; 4409 link_changed = B_TRUE; 4410 4411 if (Adapter->link_speed == SPEED_1000) 4412 Adapter->stall_threshold = TX_STALL_TIME_2S; 4413 else 4414 Adapter->stall_threshold = TX_STALL_TIME_8S; 4415 4416 Adapter->tx_link_down_timeout = 0; 4417 4418 if ((hw->mac.type == e1000_82571) || 4419 (hw->mac.type == e1000_82572)) { 4420 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 4421 if (speed == SPEED_1000) 4422 reg_tarc |= (1 << 21); 4423 else 4424 reg_tarc &= ~(1 << 21); 4425 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 4426 } 4427 } 4428 Adapter->smartspeed = 0; 4429 } else { 4430 if (Adapter->link_state != LINK_STATE_DOWN) { 4431 Adapter->link_speed = 0; 4432 Adapter->link_duplex = 0; 4433 Adapter->link_state = LINK_STATE_DOWN; 4434 link_changed = B_TRUE; 4435 4436 /* 4437 * SmartSpeed workaround for Tabor/TanaX, When the 4438 * driver loses link disable auto master/slave 4439 * resolution. 4440 */ 4441 if (hw->phy.type == e1000_phy_igp) { 4442 (void) e1000_read_phy_reg(hw, 4443 PHY_1000T_CTRL, &phydata); 4444 phydata |= CR_1000T_MS_ENABLE; 4445 (void) e1000_write_phy_reg(hw, 4446 PHY_1000T_CTRL, phydata); 4447 } 4448 } else { 4449 e1000g_smartspeed(Adapter); 4450 } 4451 4452 if (Adapter->e1000g_state & E1000G_STARTED) { 4453 if (Adapter->tx_link_down_timeout < 4454 MAX_TX_LINK_DOWN_TIMEOUT) { 4455 Adapter->tx_link_down_timeout++; 4456 } else if (Adapter->tx_link_down_timeout == 4457 MAX_TX_LINK_DOWN_TIMEOUT) { 4458 e1000g_tx_clean(Adapter); 4459 Adapter->tx_link_down_timeout++; 4460 } 4461 } 4462 } 4463 4464 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4465 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4466 4467 return (link_changed); 4468 } 4469 4470 /* 4471 * e1000g_reset_link - Using the link properties to setup the link 4472 */ 4473 int 4474 e1000g_reset_link(struct e1000g *Adapter) 4475 { 4476 struct e1000_mac_info *mac; 4477 struct e1000_phy_info *phy; 4478 struct e1000_hw *hw; 4479 boolean_t invalid; 4480 4481 mac = &Adapter->shared.mac; 4482 phy = &Adapter->shared.phy; 4483 hw = &Adapter->shared; 4484 invalid = B_FALSE; 4485 4486 if (hw->phy.media_type != e1000_media_type_copper) 4487 goto out; 4488 4489 if (Adapter->param_adv_autoneg == 1) { 4490 mac->autoneg = B_TRUE; 4491 phy->autoneg_advertised = 0; 4492 4493 /* 4494 * 1000hdx is not supported for autonegotiation 4495 */ 4496 if (Adapter->param_adv_1000fdx == 1) 4497 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 4498 4499 if (Adapter->param_adv_100fdx == 1) 4500 phy->autoneg_advertised |= ADVERTISE_100_FULL; 4501 4502 if (Adapter->param_adv_100hdx == 1) 4503 phy->autoneg_advertised |= ADVERTISE_100_HALF; 4504 4505 if (Adapter->param_adv_10fdx == 1) 4506 phy->autoneg_advertised |= ADVERTISE_10_FULL; 4507 4508 if (Adapter->param_adv_10hdx == 1) 4509 phy->autoneg_advertised |= ADVERTISE_10_HALF; 4510 4511 if (phy->autoneg_advertised == 0) 4512 invalid = B_TRUE; 4513 } else { 4514 mac->autoneg = B_FALSE; 4515 4516 /* 4517 * For Intel copper cards, 1000fdx and 1000hdx are not 4518 * supported for forced link 4519 */ 4520 if (Adapter->param_adv_100fdx == 1) 4521 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4522 else if (Adapter->param_adv_100hdx == 1) 4523 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4524 else if (Adapter->param_adv_10fdx == 1) 4525 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4526 else if (Adapter->param_adv_10hdx == 1) 4527 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4528 else 4529 invalid = B_TRUE; 4530 4531 } 4532 4533 if (invalid) { 4534 e1000g_log(Adapter, CE_WARN, 4535 "Invalid link settings. Setup link to " 4536 "support autonegotiation with all link capabilities."); 4537 mac->autoneg = B_TRUE; 4538 phy->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 4539 } 4540 4541 out: 4542 return (e1000_setup_link(&Adapter->shared)); 4543 } 4544 4545 static void 4546 e1000g_timer_tx_resched(struct e1000g *Adapter) 4547 { 4548 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 4549 4550 rw_enter(&Adapter->chip_lock, RW_READER); 4551 4552 if (tx_ring->resched_needed && 4553 ((ddi_get_lbolt() - tx_ring->resched_timestamp) > 4554 drv_usectohz(1000000)) && 4555 (Adapter->e1000g_state & E1000G_STARTED) && 4556 (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) { 4557 tx_ring->resched_needed = B_FALSE; 4558 mac_tx_update(Adapter->mh); 4559 E1000G_STAT(tx_ring->stat_reschedule); 4560 E1000G_STAT(tx_ring->stat_timer_reschedule); 4561 } 4562 4563 rw_exit(&Adapter->chip_lock); 4564 } 4565 4566 static void 4567 e1000g_local_timer(void *ws) 4568 { 4569 struct e1000g *Adapter = (struct e1000g *)ws; 4570 struct e1000_hw *hw; 4571 e1000g_ether_addr_t ether_addr; 4572 boolean_t link_changed; 4573 4574 hw = &Adapter->shared; 4575 4576 if (Adapter->e1000g_state & E1000G_ERROR) { 4577 rw_enter(&Adapter->chip_lock, RW_WRITER); 4578 Adapter->e1000g_state &= ~E1000G_ERROR; 4579 rw_exit(&Adapter->chip_lock); 4580 4581 Adapter->reset_count++; 4582 if (e1000g_global_reset(Adapter)) { 4583 ddi_fm_service_impact(Adapter->dip, 4584 DDI_SERVICE_RESTORED); 4585 e1000g_timer_tx_resched(Adapter); 4586 } else 4587 ddi_fm_service_impact(Adapter->dip, 4588 DDI_SERVICE_LOST); 4589 return; 4590 } 4591 4592 if (e1000g_stall_check(Adapter)) { 4593 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4594 "Tx stall detected. Activate automatic recovery.\n"); 4595 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 4596 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 4597 Adapter->reset_count++; 4598 if (e1000g_reset_adapter(Adapter)) { 4599 ddi_fm_service_impact(Adapter->dip, 4600 DDI_SERVICE_RESTORED); 4601 e1000g_timer_tx_resched(Adapter); 4602 } 4603 return; 4604 } 4605 4606 link_changed = B_FALSE; 4607 rw_enter(&Adapter->chip_lock, RW_READER); 4608 if (Adapter->link_complete) 4609 link_changed = e1000g_link_check(Adapter); 4610 rw_exit(&Adapter->chip_lock); 4611 4612 if (link_changed) { 4613 if (!Adapter->reset_flag && 4614 (Adapter->e1000g_state & E1000G_STARTED) && 4615 !(Adapter->e1000g_state & E1000G_SUSPENDED)) 4616 mac_link_update(Adapter->mh, Adapter->link_state); 4617 if (Adapter->link_state == LINK_STATE_UP) 4618 Adapter->reset_flag = B_FALSE; 4619 } 4620 /* 4621 * Workaround for esb2. Data stuck in fifo on a link 4622 * down event. Reset the adapter to recover it. 4623 */ 4624 if (Adapter->esb2_workaround) { 4625 Adapter->esb2_workaround = B_FALSE; 4626 (void) e1000g_reset_adapter(Adapter); 4627 return; 4628 } 4629 4630 /* 4631 * With 82571 controllers, any locally administered address will 4632 * be overwritten when there is a reset on the other port. 4633 * Detect this circumstance and correct it. 4634 */ 4635 if ((hw->mac.type == e1000_82571) && 4636 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 4637 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 4638 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 4639 4640 ether_addr.reg.low = ntohl(ether_addr.reg.low); 4641 ether_addr.reg.high = ntohl(ether_addr.reg.high); 4642 4643 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 4644 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 4645 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 4646 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 4647 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 4648 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 4649 (void) e1000_rar_set(hw, hw->mac.addr, 0); 4650 } 4651 } 4652 4653 /* 4654 * Long TTL workaround for 82541/82547 4655 */ 4656 (void) e1000_igp_ttl_workaround_82547(hw); 4657 4658 /* 4659 * Check for Adaptive IFS settings If there are lots of collisions 4660 * change the value in steps... 4661 * These properties should only be set for 10/100 4662 */ 4663 if ((hw->phy.media_type == e1000_media_type_copper) && 4664 ((Adapter->link_speed == SPEED_100) || 4665 (Adapter->link_speed == SPEED_10))) { 4666 e1000_update_adaptive(hw); 4667 } 4668 /* 4669 * Set Timer Interrupts 4670 */ 4671 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 4672 4673 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4674 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4675 else 4676 e1000g_timer_tx_resched(Adapter); 4677 4678 restart_watchdog_timer(Adapter); 4679 } 4680 4681 /* 4682 * The function e1000g_link_timer() is called when the timer for link setup 4683 * is expired, which indicates the completion of the link setup. The link 4684 * state will not be updated until the link setup is completed. And the 4685 * link state will not be sent to the upper layer through mac_link_update() 4686 * in this function. It will be updated in the local timer routine or the 4687 * interrupt service routine after the interface is started (plumbed). 4688 */ 4689 static void 4690 e1000g_link_timer(void *arg) 4691 { 4692 struct e1000g *Adapter = (struct e1000g *)arg; 4693 4694 mutex_enter(&Adapter->link_lock); 4695 Adapter->link_complete = B_TRUE; 4696 Adapter->link_tid = 0; 4697 mutex_exit(&Adapter->link_lock); 4698 } 4699 4700 /* 4701 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 4702 * 4703 * This function read the forced speed and duplex for 10/100 Mbps speeds 4704 * and also for 1000 Mbps speeds from the e1000g.conf file 4705 */ 4706 static void 4707 e1000g_force_speed_duplex(struct e1000g *Adapter) 4708 { 4709 int forced; 4710 int propval; 4711 struct e1000_mac_info *mac = &Adapter->shared.mac; 4712 struct e1000_phy_info *phy = &Adapter->shared.phy; 4713 4714 /* 4715 * get value out of config file 4716 */ 4717 (void) e1000g_get_prop(Adapter, "ForceSpeedDuplex", 4718 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY, &forced); 4719 4720 switch (forced) { 4721 case GDIAG_10_HALF: 4722 /* 4723 * Disable Auto Negotiation 4724 */ 4725 mac->autoneg = B_FALSE; 4726 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4727 break; 4728 case GDIAG_10_FULL: 4729 /* 4730 * Disable Auto Negotiation 4731 */ 4732 mac->autoneg = B_FALSE; 4733 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4734 break; 4735 case GDIAG_100_HALF: 4736 /* 4737 * Disable Auto Negotiation 4738 */ 4739 mac->autoneg = B_FALSE; 4740 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4741 break; 4742 case GDIAG_100_FULL: 4743 /* 4744 * Disable Auto Negotiation 4745 */ 4746 mac->autoneg = B_FALSE; 4747 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4748 break; 4749 case GDIAG_1000_FULL: 4750 /* 4751 * The gigabit spec requires autonegotiation. Therefore, 4752 * when the user wants to force the speed to 1000Mbps, we 4753 * enable AutoNeg, but only allow the harware to advertise 4754 * 1000Mbps. This is different from 10/100 operation, where 4755 * we are allowed to link without any negotiation. 4756 */ 4757 mac->autoneg = B_TRUE; 4758 phy->autoneg_advertised = ADVERTISE_1000_FULL; 4759 break; 4760 default: /* obey the setting of AutoNegAdvertised */ 4761 mac->autoneg = B_TRUE; 4762 (void) e1000g_get_prop(Adapter, "AutoNegAdvertised", 4763 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 4764 AUTONEG_ADVERTISE_SPEED_DEFAULT, &propval); 4765 phy->autoneg_advertised = (uint16_t)propval; 4766 break; 4767 } /* switch */ 4768 } 4769 4770 /* 4771 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 4772 * 4773 * This function reads MaxFrameSize from e1000g.conf 4774 */ 4775 static void 4776 e1000g_get_max_frame_size(struct e1000g *Adapter) 4777 { 4778 int max_frame; 4779 4780 /* 4781 * get value out of config file 4782 */ 4783 (void) e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0, 4784 &max_frame); 4785 4786 switch (max_frame) { 4787 case 0: 4788 Adapter->default_mtu = ETHERMTU; 4789 break; 4790 case 1: 4791 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 4792 sizeof (struct ether_vlan_header) - ETHERFCSL; 4793 break; 4794 case 2: 4795 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 4796 sizeof (struct ether_vlan_header) - ETHERFCSL; 4797 break; 4798 case 3: 4799 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 4800 sizeof (struct ether_vlan_header) - ETHERFCSL; 4801 break; 4802 default: 4803 Adapter->default_mtu = ETHERMTU; 4804 break; 4805 } /* switch */ 4806 4807 /* 4808 * If the user configed MTU is larger than the deivce's maximum MTU, 4809 * the MTU is set to the deivce's maximum value. 4810 */ 4811 if (Adapter->default_mtu > Adapter->max_mtu) 4812 Adapter->default_mtu = Adapter->max_mtu; 4813 4814 Adapter->max_frame_size = e1000g_mtu2maxframe(Adapter->default_mtu); 4815 } 4816 4817 /* 4818 * e1000g_pch_limits - Apply limits of the PCH silicon type 4819 * 4820 * At any frame size larger than the ethernet default, 4821 * prevent linking at 10/100 speeds. 4822 */ 4823 static void 4824 e1000g_pch_limits(struct e1000g *Adapter) 4825 { 4826 struct e1000_hw *hw = &Adapter->shared; 4827 4828 /* only applies to PCH silicon type */ 4829 if (hw->mac.type != e1000_pchlan && hw->mac.type != e1000_pch2lan) 4830 return; 4831 4832 /* only applies to frames larger than ethernet default */ 4833 if (Adapter->max_frame_size > DEFAULT_FRAME_SIZE) { 4834 hw->mac.autoneg = B_TRUE; 4835 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL; 4836 4837 Adapter->param_adv_autoneg = 1; 4838 Adapter->param_adv_1000fdx = 1; 4839 4840 Adapter->param_adv_100fdx = 0; 4841 Adapter->param_adv_100hdx = 0; 4842 Adapter->param_adv_10fdx = 0; 4843 Adapter->param_adv_10hdx = 0; 4844 4845 e1000g_param_sync(Adapter); 4846 } 4847 } 4848 4849 /* 4850 * e1000g_mtu2maxframe - convert given MTU to maximum frame size 4851 */ 4852 static uint32_t 4853 e1000g_mtu2maxframe(uint32_t mtu) 4854 { 4855 uint32_t maxframe; 4856 4857 maxframe = mtu + sizeof (struct ether_vlan_header) + ETHERFCSL; 4858 4859 return (maxframe); 4860 } 4861 4862 static void 4863 arm_watchdog_timer(struct e1000g *Adapter) 4864 { 4865 Adapter->watchdog_tid = 4866 timeout(e1000g_local_timer, 4867 (void *)Adapter, 1 * drv_usectohz(1000000)); 4868 } 4869 #pragma inline(arm_watchdog_timer) 4870 4871 static void 4872 enable_watchdog_timer(struct e1000g *Adapter) 4873 { 4874 mutex_enter(&Adapter->watchdog_lock); 4875 4876 if (!Adapter->watchdog_timer_enabled) { 4877 Adapter->watchdog_timer_enabled = B_TRUE; 4878 Adapter->watchdog_timer_started = B_TRUE; 4879 arm_watchdog_timer(Adapter); 4880 } 4881 4882 mutex_exit(&Adapter->watchdog_lock); 4883 } 4884 4885 static void 4886 disable_watchdog_timer(struct e1000g *Adapter) 4887 { 4888 timeout_id_t tid; 4889 4890 mutex_enter(&Adapter->watchdog_lock); 4891 4892 Adapter->watchdog_timer_enabled = B_FALSE; 4893 Adapter->watchdog_timer_started = B_FALSE; 4894 tid = Adapter->watchdog_tid; 4895 Adapter->watchdog_tid = 0; 4896 4897 mutex_exit(&Adapter->watchdog_lock); 4898 4899 if (tid != 0) 4900 (void) untimeout(tid); 4901 } 4902 4903 static void 4904 start_watchdog_timer(struct e1000g *Adapter) 4905 { 4906 mutex_enter(&Adapter->watchdog_lock); 4907 4908 if (Adapter->watchdog_timer_enabled) { 4909 if (!Adapter->watchdog_timer_started) { 4910 Adapter->watchdog_timer_started = B_TRUE; 4911 arm_watchdog_timer(Adapter); 4912 } 4913 } 4914 4915 mutex_exit(&Adapter->watchdog_lock); 4916 } 4917 4918 static void 4919 restart_watchdog_timer(struct e1000g *Adapter) 4920 { 4921 mutex_enter(&Adapter->watchdog_lock); 4922 4923 if (Adapter->watchdog_timer_started) 4924 arm_watchdog_timer(Adapter); 4925 4926 mutex_exit(&Adapter->watchdog_lock); 4927 } 4928 4929 static void 4930 stop_watchdog_timer(struct e1000g *Adapter) 4931 { 4932 timeout_id_t tid; 4933 4934 mutex_enter(&Adapter->watchdog_lock); 4935 4936 Adapter->watchdog_timer_started = B_FALSE; 4937 tid = Adapter->watchdog_tid; 4938 Adapter->watchdog_tid = 0; 4939 4940 mutex_exit(&Adapter->watchdog_lock); 4941 4942 if (tid != 0) 4943 (void) untimeout(tid); 4944 } 4945 4946 static void 4947 stop_link_timer(struct e1000g *Adapter) 4948 { 4949 timeout_id_t tid; 4950 4951 /* Disable the link timer */ 4952 mutex_enter(&Adapter->link_lock); 4953 4954 tid = Adapter->link_tid; 4955 Adapter->link_tid = 0; 4956 4957 mutex_exit(&Adapter->link_lock); 4958 4959 if (tid != 0) 4960 (void) untimeout(tid); 4961 } 4962 4963 static void 4964 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4965 { 4966 timeout_id_t tid; 4967 4968 /* Disable the tx timer for 82547 chipset */ 4969 mutex_enter(&tx_ring->tx_lock); 4970 4971 tx_ring->timer_enable_82547 = B_FALSE; 4972 tid = tx_ring->timer_id_82547; 4973 tx_ring->timer_id_82547 = 0; 4974 4975 mutex_exit(&tx_ring->tx_lock); 4976 4977 if (tid != 0) 4978 (void) untimeout(tid); 4979 } 4980 4981 void 4982 e1000g_clear_interrupt(struct e1000g *Adapter) 4983 { 4984 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4985 0xffffffff & ~E1000_IMS_RXSEQ); 4986 } 4987 4988 void 4989 e1000g_mask_interrupt(struct e1000g *Adapter) 4990 { 4991 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4992 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4993 4994 if (Adapter->tx_intr_enable) 4995 e1000g_mask_tx_interrupt(Adapter); 4996 } 4997 4998 /* 4999 * This routine is called by e1000g_quiesce(), therefore must not block. 5000 */ 5001 void 5002 e1000g_clear_all_interrupts(struct e1000g *Adapter) 5003 { 5004 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 5005 } 5006 5007 void 5008 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 5009 { 5010 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 5011 } 5012 5013 void 5014 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 5015 { 5016 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 5017 } 5018 5019 static void 5020 e1000g_smartspeed(struct e1000g *Adapter) 5021 { 5022 struct e1000_hw *hw = &Adapter->shared; 5023 uint16_t phy_status; 5024 uint16_t phy_ctrl; 5025 5026 /* 5027 * If we're not T-or-T, or we're not autoneg'ing, or we're not 5028 * advertising 1000Full, we don't even use the workaround 5029 */ 5030 if ((hw->phy.type != e1000_phy_igp) || 5031 !hw->mac.autoneg || 5032 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 5033 return; 5034 5035 /* 5036 * True if this is the first call of this function or after every 5037 * 30 seconds of not having link 5038 */ 5039 if (Adapter->smartspeed == 0) { 5040 /* 5041 * If Master/Slave config fault is asserted twice, we 5042 * assume back-to-back 5043 */ 5044 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 5045 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 5046 return; 5047 5048 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 5049 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 5050 return; 5051 /* 5052 * We're assuming back-2-back because our status register 5053 * insists! there's a fault in the master/slave 5054 * relationship that was "negotiated" 5055 */ 5056 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 5057 /* 5058 * Is the phy configured for manual configuration of 5059 * master/slave? 5060 */ 5061 if (phy_ctrl & CR_1000T_MS_ENABLE) { 5062 /* 5063 * Yes. Then disable manual configuration (enable 5064 * auto configuration) of master/slave 5065 */ 5066 phy_ctrl &= ~CR_1000T_MS_ENABLE; 5067 (void) e1000_write_phy_reg(hw, 5068 PHY_1000T_CTRL, phy_ctrl); 5069 /* 5070 * Effectively starting the clock 5071 */ 5072 Adapter->smartspeed++; 5073 /* 5074 * Restart autonegotiation 5075 */ 5076 if (!e1000_phy_setup_autoneg(hw) && 5077 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 5078 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 5079 MII_CR_RESTART_AUTO_NEG); 5080 (void) e1000_write_phy_reg(hw, 5081 PHY_CONTROL, phy_ctrl); 5082 } 5083 } 5084 return; 5085 /* 5086 * Has 6 seconds transpired still without link? Remember, 5087 * you should reset the smartspeed counter once you obtain 5088 * link 5089 */ 5090 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 5091 /* 5092 * Yes. Remember, we did at the start determine that 5093 * there's a master/slave configuration fault, so we're 5094 * still assuming there's someone on the other end, but we 5095 * just haven't yet been able to talk to it. We then 5096 * re-enable auto configuration of master/slave to see if 5097 * we're running 2/3 pair cables. 5098 */ 5099 /* 5100 * If still no link, perhaps using 2/3 pair cable 5101 */ 5102 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 5103 phy_ctrl |= CR_1000T_MS_ENABLE; 5104 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 5105 /* 5106 * Restart autoneg with phy enabled for manual 5107 * configuration of master/slave 5108 */ 5109 if (!e1000_phy_setup_autoneg(hw) && 5110 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 5111 phy_ctrl |= 5112 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 5113 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 5114 } 5115 /* 5116 * Hopefully, there are no more faults and we've obtained 5117 * link as a result. 5118 */ 5119 } 5120 /* 5121 * Restart process after E1000_SMARTSPEED_MAX iterations (30 5122 * seconds) 5123 */ 5124 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 5125 Adapter->smartspeed = 0; 5126 } 5127 5128 static boolean_t 5129 is_valid_mac_addr(uint8_t *mac_addr) 5130 { 5131 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 5132 const uint8_t addr_test2[6] = 5133 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 5134 5135 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 5136 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 5137 return (B_FALSE); 5138 5139 return (B_TRUE); 5140 } 5141 5142 /* 5143 * e1000g_stall_check - check for tx stall 5144 * 5145 * This function checks if the adapter is stalled (in transmit). 5146 * 5147 * It is called each time the watchdog timeout is invoked. 5148 * If the transmit descriptor reclaim continuously fails, 5149 * the watchdog value will increment by 1. If the watchdog 5150 * value exceeds the threshold, the adapter is assumed to 5151 * have stalled and need to be reset. 5152 */ 5153 static boolean_t 5154 e1000g_stall_check(struct e1000g *Adapter) 5155 { 5156 e1000g_tx_ring_t *tx_ring; 5157 5158 tx_ring = Adapter->tx_ring; 5159 5160 if (Adapter->link_state != LINK_STATE_UP) 5161 return (B_FALSE); 5162 5163 (void) e1000g_recycle(tx_ring); 5164 5165 if (Adapter->stall_flag) 5166 return (B_TRUE); 5167 5168 return (B_FALSE); 5169 } 5170 5171 #ifdef E1000G_DEBUG 5172 static enum ioc_reply 5173 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 5174 { 5175 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 5176 e1000g_peekpoke_t *ppd; 5177 uint64_t mem_va; 5178 uint64_t maxoff; 5179 boolean_t peek; 5180 5181 switch (iocp->ioc_cmd) { 5182 5183 case E1000G_IOC_REG_PEEK: 5184 peek = B_TRUE; 5185 break; 5186 5187 case E1000G_IOC_REG_POKE: 5188 peek = B_FALSE; 5189 break; 5190 5191 deault: 5192 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 5193 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 5194 iocp->ioc_cmd); 5195 return (IOC_INVAL); 5196 } 5197 5198 /* 5199 * Validate format of ioctl 5200 */ 5201 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 5202 return (IOC_INVAL); 5203 if (mp->b_cont == NULL) 5204 return (IOC_INVAL); 5205 5206 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 5207 5208 /* 5209 * Validate request parameters 5210 */ 5211 switch (ppd->pp_acc_space) { 5212 5213 default: 5214 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 5215 "e1000g_diag_ioctl: invalid access space 0x%X\n", 5216 ppd->pp_acc_space); 5217 return (IOC_INVAL); 5218 5219 case E1000G_PP_SPACE_REG: 5220 /* 5221 * Memory-mapped I/O space 5222 */ 5223 ASSERT(ppd->pp_acc_size == 4); 5224 if (ppd->pp_acc_size != 4) 5225 return (IOC_INVAL); 5226 5227 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5228 return (IOC_INVAL); 5229 5230 mem_va = 0; 5231 maxoff = 0x10000; 5232 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 5233 break; 5234 5235 case E1000G_PP_SPACE_E1000G: 5236 /* 5237 * E1000g data structure! 5238 */ 5239 mem_va = (uintptr_t)e1000gp; 5240 maxoff = sizeof (struct e1000g); 5241 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 5242 break; 5243 5244 } 5245 5246 if (ppd->pp_acc_offset >= maxoff) 5247 return (IOC_INVAL); 5248 5249 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 5250 return (IOC_INVAL); 5251 5252 /* 5253 * All OK - go! 5254 */ 5255 ppd->pp_acc_offset += mem_va; 5256 (*ppfn)(e1000gp, ppd); 5257 return (peek ? IOC_REPLY : IOC_ACK); 5258 } 5259 5260 static void 5261 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 5262 { 5263 ddi_acc_handle_t handle; 5264 uint32_t *regaddr; 5265 5266 handle = e1000gp->osdep.reg_handle; 5267 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 5268 (uintptr_t)ppd->pp_acc_offset); 5269 5270 ppd->pp_acc_data = ddi_get32(handle, regaddr); 5271 } 5272 5273 static void 5274 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 5275 { 5276 ddi_acc_handle_t handle; 5277 uint32_t *regaddr; 5278 uint32_t value; 5279 5280 handle = e1000gp->osdep.reg_handle; 5281 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 5282 (uintptr_t)ppd->pp_acc_offset); 5283 value = (uint32_t)ppd->pp_acc_data; 5284 5285 ddi_put32(handle, regaddr, value); 5286 } 5287 5288 static void 5289 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 5290 { 5291 uint64_t value; 5292 void *vaddr; 5293 5294 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5295 5296 switch (ppd->pp_acc_size) { 5297 case 1: 5298 value = *(uint8_t *)vaddr; 5299 break; 5300 5301 case 2: 5302 value = *(uint16_t *)vaddr; 5303 break; 5304 5305 case 4: 5306 value = *(uint32_t *)vaddr; 5307 break; 5308 5309 case 8: 5310 value = *(uint64_t *)vaddr; 5311 break; 5312 } 5313 5314 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 5315 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 5316 (void *)e1000gp, (void *)ppd, value, vaddr); 5317 5318 ppd->pp_acc_data = value; 5319 } 5320 5321 static void 5322 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 5323 { 5324 uint64_t value; 5325 void *vaddr; 5326 5327 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5328 value = ppd->pp_acc_data; 5329 5330 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 5331 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 5332 (void *)e1000gp, (void *)ppd, value, vaddr); 5333 5334 switch (ppd->pp_acc_size) { 5335 case 1: 5336 *(uint8_t *)vaddr = (uint8_t)value; 5337 break; 5338 5339 case 2: 5340 *(uint16_t *)vaddr = (uint16_t)value; 5341 break; 5342 5343 case 4: 5344 *(uint32_t *)vaddr = (uint32_t)value; 5345 break; 5346 5347 case 8: 5348 *(uint64_t *)vaddr = (uint64_t)value; 5349 break; 5350 } 5351 } 5352 #endif 5353 5354 /* 5355 * Loopback Support 5356 */ 5357 static lb_property_t lb_normal = 5358 { normal, "normal", E1000G_LB_NONE }; 5359 static lb_property_t lb_external1000 = 5360 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 5361 static lb_property_t lb_external100 = 5362 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 5363 static lb_property_t lb_external10 = 5364 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 5365 static lb_property_t lb_phy = 5366 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 5367 5368 static enum ioc_reply 5369 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 5370 { 5371 lb_info_sz_t *lbsp; 5372 lb_property_t *lbpp; 5373 struct e1000_hw *hw; 5374 uint32_t *lbmp; 5375 uint32_t size; 5376 uint32_t value; 5377 5378 hw = &Adapter->shared; 5379 5380 if (mp->b_cont == NULL) 5381 return (IOC_INVAL); 5382 5383 if (!e1000g_check_loopback_support(hw)) { 5384 e1000g_log(NULL, CE_WARN, 5385 "Loopback is not supported on e1000g%d", Adapter->instance); 5386 return (IOC_INVAL); 5387 } 5388 5389 switch (iocp->ioc_cmd) { 5390 default: 5391 return (IOC_INVAL); 5392 5393 case LB_GET_INFO_SIZE: 5394 size = sizeof (lb_info_sz_t); 5395 if (iocp->ioc_count != size) 5396 return (IOC_INVAL); 5397 5398 rw_enter(&Adapter->chip_lock, RW_WRITER); 5399 e1000g_get_phy_state(Adapter); 5400 5401 /* 5402 * Workaround for hardware faults. In order to get a stable 5403 * state of phy, we will wait for a specific interval and 5404 * try again. The time delay is an experiential value based 5405 * on our testing. 5406 */ 5407 msec_delay(100); 5408 e1000g_get_phy_state(Adapter); 5409 rw_exit(&Adapter->chip_lock); 5410 5411 value = sizeof (lb_normal); 5412 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5413 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5414 (hw->phy.media_type == e1000_media_type_fiber) || 5415 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5416 value += sizeof (lb_phy); 5417 switch (hw->mac.type) { 5418 case e1000_82571: 5419 case e1000_82572: 5420 case e1000_80003es2lan: 5421 value += sizeof (lb_external1000); 5422 break; 5423 } 5424 } 5425 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5426 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5427 value += sizeof (lb_external100); 5428 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5429 value += sizeof (lb_external10); 5430 5431 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 5432 *lbsp = value; 5433 break; 5434 5435 case LB_GET_INFO: 5436 value = sizeof (lb_normal); 5437 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5438 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5439 (hw->phy.media_type == e1000_media_type_fiber) || 5440 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5441 value += sizeof (lb_phy); 5442 switch (hw->mac.type) { 5443 case e1000_82571: 5444 case e1000_82572: 5445 case e1000_80003es2lan: 5446 value += sizeof (lb_external1000); 5447 break; 5448 } 5449 } 5450 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5451 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5452 value += sizeof (lb_external100); 5453 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5454 value += sizeof (lb_external10); 5455 5456 size = value; 5457 if (iocp->ioc_count != size) 5458 return (IOC_INVAL); 5459 5460 value = 0; 5461 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 5462 lbpp[value++] = lb_normal; 5463 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5464 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5465 (hw->phy.media_type == e1000_media_type_fiber) || 5466 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5467 lbpp[value++] = lb_phy; 5468 switch (hw->mac.type) { 5469 case e1000_82571: 5470 case e1000_82572: 5471 case e1000_80003es2lan: 5472 lbpp[value++] = lb_external1000; 5473 break; 5474 } 5475 } 5476 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5477 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5478 lbpp[value++] = lb_external100; 5479 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5480 lbpp[value++] = lb_external10; 5481 break; 5482 5483 case LB_GET_MODE: 5484 size = sizeof (uint32_t); 5485 if (iocp->ioc_count != size) 5486 return (IOC_INVAL); 5487 5488 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 5489 *lbmp = Adapter->loopback_mode; 5490 break; 5491 5492 case LB_SET_MODE: 5493 size = 0; 5494 if (iocp->ioc_count != sizeof (uint32_t)) 5495 return (IOC_INVAL); 5496 5497 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 5498 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 5499 return (IOC_INVAL); 5500 break; 5501 } 5502 5503 iocp->ioc_count = size; 5504 iocp->ioc_error = 0; 5505 5506 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 5507 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 5508 return (IOC_INVAL); 5509 } 5510 5511 return (IOC_REPLY); 5512 } 5513 5514 static boolean_t 5515 e1000g_check_loopback_support(struct e1000_hw *hw) 5516 { 5517 switch (hw->mac.type) { 5518 case e1000_82540: 5519 case e1000_82545: 5520 case e1000_82545_rev_3: 5521 case e1000_82546: 5522 case e1000_82546_rev_3: 5523 case e1000_82541: 5524 case e1000_82541_rev_2: 5525 case e1000_82547: 5526 case e1000_82547_rev_2: 5527 case e1000_82571: 5528 case e1000_82572: 5529 case e1000_82573: 5530 case e1000_82574: 5531 case e1000_80003es2lan: 5532 case e1000_ich9lan: 5533 case e1000_ich10lan: 5534 return (B_TRUE); 5535 } 5536 return (B_FALSE); 5537 } 5538 5539 static boolean_t 5540 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 5541 { 5542 struct e1000_hw *hw; 5543 int i, times; 5544 boolean_t link_up; 5545 5546 if (mode == Adapter->loopback_mode) 5547 return (B_TRUE); 5548 5549 hw = &Adapter->shared; 5550 times = 0; 5551 5552 Adapter->loopback_mode = mode; 5553 5554 if (mode == E1000G_LB_NONE) { 5555 /* Reset the chip */ 5556 hw->phy.autoneg_wait_to_complete = B_TRUE; 5557 (void) e1000g_reset_adapter(Adapter); 5558 hw->phy.autoneg_wait_to_complete = B_FALSE; 5559 return (B_TRUE); 5560 } 5561 5562 again: 5563 5564 rw_enter(&Adapter->chip_lock, RW_WRITER); 5565 5566 switch (mode) { 5567 default: 5568 rw_exit(&Adapter->chip_lock); 5569 return (B_FALSE); 5570 5571 case E1000G_LB_EXTERNAL_1000: 5572 e1000g_set_external_loopback_1000(Adapter); 5573 break; 5574 5575 case E1000G_LB_EXTERNAL_100: 5576 e1000g_set_external_loopback_100(Adapter); 5577 break; 5578 5579 case E1000G_LB_EXTERNAL_10: 5580 e1000g_set_external_loopback_10(Adapter); 5581 break; 5582 5583 case E1000G_LB_INTERNAL_PHY: 5584 e1000g_set_internal_loopback(Adapter); 5585 break; 5586 } 5587 5588 times++; 5589 5590 rw_exit(&Adapter->chip_lock); 5591 5592 /* Wait for link up */ 5593 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 5594 msec_delay(100); 5595 5596 rw_enter(&Adapter->chip_lock, RW_WRITER); 5597 5598 link_up = e1000g_link_up(Adapter); 5599 5600 rw_exit(&Adapter->chip_lock); 5601 5602 if (!link_up) { 5603 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5604 "Failed to get the link up"); 5605 if (times < 2) { 5606 /* Reset the link */ 5607 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5608 "Reset the link ..."); 5609 (void) e1000g_reset_adapter(Adapter); 5610 goto again; 5611 } 5612 5613 /* 5614 * Reset driver to loopback none when set loopback failed 5615 * for the second time. 5616 */ 5617 Adapter->loopback_mode = E1000G_LB_NONE; 5618 5619 /* Reset the chip */ 5620 hw->phy.autoneg_wait_to_complete = B_TRUE; 5621 (void) e1000g_reset_adapter(Adapter); 5622 hw->phy.autoneg_wait_to_complete = B_FALSE; 5623 5624 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5625 "Set loopback mode failed, reset to loopback none"); 5626 5627 return (B_FALSE); 5628 } 5629 5630 return (B_TRUE); 5631 } 5632 5633 /* 5634 * The following loopback settings are from Intel's technical 5635 * document - "How To Loopback". All the register settings and 5636 * time delay values are directly inherited from the document 5637 * without more explanations available. 5638 */ 5639 static void 5640 e1000g_set_internal_loopback(struct e1000g *Adapter) 5641 { 5642 struct e1000_hw *hw; 5643 uint32_t ctrl; 5644 uint32_t status; 5645 uint16_t phy_ctrl; 5646 uint16_t phy_reg; 5647 uint32_t txcw; 5648 5649 hw = &Adapter->shared; 5650 5651 /* Disable Smart Power Down */ 5652 phy_spd_state(hw, B_FALSE); 5653 5654 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 5655 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 5656 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 5657 5658 switch (hw->mac.type) { 5659 case e1000_82540: 5660 case e1000_82545: 5661 case e1000_82545_rev_3: 5662 case e1000_82546: 5663 case e1000_82546_rev_3: 5664 case e1000_82573: 5665 /* Auto-MDI/MDIX off */ 5666 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 5667 /* Reset PHY to update Auto-MDI/MDIX */ 5668 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5669 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 5670 /* Reset PHY to auto-neg off and force 1000 */ 5671 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5672 phy_ctrl | MII_CR_RESET); 5673 /* 5674 * Disable PHY receiver for 82540/545/546 and 82573 Family. 5675 * See comments above e1000g_set_internal_loopback() for the 5676 * background. 5677 */ 5678 (void) e1000_write_phy_reg(hw, 29, 0x001F); 5679 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 5680 (void) e1000_write_phy_reg(hw, 29, 0x001A); 5681 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 5682 break; 5683 case e1000_80003es2lan: 5684 /* Force Link Up */ 5685 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 5686 0x1CC); 5687 /* Sets PCS loopback at 1Gbs */ 5688 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 5689 0x1046); 5690 break; 5691 } 5692 5693 /* 5694 * The following registers should be set for e1000_phy_bm phy type. 5695 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy. 5696 * For others, we do not need to set these registers. 5697 */ 5698 if (hw->phy.type == e1000_phy_bm) { 5699 /* Set Default MAC Interface speed to 1GB */ 5700 (void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg); 5701 phy_reg &= ~0x0007; 5702 phy_reg |= 0x006; 5703 (void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg); 5704 /* Assert SW reset for above settings to take effect */ 5705 (void) e1000_phy_commit(hw); 5706 msec_delay(1); 5707 /* Force Full Duplex */ 5708 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5709 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5710 phy_reg | 0x000C); 5711 /* Set Link Up (in force link) */ 5712 (void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg); 5713 (void) e1000_write_phy_reg(hw, PHY_REG(776, 16), 5714 phy_reg | 0x0040); 5715 /* Force Link */ 5716 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5717 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5718 phy_reg | 0x0040); 5719 /* Set Early Link Enable */ 5720 (void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg); 5721 (void) e1000_write_phy_reg(hw, PHY_REG(769, 20), 5722 phy_reg | 0x0400); 5723 } 5724 5725 /* Set loopback */ 5726 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 5727 5728 msec_delay(250); 5729 5730 /* Now set up the MAC to the same speed/duplex as the PHY. */ 5731 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5732 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5733 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5734 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5735 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 5736 E1000_CTRL_FD); /* Force Duplex to FULL */ 5737 5738 switch (hw->mac.type) { 5739 case e1000_82540: 5740 case e1000_82545: 5741 case e1000_82545_rev_3: 5742 case e1000_82546: 5743 case e1000_82546_rev_3: 5744 /* 5745 * For some serdes we'll need to commit the writes now 5746 * so that the status is updated on link 5747 */ 5748 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 5749 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5750 msec_delay(100); 5751 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5752 } 5753 5754 if (hw->phy.media_type == e1000_media_type_copper) { 5755 /* Invert Loss of Signal */ 5756 ctrl |= E1000_CTRL_ILOS; 5757 } else { 5758 /* Set ILOS on fiber nic if half duplex is detected */ 5759 status = E1000_READ_REG(hw, E1000_STATUS); 5760 if ((status & E1000_STATUS_FD) == 0) 5761 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5762 } 5763 break; 5764 5765 case e1000_82571: 5766 case e1000_82572: 5767 /* 5768 * The fiber/SerDes versions of this adapter do not contain an 5769 * accessible PHY. Therefore, loopback beyond MAC must be done 5770 * using SerDes analog loopback. 5771 */ 5772 if (hw->phy.media_type != e1000_media_type_copper) { 5773 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5774 txcw = E1000_READ_REG(hw, E1000_TXCW); 5775 txcw &= ~((uint32_t)1 << 31); 5776 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5777 5778 /* 5779 * Write 0x410 to Serdes Control register 5780 * to enable Serdes analog loopback 5781 */ 5782 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5783 msec_delay(10); 5784 } 5785 5786 status = E1000_READ_REG(hw, E1000_STATUS); 5787 /* Set ILOS on fiber nic if half duplex is detected */ 5788 if ((hw->phy.media_type == e1000_media_type_fiber) && 5789 ((status & E1000_STATUS_FD) == 0 || 5790 (status & E1000_STATUS_LU) == 0)) 5791 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5792 else if (hw->phy.media_type == e1000_media_type_internal_serdes) 5793 ctrl |= E1000_CTRL_SLU; 5794 break; 5795 5796 case e1000_82573: 5797 ctrl |= E1000_CTRL_ILOS; 5798 break; 5799 case e1000_ich9lan: 5800 case e1000_ich10lan: 5801 ctrl |= E1000_CTRL_SLU; 5802 break; 5803 } 5804 if (hw->phy.type == e1000_phy_bm) 5805 ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS; 5806 5807 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5808 } 5809 5810 static void 5811 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 5812 { 5813 struct e1000_hw *hw; 5814 uint32_t rctl; 5815 uint32_t ctrl_ext; 5816 uint32_t ctrl; 5817 uint32_t status; 5818 uint32_t txcw; 5819 uint16_t phydata; 5820 5821 hw = &Adapter->shared; 5822 5823 /* Disable Smart Power Down */ 5824 phy_spd_state(hw, B_FALSE); 5825 5826 switch (hw->mac.type) { 5827 case e1000_82571: 5828 case e1000_82572: 5829 switch (hw->phy.media_type) { 5830 case e1000_media_type_copper: 5831 /* Force link up (Must be done before the PHY writes) */ 5832 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5833 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 5834 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5835 5836 rctl = E1000_READ_REG(hw, E1000_RCTL); 5837 rctl |= (E1000_RCTL_EN | 5838 E1000_RCTL_SBP | 5839 E1000_RCTL_UPE | 5840 E1000_RCTL_MPE | 5841 E1000_RCTL_LPE | 5842 E1000_RCTL_BAM); /* 0x803E */ 5843 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 5844 5845 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5846 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 5847 E1000_CTRL_EXT_SDP6_DATA | 5848 E1000_CTRL_EXT_SDP3_DATA | 5849 E1000_CTRL_EXT_SDP4_DIR | 5850 E1000_CTRL_EXT_SDP6_DIR | 5851 E1000_CTRL_EXT_SDP3_DIR); /* 0x0DD0 */ 5852 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5853 5854 /* 5855 * This sequence tunes the PHY's SDP and no customer 5856 * settable values. For background, see comments above 5857 * e1000g_set_internal_loopback(). 5858 */ 5859 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 5860 msec_delay(10); 5861 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 5862 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 5863 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 5864 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 5865 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 5866 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 5867 5868 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 5869 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 5870 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 5871 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 5872 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 5873 5874 msec_delay(50); 5875 break; 5876 case e1000_media_type_fiber: 5877 case e1000_media_type_internal_serdes: 5878 status = E1000_READ_REG(hw, E1000_STATUS); 5879 if (((status & E1000_STATUS_LU) == 0) || 5880 (hw->phy.media_type == 5881 e1000_media_type_internal_serdes)) { 5882 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5883 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5884 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5885 } 5886 5887 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5888 txcw = E1000_READ_REG(hw, E1000_TXCW); 5889 txcw &= ~((uint32_t)1 << 31); 5890 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5891 5892 /* 5893 * Write 0x410 to Serdes Control register 5894 * to enable Serdes analog loopback 5895 */ 5896 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5897 msec_delay(10); 5898 break; 5899 default: 5900 break; 5901 } 5902 break; 5903 case e1000_82574: 5904 case e1000_80003es2lan: 5905 case e1000_ich9lan: 5906 case e1000_ich10lan: 5907 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 5908 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 5909 phydata | (1 << 5)); 5910 Adapter->param_adv_autoneg = 1; 5911 Adapter->param_adv_1000fdx = 1; 5912 (void) e1000g_reset_link(Adapter); 5913 break; 5914 } 5915 } 5916 5917 static void 5918 e1000g_set_external_loopback_100(struct e1000g *Adapter) 5919 { 5920 struct e1000_hw *hw; 5921 uint32_t ctrl; 5922 uint16_t phy_ctrl; 5923 5924 hw = &Adapter->shared; 5925 5926 /* Disable Smart Power Down */ 5927 phy_spd_state(hw, B_FALSE); 5928 5929 phy_ctrl = (MII_CR_FULL_DUPLEX | 5930 MII_CR_SPEED_100); 5931 5932 /* Force 100/FD, reset PHY */ 5933 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5934 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 5935 msec_delay(10); 5936 5937 /* Force 100/FD */ 5938 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5939 phy_ctrl); /* 0x2100 */ 5940 msec_delay(10); 5941 5942 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5943 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5944 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5945 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5946 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5947 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5948 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 5949 E1000_CTRL_FD); /* Force Duplex to FULL */ 5950 5951 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5952 } 5953 5954 static void 5955 e1000g_set_external_loopback_10(struct e1000g *Adapter) 5956 { 5957 struct e1000_hw *hw; 5958 uint32_t ctrl; 5959 uint16_t phy_ctrl; 5960 5961 hw = &Adapter->shared; 5962 5963 /* Disable Smart Power Down */ 5964 phy_spd_state(hw, B_FALSE); 5965 5966 phy_ctrl = (MII_CR_FULL_DUPLEX | 5967 MII_CR_SPEED_10); 5968 5969 /* Force 10/FD, reset PHY */ 5970 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5971 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 5972 msec_delay(10); 5973 5974 /* Force 10/FD */ 5975 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5976 phy_ctrl); /* 0x0100 */ 5977 msec_delay(10); 5978 5979 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5980 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5981 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5982 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5983 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5984 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5985 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 5986 E1000_CTRL_FD); /* Force Duplex to FULL */ 5987 5988 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5989 } 5990 5991 #ifdef __sparc 5992 static boolean_t 5993 e1000g_find_mac_address(struct e1000g *Adapter) 5994 { 5995 struct e1000_hw *hw = &Adapter->shared; 5996 uchar_t *bytes; 5997 struct ether_addr sysaddr; 5998 uint_t nelts; 5999 int err; 6000 boolean_t found = B_FALSE; 6001 6002 /* 6003 * The "vendor's factory-set address" may already have 6004 * been extracted from the chip, but if the property 6005 * "local-mac-address" is set we use that instead. 6006 * 6007 * We check whether it looks like an array of 6 6008 * bytes (which it should, if OBP set it). If we can't 6009 * make sense of it this way, we'll ignore it. 6010 */ 6011 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 6012 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 6013 if (err == DDI_PROP_SUCCESS) { 6014 if (nelts == ETHERADDRL) { 6015 while (nelts--) 6016 hw->mac.addr[nelts] = bytes[nelts]; 6017 found = B_TRUE; 6018 } 6019 ddi_prop_free(bytes); 6020 } 6021 6022 /* 6023 * Look up the OBP property "local-mac-address?". If the user has set 6024 * 'local-mac-address? = false', use "the system address" instead. 6025 */ 6026 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 6027 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 6028 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 6029 if (localetheraddr(NULL, &sysaddr) != 0) { 6030 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 6031 found = B_TRUE; 6032 } 6033 } 6034 ddi_prop_free(bytes); 6035 } 6036 6037 /* 6038 * Finally(!), if there's a valid "mac-address" property (created 6039 * if we netbooted from this interface), we must use this instead 6040 * of any of the above to ensure that the NFS/install server doesn't 6041 * get confused by the address changing as Solaris takes over! 6042 */ 6043 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 6044 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 6045 if (err == DDI_PROP_SUCCESS) { 6046 if (nelts == ETHERADDRL) { 6047 while (nelts--) 6048 hw->mac.addr[nelts] = bytes[nelts]; 6049 found = B_TRUE; 6050 } 6051 ddi_prop_free(bytes); 6052 } 6053 6054 if (found) { 6055 bcopy(hw->mac.addr, hw->mac.perm_addr, 6056 ETHERADDRL); 6057 } 6058 6059 return (found); 6060 } 6061 #endif 6062 6063 static int 6064 e1000g_add_intrs(struct e1000g *Adapter) 6065 { 6066 dev_info_t *devinfo; 6067 int intr_types; 6068 int rc; 6069 6070 devinfo = Adapter->dip; 6071 6072 /* Get supported interrupt types */ 6073 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 6074 6075 if (rc != DDI_SUCCESS) { 6076 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6077 "Get supported interrupt types failed: %d\n", rc); 6078 return (DDI_FAILURE); 6079 } 6080 6081 /* 6082 * Based on Intel Technical Advisory document (TA-160), there are some 6083 * cases where some older Intel PCI-X NICs may "advertise" to the OS 6084 * that it supports MSI, but in fact has problems. 6085 * So we should only enable MSI for PCI-E NICs and disable MSI for old 6086 * PCI/PCI-X NICs. 6087 */ 6088 if (Adapter->shared.mac.type < e1000_82571) 6089 Adapter->msi_enable = B_FALSE; 6090 6091 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 6092 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 6093 6094 if (rc != DDI_SUCCESS) { 6095 /* EMPTY */ 6096 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 6097 "Add MSI failed, trying Legacy interrupts\n"); 6098 } else { 6099 Adapter->intr_type = DDI_INTR_TYPE_MSI; 6100 } 6101 } 6102 6103 if ((Adapter->intr_type == 0) && 6104 (intr_types & DDI_INTR_TYPE_FIXED)) { 6105 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 6106 6107 if (rc != DDI_SUCCESS) { 6108 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 6109 "Add Legacy interrupts failed\n"); 6110 return (DDI_FAILURE); 6111 } 6112 6113 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 6114 } 6115 6116 if (Adapter->intr_type == 0) { 6117 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 6118 "No interrupts registered\n"); 6119 return (DDI_FAILURE); 6120 } 6121 6122 return (DDI_SUCCESS); 6123 } 6124 6125 /* 6126 * e1000g_intr_add() handles MSI/Legacy interrupts 6127 */ 6128 static int 6129 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 6130 { 6131 dev_info_t *devinfo; 6132 int count, avail, actual; 6133 int x, y, rc, inum = 0; 6134 int flag; 6135 ddi_intr_handler_t *intr_handler; 6136 6137 devinfo = Adapter->dip; 6138 6139 /* get number of interrupts */ 6140 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 6141 if ((rc != DDI_SUCCESS) || (count == 0)) { 6142 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 6143 "Get interrupt number failed. Return: %d, count: %d\n", 6144 rc, count); 6145 return (DDI_FAILURE); 6146 } 6147 6148 /* get number of available interrupts */ 6149 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 6150 if ((rc != DDI_SUCCESS) || (avail == 0)) { 6151 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 6152 "Get interrupt available number failed. " 6153 "Return: %d, available: %d\n", rc, avail); 6154 return (DDI_FAILURE); 6155 } 6156 6157 if (avail < count) { 6158 /* EMPTY */ 6159 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 6160 "Interrupts count: %d, available: %d\n", 6161 count, avail); 6162 } 6163 6164 /* Allocate an array of interrupt handles */ 6165 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 6166 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 6167 6168 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 6169 flag = DDI_INTR_ALLOC_NORMAL; 6170 6171 /* call ddi_intr_alloc() */ 6172 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 6173 count, &actual, flag); 6174 6175 if ((rc != DDI_SUCCESS) || (actual == 0)) { 6176 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6177 "Allocate interrupts failed: %d\n", rc); 6178 6179 kmem_free(Adapter->htable, Adapter->intr_size); 6180 return (DDI_FAILURE); 6181 } 6182 6183 if (actual < count) { 6184 /* EMPTY */ 6185 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 6186 "Interrupts requested: %d, received: %d\n", 6187 count, actual); 6188 } 6189 6190 Adapter->intr_cnt = actual; 6191 6192 /* Get priority for first msi, assume remaining are all the same */ 6193 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 6194 6195 if (rc != DDI_SUCCESS) { 6196 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6197 "Get interrupt priority failed: %d\n", rc); 6198 6199 /* Free already allocated intr */ 6200 for (y = 0; y < actual; y++) 6201 (void) ddi_intr_free(Adapter->htable[y]); 6202 6203 kmem_free(Adapter->htable, Adapter->intr_size); 6204 return (DDI_FAILURE); 6205 } 6206 6207 /* 6208 * In Legacy Interrupt mode, for PCI-Express adapters, we should 6209 * use the interrupt service routine e1000g_intr_pciexpress() 6210 * to avoid interrupt stealing when sharing interrupt with other 6211 * devices. 6212 */ 6213 if (Adapter->shared.mac.type < e1000_82571) 6214 intr_handler = e1000g_intr; 6215 else 6216 intr_handler = e1000g_intr_pciexpress; 6217 6218 /* Call ddi_intr_add_handler() */ 6219 for (x = 0; x < actual; x++) { 6220 rc = ddi_intr_add_handler(Adapter->htable[x], 6221 intr_handler, (caddr_t)Adapter, NULL); 6222 6223 if (rc != DDI_SUCCESS) { 6224 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6225 "Add interrupt handler failed: %d\n", rc); 6226 6227 /* Remove already added handler */ 6228 for (y = 0; y < x; y++) 6229 (void) ddi_intr_remove_handler( 6230 Adapter->htable[y]); 6231 6232 /* Free already allocated intr */ 6233 for (y = 0; y < actual; y++) 6234 (void) ddi_intr_free(Adapter->htable[y]); 6235 6236 kmem_free(Adapter->htable, Adapter->intr_size); 6237 return (DDI_FAILURE); 6238 } 6239 } 6240 6241 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 6242 6243 if (rc != DDI_SUCCESS) { 6244 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6245 "Get interrupt cap failed: %d\n", rc); 6246 6247 /* Free already allocated intr */ 6248 for (y = 0; y < actual; y++) { 6249 (void) ddi_intr_remove_handler(Adapter->htable[y]); 6250 (void) ddi_intr_free(Adapter->htable[y]); 6251 } 6252 6253 kmem_free(Adapter->htable, Adapter->intr_size); 6254 return (DDI_FAILURE); 6255 } 6256 6257 return (DDI_SUCCESS); 6258 } 6259 6260 static int 6261 e1000g_rem_intrs(struct e1000g *Adapter) 6262 { 6263 int x; 6264 int rc; 6265 6266 for (x = 0; x < Adapter->intr_cnt; x++) { 6267 rc = ddi_intr_remove_handler(Adapter->htable[x]); 6268 if (rc != DDI_SUCCESS) { 6269 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6270 "Remove intr handler failed: %d\n", rc); 6271 return (DDI_FAILURE); 6272 } 6273 6274 rc = ddi_intr_free(Adapter->htable[x]); 6275 if (rc != DDI_SUCCESS) { 6276 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6277 "Free intr failed: %d\n", rc); 6278 return (DDI_FAILURE); 6279 } 6280 } 6281 6282 kmem_free(Adapter->htable, Adapter->intr_size); 6283 6284 return (DDI_SUCCESS); 6285 } 6286 6287 static int 6288 e1000g_enable_intrs(struct e1000g *Adapter) 6289 { 6290 int x; 6291 int rc; 6292 6293 /* Enable interrupts */ 6294 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 6295 /* Call ddi_intr_block_enable() for MSI */ 6296 rc = ddi_intr_block_enable(Adapter->htable, 6297 Adapter->intr_cnt); 6298 if (rc != DDI_SUCCESS) { 6299 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6300 "Enable block intr failed: %d\n", rc); 6301 return (DDI_FAILURE); 6302 } 6303 } else { 6304 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 6305 for (x = 0; x < Adapter->intr_cnt; x++) { 6306 rc = ddi_intr_enable(Adapter->htable[x]); 6307 if (rc != DDI_SUCCESS) { 6308 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6309 "Enable intr failed: %d\n", rc); 6310 return (DDI_FAILURE); 6311 } 6312 } 6313 } 6314 6315 return (DDI_SUCCESS); 6316 } 6317 6318 static int 6319 e1000g_disable_intrs(struct e1000g *Adapter) 6320 { 6321 int x; 6322 int rc; 6323 6324 /* Disable all interrupts */ 6325 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 6326 rc = ddi_intr_block_disable(Adapter->htable, 6327 Adapter->intr_cnt); 6328 if (rc != DDI_SUCCESS) { 6329 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6330 "Disable block intr failed: %d\n", rc); 6331 return (DDI_FAILURE); 6332 } 6333 } else { 6334 for (x = 0; x < Adapter->intr_cnt; x++) { 6335 rc = ddi_intr_disable(Adapter->htable[x]); 6336 if (rc != DDI_SUCCESS) { 6337 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6338 "Disable intr failed: %d\n", rc); 6339 return (DDI_FAILURE); 6340 } 6341 } 6342 } 6343 6344 return (DDI_SUCCESS); 6345 } 6346 6347 /* 6348 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 6349 */ 6350 static void 6351 e1000g_get_phy_state(struct e1000g *Adapter) 6352 { 6353 struct e1000_hw *hw = &Adapter->shared; 6354 6355 if (hw->phy.media_type == e1000_media_type_copper) { 6356 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 6357 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 6358 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 6359 &Adapter->phy_an_adv); 6360 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, 6361 &Adapter->phy_an_exp); 6362 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, 6363 &Adapter->phy_ext_status); 6364 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, 6365 &Adapter->phy_1000t_ctrl); 6366 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 6367 &Adapter->phy_1000t_status); 6368 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, 6369 &Adapter->phy_lp_able); 6370 6371 Adapter->param_autoneg_cap = 6372 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 6373 Adapter->param_pause_cap = 6374 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 6375 Adapter->param_asym_pause_cap = 6376 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 6377 Adapter->param_1000fdx_cap = 6378 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 6379 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 6380 Adapter->param_1000hdx_cap = 6381 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 6382 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 6383 Adapter->param_100t4_cap = 6384 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 6385 Adapter->param_100fdx_cap = 6386 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 6387 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 6388 Adapter->param_100hdx_cap = 6389 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 6390 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 6391 Adapter->param_10fdx_cap = 6392 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 6393 Adapter->param_10hdx_cap = 6394 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 6395 6396 Adapter->param_adv_autoneg = hw->mac.autoneg; 6397 Adapter->param_adv_pause = 6398 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 6399 Adapter->param_adv_asym_pause = 6400 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 6401 Adapter->param_adv_1000hdx = 6402 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 6403 Adapter->param_adv_100t4 = 6404 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 6405 if (Adapter->param_adv_autoneg == 1) { 6406 Adapter->param_adv_1000fdx = 6407 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) 6408 ? 1 : 0; 6409 Adapter->param_adv_100fdx = 6410 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) 6411 ? 1 : 0; 6412 Adapter->param_adv_100hdx = 6413 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) 6414 ? 1 : 0; 6415 Adapter->param_adv_10fdx = 6416 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 6417 Adapter->param_adv_10hdx = 6418 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 6419 } 6420 6421 Adapter->param_lp_autoneg = 6422 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 6423 Adapter->param_lp_pause = 6424 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 6425 Adapter->param_lp_asym_pause = 6426 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 6427 Adapter->param_lp_1000fdx = 6428 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 6429 Adapter->param_lp_1000hdx = 6430 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 6431 Adapter->param_lp_100t4 = 6432 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 6433 Adapter->param_lp_100fdx = 6434 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 6435 Adapter->param_lp_100hdx = 6436 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 6437 Adapter->param_lp_10fdx = 6438 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 6439 Adapter->param_lp_10hdx = 6440 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 6441 } else { 6442 /* 6443 * 1Gig Fiber adapter only offers 1Gig Full Duplex. Meaning, 6444 * it can only work with 1Gig Full Duplex Link Partner. 6445 */ 6446 Adapter->param_autoneg_cap = 0; 6447 Adapter->param_pause_cap = 1; 6448 Adapter->param_asym_pause_cap = 1; 6449 Adapter->param_1000fdx_cap = 1; 6450 Adapter->param_1000hdx_cap = 0; 6451 Adapter->param_100t4_cap = 0; 6452 Adapter->param_100fdx_cap = 0; 6453 Adapter->param_100hdx_cap = 0; 6454 Adapter->param_10fdx_cap = 0; 6455 Adapter->param_10hdx_cap = 0; 6456 6457 Adapter->param_adv_autoneg = 0; 6458 Adapter->param_adv_pause = 1; 6459 Adapter->param_adv_asym_pause = 1; 6460 Adapter->param_adv_1000fdx = 1; 6461 Adapter->param_adv_1000hdx = 0; 6462 Adapter->param_adv_100t4 = 0; 6463 Adapter->param_adv_100fdx = 0; 6464 Adapter->param_adv_100hdx = 0; 6465 Adapter->param_adv_10fdx = 0; 6466 Adapter->param_adv_10hdx = 0; 6467 6468 Adapter->param_lp_autoneg = 0; 6469 Adapter->param_lp_pause = 0; 6470 Adapter->param_lp_asym_pause = 0; 6471 Adapter->param_lp_1000fdx = 0; 6472 Adapter->param_lp_1000hdx = 0; 6473 Adapter->param_lp_100t4 = 0; 6474 Adapter->param_lp_100fdx = 0; 6475 Adapter->param_lp_100hdx = 0; 6476 Adapter->param_lp_10fdx = 0; 6477 Adapter->param_lp_10hdx = 0; 6478 } 6479 } 6480 6481 /* 6482 * FMA support 6483 */ 6484 6485 int 6486 e1000g_check_acc_handle(ddi_acc_handle_t handle) 6487 { 6488 ddi_fm_error_t de; 6489 6490 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 6491 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 6492 return (de.fme_status); 6493 } 6494 6495 int 6496 e1000g_check_dma_handle(ddi_dma_handle_t handle) 6497 { 6498 ddi_fm_error_t de; 6499 6500 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 6501 return (de.fme_status); 6502 } 6503 6504 /* 6505 * The IO fault service error handling callback function 6506 */ 6507 /* ARGSUSED2 */ 6508 static int 6509 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 6510 { 6511 /* 6512 * as the driver can always deal with an error in any dma or 6513 * access handle, we can just return the fme_status value. 6514 */ 6515 pci_ereport_post(dip, err, NULL); 6516 return (err->fme_status); 6517 } 6518 6519 static void 6520 e1000g_fm_init(struct e1000g *Adapter) 6521 { 6522 ddi_iblock_cookie_t iblk; 6523 int fma_dma_flag; 6524 6525 /* Only register with IO Fault Services if we have some capability */ 6526 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 6527 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 6528 } else { 6529 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 6530 } 6531 6532 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 6533 fma_dma_flag = 1; 6534 } else { 6535 fma_dma_flag = 0; 6536 } 6537 6538 (void) e1000g_set_fma_flags(fma_dma_flag); 6539 6540 if (Adapter->fm_capabilities) { 6541 6542 /* Register capabilities with IO Fault Services */ 6543 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 6544 6545 /* 6546 * Initialize pci ereport capabilities if ereport capable 6547 */ 6548 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6549 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6550 pci_ereport_setup(Adapter->dip); 6551 6552 /* 6553 * Register error callback if error callback capable 6554 */ 6555 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6556 ddi_fm_handler_register(Adapter->dip, 6557 e1000g_fm_error_cb, (void*) Adapter); 6558 } 6559 } 6560 6561 static void 6562 e1000g_fm_fini(struct e1000g *Adapter) 6563 { 6564 /* Only unregister FMA capabilities if we registered some */ 6565 if (Adapter->fm_capabilities) { 6566 6567 /* 6568 * Release any resources allocated by pci_ereport_setup() 6569 */ 6570 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6571 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6572 pci_ereport_teardown(Adapter->dip); 6573 6574 /* 6575 * Un-register error callback if error callback capable 6576 */ 6577 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6578 ddi_fm_handler_unregister(Adapter->dip); 6579 6580 /* Unregister from IO Fault Services */ 6581 mutex_enter(&e1000g_rx_detach_lock); 6582 ddi_fm_fini(Adapter->dip); 6583 if (Adapter->priv_dip != NULL) { 6584 DEVI(Adapter->priv_dip)->devi_fmhdl = NULL; 6585 } 6586 mutex_exit(&e1000g_rx_detach_lock); 6587 } 6588 } 6589 6590 void 6591 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 6592 { 6593 uint64_t ena; 6594 char buf[FM_MAX_CLASS]; 6595 6596 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 6597 ena = fm_ena_generate(0, FM_ENA_FMT1); 6598 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 6599 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 6600 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 6601 } 6602 } 6603 6604 /* 6605 * quiesce(9E) entry point. 6606 * 6607 * This function is called when the system is single-threaded at high 6608 * PIL with preemption disabled. Therefore, this function must not be 6609 * blocked. 6610 * 6611 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 6612 * DDI_FAILURE indicates an error condition and should almost never happen. 6613 */ 6614 static int 6615 e1000g_quiesce(dev_info_t *devinfo) 6616 { 6617 struct e1000g *Adapter; 6618 6619 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 6620 6621 if (Adapter == NULL) 6622 return (DDI_FAILURE); 6623 6624 e1000g_clear_all_interrupts(Adapter); 6625 6626 (void) e1000_reset_hw(&Adapter->shared); 6627 6628 /* Setup our HW Tx Head & Tail descriptor pointers */ 6629 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 6630 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 6631 6632 /* Setup our HW Rx Head & Tail descriptor pointers */ 6633 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 6634 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 6635 6636 return (DDI_SUCCESS); 6637 } 6638 6639 /* 6640 * synchronize the adv* and en* parameters. 6641 * 6642 * See comments in <sys/dld.h> for details of the *_en_* 6643 * parameters. The usage of ndd for setting adv parameters will 6644 * synchronize all the en parameters with the e1000g parameters, 6645 * implicitly disabling any settings made via dladm. 6646 */ 6647 static void 6648 e1000g_param_sync(struct e1000g *Adapter) 6649 { 6650 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 6651 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 6652 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 6653 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 6654 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 6655 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 6656 } 6657 6658 /* 6659 * e1000g_get_driver_control - tell manageability firmware that the driver 6660 * has control. 6661 */ 6662 static void 6663 e1000g_get_driver_control(struct e1000_hw *hw) 6664 { 6665 uint32_t ctrl_ext; 6666 uint32_t swsm; 6667 6668 /* tell manageability firmware the driver has taken over */ 6669 switch (hw->mac.type) { 6670 case e1000_82573: 6671 swsm = E1000_READ_REG(hw, E1000_SWSM); 6672 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 6673 break; 6674 case e1000_82571: 6675 case e1000_82572: 6676 case e1000_82574: 6677 case e1000_80003es2lan: 6678 case e1000_ich8lan: 6679 case e1000_ich9lan: 6680 case e1000_ich10lan: 6681 case e1000_pchlan: 6682 case e1000_pch2lan: 6683 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6684 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6685 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 6686 break; 6687 default: 6688 /* no manageability firmware: do nothing */ 6689 break; 6690 } 6691 } 6692 6693 /* 6694 * e1000g_release_driver_control - tell manageability firmware that the driver 6695 * has released control. 6696 */ 6697 static void 6698 e1000g_release_driver_control(struct e1000_hw *hw) 6699 { 6700 uint32_t ctrl_ext; 6701 uint32_t swsm; 6702 6703 /* tell manageability firmware the driver has released control */ 6704 switch (hw->mac.type) { 6705 case e1000_82573: 6706 swsm = E1000_READ_REG(hw, E1000_SWSM); 6707 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 6708 break; 6709 case e1000_82571: 6710 case e1000_82572: 6711 case e1000_82574: 6712 case e1000_80003es2lan: 6713 case e1000_ich8lan: 6714 case e1000_ich9lan: 6715 case e1000_ich10lan: 6716 case e1000_pchlan: 6717 case e1000_pch2lan: 6718 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6719 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6720 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 6721 break; 6722 default: 6723 /* no manageability firmware: do nothing */ 6724 break; 6725 } 6726 } 6727 6728 /* 6729 * Restore e1000g promiscuous mode. 6730 */ 6731 static void 6732 e1000g_restore_promisc(struct e1000g *Adapter) 6733 { 6734 if (Adapter->e1000g_promisc) { 6735 uint32_t rctl; 6736 6737 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 6738 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 6739 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 6740 } 6741 } 6742