1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * ********************************************************************** 30 * * 31 * Module Name: * 32 * e1000g_main.c * 33 * * 34 * Abstract: * 35 * This file contains the interface routines for the solaris OS. * 36 * It has all DDI entry point routines and GLD entry point routines. * 37 * * 38 * This file also contains routines that take care of initialization * 39 * uninit routine and interrupt routine. * 40 * * 41 * ********************************************************************** 42 */ 43 44 #include <sys/dlpi.h> 45 #include <sys/mac.h> 46 #include "e1000g_sw.h" 47 #include "e1000g_debug.h" 48 49 static char ident[] = "Intel PRO/1000 Ethernet 5.2.5"; 50 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 51 static char e1000g_version[] = "Driver Ver. 5.2.5"; 52 53 /* 54 * Proto types for DDI entry points 55 */ 56 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 57 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 58 59 /* 60 * init and intr routines prototype 61 */ 62 static int e1000g_resume(dev_info_t *); 63 static int e1000g_suspend(dev_info_t *); 64 static uint_t e1000g_intr_pciexpress(caddr_t); 65 static uint_t e1000g_intr(caddr_t); 66 static void e1000g_intr_work(struct e1000g *, uint32_t); 67 #pragma inline(e1000g_intr_work) 68 static uint32_t e1000g_get_itr(uint32_t, uint32_t, uint32_t); 69 #pragma inline(e1000g_get_itr) 70 static int e1000g_init(struct e1000g *); 71 static int e1000g_start(struct e1000g *, boolean_t); 72 static void e1000g_stop(struct e1000g *, boolean_t); 73 static int e1000g_m_start(void *); 74 static void e1000g_m_stop(void *); 75 static int e1000g_m_promisc(void *, boolean_t); 76 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 77 static int e1000g_m_unicst(void *, const uint8_t *); 78 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 79 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 80 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 81 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 82 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 83 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 84 static void e1000g_init_locks(struct e1000g *); 85 static void e1000g_destroy_locks(struct e1000g *); 86 static int e1000g_identify_hardware(struct e1000g *); 87 static int e1000g_regs_map(struct e1000g *); 88 static int e1000g_set_driver_params(struct e1000g *); 89 static int e1000g_register_mac(struct e1000g *); 90 static boolean_t e1000g_rx_drain(struct e1000g *); 91 static boolean_t e1000g_tx_drain(struct e1000g *); 92 static void e1000g_init_unicst(struct e1000g *); 93 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 94 95 /* 96 * Local routines 97 */ 98 static void e1000g_tx_clean(struct e1000g *); 99 static void e1000g_rx_clean(struct e1000g *); 100 static void e1000g_link_timer(void *); 101 static void e1000g_local_timer(void *); 102 static boolean_t e1000g_link_check(struct e1000g *); 103 static boolean_t e1000g_stall_check(struct e1000g *); 104 static void e1000g_smartspeed(struct e1000g *); 105 static void e1000g_get_conf(struct e1000g *); 106 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 107 static void enable_watchdog_timer(struct e1000g *); 108 static void disable_watchdog_timer(struct e1000g *); 109 static void start_watchdog_timer(struct e1000g *); 110 static void restart_watchdog_timer(struct e1000g *); 111 static void stop_watchdog_timer(struct e1000g *); 112 static void stop_link_timer(struct e1000g *); 113 static void stop_82547_timer(e1000g_tx_ring_t *); 114 static void e1000g_force_speed_duplex(struct e1000g *); 115 static void e1000g_get_max_frame_size(struct e1000g *); 116 static boolean_t is_valid_mac_addr(uint8_t *); 117 static void e1000g_unattach(dev_info_t *, struct e1000g *); 118 #ifdef E1000G_DEBUG 119 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 120 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 121 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 122 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 123 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 124 struct iocblk *, mblk_t *); 125 #endif 126 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 127 struct iocblk *, mblk_t *); 128 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 129 static void e1000g_set_internal_loopback(struct e1000g *); 130 static void e1000g_set_external_loopback_1000(struct e1000g *); 131 static void e1000g_set_external_loopback_100(struct e1000g *); 132 static void e1000g_set_external_loopback_10(struct e1000g *); 133 static int e1000g_add_intrs(struct e1000g *); 134 static int e1000g_intr_add(struct e1000g *, int); 135 static int e1000g_rem_intrs(struct e1000g *); 136 static int e1000g_enable_intrs(struct e1000g *); 137 static int e1000g_disable_intrs(struct e1000g *); 138 static boolean_t e1000g_link_up(struct e1000g *); 139 #ifdef __sparc 140 static boolean_t e1000g_find_mac_address(struct e1000g *); 141 #endif 142 static void e1000g_get_phy_state(struct e1000g *); 143 static void e1000g_free_priv_devi_node(struct e1000g *, boolean_t); 144 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 145 const void *impl_data); 146 static void e1000g_fm_init(struct e1000g *Adapter); 147 static void e1000g_fm_fini(struct e1000g *Adapter); 148 149 static struct cb_ops cb_ws_ops = { 150 nulldev, /* cb_open */ 151 nulldev, /* cb_close */ 152 nodev, /* cb_strategy */ 153 nodev, /* cb_print */ 154 nodev, /* cb_dump */ 155 nodev, /* cb_read */ 156 nodev, /* cb_write */ 157 nodev, /* cb_ioctl */ 158 nodev, /* cb_devmap */ 159 nodev, /* cb_mmap */ 160 nodev, /* cb_segmap */ 161 nochpoll, /* cb_chpoll */ 162 ddi_prop_op, /* cb_prop_op */ 163 NULL, /* cb_stream */ 164 D_MP | D_HOTPLUG, /* cb_flag */ 165 CB_REV, /* cb_rev */ 166 nodev, /* cb_aread */ 167 nodev /* cb_awrite */ 168 }; 169 170 static struct dev_ops ws_ops = { 171 DEVO_REV, /* devo_rev */ 172 0, /* devo_refcnt */ 173 NULL, /* devo_getinfo */ 174 nulldev, /* devo_identify */ 175 nulldev, /* devo_probe */ 176 e1000g_attach, /* devo_attach */ 177 e1000g_detach, /* devo_detach */ 178 nodev, /* devo_reset */ 179 &cb_ws_ops, /* devo_cb_ops */ 180 NULL, /* devo_bus_ops */ 181 ddi_power /* devo_power */ 182 }; 183 184 static struct modldrv modldrv = { 185 &mod_driverops, /* Type of module. This one is a driver */ 186 ident, /* Discription string */ 187 &ws_ops, /* driver ops */ 188 }; 189 190 static struct modlinkage modlinkage = { 191 MODREV_1, &modldrv, NULL 192 }; 193 194 /* Access attributes for register mapping */ 195 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 196 DDI_DEVICE_ATTR_V0, 197 DDI_STRUCTURE_LE_ACC, 198 DDI_STRICTORDER_ACC, 199 DDI_FLAGERR_ACC 200 }; 201 202 #define E1000G_M_CALLBACK_FLAGS (MC_IOCTL | MC_GETCAPAB) 203 204 static mac_callbacks_t e1000g_m_callbacks = { 205 E1000G_M_CALLBACK_FLAGS, 206 e1000g_m_stat, 207 e1000g_m_start, 208 e1000g_m_stop, 209 e1000g_m_promisc, 210 e1000g_m_multicst, 211 e1000g_m_unicst, 212 e1000g_m_tx, 213 NULL, 214 e1000g_m_ioctl, 215 e1000g_m_getcapab 216 }; 217 218 /* 219 * Global variables 220 */ 221 uint32_t e1000g_mblks_pending = 0; 222 /* 223 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 224 * Here we maintain a private dev_info list if e1000g_force_detach is 225 * enabled. If we force the driver to detach while there are still some 226 * rx buffers retained in the upper layer, we have to keep a copy of the 227 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 228 * structure will be freed after the driver is detached. However when we 229 * finally free those rx buffers released by the upper layer, we need to 230 * refer to the dev_info to free the dma buffers. So we save a copy of 231 * the dev_info for this purpose. On x86 platform, we assume this copy 232 * of dev_info is always valid, but on SPARC platform, it could be invalid 233 * after the system board level DR operation. For this reason, the global 234 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 235 */ 236 #ifdef __sparc 237 boolean_t e1000g_force_detach = B_FALSE; 238 #else 239 boolean_t e1000g_force_detach = B_TRUE; 240 #endif 241 private_devi_list_t *e1000g_private_devi_list = NULL; 242 243 /* 244 * The rwlock is defined to protect the whole processing of rx recycling 245 * and the rx packets release in detach processing to make them mutually 246 * exclusive. 247 * The rx recycling processes different rx packets in different threads, 248 * so it will be protected with RW_READER and it won't block any other rx 249 * recycling threads. 250 * While the detach processing will be protected with RW_WRITER to make 251 * it mutually exclusive with the rx recycling. 252 */ 253 krwlock_t e1000g_rx_detach_lock; 254 /* 255 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 256 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 257 * If there are many e1000g instances, the system may run out of DVMA 258 * resources during the initialization of the instances, then the flag will 259 * be changed to "USE_DMA". Because different e1000g instances are initialized 260 * in parallel, we need to use this lock to protect the flag. 261 */ 262 krwlock_t e1000g_dma_type_lock; 263 264 265 /* 266 * Loadable module configuration entry points for the driver 267 */ 268 269 /* 270 * _init - module initialization 271 */ 272 int 273 _init(void) 274 { 275 int status; 276 277 mac_init_ops(&ws_ops, WSNAME); 278 status = mod_install(&modlinkage); 279 if (status != DDI_SUCCESS) 280 mac_fini_ops(&ws_ops); 281 else { 282 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 283 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 284 } 285 286 return (status); 287 } 288 289 /* 290 * _fini - module finalization 291 */ 292 int 293 _fini(void) 294 { 295 int status; 296 297 rw_enter(&e1000g_rx_detach_lock, RW_READER); 298 if (e1000g_mblks_pending != 0) { 299 rw_exit(&e1000g_rx_detach_lock); 300 return (EBUSY); 301 } 302 rw_exit(&e1000g_rx_detach_lock); 303 304 status = mod_remove(&modlinkage); 305 if (status == DDI_SUCCESS) { 306 mac_fini_ops(&ws_ops); 307 308 if (e1000g_force_detach) { 309 private_devi_list_t *devi_node; 310 311 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 312 while (e1000g_private_devi_list != NULL) { 313 devi_node = e1000g_private_devi_list; 314 e1000g_private_devi_list = 315 e1000g_private_devi_list->next; 316 317 kmem_free(devi_node->priv_dip, 318 sizeof (struct dev_info)); 319 kmem_free(devi_node, 320 sizeof (private_devi_list_t)); 321 } 322 rw_exit(&e1000g_rx_detach_lock); 323 } 324 325 rw_destroy(&e1000g_rx_detach_lock); 326 rw_destroy(&e1000g_dma_type_lock); 327 } 328 329 return (status); 330 } 331 332 /* 333 * _info - module information 334 */ 335 int 336 _info(struct modinfo *modinfop) 337 { 338 return (mod_info(&modlinkage, modinfop)); 339 } 340 341 /* 342 * e1000g_attach - driver attach 343 * 344 * This function is the device-specific initialization entry 345 * point. This entry point is required and must be written. 346 * The DDI_ATTACH command must be provided in the attach entry 347 * point. When attach() is called with cmd set to DDI_ATTACH, 348 * all normal kernel services (such as kmem_alloc(9F)) are 349 * available for use by the driver. 350 * 351 * The attach() function will be called once for each instance 352 * of the device on the system with cmd set to DDI_ATTACH. 353 * Until attach() succeeds, the only driver entry points which 354 * may be called are open(9E) and getinfo(9E). 355 */ 356 static int 357 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 358 { 359 struct e1000g *Adapter; 360 struct e1000_hw *hw; 361 struct e1000g_osdep *osdep; 362 int instance; 363 364 switch (cmd) { 365 default: 366 e1000g_log(NULL, CE_WARN, 367 "Unsupported command send to e1000g_attach... "); 368 return (DDI_FAILURE); 369 370 case DDI_RESUME: 371 return (e1000g_resume(devinfo)); 372 373 case DDI_ATTACH: 374 break; 375 } 376 377 /* 378 * get device instance number 379 */ 380 instance = ddi_get_instance(devinfo); 381 382 /* 383 * Allocate soft data structure 384 */ 385 Adapter = 386 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 387 388 Adapter->dip = devinfo; 389 Adapter->instance = instance; 390 Adapter->tx_ring->adapter = Adapter; 391 Adapter->rx_ring->adapter = Adapter; 392 393 hw = &Adapter->shared; 394 osdep = &Adapter->osdep; 395 hw->back = osdep; 396 osdep->adapter = Adapter; 397 398 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 399 400 /* 401 * Initialize for fma support 402 */ 403 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 404 0, 0x0f, 405 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 406 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 407 e1000g_fm_init(Adapter); 408 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 409 410 /* 411 * PCI Configure 412 */ 413 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 414 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 415 goto attach_fail; 416 } 417 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 418 419 /* 420 * Setup hardware 421 */ 422 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 423 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 424 goto attach_fail; 425 } 426 427 /* 428 * Map in the device registers. 429 */ 430 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 431 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 432 goto attach_fail; 433 } 434 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 435 436 /* 437 * Initialize driver parameters 438 */ 439 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 440 goto attach_fail; 441 } 442 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 443 444 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 445 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 446 goto attach_fail; 447 } 448 449 /* 450 * Initialize interrupts 451 */ 452 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 453 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 454 goto attach_fail; 455 } 456 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 457 458 /* 459 * Initialize mutex's for this device. 460 * Do this before enabling the interrupt handler and 461 * register the softint to avoid the condition where 462 * interrupt handler can try using uninitialized mutex 463 */ 464 e1000g_init_locks(Adapter); 465 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 466 467 /* 468 * Initialize Driver Counters 469 */ 470 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 471 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 472 goto attach_fail; 473 } 474 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 475 476 /* 477 * Initialize chip hardware and software structures 478 */ 479 if (e1000g_init(Adapter) != DDI_SUCCESS) { 480 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 481 goto attach_fail; 482 } 483 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 484 485 /* 486 * Initialize NDD parameters 487 */ 488 if (e1000g_nd_init(Adapter) != DDI_SUCCESS) { 489 e1000g_log(Adapter, CE_WARN, "Init ndd failed"); 490 goto attach_fail; 491 } 492 Adapter->attach_progress |= ATTACH_PROGRESS_NDD; 493 494 /* 495 * Register the driver to the MAC 496 */ 497 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 498 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 499 goto attach_fail; 500 } 501 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 502 503 /* 504 * Now that mutex locks are initialized, and the chip is also 505 * initialized, enable interrupts. 506 */ 507 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 508 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 509 goto attach_fail; 510 } 511 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 512 513 /* 514 * If e1000g_force_detach is enabled, in global private dip list, 515 * we will create a new entry, which maintains the priv_dip for DR 516 * supports after driver detached. 517 */ 518 if (e1000g_force_detach) { 519 private_devi_list_t *devi_node; 520 521 Adapter->priv_dip = 522 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 523 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 524 sizeof (struct dev_info)); 525 526 devi_node = 527 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 528 529 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 530 devi_node->priv_dip = Adapter->priv_dip; 531 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 532 devi_node->next = e1000g_private_devi_list; 533 e1000g_private_devi_list = devi_node; 534 rw_exit(&e1000g_rx_detach_lock); 535 } 536 537 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 538 539 return (DDI_SUCCESS); 540 541 attach_fail: 542 e1000g_unattach(devinfo, Adapter); 543 return (DDI_FAILURE); 544 } 545 546 static int 547 e1000g_register_mac(struct e1000g *Adapter) 548 { 549 struct e1000_hw *hw = &Adapter->shared; 550 mac_register_t *mac; 551 int err; 552 553 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 554 return (DDI_FAILURE); 555 556 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 557 mac->m_driver = Adapter; 558 mac->m_dip = Adapter->dip; 559 mac->m_src_addr = hw->mac.addr; 560 mac->m_callbacks = &e1000g_m_callbacks; 561 mac->m_min_sdu = 0; 562 mac->m_max_sdu = 563 (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) ? 564 hw->mac.max_frame_size - 256 : 565 (hw->mac.max_frame_size != ETHERMAX) ? 566 hw->mac.max_frame_size - 24 : ETHERMTU; 567 mac->m_margin = VLAN_TAGSZ; 568 569 err = mac_register(mac, &Adapter->mh); 570 mac_free(mac); 571 572 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 573 } 574 575 static int 576 e1000g_identify_hardware(struct e1000g *Adapter) 577 { 578 struct e1000_hw *hw = &Adapter->shared; 579 struct e1000g_osdep *osdep = &Adapter->osdep; 580 581 /* Get the device id */ 582 hw->vendor_id = 583 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 584 hw->device_id = 585 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 586 hw->revision_id = 587 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 588 hw->subsystem_device_id = 589 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 590 hw->subsystem_vendor_id = 591 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 592 593 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 594 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 595 "MAC type could not be set properly."); 596 return (DDI_FAILURE); 597 } 598 599 return (DDI_SUCCESS); 600 } 601 602 static int 603 e1000g_regs_map(struct e1000g *Adapter) 604 { 605 dev_info_t *devinfo = Adapter->dip; 606 struct e1000_hw *hw = &Adapter->shared; 607 struct e1000g_osdep *osdep = &Adapter->osdep; 608 off_t mem_size; 609 610 /* 611 * first get the size of device register to be mapped. The 612 * second parameter is the register we are interested. I our 613 * wiseman 0 is for config registers and 1 is for memory mapped 614 * registers Mem size should have memory mapped region size 615 */ 616 if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { 617 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 618 "ddi_dev_regsize for registers failed"); 619 return (DDI_FAILURE); 620 } 621 622 if ((ddi_regs_map_setup(devinfo, 1, /* register of interest */ 623 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 624 &osdep->reg_handle)) != DDI_SUCCESS) { 625 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 626 "ddi_regs_map_setup for registers failed"); 627 goto regs_map_fail; 628 } 629 630 /* ICH needs to map flash memory */ 631 if (hw->mac.type == e1000_ich8lan || hw->mac.type == e1000_ich9lan) { 632 /* get flash size */ 633 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 634 &mem_size) != DDI_SUCCESS) { 635 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 636 "ddi_dev_regsize for ICH flash failed"); 637 goto regs_map_fail; 638 } 639 640 /* map flash in */ 641 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 642 (caddr_t *)&hw->flash_address, 0, 643 mem_size, &e1000g_regs_acc_attr, 644 &osdep->ich_flash_handle) != DDI_SUCCESS) { 645 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 646 "ddi_regs_map_setup for ICH flash failed"); 647 goto regs_map_fail; 648 } 649 } 650 651 return (DDI_SUCCESS); 652 653 regs_map_fail: 654 if (osdep->reg_handle != NULL) 655 ddi_regs_map_free(&osdep->reg_handle); 656 657 return (DDI_FAILURE); 658 } 659 660 static int 661 e1000g_set_driver_params(struct e1000g *Adapter) 662 { 663 struct e1000_hw *hw; 664 e1000g_tx_ring_t *tx_ring; 665 uint32_t mem_bar, io_bar, bar64; 666 #ifdef __sparc 667 dev_info_t *devinfo = Adapter->dip; 668 ulong_t iommu_pagesize; 669 #endif 670 671 hw = &Adapter->shared; 672 673 /* Set MAC type and initialize hardware functions */ 674 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 675 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 676 "Could not setup hardware functions"); 677 return (DDI_FAILURE); 678 } 679 680 /* Get bus information */ 681 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 682 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 683 "Could not get bus information"); 684 return (DDI_FAILURE); 685 } 686 687 /* get mem_base addr */ 688 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 689 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 690 691 /* get io_base addr */ 692 if (hw->mac.type >= e1000_82544) { 693 if (bar64) { 694 /* IO BAR is different for 64 bit BAR mode */ 695 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 696 PCI_CONF_BASE4); 697 } else { 698 /* normal 32-bit BAR mode */ 699 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 700 PCI_CONF_BASE2); 701 } 702 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 703 } else { 704 /* no I/O access for adapters prior to 82544 */ 705 hw->io_base = 0x0; 706 } 707 708 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 709 710 hw->mac.autoneg_failed = B_TRUE; 711 712 /* Set the wait_for_link flag to B_FALSE */ 713 hw->phy.wait_for_link = B_FALSE; 714 715 /* Adaptive IFS related changes */ 716 hw->mac.adaptive_ifs = B_TRUE; 717 718 /* Enable phy init script for IGP phy of 82541/82547 */ 719 if ((hw->mac.type == e1000_82547) || 720 (hw->mac.type == e1000_82541) || 721 (hw->mac.type == e1000_82547_rev_2) || 722 (hw->mac.type == e1000_82541_rev_2)) 723 e1000_init_script_state_82541(hw, B_TRUE); 724 725 /* Enable the TTL workaround for 82541/82547 */ 726 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 727 728 #ifdef __sparc 729 Adapter->strip_crc = B_TRUE; 730 #else 731 Adapter->strip_crc = B_FALSE; 732 #endif 733 734 /* Get conf file properties */ 735 e1000g_get_conf(Adapter); 736 737 /* Get speed/duplex settings in conf file */ 738 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 739 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 740 e1000g_force_speed_duplex(Adapter); 741 742 /* Get Jumbo Frames settings in conf file */ 743 e1000g_get_max_frame_size(Adapter); 744 hw->mac.min_frame_size = 745 MINIMUM_ETHERNET_PACKET_SIZE + CRC_LENGTH; 746 747 #ifdef __sparc 748 /* Get the system page size */ 749 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 750 iommu_pagesize = dvma_pagesize(devinfo); 751 if (iommu_pagesize != 0) { 752 if (Adapter->sys_page_sz == iommu_pagesize) { 753 if (iommu_pagesize > 0x4000) 754 Adapter->sys_page_sz = 0x4000; 755 } else { 756 if (Adapter->sys_page_sz > iommu_pagesize) 757 Adapter->sys_page_sz = iommu_pagesize; 758 } 759 } 760 Adapter->dvma_page_num = hw->mac.max_frame_size / 761 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 762 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 763 #endif 764 765 /* Set Rx/Tx buffer size */ 766 switch (hw->mac.max_frame_size) { 767 case ETHERMAX: 768 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 769 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 770 break; 771 case FRAME_SIZE_UPTO_4K: 772 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 773 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 774 break; 775 case FRAME_SIZE_UPTO_8K: 776 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 777 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 778 break; 779 case FRAME_SIZE_UPTO_9K: 780 case FRAME_SIZE_UPTO_16K: 781 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 782 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 783 break; 784 default: 785 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 786 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 787 break; 788 } 789 Adapter->rx_buffer_size += E1000G_IPALIGNPRESERVEROOM; 790 791 #ifndef NO_82542_SUPPORT 792 /* 793 * For Wiseman adapters we have an requirement of having receive 794 * buffers aligned at 256 byte boundary. Since Livengood does not 795 * require this and forcing it for all hardwares will have 796 * performance implications, I am making it applicable only for 797 * Wiseman and for Jumbo frames enabled mode as rest of the time, 798 * it is okay to have normal frames...but it does involve a 799 * potential risk where we may loose data if buffer is not 800 * aligned...so all wiseman boards to have 256 byte aligned 801 * buffers 802 */ 803 if (hw->mac.type < e1000_82543) 804 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 805 else 806 Adapter->rx_buf_align = 1; 807 #endif 808 809 /* Master Latency Timer */ 810 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 811 812 /* copper options */ 813 if (hw->media_type == e1000_media_type_copper) { 814 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 815 hw->phy.disable_polarity_correction = B_FALSE; 816 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 817 } 818 819 /* The initial link state should be "unknown" */ 820 Adapter->link_state = LINK_STATE_UNKNOWN; 821 822 /* Initialize rx parameters */ 823 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 824 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 825 826 /* Initialize tx parameters */ 827 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 828 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 829 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 830 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 831 832 tx_ring = Adapter->tx_ring; 833 tx_ring->frags_limit = 834 (hw->mac.max_frame_size / Adapter->tx_bcopy_thresh) + 2; 835 if (tx_ring->frags_limit > (MAX_TX_DESC_PER_PACKET >> 1)) 836 tx_ring->frags_limit = (MAX_TX_DESC_PER_PACKET >> 1); 837 838 /* Initialize rx parameters */ 839 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 840 841 return (DDI_SUCCESS); 842 } 843 844 /* 845 * e1000g_detach - driver detach 846 * 847 * The detach() function is the complement of the attach routine. 848 * If cmd is set to DDI_DETACH, detach() is used to remove the 849 * state associated with a given instance of a device node 850 * prior to the removal of that instance from the system. 851 * 852 * The detach() function will be called once for each instance 853 * of the device for which there has been a successful attach() 854 * once there are no longer any opens on the device. 855 * 856 * Interrupts routine are disabled, All memory allocated by this 857 * driver are freed. 858 */ 859 static int 860 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 861 { 862 struct e1000g *Adapter; 863 boolean_t rx_drain; 864 865 switch (cmd) { 866 default: 867 return (DDI_FAILURE); 868 869 case DDI_SUSPEND: 870 return (e1000g_suspend(devinfo)); 871 872 case DDI_DETACH: 873 break; 874 } 875 876 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 877 if (Adapter == NULL) 878 return (DDI_FAILURE); 879 880 if (mac_unregister(Adapter->mh) != 0) { 881 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 882 return (DDI_FAILURE); 883 } 884 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 885 886 887 if (Adapter->chip_state != E1000G_STOP) 888 e1000g_stop(Adapter, B_TRUE); 889 890 rx_drain = e1000g_rx_drain(Adapter); 891 892 /* 893 * If e1000g_force_detach is enabled, driver detach is safe. 894 * We will let e1000g_free_priv_devi_node routine determine 895 * whether we need to free the priv_dip entry for current 896 * driver instance. 897 */ 898 if (e1000g_force_detach) { 899 e1000g_free_priv_devi_node(Adapter, rx_drain); 900 } else { 901 if (!rx_drain) 902 return (DDI_FAILURE); 903 } 904 905 e1000g_unattach(devinfo, Adapter); 906 907 return (DDI_SUCCESS); 908 } 909 910 /* 911 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 912 * 913 * If free_flag is true, that indicates the upper layer is not holding 914 * the rx buffers, we could free the priv_dip entry safely. 915 * 916 * Otherwise, we have to keep this entry even after driver detached, 917 * and we also need to mark this entry with E1000G_PRIV_DEVI_DETACH flag, 918 * so that driver could free it while all of rx buffers are returned 919 * by upper layer later. 920 */ 921 static void 922 e1000g_free_priv_devi_node(struct e1000g *Adapter, boolean_t free_flag) 923 { 924 private_devi_list_t *devi_node, *devi_del; 925 926 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 927 ASSERT(e1000g_private_devi_list != NULL); 928 ASSERT(Adapter->priv_dip != NULL); 929 930 devi_node = e1000g_private_devi_list; 931 if (devi_node->priv_dip == Adapter->priv_dip) { 932 if (free_flag) { 933 e1000g_private_devi_list = 934 devi_node->next; 935 kmem_free(devi_node->priv_dip, 936 sizeof (struct dev_info)); 937 kmem_free(devi_node, 938 sizeof (private_devi_list_t)); 939 } else { 940 ASSERT(e1000g_mblks_pending != 0); 941 devi_node->flag = 942 E1000G_PRIV_DEVI_DETACH; 943 } 944 rw_exit(&e1000g_rx_detach_lock); 945 return; 946 } 947 948 devi_node = e1000g_private_devi_list; 949 while (devi_node->next != NULL) { 950 if (devi_node->next->priv_dip == Adapter->priv_dip) { 951 if (free_flag) { 952 devi_del = devi_node->next; 953 devi_node->next = devi_del->next; 954 kmem_free(devi_del->priv_dip, 955 sizeof (struct dev_info)); 956 kmem_free(devi_del, 957 sizeof (private_devi_list_t)); 958 } else { 959 ASSERT(e1000g_mblks_pending != 0); 960 devi_node->next->flag = 961 E1000G_PRIV_DEVI_DETACH; 962 } 963 break; 964 } 965 devi_node = devi_node->next; 966 } 967 rw_exit(&e1000g_rx_detach_lock); 968 } 969 970 static void 971 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 972 { 973 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 974 (void) e1000g_disable_intrs(Adapter); 975 } 976 977 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 978 (void) mac_unregister(Adapter->mh); 979 } 980 981 if (Adapter->attach_progress & ATTACH_PROGRESS_NDD) { 982 e1000g_nd_cleanup(Adapter); 983 } 984 985 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 986 (void) e1000g_rem_intrs(Adapter); 987 } 988 989 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 990 (void) ddi_prop_remove_all(devinfo); 991 } 992 993 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 994 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 995 } 996 997 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 998 stop_link_timer(Adapter); 999 if (e1000_reset_hw(&Adapter->shared) != 0) { 1000 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1001 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1002 } 1003 } 1004 1005 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1006 if (Adapter->osdep.reg_handle != NULL) 1007 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1008 if (Adapter->osdep.ich_flash_handle != NULL) 1009 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1010 } 1011 1012 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1013 if (Adapter->osdep.cfg_handle != NULL) 1014 pci_config_teardown(&Adapter->osdep.cfg_handle); 1015 } 1016 1017 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1018 e1000g_destroy_locks(Adapter); 1019 } 1020 1021 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1022 e1000g_fm_fini(Adapter); 1023 } 1024 1025 e1000_remove_device(&Adapter->shared); 1026 1027 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1028 1029 /* 1030 * Another hotplug spec requirement, 1031 * run ddi_set_driver_private(devinfo, null); 1032 */ 1033 ddi_set_driver_private(devinfo, NULL); 1034 } 1035 1036 static void 1037 e1000g_init_locks(struct e1000g *Adapter) 1038 { 1039 e1000g_tx_ring_t *tx_ring; 1040 e1000g_rx_ring_t *rx_ring; 1041 1042 rw_init(&Adapter->chip_lock, NULL, 1043 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1044 mutex_init(&Adapter->link_lock, NULL, 1045 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1046 mutex_init(&Adapter->watchdog_lock, NULL, 1047 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1048 1049 tx_ring = Adapter->tx_ring; 1050 1051 mutex_init(&tx_ring->tx_lock, NULL, 1052 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1053 mutex_init(&tx_ring->usedlist_lock, NULL, 1054 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1055 mutex_init(&tx_ring->freelist_lock, NULL, 1056 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1057 1058 rx_ring = Adapter->rx_ring; 1059 1060 mutex_init(&rx_ring->freelist_lock, NULL, 1061 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1062 } 1063 1064 static void 1065 e1000g_destroy_locks(struct e1000g *Adapter) 1066 { 1067 e1000g_tx_ring_t *tx_ring; 1068 e1000g_rx_ring_t *rx_ring; 1069 1070 tx_ring = Adapter->tx_ring; 1071 mutex_destroy(&tx_ring->tx_lock); 1072 mutex_destroy(&tx_ring->usedlist_lock); 1073 mutex_destroy(&tx_ring->freelist_lock); 1074 1075 rx_ring = Adapter->rx_ring; 1076 mutex_destroy(&rx_ring->freelist_lock); 1077 1078 mutex_destroy(&Adapter->link_lock); 1079 mutex_destroy(&Adapter->watchdog_lock); 1080 rw_destroy(&Adapter->chip_lock); 1081 } 1082 1083 static int 1084 e1000g_resume(dev_info_t *devinfo) 1085 { 1086 struct e1000g *Adapter; 1087 1088 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1089 if (Adapter == NULL) 1090 return (DDI_FAILURE); 1091 1092 if (e1000g_start(Adapter, B_TRUE)) 1093 return (DDI_FAILURE); 1094 1095 return (DDI_SUCCESS); 1096 } 1097 1098 static int 1099 e1000g_suspend(dev_info_t *devinfo) 1100 { 1101 struct e1000g *Adapter; 1102 1103 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1104 if (Adapter == NULL) 1105 return (DDI_FAILURE); 1106 1107 e1000g_stop(Adapter, B_TRUE); 1108 1109 return (DDI_SUCCESS); 1110 } 1111 1112 static int 1113 e1000g_init(struct e1000g *Adapter) 1114 { 1115 uint32_t pba; 1116 uint32_t high_water; 1117 struct e1000_hw *hw; 1118 clock_t link_timeout; 1119 1120 hw = &Adapter->shared; 1121 1122 rw_enter(&Adapter->chip_lock, RW_WRITER); 1123 1124 /* 1125 * reset to put the hardware in a known state 1126 * before we try to do anything with the eeprom 1127 */ 1128 if (e1000_reset_hw(hw) != 0) { 1129 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1130 goto init_fail; 1131 } 1132 1133 if (e1000_validate_nvm_checksum(hw) < 0) { 1134 /* 1135 * Some PCI-E parts fail the first check due to 1136 * the link being in sleep state. Call it again, 1137 * if it fails a second time its a real issue. 1138 */ 1139 if (e1000_validate_nvm_checksum(hw) < 0) { 1140 e1000g_log(Adapter, CE_WARN, 1141 "Invalid NVM checksum. Please contact " 1142 "the vendor to update the NVM."); 1143 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1144 goto init_fail; 1145 } 1146 } 1147 1148 #ifdef __sparc 1149 /* 1150 * Firstly, we try to get the local ethernet address from OBP. If 1151 * fail, we get from EEPROM of NIC card. 1152 */ 1153 if (!e1000g_find_mac_address(Adapter)) { 1154 if (e1000_read_mac_addr(hw) < 0) { 1155 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1156 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1157 goto init_fail; 1158 } 1159 } 1160 #else 1161 /* Get the local ethernet address. */ 1162 if (e1000_read_mac_addr(hw) < 0) { 1163 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1164 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1165 goto init_fail; 1166 } 1167 #endif 1168 1169 /* check for valid mac address */ 1170 if (!is_valid_mac_addr(hw->mac.addr)) { 1171 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1172 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1173 goto init_fail; 1174 } 1175 1176 /* Set LAA state for 82571 chipset */ 1177 e1000_set_laa_state_82571(hw, B_TRUE); 1178 1179 /* Master Latency Timer implementation */ 1180 if (Adapter->master_latency_timer) { 1181 pci_config_put8(Adapter->osdep.cfg_handle, 1182 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1183 } 1184 1185 if (hw->mac.type < e1000_82547) { 1186 /* 1187 * Total FIFO is 64K 1188 */ 1189 if (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) 1190 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1191 else 1192 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1193 } else if (hw->mac.type >= e1000_82571 && 1194 hw->mac.type <= e1000_82572) { 1195 /* 1196 * Total FIFO is 48K 1197 */ 1198 if (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) 1199 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1200 else 1201 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1202 } else if (hw->mac.type == e1000_ich8lan) { 1203 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1204 } else if (hw->mac.type == e1000_ich9lan) { 1205 pba = E1000_PBA_12K; 1206 } else { 1207 /* 1208 * Total FIFO is 40K 1209 */ 1210 if (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) 1211 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1212 else 1213 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1214 } 1215 E1000_WRITE_REG(hw, E1000_PBA, pba); 1216 1217 /* 1218 * These parameters set thresholds for the adapter's generation(Tx) 1219 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1220 * settings. Flow control is enabled or disabled in the configuration 1221 * file. 1222 * High-water mark is set down from the top of the rx fifo (not 1223 * sensitive to max_frame_size) and low-water is set just below 1224 * high-water mark. 1225 * The high water mark must be low enough to fit one full frame above 1226 * it in the rx FIFO. Should be the lower of: 1227 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1228 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1229 * Rx FIFO size minus one full frame. 1230 */ 1231 high_water = min(((pba << 10) * 9 / 10), 1232 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_ich9lan) ? 1233 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1234 ((pba << 10) - hw->mac.max_frame_size))); 1235 1236 hw->mac.fc_high_water = high_water & 0xFFF8; 1237 hw->mac.fc_low_water = hw->mac.fc_high_water - 8; 1238 1239 if (hw->mac.type == e1000_80003es2lan) 1240 hw->mac.fc_pause_time = 0xFFFF; 1241 else 1242 hw->mac.fc_pause_time = E1000_FC_PAUSE_TIME; 1243 hw->mac.fc_send_xon = B_TRUE; 1244 hw->mac.fc = hw->mac.original_fc; 1245 1246 /* 1247 * Reset the adapter hardware the second time. 1248 */ 1249 if (e1000_reset_hw(hw) != 0) { 1250 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1251 goto init_fail; 1252 } 1253 1254 /* disable wakeup control by default */ 1255 if (hw->mac.type >= e1000_82544) 1256 E1000_WRITE_REG(hw, E1000_WUC, 0); 1257 1258 /* MWI setup */ 1259 e1000_pci_set_mwi(hw); 1260 1261 /* 1262 * Configure/Initialize hardware 1263 */ 1264 if (e1000_init_hw(hw) < 0) { 1265 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1266 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1267 goto init_fail; 1268 } 1269 1270 /* Disable Smart Power Down */ 1271 phy_spd_state(hw, B_FALSE); 1272 1273 /* Make sure driver has control */ 1274 e1000g_get_driver_control(hw); 1275 1276 /* 1277 * Initialize unicast addresses. 1278 */ 1279 e1000g_init_unicst(Adapter); 1280 1281 /* 1282 * Setup and initialize the mctable structures. After this routine 1283 * completes Multicast table will be set 1284 */ 1285 e1000g_setup_multicast(Adapter); 1286 msec_delay(5); 1287 1288 /* 1289 * Implement Adaptive IFS 1290 */ 1291 e1000_reset_adaptive(hw); 1292 1293 /* Setup Interrupt Throttling Register */ 1294 if (hw->mac.type >= e1000_82540) { 1295 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1296 } else 1297 Adapter->intr_adaptive = B_FALSE; 1298 1299 /* Start the timer for link setup */ 1300 if (hw->mac.autoneg) 1301 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1302 else 1303 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1304 1305 mutex_enter(&Adapter->link_lock); 1306 if (hw->phy.wait_for_link) { 1307 Adapter->link_complete = B_TRUE; 1308 } else { 1309 Adapter->link_complete = B_FALSE; 1310 Adapter->link_tid = timeout(e1000g_link_timer, 1311 (void *)Adapter, link_timeout); 1312 } 1313 mutex_exit(&Adapter->link_lock); 1314 1315 /* Enable PCI-Ex master */ 1316 if (hw->bus.type == e1000_bus_type_pci_express) { 1317 e1000_enable_pciex_master(hw); 1318 } 1319 1320 /* Save the state of the phy */ 1321 e1000g_get_phy_state(Adapter); 1322 1323 Adapter->init_count++; 1324 1325 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1326 goto init_fail; 1327 } 1328 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1329 goto init_fail; 1330 } 1331 1332 rw_exit(&Adapter->chip_lock); 1333 1334 return (DDI_SUCCESS); 1335 1336 init_fail: 1337 rw_exit(&Adapter->chip_lock); 1338 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1339 return (DDI_FAILURE); 1340 } 1341 1342 /* 1343 * Check if the link is up 1344 */ 1345 static boolean_t 1346 e1000g_link_up(struct e1000g *Adapter) 1347 { 1348 struct e1000_hw *hw; 1349 boolean_t link_up; 1350 1351 hw = &Adapter->shared; 1352 1353 e1000_check_for_link(hw); 1354 1355 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1356 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1357 ((hw->media_type == e1000_media_type_internal_serdes) && 1358 (hw->mac.serdes_has_link))) { 1359 link_up = B_TRUE; 1360 } else { 1361 link_up = B_FALSE; 1362 } 1363 1364 return (link_up); 1365 } 1366 1367 static void 1368 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1369 { 1370 struct iocblk *iocp; 1371 struct e1000g *e1000gp; 1372 enum ioc_reply status; 1373 int err; 1374 1375 iocp = (struct iocblk *)mp->b_rptr; 1376 iocp->ioc_error = 0; 1377 e1000gp = (struct e1000g *)arg; 1378 1379 ASSERT(e1000gp); 1380 if (e1000gp == NULL) { 1381 miocnak(q, mp, 0, EINVAL); 1382 return; 1383 } 1384 1385 switch (iocp->ioc_cmd) { 1386 1387 case LB_GET_INFO_SIZE: 1388 case LB_GET_INFO: 1389 case LB_GET_MODE: 1390 case LB_SET_MODE: 1391 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1392 break; 1393 1394 case ND_GET: 1395 case ND_SET: 1396 status = e1000g_nd_ioctl(e1000gp, q, mp, iocp); 1397 break; 1398 1399 #ifdef E1000G_DEBUG 1400 case E1000G_IOC_REG_PEEK: 1401 case E1000G_IOC_REG_POKE: 1402 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1403 break; 1404 case E1000G_IOC_CHIP_RESET: 1405 e1000gp->reset_count++; 1406 if (e1000g_reset(e1000gp)) 1407 status = IOC_ACK; 1408 else 1409 status = IOC_INVAL; 1410 break; 1411 #endif 1412 default: 1413 status = IOC_INVAL; 1414 break; 1415 } 1416 1417 /* 1418 * Decide how to reply 1419 */ 1420 switch (status) { 1421 default: 1422 case IOC_INVAL: 1423 /* 1424 * Error, reply with a NAK and EINVAL or the specified error 1425 */ 1426 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1427 EINVAL : iocp->ioc_error); 1428 break; 1429 1430 case IOC_DONE: 1431 /* 1432 * OK, reply already sent 1433 */ 1434 break; 1435 1436 case IOC_ACK: 1437 /* 1438 * OK, reply with an ACK 1439 */ 1440 miocack(q, mp, 0, 0); 1441 break; 1442 1443 case IOC_REPLY: 1444 /* 1445 * OK, send prepared reply as ACK or NAK 1446 */ 1447 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1448 M_IOCACK : M_IOCNAK; 1449 qreply(q, mp); 1450 break; 1451 } 1452 } 1453 1454 static int 1455 e1000g_m_start(void *arg) 1456 { 1457 struct e1000g *Adapter = (struct e1000g *)arg; 1458 1459 return (e1000g_start(Adapter, B_TRUE)); 1460 } 1461 1462 static int 1463 e1000g_start(struct e1000g *Adapter, boolean_t global) 1464 { 1465 if (global) { 1466 /* Allocate dma resources for descriptors and buffers */ 1467 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1468 e1000g_log(Adapter, CE_WARN, 1469 "Alloc DMA resources failed"); 1470 return (ENOTACTIVE); 1471 } 1472 Adapter->rx_buffer_setup = B_FALSE; 1473 } 1474 1475 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1476 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1477 e1000g_log(Adapter, CE_WARN, 1478 "Adapter initialization failed"); 1479 if (global) 1480 e1000g_release_dma_resources(Adapter); 1481 return (ENOTACTIVE); 1482 } 1483 } 1484 1485 rw_enter(&Adapter->chip_lock, RW_WRITER); 1486 1487 /* Setup and initialize the transmit structures */ 1488 e1000g_tx_setup(Adapter); 1489 msec_delay(5); 1490 1491 /* Setup and initialize the receive structures */ 1492 e1000g_rx_setup(Adapter); 1493 msec_delay(5); 1494 1495 e1000g_mask_interrupt(Adapter); 1496 1497 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1498 rw_exit(&Adapter->chip_lock); 1499 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1500 return (ENOTACTIVE); 1501 } 1502 1503 Adapter->chip_state = E1000G_START; 1504 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1505 1506 rw_exit(&Adapter->chip_lock); 1507 1508 /* Enable and start the watchdog timer */ 1509 enable_watchdog_timer(Adapter); 1510 1511 return (0); 1512 } 1513 1514 static void 1515 e1000g_m_stop(void *arg) 1516 { 1517 struct e1000g *Adapter = (struct e1000g *)arg; 1518 1519 e1000g_stop(Adapter, B_TRUE); 1520 } 1521 1522 static void 1523 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1524 { 1525 /* Set stop flags */ 1526 rw_enter(&Adapter->chip_lock, RW_WRITER); 1527 1528 Adapter->chip_state = E1000G_STOP; 1529 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1530 1531 rw_exit(&Adapter->chip_lock); 1532 1533 /* Drain tx sessions */ 1534 (void) e1000g_tx_drain(Adapter); 1535 1536 /* Disable and stop all the timers */ 1537 disable_watchdog_timer(Adapter); 1538 stop_link_timer(Adapter); 1539 stop_82547_timer(Adapter->tx_ring); 1540 1541 /* Stop the chip and release pending resources */ 1542 rw_enter(&Adapter->chip_lock, RW_WRITER); 1543 1544 e1000g_clear_all_interrupts(Adapter); 1545 if (e1000_reset_hw(&Adapter->shared) != 0) { 1546 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1547 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1548 } 1549 1550 /* Release resources still held by the TX descriptors */ 1551 e1000g_tx_clean(Adapter); 1552 1553 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1554 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1555 1556 /* Clean the pending rx jumbo packet fragment */ 1557 e1000g_rx_clean(Adapter); 1558 1559 rw_exit(&Adapter->chip_lock); 1560 1561 if (global) 1562 e1000g_release_dma_resources(Adapter); 1563 } 1564 1565 static void 1566 e1000g_rx_clean(struct e1000g *Adapter) 1567 { 1568 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 1569 1570 if (rx_ring->rx_mblk != NULL) { 1571 freemsg(rx_ring->rx_mblk); 1572 rx_ring->rx_mblk = NULL; 1573 rx_ring->rx_mblk_tail = NULL; 1574 rx_ring->rx_mblk_len = 0; 1575 } 1576 } 1577 1578 static void 1579 e1000g_tx_clean(struct e1000g *Adapter) 1580 { 1581 e1000g_tx_ring_t *tx_ring; 1582 p_tx_sw_packet_t packet; 1583 mblk_t *mp; 1584 mblk_t *nmp; 1585 uint32_t packet_count; 1586 1587 tx_ring = Adapter->tx_ring; 1588 1589 /* 1590 * Here we don't need to protect the lists using 1591 * the usedlist_lock and freelist_lock, for they 1592 * have been protected by the chip_lock. 1593 */ 1594 mp = NULL; 1595 nmp = NULL; 1596 packet_count = 0; 1597 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1598 while (packet != NULL) { 1599 if (packet->mp != NULL) { 1600 /* Assemble the message chain */ 1601 if (mp == NULL) { 1602 mp = packet->mp; 1603 nmp = packet->mp; 1604 } else { 1605 nmp->b_next = packet->mp; 1606 nmp = packet->mp; 1607 } 1608 /* Disconnect the message from the sw packet */ 1609 packet->mp = NULL; 1610 } 1611 1612 e1000g_free_tx_swpkt(packet); 1613 packet_count++; 1614 1615 packet = (p_tx_sw_packet_t) 1616 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1617 } 1618 1619 if (mp != NULL) 1620 freemsgchain(mp); 1621 1622 if (packet_count > 0) { 1623 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1624 QUEUE_INIT_LIST(&tx_ring->used_list); 1625 1626 /* Setup TX descriptor pointers */ 1627 tx_ring->tbd_next = tx_ring->tbd_first; 1628 tx_ring->tbd_oldest = tx_ring->tbd_first; 1629 1630 /* Setup our HW Tx Head & Tail descriptor pointers */ 1631 E1000_WRITE_REG(&Adapter->shared, E1000_TDH, 0); 1632 E1000_WRITE_REG(&Adapter->shared, E1000_TDT, 0); 1633 } 1634 } 1635 1636 static boolean_t 1637 e1000g_tx_drain(struct e1000g *Adapter) 1638 { 1639 int i; 1640 boolean_t done; 1641 e1000g_tx_ring_t *tx_ring; 1642 1643 tx_ring = Adapter->tx_ring; 1644 1645 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1646 for (i = 0; i < TX_DRAIN_TIME; i++) { 1647 mutex_enter(&tx_ring->usedlist_lock); 1648 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1649 mutex_exit(&tx_ring->usedlist_lock); 1650 1651 if (done) 1652 break; 1653 1654 msec_delay(1); 1655 } 1656 1657 return (done); 1658 } 1659 1660 static boolean_t 1661 e1000g_rx_drain(struct e1000g *Adapter) 1662 { 1663 e1000g_rx_ring_t *rx_ring; 1664 p_rx_sw_packet_t packet; 1665 boolean_t done; 1666 1667 rx_ring = Adapter->rx_ring; 1668 done = B_TRUE; 1669 1670 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 1671 1672 while (rx_ring->pending_list != NULL) { 1673 packet = rx_ring->pending_list; 1674 rx_ring->pending_list = 1675 rx_ring->pending_list->next; 1676 1677 if (packet->flag == E1000G_RX_SW_STOP) { 1678 packet->flag = E1000G_RX_SW_DETACH; 1679 done = B_FALSE; 1680 } else { 1681 ASSERT(packet->flag == E1000G_RX_SW_FREE); 1682 ASSERT(packet->mp == NULL); 1683 e1000g_free_rx_sw_packet(packet); 1684 } 1685 } 1686 1687 rw_exit(&e1000g_rx_detach_lock); 1688 1689 return (done); 1690 } 1691 1692 boolean_t 1693 e1000g_reset(struct e1000g *Adapter) 1694 { 1695 e1000g_stop(Adapter, B_FALSE); 1696 1697 if (e1000g_start(Adapter, B_FALSE)) { 1698 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1699 return (B_FALSE); 1700 } 1701 1702 return (B_TRUE); 1703 } 1704 1705 boolean_t 1706 e1000g_global_reset(struct e1000g *Adapter) 1707 { 1708 e1000g_stop(Adapter, B_TRUE); 1709 1710 Adapter->init_count = 0; 1711 1712 if (e1000g_start(Adapter, B_TRUE)) { 1713 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1714 return (B_FALSE); 1715 } 1716 1717 return (B_TRUE); 1718 } 1719 1720 /* 1721 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 1722 * 1723 * This interrupt service routine is for PCI-Express adapters. 1724 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 1725 * bit is set. 1726 */ 1727 static uint_t 1728 e1000g_intr_pciexpress(caddr_t arg) 1729 { 1730 struct e1000g *Adapter; 1731 uint32_t icr; 1732 1733 Adapter = (struct e1000g *)arg; 1734 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1735 1736 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1737 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1738 1739 if (icr & E1000_ICR_INT_ASSERTED) { 1740 /* 1741 * E1000_ICR_INT_ASSERTED bit was set: 1742 * Read(Clear) the ICR, claim this interrupt, 1743 * look for work to do. 1744 */ 1745 e1000g_intr_work(Adapter, icr); 1746 return (DDI_INTR_CLAIMED); 1747 } else { 1748 /* 1749 * E1000_ICR_INT_ASSERTED bit was not set: 1750 * Don't claim this interrupt, return immediately. 1751 */ 1752 return (DDI_INTR_UNCLAIMED); 1753 } 1754 } 1755 1756 /* 1757 * e1000g_intr - ISR for PCI/PCI-X chipsets 1758 * 1759 * This interrupt service routine is for PCI/PCI-X adapters. 1760 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 1761 * bit is set or not. 1762 */ 1763 static uint_t 1764 e1000g_intr(caddr_t arg) 1765 { 1766 struct e1000g *Adapter; 1767 uint32_t icr; 1768 1769 Adapter = (struct e1000g *)arg; 1770 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1771 1772 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1773 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1774 1775 if (icr) { 1776 /* 1777 * Any bit was set in ICR: 1778 * Read(Clear) the ICR, claim this interrupt, 1779 * look for work to do. 1780 */ 1781 e1000g_intr_work(Adapter, icr); 1782 return (DDI_INTR_CLAIMED); 1783 } else { 1784 /* 1785 * No bit was set in ICR: 1786 * Don't claim this interrupt, return immediately. 1787 */ 1788 return (DDI_INTR_UNCLAIMED); 1789 } 1790 } 1791 1792 /* 1793 * e1000g_intr_work - actual processing of ISR 1794 * 1795 * Read(clear) the ICR contents and call appropriate interrupt 1796 * processing routines. 1797 */ 1798 static void 1799 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 1800 { 1801 struct e1000_hw *hw; 1802 hw = &Adapter->shared; 1803 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 1804 uint32_t itr; 1805 1806 Adapter->rx_pkt_cnt = 0; 1807 Adapter->tx_pkt_cnt = 0; 1808 1809 rw_enter(&Adapter->chip_lock, RW_READER); 1810 /* 1811 * Here we need to check the "chip_state" flag within the chip_lock to 1812 * ensure the receive routine will not execute when the adapter is 1813 * being reset. 1814 */ 1815 if (Adapter->chip_state != E1000G_START) { 1816 rw_exit(&Adapter->chip_lock); 1817 return; 1818 } 1819 1820 if (icr & E1000_ICR_RXT0) { 1821 mblk_t *mp; 1822 1823 mp = e1000g_receive(Adapter); 1824 1825 rw_exit(&Adapter->chip_lock); 1826 1827 if (mp != NULL) 1828 mac_rx(Adapter->mh, Adapter->mrh, mp); 1829 } else 1830 rw_exit(&Adapter->chip_lock); 1831 1832 if (icr & E1000_ICR_TXDW) { 1833 if (!Adapter->tx_intr_enable) 1834 e1000g_clear_tx_interrupt(Adapter); 1835 1836 /* Recycle the tx descriptors */ 1837 rw_enter(&Adapter->chip_lock, RW_READER); 1838 e1000g_recycle(tx_ring); 1839 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 1840 rw_exit(&Adapter->chip_lock); 1841 1842 /* Schedule the re-transmit */ 1843 if (tx_ring->resched_needed && 1844 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 1845 tx_ring->resched_needed = B_FALSE; 1846 mac_tx_update(Adapter->mh); 1847 E1000G_STAT(tx_ring->stat_reschedule); 1848 } 1849 } 1850 1851 if (Adapter->intr_adaptive) { 1852 itr = e1000g_get_itr(Adapter->rx_pkt_cnt, Adapter->tx_pkt_cnt, 1853 Adapter->intr_throttling_rate); 1854 if (itr) { 1855 E1000_WRITE_REG(hw, E1000_ITR, itr); 1856 Adapter->intr_throttling_rate = itr; 1857 } 1858 } 1859 1860 /* 1861 * The Receive Sequence errors RXSEQ and the link status change LSC 1862 * are checked to detect that the cable has been pulled out. For 1863 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1864 * are an indication that cable is not connected. 1865 */ 1866 if ((icr & E1000_ICR_RXSEQ) || 1867 (icr & E1000_ICR_LSC) || 1868 (icr & E1000_ICR_GPI_EN1)) { 1869 boolean_t link_changed; 1870 timeout_id_t tid = 0; 1871 1872 stop_watchdog_timer(Adapter); 1873 1874 rw_enter(&Adapter->chip_lock, RW_WRITER); 1875 1876 /* 1877 * Because we got a link-status-change interrupt, force 1878 * e1000_check_for_link() to look at phy 1879 */ 1880 Adapter->shared.mac.get_link_status = B_TRUE; 1881 1882 /* e1000g_link_check takes care of link status change */ 1883 link_changed = e1000g_link_check(Adapter); 1884 1885 /* Get new phy state */ 1886 e1000g_get_phy_state(Adapter); 1887 1888 /* 1889 * If the link timer has not timed out, we'll not notify 1890 * the upper layer with any link state until the link is up. 1891 */ 1892 if (link_changed && !Adapter->link_complete) { 1893 if (Adapter->link_state == LINK_STATE_UP) { 1894 mutex_enter(&Adapter->link_lock); 1895 Adapter->link_complete = B_TRUE; 1896 tid = Adapter->link_tid; 1897 Adapter->link_tid = 0; 1898 mutex_exit(&Adapter->link_lock); 1899 } else { 1900 link_changed = B_FALSE; 1901 } 1902 } 1903 rw_exit(&Adapter->chip_lock); 1904 1905 if (link_changed) { 1906 if (tid != 0) 1907 (void) untimeout(tid); 1908 1909 /* 1910 * Workaround for esb2. Data stuck in fifo on a link 1911 * down event. Reset the adapter to recover it. 1912 */ 1913 if ((Adapter->link_state == LINK_STATE_DOWN) && 1914 (Adapter->shared.mac.type == e1000_80003es2lan)) 1915 (void) e1000g_reset(Adapter); 1916 1917 mac_link_update(Adapter->mh, Adapter->link_state); 1918 } 1919 1920 start_watchdog_timer(Adapter); 1921 } 1922 } 1923 1924 static uint32_t 1925 e1000g_get_itr(uint32_t rx_packet, uint32_t tx_packet, uint32_t cur_itr) 1926 { 1927 uint32_t new_itr; 1928 1929 /* 1930 * Determine a propper itr according to rx/tx packet count 1931 * per interrupt, the value of itr are based on document 1932 * and testing. 1933 */ 1934 if ((rx_packet < DEFAULT_INTR_PACKET_LOW) || 1935 (tx_packet < DEFAULT_INTR_PACKET_LOW)) { 1936 new_itr = DEFAULT_INTR_THROTTLING_LOW; 1937 goto itr_done; 1938 } 1939 if ((rx_packet > DEFAULT_INTR_PACKET_HIGH) || 1940 (tx_packet > DEFAULT_INTR_PACKET_HIGH)) { 1941 new_itr = DEFAULT_INTR_THROTTLING_LOW; 1942 goto itr_done; 1943 } 1944 if (cur_itr < DEFAULT_INTR_THROTTLING_HIGH) { 1945 new_itr = cur_itr + (DEFAULT_INTR_THROTTLING_HIGH >> 2); 1946 if (new_itr > DEFAULT_INTR_THROTTLING_HIGH) 1947 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 1948 } else 1949 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 1950 1951 itr_done: 1952 if (cur_itr == new_itr) 1953 return (0); 1954 else 1955 return (new_itr); 1956 } 1957 1958 static void 1959 e1000g_init_unicst(struct e1000g *Adapter) 1960 { 1961 struct e1000_hw *hw; 1962 int slot; 1963 1964 hw = &Adapter->shared; 1965 1966 if (!Adapter->unicst_init) { 1967 /* Initialize the multiple unicast addresses */ 1968 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 1969 1970 if ((hw->mac.type == e1000_82571) && 1971 (e1000_get_laa_state_82571(hw) == B_TRUE)) 1972 Adapter->unicst_total--; 1973 1974 Adapter->unicst_avail = Adapter->unicst_total - 1; 1975 1976 /* Store the default mac address */ 1977 e1000_rar_set(hw, hw->mac.addr, 0); 1978 if ((hw->mac.type == e1000_82571) && 1979 (e1000_get_laa_state_82571(hw) == B_TRUE)) 1980 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 1981 1982 bcopy(hw->mac.addr, Adapter->unicst_addr[0].mac.addr, 1983 ETHERADDRL); 1984 Adapter->unicst_addr[0].mac.set = 1; 1985 1986 for (slot = 1; slot < Adapter->unicst_total; slot++) 1987 Adapter->unicst_addr[slot].mac.set = 0; 1988 1989 Adapter->unicst_init = B_TRUE; 1990 } else { 1991 /* Recover the default mac address */ 1992 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac.addr, 1993 ETHERADDRL); 1994 1995 /* Store the default mac address */ 1996 e1000_rar_set(hw, hw->mac.addr, 0); 1997 if ((hw->mac.type == e1000_82571) && 1998 (e1000_get_laa_state_82571(hw) == B_TRUE)) 1999 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2000 2001 /* Re-configure the RAR registers */ 2002 for (slot = 1; slot < Adapter->unicst_total; slot++) 2003 e1000_rar_set(hw, 2004 Adapter->unicst_addr[slot].mac.addr, slot); 2005 } 2006 2007 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2008 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2009 } 2010 2011 static int 2012 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 2013 { 2014 struct e1000g *Adapter; 2015 2016 Adapter = (struct e1000g *)arg; 2017 2018 /* Store the default MAC address */ 2019 bcopy(mac_addr, Adapter->shared.mac.addr, ETHERADDRL); 2020 2021 /* Set MAC address in address slot 0, which is the default address */ 2022 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 2023 } 2024 2025 static int 2026 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2027 mac_addr_slot_t slot) 2028 { 2029 struct e1000_hw *hw; 2030 2031 hw = &Adapter->shared; 2032 2033 rw_enter(&Adapter->chip_lock, RW_WRITER); 2034 2035 #ifndef NO_82542_SUPPORT 2036 /* 2037 * The first revision of Wiseman silicon (rev 2.0) has an errata 2038 * that requires the receiver to be in reset when any of the 2039 * receive address registers (RAR regs) are accessed. The first 2040 * rev of Wiseman silicon also requires MWI to be disabled when 2041 * a global reset or a receive reset is issued. So before we 2042 * initialize the RARs, we check the rev of the Wiseman controller 2043 * and work around any necessary HW errata. 2044 */ 2045 if ((hw->mac.type == e1000_82542) && 2046 (hw->revision_id == E1000_REVISION_2)) { 2047 e1000_pci_clear_mwi(hw); 2048 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2049 msec_delay(5); 2050 } 2051 #endif 2052 2053 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 2054 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2055 2056 if (slot == 0) { 2057 if ((hw->mac.type == e1000_82571) && 2058 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2059 e1000_rar_set(hw, (uint8_t *)mac_addr, LAST_RAR_ENTRY); 2060 } 2061 2062 #ifndef NO_82542_SUPPORT 2063 /* 2064 * If we are using Wiseman rev 2.0 silicon, we will have previously 2065 * put the receive in reset, and disabled MWI, to work around some 2066 * HW errata. Now we should take the receiver out of reset, and 2067 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2068 */ 2069 if ((hw->mac.type == e1000_82542) && 2070 (hw->revision_id == E1000_REVISION_2)) { 2071 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2072 msec_delay(1); 2073 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2074 e1000_pci_set_mwi(hw); 2075 e1000g_rx_setup(Adapter); 2076 } 2077 #endif 2078 2079 rw_exit(&Adapter->chip_lock); 2080 2081 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2082 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2083 return (EIO); 2084 } 2085 2086 return (0); 2087 } 2088 2089 /* 2090 * e1000g_m_unicst_add() - will find an unused address slot, set the 2091 * address value to the one specified, reserve that slot and enable 2092 * the NIC to start filtering on the new MAC address. 2093 * Returns 0 on success. 2094 */ 2095 static int 2096 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 2097 { 2098 struct e1000g *Adapter = (struct e1000g *)arg; 2099 mac_addr_slot_t slot; 2100 int err; 2101 2102 if (mac_unicst_verify(Adapter->mh, 2103 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2104 return (EINVAL); 2105 2106 rw_enter(&Adapter->chip_lock, RW_WRITER); 2107 if (Adapter->unicst_avail == 0) { 2108 /* no slots available */ 2109 rw_exit(&Adapter->chip_lock); 2110 return (ENOSPC); 2111 } 2112 2113 /* 2114 * Primary/default address is in slot 0. The next addresses 2115 * are the multiple MAC addresses. So multiple MAC address 0 2116 * is in slot 1, 1 in slot 2, and so on. So the first multiple 2117 * MAC address resides in slot 1. 2118 */ 2119 for (slot = 1; slot < Adapter->unicst_total; slot++) { 2120 if (Adapter->unicst_addr[slot].mac.set == 0) { 2121 Adapter->unicst_addr[slot].mac.set = 1; 2122 break; 2123 } 2124 } 2125 2126 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 2127 2128 Adapter->unicst_avail--; 2129 rw_exit(&Adapter->chip_lock); 2130 2131 maddr->mma_slot = slot; 2132 2133 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 2134 rw_enter(&Adapter->chip_lock, RW_WRITER); 2135 Adapter->unicst_addr[slot].mac.set = 0; 2136 Adapter->unicst_avail++; 2137 rw_exit(&Adapter->chip_lock); 2138 } 2139 2140 return (err); 2141 } 2142 2143 /* 2144 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 2145 * call to e1000g_m_unicst_add(). The slot number that was returned in 2146 * e1000g_m_unicst_add() is passed in the call to remove the address. 2147 * Returns 0 on success. 2148 */ 2149 static int 2150 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 2151 { 2152 struct e1000g *Adapter = (struct e1000g *)arg; 2153 int err; 2154 2155 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2156 return (EINVAL); 2157 2158 rw_enter(&Adapter->chip_lock, RW_WRITER); 2159 if (Adapter->unicst_addr[slot].mac.set == 1) { 2160 Adapter->unicst_addr[slot].mac.set = 0; 2161 Adapter->unicst_avail++; 2162 rw_exit(&Adapter->chip_lock); 2163 2164 /* Copy the default address to the passed slot */ 2165 if (err = e1000g_unicst_set(Adapter, 2166 Adapter->unicst_addr[0].mac.addr, slot) != 0) { 2167 rw_enter(&Adapter->chip_lock, RW_WRITER); 2168 Adapter->unicst_addr[slot].mac.set = 1; 2169 Adapter->unicst_avail--; 2170 rw_exit(&Adapter->chip_lock); 2171 } 2172 return (err); 2173 } 2174 rw_exit(&Adapter->chip_lock); 2175 2176 return (EINVAL); 2177 } 2178 2179 /* 2180 * e1000g_m_unicst_modify() - modifies the value of an address that 2181 * has been added by e1000g_m_unicst_add(). The new address, address 2182 * length and the slot number that was returned in the call to add 2183 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2184 * set to 0. Returns 0 on success. 2185 */ 2186 static int 2187 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2188 { 2189 struct e1000g *Adapter = (struct e1000g *)arg; 2190 mac_addr_slot_t slot; 2191 2192 if (mac_unicst_verify(Adapter->mh, 2193 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2194 return (EINVAL); 2195 2196 slot = maddr->mma_slot; 2197 2198 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2199 return (EINVAL); 2200 2201 rw_enter(&Adapter->chip_lock, RW_WRITER); 2202 if (Adapter->unicst_addr[slot].mac.set == 1) { 2203 rw_exit(&Adapter->chip_lock); 2204 2205 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2206 } 2207 rw_exit(&Adapter->chip_lock); 2208 2209 return (EINVAL); 2210 } 2211 2212 /* 2213 * e1000g_m_unicst_get() - will get the MAC address and all other 2214 * information related to the address slot passed in mac_multi_addr_t. 2215 * mma_flags should be set to 0 in the call. 2216 * On return, mma_flags can take the following values: 2217 * 1) MMAC_SLOT_UNUSED 2218 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2219 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2220 * 4) MMAC_SLOT_USED 2221 */ 2222 static int 2223 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2224 { 2225 struct e1000g *Adapter = (struct e1000g *)arg; 2226 mac_addr_slot_t slot; 2227 2228 slot = maddr->mma_slot; 2229 2230 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2231 return (EINVAL); 2232 2233 rw_enter(&Adapter->chip_lock, RW_WRITER); 2234 if (Adapter->unicst_addr[slot].mac.set == 1) { 2235 bcopy(Adapter->unicst_addr[slot].mac.addr, 2236 maddr->mma_addr, ETHERADDRL); 2237 maddr->mma_flags = MMAC_SLOT_USED; 2238 } else { 2239 maddr->mma_flags = MMAC_SLOT_UNUSED; 2240 } 2241 rw_exit(&Adapter->chip_lock); 2242 2243 return (0); 2244 } 2245 2246 static int 2247 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2248 { 2249 struct e1000_hw *hw = &Adapter->shared; 2250 unsigned i; 2251 int res = 0; 2252 2253 rw_enter(&Adapter->chip_lock, RW_WRITER); 2254 2255 if ((multiaddr[0] & 01) == 0) { 2256 res = EINVAL; 2257 goto done; 2258 } 2259 2260 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2261 res = ENOENT; 2262 goto done; 2263 } 2264 2265 bcopy(multiaddr, 2266 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2267 Adapter->mcast_count++; 2268 2269 /* 2270 * Update the MC table in the hardware 2271 */ 2272 e1000g_clear_interrupt(Adapter); 2273 2274 e1000g_setup_multicast(Adapter); 2275 2276 #ifndef NO_82542_SUPPORT 2277 if ((hw->mac.type == e1000_82542) && 2278 (hw->revision_id == E1000_REVISION_2)) 2279 e1000g_rx_setup(Adapter); 2280 #endif 2281 2282 e1000g_mask_interrupt(Adapter); 2283 2284 done: 2285 rw_exit(&Adapter->chip_lock); 2286 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2287 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2288 res = EIO; 2289 } 2290 2291 return (res); 2292 } 2293 2294 static int 2295 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2296 { 2297 struct e1000_hw *hw = &Adapter->shared; 2298 unsigned i; 2299 2300 rw_enter(&Adapter->chip_lock, RW_WRITER); 2301 2302 for (i = 0; i < Adapter->mcast_count; i++) { 2303 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2304 ETHERADDRL) == 0) { 2305 for (i++; i < Adapter->mcast_count; i++) { 2306 Adapter->mcast_table[i - 1] = 2307 Adapter->mcast_table[i]; 2308 } 2309 Adapter->mcast_count--; 2310 break; 2311 } 2312 } 2313 2314 /* 2315 * Update the MC table in the hardware 2316 */ 2317 e1000g_clear_interrupt(Adapter); 2318 2319 e1000g_setup_multicast(Adapter); 2320 2321 #ifndef NO_82542_SUPPORT 2322 if ((hw->mac.type == e1000_82542) && 2323 (hw->revision_id == E1000_REVISION_2)) 2324 e1000g_rx_setup(Adapter); 2325 #endif 2326 2327 e1000g_mask_interrupt(Adapter); 2328 2329 done: 2330 rw_exit(&Adapter->chip_lock); 2331 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2332 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2333 return (EIO); 2334 } 2335 2336 return (0); 2337 } 2338 2339 /* 2340 * e1000g_setup_multicast - setup multicast data structures 2341 * 2342 * This routine initializes all of the multicast related structures. 2343 */ 2344 void 2345 e1000g_setup_multicast(struct e1000g *Adapter) 2346 { 2347 uint8_t *mc_addr_list; 2348 uint32_t mc_addr_count; 2349 uint32_t rctl; 2350 struct e1000_hw *hw; 2351 2352 hw = &Adapter->shared; 2353 2354 /* 2355 * The e1000g has the ability to do perfect filtering of 16 2356 * addresses. The driver uses one of the e1000g's 16 receive 2357 * address registers for its node/network/mac/individual address. 2358 * So, we have room for up to 15 multicast addresses in the CAM, 2359 * additional MC addresses are handled by the MTA (Multicast Table 2360 * Array) 2361 */ 2362 2363 rctl = E1000_READ_REG(hw, E1000_RCTL); 2364 2365 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2366 2367 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2368 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2369 "Adapter requested more than %d MC Addresses.\n", 2370 MAX_NUM_MULTICAST_ADDRESSES); 2371 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2372 } else { 2373 /* 2374 * Set the number of MC addresses that we are being 2375 * requested to use 2376 */ 2377 mc_addr_count = Adapter->mcast_count; 2378 } 2379 #ifndef NO_82542_SUPPORT 2380 /* 2381 * The Wiseman 2.0 silicon has an errata by which the receiver will 2382 * hang while writing to the receive address registers if the receiver 2383 * is not in reset before writing to the registers. Updating the RAR 2384 * is done during the setting up of the multicast table, hence the 2385 * receiver has to be put in reset before updating the multicast table 2386 * and then taken out of reset at the end 2387 */ 2388 /* 2389 * if WMI was enabled then dis able it before issueing the global 2390 * reset to the hardware. 2391 */ 2392 /* 2393 * Only required for WISEMAN_2_0 2394 */ 2395 if ((hw->mac.type == e1000_82542) && 2396 (hw->revision_id == E1000_REVISION_2)) { 2397 e1000_pci_clear_mwi(hw); 2398 /* 2399 * The e1000g must be in reset before changing any RA 2400 * registers. Reset receive unit. The chip will remain in 2401 * the reset state until software explicitly restarts it. 2402 */ 2403 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2404 /* Allow receiver time to go in to reset */ 2405 msec_delay(5); 2406 } 2407 #endif 2408 2409 e1000_mc_addr_list_update(hw, mc_addr_list, mc_addr_count, 2410 Adapter->unicst_total, hw->mac.rar_entry_count); 2411 2412 #ifndef NO_82542_SUPPORT 2413 /* 2414 * Only for Wiseman_2_0 2415 * If MWI was enabled then re-enable it after issueing (as we 2416 * disabled it up there) the receive reset command. 2417 * Wainwright does not have a receive reset command and only thing 2418 * close to it is global reset which will require tx setup also 2419 */ 2420 if ((hw->mac.type == e1000_82542) && 2421 (hw->revision_id == E1000_REVISION_2)) { 2422 /* 2423 * if WMI was enabled then reenable it after issueing the 2424 * global or receive reset to the hardware. 2425 */ 2426 2427 /* 2428 * Take receiver out of reset 2429 * clear E1000_RCTL_RST bit (and all others) 2430 */ 2431 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2432 msec_delay(5); 2433 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2434 e1000_pci_set_mwi(hw); 2435 } 2436 #endif 2437 2438 /* 2439 * Restore original value 2440 */ 2441 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2442 } 2443 2444 int 2445 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2446 { 2447 struct e1000g *Adapter = (struct e1000g *)arg; 2448 2449 return ((add) ? multicst_add(Adapter, addr) 2450 : multicst_remove(Adapter, addr)); 2451 } 2452 2453 int 2454 e1000g_m_promisc(void *arg, boolean_t on) 2455 { 2456 struct e1000g *Adapter = (struct e1000g *)arg; 2457 uint32_t rctl; 2458 2459 rw_enter(&Adapter->chip_lock, RW_WRITER); 2460 2461 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2462 2463 if (on) 2464 rctl |= 2465 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2466 else 2467 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2468 2469 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2470 2471 Adapter->e1000g_promisc = on; 2472 2473 rw_exit(&Adapter->chip_lock); 2474 2475 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2476 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2477 return (EIO); 2478 } 2479 2480 return (0); 2481 } 2482 2483 static boolean_t 2484 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2485 { 2486 struct e1000g *Adapter = (struct e1000g *)arg; 2487 struct e1000_hw *hw = &Adapter->shared; 2488 2489 switch (cap) { 2490 case MAC_CAPAB_HCKSUM: { 2491 uint32_t *txflags = cap_data; 2492 /* 2493 * Checksum on/off selection via global parameters. 2494 * 2495 * If the chip is flagged as not capable of (correctly) 2496 * handling checksumming, we don't enable it on either 2497 * Rx or Tx side. Otherwise, we take this chip's settings 2498 * from the patchable global defaults. 2499 * 2500 * We advertise our capabilities only if TX offload is 2501 * enabled. On receive, the stack will accept checksummed 2502 * packets anyway, even if we haven't said we can deliver 2503 * them. 2504 */ 2505 switch (hw->mac.type) { 2506 case e1000_82540: 2507 case e1000_82544: 2508 case e1000_82545: 2509 case e1000_82545_rev_3: 2510 case e1000_82546: 2511 case e1000_82546_rev_3: 2512 case e1000_82571: 2513 case e1000_82572: 2514 case e1000_82573: 2515 case e1000_80003es2lan: 2516 *txflags = HCKSUM_IPHDRCKSUM | HCKSUM_INET_PARTIAL; 2517 break; 2518 2519 /* 2520 * For the following Intel PRO/1000 chipsets, we have not 2521 * tested the hardware checksum offload capability, so we 2522 * disable the capability for them. 2523 * e1000_82542, 2524 * e1000_82543, 2525 * e1000_82541, 2526 * e1000_82541_rev_2, 2527 * e1000_82547, 2528 * e1000_82547_rev_2, 2529 */ 2530 default: 2531 return (B_FALSE); 2532 } 2533 2534 break; 2535 } 2536 case MAC_CAPAB_POLL: 2537 /* 2538 * There's nothing for us to fill in, simply returning 2539 * B_TRUE stating that we support polling is sufficient. 2540 */ 2541 break; 2542 2543 case MAC_CAPAB_MULTIADDRESS: { 2544 multiaddress_capab_t *mmacp = cap_data; 2545 2546 /* 2547 * The number of MAC addresses made available by 2548 * this capability is one less than the total as 2549 * the primary address in slot 0 is counted in 2550 * the total. 2551 */ 2552 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2553 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2554 /* No multiple factory addresses, set mma_flag to 0 */ 2555 mmacp->maddr_flag = 0; 2556 mmacp->maddr_handle = Adapter; 2557 mmacp->maddr_add = e1000g_m_unicst_add; 2558 mmacp->maddr_remove = e1000g_m_unicst_remove; 2559 mmacp->maddr_modify = e1000g_m_unicst_modify; 2560 mmacp->maddr_get = e1000g_m_unicst_get; 2561 mmacp->maddr_reserve = NULL; 2562 break; 2563 } 2564 default: 2565 return (B_FALSE); 2566 } 2567 return (B_TRUE); 2568 } 2569 2570 /* 2571 * e1000g_get_conf - get configurations set in e1000g.conf 2572 * 2573 * This routine gets user-configured values out of the configuration 2574 * file e1000g.conf. 2575 * 2576 * For each configurable value, there is a minimum, a maximum, and a 2577 * default. 2578 * If user does not configure a value, use the default. 2579 * If user configures below the minimum, use the minumum. 2580 * If user configures above the maximum, use the maxumum. 2581 */ 2582 static void 2583 e1000g_get_conf(struct e1000g *Adapter) 2584 { 2585 struct e1000_hw *hw = &Adapter->shared; 2586 boolean_t tbi_compatibility = B_FALSE; 2587 2588 /* 2589 * get each configurable property from e1000g.conf 2590 */ 2591 2592 /* 2593 * NumTxDescriptors 2594 */ 2595 Adapter->tx_desc_num = 2596 e1000g_get_prop(Adapter, "NumTxDescriptors", 2597 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 2598 DEFAULT_NUM_TX_DESCRIPTOR); 2599 2600 /* 2601 * NumRxDescriptors 2602 */ 2603 Adapter->rx_desc_num = 2604 e1000g_get_prop(Adapter, "NumRxDescriptors", 2605 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 2606 DEFAULT_NUM_RX_DESCRIPTOR); 2607 2608 /* 2609 * NumRxFreeList 2610 */ 2611 Adapter->rx_freelist_num = 2612 e1000g_get_prop(Adapter, "NumRxFreeList", 2613 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 2614 DEFAULT_NUM_RX_FREELIST); 2615 2616 /* 2617 * NumTxPacketList 2618 */ 2619 Adapter->tx_freelist_num = 2620 e1000g_get_prop(Adapter, "NumTxPacketList", 2621 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 2622 DEFAULT_NUM_TX_FREELIST); 2623 2624 /* 2625 * FlowControl 2626 */ 2627 hw->mac.fc_send_xon = B_TRUE; 2628 hw->mac.fc = 2629 e1000g_get_prop(Adapter, "FlowControl", 2630 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 2631 /* 4 is the setting that says "let the eeprom decide" */ 2632 if (hw->mac.fc == 4) 2633 hw->mac.fc = e1000_fc_default; 2634 2635 /* 2636 * Max Num Receive Packets on Interrupt 2637 */ 2638 Adapter->rx_limit_onintr = 2639 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 2640 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 2641 DEFAULT_RX_LIMIT_ON_INTR); 2642 2643 /* 2644 * PHY master slave setting 2645 */ 2646 hw->phy.ms_type = 2647 e1000g_get_prop(Adapter, "SetMasterSlave", 2648 e1000_ms_hw_default, e1000_ms_auto, 2649 e1000_ms_hw_default); 2650 2651 /* 2652 * Parameter which controls TBI mode workaround, which is only 2653 * needed on certain switches such as Cisco 6500/Foundry 2654 */ 2655 tbi_compatibility = 2656 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 2657 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 2658 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 2659 2660 /* 2661 * MSI Enable 2662 */ 2663 Adapter->msi_enabled = 2664 e1000g_get_prop(Adapter, "MSIEnable", 2665 0, 1, DEFAULT_MSI_ENABLE); 2666 2667 /* 2668 * Interrupt Throttling Rate 2669 */ 2670 Adapter->intr_throttling_rate = 2671 e1000g_get_prop(Adapter, "intr_throttling_rate", 2672 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 2673 DEFAULT_INTR_THROTTLING); 2674 2675 /* 2676 * Adaptive Interrupt Blanking Enable/Disable 2677 * It is enabled by default 2678 */ 2679 Adapter->intr_adaptive = 2680 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 2681 B_TRUE : B_FALSE; 2682 2683 /* 2684 * Tx recycle threshold 2685 */ 2686 Adapter->tx_recycle_thresh = 2687 e1000g_get_prop(Adapter, "tx_recycle_thresh", 2688 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 2689 DEFAULT_TX_RECYCLE_THRESHOLD); 2690 2691 /* 2692 * Tx recycle descriptor number 2693 */ 2694 Adapter->tx_recycle_num = 2695 e1000g_get_prop(Adapter, "tx_recycle_num", 2696 MIN_TX_RECYCLE_NUM, MAX_TX_RECYCLE_NUM, 2697 DEFAULT_TX_RECYCLE_NUM); 2698 } 2699 2700 /* 2701 * e1000g_get_prop - routine to read properties 2702 * 2703 * Get a user-configure property value out of the configuration 2704 * file e1000g.conf. 2705 * 2706 * Caller provides name of the property, a default value, a minimum 2707 * value, and a maximum value. 2708 * 2709 * Return configured value of the property, with default, minimum and 2710 * maximum properly applied. 2711 */ 2712 static int 2713 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 2714 char *propname, /* name of the property */ 2715 int minval, /* minimum acceptable value */ 2716 int maxval, /* maximim acceptable value */ 2717 int defval) /* default value */ 2718 { 2719 int propval; /* value returned for requested property */ 2720 int *props; /* point to array of properties returned */ 2721 uint_t nprops; /* number of property value returned */ 2722 2723 /* 2724 * get the array of properties from the config file 2725 */ 2726 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 2727 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 2728 /* got some properties, test if we got enough */ 2729 if (Adapter->instance < nprops) { 2730 propval = props[Adapter->instance]; 2731 } else { 2732 /* not enough properties configured */ 2733 propval = defval; 2734 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 2735 "Not Enough %s values found in e1000g.conf" 2736 " - set to %d\n", 2737 propname, propval); 2738 } 2739 2740 /* free memory allocated for properties */ 2741 ddi_prop_free(props); 2742 2743 } else { 2744 propval = defval; 2745 } 2746 2747 /* 2748 * enforce limits 2749 */ 2750 if (propval > maxval) { 2751 propval = maxval; 2752 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 2753 "Too High %s value in e1000g.conf - set to %d\n", 2754 propname, propval); 2755 } 2756 2757 if (propval < minval) { 2758 propval = minval; 2759 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 2760 "Too Low %s value in e1000g.conf - set to %d\n", 2761 propname, propval); 2762 } 2763 2764 return (propval); 2765 } 2766 2767 static boolean_t 2768 e1000g_link_check(struct e1000g *Adapter) 2769 { 2770 uint16_t speed, duplex, phydata; 2771 boolean_t link_changed = B_FALSE; 2772 struct e1000_hw *hw; 2773 uint32_t reg_tarc; 2774 2775 hw = &Adapter->shared; 2776 2777 if (e1000g_link_up(Adapter)) { 2778 /* 2779 * The Link is up, check whether it was marked as down earlier 2780 */ 2781 if (Adapter->link_state != LINK_STATE_UP) { 2782 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2783 Adapter->link_speed = speed; 2784 Adapter->link_duplex = duplex; 2785 Adapter->link_state = LINK_STATE_UP; 2786 link_changed = B_TRUE; 2787 2788 Adapter->tx_link_down_timeout = 0; 2789 2790 if ((hw->mac.type == e1000_82571) || 2791 (hw->mac.type == e1000_82572)) { 2792 reg_tarc = E1000_READ_REG(hw, E1000_TARC0); 2793 if (speed == SPEED_1000) 2794 reg_tarc |= (1 << 21); 2795 else 2796 reg_tarc &= ~(1 << 21); 2797 E1000_WRITE_REG(hw, E1000_TARC0, reg_tarc); 2798 } 2799 } 2800 Adapter->smartspeed = 0; 2801 } else { 2802 if (Adapter->link_state != LINK_STATE_DOWN) { 2803 Adapter->link_speed = 0; 2804 Adapter->link_duplex = 0; 2805 Adapter->link_state = LINK_STATE_DOWN; 2806 link_changed = B_TRUE; 2807 2808 /* 2809 * SmartSpeed workaround for Tabor/TanaX, When the 2810 * driver loses link disable auto master/slave 2811 * resolution. 2812 */ 2813 if (hw->phy.type == e1000_phy_igp) { 2814 e1000_read_phy_reg(hw, 2815 PHY_1000T_CTRL, &phydata); 2816 phydata |= CR_1000T_MS_ENABLE; 2817 e1000_write_phy_reg(hw, 2818 PHY_1000T_CTRL, phydata); 2819 } 2820 } else { 2821 e1000g_smartspeed(Adapter); 2822 } 2823 2824 if (Adapter->chip_state == E1000G_START) { 2825 if (Adapter->tx_link_down_timeout < 2826 MAX_TX_LINK_DOWN_TIMEOUT) { 2827 Adapter->tx_link_down_timeout++; 2828 } else if (Adapter->tx_link_down_timeout == 2829 MAX_TX_LINK_DOWN_TIMEOUT) { 2830 e1000g_tx_clean(Adapter); 2831 Adapter->tx_link_down_timeout++; 2832 } 2833 } 2834 } 2835 2836 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2837 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2838 2839 return (link_changed); 2840 } 2841 2842 static void 2843 e1000g_local_timer(void *ws) 2844 { 2845 struct e1000g *Adapter = (struct e1000g *)ws; 2846 struct e1000_hw *hw; 2847 e1000g_ether_addr_t ether_addr; 2848 boolean_t link_changed; 2849 2850 hw = &Adapter->shared; 2851 2852 if (Adapter->chip_state == E1000G_ERROR) { 2853 Adapter->reset_count++; 2854 if (e1000g_global_reset(Adapter)) 2855 ddi_fm_service_impact(Adapter->dip, 2856 DDI_SERVICE_RESTORED); 2857 else 2858 ddi_fm_service_impact(Adapter->dip, 2859 DDI_SERVICE_LOST); 2860 return; 2861 } 2862 2863 if (e1000g_stall_check(Adapter)) { 2864 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 2865 "Tx stall detected. Activate automatic recovery.\n"); 2866 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 2867 Adapter->reset_count++; 2868 if (e1000g_reset(Adapter)) 2869 ddi_fm_service_impact(Adapter->dip, 2870 DDI_SERVICE_RESTORED); 2871 else 2872 ddi_fm_service_impact(Adapter->dip, 2873 DDI_SERVICE_LOST); 2874 return; 2875 } 2876 2877 link_changed = B_FALSE; 2878 rw_enter(&Adapter->chip_lock, RW_READER); 2879 if (Adapter->link_complete) 2880 link_changed = e1000g_link_check(Adapter); 2881 rw_exit(&Adapter->chip_lock); 2882 2883 if (link_changed) { 2884 /* 2885 * Workaround for esb2. Data stuck in fifo on a link 2886 * down event. Reset the adapter to recover it. 2887 */ 2888 if ((Adapter->link_state == LINK_STATE_DOWN) && 2889 (hw->mac.type == e1000_80003es2lan)) 2890 (void) e1000g_reset(Adapter); 2891 2892 mac_link_update(Adapter->mh, Adapter->link_state); 2893 } 2894 2895 /* 2896 * With 82571 controllers, any locally administered address will 2897 * be overwritten when there is a reset on the other port. 2898 * Detect this circumstance and correct it. 2899 */ 2900 if ((hw->mac.type == e1000_82571) && 2901 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 2902 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 2903 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 2904 2905 ether_addr.reg.low = ntohl(ether_addr.reg.low); 2906 ether_addr.reg.high = ntohl(ether_addr.reg.high); 2907 2908 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 2909 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 2910 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 2911 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 2912 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 2913 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 2914 e1000_rar_set(hw, hw->mac.addr, 0); 2915 } 2916 } 2917 2918 /* 2919 * Long TTL workaround for 82541/82547 2920 */ 2921 e1000_igp_ttl_workaround_82547(hw); 2922 2923 /* 2924 * Check for Adaptive IFS settings If there are lots of collisions 2925 * change the value in steps... 2926 * These properties should only be set for 10/100 2927 */ 2928 if ((hw->media_type == e1000_media_type_copper) && 2929 ((Adapter->link_speed == SPEED_100) || 2930 (Adapter->link_speed == SPEED_10))) { 2931 e1000_update_adaptive(hw); 2932 } 2933 /* 2934 * Set Timer Interrupts 2935 */ 2936 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2937 2938 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2939 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2940 2941 restart_watchdog_timer(Adapter); 2942 } 2943 2944 /* 2945 * The function e1000g_link_timer() is called when the timer for link setup 2946 * is expired, which indicates the completion of the link setup. The link 2947 * state will not be updated until the link setup is completed. And the 2948 * link state will not be sent to the upper layer through mac_link_update() 2949 * in this function. It will be updated in the local timer routine or the 2950 * interrupt service routine after the interface is started (plumbed). 2951 */ 2952 static void 2953 e1000g_link_timer(void *arg) 2954 { 2955 struct e1000g *Adapter = (struct e1000g *)arg; 2956 2957 mutex_enter(&Adapter->link_lock); 2958 Adapter->link_complete = B_TRUE; 2959 Adapter->link_tid = 0; 2960 mutex_exit(&Adapter->link_lock); 2961 } 2962 2963 /* 2964 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 2965 * 2966 * This function read the forced speed and duplex for 10/100 Mbps speeds 2967 * and also for 1000 Mbps speeds from the e1000g.conf file 2968 */ 2969 static void 2970 e1000g_force_speed_duplex(struct e1000g *Adapter) 2971 { 2972 int forced; 2973 struct e1000_mac_info *mac = &Adapter->shared.mac; 2974 struct e1000_phy_info *phy = &Adapter->shared.phy; 2975 2976 /* 2977 * get value out of config file 2978 */ 2979 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 2980 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 2981 2982 switch (forced) { 2983 case GDIAG_10_HALF: 2984 /* 2985 * Disable Auto Negotiation 2986 */ 2987 mac->autoneg = B_FALSE; 2988 mac->forced_speed_duplex = ADVERTISE_10_HALF; 2989 break; 2990 case GDIAG_10_FULL: 2991 /* 2992 * Disable Auto Negotiation 2993 */ 2994 mac->autoneg = B_FALSE; 2995 mac->forced_speed_duplex = ADVERTISE_10_FULL; 2996 break; 2997 case GDIAG_100_HALF: 2998 /* 2999 * Disable Auto Negotiation 3000 */ 3001 mac->autoneg = B_FALSE; 3002 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3003 break; 3004 case GDIAG_100_FULL: 3005 /* 3006 * Disable Auto Negotiation 3007 */ 3008 mac->autoneg = B_FALSE; 3009 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3010 break; 3011 case GDIAG_1000_FULL: 3012 /* 3013 * The gigabit spec requires autonegotiation. Therefore, 3014 * when the user wants to force the speed to 1000Mbps, we 3015 * enable AutoNeg, but only allow the harware to advertise 3016 * 1000Mbps. This is different from 10/100 operation, where 3017 * we are allowed to link without any negotiation. 3018 */ 3019 mac->autoneg = B_TRUE; 3020 phy->autoneg_advertised = ADVERTISE_1000_FULL; 3021 break; 3022 default: /* obey the setting of AutoNegAdvertised */ 3023 mac->autoneg = B_TRUE; 3024 phy->autoneg_advertised = 3025 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 3026 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 3027 AUTONEG_ADVERTISE_SPEED_DEFAULT); 3028 break; 3029 } /* switch */ 3030 } 3031 3032 /* 3033 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 3034 * 3035 * This function reads MaxFrameSize from e1000g.conf 3036 */ 3037 static void 3038 e1000g_get_max_frame_size(struct e1000g *Adapter) 3039 { 3040 int max_frame; 3041 struct e1000_mac_info *mac = &Adapter->shared.mac; 3042 struct e1000_phy_info *phy = &Adapter->shared.phy; 3043 3044 /* 3045 * get value out of config file 3046 */ 3047 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 3048 3049 switch (max_frame) { 3050 case 0: 3051 mac->max_frame_size = ETHERMAX; 3052 break; 3053 case 1: 3054 mac->max_frame_size = FRAME_SIZE_UPTO_4K; 3055 break; 3056 case 2: 3057 mac->max_frame_size = FRAME_SIZE_UPTO_8K; 3058 break; 3059 case 3: 3060 if (mac->type < e1000_82571) 3061 mac->max_frame_size = FRAME_SIZE_UPTO_16K; 3062 else 3063 mac->max_frame_size = FRAME_SIZE_UPTO_9K; 3064 break; 3065 default: 3066 mac->max_frame_size = ETHERMAX; 3067 break; 3068 } /* switch */ 3069 3070 /* ich8 does not do jumbo frames */ 3071 if (mac->type == e1000_ich8lan) { 3072 mac->max_frame_size = ETHERMAX; 3073 } 3074 3075 /* ich9 does not do jumbo frames on one phy type */ 3076 if ((mac->type == e1000_ich9lan) && 3077 (phy->type == e1000_phy_ife)) { 3078 mac->max_frame_size = ETHERMAX; 3079 } 3080 } 3081 3082 static void 3083 arm_watchdog_timer(struct e1000g *Adapter) 3084 { 3085 Adapter->watchdog_tid = 3086 timeout(e1000g_local_timer, 3087 (void *)Adapter, 1 * drv_usectohz(1000000)); 3088 } 3089 #pragma inline(arm_watchdog_timer) 3090 3091 static void 3092 enable_watchdog_timer(struct e1000g *Adapter) 3093 { 3094 mutex_enter(&Adapter->watchdog_lock); 3095 3096 if (!Adapter->watchdog_timer_enabled) { 3097 Adapter->watchdog_timer_enabled = B_TRUE; 3098 Adapter->watchdog_timer_started = B_TRUE; 3099 arm_watchdog_timer(Adapter); 3100 } 3101 3102 mutex_exit(&Adapter->watchdog_lock); 3103 } 3104 3105 static void 3106 disable_watchdog_timer(struct e1000g *Adapter) 3107 { 3108 timeout_id_t tid; 3109 3110 mutex_enter(&Adapter->watchdog_lock); 3111 3112 Adapter->watchdog_timer_enabled = B_FALSE; 3113 Adapter->watchdog_timer_started = B_FALSE; 3114 tid = Adapter->watchdog_tid; 3115 Adapter->watchdog_tid = 0; 3116 3117 mutex_exit(&Adapter->watchdog_lock); 3118 3119 if (tid != 0) 3120 (void) untimeout(tid); 3121 } 3122 3123 static void 3124 start_watchdog_timer(struct e1000g *Adapter) 3125 { 3126 mutex_enter(&Adapter->watchdog_lock); 3127 3128 if (Adapter->watchdog_timer_enabled) { 3129 if (!Adapter->watchdog_timer_started) { 3130 Adapter->watchdog_timer_started = B_TRUE; 3131 arm_watchdog_timer(Adapter); 3132 } 3133 } 3134 3135 mutex_exit(&Adapter->watchdog_lock); 3136 } 3137 3138 static void 3139 restart_watchdog_timer(struct e1000g *Adapter) 3140 { 3141 mutex_enter(&Adapter->watchdog_lock); 3142 3143 if (Adapter->watchdog_timer_started) 3144 arm_watchdog_timer(Adapter); 3145 3146 mutex_exit(&Adapter->watchdog_lock); 3147 } 3148 3149 static void 3150 stop_watchdog_timer(struct e1000g *Adapter) 3151 { 3152 timeout_id_t tid; 3153 3154 mutex_enter(&Adapter->watchdog_lock); 3155 3156 Adapter->watchdog_timer_started = B_FALSE; 3157 tid = Adapter->watchdog_tid; 3158 Adapter->watchdog_tid = 0; 3159 3160 mutex_exit(&Adapter->watchdog_lock); 3161 3162 if (tid != 0) 3163 (void) untimeout(tid); 3164 } 3165 3166 static void 3167 stop_link_timer(struct e1000g *Adapter) 3168 { 3169 timeout_id_t tid; 3170 3171 /* Disable the link timer */ 3172 mutex_enter(&Adapter->link_lock); 3173 3174 tid = Adapter->link_tid; 3175 Adapter->link_tid = 0; 3176 3177 mutex_exit(&Adapter->link_lock); 3178 3179 if (tid != 0) 3180 (void) untimeout(tid); 3181 } 3182 3183 static void 3184 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 3185 { 3186 timeout_id_t tid; 3187 3188 /* Disable the tx timer for 82547 chipset */ 3189 mutex_enter(&tx_ring->tx_lock); 3190 3191 tx_ring->timer_enable_82547 = B_FALSE; 3192 tid = tx_ring->timer_id_82547; 3193 tx_ring->timer_id_82547 = 0; 3194 3195 mutex_exit(&tx_ring->tx_lock); 3196 3197 if (tid != 0) 3198 (void) untimeout(tid); 3199 } 3200 3201 void 3202 e1000g_clear_interrupt(struct e1000g *Adapter) 3203 { 3204 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 3205 0xffffffff & ~E1000_IMS_RXSEQ); 3206 } 3207 3208 void 3209 e1000g_mask_interrupt(struct e1000g *Adapter) 3210 { 3211 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 3212 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 3213 3214 if (Adapter->tx_intr_enable) 3215 e1000g_mask_tx_interrupt(Adapter); 3216 } 3217 3218 void 3219 e1000g_clear_all_interrupts(struct e1000g *Adapter) 3220 { 3221 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 3222 } 3223 3224 void 3225 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 3226 { 3227 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 3228 } 3229 3230 void 3231 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 3232 { 3233 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 3234 } 3235 3236 static void 3237 e1000g_smartspeed(struct e1000g *Adapter) 3238 { 3239 struct e1000_hw *hw = &Adapter->shared; 3240 uint16_t phy_status; 3241 uint16_t phy_ctrl; 3242 3243 /* 3244 * If we're not T-or-T, or we're not autoneg'ing, or we're not 3245 * advertising 1000Full, we don't even use the workaround 3246 */ 3247 if ((hw->phy.type != e1000_phy_igp) || 3248 !hw->mac.autoneg || 3249 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 3250 return; 3251 3252 /* 3253 * True if this is the first call of this function or after every 3254 * 30 seconds of not having link 3255 */ 3256 if (Adapter->smartspeed == 0) { 3257 /* 3258 * If Master/Slave config fault is asserted twice, we 3259 * assume back-to-back 3260 */ 3261 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 3262 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3263 return; 3264 3265 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 3266 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3267 return; 3268 /* 3269 * We're assuming back-2-back because our status register 3270 * insists! there's a fault in the master/slave 3271 * relationship that was "negotiated" 3272 */ 3273 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 3274 /* 3275 * Is the phy configured for manual configuration of 3276 * master/slave? 3277 */ 3278 if (phy_ctrl & CR_1000T_MS_ENABLE) { 3279 /* 3280 * Yes. Then disable manual configuration (enable 3281 * auto configuration) of master/slave 3282 */ 3283 phy_ctrl &= ~CR_1000T_MS_ENABLE; 3284 e1000_write_phy_reg(hw, 3285 PHY_1000T_CTRL, phy_ctrl); 3286 /* 3287 * Effectively starting the clock 3288 */ 3289 Adapter->smartspeed++; 3290 /* 3291 * Restart autonegotiation 3292 */ 3293 if (!e1000_phy_setup_autoneg(hw) && 3294 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 3295 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 3296 MII_CR_RESTART_AUTO_NEG); 3297 e1000_write_phy_reg(hw, 3298 PHY_CONTROL, phy_ctrl); 3299 } 3300 } 3301 return; 3302 /* 3303 * Has 6 seconds transpired still without link? Remember, 3304 * you should reset the smartspeed counter once you obtain 3305 * link 3306 */ 3307 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 3308 /* 3309 * Yes. Remember, we did at the start determine that 3310 * there's a master/slave configuration fault, so we're 3311 * still assuming there's someone on the other end, but we 3312 * just haven't yet been able to talk to it. We then 3313 * re-enable auto configuration of master/slave to see if 3314 * we're running 2/3 pair cables. 3315 */ 3316 /* 3317 * If still no link, perhaps using 2/3 pair cable 3318 */ 3319 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 3320 phy_ctrl |= CR_1000T_MS_ENABLE; 3321 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 3322 /* 3323 * Restart autoneg with phy enabled for manual 3324 * configuration of master/slave 3325 */ 3326 if (!e1000_phy_setup_autoneg(hw) && 3327 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 3328 phy_ctrl |= 3329 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 3330 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 3331 } 3332 /* 3333 * Hopefully, there are no more faults and we've obtained 3334 * link as a result. 3335 */ 3336 } 3337 /* 3338 * Restart process after E1000_SMARTSPEED_MAX iterations (30 3339 * seconds) 3340 */ 3341 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 3342 Adapter->smartspeed = 0; 3343 } 3344 3345 static boolean_t 3346 is_valid_mac_addr(uint8_t *mac_addr) 3347 { 3348 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 3349 const uint8_t addr_test2[6] = 3350 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 3351 3352 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 3353 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 3354 return (B_FALSE); 3355 3356 return (B_TRUE); 3357 } 3358 3359 /* 3360 * e1000g_stall_check - check for tx stall 3361 * 3362 * This function checks if the adapter is stalled (in transmit). 3363 * 3364 * It is called each time the watchdog timeout is invoked. 3365 * If the transmit descriptor reclaim continuously fails, 3366 * the watchdog value will increment by 1. If the watchdog 3367 * value exceeds the threshold, the adapter is assumed to 3368 * have stalled and need to be reset. 3369 */ 3370 static boolean_t 3371 e1000g_stall_check(struct e1000g *Adapter) 3372 { 3373 e1000g_tx_ring_t *tx_ring; 3374 3375 tx_ring = Adapter->tx_ring; 3376 3377 if (Adapter->link_state != LINK_STATE_UP) 3378 return (B_FALSE); 3379 3380 if (tx_ring->recycle_fail > 0) 3381 tx_ring->stall_watchdog++; 3382 else 3383 tx_ring->stall_watchdog = 0; 3384 3385 if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) 3386 return (B_FALSE); 3387 3388 tx_ring->stall_watchdog = 0; 3389 tx_ring->recycle_fail = 0; 3390 3391 return (B_TRUE); 3392 } 3393 3394 #ifdef E1000G_DEBUG 3395 static enum ioc_reply 3396 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 3397 { 3398 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 3399 e1000g_peekpoke_t *ppd; 3400 uint64_t mem_va; 3401 uint64_t maxoff; 3402 boolean_t peek; 3403 3404 switch (iocp->ioc_cmd) { 3405 3406 case E1000G_IOC_REG_PEEK: 3407 peek = B_TRUE; 3408 break; 3409 3410 case E1000G_IOC_REG_POKE: 3411 peek = B_FALSE; 3412 break; 3413 3414 deault: 3415 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 3416 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 3417 iocp->ioc_cmd); 3418 return (IOC_INVAL); 3419 } 3420 3421 /* 3422 * Validate format of ioctl 3423 */ 3424 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 3425 return (IOC_INVAL); 3426 if (mp->b_cont == NULL) 3427 return (IOC_INVAL); 3428 3429 ppd = (e1000g_peekpoke_t *)mp->b_cont->b_rptr; 3430 3431 /* 3432 * Validate request parameters 3433 */ 3434 switch (ppd->pp_acc_space) { 3435 3436 default: 3437 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 3438 "e1000g_diag_ioctl: invalid access space 0x%X\n", 3439 ppd->pp_acc_space); 3440 return (IOC_INVAL); 3441 3442 case E1000G_PP_SPACE_REG: 3443 /* 3444 * Memory-mapped I/O space 3445 */ 3446 ASSERT(ppd->pp_acc_size == 4); 3447 if (ppd->pp_acc_size != 4) 3448 return (IOC_INVAL); 3449 3450 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 3451 return (IOC_INVAL); 3452 3453 mem_va = 0; 3454 maxoff = 0x10000; 3455 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 3456 break; 3457 3458 case E1000G_PP_SPACE_E1000G: 3459 /* 3460 * E1000g data structure! 3461 */ 3462 mem_va = (uintptr_t)e1000gp; 3463 maxoff = sizeof (struct e1000g); 3464 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 3465 break; 3466 3467 } 3468 3469 if (ppd->pp_acc_offset >= maxoff) 3470 return (IOC_INVAL); 3471 3472 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 3473 return (IOC_INVAL); 3474 3475 /* 3476 * All OK - go! 3477 */ 3478 ppd->pp_acc_offset += mem_va; 3479 (*ppfn)(e1000gp, ppd); 3480 return (peek ? IOC_REPLY : IOC_ACK); 3481 } 3482 3483 static void 3484 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3485 { 3486 ddi_acc_handle_t handle; 3487 uint32_t *regaddr; 3488 3489 handle = e1000gp->osdep.reg_handle; 3490 regaddr = 3491 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 3492 3493 ppd->pp_acc_data = ddi_get32(handle, regaddr); 3494 } 3495 3496 static void 3497 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3498 { 3499 ddi_acc_handle_t handle; 3500 uint32_t *regaddr; 3501 uint32_t value; 3502 3503 handle = e1000gp->osdep.reg_handle; 3504 regaddr = 3505 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 3506 value = (uint32_t)ppd->pp_acc_data; 3507 3508 ddi_put32(handle, regaddr, value); 3509 } 3510 3511 static void 3512 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3513 { 3514 uint64_t value; 3515 void *vaddr; 3516 3517 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 3518 3519 switch (ppd->pp_acc_size) { 3520 case 1: 3521 value = *(uint8_t *)vaddr; 3522 break; 3523 3524 case 2: 3525 value = *(uint16_t *)vaddr; 3526 break; 3527 3528 case 4: 3529 value = *(uint32_t *)vaddr; 3530 break; 3531 3532 case 8: 3533 value = *(uint64_t *)vaddr; 3534 break; 3535 } 3536 3537 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 3538 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 3539 (void *)e1000gp, (void *)ppd, value, vaddr); 3540 3541 ppd->pp_acc_data = value; 3542 } 3543 3544 static void 3545 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3546 { 3547 uint64_t value; 3548 void *vaddr; 3549 3550 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 3551 value = ppd->pp_acc_data; 3552 3553 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 3554 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 3555 (void *)e1000gp, (void *)ppd, value, vaddr); 3556 3557 switch (ppd->pp_acc_size) { 3558 case 1: 3559 *(uint8_t *)vaddr = (uint8_t)value; 3560 break; 3561 3562 case 2: 3563 *(uint16_t *)vaddr = (uint16_t)value; 3564 break; 3565 3566 case 4: 3567 *(uint32_t *)vaddr = (uint32_t)value; 3568 break; 3569 3570 case 8: 3571 *(uint64_t *)vaddr = (uint64_t)value; 3572 break; 3573 } 3574 } 3575 #endif 3576 3577 /* 3578 * Loopback Support 3579 */ 3580 static lb_property_t lb_normal = 3581 { normal, "normal", E1000G_LB_NONE }; 3582 static lb_property_t lb_external1000 = 3583 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 3584 static lb_property_t lb_external100 = 3585 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 3586 static lb_property_t lb_external10 = 3587 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 3588 static lb_property_t lb_phy = 3589 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 3590 3591 static enum ioc_reply 3592 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 3593 { 3594 lb_info_sz_t *lbsp; 3595 lb_property_t *lbpp; 3596 struct e1000_hw *hw; 3597 uint32_t *lbmp; 3598 uint32_t size; 3599 uint32_t value; 3600 3601 hw = &Adapter->shared; 3602 3603 if (mp->b_cont == NULL) 3604 return (IOC_INVAL); 3605 3606 switch (iocp->ioc_cmd) { 3607 default: 3608 return (IOC_INVAL); 3609 3610 case LB_GET_INFO_SIZE: 3611 size = sizeof (lb_info_sz_t); 3612 if (iocp->ioc_count != size) 3613 return (IOC_INVAL); 3614 3615 rw_enter(&Adapter->chip_lock, RW_WRITER); 3616 e1000g_get_phy_state(Adapter); 3617 3618 /* 3619 * Workaround for hardware faults. In order to get a stable 3620 * state of phy, we will wait for a specific interval and 3621 * try again. The time delay is an experiential value based 3622 * on our testing. 3623 */ 3624 msec_delay(100); 3625 e1000g_get_phy_state(Adapter); 3626 rw_exit(&Adapter->chip_lock); 3627 3628 value = sizeof (lb_normal); 3629 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3630 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3631 (hw->media_type == e1000_media_type_fiber) || 3632 (hw->media_type == e1000_media_type_internal_serdes)) { 3633 value += sizeof (lb_phy); 3634 switch (hw->mac.type) { 3635 case e1000_82571: 3636 case e1000_82572: 3637 value += sizeof (lb_external1000); 3638 break; 3639 } 3640 } 3641 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 3642 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 3643 value += sizeof (lb_external100); 3644 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 3645 value += sizeof (lb_external10); 3646 3647 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 3648 *lbsp = value; 3649 break; 3650 3651 case LB_GET_INFO: 3652 value = sizeof (lb_normal); 3653 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3654 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3655 (hw->media_type == e1000_media_type_fiber) || 3656 (hw->media_type == e1000_media_type_internal_serdes)) { 3657 value += sizeof (lb_phy); 3658 switch (hw->mac.type) { 3659 case e1000_82571: 3660 case e1000_82572: 3661 value += sizeof (lb_external1000); 3662 break; 3663 } 3664 } 3665 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 3666 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 3667 value += sizeof (lb_external100); 3668 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 3669 value += sizeof (lb_external10); 3670 3671 size = value; 3672 if (iocp->ioc_count != size) 3673 return (IOC_INVAL); 3674 3675 value = 0; 3676 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 3677 lbpp[value++] = lb_normal; 3678 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3679 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3680 (hw->media_type == e1000_media_type_fiber) || 3681 (hw->media_type == e1000_media_type_internal_serdes)) { 3682 lbpp[value++] = lb_phy; 3683 switch (hw->mac.type) { 3684 case e1000_82571: 3685 case e1000_82572: 3686 lbpp[value++] = lb_external1000; 3687 break; 3688 } 3689 } 3690 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 3691 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 3692 lbpp[value++] = lb_external100; 3693 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 3694 lbpp[value++] = lb_external10; 3695 break; 3696 3697 case LB_GET_MODE: 3698 size = sizeof (uint32_t); 3699 if (iocp->ioc_count != size) 3700 return (IOC_INVAL); 3701 3702 lbmp = (uint32_t *)mp->b_cont->b_rptr; 3703 *lbmp = Adapter->loopback_mode; 3704 break; 3705 3706 case LB_SET_MODE: 3707 size = 0; 3708 if (iocp->ioc_count != sizeof (uint32_t)) 3709 return (IOC_INVAL); 3710 3711 lbmp = (uint32_t *)mp->b_cont->b_rptr; 3712 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 3713 return (IOC_INVAL); 3714 break; 3715 } 3716 3717 iocp->ioc_count = size; 3718 iocp->ioc_error = 0; 3719 3720 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 3721 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3722 return (IOC_INVAL); 3723 } 3724 3725 return (IOC_REPLY); 3726 } 3727 3728 static boolean_t 3729 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 3730 { 3731 struct e1000_hw *hw; 3732 int i, times; 3733 boolean_t link_up; 3734 3735 if (mode == Adapter->loopback_mode) 3736 return (B_TRUE); 3737 3738 hw = &Adapter->shared; 3739 times = 0; 3740 3741 Adapter->loopback_mode = mode; 3742 3743 if (mode == E1000G_LB_NONE) { 3744 /* Reset the chip */ 3745 hw->phy.wait_for_link = B_TRUE; 3746 (void) e1000g_reset(Adapter); 3747 hw->phy.wait_for_link = B_FALSE; 3748 return (B_TRUE); 3749 } 3750 3751 again: 3752 3753 rw_enter(&Adapter->chip_lock, RW_WRITER); 3754 3755 switch (mode) { 3756 default: 3757 rw_exit(&Adapter->chip_lock); 3758 return (B_FALSE); 3759 3760 case E1000G_LB_EXTERNAL_1000: 3761 e1000g_set_external_loopback_1000(Adapter); 3762 break; 3763 3764 case E1000G_LB_EXTERNAL_100: 3765 e1000g_set_external_loopback_100(Adapter); 3766 break; 3767 3768 case E1000G_LB_EXTERNAL_10: 3769 e1000g_set_external_loopback_10(Adapter); 3770 break; 3771 3772 case E1000G_LB_INTERNAL_PHY: 3773 e1000g_set_internal_loopback(Adapter); 3774 break; 3775 } 3776 3777 times++; 3778 3779 rw_exit(&Adapter->chip_lock); 3780 3781 /* Wait for link up */ 3782 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 3783 msec_delay(100); 3784 3785 rw_enter(&Adapter->chip_lock, RW_WRITER); 3786 3787 link_up = e1000g_link_up(Adapter); 3788 3789 rw_exit(&Adapter->chip_lock); 3790 3791 if (!link_up) { 3792 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3793 "Failed to get the link up"); 3794 if (times < 2) { 3795 /* Reset the link */ 3796 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3797 "Reset the link ..."); 3798 (void) e1000g_reset(Adapter); 3799 goto again; 3800 } 3801 } 3802 3803 return (B_TRUE); 3804 } 3805 3806 /* 3807 * The following loopback settings are from Intel's technical 3808 * document - "How To Loopback". All the register settings and 3809 * time delay values are directly inherited from the document 3810 * without more explanations available. 3811 */ 3812 static void 3813 e1000g_set_internal_loopback(struct e1000g *Adapter) 3814 { 3815 struct e1000_hw *hw; 3816 uint32_t ctrl; 3817 uint32_t status; 3818 uint16_t phy_ctrl; 3819 uint32_t txcw; 3820 3821 hw = &Adapter->shared; 3822 3823 /* Disable Smart Power Down */ 3824 phy_spd_state(hw, B_FALSE); 3825 3826 e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 3827 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 3828 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 3829 3830 switch (hw->mac.type) { 3831 case e1000_82540: 3832 case e1000_82545: 3833 case e1000_82545_rev_3: 3834 case e1000_82546: 3835 case e1000_82546_rev_3: 3836 case e1000_82573: 3837 /* Auto-MDI/MDIX off */ 3838 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 3839 /* Reset PHY to update Auto-MDI/MDIX */ 3840 e1000_write_phy_reg(hw, PHY_CONTROL, 3841 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 3842 /* Reset PHY to auto-neg off and force 1000 */ 3843 e1000_write_phy_reg(hw, PHY_CONTROL, 3844 phy_ctrl | MII_CR_RESET); 3845 /* 3846 * Disable PHY receiver for 82540/545/546 and 82573 Family. 3847 * See comments above e1000g_set_internal_loopback() for the 3848 * background. 3849 */ 3850 e1000_write_phy_reg(hw, 29, 0x001F); 3851 e1000_write_phy_reg(hw, 30, 0x8FFC); 3852 e1000_write_phy_reg(hw, 29, 0x001A); 3853 e1000_write_phy_reg(hw, 30, 0x8FF0); 3854 break; 3855 } 3856 3857 /* Set loopback */ 3858 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 3859 3860 msec_delay(250); 3861 3862 /* Now set up the MAC to the same speed/duplex as the PHY. */ 3863 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3864 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3865 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3866 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3867 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 3868 E1000_CTRL_FD); /* Force Duplex to FULL */ 3869 3870 switch (hw->mac.type) { 3871 case e1000_82540: 3872 case e1000_82545: 3873 case e1000_82545_rev_3: 3874 case e1000_82546: 3875 case e1000_82546_rev_3: 3876 /* 3877 * For some serdes we'll need to commit the writes now 3878 * so that the status is updated on link 3879 */ 3880 if (hw->media_type == e1000_media_type_internal_serdes) { 3881 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3882 msec_delay(100); 3883 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3884 } 3885 3886 if (hw->media_type == e1000_media_type_copper) { 3887 /* Invert Loss of Signal */ 3888 ctrl |= E1000_CTRL_ILOS; 3889 } else { 3890 /* Set ILOS on fiber nic if half duplex is detected */ 3891 status = E1000_READ_REG(hw, E1000_STATUS); 3892 if ((status & E1000_STATUS_FD) == 0) 3893 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3894 } 3895 break; 3896 3897 case e1000_82571: 3898 case e1000_82572: 3899 /* 3900 * The fiber/SerDes versions of this adapter do not contain an 3901 * accessible PHY. Therefore, loopback beyond MAC must be done 3902 * using SerDes analog loopback. 3903 */ 3904 if (hw->media_type != e1000_media_type_copper) { 3905 status = E1000_READ_REG(hw, E1000_STATUS); 3906 /* Set ILOS on fiber nic if half duplex is detected */ 3907 if (((status & E1000_STATUS_LU) == 0) || 3908 ((status & E1000_STATUS_FD) == 0) || 3909 (hw->media_type == 3910 e1000_media_type_internal_serdes)) 3911 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3912 3913 /* Disable autoneg by setting bit 31 of TXCW to zero */ 3914 txcw = E1000_READ_REG(hw, E1000_TXCW); 3915 txcw &= ~((uint32_t)1 << 31); 3916 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 3917 3918 /* 3919 * Write 0x410 to Serdes Control register 3920 * to enable Serdes analog loopback 3921 */ 3922 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 3923 msec_delay(10); 3924 } 3925 break; 3926 3927 case e1000_82573: 3928 ctrl |= E1000_CTRL_ILOS; 3929 break; 3930 } 3931 3932 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3933 3934 } 3935 3936 static void 3937 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 3938 { 3939 struct e1000_hw *hw; 3940 uint32_t rctl; 3941 uint32_t ctrl_ext; 3942 uint32_t ctrl; 3943 uint32_t status; 3944 uint32_t txcw; 3945 3946 hw = &Adapter->shared; 3947 3948 /* Disable Smart Power Down */ 3949 phy_spd_state(hw, B_FALSE); 3950 3951 switch (hw->media_type) { 3952 case e1000_media_type_copper: 3953 /* Force link up (Must be done before the PHY writes) */ 3954 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3955 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 3956 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3957 3958 rctl = E1000_READ_REG(hw, E1000_RCTL); 3959 rctl |= (E1000_RCTL_EN | 3960 E1000_RCTL_SBP | 3961 E1000_RCTL_UPE | 3962 E1000_RCTL_MPE | 3963 E1000_RCTL_LPE | 3964 E1000_RCTL_BAM); /* 0x803E */ 3965 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3966 3967 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3968 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 3969 E1000_CTRL_EXT_SDP6_DATA | 3970 E1000_CTRL_EXT_SDP7_DATA | 3971 E1000_CTRL_EXT_SDP4_DIR | 3972 E1000_CTRL_EXT_SDP6_DIR | 3973 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 3974 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3975 3976 /* 3977 * This sequence tunes the PHY's SDP and no customer 3978 * settable values. For background, see comments above 3979 * e1000g_set_internal_loopback(). 3980 */ 3981 e1000_write_phy_reg(hw, 0x0, 0x140); 3982 msec_delay(10); 3983 e1000_write_phy_reg(hw, 0x9, 0x1A00); 3984 e1000_write_phy_reg(hw, 0x12, 0xC10); 3985 e1000_write_phy_reg(hw, 0x12, 0x1C10); 3986 e1000_write_phy_reg(hw, 0x1F37, 0x76); 3987 e1000_write_phy_reg(hw, 0x1F33, 0x1); 3988 e1000_write_phy_reg(hw, 0x1F33, 0x0); 3989 3990 e1000_write_phy_reg(hw, 0x1F35, 0x65); 3991 e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 3992 e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 3993 e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 3994 e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 3995 3996 msec_delay(50); 3997 break; 3998 case e1000_media_type_fiber: 3999 case e1000_media_type_internal_serdes: 4000 status = E1000_READ_REG(hw, E1000_STATUS); 4001 if (((status & E1000_STATUS_LU) == 0) || 4002 (hw->media_type == e1000_media_type_internal_serdes)) { 4003 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4004 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4005 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4006 } 4007 4008 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4009 txcw = E1000_READ_REG(hw, E1000_TXCW); 4010 txcw &= ~((uint32_t)1 << 31); 4011 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4012 4013 /* 4014 * Write 0x410 to Serdes Control register 4015 * to enable Serdes analog loopback 4016 */ 4017 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4018 msec_delay(10); 4019 break; 4020 default: 4021 break; 4022 } 4023 } 4024 4025 static void 4026 e1000g_set_external_loopback_100(struct e1000g *Adapter) 4027 { 4028 struct e1000_hw *hw; 4029 uint32_t ctrl; 4030 uint16_t phy_ctrl; 4031 4032 hw = &Adapter->shared; 4033 4034 /* Disable Smart Power Down */ 4035 phy_spd_state(hw, B_FALSE); 4036 4037 phy_ctrl = (MII_CR_FULL_DUPLEX | 4038 MII_CR_SPEED_100); 4039 4040 /* Force 100/FD, reset PHY */ 4041 e1000_write_phy_reg(hw, PHY_CONTROL, 4042 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 4043 msec_delay(10); 4044 4045 /* Force 100/FD */ 4046 e1000_write_phy_reg(hw, PHY_CONTROL, 4047 phy_ctrl); /* 0x2100 */ 4048 msec_delay(10); 4049 4050 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4051 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4052 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4053 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4054 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4055 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4056 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 4057 E1000_CTRL_FD); /* Force Duplex to FULL */ 4058 4059 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4060 } 4061 4062 static void 4063 e1000g_set_external_loopback_10(struct e1000g *Adapter) 4064 { 4065 struct e1000_hw *hw; 4066 uint32_t ctrl; 4067 uint16_t phy_ctrl; 4068 4069 hw = &Adapter->shared; 4070 4071 /* Disable Smart Power Down */ 4072 phy_spd_state(hw, B_FALSE); 4073 4074 phy_ctrl = (MII_CR_FULL_DUPLEX | 4075 MII_CR_SPEED_10); 4076 4077 /* Force 10/FD, reset PHY */ 4078 e1000_write_phy_reg(hw, PHY_CONTROL, 4079 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 4080 msec_delay(10); 4081 4082 /* Force 10/FD */ 4083 e1000_write_phy_reg(hw, PHY_CONTROL, 4084 phy_ctrl); /* 0x0100 */ 4085 msec_delay(10); 4086 4087 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4088 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4089 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4090 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4091 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4092 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4093 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 4094 E1000_CTRL_FD); /* Force Duplex to FULL */ 4095 4096 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4097 } 4098 4099 #ifdef __sparc 4100 static boolean_t 4101 e1000g_find_mac_address(struct e1000g *Adapter) 4102 { 4103 struct e1000_hw *hw = &Adapter->shared; 4104 uchar_t *bytes; 4105 struct ether_addr sysaddr; 4106 uint_t nelts; 4107 int err; 4108 boolean_t found = B_FALSE; 4109 4110 /* 4111 * The "vendor's factory-set address" may already have 4112 * been extracted from the chip, but if the property 4113 * "local-mac-address" is set we use that instead. 4114 * 4115 * We check whether it looks like an array of 6 4116 * bytes (which it should, if OBP set it). If we can't 4117 * make sense of it this way, we'll ignore it. 4118 */ 4119 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4120 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 4121 if (err == DDI_PROP_SUCCESS) { 4122 if (nelts == ETHERADDRL) { 4123 while (nelts--) 4124 hw->mac.addr[nelts] = bytes[nelts]; 4125 found = B_TRUE; 4126 } 4127 ddi_prop_free(bytes); 4128 } 4129 4130 /* 4131 * Look up the OBP property "local-mac-address?". If the user has set 4132 * 'local-mac-address? = false', use "the system address" instead. 4133 */ 4134 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 4135 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 4136 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 4137 if (localetheraddr(NULL, &sysaddr) != 0) { 4138 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 4139 found = B_TRUE; 4140 } 4141 } 4142 ddi_prop_free(bytes); 4143 } 4144 4145 /* 4146 * Finally(!), if there's a valid "mac-address" property (created 4147 * if we netbooted from this interface), we must use this instead 4148 * of any of the above to ensure that the NFS/install server doesn't 4149 * get confused by the address changing as Solaris takes over! 4150 */ 4151 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4152 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 4153 if (err == DDI_PROP_SUCCESS) { 4154 if (nelts == ETHERADDRL) { 4155 while (nelts--) 4156 hw->mac.addr[nelts] = bytes[nelts]; 4157 found = B_TRUE; 4158 } 4159 ddi_prop_free(bytes); 4160 } 4161 4162 if (found) { 4163 bcopy(hw->mac.addr, hw->mac.perm_addr, 4164 ETHERADDRL); 4165 } 4166 4167 return (found); 4168 } 4169 #endif 4170 4171 static int 4172 e1000g_add_intrs(struct e1000g *Adapter) 4173 { 4174 dev_info_t *devinfo; 4175 int intr_types; 4176 int rc; 4177 4178 devinfo = Adapter->dip; 4179 4180 /* Get supported interrupt types */ 4181 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 4182 4183 if (rc != DDI_SUCCESS) { 4184 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4185 "Get supported interrupt types failed: %d\n", rc); 4186 return (DDI_FAILURE); 4187 } 4188 4189 /* 4190 * Based on Intel Technical Advisory document (TA-160), there are some 4191 * cases where some older Intel PCI-X NICs may "advertise" to the OS 4192 * that it supports MSI, but in fact has problems. 4193 * So we should only enable MSI for PCI-E NICs and disable MSI for old 4194 * PCI/PCI-X NICs. 4195 */ 4196 if (Adapter->shared.mac.type < e1000_82571) 4197 Adapter->msi_enabled = B_FALSE; 4198 4199 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enabled) { 4200 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 4201 4202 if (rc != DDI_SUCCESS) { 4203 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4204 "Add MSI failed, trying Legacy interrupts\n"); 4205 } else { 4206 Adapter->intr_type = DDI_INTR_TYPE_MSI; 4207 } 4208 } 4209 4210 if ((Adapter->intr_type == 0) && 4211 (intr_types & DDI_INTR_TYPE_FIXED)) { 4212 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 4213 4214 if (rc != DDI_SUCCESS) { 4215 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4216 "Add Legacy interrupts failed\n"); 4217 return (DDI_FAILURE); 4218 } 4219 4220 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 4221 } 4222 4223 if (Adapter->intr_type == 0) { 4224 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4225 "No interrupts registered\n"); 4226 return (DDI_FAILURE); 4227 } 4228 4229 return (DDI_SUCCESS); 4230 } 4231 4232 /* 4233 * e1000g_intr_add() handles MSI/Legacy interrupts 4234 */ 4235 static int 4236 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 4237 { 4238 dev_info_t *devinfo; 4239 int count, avail, actual; 4240 int x, y, rc, inum = 0; 4241 int flag; 4242 ddi_intr_handler_t *intr_handler; 4243 4244 devinfo = Adapter->dip; 4245 4246 /* get number of interrupts */ 4247 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 4248 if ((rc != DDI_SUCCESS) || (count == 0)) { 4249 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4250 "Get interrupt number failed. Return: %d, count: %d\n", 4251 rc, count); 4252 return (DDI_FAILURE); 4253 } 4254 4255 /* get number of available interrupts */ 4256 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 4257 if ((rc != DDI_SUCCESS) || (avail == 0)) { 4258 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4259 "Get interrupt available number failed. " 4260 "Return: %d, available: %d\n", rc, avail); 4261 return (DDI_FAILURE); 4262 } 4263 4264 if (avail < count) { 4265 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4266 "Interrupts count: %d, available: %d\n", 4267 count, avail); 4268 } 4269 4270 /* Allocate an array of interrupt handles */ 4271 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 4272 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 4273 4274 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 4275 flag = DDI_INTR_ALLOC_NORMAL; 4276 4277 /* call ddi_intr_alloc() */ 4278 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 4279 count, &actual, flag); 4280 4281 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4282 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4283 "Allocate interrupts failed: %d\n", rc); 4284 4285 kmem_free(Adapter->htable, Adapter->intr_size); 4286 return (DDI_FAILURE); 4287 } 4288 4289 if (actual < count) { 4290 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4291 "Interrupts requested: %d, received: %d\n", 4292 count, actual); 4293 } 4294 4295 Adapter->intr_cnt = actual; 4296 4297 /* Get priority for first msi, assume remaining are all the same */ 4298 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 4299 4300 if (rc != DDI_SUCCESS) { 4301 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4302 "Get interrupt priority failed: %d\n", rc); 4303 4304 /* Free already allocated intr */ 4305 for (y = 0; y < actual; y++) 4306 (void) ddi_intr_free(Adapter->htable[y]); 4307 4308 kmem_free(Adapter->htable, Adapter->intr_size); 4309 return (DDI_FAILURE); 4310 } 4311 4312 /* 4313 * In Legacy Interrupt mode, for PCI-Express adapters, we should 4314 * use the interrupt service routine e1000g_intr_pciexpress() 4315 * to avoid interrupt stealing when sharing interrupt with other 4316 * devices. 4317 */ 4318 if (Adapter->shared.mac.type < e1000_82571) 4319 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 4320 else 4321 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 4322 4323 /* Call ddi_intr_add_handler() */ 4324 for (x = 0; x < actual; x++) { 4325 rc = ddi_intr_add_handler(Adapter->htable[x], 4326 intr_handler, (caddr_t)Adapter, NULL); 4327 4328 if (rc != DDI_SUCCESS) { 4329 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4330 "Add interrupt handler failed: %d\n", rc); 4331 4332 /* Remove already added handler */ 4333 for (y = 0; y < x; y++) 4334 (void) ddi_intr_remove_handler( 4335 Adapter->htable[y]); 4336 4337 /* Free already allocated intr */ 4338 for (y = 0; y < actual; y++) 4339 (void) ddi_intr_free(Adapter->htable[y]); 4340 4341 kmem_free(Adapter->htable, Adapter->intr_size); 4342 return (DDI_FAILURE); 4343 } 4344 } 4345 4346 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 4347 4348 if (rc != DDI_SUCCESS) { 4349 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4350 "Get interrupt cap failed: %d\n", rc); 4351 4352 /* Free already allocated intr */ 4353 for (y = 0; y < actual; y++) { 4354 (void) ddi_intr_remove_handler(Adapter->htable[y]); 4355 (void) ddi_intr_free(Adapter->htable[y]); 4356 } 4357 4358 kmem_free(Adapter->htable, Adapter->intr_size); 4359 return (DDI_FAILURE); 4360 } 4361 4362 return (DDI_SUCCESS); 4363 } 4364 4365 static int 4366 e1000g_rem_intrs(struct e1000g *Adapter) 4367 { 4368 int x; 4369 int rc; 4370 4371 for (x = 0; x < Adapter->intr_cnt; x++) { 4372 rc = ddi_intr_remove_handler(Adapter->htable[x]); 4373 if (rc != DDI_SUCCESS) { 4374 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4375 "Remove intr handler failed: %d\n", rc); 4376 return (DDI_FAILURE); 4377 } 4378 4379 rc = ddi_intr_free(Adapter->htable[x]); 4380 if (rc != DDI_SUCCESS) { 4381 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4382 "Free intr failed: %d\n", rc); 4383 return (DDI_FAILURE); 4384 } 4385 } 4386 4387 kmem_free(Adapter->htable, Adapter->intr_size); 4388 4389 return (DDI_SUCCESS); 4390 } 4391 4392 static int 4393 e1000g_enable_intrs(struct e1000g *Adapter) 4394 { 4395 int x; 4396 int rc; 4397 4398 /* Enable interrupts */ 4399 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 4400 /* Call ddi_intr_block_enable() for MSI */ 4401 rc = ddi_intr_block_enable(Adapter->htable, 4402 Adapter->intr_cnt); 4403 if (rc != DDI_SUCCESS) { 4404 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4405 "Enable block intr failed: %d\n", rc); 4406 return (DDI_FAILURE); 4407 } 4408 } else { 4409 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 4410 for (x = 0; x < Adapter->intr_cnt; x++) { 4411 rc = ddi_intr_enable(Adapter->htable[x]); 4412 if (rc != DDI_SUCCESS) { 4413 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4414 "Enable intr failed: %d\n", rc); 4415 return (DDI_FAILURE); 4416 } 4417 } 4418 } 4419 4420 return (DDI_SUCCESS); 4421 } 4422 4423 static int 4424 e1000g_disable_intrs(struct e1000g *Adapter) 4425 { 4426 int x; 4427 int rc; 4428 4429 /* Disable all interrupts */ 4430 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 4431 rc = ddi_intr_block_disable(Adapter->htable, 4432 Adapter->intr_cnt); 4433 if (rc != DDI_SUCCESS) { 4434 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4435 "Disable block intr failed: %d\n", rc); 4436 return (DDI_FAILURE); 4437 } 4438 } else { 4439 for (x = 0; x < Adapter->intr_cnt; x++) { 4440 rc = ddi_intr_disable(Adapter->htable[x]); 4441 if (rc != DDI_SUCCESS) { 4442 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4443 "Disable intr failed: %d\n", rc); 4444 return (DDI_FAILURE); 4445 } 4446 } 4447 } 4448 4449 return (DDI_SUCCESS); 4450 } 4451 4452 /* 4453 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 4454 */ 4455 static void 4456 e1000g_get_phy_state(struct e1000g *Adapter) 4457 { 4458 struct e1000_hw *hw = &Adapter->shared; 4459 4460 e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 4461 e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 4462 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 4463 e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 4464 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 4465 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 4466 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &Adapter->phy_1000t_status); 4467 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 4468 } 4469 4470 /* 4471 * FMA support 4472 */ 4473 4474 int 4475 e1000g_check_acc_handle(ddi_acc_handle_t handle) 4476 { 4477 ddi_fm_error_t de; 4478 4479 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 4480 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 4481 return (de.fme_status); 4482 } 4483 4484 int 4485 e1000g_check_dma_handle(ddi_dma_handle_t handle) 4486 { 4487 ddi_fm_error_t de; 4488 4489 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 4490 return (de.fme_status); 4491 } 4492 4493 /* 4494 * The IO fault service error handling callback function 4495 */ 4496 static int 4497 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 4498 { 4499 /* 4500 * as the driver can always deal with an error in any dma or 4501 * access handle, we can just return the fme_status value. 4502 */ 4503 pci_ereport_post(dip, err, NULL); 4504 return (err->fme_status); 4505 } 4506 4507 static void 4508 e1000g_fm_init(struct e1000g *Adapter) 4509 { 4510 ddi_iblock_cookie_t iblk; 4511 int fma_acc_flag, fma_dma_flag; 4512 4513 /* Only register with IO Fault Services if we have some capability */ 4514 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 4515 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 4516 fma_acc_flag = 1; 4517 } else { 4518 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 4519 fma_acc_flag = 0; 4520 } 4521 4522 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 4523 fma_dma_flag = 1; 4524 } else { 4525 fma_dma_flag = 0; 4526 } 4527 4528 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 4529 4530 if (Adapter->fm_capabilities) { 4531 4532 /* Register capabilities with IO Fault Services */ 4533 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 4534 4535 /* 4536 * Initialize pci ereport capabilities if ereport capable 4537 */ 4538 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 4539 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 4540 pci_ereport_setup(Adapter->dip); 4541 4542 /* 4543 * Register error callback if error callback capable 4544 */ 4545 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 4546 ddi_fm_handler_register(Adapter->dip, 4547 e1000g_fm_error_cb, (void*) Adapter); 4548 } 4549 } 4550 4551 static void 4552 e1000g_fm_fini(struct e1000g *Adapter) 4553 { 4554 /* Only unregister FMA capabilities if we registered some */ 4555 if (Adapter->fm_capabilities) { 4556 4557 /* 4558 * Release any resources allocated by pci_ereport_setup() 4559 */ 4560 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 4561 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 4562 pci_ereport_teardown(Adapter->dip); 4563 4564 /* 4565 * Un-register error callback if error callback capable 4566 */ 4567 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 4568 ddi_fm_handler_unregister(Adapter->dip); 4569 4570 /* Unregister from IO Fault Services */ 4571 ddi_fm_fini(Adapter->dip); 4572 } 4573 } 4574 4575 void 4576 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 4577 { 4578 uint64_t ena; 4579 char buf[FM_MAX_CLASS]; 4580 4581 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 4582 ena = fm_ena_generate(0, FM_ENA_FMT1); 4583 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 4584 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 4585 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 4586 } 4587 } 4588