1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet 5.2.13"; 48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 49 static char e1000g_version[] = "Driver Ver. 5.2.13"; 50 51 /* 52 * Proto types for DDI entry points 53 */ 54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 56 57 /* 58 * init and intr routines prototype 59 */ 60 static int e1000g_resume(dev_info_t *); 61 static int e1000g_suspend(dev_info_t *); 62 static uint_t e1000g_intr_pciexpress(caddr_t); 63 static uint_t e1000g_intr(caddr_t); 64 static void e1000g_intr_work(struct e1000g *, uint32_t); 65 #pragma inline(e1000g_intr_work) 66 static uint32_t e1000g_get_itr(uint32_t, uint32_t, uint32_t); 67 #pragma inline(e1000g_get_itr) 68 static int e1000g_init(struct e1000g *); 69 static int e1000g_start(struct e1000g *, boolean_t); 70 static void e1000g_stop(struct e1000g *, boolean_t); 71 static int e1000g_m_start(void *); 72 static void e1000g_m_stop(void *); 73 static int e1000g_m_promisc(void *, boolean_t); 74 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 75 static int e1000g_m_unicst(void *, const uint8_t *); 76 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 77 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 78 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 79 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 80 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 81 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 82 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 83 uint_t, const void *); 84 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 85 uint_t, uint_t, void *); 86 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 87 const void *); 88 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 89 uint_t, void *); 90 static void e1000g_init_locks(struct e1000g *); 91 static void e1000g_destroy_locks(struct e1000g *); 92 static int e1000g_identify_hardware(struct e1000g *); 93 static int e1000g_regs_map(struct e1000g *); 94 static int e1000g_set_driver_params(struct e1000g *); 95 static void e1000g_set_bufsize(struct e1000g *); 96 static int e1000g_register_mac(struct e1000g *); 97 static boolean_t e1000g_rx_drain(struct e1000g *); 98 static boolean_t e1000g_tx_drain(struct e1000g *); 99 static void e1000g_init_unicst(struct e1000g *); 100 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 101 102 /* 103 * Local routines 104 */ 105 static void e1000g_tx_clean(struct e1000g *); 106 static void e1000g_rx_clean(struct e1000g *); 107 static void e1000g_link_timer(void *); 108 static void e1000g_local_timer(void *); 109 static boolean_t e1000g_link_check(struct e1000g *); 110 static boolean_t e1000g_stall_check(struct e1000g *); 111 static void e1000g_smartspeed(struct e1000g *); 112 static void e1000g_get_conf(struct e1000g *); 113 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 114 static void enable_watchdog_timer(struct e1000g *); 115 static void disable_watchdog_timer(struct e1000g *); 116 static void start_watchdog_timer(struct e1000g *); 117 static void restart_watchdog_timer(struct e1000g *); 118 static void stop_watchdog_timer(struct e1000g *); 119 static void stop_link_timer(struct e1000g *); 120 static void stop_82547_timer(e1000g_tx_ring_t *); 121 static void e1000g_force_speed_duplex(struct e1000g *); 122 static void e1000g_get_max_frame_size(struct e1000g *); 123 static boolean_t is_valid_mac_addr(uint8_t *); 124 static void e1000g_unattach(dev_info_t *, struct e1000g *); 125 #ifdef E1000G_DEBUG 126 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 127 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 128 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 129 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 130 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 131 struct iocblk *, mblk_t *); 132 #endif 133 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 134 struct iocblk *, mblk_t *); 135 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 136 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 137 static void e1000g_set_internal_loopback(struct e1000g *); 138 static void e1000g_set_external_loopback_1000(struct e1000g *); 139 static void e1000g_set_external_loopback_100(struct e1000g *); 140 static void e1000g_set_external_loopback_10(struct e1000g *); 141 static int e1000g_add_intrs(struct e1000g *); 142 static int e1000g_intr_add(struct e1000g *, int); 143 static int e1000g_rem_intrs(struct e1000g *); 144 static int e1000g_enable_intrs(struct e1000g *); 145 static int e1000g_disable_intrs(struct e1000g *); 146 static boolean_t e1000g_link_up(struct e1000g *); 147 #ifdef __sparc 148 static boolean_t e1000g_find_mac_address(struct e1000g *); 149 #endif 150 static void e1000g_get_phy_state(struct e1000g *); 151 static void e1000g_free_priv_devi_node(struct e1000g *, boolean_t); 152 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 153 const void *impl_data); 154 static void e1000g_fm_init(struct e1000g *Adapter); 155 static void e1000g_fm_fini(struct e1000g *Adapter); 156 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 157 static void e1000g_param_sync(struct e1000g *); 158 static void e1000g_get_driver_control(struct e1000_hw *); 159 static void e1000g_release_driver_control(struct e1000_hw *); 160 161 mac_priv_prop_t e1000g_priv_props[] = { 162 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 163 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 164 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 165 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 166 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 167 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 168 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 169 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 170 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 171 {"_intr_adaptive", MAC_PROP_PERM_RW}, 172 {"_tx_recycle_thresh", MAC_PROP_PERM_RW}, 173 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 174 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 175 {"_tx_recycle_num", MAC_PROP_PERM_RW} 176 }; 177 #define E1000G_MAX_PRIV_PROPS \ 178 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 179 180 181 static struct cb_ops cb_ws_ops = { 182 nulldev, /* cb_open */ 183 nulldev, /* cb_close */ 184 nodev, /* cb_strategy */ 185 nodev, /* cb_print */ 186 nodev, /* cb_dump */ 187 nodev, /* cb_read */ 188 nodev, /* cb_write */ 189 nodev, /* cb_ioctl */ 190 nodev, /* cb_devmap */ 191 nodev, /* cb_mmap */ 192 nodev, /* cb_segmap */ 193 nochpoll, /* cb_chpoll */ 194 ddi_prop_op, /* cb_prop_op */ 195 NULL, /* cb_stream */ 196 D_MP | D_HOTPLUG, /* cb_flag */ 197 CB_REV, /* cb_rev */ 198 nodev, /* cb_aread */ 199 nodev /* cb_awrite */ 200 }; 201 202 static struct dev_ops ws_ops = { 203 DEVO_REV, /* devo_rev */ 204 0, /* devo_refcnt */ 205 NULL, /* devo_getinfo */ 206 nulldev, /* devo_identify */ 207 nulldev, /* devo_probe */ 208 e1000g_attach, /* devo_attach */ 209 e1000g_detach, /* devo_detach */ 210 nodev, /* devo_reset */ 211 &cb_ws_ops, /* devo_cb_ops */ 212 NULL, /* devo_bus_ops */ 213 ddi_power /* devo_power */ 214 }; 215 216 static struct modldrv modldrv = { 217 &mod_driverops, /* Type of module. This one is a driver */ 218 ident, /* Discription string */ 219 &ws_ops, /* driver ops */ 220 }; 221 222 static struct modlinkage modlinkage = { 223 MODREV_1, &modldrv, NULL 224 }; 225 226 /* Access attributes for register mapping */ 227 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 228 DDI_DEVICE_ATTR_V0, 229 DDI_STRUCTURE_LE_ACC, 230 DDI_STRICTORDER_ACC, 231 DDI_FLAGERR_ACC 232 }; 233 234 #define E1000G_M_CALLBACK_FLAGS \ 235 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 236 237 static mac_callbacks_t e1000g_m_callbacks = { 238 E1000G_M_CALLBACK_FLAGS, 239 e1000g_m_stat, 240 e1000g_m_start, 241 e1000g_m_stop, 242 e1000g_m_promisc, 243 e1000g_m_multicst, 244 e1000g_m_unicst, 245 e1000g_m_tx, 246 NULL, 247 e1000g_m_ioctl, 248 e1000g_m_getcapab, 249 NULL, 250 NULL, 251 e1000g_m_setprop, 252 e1000g_m_getprop 253 }; 254 255 /* 256 * Global variables 257 */ 258 uint32_t e1000g_mblks_pending = 0; 259 /* 260 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 261 * Here we maintain a private dev_info list if e1000g_force_detach is 262 * enabled. If we force the driver to detach while there are still some 263 * rx buffers retained in the upper layer, we have to keep a copy of the 264 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 265 * structure will be freed after the driver is detached. However when we 266 * finally free those rx buffers released by the upper layer, we need to 267 * refer to the dev_info to free the dma buffers. So we save a copy of 268 * the dev_info for this purpose. On x86 platform, we assume this copy 269 * of dev_info is always valid, but on SPARC platform, it could be invalid 270 * after the system board level DR operation. For this reason, the global 271 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 272 */ 273 #ifdef __sparc 274 boolean_t e1000g_force_detach = B_FALSE; 275 #else 276 boolean_t e1000g_force_detach = B_TRUE; 277 #endif 278 private_devi_list_t *e1000g_private_devi_list = NULL; 279 280 /* 281 * The rwlock is defined to protect the whole processing of rx recycling 282 * and the rx packets release in detach processing to make them mutually 283 * exclusive. 284 * The rx recycling processes different rx packets in different threads, 285 * so it will be protected with RW_READER and it won't block any other rx 286 * recycling threads. 287 * While the detach processing will be protected with RW_WRITER to make 288 * it mutually exclusive with the rx recycling. 289 */ 290 krwlock_t e1000g_rx_detach_lock; 291 /* 292 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 293 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 294 * If there are many e1000g instances, the system may run out of DVMA 295 * resources during the initialization of the instances, then the flag will 296 * be changed to "USE_DMA". Because different e1000g instances are initialized 297 * in parallel, we need to use this lock to protect the flag. 298 */ 299 krwlock_t e1000g_dma_type_lock; 300 301 /* 302 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 303 * Based on the information from Intel, the 82546 chipset has some hardware 304 * problem. When one port is being reset and the other port is trying to 305 * access the eeprom, it could cause system hang or panic. To workaround this 306 * hardware problem, we use a global mutex to prevent such operations from 307 * happening simultaneously on different instances. This workaround is applied 308 * to all the devices supported by this driver. 309 */ 310 kmutex_t e1000g_nvm_lock; 311 312 /* 313 * Loadable module configuration entry points for the driver 314 */ 315 316 /* 317 * _init - module initialization 318 */ 319 int 320 _init(void) 321 { 322 int status; 323 324 mac_init_ops(&ws_ops, WSNAME); 325 status = mod_install(&modlinkage); 326 if (status != DDI_SUCCESS) 327 mac_fini_ops(&ws_ops); 328 else { 329 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 330 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 331 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 332 } 333 334 return (status); 335 } 336 337 /* 338 * _fini - module finalization 339 */ 340 int 341 _fini(void) 342 { 343 int status; 344 345 rw_enter(&e1000g_rx_detach_lock, RW_READER); 346 if (e1000g_mblks_pending != 0) { 347 rw_exit(&e1000g_rx_detach_lock); 348 return (EBUSY); 349 } 350 rw_exit(&e1000g_rx_detach_lock); 351 352 status = mod_remove(&modlinkage); 353 if (status == DDI_SUCCESS) { 354 mac_fini_ops(&ws_ops); 355 356 if (e1000g_force_detach) { 357 private_devi_list_t *devi_node; 358 359 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 360 while (e1000g_private_devi_list != NULL) { 361 devi_node = e1000g_private_devi_list; 362 e1000g_private_devi_list = 363 e1000g_private_devi_list->next; 364 365 kmem_free(devi_node->priv_dip, 366 sizeof (struct dev_info)); 367 kmem_free(devi_node, 368 sizeof (private_devi_list_t)); 369 } 370 rw_exit(&e1000g_rx_detach_lock); 371 } 372 373 rw_destroy(&e1000g_rx_detach_lock); 374 rw_destroy(&e1000g_dma_type_lock); 375 mutex_destroy(&e1000g_nvm_lock); 376 } 377 378 return (status); 379 } 380 381 /* 382 * _info - module information 383 */ 384 int 385 _info(struct modinfo *modinfop) 386 { 387 return (mod_info(&modlinkage, modinfop)); 388 } 389 390 /* 391 * e1000g_attach - driver attach 392 * 393 * This function is the device-specific initialization entry 394 * point. This entry point is required and must be written. 395 * The DDI_ATTACH command must be provided in the attach entry 396 * point. When attach() is called with cmd set to DDI_ATTACH, 397 * all normal kernel services (such as kmem_alloc(9F)) are 398 * available for use by the driver. 399 * 400 * The attach() function will be called once for each instance 401 * of the device on the system with cmd set to DDI_ATTACH. 402 * Until attach() succeeds, the only driver entry points which 403 * may be called are open(9E) and getinfo(9E). 404 */ 405 static int 406 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 407 { 408 struct e1000g *Adapter; 409 struct e1000_hw *hw; 410 struct e1000g_osdep *osdep; 411 int instance; 412 413 switch (cmd) { 414 default: 415 e1000g_log(NULL, CE_WARN, 416 "Unsupported command send to e1000g_attach... "); 417 return (DDI_FAILURE); 418 419 case DDI_RESUME: 420 return (e1000g_resume(devinfo)); 421 422 case DDI_ATTACH: 423 break; 424 } 425 426 /* 427 * get device instance number 428 */ 429 instance = ddi_get_instance(devinfo); 430 431 /* 432 * Allocate soft data structure 433 */ 434 Adapter = 435 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 436 437 Adapter->dip = devinfo; 438 Adapter->instance = instance; 439 Adapter->tx_ring->adapter = Adapter; 440 Adapter->rx_ring->adapter = Adapter; 441 442 hw = &Adapter->shared; 443 osdep = &Adapter->osdep; 444 hw->back = osdep; 445 osdep->adapter = Adapter; 446 447 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 448 449 /* 450 * Initialize for fma support 451 */ 452 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 453 0, 0x0f, 454 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 455 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 456 e1000g_fm_init(Adapter); 457 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 458 459 /* 460 * PCI Configure 461 */ 462 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 463 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 464 goto attach_fail; 465 } 466 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 467 468 /* 469 * Setup hardware 470 */ 471 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 472 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 473 goto attach_fail; 474 } 475 476 /* 477 * Map in the device registers. 478 */ 479 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 480 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 481 goto attach_fail; 482 } 483 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 484 485 /* 486 * Initialize driver parameters 487 */ 488 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 489 goto attach_fail; 490 } 491 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 492 493 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 494 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 495 goto attach_fail; 496 } 497 498 /* 499 * Initialize interrupts 500 */ 501 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 502 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 503 goto attach_fail; 504 } 505 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 506 507 /* 508 * Initialize mutex's for this device. 509 * Do this before enabling the interrupt handler and 510 * register the softint to avoid the condition where 511 * interrupt handler can try using uninitialized mutex 512 */ 513 e1000g_init_locks(Adapter); 514 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 515 516 /* 517 * Initialize Driver Counters 518 */ 519 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 520 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 521 goto attach_fail; 522 } 523 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 524 525 /* 526 * Initialize chip hardware and software structures 527 */ 528 if (e1000g_init(Adapter) != DDI_SUCCESS) { 529 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 530 goto attach_fail; 531 } 532 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 533 534 /* 535 * Register the driver to the MAC 536 */ 537 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 538 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 539 goto attach_fail; 540 } 541 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 542 543 /* 544 * Now that mutex locks are initialized, and the chip is also 545 * initialized, enable interrupts. 546 */ 547 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 548 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 549 goto attach_fail; 550 } 551 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 552 553 /* 554 * If e1000g_force_detach is enabled, in global private dip list, 555 * we will create a new entry, which maintains the priv_dip for DR 556 * supports after driver detached. 557 */ 558 if (e1000g_force_detach) { 559 private_devi_list_t *devi_node; 560 561 Adapter->priv_dip = 562 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 563 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 564 sizeof (struct dev_info)); 565 566 devi_node = 567 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 568 569 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 570 devi_node->priv_dip = Adapter->priv_dip; 571 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 572 devi_node->next = e1000g_private_devi_list; 573 e1000g_private_devi_list = devi_node; 574 rw_exit(&e1000g_rx_detach_lock); 575 } 576 577 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 578 579 return (DDI_SUCCESS); 580 581 attach_fail: 582 e1000g_unattach(devinfo, Adapter); 583 return (DDI_FAILURE); 584 } 585 586 static int 587 e1000g_register_mac(struct e1000g *Adapter) 588 { 589 struct e1000_hw *hw = &Adapter->shared; 590 mac_register_t *mac; 591 int err; 592 593 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 594 return (DDI_FAILURE); 595 596 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 597 mac->m_driver = Adapter; 598 mac->m_dip = Adapter->dip; 599 mac->m_src_addr = hw->mac.addr; 600 mac->m_callbacks = &e1000g_m_callbacks; 601 mac->m_min_sdu = 0; 602 mac->m_max_sdu = Adapter->default_mtu; 603 mac->m_margin = VLAN_TAGSZ; 604 mac->m_priv_props = e1000g_priv_props; 605 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 606 607 err = mac_register(mac, &Adapter->mh); 608 mac_free(mac); 609 610 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 611 } 612 613 static int 614 e1000g_identify_hardware(struct e1000g *Adapter) 615 { 616 struct e1000_hw *hw = &Adapter->shared; 617 struct e1000g_osdep *osdep = &Adapter->osdep; 618 619 /* Get the device id */ 620 hw->vendor_id = 621 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 622 hw->device_id = 623 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 624 hw->revision_id = 625 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 626 hw->subsystem_device_id = 627 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 628 hw->subsystem_vendor_id = 629 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 630 631 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 632 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 633 "MAC type could not be set properly."); 634 return (DDI_FAILURE); 635 } 636 637 return (DDI_SUCCESS); 638 } 639 640 static int 641 e1000g_regs_map(struct e1000g *Adapter) 642 { 643 dev_info_t *devinfo = Adapter->dip; 644 struct e1000_hw *hw = &Adapter->shared; 645 struct e1000g_osdep *osdep = &Adapter->osdep; 646 off_t mem_size; 647 648 /* Get size of adapter register memory */ 649 if (ddi_dev_regsize(devinfo, ADAPTER_REG_SET, &mem_size) != 650 DDI_SUCCESS) { 651 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 652 "ddi_dev_regsize for registers failed"); 653 return (DDI_FAILURE); 654 } 655 656 /* Map adapter register memory */ 657 if ((ddi_regs_map_setup(devinfo, ADAPTER_REG_SET, 658 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 659 &osdep->reg_handle)) != DDI_SUCCESS) { 660 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 661 "ddi_regs_map_setup for registers failed"); 662 goto regs_map_fail; 663 } 664 665 /* ICH needs to map flash memory */ 666 if (hw->mac.type == e1000_ich8lan || 667 hw->mac.type == e1000_ich9lan || 668 hw->mac.type == e1000_ich10lan) { 669 /* get flash size */ 670 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 671 &mem_size) != DDI_SUCCESS) { 672 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 673 "ddi_dev_regsize for ICH flash failed"); 674 goto regs_map_fail; 675 } 676 677 /* map flash in */ 678 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 679 (caddr_t *)&hw->flash_address, 0, 680 mem_size, &e1000g_regs_acc_attr, 681 &osdep->ich_flash_handle) != DDI_SUCCESS) { 682 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 683 "ddi_regs_map_setup for ICH flash failed"); 684 goto regs_map_fail; 685 } 686 } 687 688 return (DDI_SUCCESS); 689 690 regs_map_fail: 691 if (osdep->reg_handle != NULL) 692 ddi_regs_map_free(&osdep->reg_handle); 693 694 return (DDI_FAILURE); 695 } 696 697 static int 698 e1000g_set_driver_params(struct e1000g *Adapter) 699 { 700 struct e1000_hw *hw; 701 uint32_t mem_bar, io_bar, bar64; 702 703 hw = &Adapter->shared; 704 705 /* Set MAC type and initialize hardware functions */ 706 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 707 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 708 "Could not setup hardware functions"); 709 return (DDI_FAILURE); 710 } 711 712 /* Get bus information */ 713 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 714 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 715 "Could not get bus information"); 716 return (DDI_FAILURE); 717 } 718 719 /* get mem_base addr */ 720 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 721 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 722 723 /* get io_base addr */ 724 if (hw->mac.type >= e1000_82544) { 725 if (bar64) { 726 /* IO BAR is different for 64 bit BAR mode */ 727 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 728 PCI_CONF_BASE4); 729 } else { 730 /* normal 32-bit BAR mode */ 731 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 732 PCI_CONF_BASE2); 733 } 734 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 735 } else { 736 /* no I/O access for adapters prior to 82544 */ 737 hw->io_base = 0x0; 738 } 739 740 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 741 742 hw->mac.autoneg_failed = B_TRUE; 743 744 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 745 hw->phy.autoneg_wait_to_complete = B_FALSE; 746 747 /* Adaptive IFS related changes */ 748 hw->mac.adaptive_ifs = B_TRUE; 749 750 /* Enable phy init script for IGP phy of 82541/82547 */ 751 if ((hw->mac.type == e1000_82547) || 752 (hw->mac.type == e1000_82541) || 753 (hw->mac.type == e1000_82547_rev_2) || 754 (hw->mac.type == e1000_82541_rev_2)) 755 e1000_init_script_state_82541(hw, B_TRUE); 756 757 /* Enable the TTL workaround for 82541/82547 */ 758 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 759 760 #ifdef __sparc 761 Adapter->strip_crc = B_TRUE; 762 #else 763 Adapter->strip_crc = B_FALSE; 764 #endif 765 766 /* Get conf file properties */ 767 e1000g_get_conf(Adapter); 768 769 /* Get speed/duplex settings in conf file */ 770 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 771 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 772 e1000g_force_speed_duplex(Adapter); 773 774 /* Get Jumbo Frames settings in conf file */ 775 e1000g_get_max_frame_size(Adapter); 776 777 /* Set Rx/Tx buffer size */ 778 e1000g_set_bufsize(Adapter); 779 780 /* Master Latency Timer */ 781 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 782 783 /* copper options */ 784 if (hw->phy.media_type == e1000_media_type_copper) { 785 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 786 hw->phy.disable_polarity_correction = B_FALSE; 787 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 788 } 789 790 /* The initial link state should be "unknown" */ 791 Adapter->link_state = LINK_STATE_UNKNOWN; 792 793 /* Initialize rx parameters */ 794 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 795 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 796 797 /* Initialize tx parameters */ 798 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 799 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 800 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 801 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 802 803 /* Initialize rx parameters */ 804 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 805 806 return (DDI_SUCCESS); 807 } 808 809 static void 810 e1000g_set_bufsize(struct e1000g *Adapter) 811 { 812 struct e1000_mac_info *mac = &Adapter->shared.mac; 813 uint64_t rx_size; 814 uint64_t tx_size; 815 816 #ifdef __sparc 817 dev_info_t *devinfo = Adapter->dip; 818 ulong_t iommu_pagesize; 819 820 /* Get the system page size */ 821 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 822 iommu_pagesize = dvma_pagesize(devinfo); 823 if (iommu_pagesize != 0) { 824 if (Adapter->sys_page_sz == iommu_pagesize) { 825 if (iommu_pagesize > 0x4000) 826 Adapter->sys_page_sz = 0x4000; 827 } else { 828 if (Adapter->sys_page_sz > iommu_pagesize) 829 Adapter->sys_page_sz = iommu_pagesize; 830 } 831 } 832 if (Adapter->lso_enable) { 833 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 834 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 835 } else { 836 Adapter->dvma_page_num = Adapter->max_frame_size / 837 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 838 } 839 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 840 #endif 841 842 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 843 844 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 845 if ((rx_size > FRAME_SIZE_UPTO_2K) && (rx_size <= FRAME_SIZE_UPTO_4K)) 846 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 847 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 848 (rx_size <= FRAME_SIZE_UPTO_8K)) 849 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 850 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 851 (rx_size <= FRAME_SIZE_UPTO_16K)) 852 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 853 else 854 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 855 856 tx_size = Adapter->max_frame_size; 857 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 858 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 859 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 860 (tx_size <= FRAME_SIZE_UPTO_8K)) 861 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 862 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 863 (tx_size <= FRAME_SIZE_UPTO_16K)) 864 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 865 else 866 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 867 868 /* 869 * For Wiseman adapters we have an requirement of having receive 870 * buffers aligned at 256 byte boundary. Since Livengood does not 871 * require this and forcing it for all hardwares will have 872 * performance implications, I am making it applicable only for 873 * Wiseman and for Jumbo frames enabled mode as rest of the time, 874 * it is okay to have normal frames...but it does involve a 875 * potential risk where we may loose data if buffer is not 876 * aligned...so all wiseman boards to have 256 byte aligned 877 * buffers 878 */ 879 if (mac->type < e1000_82543) 880 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 881 else 882 Adapter->rx_buf_align = 1; 883 } 884 885 /* 886 * e1000g_detach - driver detach 887 * 888 * The detach() function is the complement of the attach routine. 889 * If cmd is set to DDI_DETACH, detach() is used to remove the 890 * state associated with a given instance of a device node 891 * prior to the removal of that instance from the system. 892 * 893 * The detach() function will be called once for each instance 894 * of the device for which there has been a successful attach() 895 * once there are no longer any opens on the device. 896 * 897 * Interrupts routine are disabled, All memory allocated by this 898 * driver are freed. 899 */ 900 static int 901 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 902 { 903 struct e1000g *Adapter; 904 boolean_t rx_drain; 905 906 switch (cmd) { 907 default: 908 return (DDI_FAILURE); 909 910 case DDI_SUSPEND: 911 return (e1000g_suspend(devinfo)); 912 913 case DDI_DETACH: 914 break; 915 } 916 917 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 918 if (Adapter == NULL) 919 return (DDI_FAILURE); 920 921 if (mac_unregister(Adapter->mh) != 0) { 922 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 923 return (DDI_FAILURE); 924 } 925 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 926 927 928 if (Adapter->chip_state != E1000G_STOP) 929 e1000g_stop(Adapter, B_TRUE); 930 931 rx_drain = e1000g_rx_drain(Adapter); 932 933 /* 934 * If e1000g_force_detach is enabled, driver detach is safe. 935 * We will let e1000g_free_priv_devi_node routine determine 936 * whether we need to free the priv_dip entry for current 937 * driver instance. 938 */ 939 if (e1000g_force_detach) { 940 e1000g_free_priv_devi_node(Adapter, rx_drain); 941 } else { 942 if (!rx_drain) 943 return (DDI_FAILURE); 944 } 945 946 e1000g_unattach(devinfo, Adapter); 947 948 return (DDI_SUCCESS); 949 } 950 951 /* 952 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 953 * 954 * If free_flag is true, that indicates the upper layer is not holding 955 * the rx buffers, we could free the priv_dip entry safely. 956 * 957 * Otherwise, we have to keep this entry even after driver detached, 958 * and we also need to mark this entry with E1000G_PRIV_DEVI_DETACH flag, 959 * so that driver could free it while all of rx buffers are returned 960 * by upper layer later. 961 */ 962 static void 963 e1000g_free_priv_devi_node(struct e1000g *Adapter, boolean_t free_flag) 964 { 965 private_devi_list_t *devi_node, *devi_del; 966 967 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 968 ASSERT(e1000g_private_devi_list != NULL); 969 ASSERT(Adapter->priv_dip != NULL); 970 971 devi_node = e1000g_private_devi_list; 972 if (devi_node->priv_dip == Adapter->priv_dip) { 973 if (free_flag) { 974 e1000g_private_devi_list = 975 devi_node->next; 976 kmem_free(devi_node->priv_dip, 977 sizeof (struct dev_info)); 978 kmem_free(devi_node, 979 sizeof (private_devi_list_t)); 980 } else { 981 ASSERT(e1000g_mblks_pending != 0); 982 devi_node->flag = 983 E1000G_PRIV_DEVI_DETACH; 984 } 985 rw_exit(&e1000g_rx_detach_lock); 986 return; 987 } 988 989 devi_node = e1000g_private_devi_list; 990 while (devi_node->next != NULL) { 991 if (devi_node->next->priv_dip == Adapter->priv_dip) { 992 if (free_flag) { 993 devi_del = devi_node->next; 994 devi_node->next = devi_del->next; 995 kmem_free(devi_del->priv_dip, 996 sizeof (struct dev_info)); 997 kmem_free(devi_del, 998 sizeof (private_devi_list_t)); 999 } else { 1000 ASSERT(e1000g_mblks_pending != 0); 1001 devi_node->next->flag = 1002 E1000G_PRIV_DEVI_DETACH; 1003 } 1004 break; 1005 } 1006 devi_node = devi_node->next; 1007 } 1008 rw_exit(&e1000g_rx_detach_lock); 1009 } 1010 1011 static void 1012 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1013 { 1014 int result; 1015 1016 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1017 (void) e1000g_disable_intrs(Adapter); 1018 } 1019 1020 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1021 (void) mac_unregister(Adapter->mh); 1022 } 1023 1024 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1025 (void) e1000g_rem_intrs(Adapter); 1026 } 1027 1028 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1029 (void) ddi_prop_remove_all(devinfo); 1030 } 1031 1032 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1033 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1034 } 1035 1036 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1037 stop_link_timer(Adapter); 1038 1039 mutex_enter(&e1000g_nvm_lock); 1040 result = e1000_reset_hw(&Adapter->shared); 1041 mutex_exit(&e1000g_nvm_lock); 1042 1043 if (result != E1000_SUCCESS) { 1044 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1045 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1046 } 1047 } 1048 1049 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1050 if (Adapter->osdep.reg_handle != NULL) 1051 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1052 if (Adapter->osdep.ich_flash_handle != NULL) 1053 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1054 } 1055 1056 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1057 if (Adapter->osdep.cfg_handle != NULL) 1058 pci_config_teardown(&Adapter->osdep.cfg_handle); 1059 } 1060 1061 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1062 e1000g_destroy_locks(Adapter); 1063 } 1064 1065 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1066 e1000g_fm_fini(Adapter); 1067 } 1068 1069 e1000_remove_device(&Adapter->shared); 1070 1071 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1072 1073 /* 1074 * Another hotplug spec requirement, 1075 * run ddi_set_driver_private(devinfo, null); 1076 */ 1077 ddi_set_driver_private(devinfo, NULL); 1078 } 1079 1080 static void 1081 e1000g_init_locks(struct e1000g *Adapter) 1082 { 1083 e1000g_tx_ring_t *tx_ring; 1084 e1000g_rx_ring_t *rx_ring; 1085 1086 rw_init(&Adapter->chip_lock, NULL, 1087 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1088 mutex_init(&Adapter->link_lock, NULL, 1089 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1090 mutex_init(&Adapter->watchdog_lock, NULL, 1091 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1092 1093 tx_ring = Adapter->tx_ring; 1094 1095 mutex_init(&tx_ring->tx_lock, NULL, 1096 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1097 mutex_init(&tx_ring->usedlist_lock, NULL, 1098 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1099 mutex_init(&tx_ring->freelist_lock, NULL, 1100 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1101 1102 rx_ring = Adapter->rx_ring; 1103 1104 mutex_init(&rx_ring->rx_lock, NULL, 1105 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1106 mutex_init(&rx_ring->freelist_lock, NULL, 1107 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1108 } 1109 1110 static void 1111 e1000g_destroy_locks(struct e1000g *Adapter) 1112 { 1113 e1000g_tx_ring_t *tx_ring; 1114 e1000g_rx_ring_t *rx_ring; 1115 1116 tx_ring = Adapter->tx_ring; 1117 mutex_destroy(&tx_ring->tx_lock); 1118 mutex_destroy(&tx_ring->usedlist_lock); 1119 mutex_destroy(&tx_ring->freelist_lock); 1120 1121 rx_ring = Adapter->rx_ring; 1122 mutex_destroy(&rx_ring->rx_lock); 1123 mutex_destroy(&rx_ring->freelist_lock); 1124 1125 mutex_destroy(&Adapter->link_lock); 1126 mutex_destroy(&Adapter->watchdog_lock); 1127 rw_destroy(&Adapter->chip_lock); 1128 } 1129 1130 static int 1131 e1000g_resume(dev_info_t *devinfo) 1132 { 1133 struct e1000g *Adapter; 1134 1135 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1136 if (Adapter == NULL) 1137 return (DDI_FAILURE); 1138 1139 if (e1000g_start(Adapter, B_TRUE)) 1140 return (DDI_FAILURE); 1141 1142 return (DDI_SUCCESS); 1143 } 1144 1145 static int 1146 e1000g_suspend(dev_info_t *devinfo) 1147 { 1148 struct e1000g *Adapter; 1149 1150 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1151 if (Adapter == NULL) 1152 return (DDI_FAILURE); 1153 1154 e1000g_stop(Adapter, B_TRUE); 1155 1156 return (DDI_SUCCESS); 1157 } 1158 1159 static int 1160 e1000g_init(struct e1000g *Adapter) 1161 { 1162 uint32_t pba; 1163 uint32_t high_water; 1164 struct e1000_hw *hw; 1165 clock_t link_timeout; 1166 int result; 1167 1168 hw = &Adapter->shared; 1169 1170 rw_enter(&Adapter->chip_lock, RW_WRITER); 1171 1172 /* 1173 * reset to put the hardware in a known state 1174 * before we try to do anything with the eeprom 1175 */ 1176 mutex_enter(&e1000g_nvm_lock); 1177 result = e1000_reset_hw(hw); 1178 mutex_exit(&e1000g_nvm_lock); 1179 1180 if (result != E1000_SUCCESS) { 1181 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1182 goto init_fail; 1183 } 1184 1185 mutex_enter(&e1000g_nvm_lock); 1186 result = e1000_validate_nvm_checksum(hw); 1187 if (result < E1000_SUCCESS) { 1188 /* 1189 * Some PCI-E parts fail the first check due to 1190 * the link being in sleep state. Call it again, 1191 * if it fails a second time its a real issue. 1192 */ 1193 result = e1000_validate_nvm_checksum(hw); 1194 } 1195 mutex_exit(&e1000g_nvm_lock); 1196 1197 if (result < E1000_SUCCESS) { 1198 e1000g_log(Adapter, CE_WARN, 1199 "Invalid NVM checksum. Please contact " 1200 "the vendor to update the NVM."); 1201 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1202 goto init_fail; 1203 } 1204 1205 result = 0; 1206 #ifdef __sparc 1207 /* 1208 * First, we try to get the local ethernet address from OBP. If 1209 * failed, then we get it from the EEPROM of NIC card. 1210 */ 1211 result = e1000g_find_mac_address(Adapter); 1212 #endif 1213 /* Get the local ethernet address. */ 1214 if (!result) { 1215 mutex_enter(&e1000g_nvm_lock); 1216 result = e1000_read_mac_addr(hw); 1217 mutex_exit(&e1000g_nvm_lock); 1218 } 1219 1220 if (result < E1000_SUCCESS) { 1221 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1222 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1223 goto init_fail; 1224 } 1225 1226 /* check for valid mac address */ 1227 if (!is_valid_mac_addr(hw->mac.addr)) { 1228 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1229 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1230 goto init_fail; 1231 } 1232 1233 /* Set LAA state for 82571 chipset */ 1234 e1000_set_laa_state_82571(hw, B_TRUE); 1235 1236 /* Master Latency Timer implementation */ 1237 if (Adapter->master_latency_timer) { 1238 pci_config_put8(Adapter->osdep.cfg_handle, 1239 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1240 } 1241 1242 if (hw->mac.type < e1000_82547) { 1243 /* 1244 * Total FIFO is 64K 1245 */ 1246 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1247 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1248 else 1249 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1250 } else if ((hw->mac.type == e1000_82571) || 1251 (hw->mac.type == e1000_82572) || 1252 (hw->mac.type == e1000_80003es2lan)) { 1253 /* 1254 * Total FIFO is 48K 1255 */ 1256 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1257 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1258 else 1259 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1260 } else if (hw->mac.type == e1000_82573) { 1261 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1262 } else if (hw->mac.type == e1000_82574) { 1263 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1264 pba = E1000_READ_REG(hw, E1000_PBA); 1265 } else if (hw->mac.type == e1000_ich8lan) { 1266 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1267 } else if (hw->mac.type == e1000_ich9lan) { 1268 pba = E1000_PBA_10K; 1269 } else if (hw->mac.type == e1000_ich10lan) { 1270 pba = E1000_PBA_10K; 1271 } else { 1272 /* 1273 * Total FIFO is 40K 1274 */ 1275 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1276 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1277 else 1278 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1279 } 1280 E1000_WRITE_REG(hw, E1000_PBA, pba); 1281 1282 /* 1283 * These parameters set thresholds for the adapter's generation(Tx) 1284 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1285 * settings. Flow control is enabled or disabled in the configuration 1286 * file. 1287 * High-water mark is set down from the top of the rx fifo (not 1288 * sensitive to max_frame_size) and low-water is set just below 1289 * high-water mark. 1290 * The high water mark must be low enough to fit one full frame above 1291 * it in the rx FIFO. Should be the lower of: 1292 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1293 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1294 * Rx FIFO size minus one full frame. 1295 */ 1296 high_water = min(((pba << 10) * 9 / 10), 1297 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_ich9lan || 1298 hw->mac.type == e1000_ich10lan) ? 1299 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1300 ((pba << 10) - Adapter->max_frame_size))); 1301 1302 hw->fc.high_water = high_water & 0xFFF8; 1303 hw->fc.low_water = hw->fc.high_water - 8; 1304 1305 if (hw->mac.type == e1000_80003es2lan) 1306 hw->fc.pause_time = 0xFFFF; 1307 else 1308 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1309 hw->fc.send_xon = B_TRUE; 1310 1311 /* 1312 * Reset the adapter hardware the second time. 1313 */ 1314 mutex_enter(&e1000g_nvm_lock); 1315 result = e1000_reset_hw(hw); 1316 mutex_exit(&e1000g_nvm_lock); 1317 1318 if (result != E1000_SUCCESS) { 1319 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1320 goto init_fail; 1321 } 1322 1323 /* disable wakeup control by default */ 1324 if (hw->mac.type >= e1000_82544) 1325 E1000_WRITE_REG(hw, E1000_WUC, 0); 1326 1327 /* MWI setup */ 1328 e1000_pci_set_mwi(hw); 1329 1330 /* 1331 * Configure/Initialize hardware 1332 */ 1333 mutex_enter(&e1000g_nvm_lock); 1334 result = e1000_init_hw(hw); 1335 mutex_exit(&e1000g_nvm_lock); 1336 1337 if (result < E1000_SUCCESS) { 1338 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1339 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1340 goto init_fail; 1341 } 1342 1343 /* 1344 * Restore LED settings to the default from EEPROM 1345 * to meet the standard for Sun platforms. 1346 */ 1347 (void) e1000_cleanup_led(hw); 1348 1349 /* Disable Smart Power Down */ 1350 phy_spd_state(hw, B_FALSE); 1351 1352 /* Make sure driver has control */ 1353 e1000g_get_driver_control(hw); 1354 1355 /* 1356 * Initialize unicast addresses. 1357 */ 1358 e1000g_init_unicst(Adapter); 1359 1360 /* 1361 * Setup and initialize the mctable structures. After this routine 1362 * completes Multicast table will be set 1363 */ 1364 e1000g_setup_multicast(Adapter); 1365 msec_delay(5); 1366 1367 /* 1368 * Implement Adaptive IFS 1369 */ 1370 e1000_reset_adaptive(hw); 1371 1372 /* Setup Interrupt Throttling Register */ 1373 if (hw->mac.type >= e1000_82540) { 1374 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1375 } else 1376 Adapter->intr_adaptive = B_FALSE; 1377 1378 /* Start the timer for link setup */ 1379 if (hw->mac.autoneg) 1380 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1381 else 1382 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1383 1384 mutex_enter(&Adapter->link_lock); 1385 if (hw->phy.autoneg_wait_to_complete) { 1386 Adapter->link_complete = B_TRUE; 1387 } else { 1388 Adapter->link_complete = B_FALSE; 1389 Adapter->link_tid = timeout(e1000g_link_timer, 1390 (void *)Adapter, link_timeout); 1391 } 1392 mutex_exit(&Adapter->link_lock); 1393 1394 /* Enable PCI-Ex master */ 1395 if (hw->bus.type == e1000_bus_type_pci_express) { 1396 e1000_enable_pciex_master(hw); 1397 } 1398 1399 /* Save the state of the phy */ 1400 e1000g_get_phy_state(Adapter); 1401 1402 e1000g_param_sync(Adapter); 1403 1404 Adapter->init_count++; 1405 1406 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1407 goto init_fail; 1408 } 1409 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1410 goto init_fail; 1411 } 1412 1413 rw_exit(&Adapter->chip_lock); 1414 1415 return (DDI_SUCCESS); 1416 1417 init_fail: 1418 rw_exit(&Adapter->chip_lock); 1419 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1420 return (DDI_FAILURE); 1421 } 1422 1423 /* 1424 * Check if the link is up 1425 */ 1426 static boolean_t 1427 e1000g_link_up(struct e1000g *Adapter) 1428 { 1429 struct e1000_hw *hw; 1430 boolean_t link_up; 1431 1432 hw = &Adapter->shared; 1433 1434 (void) e1000_check_for_link(hw); 1435 1436 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1437 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1438 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1439 (hw->mac.serdes_has_link))) { 1440 link_up = B_TRUE; 1441 } else { 1442 link_up = B_FALSE; 1443 } 1444 1445 return (link_up); 1446 } 1447 1448 static void 1449 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1450 { 1451 struct iocblk *iocp; 1452 struct e1000g *e1000gp; 1453 enum ioc_reply status; 1454 1455 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1456 iocp->ioc_error = 0; 1457 e1000gp = (struct e1000g *)arg; 1458 1459 ASSERT(e1000gp); 1460 if (e1000gp == NULL) { 1461 miocnak(q, mp, 0, EINVAL); 1462 return; 1463 } 1464 1465 switch (iocp->ioc_cmd) { 1466 1467 case LB_GET_INFO_SIZE: 1468 case LB_GET_INFO: 1469 case LB_GET_MODE: 1470 case LB_SET_MODE: 1471 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1472 break; 1473 1474 1475 #ifdef E1000G_DEBUG 1476 case E1000G_IOC_REG_PEEK: 1477 case E1000G_IOC_REG_POKE: 1478 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1479 break; 1480 case E1000G_IOC_CHIP_RESET: 1481 e1000gp->reset_count++; 1482 if (e1000g_reset(e1000gp)) 1483 status = IOC_ACK; 1484 else 1485 status = IOC_INVAL; 1486 break; 1487 #endif 1488 default: 1489 status = IOC_INVAL; 1490 break; 1491 } 1492 1493 /* 1494 * Decide how to reply 1495 */ 1496 switch (status) { 1497 default: 1498 case IOC_INVAL: 1499 /* 1500 * Error, reply with a NAK and EINVAL or the specified error 1501 */ 1502 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1503 EINVAL : iocp->ioc_error); 1504 break; 1505 1506 case IOC_DONE: 1507 /* 1508 * OK, reply already sent 1509 */ 1510 break; 1511 1512 case IOC_ACK: 1513 /* 1514 * OK, reply with an ACK 1515 */ 1516 miocack(q, mp, 0, 0); 1517 break; 1518 1519 case IOC_REPLY: 1520 /* 1521 * OK, send prepared reply as ACK or NAK 1522 */ 1523 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1524 M_IOCACK : M_IOCNAK; 1525 qreply(q, mp); 1526 break; 1527 } 1528 } 1529 1530 static int 1531 e1000g_m_start(void *arg) 1532 { 1533 struct e1000g *Adapter = (struct e1000g *)arg; 1534 1535 return (e1000g_start(Adapter, B_TRUE)); 1536 } 1537 1538 static int 1539 e1000g_start(struct e1000g *Adapter, boolean_t global) 1540 { 1541 if (global) { 1542 /* Allocate dma resources for descriptors and buffers */ 1543 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1544 e1000g_log(Adapter, CE_WARN, 1545 "Alloc DMA resources failed"); 1546 return (ENOTACTIVE); 1547 } 1548 Adapter->rx_buffer_setup = B_FALSE; 1549 } 1550 1551 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1552 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1553 e1000g_log(Adapter, CE_WARN, 1554 "Adapter initialization failed"); 1555 if (global) 1556 e1000g_release_dma_resources(Adapter); 1557 return (ENOTACTIVE); 1558 } 1559 } 1560 1561 rw_enter(&Adapter->chip_lock, RW_WRITER); 1562 1563 /* Setup and initialize the transmit structures */ 1564 e1000g_tx_setup(Adapter); 1565 msec_delay(5); 1566 1567 /* Setup and initialize the receive structures */ 1568 e1000g_rx_setup(Adapter); 1569 msec_delay(5); 1570 1571 e1000g_mask_interrupt(Adapter); 1572 1573 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1574 rw_exit(&Adapter->chip_lock); 1575 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1576 return (ENOTACTIVE); 1577 } 1578 1579 Adapter->chip_state = E1000G_START; 1580 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1581 1582 rw_exit(&Adapter->chip_lock); 1583 1584 /* Enable and start the watchdog timer */ 1585 enable_watchdog_timer(Adapter); 1586 1587 return (0); 1588 } 1589 1590 static void 1591 e1000g_m_stop(void *arg) 1592 { 1593 struct e1000g *Adapter = (struct e1000g *)arg; 1594 1595 e1000g_stop(Adapter, B_TRUE); 1596 } 1597 1598 static void 1599 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1600 { 1601 int result; 1602 1603 /* Set stop flags */ 1604 rw_enter(&Adapter->chip_lock, RW_WRITER); 1605 1606 Adapter->chip_state = E1000G_STOP; 1607 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1608 1609 rw_exit(&Adapter->chip_lock); 1610 1611 /* Drain tx sessions */ 1612 (void) e1000g_tx_drain(Adapter); 1613 1614 /* Disable and stop all the timers */ 1615 disable_watchdog_timer(Adapter); 1616 stop_link_timer(Adapter); 1617 stop_82547_timer(Adapter->tx_ring); 1618 1619 /* Stop the chip and release pending resources */ 1620 rw_enter(&Adapter->chip_lock, RW_WRITER); 1621 1622 /* Tell firmware driver is no longer in control */ 1623 e1000g_release_driver_control(&Adapter->shared); 1624 1625 e1000g_clear_all_interrupts(Adapter); 1626 1627 mutex_enter(&e1000g_nvm_lock); 1628 result = e1000_reset_hw(&Adapter->shared); 1629 mutex_exit(&e1000g_nvm_lock); 1630 1631 if (result != E1000_SUCCESS) { 1632 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1633 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1634 } 1635 1636 /* Release resources still held by the TX descriptors */ 1637 e1000g_tx_clean(Adapter); 1638 1639 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1640 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1641 1642 /* Clean the pending rx jumbo packet fragment */ 1643 e1000g_rx_clean(Adapter); 1644 1645 rw_exit(&Adapter->chip_lock); 1646 1647 if (global) 1648 e1000g_release_dma_resources(Adapter); 1649 } 1650 1651 static void 1652 e1000g_rx_clean(struct e1000g *Adapter) 1653 { 1654 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 1655 1656 if (rx_ring->rx_mblk != NULL) { 1657 freemsg(rx_ring->rx_mblk); 1658 rx_ring->rx_mblk = NULL; 1659 rx_ring->rx_mblk_tail = NULL; 1660 rx_ring->rx_mblk_len = 0; 1661 } 1662 } 1663 1664 static void 1665 e1000g_tx_clean(struct e1000g *Adapter) 1666 { 1667 e1000g_tx_ring_t *tx_ring; 1668 p_tx_sw_packet_t packet; 1669 mblk_t *mp; 1670 mblk_t *nmp; 1671 uint32_t packet_count; 1672 1673 tx_ring = Adapter->tx_ring; 1674 1675 /* 1676 * Here we don't need to protect the lists using 1677 * the usedlist_lock and freelist_lock, for they 1678 * have been protected by the chip_lock. 1679 */ 1680 mp = NULL; 1681 nmp = NULL; 1682 packet_count = 0; 1683 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1684 while (packet != NULL) { 1685 if (packet->mp != NULL) { 1686 /* Assemble the message chain */ 1687 if (mp == NULL) { 1688 mp = packet->mp; 1689 nmp = packet->mp; 1690 } else { 1691 nmp->b_next = packet->mp; 1692 nmp = packet->mp; 1693 } 1694 /* Disconnect the message from the sw packet */ 1695 packet->mp = NULL; 1696 } 1697 1698 e1000g_free_tx_swpkt(packet); 1699 packet_count++; 1700 1701 packet = (p_tx_sw_packet_t) 1702 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1703 } 1704 1705 if (mp != NULL) 1706 freemsgchain(mp); 1707 1708 if (packet_count > 0) { 1709 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1710 QUEUE_INIT_LIST(&tx_ring->used_list); 1711 1712 /* Setup TX descriptor pointers */ 1713 tx_ring->tbd_next = tx_ring->tbd_first; 1714 tx_ring->tbd_oldest = tx_ring->tbd_first; 1715 1716 /* Setup our HW Tx Head & Tail descriptor pointers */ 1717 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1718 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1719 } 1720 } 1721 1722 static boolean_t 1723 e1000g_tx_drain(struct e1000g *Adapter) 1724 { 1725 int i; 1726 boolean_t done; 1727 e1000g_tx_ring_t *tx_ring; 1728 1729 tx_ring = Adapter->tx_ring; 1730 1731 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1732 for (i = 0; i < TX_DRAIN_TIME; i++) { 1733 mutex_enter(&tx_ring->usedlist_lock); 1734 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1735 mutex_exit(&tx_ring->usedlist_lock); 1736 1737 if (done) 1738 break; 1739 1740 msec_delay(1); 1741 } 1742 1743 return (done); 1744 } 1745 1746 static boolean_t 1747 e1000g_rx_drain(struct e1000g *Adapter) 1748 { 1749 e1000g_rx_ring_t *rx_ring; 1750 p_rx_sw_packet_t packet; 1751 boolean_t done; 1752 1753 rx_ring = Adapter->rx_ring; 1754 done = B_TRUE; 1755 1756 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 1757 1758 while (rx_ring->pending_list != NULL) { 1759 packet = rx_ring->pending_list; 1760 rx_ring->pending_list = 1761 rx_ring->pending_list->next; 1762 1763 if (packet->flag == E1000G_RX_SW_STOP) { 1764 packet->flag = E1000G_RX_SW_DETACH; 1765 done = B_FALSE; 1766 } else { 1767 ASSERT(packet->flag == E1000G_RX_SW_FREE); 1768 ASSERT(packet->mp == NULL); 1769 e1000g_free_rx_sw_packet(packet); 1770 } 1771 } 1772 1773 rw_exit(&e1000g_rx_detach_lock); 1774 1775 return (done); 1776 } 1777 1778 boolean_t 1779 e1000g_reset(struct e1000g *Adapter) 1780 { 1781 e1000g_stop(Adapter, B_FALSE); 1782 1783 if (e1000g_start(Adapter, B_FALSE)) { 1784 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1785 return (B_FALSE); 1786 } 1787 1788 return (B_TRUE); 1789 } 1790 1791 boolean_t 1792 e1000g_global_reset(struct e1000g *Adapter) 1793 { 1794 e1000g_stop(Adapter, B_TRUE); 1795 1796 Adapter->init_count = 0; 1797 1798 if (e1000g_start(Adapter, B_TRUE)) { 1799 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1800 return (B_FALSE); 1801 } 1802 1803 return (B_TRUE); 1804 } 1805 1806 /* 1807 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 1808 * 1809 * This interrupt service routine is for PCI-Express adapters. 1810 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 1811 * bit is set. 1812 */ 1813 static uint_t 1814 e1000g_intr_pciexpress(caddr_t arg) 1815 { 1816 struct e1000g *Adapter; 1817 uint32_t icr; 1818 1819 Adapter = (struct e1000g *)(uintptr_t)arg; 1820 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1821 1822 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1823 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1824 1825 if (icr & E1000_ICR_INT_ASSERTED) { 1826 /* 1827 * E1000_ICR_INT_ASSERTED bit was set: 1828 * Read(Clear) the ICR, claim this interrupt, 1829 * look for work to do. 1830 */ 1831 e1000g_intr_work(Adapter, icr); 1832 return (DDI_INTR_CLAIMED); 1833 } else { 1834 /* 1835 * E1000_ICR_INT_ASSERTED bit was not set: 1836 * Don't claim this interrupt, return immediately. 1837 */ 1838 return (DDI_INTR_UNCLAIMED); 1839 } 1840 } 1841 1842 /* 1843 * e1000g_intr - ISR for PCI/PCI-X chipsets 1844 * 1845 * This interrupt service routine is for PCI/PCI-X adapters. 1846 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 1847 * bit is set or not. 1848 */ 1849 static uint_t 1850 e1000g_intr(caddr_t arg) 1851 { 1852 struct e1000g *Adapter; 1853 uint32_t icr; 1854 1855 Adapter = (struct e1000g *)(uintptr_t)arg; 1856 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1857 1858 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1859 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1860 1861 if (icr) { 1862 /* 1863 * Any bit was set in ICR: 1864 * Read(Clear) the ICR, claim this interrupt, 1865 * look for work to do. 1866 */ 1867 e1000g_intr_work(Adapter, icr); 1868 return (DDI_INTR_CLAIMED); 1869 } else { 1870 /* 1871 * No bit was set in ICR: 1872 * Don't claim this interrupt, return immediately. 1873 */ 1874 return (DDI_INTR_UNCLAIMED); 1875 } 1876 } 1877 1878 /* 1879 * e1000g_intr_work - actual processing of ISR 1880 * 1881 * Read(clear) the ICR contents and call appropriate interrupt 1882 * processing routines. 1883 */ 1884 static void 1885 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 1886 { 1887 struct e1000_hw *hw; 1888 hw = &Adapter->shared; 1889 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 1890 uint32_t itr; 1891 1892 Adapter->rx_pkt_cnt = 0; 1893 Adapter->tx_pkt_cnt = 0; 1894 1895 rw_enter(&Adapter->chip_lock, RW_READER); 1896 /* 1897 * Here we need to check the "chip_state" flag within the chip_lock to 1898 * ensure the receive routine will not execute when the adapter is 1899 * being reset. 1900 */ 1901 if (Adapter->chip_state != E1000G_START) { 1902 rw_exit(&Adapter->chip_lock); 1903 return; 1904 } 1905 1906 if (icr & E1000_ICR_RXT0) { 1907 mblk_t *mp; 1908 1909 mutex_enter(&Adapter->rx_ring->rx_lock); 1910 mp = e1000g_receive(Adapter); 1911 mutex_exit(&Adapter->rx_ring->rx_lock); 1912 1913 rw_exit(&Adapter->chip_lock); 1914 1915 if (mp != NULL) 1916 mac_rx(Adapter->mh, Adapter->mrh, mp); 1917 } else 1918 rw_exit(&Adapter->chip_lock); 1919 1920 if (icr & E1000_ICR_TXDW) { 1921 if (!Adapter->tx_intr_enable) 1922 e1000g_clear_tx_interrupt(Adapter); 1923 1924 /* Recycle the tx descriptors */ 1925 rw_enter(&Adapter->chip_lock, RW_READER); 1926 (void) e1000g_recycle(tx_ring); 1927 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 1928 rw_exit(&Adapter->chip_lock); 1929 1930 /* Schedule the re-transmit */ 1931 if (tx_ring->resched_needed && 1932 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 1933 tx_ring->resched_needed = B_FALSE; 1934 mac_tx_update(Adapter->mh); 1935 E1000G_STAT(tx_ring->stat_reschedule); 1936 } 1937 } 1938 1939 if (Adapter->intr_adaptive) { 1940 itr = e1000g_get_itr(Adapter->rx_pkt_cnt, Adapter->tx_pkt_cnt, 1941 Adapter->intr_throttling_rate); 1942 if (itr) { 1943 E1000_WRITE_REG(hw, E1000_ITR, itr); 1944 Adapter->intr_throttling_rate = itr; 1945 } 1946 } 1947 1948 /* 1949 * The Receive Sequence errors RXSEQ and the link status change LSC 1950 * are checked to detect that the cable has been pulled out. For 1951 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1952 * are an indication that cable is not connected. 1953 */ 1954 if ((icr & E1000_ICR_RXSEQ) || 1955 (icr & E1000_ICR_LSC) || 1956 (icr & E1000_ICR_GPI_EN1)) { 1957 boolean_t link_changed; 1958 timeout_id_t tid = 0; 1959 1960 stop_watchdog_timer(Adapter); 1961 1962 rw_enter(&Adapter->chip_lock, RW_WRITER); 1963 1964 /* 1965 * Because we got a link-status-change interrupt, force 1966 * e1000_check_for_link() to look at phy 1967 */ 1968 Adapter->shared.mac.get_link_status = B_TRUE; 1969 1970 /* e1000g_link_check takes care of link status change */ 1971 link_changed = e1000g_link_check(Adapter); 1972 1973 /* Get new phy state */ 1974 e1000g_get_phy_state(Adapter); 1975 1976 /* 1977 * If the link timer has not timed out, we'll not notify 1978 * the upper layer with any link state until the link is up. 1979 */ 1980 if (link_changed && !Adapter->link_complete) { 1981 if (Adapter->link_state == LINK_STATE_UP) { 1982 mutex_enter(&Adapter->link_lock); 1983 Adapter->link_complete = B_TRUE; 1984 tid = Adapter->link_tid; 1985 Adapter->link_tid = 0; 1986 mutex_exit(&Adapter->link_lock); 1987 } else { 1988 link_changed = B_FALSE; 1989 } 1990 } 1991 rw_exit(&Adapter->chip_lock); 1992 1993 if (link_changed) { 1994 if (tid != 0) 1995 (void) untimeout(tid); 1996 1997 /* 1998 * Workaround for esb2. Data stuck in fifo on a link 1999 * down event. Stop receiver here and reset in watchdog. 2000 */ 2001 if ((Adapter->link_state == LINK_STATE_DOWN) && 2002 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2003 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2004 E1000_WRITE_REG(hw, E1000_RCTL, 2005 rctl & ~E1000_RCTL_EN); 2006 e1000g_log(Adapter, CE_WARN, 2007 "ESB2 receiver disabled"); 2008 Adapter->esb2_workaround = B_TRUE; 2009 } 2010 2011 mac_link_update(Adapter->mh, Adapter->link_state); 2012 } 2013 2014 start_watchdog_timer(Adapter); 2015 } 2016 } 2017 2018 static uint32_t 2019 e1000g_get_itr(uint32_t rx_packet, uint32_t tx_packet, uint32_t cur_itr) 2020 { 2021 uint32_t new_itr; 2022 2023 /* 2024 * Determine a propper itr according to rx/tx packet count 2025 * per interrupt, the value of itr are based on document 2026 * and testing. 2027 */ 2028 if ((rx_packet < DEFAULT_INTR_PACKET_LOW) || 2029 (tx_packet < DEFAULT_INTR_PACKET_LOW)) { 2030 new_itr = DEFAULT_INTR_THROTTLING_LOW; 2031 goto itr_done; 2032 } 2033 if ((rx_packet > DEFAULT_INTR_PACKET_HIGH) || 2034 (tx_packet > DEFAULT_INTR_PACKET_HIGH)) { 2035 new_itr = DEFAULT_INTR_THROTTLING_LOW; 2036 goto itr_done; 2037 } 2038 if (cur_itr < DEFAULT_INTR_THROTTLING_HIGH) { 2039 new_itr = cur_itr + (DEFAULT_INTR_THROTTLING_HIGH >> 2); 2040 if (new_itr > DEFAULT_INTR_THROTTLING_HIGH) 2041 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 2042 } else 2043 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 2044 2045 itr_done: 2046 if (cur_itr == new_itr) 2047 return (0); 2048 else 2049 return (new_itr); 2050 } 2051 2052 static void 2053 e1000g_init_unicst(struct e1000g *Adapter) 2054 { 2055 struct e1000_hw *hw; 2056 int slot; 2057 2058 hw = &Adapter->shared; 2059 2060 if (!Adapter->unicst_init) { 2061 /* Initialize the multiple unicast addresses */ 2062 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2063 2064 if ((hw->mac.type == e1000_82571) && 2065 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2066 Adapter->unicst_total--; 2067 2068 Adapter->unicst_avail = Adapter->unicst_total - 1; 2069 2070 /* Store the default mac address */ 2071 e1000_rar_set(hw, hw->mac.addr, 0); 2072 if ((hw->mac.type == e1000_82571) && 2073 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2074 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2075 2076 bcopy(hw->mac.addr, Adapter->unicst_addr[0].mac.addr, 2077 ETHERADDRL); 2078 Adapter->unicst_addr[0].mac.set = 1; 2079 2080 for (slot = 1; slot < Adapter->unicst_total; slot++) 2081 Adapter->unicst_addr[slot].mac.set = 0; 2082 2083 Adapter->unicst_init = B_TRUE; 2084 } else { 2085 /* Recover the default mac address */ 2086 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac.addr, 2087 ETHERADDRL); 2088 2089 /* Store the default mac address */ 2090 e1000_rar_set(hw, hw->mac.addr, 0); 2091 if ((hw->mac.type == e1000_82571) && 2092 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2093 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2094 2095 /* Re-configure the RAR registers */ 2096 for (slot = 1; slot < Adapter->unicst_total; slot++) 2097 e1000_rar_set(hw, 2098 Adapter->unicst_addr[slot].mac.addr, slot); 2099 } 2100 2101 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2102 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2103 } 2104 2105 static int 2106 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 2107 { 2108 struct e1000g *Adapter; 2109 2110 Adapter = (struct e1000g *)arg; 2111 2112 /* Store the default MAC address */ 2113 bcopy(mac_addr, Adapter->shared.mac.addr, ETHERADDRL); 2114 2115 /* Set MAC address in address slot 0, which is the default address */ 2116 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 2117 } 2118 2119 static int 2120 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2121 mac_addr_slot_t slot) 2122 { 2123 struct e1000_hw *hw; 2124 2125 hw = &Adapter->shared; 2126 2127 rw_enter(&Adapter->chip_lock, RW_WRITER); 2128 2129 /* 2130 * The first revision of Wiseman silicon (rev 2.0) has an errata 2131 * that requires the receiver to be in reset when any of the 2132 * receive address registers (RAR regs) are accessed. The first 2133 * rev of Wiseman silicon also requires MWI to be disabled when 2134 * a global reset or a receive reset is issued. So before we 2135 * initialize the RARs, we check the rev of the Wiseman controller 2136 * and work around any necessary HW errata. 2137 */ 2138 if ((hw->mac.type == e1000_82542) && 2139 (hw->revision_id == E1000_REVISION_2)) { 2140 e1000_pci_clear_mwi(hw); 2141 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2142 msec_delay(5); 2143 } 2144 2145 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 2146 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2147 2148 if (slot == 0) { 2149 if ((hw->mac.type == e1000_82571) && 2150 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2151 e1000_rar_set(hw, (uint8_t *)mac_addr, LAST_RAR_ENTRY); 2152 } 2153 2154 /* 2155 * If we are using Wiseman rev 2.0 silicon, we will have previously 2156 * put the receive in reset, and disabled MWI, to work around some 2157 * HW errata. Now we should take the receiver out of reset, and 2158 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2159 */ 2160 if ((hw->mac.type == e1000_82542) && 2161 (hw->revision_id == E1000_REVISION_2)) { 2162 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2163 msec_delay(1); 2164 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2165 e1000_pci_set_mwi(hw); 2166 e1000g_rx_setup(Adapter); 2167 } 2168 2169 rw_exit(&Adapter->chip_lock); 2170 2171 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2172 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2173 return (EIO); 2174 } 2175 2176 return (0); 2177 } 2178 2179 /* 2180 * e1000g_m_unicst_add() - will find an unused address slot, set the 2181 * address value to the one specified, reserve that slot and enable 2182 * the NIC to start filtering on the new MAC address. 2183 * Returns 0 on success. 2184 */ 2185 static int 2186 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 2187 { 2188 struct e1000g *Adapter = (struct e1000g *)arg; 2189 mac_addr_slot_t slot; 2190 int err; 2191 2192 if (mac_unicst_verify(Adapter->mh, 2193 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2194 return (EINVAL); 2195 2196 rw_enter(&Adapter->chip_lock, RW_WRITER); 2197 if (Adapter->unicst_avail == 0) { 2198 /* no slots available */ 2199 rw_exit(&Adapter->chip_lock); 2200 return (ENOSPC); 2201 } 2202 2203 /* 2204 * Primary/default address is in slot 0. The next addresses 2205 * are the multiple MAC addresses. So multiple MAC address 0 2206 * is in slot 1, 1 in slot 2, and so on. So the first multiple 2207 * MAC address resides in slot 1. 2208 */ 2209 for (slot = 1; slot < Adapter->unicst_total; slot++) { 2210 if (Adapter->unicst_addr[slot].mac.set == 0) { 2211 Adapter->unicst_addr[slot].mac.set = 1; 2212 break; 2213 } 2214 } 2215 2216 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 2217 2218 Adapter->unicst_avail--; 2219 rw_exit(&Adapter->chip_lock); 2220 2221 maddr->mma_slot = slot; 2222 2223 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 2224 rw_enter(&Adapter->chip_lock, RW_WRITER); 2225 Adapter->unicst_addr[slot].mac.set = 0; 2226 Adapter->unicst_avail++; 2227 rw_exit(&Adapter->chip_lock); 2228 } 2229 2230 return (err); 2231 } 2232 2233 /* 2234 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 2235 * call to e1000g_m_unicst_add(). The slot number that was returned in 2236 * e1000g_m_unicst_add() is passed in the call to remove the address. 2237 * Returns 0 on success. 2238 */ 2239 static int 2240 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 2241 { 2242 struct e1000g *Adapter = (struct e1000g *)arg; 2243 int err; 2244 2245 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2246 return (EINVAL); 2247 2248 rw_enter(&Adapter->chip_lock, RW_WRITER); 2249 if (Adapter->unicst_addr[slot].mac.set == 1) { 2250 Adapter->unicst_addr[slot].mac.set = 0; 2251 Adapter->unicst_avail++; 2252 rw_exit(&Adapter->chip_lock); 2253 2254 /* Copy the default address to the passed slot */ 2255 if ((err = e1000g_unicst_set(Adapter, 2256 Adapter->unicst_addr[0].mac.addr, slot)) != 0) { 2257 rw_enter(&Adapter->chip_lock, RW_WRITER); 2258 Adapter->unicst_addr[slot].mac.set = 1; 2259 Adapter->unicst_avail--; 2260 rw_exit(&Adapter->chip_lock); 2261 } 2262 return (err); 2263 } 2264 rw_exit(&Adapter->chip_lock); 2265 2266 return (EINVAL); 2267 } 2268 2269 /* 2270 * e1000g_m_unicst_modify() - modifies the value of an address that 2271 * has been added by e1000g_m_unicst_add(). The new address, address 2272 * length and the slot number that was returned in the call to add 2273 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2274 * set to 0. Returns 0 on success. 2275 */ 2276 static int 2277 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2278 { 2279 struct e1000g *Adapter = (struct e1000g *)arg; 2280 mac_addr_slot_t slot; 2281 2282 if (mac_unicst_verify(Adapter->mh, 2283 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2284 return (EINVAL); 2285 2286 slot = maddr->mma_slot; 2287 2288 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2289 return (EINVAL); 2290 2291 rw_enter(&Adapter->chip_lock, RW_WRITER); 2292 if (Adapter->unicst_addr[slot].mac.set == 1) { 2293 rw_exit(&Adapter->chip_lock); 2294 2295 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2296 } 2297 rw_exit(&Adapter->chip_lock); 2298 2299 return (EINVAL); 2300 } 2301 2302 /* 2303 * e1000g_m_unicst_get() - will get the MAC address and all other 2304 * information related to the address slot passed in mac_multi_addr_t. 2305 * mma_flags should be set to 0 in the call. 2306 * On return, mma_flags can take the following values: 2307 * 1) MMAC_SLOT_UNUSED 2308 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2309 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2310 * 4) MMAC_SLOT_USED 2311 */ 2312 static int 2313 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2314 { 2315 struct e1000g *Adapter = (struct e1000g *)arg; 2316 mac_addr_slot_t slot; 2317 2318 slot = maddr->mma_slot; 2319 2320 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2321 return (EINVAL); 2322 2323 rw_enter(&Adapter->chip_lock, RW_WRITER); 2324 if (Adapter->unicst_addr[slot].mac.set == 1) { 2325 bcopy(Adapter->unicst_addr[slot].mac.addr, 2326 maddr->mma_addr, ETHERADDRL); 2327 maddr->mma_flags = MMAC_SLOT_USED; 2328 } else { 2329 maddr->mma_flags = MMAC_SLOT_UNUSED; 2330 } 2331 rw_exit(&Adapter->chip_lock); 2332 2333 return (0); 2334 } 2335 2336 static int 2337 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2338 { 2339 struct e1000_hw *hw = &Adapter->shared; 2340 int res = 0; 2341 2342 rw_enter(&Adapter->chip_lock, RW_WRITER); 2343 2344 if ((multiaddr[0] & 01) == 0) { 2345 res = EINVAL; 2346 goto done; 2347 } 2348 2349 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2350 res = ENOENT; 2351 goto done; 2352 } 2353 2354 bcopy(multiaddr, 2355 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2356 Adapter->mcast_count++; 2357 2358 /* 2359 * Update the MC table in the hardware 2360 */ 2361 e1000g_clear_interrupt(Adapter); 2362 2363 e1000g_setup_multicast(Adapter); 2364 2365 if ((hw->mac.type == e1000_82542) && 2366 (hw->revision_id == E1000_REVISION_2)) 2367 e1000g_rx_setup(Adapter); 2368 2369 e1000g_mask_interrupt(Adapter); 2370 2371 done: 2372 rw_exit(&Adapter->chip_lock); 2373 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2374 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2375 res = EIO; 2376 } 2377 2378 return (res); 2379 } 2380 2381 static int 2382 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2383 { 2384 struct e1000_hw *hw = &Adapter->shared; 2385 unsigned i; 2386 2387 rw_enter(&Adapter->chip_lock, RW_WRITER); 2388 2389 for (i = 0; i < Adapter->mcast_count; i++) { 2390 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2391 ETHERADDRL) == 0) { 2392 for (i++; i < Adapter->mcast_count; i++) { 2393 Adapter->mcast_table[i - 1] = 2394 Adapter->mcast_table[i]; 2395 } 2396 Adapter->mcast_count--; 2397 break; 2398 } 2399 } 2400 2401 /* 2402 * Update the MC table in the hardware 2403 */ 2404 e1000g_clear_interrupt(Adapter); 2405 2406 e1000g_setup_multicast(Adapter); 2407 2408 if ((hw->mac.type == e1000_82542) && 2409 (hw->revision_id == E1000_REVISION_2)) 2410 e1000g_rx_setup(Adapter); 2411 2412 e1000g_mask_interrupt(Adapter); 2413 2414 done: 2415 rw_exit(&Adapter->chip_lock); 2416 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2417 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2418 return (EIO); 2419 } 2420 2421 return (0); 2422 } 2423 2424 /* 2425 * e1000g_setup_multicast - setup multicast data structures 2426 * 2427 * This routine initializes all of the multicast related structures. 2428 */ 2429 void 2430 e1000g_setup_multicast(struct e1000g *Adapter) 2431 { 2432 uint8_t *mc_addr_list; 2433 uint32_t mc_addr_count; 2434 uint32_t rctl; 2435 struct e1000_hw *hw; 2436 2437 hw = &Adapter->shared; 2438 2439 /* 2440 * The e1000g has the ability to do perfect filtering of 16 2441 * addresses. The driver uses one of the e1000g's 16 receive 2442 * address registers for its node/network/mac/individual address. 2443 * So, we have room for up to 15 multicast addresses in the CAM, 2444 * additional MC addresses are handled by the MTA (Multicast Table 2445 * Array) 2446 */ 2447 2448 rctl = E1000_READ_REG(hw, E1000_RCTL); 2449 2450 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2451 2452 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2453 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2454 "Adapter requested more than %d MC Addresses.\n", 2455 MAX_NUM_MULTICAST_ADDRESSES); 2456 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2457 } else { 2458 /* 2459 * Set the number of MC addresses that we are being 2460 * requested to use 2461 */ 2462 mc_addr_count = Adapter->mcast_count; 2463 } 2464 /* 2465 * The Wiseman 2.0 silicon has an errata by which the receiver will 2466 * hang while writing to the receive address registers if the receiver 2467 * is not in reset before writing to the registers. Updating the RAR 2468 * is done during the setting up of the multicast table, hence the 2469 * receiver has to be put in reset before updating the multicast table 2470 * and then taken out of reset at the end 2471 */ 2472 /* 2473 * if WMI was enabled then dis able it before issueing the global 2474 * reset to the hardware. 2475 */ 2476 /* 2477 * Only required for WISEMAN_2_0 2478 */ 2479 if ((hw->mac.type == e1000_82542) && 2480 (hw->revision_id == E1000_REVISION_2)) { 2481 e1000_pci_clear_mwi(hw); 2482 /* 2483 * The e1000g must be in reset before changing any RA 2484 * registers. Reset receive unit. The chip will remain in 2485 * the reset state until software explicitly restarts it. 2486 */ 2487 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2488 /* Allow receiver time to go in to reset */ 2489 msec_delay(5); 2490 } 2491 2492 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2493 Adapter->unicst_total, hw->mac.rar_entry_count); 2494 2495 /* 2496 * Only for Wiseman_2_0 2497 * If MWI was enabled then re-enable it after issueing (as we 2498 * disabled it up there) the receive reset command. 2499 * Wainwright does not have a receive reset command and only thing 2500 * close to it is global reset which will require tx setup also 2501 */ 2502 if ((hw->mac.type == e1000_82542) && 2503 (hw->revision_id == E1000_REVISION_2)) { 2504 /* 2505 * if WMI was enabled then reenable it after issueing the 2506 * global or receive reset to the hardware. 2507 */ 2508 2509 /* 2510 * Take receiver out of reset 2511 * clear E1000_RCTL_RST bit (and all others) 2512 */ 2513 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2514 msec_delay(5); 2515 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2516 e1000_pci_set_mwi(hw); 2517 } 2518 2519 /* 2520 * Restore original value 2521 */ 2522 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2523 } 2524 2525 int 2526 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2527 { 2528 struct e1000g *Adapter = (struct e1000g *)arg; 2529 2530 return ((add) ? multicst_add(Adapter, addr) 2531 : multicst_remove(Adapter, addr)); 2532 } 2533 2534 int 2535 e1000g_m_promisc(void *arg, boolean_t on) 2536 { 2537 struct e1000g *Adapter = (struct e1000g *)arg; 2538 uint32_t rctl; 2539 2540 rw_enter(&Adapter->chip_lock, RW_WRITER); 2541 2542 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2543 2544 if (on) 2545 rctl |= 2546 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2547 else 2548 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2549 2550 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2551 2552 Adapter->e1000g_promisc = on; 2553 2554 rw_exit(&Adapter->chip_lock); 2555 2556 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2557 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2558 return (EIO); 2559 } 2560 2561 return (0); 2562 } 2563 2564 static boolean_t 2565 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2566 { 2567 struct e1000g *Adapter = (struct e1000g *)arg; 2568 2569 switch (cap) { 2570 case MAC_CAPAB_HCKSUM: { 2571 uint32_t *txflags = cap_data; 2572 2573 if (Adapter->tx_hcksum_enable) 2574 *txflags = HCKSUM_IPHDRCKSUM | 2575 HCKSUM_INET_PARTIAL; 2576 else 2577 return (B_FALSE); 2578 break; 2579 } 2580 case MAC_CAPAB_POLL: 2581 /* 2582 * There's nothing for us to fill in, simply returning 2583 * B_TRUE stating that we support polling is sufficient. 2584 */ 2585 break; 2586 2587 case MAC_CAPAB_MULTIADDRESS: { 2588 multiaddress_capab_t *mmacp = cap_data; 2589 2590 /* 2591 * The number of MAC addresses made available by 2592 * this capability is one less than the total as 2593 * the primary address in slot 0 is counted in 2594 * the total. 2595 */ 2596 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2597 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2598 /* No multiple factory addresses, set mma_flag to 0 */ 2599 mmacp->maddr_flag = 0; 2600 mmacp->maddr_handle = Adapter; 2601 mmacp->maddr_add = e1000g_m_unicst_add; 2602 mmacp->maddr_remove = e1000g_m_unicst_remove; 2603 mmacp->maddr_modify = e1000g_m_unicst_modify; 2604 mmacp->maddr_get = e1000g_m_unicst_get; 2605 mmacp->maddr_reserve = NULL; 2606 break; 2607 } 2608 2609 case MAC_CAPAB_LSO: { 2610 mac_capab_lso_t *cap_lso = cap_data; 2611 2612 if (Adapter->lso_enable) { 2613 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2614 cap_lso->lso_basic_tcp_ipv4.lso_max = 2615 E1000_LSO_MAXLEN; 2616 } else 2617 return (B_FALSE); 2618 break; 2619 } 2620 2621 default: 2622 return (B_FALSE); 2623 } 2624 return (B_TRUE); 2625 } 2626 2627 static boolean_t 2628 e1000g_param_locked(mac_prop_id_t pr_num) 2629 { 2630 /* 2631 * All en_* parameters are locked (read-only) while 2632 * the device is in any sort of loopback mode ... 2633 */ 2634 switch (pr_num) { 2635 case MAC_PROP_EN_1000FDX_CAP: 2636 case MAC_PROP_EN_1000HDX_CAP: 2637 case MAC_PROP_EN_100FDX_CAP: 2638 case MAC_PROP_EN_100HDX_CAP: 2639 case MAC_PROP_EN_10FDX_CAP: 2640 case MAC_PROP_EN_10HDX_CAP: 2641 case MAC_PROP_AUTONEG: 2642 case MAC_PROP_FLOWCTRL: 2643 return (B_TRUE); 2644 } 2645 return (B_FALSE); 2646 } 2647 2648 /* 2649 * callback function for set/get of properties 2650 */ 2651 static int 2652 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2653 uint_t pr_valsize, const void *pr_val) 2654 { 2655 struct e1000g *Adapter = arg; 2656 struct e1000_mac_info *mac = &Adapter->shared.mac; 2657 struct e1000_phy_info *phy = &Adapter->shared.phy; 2658 struct e1000_fc_info *fc = &Adapter->shared.fc; 2659 int err = 0; 2660 link_flowctrl_t flowctrl; 2661 uint32_t cur_mtu, new_mtu; 2662 uint64_t tmp = 0; 2663 2664 rw_enter(&Adapter->chip_lock, RW_WRITER); 2665 if (Adapter->loopback_mode != E1000G_LB_NONE && 2666 e1000g_param_locked(pr_num)) { 2667 /* 2668 * All en_* parameters are locked (read-only) 2669 * while the device is in any sort of loopback mode. 2670 */ 2671 rw_exit(&Adapter->chip_lock); 2672 return (EBUSY); 2673 } 2674 2675 switch (pr_num) { 2676 case MAC_PROP_EN_1000FDX_CAP: 2677 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 2678 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 2679 goto reset; 2680 case MAC_PROP_EN_1000HDX_CAP: 2681 Adapter->param_en_1000hdx = *(uint8_t *)pr_val; 2682 Adapter->param_adv_1000hdx = *(uint8_t *)pr_val; 2683 goto reset; 2684 case MAC_PROP_EN_100FDX_CAP: 2685 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 2686 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 2687 goto reset; 2688 case MAC_PROP_EN_100HDX_CAP: 2689 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 2690 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 2691 goto reset; 2692 case MAC_PROP_EN_10FDX_CAP: 2693 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 2694 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 2695 goto reset; 2696 case MAC_PROP_EN_10HDX_CAP: 2697 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 2698 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 2699 goto reset; 2700 case MAC_PROP_AUTONEG: 2701 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 2702 goto reset; 2703 case MAC_PROP_FLOWCTRL: 2704 fc->send_xon = B_TRUE; 2705 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 2706 2707 switch (flowctrl) { 2708 default: 2709 err = EINVAL; 2710 break; 2711 case LINK_FLOWCTRL_NONE: 2712 fc->type = e1000_fc_none; 2713 break; 2714 case LINK_FLOWCTRL_RX: 2715 fc->type = e1000_fc_rx_pause; 2716 break; 2717 case LINK_FLOWCTRL_TX: 2718 fc->type = e1000_fc_tx_pause; 2719 break; 2720 case LINK_FLOWCTRL_BI: 2721 fc->type = e1000_fc_full; 2722 break; 2723 } 2724 reset: 2725 if (err == 0) { 2726 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 2727 err = EINVAL; 2728 } 2729 break; 2730 case MAC_PROP_ADV_1000FDX_CAP: 2731 case MAC_PROP_ADV_1000HDX_CAP: 2732 case MAC_PROP_ADV_100FDX_CAP: 2733 case MAC_PROP_ADV_100HDX_CAP: 2734 case MAC_PROP_ADV_10FDX_CAP: 2735 case MAC_PROP_ADV_10HDX_CAP: 2736 case MAC_PROP_STATUS: 2737 case MAC_PROP_SPEED: 2738 case MAC_PROP_DUPLEX: 2739 err = ENOTSUP; /* read-only prop. Can't set this. */ 2740 break; 2741 case MAC_PROP_MTU: 2742 cur_mtu = Adapter->default_mtu; 2743 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 2744 if (new_mtu == cur_mtu) { 2745 err = 0; 2746 break; 2747 } 2748 2749 tmp = new_mtu + sizeof (struct ether_vlan_header) + 2750 ETHERFCSL; 2751 if ((tmp < DEFAULT_FRAME_SIZE) || 2752 (tmp > MAXIMUM_FRAME_SIZE)) { 2753 err = EINVAL; 2754 break; 2755 } 2756 2757 /* ich8 does not support jumbo frames */ 2758 if ((mac->type == e1000_ich8lan) && 2759 (tmp > DEFAULT_FRAME_SIZE)) { 2760 err = EINVAL; 2761 break; 2762 } 2763 /* ich9 does not do jumbo frames on one phy type */ 2764 if ((mac->type == e1000_ich9lan) && 2765 (phy->type == e1000_phy_ife) && 2766 (tmp > DEFAULT_FRAME_SIZE)) { 2767 err = EINVAL; 2768 break; 2769 } 2770 if (Adapter->chip_state != E1000G_STOP) { 2771 err = EBUSY; 2772 break; 2773 } 2774 2775 err = mac_maxsdu_update(Adapter->mh, new_mtu); 2776 if (err == 0) { 2777 Adapter->max_frame_size = (uint32_t)tmp; 2778 Adapter->default_mtu = new_mtu; 2779 e1000g_set_bufsize(Adapter); 2780 } 2781 break; 2782 case MAC_PROP_PRIVATE: 2783 err = e1000g_set_priv_prop(Adapter, pr_name, 2784 pr_valsize, pr_val); 2785 break; 2786 default: 2787 err = ENOTSUP; 2788 break; 2789 } 2790 rw_exit(&Adapter->chip_lock); 2791 return (err); 2792 } 2793 2794 static int 2795 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2796 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 2797 { 2798 struct e1000g *Adapter = arg; 2799 struct e1000_fc_info *fc = &Adapter->shared.fc; 2800 int err = 0; 2801 link_flowctrl_t flowctrl; 2802 uint64_t tmp = 0; 2803 2804 if (pr_valsize == 0) 2805 return (EINVAL); 2806 2807 bzero(pr_val, pr_valsize); 2808 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 2809 return (e1000g_get_def_val(Adapter, pr_num, 2810 pr_valsize, pr_val)); 2811 } 2812 2813 switch (pr_num) { 2814 case MAC_PROP_DUPLEX: 2815 if (pr_valsize >= sizeof (link_duplex_t)) { 2816 bcopy(&Adapter->link_duplex, pr_val, 2817 sizeof (link_duplex_t)); 2818 } else 2819 err = EINVAL; 2820 break; 2821 case MAC_PROP_SPEED: 2822 if (pr_valsize >= sizeof (uint64_t)) { 2823 tmp = Adapter->link_speed * 1000000ull; 2824 bcopy(&tmp, pr_val, sizeof (tmp)); 2825 } else 2826 err = EINVAL; 2827 break; 2828 case MAC_PROP_AUTONEG: 2829 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 2830 break; 2831 case MAC_PROP_FLOWCTRL: 2832 if (pr_valsize >= sizeof (link_flowctrl_t)) { 2833 switch (fc->type) { 2834 case e1000_fc_none: 2835 flowctrl = LINK_FLOWCTRL_NONE; 2836 break; 2837 case e1000_fc_rx_pause: 2838 flowctrl = LINK_FLOWCTRL_RX; 2839 break; 2840 case e1000_fc_tx_pause: 2841 flowctrl = LINK_FLOWCTRL_TX; 2842 break; 2843 case e1000_fc_full: 2844 flowctrl = LINK_FLOWCTRL_BI; 2845 break; 2846 } 2847 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 2848 } else 2849 err = EINVAL; 2850 break; 2851 case MAC_PROP_ADV_1000FDX_CAP: 2852 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 2853 break; 2854 case MAC_PROP_EN_1000FDX_CAP: 2855 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 2856 break; 2857 case MAC_PROP_ADV_1000HDX_CAP: 2858 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 2859 break; 2860 case MAC_PROP_EN_1000HDX_CAP: 2861 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 2862 break; 2863 case MAC_PROP_ADV_100FDX_CAP: 2864 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 2865 break; 2866 case MAC_PROP_EN_100FDX_CAP: 2867 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 2868 break; 2869 case MAC_PROP_ADV_100HDX_CAP: 2870 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 2871 break; 2872 case MAC_PROP_EN_100HDX_CAP: 2873 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 2874 break; 2875 case MAC_PROP_ADV_10FDX_CAP: 2876 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 2877 break; 2878 case MAC_PROP_EN_10FDX_CAP: 2879 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 2880 break; 2881 case MAC_PROP_ADV_10HDX_CAP: 2882 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 2883 break; 2884 case MAC_PROP_EN_10HDX_CAP: 2885 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 2886 break; 2887 case MAC_PROP_ADV_100T4_CAP: 2888 case MAC_PROP_EN_100T4_CAP: 2889 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 2890 break; 2891 case MAC_PROP_PRIVATE: 2892 err = e1000g_get_priv_prop(Adapter, pr_name, 2893 pr_flags, pr_valsize, pr_val); 2894 break; 2895 default: 2896 err = ENOTSUP; 2897 break; 2898 } 2899 return (err); 2900 } 2901 2902 /* ARGSUSED2 */ 2903 static int 2904 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 2905 uint_t pr_valsize, const void *pr_val) 2906 { 2907 int err = 0; 2908 long result; 2909 struct e1000_hw *hw = &Adapter->shared; 2910 2911 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 2912 if (pr_val == NULL) { 2913 err = EINVAL; 2914 return (err); 2915 } 2916 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2917 if (result < MIN_TX_BCOPY_THRESHOLD || 2918 result > MAX_TX_BCOPY_THRESHOLD) 2919 err = EINVAL; 2920 else { 2921 Adapter->tx_bcopy_thresh = (uint32_t)result; 2922 } 2923 return (err); 2924 } 2925 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 2926 if (pr_val == NULL) { 2927 err = EINVAL; 2928 return (err); 2929 } 2930 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2931 if (result < 0 || result > 1) 2932 err = EINVAL; 2933 else { 2934 Adapter->tx_intr_enable = (result == 1) ? 2935 B_TRUE: B_FALSE; 2936 if (Adapter->tx_intr_enable) 2937 e1000g_mask_tx_interrupt(Adapter); 2938 else 2939 e1000g_clear_tx_interrupt(Adapter); 2940 if (e1000g_check_acc_handle( 2941 Adapter->osdep.reg_handle) != DDI_FM_OK) 2942 ddi_fm_service_impact(Adapter->dip, 2943 DDI_SERVICE_DEGRADED); 2944 } 2945 return (err); 2946 } 2947 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 2948 if (pr_val == NULL) { 2949 err = EINVAL; 2950 return (err); 2951 } 2952 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2953 if (result < MIN_TX_INTR_DELAY || 2954 result > MAX_TX_INTR_DELAY) 2955 err = EINVAL; 2956 else { 2957 Adapter->tx_intr_delay = (uint32_t)result; 2958 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 2959 if (e1000g_check_acc_handle( 2960 Adapter->osdep.reg_handle) != DDI_FM_OK) 2961 ddi_fm_service_impact(Adapter->dip, 2962 DDI_SERVICE_DEGRADED); 2963 } 2964 return (err); 2965 } 2966 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 2967 if (pr_val == NULL) { 2968 err = EINVAL; 2969 return (err); 2970 } 2971 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2972 if (result < MIN_TX_INTR_ABS_DELAY || 2973 result > MAX_TX_INTR_ABS_DELAY) 2974 err = EINVAL; 2975 else { 2976 Adapter->tx_intr_abs_delay = (uint32_t)result; 2977 E1000_WRITE_REG(hw, E1000_TADV, 2978 Adapter->tx_intr_abs_delay); 2979 if (e1000g_check_acc_handle( 2980 Adapter->osdep.reg_handle) != DDI_FM_OK) 2981 ddi_fm_service_impact(Adapter->dip, 2982 DDI_SERVICE_DEGRADED); 2983 } 2984 return (err); 2985 } 2986 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 2987 if (pr_val == NULL) { 2988 err = EINVAL; 2989 return (err); 2990 } 2991 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2992 if (result < MIN_RX_BCOPY_THRESHOLD || 2993 result > MAX_RX_BCOPY_THRESHOLD) 2994 err = EINVAL; 2995 else 2996 Adapter->rx_bcopy_thresh = (uint32_t)result; 2997 return (err); 2998 } 2999 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3000 if (pr_val == NULL) { 3001 err = EINVAL; 3002 return (err); 3003 } 3004 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3005 if (result < MIN_RX_LIMIT_ON_INTR || 3006 result > MAX_RX_LIMIT_ON_INTR) 3007 err = EINVAL; 3008 else 3009 Adapter->rx_limit_onintr = (uint32_t)result; 3010 return (err); 3011 } 3012 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3013 if (pr_val == NULL) { 3014 err = EINVAL; 3015 return (err); 3016 } 3017 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3018 if (result < MIN_RX_INTR_DELAY || 3019 result > MAX_RX_INTR_DELAY) 3020 err = EINVAL; 3021 else { 3022 Adapter->rx_intr_delay = (uint32_t)result; 3023 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3024 if (e1000g_check_acc_handle( 3025 Adapter->osdep.reg_handle) != DDI_FM_OK) 3026 ddi_fm_service_impact(Adapter->dip, 3027 DDI_SERVICE_DEGRADED); 3028 } 3029 return (err); 3030 } 3031 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3032 if (pr_val == NULL) { 3033 err = EINVAL; 3034 return (err); 3035 } 3036 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3037 if (result < MIN_RX_INTR_ABS_DELAY || 3038 result > MAX_RX_INTR_ABS_DELAY) 3039 err = EINVAL; 3040 else { 3041 Adapter->rx_intr_abs_delay = (uint32_t)result; 3042 E1000_WRITE_REG(hw, E1000_RADV, 3043 Adapter->rx_intr_abs_delay); 3044 if (e1000g_check_acc_handle( 3045 Adapter->osdep.reg_handle) != DDI_FM_OK) 3046 ddi_fm_service_impact(Adapter->dip, 3047 DDI_SERVICE_DEGRADED); 3048 } 3049 return (err); 3050 } 3051 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3052 if (pr_val == NULL) { 3053 err = EINVAL; 3054 return (err); 3055 } 3056 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3057 if (result < MIN_INTR_THROTTLING || 3058 result > MAX_INTR_THROTTLING) 3059 err = EINVAL; 3060 else { 3061 if (hw->mac.type >= e1000_82540) { 3062 Adapter->intr_throttling_rate = 3063 (uint32_t)result; 3064 E1000_WRITE_REG(hw, E1000_ITR, 3065 Adapter->intr_throttling_rate); 3066 if (e1000g_check_acc_handle( 3067 Adapter->osdep.reg_handle) != DDI_FM_OK) 3068 ddi_fm_service_impact(Adapter->dip, 3069 DDI_SERVICE_DEGRADED); 3070 } else 3071 err = EINVAL; 3072 } 3073 return (err); 3074 } 3075 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3076 if (pr_val == NULL) { 3077 err = EINVAL; 3078 return (err); 3079 } 3080 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3081 if (result < 0 || result > 1) 3082 err = EINVAL; 3083 else { 3084 if (hw->mac.type >= e1000_82540) { 3085 Adapter->intr_adaptive = (result == 1) ? 3086 B_TRUE : B_FALSE; 3087 } else { 3088 err = EINVAL; 3089 } 3090 } 3091 return (err); 3092 } 3093 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3094 if (pr_val == NULL) { 3095 err = EINVAL; 3096 return (err); 3097 } 3098 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3099 if (result < MIN_TX_RECYCLE_THRESHOLD || 3100 result > MAX_TX_RECYCLE_THRESHOLD) 3101 err = EINVAL; 3102 else 3103 Adapter->tx_recycle_thresh = (uint32_t)result; 3104 return (err); 3105 } 3106 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3107 if (pr_val == NULL) { 3108 err = EINVAL; 3109 return (err); 3110 } 3111 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3112 if (result < MIN_TX_RECYCLE_NUM || 3113 result > MAX_TX_RECYCLE_NUM) 3114 err = EINVAL; 3115 else 3116 Adapter->tx_recycle_num = (uint32_t)result; 3117 return (err); 3118 } 3119 return (ENOTSUP); 3120 } 3121 3122 static int 3123 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3124 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 3125 { 3126 int err = ENOTSUP; 3127 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3128 int value; 3129 3130 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3131 if (is_default) 3132 goto done; 3133 value = Adapter->param_adv_pause; 3134 err = 0; 3135 goto done; 3136 } 3137 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3138 if (is_default) 3139 goto done; 3140 value = Adapter->param_adv_asym_pause; 3141 err = 0; 3142 goto done; 3143 } 3144 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3145 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3146 Adapter->tx_bcopy_thresh); 3147 err = 0; 3148 goto done; 3149 } 3150 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3151 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3152 Adapter->tx_intr_enable); 3153 err = 0; 3154 goto done; 3155 } 3156 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3157 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3158 Adapter->tx_intr_delay); 3159 err = 0; 3160 goto done; 3161 } 3162 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3163 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3164 Adapter->tx_intr_abs_delay); 3165 err = 0; 3166 goto done; 3167 } 3168 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3169 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3170 Adapter->rx_bcopy_thresh); 3171 err = 0; 3172 goto done; 3173 } 3174 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3175 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3176 Adapter->rx_limit_onintr); 3177 err = 0; 3178 goto done; 3179 } 3180 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3181 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3182 Adapter->rx_intr_delay); 3183 err = 0; 3184 goto done; 3185 } 3186 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3187 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3188 Adapter->rx_intr_abs_delay); 3189 err = 0; 3190 goto done; 3191 } 3192 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3193 value = (is_default ? DEFAULT_INTR_THROTTLING : 3194 Adapter->intr_throttling_rate); 3195 err = 0; 3196 goto done; 3197 } 3198 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3199 value = (is_default ? 1 : Adapter->intr_adaptive); 3200 err = 0; 3201 goto done; 3202 } 3203 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3204 value = (is_default ? DEFAULT_TX_RECYCLE_THRESHOLD : 3205 Adapter->tx_recycle_thresh); 3206 err = 0; 3207 goto done; 3208 } 3209 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3210 value = (is_default ? DEFAULT_TX_RECYCLE_NUM : 3211 Adapter->tx_recycle_num); 3212 err = 0; 3213 goto done; 3214 } 3215 done: 3216 if (err == 0) { 3217 (void) snprintf(pr_val, pr_valsize, "%d", value); 3218 } 3219 return (err); 3220 } 3221 3222 /* 3223 * e1000g_get_conf - get configurations set in e1000g.conf 3224 * This routine gets user-configured values out of the configuration 3225 * file e1000g.conf. 3226 * 3227 * For each configurable value, there is a minimum, a maximum, and a 3228 * default. 3229 * If user does not configure a value, use the default. 3230 * If user configures below the minimum, use the minumum. 3231 * If user configures above the maximum, use the maxumum. 3232 */ 3233 static void 3234 e1000g_get_conf(struct e1000g *Adapter) 3235 { 3236 struct e1000_hw *hw = &Adapter->shared; 3237 boolean_t tbi_compatibility = B_FALSE; 3238 3239 /* 3240 * get each configurable property from e1000g.conf 3241 */ 3242 3243 /* 3244 * NumTxDescriptors 3245 */ 3246 Adapter->tx_desc_num = 3247 e1000g_get_prop(Adapter, "NumTxDescriptors", 3248 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3249 DEFAULT_NUM_TX_DESCRIPTOR); 3250 3251 /* 3252 * NumRxDescriptors 3253 */ 3254 Adapter->rx_desc_num = 3255 e1000g_get_prop(Adapter, "NumRxDescriptors", 3256 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3257 DEFAULT_NUM_RX_DESCRIPTOR); 3258 3259 /* 3260 * NumRxFreeList 3261 */ 3262 Adapter->rx_freelist_num = 3263 e1000g_get_prop(Adapter, "NumRxFreeList", 3264 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3265 DEFAULT_NUM_RX_FREELIST); 3266 3267 /* 3268 * NumTxPacketList 3269 */ 3270 Adapter->tx_freelist_num = 3271 e1000g_get_prop(Adapter, "NumTxPacketList", 3272 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3273 DEFAULT_NUM_TX_FREELIST); 3274 3275 /* 3276 * FlowControl 3277 */ 3278 hw->fc.send_xon = B_TRUE; 3279 hw->fc.type = 3280 e1000g_get_prop(Adapter, "FlowControl", 3281 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3282 /* 4 is the setting that says "let the eeprom decide" */ 3283 if (hw->fc.type == 4) 3284 hw->fc.type = e1000_fc_default; 3285 3286 /* 3287 * Max Num Receive Packets on Interrupt 3288 */ 3289 Adapter->rx_limit_onintr = 3290 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3291 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3292 DEFAULT_RX_LIMIT_ON_INTR); 3293 3294 /* 3295 * PHY master slave setting 3296 */ 3297 hw->phy.ms_type = 3298 e1000g_get_prop(Adapter, "SetMasterSlave", 3299 e1000_ms_hw_default, e1000_ms_auto, 3300 e1000_ms_hw_default); 3301 3302 /* 3303 * Parameter which controls TBI mode workaround, which is only 3304 * needed on certain switches such as Cisco 6500/Foundry 3305 */ 3306 tbi_compatibility = 3307 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3308 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3309 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3310 3311 /* 3312 * MSI Enable 3313 */ 3314 Adapter->msi_enable = 3315 e1000g_get_prop(Adapter, "MSIEnable", 3316 0, 1, DEFAULT_MSI_ENABLE); 3317 3318 /* 3319 * Interrupt Throttling Rate 3320 */ 3321 Adapter->intr_throttling_rate = 3322 e1000g_get_prop(Adapter, "intr_throttling_rate", 3323 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3324 DEFAULT_INTR_THROTTLING); 3325 3326 /* 3327 * Adaptive Interrupt Blanking Enable/Disable 3328 * It is enabled by default 3329 */ 3330 Adapter->intr_adaptive = 3331 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3332 B_TRUE : B_FALSE; 3333 3334 /* 3335 * Tx recycle threshold 3336 */ 3337 Adapter->tx_recycle_thresh = 3338 e1000g_get_prop(Adapter, "tx_recycle_thresh", 3339 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 3340 DEFAULT_TX_RECYCLE_THRESHOLD); 3341 3342 /* 3343 * Tx recycle descriptor number 3344 */ 3345 Adapter->tx_recycle_num = 3346 e1000g_get_prop(Adapter, "tx_recycle_num", 3347 MIN_TX_RECYCLE_NUM, MAX_TX_RECYCLE_NUM, 3348 DEFAULT_TX_RECYCLE_NUM); 3349 3350 /* 3351 * Hardware checksum enable/disable parameter 3352 */ 3353 Adapter->tx_hcksum_enable = 3354 e1000g_get_prop(Adapter, "tx_hcksum_enable", 3355 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3356 /* 3357 * Checksum on/off selection via global parameters. 3358 * 3359 * If the chip is flagged as not capable of (correctly) 3360 * handling checksumming, we don't enable it on either 3361 * Rx or Tx side. Otherwise, we take this chip's settings 3362 * from the patchable global defaults. 3363 * 3364 * We advertise our capabilities only if TX offload is 3365 * enabled. On receive, the stack will accept checksummed 3366 * packets anyway, even if we haven't said we can deliver 3367 * them. 3368 */ 3369 switch (hw->mac.type) { 3370 case e1000_82540: 3371 case e1000_82544: 3372 case e1000_82545: 3373 case e1000_82545_rev_3: 3374 case e1000_82546: 3375 case e1000_82546_rev_3: 3376 case e1000_82571: 3377 case e1000_82572: 3378 case e1000_82573: 3379 case e1000_80003es2lan: 3380 break; 3381 /* 3382 * For the following Intel PRO/1000 chipsets, we have not 3383 * tested the hardware checksum offload capability, so we 3384 * disable the capability for them. 3385 * e1000_82542, 3386 * e1000_82543, 3387 * e1000_82541, 3388 * e1000_82541_rev_2, 3389 * e1000_82547, 3390 * e1000_82547_rev_2, 3391 */ 3392 default: 3393 Adapter->tx_hcksum_enable = B_FALSE; 3394 } 3395 3396 /* 3397 * Large Send Offloading(LSO) Enable/Disable 3398 * If the tx hardware checksum is not enabled, LSO should be 3399 * disabled. 3400 */ 3401 Adapter->lso_enable = 3402 e1000g_get_prop(Adapter, "lso_enable", 3403 0, 1, DEFAULT_LSO_ENABLE); 3404 3405 switch (hw->mac.type) { 3406 case e1000_82546: 3407 case e1000_82546_rev_3: 3408 if (Adapter->lso_enable) 3409 Adapter->lso_premature_issue = B_TRUE; 3410 /* FALLTHRU */ 3411 case e1000_82571: 3412 case e1000_82572: 3413 case e1000_82573: 3414 break; 3415 default: 3416 Adapter->lso_enable = B_FALSE; 3417 } 3418 3419 if (!Adapter->tx_hcksum_enable) { 3420 Adapter->lso_premature_issue = B_FALSE; 3421 Adapter->lso_enable = B_FALSE; 3422 } 3423 } 3424 3425 /* 3426 * e1000g_get_prop - routine to read properties 3427 * 3428 * Get a user-configure property value out of the configuration 3429 * file e1000g.conf. 3430 * 3431 * Caller provides name of the property, a default value, a minimum 3432 * value, and a maximum value. 3433 * 3434 * Return configured value of the property, with default, minimum and 3435 * maximum properly applied. 3436 */ 3437 static int 3438 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3439 char *propname, /* name of the property */ 3440 int minval, /* minimum acceptable value */ 3441 int maxval, /* maximim acceptable value */ 3442 int defval) /* default value */ 3443 { 3444 int propval; /* value returned for requested property */ 3445 int *props; /* point to array of properties returned */ 3446 uint_t nprops; /* number of property value returned */ 3447 3448 /* 3449 * get the array of properties from the config file 3450 */ 3451 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3452 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3453 /* got some properties, test if we got enough */ 3454 if (Adapter->instance < nprops) { 3455 propval = props[Adapter->instance]; 3456 } else { 3457 /* not enough properties configured */ 3458 propval = defval; 3459 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3460 "Not Enough %s values found in e1000g.conf" 3461 " - set to %d\n", 3462 propname, propval); 3463 } 3464 3465 /* free memory allocated for properties */ 3466 ddi_prop_free(props); 3467 3468 } else { 3469 propval = defval; 3470 } 3471 3472 /* 3473 * enforce limits 3474 */ 3475 if (propval > maxval) { 3476 propval = maxval; 3477 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3478 "Too High %s value in e1000g.conf - set to %d\n", 3479 propname, propval); 3480 } 3481 3482 if (propval < minval) { 3483 propval = minval; 3484 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3485 "Too Low %s value in e1000g.conf - set to %d\n", 3486 propname, propval); 3487 } 3488 3489 return (propval); 3490 } 3491 3492 static boolean_t 3493 e1000g_link_check(struct e1000g *Adapter) 3494 { 3495 uint16_t speed, duplex, phydata; 3496 boolean_t link_changed = B_FALSE; 3497 struct e1000_hw *hw; 3498 uint32_t reg_tarc; 3499 3500 hw = &Adapter->shared; 3501 3502 if (e1000g_link_up(Adapter)) { 3503 /* 3504 * The Link is up, check whether it was marked as down earlier 3505 */ 3506 if (Adapter->link_state != LINK_STATE_UP) { 3507 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3508 Adapter->link_speed = speed; 3509 Adapter->link_duplex = duplex; 3510 Adapter->link_state = LINK_STATE_UP; 3511 link_changed = B_TRUE; 3512 3513 Adapter->tx_link_down_timeout = 0; 3514 3515 if ((hw->mac.type == e1000_82571) || 3516 (hw->mac.type == e1000_82572)) { 3517 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3518 if (speed == SPEED_1000) 3519 reg_tarc |= (1 << 21); 3520 else 3521 reg_tarc &= ~(1 << 21); 3522 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3523 } 3524 } 3525 Adapter->smartspeed = 0; 3526 } else { 3527 if (Adapter->link_state != LINK_STATE_DOWN) { 3528 Adapter->link_speed = 0; 3529 Adapter->link_duplex = 0; 3530 Adapter->link_state = LINK_STATE_DOWN; 3531 link_changed = B_TRUE; 3532 3533 /* 3534 * SmartSpeed workaround for Tabor/TanaX, When the 3535 * driver loses link disable auto master/slave 3536 * resolution. 3537 */ 3538 if (hw->phy.type == e1000_phy_igp) { 3539 (void) e1000_read_phy_reg(hw, 3540 PHY_1000T_CTRL, &phydata); 3541 phydata |= CR_1000T_MS_ENABLE; 3542 (void) e1000_write_phy_reg(hw, 3543 PHY_1000T_CTRL, phydata); 3544 } 3545 } else { 3546 e1000g_smartspeed(Adapter); 3547 } 3548 3549 if (Adapter->chip_state == E1000G_START) { 3550 if (Adapter->tx_link_down_timeout < 3551 MAX_TX_LINK_DOWN_TIMEOUT) { 3552 Adapter->tx_link_down_timeout++; 3553 } else if (Adapter->tx_link_down_timeout == 3554 MAX_TX_LINK_DOWN_TIMEOUT) { 3555 e1000g_tx_clean(Adapter); 3556 Adapter->tx_link_down_timeout++; 3557 } 3558 } 3559 } 3560 3561 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3562 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3563 3564 return (link_changed); 3565 } 3566 3567 /* 3568 * e1000g_reset_link - Using the link properties to setup the link 3569 */ 3570 int 3571 e1000g_reset_link(struct e1000g *Adapter) 3572 { 3573 struct e1000_mac_info *mac; 3574 struct e1000_phy_info *phy; 3575 boolean_t invalid; 3576 3577 mac = &Adapter->shared.mac; 3578 phy = &Adapter->shared.phy; 3579 invalid = B_FALSE; 3580 3581 if (Adapter->param_adv_autoneg == 1) { 3582 mac->autoneg = B_TRUE; 3583 phy->autoneg_advertised = 0; 3584 3585 /* 3586 * 1000hdx is not supported for autonegotiation 3587 */ 3588 if (Adapter->param_adv_1000fdx == 1) 3589 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3590 3591 if (Adapter->param_adv_100fdx == 1) 3592 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3593 3594 if (Adapter->param_adv_100hdx == 1) 3595 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3596 3597 if (Adapter->param_adv_10fdx == 1) 3598 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3599 3600 if (Adapter->param_adv_10hdx == 1) 3601 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3602 3603 if (phy->autoneg_advertised == 0) 3604 invalid = B_TRUE; 3605 } else { 3606 mac->autoneg = B_FALSE; 3607 3608 /* 3609 * 1000fdx and 1000hdx are not supported for forced link 3610 */ 3611 if (Adapter->param_adv_100fdx == 1) 3612 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3613 else if (Adapter->param_adv_100hdx == 1) 3614 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3615 else if (Adapter->param_adv_10fdx == 1) 3616 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3617 else if (Adapter->param_adv_10hdx == 1) 3618 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3619 else 3620 invalid = B_TRUE; 3621 3622 } 3623 3624 if (invalid) { 3625 e1000g_log(Adapter, CE_WARN, 3626 "Invalid link sets. Setup link to" 3627 "support autonegotiation with all link capabilities."); 3628 mac->autoneg = B_TRUE; 3629 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3630 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3631 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3632 } 3633 3634 return (e1000_setup_link(&Adapter->shared)); 3635 } 3636 3637 static void 3638 e1000g_local_timer(void *ws) 3639 { 3640 struct e1000g *Adapter = (struct e1000g *)ws; 3641 struct e1000_hw *hw; 3642 e1000g_ether_addr_t ether_addr; 3643 boolean_t link_changed; 3644 3645 hw = &Adapter->shared; 3646 3647 if (Adapter->chip_state == E1000G_ERROR) { 3648 Adapter->reset_count++; 3649 if (e1000g_global_reset(Adapter)) 3650 ddi_fm_service_impact(Adapter->dip, 3651 DDI_SERVICE_RESTORED); 3652 else 3653 ddi_fm_service_impact(Adapter->dip, 3654 DDI_SERVICE_LOST); 3655 return; 3656 } 3657 3658 if (e1000g_stall_check(Adapter)) { 3659 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3660 "Tx stall detected. Activate automatic recovery.\n"); 3661 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 3662 Adapter->reset_count++; 3663 if (e1000g_reset(Adapter)) 3664 ddi_fm_service_impact(Adapter->dip, 3665 DDI_SERVICE_RESTORED); 3666 else 3667 ddi_fm_service_impact(Adapter->dip, 3668 DDI_SERVICE_LOST); 3669 return; 3670 } 3671 3672 link_changed = B_FALSE; 3673 rw_enter(&Adapter->chip_lock, RW_READER); 3674 if (Adapter->link_complete) 3675 link_changed = e1000g_link_check(Adapter); 3676 rw_exit(&Adapter->chip_lock); 3677 3678 if (link_changed) 3679 mac_link_update(Adapter->mh, Adapter->link_state); 3680 3681 /* 3682 * Workaround for esb2. Data stuck in fifo on a link 3683 * down event. Reset the adapter to recover it. 3684 */ 3685 if (Adapter->esb2_workaround) { 3686 Adapter->esb2_workaround = B_FALSE; 3687 (void) e1000g_reset(Adapter); 3688 } 3689 3690 /* 3691 * With 82571 controllers, any locally administered address will 3692 * be overwritten when there is a reset on the other port. 3693 * Detect this circumstance and correct it. 3694 */ 3695 if ((hw->mac.type == e1000_82571) && 3696 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 3697 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 3698 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 3699 3700 ether_addr.reg.low = ntohl(ether_addr.reg.low); 3701 ether_addr.reg.high = ntohl(ether_addr.reg.high); 3702 3703 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 3704 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 3705 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 3706 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 3707 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 3708 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 3709 e1000_rar_set(hw, hw->mac.addr, 0); 3710 } 3711 } 3712 3713 /* 3714 * Long TTL workaround for 82541/82547 3715 */ 3716 (void) e1000_igp_ttl_workaround_82547(hw); 3717 3718 /* 3719 * Check for Adaptive IFS settings If there are lots of collisions 3720 * change the value in steps... 3721 * These properties should only be set for 10/100 3722 */ 3723 if ((hw->phy.media_type == e1000_media_type_copper) && 3724 ((Adapter->link_speed == SPEED_100) || 3725 (Adapter->link_speed == SPEED_10))) { 3726 e1000_update_adaptive(hw); 3727 } 3728 /* 3729 * Set Timer Interrupts 3730 */ 3731 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 3732 3733 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3734 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3735 3736 restart_watchdog_timer(Adapter); 3737 } 3738 3739 /* 3740 * The function e1000g_link_timer() is called when the timer for link setup 3741 * is expired, which indicates the completion of the link setup. The link 3742 * state will not be updated until the link setup is completed. And the 3743 * link state will not be sent to the upper layer through mac_link_update() 3744 * in this function. It will be updated in the local timer routine or the 3745 * interrupt service routine after the interface is started (plumbed). 3746 */ 3747 static void 3748 e1000g_link_timer(void *arg) 3749 { 3750 struct e1000g *Adapter = (struct e1000g *)arg; 3751 3752 mutex_enter(&Adapter->link_lock); 3753 Adapter->link_complete = B_TRUE; 3754 Adapter->link_tid = 0; 3755 mutex_exit(&Adapter->link_lock); 3756 } 3757 3758 /* 3759 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 3760 * 3761 * This function read the forced speed and duplex for 10/100 Mbps speeds 3762 * and also for 1000 Mbps speeds from the e1000g.conf file 3763 */ 3764 static void 3765 e1000g_force_speed_duplex(struct e1000g *Adapter) 3766 { 3767 int forced; 3768 struct e1000_mac_info *mac = &Adapter->shared.mac; 3769 struct e1000_phy_info *phy = &Adapter->shared.phy; 3770 3771 /* 3772 * get value out of config file 3773 */ 3774 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 3775 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 3776 3777 switch (forced) { 3778 case GDIAG_10_HALF: 3779 /* 3780 * Disable Auto Negotiation 3781 */ 3782 mac->autoneg = B_FALSE; 3783 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3784 break; 3785 case GDIAG_10_FULL: 3786 /* 3787 * Disable Auto Negotiation 3788 */ 3789 mac->autoneg = B_FALSE; 3790 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3791 break; 3792 case GDIAG_100_HALF: 3793 /* 3794 * Disable Auto Negotiation 3795 */ 3796 mac->autoneg = B_FALSE; 3797 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3798 break; 3799 case GDIAG_100_FULL: 3800 /* 3801 * Disable Auto Negotiation 3802 */ 3803 mac->autoneg = B_FALSE; 3804 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3805 break; 3806 case GDIAG_1000_FULL: 3807 /* 3808 * The gigabit spec requires autonegotiation. Therefore, 3809 * when the user wants to force the speed to 1000Mbps, we 3810 * enable AutoNeg, but only allow the harware to advertise 3811 * 1000Mbps. This is different from 10/100 operation, where 3812 * we are allowed to link without any negotiation. 3813 */ 3814 mac->autoneg = B_TRUE; 3815 phy->autoneg_advertised = ADVERTISE_1000_FULL; 3816 break; 3817 default: /* obey the setting of AutoNegAdvertised */ 3818 mac->autoneg = B_TRUE; 3819 phy->autoneg_advertised = 3820 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 3821 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 3822 AUTONEG_ADVERTISE_SPEED_DEFAULT); 3823 break; 3824 } /* switch */ 3825 } 3826 3827 /* 3828 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 3829 * 3830 * This function reads MaxFrameSize from e1000g.conf 3831 */ 3832 static void 3833 e1000g_get_max_frame_size(struct e1000g *Adapter) 3834 { 3835 int max_frame; 3836 struct e1000_mac_info *mac = &Adapter->shared.mac; 3837 struct e1000_phy_info *phy = &Adapter->shared.phy; 3838 3839 /* 3840 * get value out of config file 3841 */ 3842 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 3843 3844 switch (max_frame) { 3845 case 0: 3846 Adapter->default_mtu = ETHERMTU; 3847 break; 3848 /* 3849 * To avoid excessive memory allocation for rx buffers, 3850 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 3851 */ 3852 case 1: 3853 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 3854 sizeof (struct ether_vlan_header) - ETHERFCSL - 3855 E1000G_IPALIGNPRESERVEROOM; 3856 break; 3857 case 2: 3858 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 3859 sizeof (struct ether_vlan_header) - ETHERFCSL - 3860 E1000G_IPALIGNPRESERVEROOM; 3861 break; 3862 case 3: 3863 if (mac->type >= e1000_82571) 3864 Adapter->default_mtu = MAXIMUM_MTU; 3865 else 3866 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 3867 sizeof (struct ether_vlan_header) - ETHERFCSL - 3868 E1000G_IPALIGNPRESERVEROOM; 3869 break; 3870 default: 3871 Adapter->default_mtu = ETHERMTU; 3872 break; 3873 } /* switch */ 3874 3875 Adapter->max_frame_size = Adapter->default_mtu + 3876 sizeof (struct ether_vlan_header) + ETHERFCSL; 3877 3878 /* ich8 does not do jumbo frames */ 3879 if (mac->type == e1000_ich8lan) { 3880 Adapter->max_frame_size = ETHERMTU + 3881 sizeof (struct ether_vlan_header) + ETHERFCSL; 3882 } 3883 3884 /* ich9 does not do jumbo frames on one phy type */ 3885 if ((mac->type == e1000_ich9lan) && 3886 (phy->type == e1000_phy_ife)) { 3887 Adapter->max_frame_size = ETHERMTU + 3888 sizeof (struct ether_vlan_header) + ETHERFCSL; 3889 } 3890 } 3891 3892 static void 3893 arm_watchdog_timer(struct e1000g *Adapter) 3894 { 3895 Adapter->watchdog_tid = 3896 timeout(e1000g_local_timer, 3897 (void *)Adapter, 1 * drv_usectohz(1000000)); 3898 } 3899 #pragma inline(arm_watchdog_timer) 3900 3901 static void 3902 enable_watchdog_timer(struct e1000g *Adapter) 3903 { 3904 mutex_enter(&Adapter->watchdog_lock); 3905 3906 if (!Adapter->watchdog_timer_enabled) { 3907 Adapter->watchdog_timer_enabled = B_TRUE; 3908 Adapter->watchdog_timer_started = B_TRUE; 3909 arm_watchdog_timer(Adapter); 3910 } 3911 3912 mutex_exit(&Adapter->watchdog_lock); 3913 } 3914 3915 static void 3916 disable_watchdog_timer(struct e1000g *Adapter) 3917 { 3918 timeout_id_t tid; 3919 3920 mutex_enter(&Adapter->watchdog_lock); 3921 3922 Adapter->watchdog_timer_enabled = B_FALSE; 3923 Adapter->watchdog_timer_started = B_FALSE; 3924 tid = Adapter->watchdog_tid; 3925 Adapter->watchdog_tid = 0; 3926 3927 mutex_exit(&Adapter->watchdog_lock); 3928 3929 if (tid != 0) 3930 (void) untimeout(tid); 3931 } 3932 3933 static void 3934 start_watchdog_timer(struct e1000g *Adapter) 3935 { 3936 mutex_enter(&Adapter->watchdog_lock); 3937 3938 if (Adapter->watchdog_timer_enabled) { 3939 if (!Adapter->watchdog_timer_started) { 3940 Adapter->watchdog_timer_started = B_TRUE; 3941 arm_watchdog_timer(Adapter); 3942 } 3943 } 3944 3945 mutex_exit(&Adapter->watchdog_lock); 3946 } 3947 3948 static void 3949 restart_watchdog_timer(struct e1000g *Adapter) 3950 { 3951 mutex_enter(&Adapter->watchdog_lock); 3952 3953 if (Adapter->watchdog_timer_started) 3954 arm_watchdog_timer(Adapter); 3955 3956 mutex_exit(&Adapter->watchdog_lock); 3957 } 3958 3959 static void 3960 stop_watchdog_timer(struct e1000g *Adapter) 3961 { 3962 timeout_id_t tid; 3963 3964 mutex_enter(&Adapter->watchdog_lock); 3965 3966 Adapter->watchdog_timer_started = B_FALSE; 3967 tid = Adapter->watchdog_tid; 3968 Adapter->watchdog_tid = 0; 3969 3970 mutex_exit(&Adapter->watchdog_lock); 3971 3972 if (tid != 0) 3973 (void) untimeout(tid); 3974 } 3975 3976 static void 3977 stop_link_timer(struct e1000g *Adapter) 3978 { 3979 timeout_id_t tid; 3980 3981 /* Disable the link timer */ 3982 mutex_enter(&Adapter->link_lock); 3983 3984 tid = Adapter->link_tid; 3985 Adapter->link_tid = 0; 3986 3987 mutex_exit(&Adapter->link_lock); 3988 3989 if (tid != 0) 3990 (void) untimeout(tid); 3991 } 3992 3993 static void 3994 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 3995 { 3996 timeout_id_t tid; 3997 3998 /* Disable the tx timer for 82547 chipset */ 3999 mutex_enter(&tx_ring->tx_lock); 4000 4001 tx_ring->timer_enable_82547 = B_FALSE; 4002 tid = tx_ring->timer_id_82547; 4003 tx_ring->timer_id_82547 = 0; 4004 4005 mutex_exit(&tx_ring->tx_lock); 4006 4007 if (tid != 0) 4008 (void) untimeout(tid); 4009 } 4010 4011 void 4012 e1000g_clear_interrupt(struct e1000g *Adapter) 4013 { 4014 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4015 0xffffffff & ~E1000_IMS_RXSEQ); 4016 } 4017 4018 void 4019 e1000g_mask_interrupt(struct e1000g *Adapter) 4020 { 4021 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4022 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4023 4024 if (Adapter->tx_intr_enable) 4025 e1000g_mask_tx_interrupt(Adapter); 4026 } 4027 4028 void 4029 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4030 { 4031 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4032 } 4033 4034 void 4035 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4036 { 4037 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4038 } 4039 4040 void 4041 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4042 { 4043 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4044 } 4045 4046 static void 4047 e1000g_smartspeed(struct e1000g *Adapter) 4048 { 4049 struct e1000_hw *hw = &Adapter->shared; 4050 uint16_t phy_status; 4051 uint16_t phy_ctrl; 4052 4053 /* 4054 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4055 * advertising 1000Full, we don't even use the workaround 4056 */ 4057 if ((hw->phy.type != e1000_phy_igp) || 4058 !hw->mac.autoneg || 4059 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4060 return; 4061 4062 /* 4063 * True if this is the first call of this function or after every 4064 * 30 seconds of not having link 4065 */ 4066 if (Adapter->smartspeed == 0) { 4067 /* 4068 * If Master/Slave config fault is asserted twice, we 4069 * assume back-to-back 4070 */ 4071 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4072 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4073 return; 4074 4075 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4076 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4077 return; 4078 /* 4079 * We're assuming back-2-back because our status register 4080 * insists! there's a fault in the master/slave 4081 * relationship that was "negotiated" 4082 */ 4083 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4084 /* 4085 * Is the phy configured for manual configuration of 4086 * master/slave? 4087 */ 4088 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4089 /* 4090 * Yes. Then disable manual configuration (enable 4091 * auto configuration) of master/slave 4092 */ 4093 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4094 (void) e1000_write_phy_reg(hw, 4095 PHY_1000T_CTRL, phy_ctrl); 4096 /* 4097 * Effectively starting the clock 4098 */ 4099 Adapter->smartspeed++; 4100 /* 4101 * Restart autonegotiation 4102 */ 4103 if (!e1000_phy_setup_autoneg(hw) && 4104 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4105 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4106 MII_CR_RESTART_AUTO_NEG); 4107 (void) e1000_write_phy_reg(hw, 4108 PHY_CONTROL, phy_ctrl); 4109 } 4110 } 4111 return; 4112 /* 4113 * Has 6 seconds transpired still without link? Remember, 4114 * you should reset the smartspeed counter once you obtain 4115 * link 4116 */ 4117 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4118 /* 4119 * Yes. Remember, we did at the start determine that 4120 * there's a master/slave configuration fault, so we're 4121 * still assuming there's someone on the other end, but we 4122 * just haven't yet been able to talk to it. We then 4123 * re-enable auto configuration of master/slave to see if 4124 * we're running 2/3 pair cables. 4125 */ 4126 /* 4127 * If still no link, perhaps using 2/3 pair cable 4128 */ 4129 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4130 phy_ctrl |= CR_1000T_MS_ENABLE; 4131 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4132 /* 4133 * Restart autoneg with phy enabled for manual 4134 * configuration of master/slave 4135 */ 4136 if (!e1000_phy_setup_autoneg(hw) && 4137 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4138 phy_ctrl |= 4139 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4140 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4141 } 4142 /* 4143 * Hopefully, there are no more faults and we've obtained 4144 * link as a result. 4145 */ 4146 } 4147 /* 4148 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4149 * seconds) 4150 */ 4151 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4152 Adapter->smartspeed = 0; 4153 } 4154 4155 static boolean_t 4156 is_valid_mac_addr(uint8_t *mac_addr) 4157 { 4158 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4159 const uint8_t addr_test2[6] = 4160 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4161 4162 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4163 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4164 return (B_FALSE); 4165 4166 return (B_TRUE); 4167 } 4168 4169 /* 4170 * e1000g_stall_check - check for tx stall 4171 * 4172 * This function checks if the adapter is stalled (in transmit). 4173 * 4174 * It is called each time the watchdog timeout is invoked. 4175 * If the transmit descriptor reclaim continuously fails, 4176 * the watchdog value will increment by 1. If the watchdog 4177 * value exceeds the threshold, the adapter is assumed to 4178 * have stalled and need to be reset. 4179 */ 4180 static boolean_t 4181 e1000g_stall_check(struct e1000g *Adapter) 4182 { 4183 e1000g_tx_ring_t *tx_ring; 4184 4185 tx_ring = Adapter->tx_ring; 4186 4187 if (Adapter->link_state != LINK_STATE_UP) 4188 return (B_FALSE); 4189 4190 if (tx_ring->recycle_fail > 0) 4191 tx_ring->stall_watchdog++; 4192 else 4193 tx_ring->stall_watchdog = 0; 4194 4195 if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) 4196 return (B_FALSE); 4197 4198 tx_ring->stall_watchdog = 0; 4199 tx_ring->recycle_fail = 0; 4200 4201 return (B_TRUE); 4202 } 4203 4204 #ifdef E1000G_DEBUG 4205 static enum ioc_reply 4206 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4207 { 4208 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4209 e1000g_peekpoke_t *ppd; 4210 uint64_t mem_va; 4211 uint64_t maxoff; 4212 boolean_t peek; 4213 4214 switch (iocp->ioc_cmd) { 4215 4216 case E1000G_IOC_REG_PEEK: 4217 peek = B_TRUE; 4218 break; 4219 4220 case E1000G_IOC_REG_POKE: 4221 peek = B_FALSE; 4222 break; 4223 4224 deault: 4225 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4226 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4227 iocp->ioc_cmd); 4228 return (IOC_INVAL); 4229 } 4230 4231 /* 4232 * Validate format of ioctl 4233 */ 4234 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4235 return (IOC_INVAL); 4236 if (mp->b_cont == NULL) 4237 return (IOC_INVAL); 4238 4239 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4240 4241 /* 4242 * Validate request parameters 4243 */ 4244 switch (ppd->pp_acc_space) { 4245 4246 default: 4247 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4248 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4249 ppd->pp_acc_space); 4250 return (IOC_INVAL); 4251 4252 case E1000G_PP_SPACE_REG: 4253 /* 4254 * Memory-mapped I/O space 4255 */ 4256 ASSERT(ppd->pp_acc_size == 4); 4257 if (ppd->pp_acc_size != 4) 4258 return (IOC_INVAL); 4259 4260 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4261 return (IOC_INVAL); 4262 4263 mem_va = 0; 4264 maxoff = 0x10000; 4265 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4266 break; 4267 4268 case E1000G_PP_SPACE_E1000G: 4269 /* 4270 * E1000g data structure! 4271 */ 4272 mem_va = (uintptr_t)e1000gp; 4273 maxoff = sizeof (struct e1000g); 4274 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4275 break; 4276 4277 } 4278 4279 if (ppd->pp_acc_offset >= maxoff) 4280 return (IOC_INVAL); 4281 4282 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4283 return (IOC_INVAL); 4284 4285 /* 4286 * All OK - go! 4287 */ 4288 ppd->pp_acc_offset += mem_va; 4289 (*ppfn)(e1000gp, ppd); 4290 return (peek ? IOC_REPLY : IOC_ACK); 4291 } 4292 4293 static void 4294 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4295 { 4296 ddi_acc_handle_t handle; 4297 uint32_t *regaddr; 4298 4299 handle = e1000gp->osdep.reg_handle; 4300 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4301 (uintptr_t)ppd->pp_acc_offset); 4302 4303 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4304 } 4305 4306 static void 4307 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4308 { 4309 ddi_acc_handle_t handle; 4310 uint32_t *regaddr; 4311 uint32_t value; 4312 4313 handle = e1000gp->osdep.reg_handle; 4314 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4315 (uintptr_t)ppd->pp_acc_offset); 4316 value = (uint32_t)ppd->pp_acc_data; 4317 4318 ddi_put32(handle, regaddr, value); 4319 } 4320 4321 static void 4322 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4323 { 4324 uint64_t value; 4325 void *vaddr; 4326 4327 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4328 4329 switch (ppd->pp_acc_size) { 4330 case 1: 4331 value = *(uint8_t *)vaddr; 4332 break; 4333 4334 case 2: 4335 value = *(uint16_t *)vaddr; 4336 break; 4337 4338 case 4: 4339 value = *(uint32_t *)vaddr; 4340 break; 4341 4342 case 8: 4343 value = *(uint64_t *)vaddr; 4344 break; 4345 } 4346 4347 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4348 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4349 (void *)e1000gp, (void *)ppd, value, vaddr); 4350 4351 ppd->pp_acc_data = value; 4352 } 4353 4354 static void 4355 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4356 { 4357 uint64_t value; 4358 void *vaddr; 4359 4360 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4361 value = ppd->pp_acc_data; 4362 4363 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4364 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4365 (void *)e1000gp, (void *)ppd, value, vaddr); 4366 4367 switch (ppd->pp_acc_size) { 4368 case 1: 4369 *(uint8_t *)vaddr = (uint8_t)value; 4370 break; 4371 4372 case 2: 4373 *(uint16_t *)vaddr = (uint16_t)value; 4374 break; 4375 4376 case 4: 4377 *(uint32_t *)vaddr = (uint32_t)value; 4378 break; 4379 4380 case 8: 4381 *(uint64_t *)vaddr = (uint64_t)value; 4382 break; 4383 } 4384 } 4385 #endif 4386 4387 /* 4388 * Loopback Support 4389 */ 4390 static lb_property_t lb_normal = 4391 { normal, "normal", E1000G_LB_NONE }; 4392 static lb_property_t lb_external1000 = 4393 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4394 static lb_property_t lb_external100 = 4395 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4396 static lb_property_t lb_external10 = 4397 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4398 static lb_property_t lb_phy = 4399 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4400 4401 static enum ioc_reply 4402 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4403 { 4404 lb_info_sz_t *lbsp; 4405 lb_property_t *lbpp; 4406 struct e1000_hw *hw; 4407 uint32_t *lbmp; 4408 uint32_t size; 4409 uint32_t value; 4410 4411 hw = &Adapter->shared; 4412 4413 if (mp->b_cont == NULL) 4414 return (IOC_INVAL); 4415 4416 if (!e1000g_check_loopback_support(hw)) { 4417 e1000g_log(NULL, CE_WARN, 4418 "Loopback is not supported on e1000g%d", Adapter->instance); 4419 return (IOC_INVAL); 4420 } 4421 4422 switch (iocp->ioc_cmd) { 4423 default: 4424 return (IOC_INVAL); 4425 4426 case LB_GET_INFO_SIZE: 4427 size = sizeof (lb_info_sz_t); 4428 if (iocp->ioc_count != size) 4429 return (IOC_INVAL); 4430 4431 rw_enter(&Adapter->chip_lock, RW_WRITER); 4432 e1000g_get_phy_state(Adapter); 4433 4434 /* 4435 * Workaround for hardware faults. In order to get a stable 4436 * state of phy, we will wait for a specific interval and 4437 * try again. The time delay is an experiential value based 4438 * on our testing. 4439 */ 4440 msec_delay(100); 4441 e1000g_get_phy_state(Adapter); 4442 rw_exit(&Adapter->chip_lock); 4443 4444 value = sizeof (lb_normal); 4445 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4446 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4447 (hw->phy.media_type == e1000_media_type_fiber) || 4448 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4449 value += sizeof (lb_phy); 4450 switch (hw->mac.type) { 4451 case e1000_82571: 4452 case e1000_82572: 4453 case e1000_80003es2lan: 4454 value += sizeof (lb_external1000); 4455 break; 4456 } 4457 } 4458 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4459 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4460 value += sizeof (lb_external100); 4461 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4462 value += sizeof (lb_external10); 4463 4464 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 4465 *lbsp = value; 4466 break; 4467 4468 case LB_GET_INFO: 4469 value = sizeof (lb_normal); 4470 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4471 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4472 (hw->phy.media_type == e1000_media_type_fiber) || 4473 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4474 value += sizeof (lb_phy); 4475 switch (hw->mac.type) { 4476 case e1000_82571: 4477 case e1000_82572: 4478 case e1000_80003es2lan: 4479 value += sizeof (lb_external1000); 4480 break; 4481 } 4482 } 4483 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4484 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4485 value += sizeof (lb_external100); 4486 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4487 value += sizeof (lb_external10); 4488 4489 size = value; 4490 if (iocp->ioc_count != size) 4491 return (IOC_INVAL); 4492 4493 value = 0; 4494 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 4495 lbpp[value++] = lb_normal; 4496 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4497 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4498 (hw->phy.media_type == e1000_media_type_fiber) || 4499 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4500 lbpp[value++] = lb_phy; 4501 switch (hw->mac.type) { 4502 case e1000_82571: 4503 case e1000_82572: 4504 case e1000_80003es2lan: 4505 lbpp[value++] = lb_external1000; 4506 break; 4507 } 4508 } 4509 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4510 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4511 lbpp[value++] = lb_external100; 4512 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4513 lbpp[value++] = lb_external10; 4514 break; 4515 4516 case LB_GET_MODE: 4517 size = sizeof (uint32_t); 4518 if (iocp->ioc_count != size) 4519 return (IOC_INVAL); 4520 4521 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4522 *lbmp = Adapter->loopback_mode; 4523 break; 4524 4525 case LB_SET_MODE: 4526 size = 0; 4527 if (iocp->ioc_count != sizeof (uint32_t)) 4528 return (IOC_INVAL); 4529 4530 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4531 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4532 return (IOC_INVAL); 4533 break; 4534 } 4535 4536 iocp->ioc_count = size; 4537 iocp->ioc_error = 0; 4538 4539 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4540 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4541 return (IOC_INVAL); 4542 } 4543 4544 return (IOC_REPLY); 4545 } 4546 4547 static boolean_t 4548 e1000g_check_loopback_support(struct e1000_hw *hw) 4549 { 4550 switch (hw->mac.type) { 4551 case e1000_82540: 4552 case e1000_82545: 4553 case e1000_82545_rev_3: 4554 case e1000_82546: 4555 case e1000_82546_rev_3: 4556 case e1000_82541: 4557 case e1000_82541_rev_2: 4558 case e1000_82547: 4559 case e1000_82547_rev_2: 4560 case e1000_82571: 4561 case e1000_82572: 4562 case e1000_82573: 4563 case e1000_80003es2lan: 4564 return (B_TRUE); 4565 } 4566 return (B_FALSE); 4567 } 4568 4569 static boolean_t 4570 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 4571 { 4572 struct e1000_hw *hw; 4573 int i, times; 4574 boolean_t link_up; 4575 4576 if (mode == Adapter->loopback_mode) 4577 return (B_TRUE); 4578 4579 hw = &Adapter->shared; 4580 times = 0; 4581 4582 Adapter->loopback_mode = mode; 4583 4584 if (mode == E1000G_LB_NONE) { 4585 /* Reset the chip */ 4586 hw->phy.autoneg_wait_to_complete = B_TRUE; 4587 (void) e1000g_reset(Adapter); 4588 hw->phy.autoneg_wait_to_complete = B_FALSE; 4589 return (B_TRUE); 4590 } 4591 4592 again: 4593 4594 rw_enter(&Adapter->chip_lock, RW_WRITER); 4595 4596 switch (mode) { 4597 default: 4598 rw_exit(&Adapter->chip_lock); 4599 return (B_FALSE); 4600 4601 case E1000G_LB_EXTERNAL_1000: 4602 e1000g_set_external_loopback_1000(Adapter); 4603 break; 4604 4605 case E1000G_LB_EXTERNAL_100: 4606 e1000g_set_external_loopback_100(Adapter); 4607 break; 4608 4609 case E1000G_LB_EXTERNAL_10: 4610 e1000g_set_external_loopback_10(Adapter); 4611 break; 4612 4613 case E1000G_LB_INTERNAL_PHY: 4614 e1000g_set_internal_loopback(Adapter); 4615 break; 4616 } 4617 4618 times++; 4619 4620 rw_exit(&Adapter->chip_lock); 4621 4622 /* Wait for link up */ 4623 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 4624 msec_delay(100); 4625 4626 rw_enter(&Adapter->chip_lock, RW_WRITER); 4627 4628 link_up = e1000g_link_up(Adapter); 4629 4630 rw_exit(&Adapter->chip_lock); 4631 4632 if (!link_up) { 4633 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4634 "Failed to get the link up"); 4635 if (times < 2) { 4636 /* Reset the link */ 4637 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4638 "Reset the link ..."); 4639 (void) e1000g_reset(Adapter); 4640 goto again; 4641 } 4642 } 4643 4644 return (B_TRUE); 4645 } 4646 4647 /* 4648 * The following loopback settings are from Intel's technical 4649 * document - "How To Loopback". All the register settings and 4650 * time delay values are directly inherited from the document 4651 * without more explanations available. 4652 */ 4653 static void 4654 e1000g_set_internal_loopback(struct e1000g *Adapter) 4655 { 4656 struct e1000_hw *hw; 4657 uint32_t ctrl; 4658 uint32_t status; 4659 uint16_t phy_ctrl; 4660 uint32_t txcw; 4661 4662 hw = &Adapter->shared; 4663 4664 /* Disable Smart Power Down */ 4665 phy_spd_state(hw, B_FALSE); 4666 4667 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4668 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 4669 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 4670 4671 switch (hw->mac.type) { 4672 case e1000_82540: 4673 case e1000_82545: 4674 case e1000_82545_rev_3: 4675 case e1000_82546: 4676 case e1000_82546_rev_3: 4677 case e1000_82573: 4678 /* Auto-MDI/MDIX off */ 4679 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 4680 /* Reset PHY to update Auto-MDI/MDIX */ 4681 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4682 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 4683 /* Reset PHY to auto-neg off and force 1000 */ 4684 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4685 phy_ctrl | MII_CR_RESET); 4686 /* 4687 * Disable PHY receiver for 82540/545/546 and 82573 Family. 4688 * See comments above e1000g_set_internal_loopback() for the 4689 * background. 4690 */ 4691 (void) e1000_write_phy_reg(hw, 29, 0x001F); 4692 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 4693 (void) e1000_write_phy_reg(hw, 29, 0x001A); 4694 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 4695 break; 4696 case e1000_80003es2lan: 4697 /* Force Link Up */ 4698 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 4699 0x1CC); 4700 /* Sets PCS loopback at 1Gbs */ 4701 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 4702 0x1046); 4703 break; 4704 } 4705 4706 /* Set loopback */ 4707 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 4708 4709 msec_delay(250); 4710 4711 /* Now set up the MAC to the same speed/duplex as the PHY. */ 4712 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4713 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4714 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4715 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4716 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 4717 E1000_CTRL_FD); /* Force Duplex to FULL */ 4718 4719 switch (hw->mac.type) { 4720 case e1000_82540: 4721 case e1000_82545: 4722 case e1000_82545_rev_3: 4723 case e1000_82546: 4724 case e1000_82546_rev_3: 4725 /* 4726 * For some serdes we'll need to commit the writes now 4727 * so that the status is updated on link 4728 */ 4729 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 4730 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4731 msec_delay(100); 4732 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4733 } 4734 4735 if (hw->phy.media_type == e1000_media_type_copper) { 4736 /* Invert Loss of Signal */ 4737 ctrl |= E1000_CTRL_ILOS; 4738 } else { 4739 /* Set ILOS on fiber nic if half duplex is detected */ 4740 status = E1000_READ_REG(hw, E1000_STATUS); 4741 if ((status & E1000_STATUS_FD) == 0) 4742 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4743 } 4744 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4745 break; 4746 4747 case e1000_82571: 4748 case e1000_82572: 4749 /* 4750 * The fiber/SerDes versions of this adapter do not contain an 4751 * accessible PHY. Therefore, loopback beyond MAC must be done 4752 * using SerDes analog loopback. 4753 */ 4754 if (hw->phy.media_type != e1000_media_type_copper) { 4755 status = E1000_READ_REG(hw, E1000_STATUS); 4756 /* Set ILOS on fiber nic if half duplex is detected */ 4757 if (((status & E1000_STATUS_LU) == 0) || 4758 ((status & E1000_STATUS_FD) == 0) || 4759 (hw->phy.media_type == 4760 e1000_media_type_internal_serdes)) 4761 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4762 4763 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4764 txcw = E1000_READ_REG(hw, E1000_TXCW); 4765 txcw &= ~((uint32_t)1 << 31); 4766 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4767 4768 /* 4769 * Write 0x410 to Serdes Control register 4770 * to enable Serdes analog loopback 4771 */ 4772 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4773 msec_delay(10); 4774 } 4775 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4776 break; 4777 4778 case e1000_82573: 4779 ctrl |= E1000_CTRL_ILOS; 4780 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4781 break; 4782 } 4783 } 4784 4785 static void 4786 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 4787 { 4788 struct e1000_hw *hw; 4789 uint32_t rctl; 4790 uint32_t ctrl_ext; 4791 uint32_t ctrl; 4792 uint32_t status; 4793 uint32_t txcw; 4794 uint16_t phydata; 4795 4796 hw = &Adapter->shared; 4797 4798 /* Disable Smart Power Down */ 4799 phy_spd_state(hw, B_FALSE); 4800 4801 switch (hw->mac.type) { 4802 case e1000_82571: 4803 case e1000_82572: 4804 switch (hw->phy.media_type) { 4805 case e1000_media_type_copper: 4806 /* Force link up (Must be done before the PHY writes) */ 4807 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4808 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 4809 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4810 4811 rctl = E1000_READ_REG(hw, E1000_RCTL); 4812 rctl |= (E1000_RCTL_EN | 4813 E1000_RCTL_SBP | 4814 E1000_RCTL_UPE | 4815 E1000_RCTL_MPE | 4816 E1000_RCTL_LPE | 4817 E1000_RCTL_BAM); /* 0x803E */ 4818 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4819 4820 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4821 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 4822 E1000_CTRL_EXT_SDP6_DATA | 4823 E1000_CTRL_EXT_SDP7_DATA | 4824 E1000_CTRL_EXT_SDP4_DIR | 4825 E1000_CTRL_EXT_SDP6_DIR | 4826 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 4827 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4828 4829 /* 4830 * This sequence tunes the PHY's SDP and no customer 4831 * settable values. For background, see comments above 4832 * e1000g_set_internal_loopback(). 4833 */ 4834 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 4835 msec_delay(10); 4836 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 4837 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 4838 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 4839 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 4840 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 4841 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 4842 4843 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 4844 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 4845 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 4846 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 4847 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 4848 4849 msec_delay(50); 4850 break; 4851 case e1000_media_type_fiber: 4852 case e1000_media_type_internal_serdes: 4853 status = E1000_READ_REG(hw, E1000_STATUS); 4854 if (((status & E1000_STATUS_LU) == 0) || 4855 (hw->phy.media_type == 4856 e1000_media_type_internal_serdes)) { 4857 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4858 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4859 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4860 } 4861 4862 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4863 txcw = E1000_READ_REG(hw, E1000_TXCW); 4864 txcw &= ~((uint32_t)1 << 31); 4865 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4866 4867 /* 4868 * Write 0x410 to Serdes Control register 4869 * to enable Serdes analog loopback 4870 */ 4871 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4872 msec_delay(10); 4873 break; 4874 default: 4875 break; 4876 } 4877 break; 4878 case e1000_80003es2lan: 4879 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 4880 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 4881 phydata | (1 << 5)); 4882 Adapter->param_adv_autoneg = 1; 4883 Adapter->param_adv_1000fdx = 1; 4884 (void) e1000g_reset_link(Adapter); 4885 break; 4886 } 4887 } 4888 4889 static void 4890 e1000g_set_external_loopback_100(struct e1000g *Adapter) 4891 { 4892 struct e1000_hw *hw; 4893 uint32_t ctrl; 4894 uint16_t phy_ctrl; 4895 4896 hw = &Adapter->shared; 4897 4898 /* Disable Smart Power Down */ 4899 phy_spd_state(hw, B_FALSE); 4900 4901 phy_ctrl = (MII_CR_FULL_DUPLEX | 4902 MII_CR_SPEED_100); 4903 4904 /* Force 100/FD, reset PHY */ 4905 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4906 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 4907 msec_delay(10); 4908 4909 /* Force 100/FD */ 4910 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4911 phy_ctrl); /* 0x2100 */ 4912 msec_delay(10); 4913 4914 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4915 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4916 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4917 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4918 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4919 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4920 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 4921 E1000_CTRL_FD); /* Force Duplex to FULL */ 4922 4923 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4924 } 4925 4926 static void 4927 e1000g_set_external_loopback_10(struct e1000g *Adapter) 4928 { 4929 struct e1000_hw *hw; 4930 uint32_t ctrl; 4931 uint16_t phy_ctrl; 4932 4933 hw = &Adapter->shared; 4934 4935 /* Disable Smart Power Down */ 4936 phy_spd_state(hw, B_FALSE); 4937 4938 phy_ctrl = (MII_CR_FULL_DUPLEX | 4939 MII_CR_SPEED_10); 4940 4941 /* Force 10/FD, reset PHY */ 4942 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4943 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 4944 msec_delay(10); 4945 4946 /* Force 10/FD */ 4947 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4948 phy_ctrl); /* 0x0100 */ 4949 msec_delay(10); 4950 4951 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4952 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4953 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4954 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4955 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4956 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4957 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 4958 E1000_CTRL_FD); /* Force Duplex to FULL */ 4959 4960 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4961 } 4962 4963 #ifdef __sparc 4964 static boolean_t 4965 e1000g_find_mac_address(struct e1000g *Adapter) 4966 { 4967 struct e1000_hw *hw = &Adapter->shared; 4968 uchar_t *bytes; 4969 struct ether_addr sysaddr; 4970 uint_t nelts; 4971 int err; 4972 boolean_t found = B_FALSE; 4973 4974 /* 4975 * The "vendor's factory-set address" may already have 4976 * been extracted from the chip, but if the property 4977 * "local-mac-address" is set we use that instead. 4978 * 4979 * We check whether it looks like an array of 6 4980 * bytes (which it should, if OBP set it). If we can't 4981 * make sense of it this way, we'll ignore it. 4982 */ 4983 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4984 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 4985 if (err == DDI_PROP_SUCCESS) { 4986 if (nelts == ETHERADDRL) { 4987 while (nelts--) 4988 hw->mac.addr[nelts] = bytes[nelts]; 4989 found = B_TRUE; 4990 } 4991 ddi_prop_free(bytes); 4992 } 4993 4994 /* 4995 * Look up the OBP property "local-mac-address?". If the user has set 4996 * 'local-mac-address? = false', use "the system address" instead. 4997 */ 4998 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 4999 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5000 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5001 if (localetheraddr(NULL, &sysaddr) != 0) { 5002 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5003 found = B_TRUE; 5004 } 5005 } 5006 ddi_prop_free(bytes); 5007 } 5008 5009 /* 5010 * Finally(!), if there's a valid "mac-address" property (created 5011 * if we netbooted from this interface), we must use this instead 5012 * of any of the above to ensure that the NFS/install server doesn't 5013 * get confused by the address changing as Solaris takes over! 5014 */ 5015 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5016 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5017 if (err == DDI_PROP_SUCCESS) { 5018 if (nelts == ETHERADDRL) { 5019 while (nelts--) 5020 hw->mac.addr[nelts] = bytes[nelts]; 5021 found = B_TRUE; 5022 } 5023 ddi_prop_free(bytes); 5024 } 5025 5026 if (found) { 5027 bcopy(hw->mac.addr, hw->mac.perm_addr, 5028 ETHERADDRL); 5029 } 5030 5031 return (found); 5032 } 5033 #endif 5034 5035 static int 5036 e1000g_add_intrs(struct e1000g *Adapter) 5037 { 5038 dev_info_t *devinfo; 5039 int intr_types; 5040 int rc; 5041 5042 devinfo = Adapter->dip; 5043 5044 /* Get supported interrupt types */ 5045 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5046 5047 if (rc != DDI_SUCCESS) { 5048 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5049 "Get supported interrupt types failed: %d\n", rc); 5050 return (DDI_FAILURE); 5051 } 5052 5053 /* 5054 * Based on Intel Technical Advisory document (TA-160), there are some 5055 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5056 * that it supports MSI, but in fact has problems. 5057 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5058 * PCI/PCI-X NICs. 5059 */ 5060 if (Adapter->shared.mac.type < e1000_82571) 5061 Adapter->msi_enable = B_FALSE; 5062 5063 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5064 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5065 5066 if (rc != DDI_SUCCESS) { 5067 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5068 "Add MSI failed, trying Legacy interrupts\n"); 5069 } else { 5070 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5071 } 5072 } 5073 5074 if ((Adapter->intr_type == 0) && 5075 (intr_types & DDI_INTR_TYPE_FIXED)) { 5076 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5077 5078 if (rc != DDI_SUCCESS) { 5079 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5080 "Add Legacy interrupts failed\n"); 5081 return (DDI_FAILURE); 5082 } 5083 5084 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5085 } 5086 5087 if (Adapter->intr_type == 0) { 5088 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5089 "No interrupts registered\n"); 5090 return (DDI_FAILURE); 5091 } 5092 5093 return (DDI_SUCCESS); 5094 } 5095 5096 /* 5097 * e1000g_intr_add() handles MSI/Legacy interrupts 5098 */ 5099 static int 5100 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5101 { 5102 dev_info_t *devinfo; 5103 int count, avail, actual; 5104 int x, y, rc, inum = 0; 5105 int flag; 5106 ddi_intr_handler_t *intr_handler; 5107 5108 devinfo = Adapter->dip; 5109 5110 /* get number of interrupts */ 5111 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5112 if ((rc != DDI_SUCCESS) || (count == 0)) { 5113 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5114 "Get interrupt number failed. Return: %d, count: %d\n", 5115 rc, count); 5116 return (DDI_FAILURE); 5117 } 5118 5119 /* get number of available interrupts */ 5120 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5121 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5122 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5123 "Get interrupt available number failed. " 5124 "Return: %d, available: %d\n", rc, avail); 5125 return (DDI_FAILURE); 5126 } 5127 5128 if (avail < count) { 5129 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5130 "Interrupts count: %d, available: %d\n", 5131 count, avail); 5132 } 5133 5134 /* Allocate an array of interrupt handles */ 5135 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5136 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5137 5138 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5139 flag = DDI_INTR_ALLOC_NORMAL; 5140 5141 /* call ddi_intr_alloc() */ 5142 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5143 count, &actual, flag); 5144 5145 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5146 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5147 "Allocate interrupts failed: %d\n", rc); 5148 5149 kmem_free(Adapter->htable, Adapter->intr_size); 5150 return (DDI_FAILURE); 5151 } 5152 5153 if (actual < count) { 5154 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5155 "Interrupts requested: %d, received: %d\n", 5156 count, actual); 5157 } 5158 5159 Adapter->intr_cnt = actual; 5160 5161 /* Get priority for first msi, assume remaining are all the same */ 5162 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5163 5164 if (rc != DDI_SUCCESS) { 5165 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5166 "Get interrupt priority failed: %d\n", rc); 5167 5168 /* Free already allocated intr */ 5169 for (y = 0; y < actual; y++) 5170 (void) ddi_intr_free(Adapter->htable[y]); 5171 5172 kmem_free(Adapter->htable, Adapter->intr_size); 5173 return (DDI_FAILURE); 5174 } 5175 5176 /* 5177 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5178 * use the interrupt service routine e1000g_intr_pciexpress() 5179 * to avoid interrupt stealing when sharing interrupt with other 5180 * devices. 5181 */ 5182 if (Adapter->shared.mac.type < e1000_82571) 5183 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5184 else 5185 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5186 5187 /* Call ddi_intr_add_handler() */ 5188 for (x = 0; x < actual; x++) { 5189 rc = ddi_intr_add_handler(Adapter->htable[x], 5190 intr_handler, (caddr_t)Adapter, NULL); 5191 5192 if (rc != DDI_SUCCESS) { 5193 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5194 "Add interrupt handler failed: %d\n", rc); 5195 5196 /* Remove already added handler */ 5197 for (y = 0; y < x; y++) 5198 (void) ddi_intr_remove_handler( 5199 Adapter->htable[y]); 5200 5201 /* Free already allocated intr */ 5202 for (y = 0; y < actual; y++) 5203 (void) ddi_intr_free(Adapter->htable[y]); 5204 5205 kmem_free(Adapter->htable, Adapter->intr_size); 5206 return (DDI_FAILURE); 5207 } 5208 } 5209 5210 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5211 5212 if (rc != DDI_SUCCESS) { 5213 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5214 "Get interrupt cap failed: %d\n", rc); 5215 5216 /* Free already allocated intr */ 5217 for (y = 0; y < actual; y++) { 5218 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5219 (void) ddi_intr_free(Adapter->htable[y]); 5220 } 5221 5222 kmem_free(Adapter->htable, Adapter->intr_size); 5223 return (DDI_FAILURE); 5224 } 5225 5226 return (DDI_SUCCESS); 5227 } 5228 5229 static int 5230 e1000g_rem_intrs(struct e1000g *Adapter) 5231 { 5232 int x; 5233 int rc; 5234 5235 for (x = 0; x < Adapter->intr_cnt; x++) { 5236 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5237 if (rc != DDI_SUCCESS) { 5238 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5239 "Remove intr handler failed: %d\n", rc); 5240 return (DDI_FAILURE); 5241 } 5242 5243 rc = ddi_intr_free(Adapter->htable[x]); 5244 if (rc != DDI_SUCCESS) { 5245 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5246 "Free intr failed: %d\n", rc); 5247 return (DDI_FAILURE); 5248 } 5249 } 5250 5251 kmem_free(Adapter->htable, Adapter->intr_size); 5252 5253 return (DDI_SUCCESS); 5254 } 5255 5256 static int 5257 e1000g_enable_intrs(struct e1000g *Adapter) 5258 { 5259 int x; 5260 int rc; 5261 5262 /* Enable interrupts */ 5263 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5264 /* Call ddi_intr_block_enable() for MSI */ 5265 rc = ddi_intr_block_enable(Adapter->htable, 5266 Adapter->intr_cnt); 5267 if (rc != DDI_SUCCESS) { 5268 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5269 "Enable block intr failed: %d\n", rc); 5270 return (DDI_FAILURE); 5271 } 5272 } else { 5273 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5274 for (x = 0; x < Adapter->intr_cnt; x++) { 5275 rc = ddi_intr_enable(Adapter->htable[x]); 5276 if (rc != DDI_SUCCESS) { 5277 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5278 "Enable intr failed: %d\n", rc); 5279 return (DDI_FAILURE); 5280 } 5281 } 5282 } 5283 5284 return (DDI_SUCCESS); 5285 } 5286 5287 static int 5288 e1000g_disable_intrs(struct e1000g *Adapter) 5289 { 5290 int x; 5291 int rc; 5292 5293 /* Disable all interrupts */ 5294 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5295 rc = ddi_intr_block_disable(Adapter->htable, 5296 Adapter->intr_cnt); 5297 if (rc != DDI_SUCCESS) { 5298 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5299 "Disable block intr failed: %d\n", rc); 5300 return (DDI_FAILURE); 5301 } 5302 } else { 5303 for (x = 0; x < Adapter->intr_cnt; x++) { 5304 rc = ddi_intr_disable(Adapter->htable[x]); 5305 if (rc != DDI_SUCCESS) { 5306 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5307 "Disable intr failed: %d\n", rc); 5308 return (DDI_FAILURE); 5309 } 5310 } 5311 } 5312 5313 return (DDI_SUCCESS); 5314 } 5315 5316 /* 5317 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5318 */ 5319 static void 5320 e1000g_get_phy_state(struct e1000g *Adapter) 5321 { 5322 struct e1000_hw *hw = &Adapter->shared; 5323 5324 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5325 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5326 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 5327 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 5328 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 5329 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 5330 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5331 &Adapter->phy_1000t_status); 5332 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 5333 5334 Adapter->param_autoneg_cap = 5335 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5336 Adapter->param_pause_cap = 5337 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5338 Adapter->param_asym_pause_cap = 5339 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5340 Adapter->param_1000fdx_cap = 5341 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5342 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5343 Adapter->param_1000hdx_cap = 5344 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5345 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5346 Adapter->param_100t4_cap = 5347 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5348 Adapter->param_100fdx_cap = 5349 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5350 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5351 Adapter->param_100hdx_cap = 5352 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5353 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5354 Adapter->param_10fdx_cap = 5355 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5356 Adapter->param_10hdx_cap = 5357 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5358 5359 Adapter->param_adv_autoneg = hw->mac.autoneg; 5360 Adapter->param_adv_pause = 5361 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5362 Adapter->param_adv_asym_pause = 5363 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5364 Adapter->param_adv_1000hdx = 5365 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5366 Adapter->param_adv_100t4 = 5367 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5368 if (Adapter->param_adv_autoneg == 1) { 5369 Adapter->param_adv_1000fdx = 5370 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5371 Adapter->param_adv_100fdx = 5372 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5373 Adapter->param_adv_100hdx = 5374 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5375 Adapter->param_adv_10fdx = 5376 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5377 Adapter->param_adv_10hdx = 5378 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5379 } 5380 5381 Adapter->param_lp_autoneg = 5382 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5383 Adapter->param_lp_pause = 5384 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5385 Adapter->param_lp_asym_pause = 5386 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5387 Adapter->param_lp_1000fdx = 5388 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5389 Adapter->param_lp_1000hdx = 5390 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5391 Adapter->param_lp_100t4 = 5392 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5393 Adapter->param_lp_100fdx = 5394 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5395 Adapter->param_lp_100hdx = 5396 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5397 Adapter->param_lp_10fdx = 5398 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5399 Adapter->param_lp_10hdx = 5400 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5401 } 5402 5403 /* 5404 * FMA support 5405 */ 5406 5407 int 5408 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5409 { 5410 ddi_fm_error_t de; 5411 5412 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5413 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5414 return (de.fme_status); 5415 } 5416 5417 int 5418 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5419 { 5420 ddi_fm_error_t de; 5421 5422 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5423 return (de.fme_status); 5424 } 5425 5426 /* 5427 * The IO fault service error handling callback function 5428 */ 5429 /* ARGSUSED2 */ 5430 static int 5431 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5432 { 5433 /* 5434 * as the driver can always deal with an error in any dma or 5435 * access handle, we can just return the fme_status value. 5436 */ 5437 pci_ereport_post(dip, err, NULL); 5438 return (err->fme_status); 5439 } 5440 5441 static void 5442 e1000g_fm_init(struct e1000g *Adapter) 5443 { 5444 ddi_iblock_cookie_t iblk; 5445 int fma_acc_flag, fma_dma_flag; 5446 5447 /* Only register with IO Fault Services if we have some capability */ 5448 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5449 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5450 fma_acc_flag = 1; 5451 } else { 5452 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5453 fma_acc_flag = 0; 5454 } 5455 5456 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5457 fma_dma_flag = 1; 5458 } else { 5459 fma_dma_flag = 0; 5460 } 5461 5462 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5463 5464 if (Adapter->fm_capabilities) { 5465 5466 /* Register capabilities with IO Fault Services */ 5467 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5468 5469 /* 5470 * Initialize pci ereport capabilities if ereport capable 5471 */ 5472 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5473 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5474 pci_ereport_setup(Adapter->dip); 5475 5476 /* 5477 * Register error callback if error callback capable 5478 */ 5479 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5480 ddi_fm_handler_register(Adapter->dip, 5481 e1000g_fm_error_cb, (void*) Adapter); 5482 } 5483 } 5484 5485 static void 5486 e1000g_fm_fini(struct e1000g *Adapter) 5487 { 5488 /* Only unregister FMA capabilities if we registered some */ 5489 if (Adapter->fm_capabilities) { 5490 5491 /* 5492 * Release any resources allocated by pci_ereport_setup() 5493 */ 5494 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5495 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5496 pci_ereport_teardown(Adapter->dip); 5497 5498 /* 5499 * Un-register error callback if error callback capable 5500 */ 5501 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5502 ddi_fm_handler_unregister(Adapter->dip); 5503 5504 /* Unregister from IO Fault Services */ 5505 ddi_fm_fini(Adapter->dip); 5506 } 5507 } 5508 5509 void 5510 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 5511 { 5512 uint64_t ena; 5513 char buf[FM_MAX_CLASS]; 5514 5515 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5516 ena = fm_ena_generate(0, FM_ENA_FMT1); 5517 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 5518 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 5519 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5520 } 5521 } 5522 5523 static int 5524 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 5525 uint_t pr_valsize, void *pr_val) 5526 { 5527 link_flowctrl_t fl; 5528 int err = 0; 5529 5530 ASSERT(pr_valsize > 0); 5531 switch (pr_num) { 5532 case MAC_PROP_AUTONEG: 5533 *(uint8_t *)pr_val = 5534 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0); 5535 break; 5536 case MAC_PROP_FLOWCTRL: 5537 if (pr_valsize < sizeof (link_flowctrl_t)) 5538 return (EINVAL); 5539 fl = LINK_FLOWCTRL_BI; 5540 bcopy(&fl, pr_val, sizeof (fl)); 5541 break; 5542 case MAC_PROP_ADV_1000FDX_CAP: 5543 case MAC_PROP_EN_1000FDX_CAP: 5544 *(uint8_t *)pr_val = 5545 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5546 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5547 break; 5548 case MAC_PROP_ADV_1000HDX_CAP: 5549 case MAC_PROP_EN_1000HDX_CAP: 5550 *(uint8_t *)pr_val = 5551 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5552 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5553 break; 5554 case MAC_PROP_ADV_100FDX_CAP: 5555 case MAC_PROP_EN_100FDX_CAP: 5556 *(uint8_t *)pr_val = 5557 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5558 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5559 break; 5560 case MAC_PROP_ADV_100HDX_CAP: 5561 case MAC_PROP_EN_100HDX_CAP: 5562 *(uint8_t *)pr_val = 5563 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5564 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5565 break; 5566 case MAC_PROP_ADV_10FDX_CAP: 5567 case MAC_PROP_EN_10FDX_CAP: 5568 *(uint8_t *)pr_val = 5569 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5570 break; 5571 case MAC_PROP_ADV_10HDX_CAP: 5572 case MAC_PROP_EN_10HDX_CAP: 5573 *(uint8_t *)pr_val = 5574 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5575 break; 5576 default: 5577 err = ENOTSUP; 5578 break; 5579 } 5580 return (err); 5581 } 5582 5583 /* 5584 * synchronize the adv* and en* parameters. 5585 * 5586 * See comments in <sys/dld.h> for details of the *_en_* 5587 * parameters. The usage of ndd for setting adv parameters will 5588 * synchronize all the en parameters with the e1000g parameters, 5589 * implicitly disabling any settings made via dladm. 5590 */ 5591 static void 5592 e1000g_param_sync(struct e1000g *Adapter) 5593 { 5594 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 5595 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 5596 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 5597 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 5598 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 5599 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 5600 } 5601 5602 /* 5603 * e1000g_get_driver_control - tell manageability firmware that the driver 5604 * has control. 5605 */ 5606 static void 5607 e1000g_get_driver_control(struct e1000_hw *hw) 5608 { 5609 uint32_t ctrl_ext; 5610 uint32_t swsm; 5611 5612 /* tell manageability firmware the driver has taken over */ 5613 switch (hw->mac.type) { 5614 case e1000_82573: 5615 swsm = E1000_READ_REG(hw, E1000_SWSM); 5616 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 5617 break; 5618 case e1000_82571: 5619 case e1000_82572: 5620 case e1000_82574: 5621 case e1000_80003es2lan: 5622 case e1000_ich8lan: 5623 case e1000_ich9lan: 5624 case e1000_ich10lan: 5625 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5626 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 5627 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 5628 break; 5629 default: 5630 /* no manageability firmware: do nothing */ 5631 break; 5632 } 5633 } 5634 5635 /* 5636 * e1000g_release_driver_control - tell manageability firmware that the driver 5637 * has released control. 5638 */ 5639 static void 5640 e1000g_release_driver_control(struct e1000_hw *hw) 5641 { 5642 uint32_t ctrl_ext; 5643 uint32_t swsm; 5644 5645 /* tell manageability firmware the driver has released control */ 5646 switch (hw->mac.type) { 5647 case e1000_82573: 5648 swsm = E1000_READ_REG(hw, E1000_SWSM); 5649 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 5650 break; 5651 case e1000_82571: 5652 case e1000_82572: 5653 case e1000_82574: 5654 case e1000_80003es2lan: 5655 case e1000_ich8lan: 5656 case e1000_ich9lan: 5657 case e1000_ich10lan: 5658 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5659 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 5660 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 5661 break; 5662 default: 5663 /* no manageability firmware: do nothing */ 5664 break; 5665 } 5666 } 5667