1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet"; 48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 49 static char e1000g_version[] = "Driver Ver. 5.3.3"; 50 51 /* 52 * Proto types for DDI entry points 53 */ 54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 56 static int e1000g_quiesce(dev_info_t *); 57 58 /* 59 * init and intr routines prototype 60 */ 61 static int e1000g_resume(dev_info_t *); 62 static int e1000g_suspend(dev_info_t *); 63 static uint_t e1000g_intr_pciexpress(caddr_t); 64 static uint_t e1000g_intr(caddr_t); 65 static void e1000g_intr_work(struct e1000g *, uint32_t); 66 #pragma inline(e1000g_intr_work) 67 static int e1000g_init(struct e1000g *); 68 static int e1000g_start(struct e1000g *, boolean_t); 69 static void e1000g_stop(struct e1000g *, boolean_t); 70 static int e1000g_m_start(void *); 71 static void e1000g_m_stop(void *); 72 static int e1000g_m_promisc(void *, boolean_t); 73 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 74 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 75 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 76 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 77 uint_t, const void *); 78 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 79 uint_t, uint_t, void *, uint_t *); 80 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 81 const void *); 82 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 83 uint_t, void *, uint_t *); 84 static void e1000g_init_locks(struct e1000g *); 85 static void e1000g_destroy_locks(struct e1000g *); 86 static int e1000g_identify_hardware(struct e1000g *); 87 static int e1000g_regs_map(struct e1000g *); 88 static int e1000g_set_driver_params(struct e1000g *); 89 static void e1000g_set_bufsize(struct e1000g *); 90 static int e1000g_register_mac(struct e1000g *); 91 static boolean_t e1000g_rx_drain(struct e1000g *); 92 static boolean_t e1000g_tx_drain(struct e1000g *); 93 static void e1000g_init_unicst(struct e1000g *); 94 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int); 95 96 /* 97 * Local routines 98 */ 99 static boolean_t e1000g_reset_adapter(struct e1000g *); 100 static void e1000g_tx_clean(struct e1000g *); 101 static void e1000g_rx_clean(struct e1000g *); 102 static void e1000g_link_timer(void *); 103 static void e1000g_local_timer(void *); 104 static boolean_t e1000g_link_check(struct e1000g *); 105 static boolean_t e1000g_stall_check(struct e1000g *); 106 static void e1000g_smartspeed(struct e1000g *); 107 static void e1000g_get_conf(struct e1000g *); 108 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 109 static void enable_watchdog_timer(struct e1000g *); 110 static void disable_watchdog_timer(struct e1000g *); 111 static void start_watchdog_timer(struct e1000g *); 112 static void restart_watchdog_timer(struct e1000g *); 113 static void stop_watchdog_timer(struct e1000g *); 114 static void stop_link_timer(struct e1000g *); 115 static void stop_82547_timer(e1000g_tx_ring_t *); 116 static void e1000g_force_speed_duplex(struct e1000g *); 117 static void e1000g_get_max_frame_size(struct e1000g *); 118 static boolean_t is_valid_mac_addr(uint8_t *); 119 static void e1000g_unattach(dev_info_t *, struct e1000g *); 120 #ifdef E1000G_DEBUG 121 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 122 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 123 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 124 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 125 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 126 struct iocblk *, mblk_t *); 127 #endif 128 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 129 struct iocblk *, mblk_t *); 130 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 131 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 132 static void e1000g_set_internal_loopback(struct e1000g *); 133 static void e1000g_set_external_loopback_1000(struct e1000g *); 134 static void e1000g_set_external_loopback_100(struct e1000g *); 135 static void e1000g_set_external_loopback_10(struct e1000g *); 136 static int e1000g_add_intrs(struct e1000g *); 137 static int e1000g_intr_add(struct e1000g *, int); 138 static int e1000g_rem_intrs(struct e1000g *); 139 static int e1000g_enable_intrs(struct e1000g *); 140 static int e1000g_disable_intrs(struct e1000g *); 141 static boolean_t e1000g_link_up(struct e1000g *); 142 #ifdef __sparc 143 static boolean_t e1000g_find_mac_address(struct e1000g *); 144 #endif 145 static void e1000g_get_phy_state(struct e1000g *); 146 static void e1000g_free_priv_devi_node(struct e1000g *, boolean_t); 147 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 148 const void *impl_data); 149 static void e1000g_fm_init(struct e1000g *Adapter); 150 static void e1000g_fm_fini(struct e1000g *Adapter); 151 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 152 static void e1000g_param_sync(struct e1000g *); 153 static void e1000g_get_driver_control(struct e1000_hw *); 154 static void e1000g_release_driver_control(struct e1000_hw *); 155 static void e1000g_restore_promisc(struct e1000g *Adapter); 156 157 mac_priv_prop_t e1000g_priv_props[] = { 158 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 159 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 160 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 161 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 162 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 163 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 164 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 165 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 166 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 167 {"_intr_adaptive", MAC_PROP_PERM_RW}, 168 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 169 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 170 }; 171 #define E1000G_MAX_PRIV_PROPS \ 172 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 173 174 175 static struct cb_ops cb_ws_ops = { 176 nulldev, /* cb_open */ 177 nulldev, /* cb_close */ 178 nodev, /* cb_strategy */ 179 nodev, /* cb_print */ 180 nodev, /* cb_dump */ 181 nodev, /* cb_read */ 182 nodev, /* cb_write */ 183 nodev, /* cb_ioctl */ 184 nodev, /* cb_devmap */ 185 nodev, /* cb_mmap */ 186 nodev, /* cb_segmap */ 187 nochpoll, /* cb_chpoll */ 188 ddi_prop_op, /* cb_prop_op */ 189 NULL, /* cb_stream */ 190 D_MP | D_HOTPLUG, /* cb_flag */ 191 CB_REV, /* cb_rev */ 192 nodev, /* cb_aread */ 193 nodev /* cb_awrite */ 194 }; 195 196 static struct dev_ops ws_ops = { 197 DEVO_REV, /* devo_rev */ 198 0, /* devo_refcnt */ 199 NULL, /* devo_getinfo */ 200 nulldev, /* devo_identify */ 201 nulldev, /* devo_probe */ 202 e1000g_attach, /* devo_attach */ 203 e1000g_detach, /* devo_detach */ 204 nodev, /* devo_reset */ 205 &cb_ws_ops, /* devo_cb_ops */ 206 NULL, /* devo_bus_ops */ 207 ddi_power, /* devo_power */ 208 e1000g_quiesce /* devo_quiesce */ 209 }; 210 211 static struct modldrv modldrv = { 212 &mod_driverops, /* Type of module. This one is a driver */ 213 ident, /* Discription string */ 214 &ws_ops, /* driver ops */ 215 }; 216 217 static struct modlinkage modlinkage = { 218 MODREV_1, &modldrv, NULL 219 }; 220 221 /* Access attributes for register mapping */ 222 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 223 DDI_DEVICE_ATTR_V0, 224 DDI_STRUCTURE_LE_ACC, 225 DDI_STRICTORDER_ACC, 226 DDI_FLAGERR_ACC 227 }; 228 229 #define E1000G_M_CALLBACK_FLAGS \ 230 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 231 232 static mac_callbacks_t e1000g_m_callbacks = { 233 E1000G_M_CALLBACK_FLAGS, 234 e1000g_m_stat, 235 e1000g_m_start, 236 e1000g_m_stop, 237 e1000g_m_promisc, 238 e1000g_m_multicst, 239 NULL, 240 e1000g_m_tx, 241 e1000g_m_ioctl, 242 e1000g_m_getcapab, 243 NULL, 244 NULL, 245 e1000g_m_setprop, 246 e1000g_m_getprop 247 }; 248 249 /* 250 * Global variables 251 */ 252 uint32_t e1000g_mblks_pending = 0; 253 /* 254 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 255 * Here we maintain a private dev_info list if e1000g_force_detach is 256 * enabled. If we force the driver to detach while there are still some 257 * rx buffers retained in the upper layer, we have to keep a copy of the 258 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 259 * structure will be freed after the driver is detached. However when we 260 * finally free those rx buffers released by the upper layer, we need to 261 * refer to the dev_info to free the dma buffers. So we save a copy of 262 * the dev_info for this purpose. On x86 platform, we assume this copy 263 * of dev_info is always valid, but on SPARC platform, it could be invalid 264 * after the system board level DR operation. For this reason, the global 265 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 266 */ 267 #ifdef __sparc 268 boolean_t e1000g_force_detach = B_FALSE; 269 #else 270 boolean_t e1000g_force_detach = B_TRUE; 271 #endif 272 private_devi_list_t *e1000g_private_devi_list = NULL; 273 274 /* 275 * The rwlock is defined to protect the whole processing of rx recycling 276 * and the rx packets release in detach processing to make them mutually 277 * exclusive. 278 * The rx recycling processes different rx packets in different threads, 279 * so it will be protected with RW_READER and it won't block any other rx 280 * recycling threads. 281 * While the detach processing will be protected with RW_WRITER to make 282 * it mutually exclusive with the rx recycling. 283 */ 284 krwlock_t e1000g_rx_detach_lock; 285 /* 286 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 287 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 288 * If there are many e1000g instances, the system may run out of DVMA 289 * resources during the initialization of the instances, then the flag will 290 * be changed to "USE_DMA". Because different e1000g instances are initialized 291 * in parallel, we need to use this lock to protect the flag. 292 */ 293 krwlock_t e1000g_dma_type_lock; 294 295 /* 296 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 297 * Based on the information from Intel, the 82546 chipset has some hardware 298 * problem. When one port is being reset and the other port is trying to 299 * access the eeprom, it could cause system hang or panic. To workaround this 300 * hardware problem, we use a global mutex to prevent such operations from 301 * happening simultaneously on different instances. This workaround is applied 302 * to all the devices supported by this driver. 303 */ 304 kmutex_t e1000g_nvm_lock; 305 306 /* 307 * Loadable module configuration entry points for the driver 308 */ 309 310 /* 311 * _init - module initialization 312 */ 313 int 314 _init(void) 315 { 316 int status; 317 318 mac_init_ops(&ws_ops, WSNAME); 319 status = mod_install(&modlinkage); 320 if (status != DDI_SUCCESS) 321 mac_fini_ops(&ws_ops); 322 else { 323 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 324 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 325 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 326 } 327 328 return (status); 329 } 330 331 /* 332 * _fini - module finalization 333 */ 334 int 335 _fini(void) 336 { 337 int status; 338 339 rw_enter(&e1000g_rx_detach_lock, RW_READER); 340 if (e1000g_mblks_pending != 0) { 341 rw_exit(&e1000g_rx_detach_lock); 342 return (EBUSY); 343 } 344 rw_exit(&e1000g_rx_detach_lock); 345 346 status = mod_remove(&modlinkage); 347 if (status == DDI_SUCCESS) { 348 mac_fini_ops(&ws_ops); 349 350 if (e1000g_force_detach) { 351 private_devi_list_t *devi_node; 352 353 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 354 while (e1000g_private_devi_list != NULL) { 355 devi_node = e1000g_private_devi_list; 356 e1000g_private_devi_list = 357 e1000g_private_devi_list->next; 358 359 kmem_free(devi_node->priv_dip, 360 sizeof (struct dev_info)); 361 kmem_free(devi_node, 362 sizeof (private_devi_list_t)); 363 } 364 rw_exit(&e1000g_rx_detach_lock); 365 } 366 367 rw_destroy(&e1000g_rx_detach_lock); 368 rw_destroy(&e1000g_dma_type_lock); 369 mutex_destroy(&e1000g_nvm_lock); 370 } 371 372 return (status); 373 } 374 375 /* 376 * _info - module information 377 */ 378 int 379 _info(struct modinfo *modinfop) 380 { 381 return (mod_info(&modlinkage, modinfop)); 382 } 383 384 /* 385 * e1000g_attach - driver attach 386 * 387 * This function is the device-specific initialization entry 388 * point. This entry point is required and must be written. 389 * The DDI_ATTACH command must be provided in the attach entry 390 * point. When attach() is called with cmd set to DDI_ATTACH, 391 * all normal kernel services (such as kmem_alloc(9F)) are 392 * available for use by the driver. 393 * 394 * The attach() function will be called once for each instance 395 * of the device on the system with cmd set to DDI_ATTACH. 396 * Until attach() succeeds, the only driver entry points which 397 * may be called are open(9E) and getinfo(9E). 398 */ 399 static int 400 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 401 { 402 struct e1000g *Adapter; 403 struct e1000_hw *hw; 404 struct e1000g_osdep *osdep; 405 int instance; 406 407 switch (cmd) { 408 default: 409 e1000g_log(NULL, CE_WARN, 410 "Unsupported command send to e1000g_attach... "); 411 return (DDI_FAILURE); 412 413 case DDI_RESUME: 414 return (e1000g_resume(devinfo)); 415 416 case DDI_ATTACH: 417 break; 418 } 419 420 /* 421 * get device instance number 422 */ 423 instance = ddi_get_instance(devinfo); 424 425 /* 426 * Allocate soft data structure 427 */ 428 Adapter = 429 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 430 431 Adapter->dip = devinfo; 432 Adapter->instance = instance; 433 Adapter->tx_ring->adapter = Adapter; 434 Adapter->rx_ring->adapter = Adapter; 435 436 hw = &Adapter->shared; 437 osdep = &Adapter->osdep; 438 hw->back = osdep; 439 osdep->adapter = Adapter; 440 441 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 442 443 /* 444 * Initialize for fma support 445 */ 446 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 447 0, 0x0f, 448 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 449 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 450 e1000g_fm_init(Adapter); 451 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 452 453 /* 454 * PCI Configure 455 */ 456 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 457 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 458 goto attach_fail; 459 } 460 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 461 462 /* 463 * Setup hardware 464 */ 465 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 466 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 467 goto attach_fail; 468 } 469 470 /* 471 * Map in the device registers. 472 */ 473 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 474 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 475 goto attach_fail; 476 } 477 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 478 479 /* 480 * Initialize driver parameters 481 */ 482 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 483 goto attach_fail; 484 } 485 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 486 487 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 488 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 489 goto attach_fail; 490 } 491 492 /* 493 * Initialize interrupts 494 */ 495 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 496 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 497 goto attach_fail; 498 } 499 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 500 501 /* 502 * Initialize mutex's for this device. 503 * Do this before enabling the interrupt handler and 504 * register the softint to avoid the condition where 505 * interrupt handler can try using uninitialized mutex 506 */ 507 e1000g_init_locks(Adapter); 508 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 509 510 /* 511 * Initialize Driver Counters 512 */ 513 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 514 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 515 goto attach_fail; 516 } 517 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 518 519 /* 520 * Initialize chip hardware and software structures 521 */ 522 rw_enter(&Adapter->chip_lock, RW_WRITER); 523 if (e1000g_init(Adapter) != DDI_SUCCESS) { 524 rw_exit(&Adapter->chip_lock); 525 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 526 goto attach_fail; 527 } 528 rw_exit(&Adapter->chip_lock); 529 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 530 531 /* 532 * Register the driver to the MAC 533 */ 534 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 535 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 536 goto attach_fail; 537 } 538 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 539 540 /* 541 * Now that mutex locks are initialized, and the chip is also 542 * initialized, enable interrupts. 543 */ 544 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 545 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 546 goto attach_fail; 547 } 548 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 549 550 /* 551 * If e1000g_force_detach is enabled, in global private dip list, 552 * we will create a new entry, which maintains the priv_dip for DR 553 * supports after driver detached. 554 */ 555 if (e1000g_force_detach) { 556 private_devi_list_t *devi_node; 557 558 Adapter->priv_dip = 559 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 560 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 561 sizeof (struct dev_info)); 562 563 devi_node = 564 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 565 566 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 567 devi_node->priv_dip = Adapter->priv_dip; 568 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 569 devi_node->next = e1000g_private_devi_list; 570 e1000g_private_devi_list = devi_node; 571 rw_exit(&e1000g_rx_detach_lock); 572 } 573 574 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 575 Adapter->e1000g_state = E1000G_INITIALIZED; 576 577 return (DDI_SUCCESS); 578 579 attach_fail: 580 e1000g_unattach(devinfo, Adapter); 581 return (DDI_FAILURE); 582 } 583 584 static int 585 e1000g_register_mac(struct e1000g *Adapter) 586 { 587 struct e1000_hw *hw = &Adapter->shared; 588 mac_register_t *mac; 589 int err; 590 591 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 592 return (DDI_FAILURE); 593 594 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 595 mac->m_driver = Adapter; 596 mac->m_dip = Adapter->dip; 597 mac->m_src_addr = hw->mac.addr; 598 mac->m_callbacks = &e1000g_m_callbacks; 599 mac->m_min_sdu = 0; 600 mac->m_max_sdu = Adapter->default_mtu; 601 mac->m_margin = VLAN_TAGSZ; 602 mac->m_priv_props = e1000g_priv_props; 603 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 604 mac->m_v12n = MAC_VIRT_LEVEL1; 605 606 err = mac_register(mac, &Adapter->mh); 607 mac_free(mac); 608 609 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 610 } 611 612 static int 613 e1000g_identify_hardware(struct e1000g *Adapter) 614 { 615 struct e1000_hw *hw = &Adapter->shared; 616 struct e1000g_osdep *osdep = &Adapter->osdep; 617 618 /* Get the device id */ 619 hw->vendor_id = 620 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 621 hw->device_id = 622 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 623 hw->revision_id = 624 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 625 hw->subsystem_device_id = 626 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 627 hw->subsystem_vendor_id = 628 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 629 630 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 631 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 632 "MAC type could not be set properly."); 633 return (DDI_FAILURE); 634 } 635 636 return (DDI_SUCCESS); 637 } 638 639 static int 640 e1000g_regs_map(struct e1000g *Adapter) 641 { 642 dev_info_t *devinfo = Adapter->dip; 643 struct e1000_hw *hw = &Adapter->shared; 644 struct e1000g_osdep *osdep = &Adapter->osdep; 645 off_t mem_size; 646 647 /* Get size of adapter register memory */ 648 if (ddi_dev_regsize(devinfo, ADAPTER_REG_SET, &mem_size) != 649 DDI_SUCCESS) { 650 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 651 "ddi_dev_regsize for registers failed"); 652 return (DDI_FAILURE); 653 } 654 655 /* Map adapter register memory */ 656 if ((ddi_regs_map_setup(devinfo, ADAPTER_REG_SET, 657 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 658 &osdep->reg_handle)) != DDI_SUCCESS) { 659 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 660 "ddi_regs_map_setup for registers failed"); 661 goto regs_map_fail; 662 } 663 664 /* ICH needs to map flash memory */ 665 if (hw->mac.type == e1000_ich8lan || 666 hw->mac.type == e1000_ich9lan || 667 hw->mac.type == e1000_ich10lan) { 668 /* get flash size */ 669 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 670 &mem_size) != DDI_SUCCESS) { 671 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 672 "ddi_dev_regsize for ICH flash failed"); 673 goto regs_map_fail; 674 } 675 676 /* map flash in */ 677 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 678 (caddr_t *)&hw->flash_address, 0, 679 mem_size, &e1000g_regs_acc_attr, 680 &osdep->ich_flash_handle) != DDI_SUCCESS) { 681 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 682 "ddi_regs_map_setup for ICH flash failed"); 683 goto regs_map_fail; 684 } 685 } 686 687 return (DDI_SUCCESS); 688 689 regs_map_fail: 690 if (osdep->reg_handle != NULL) 691 ddi_regs_map_free(&osdep->reg_handle); 692 693 return (DDI_FAILURE); 694 } 695 696 static int 697 e1000g_set_driver_params(struct e1000g *Adapter) 698 { 699 struct e1000_hw *hw; 700 uint32_t mem_bar, io_bar, bar64; 701 702 hw = &Adapter->shared; 703 704 /* Set MAC type and initialize hardware functions */ 705 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 706 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 707 "Could not setup hardware functions"); 708 return (DDI_FAILURE); 709 } 710 711 /* Get bus information */ 712 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 713 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 714 "Could not get bus information"); 715 return (DDI_FAILURE); 716 } 717 718 /* get mem_base addr */ 719 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 720 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 721 722 /* get io_base addr */ 723 if (hw->mac.type >= e1000_82544) { 724 if (bar64) { 725 /* IO BAR is different for 64 bit BAR mode */ 726 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 727 PCI_CONF_BASE4); 728 } else { 729 /* normal 32-bit BAR mode */ 730 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 731 PCI_CONF_BASE2); 732 } 733 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 734 } else { 735 /* no I/O access for adapters prior to 82544 */ 736 hw->io_base = 0x0; 737 } 738 739 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 740 741 hw->mac.autoneg_failed = B_TRUE; 742 743 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 744 hw->phy.autoneg_wait_to_complete = B_FALSE; 745 746 /* Adaptive IFS related changes */ 747 hw->mac.adaptive_ifs = B_TRUE; 748 749 /* Enable phy init script for IGP phy of 82541/82547 */ 750 if ((hw->mac.type == e1000_82547) || 751 (hw->mac.type == e1000_82541) || 752 (hw->mac.type == e1000_82547_rev_2) || 753 (hw->mac.type == e1000_82541_rev_2)) 754 e1000_init_script_state_82541(hw, B_TRUE); 755 756 /* Enable the TTL workaround for 82541/82547 */ 757 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 758 759 #ifdef __sparc 760 Adapter->strip_crc = B_TRUE; 761 #else 762 Adapter->strip_crc = B_FALSE; 763 #endif 764 765 /* Get conf file properties */ 766 e1000g_get_conf(Adapter); 767 768 /* Get speed/duplex settings in conf file */ 769 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 770 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 771 e1000g_force_speed_duplex(Adapter); 772 773 /* Get Jumbo Frames settings in conf file */ 774 e1000g_get_max_frame_size(Adapter); 775 776 /* Set Rx/Tx buffer size */ 777 e1000g_set_bufsize(Adapter); 778 779 /* Master Latency Timer */ 780 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 781 782 /* copper options */ 783 if (hw->phy.media_type == e1000_media_type_copper) { 784 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 785 hw->phy.disable_polarity_correction = B_FALSE; 786 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 787 } 788 789 /* The initial link state should be "unknown" */ 790 Adapter->link_state = LINK_STATE_UNKNOWN; 791 792 /* Initialize rx parameters */ 793 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 794 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 795 796 /* Initialize tx parameters */ 797 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 798 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 799 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 800 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 801 802 /* Initialize rx parameters */ 803 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 804 805 return (DDI_SUCCESS); 806 } 807 808 static void 809 e1000g_set_bufsize(struct e1000g *Adapter) 810 { 811 struct e1000_mac_info *mac = &Adapter->shared.mac; 812 uint64_t rx_size; 813 uint64_t tx_size; 814 815 dev_info_t *devinfo = Adapter->dip; 816 #ifdef __sparc 817 ulong_t iommu_pagesize; 818 #endif 819 /* Get the system page size */ 820 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 821 822 #ifdef __sparc 823 iommu_pagesize = dvma_pagesize(devinfo); 824 if (iommu_pagesize != 0) { 825 if (Adapter->sys_page_sz == iommu_pagesize) { 826 if (iommu_pagesize > 0x4000) 827 Adapter->sys_page_sz = 0x4000; 828 } else { 829 if (Adapter->sys_page_sz > iommu_pagesize) 830 Adapter->sys_page_sz = iommu_pagesize; 831 } 832 } 833 if (Adapter->lso_enable) { 834 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 835 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 836 } else { 837 Adapter->dvma_page_num = Adapter->max_frame_size / 838 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 839 } 840 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 841 #endif 842 843 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 844 845 if (Adapter->mem_workaround_82546 && 846 ((mac->type == e1000_82545) || 847 (mac->type == e1000_82546) || 848 (mac->type == e1000_82546_rev_3))) { 849 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 850 } else { 851 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 852 if ((rx_size > FRAME_SIZE_UPTO_2K) && 853 (rx_size <= FRAME_SIZE_UPTO_4K)) 854 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 855 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 856 (rx_size <= FRAME_SIZE_UPTO_8K)) 857 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 858 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 859 (rx_size <= FRAME_SIZE_UPTO_16K)) 860 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 861 else 862 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 863 } 864 865 tx_size = Adapter->max_frame_size; 866 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 867 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 868 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 869 (tx_size <= FRAME_SIZE_UPTO_8K)) 870 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 871 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 872 (tx_size <= FRAME_SIZE_UPTO_16K)) 873 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 874 else 875 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 876 877 /* 878 * For Wiseman adapters we have an requirement of having receive 879 * buffers aligned at 256 byte boundary. Since Livengood does not 880 * require this and forcing it for all hardwares will have 881 * performance implications, I am making it applicable only for 882 * Wiseman and for Jumbo frames enabled mode as rest of the time, 883 * it is okay to have normal frames...but it does involve a 884 * potential risk where we may loose data if buffer is not 885 * aligned...so all wiseman boards to have 256 byte aligned 886 * buffers 887 */ 888 if (mac->type < e1000_82543) 889 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 890 else 891 Adapter->rx_buf_align = 1; 892 } 893 894 /* 895 * e1000g_detach - driver detach 896 * 897 * The detach() function is the complement of the attach routine. 898 * If cmd is set to DDI_DETACH, detach() is used to remove the 899 * state associated with a given instance of a device node 900 * prior to the removal of that instance from the system. 901 * 902 * The detach() function will be called once for each instance 903 * of the device for which there has been a successful attach() 904 * once there are no longer any opens on the device. 905 * 906 * Interrupts routine are disabled, All memory allocated by this 907 * driver are freed. 908 */ 909 static int 910 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 911 { 912 struct e1000g *Adapter; 913 boolean_t rx_drain; 914 915 switch (cmd) { 916 default: 917 return (DDI_FAILURE); 918 919 case DDI_SUSPEND: 920 return (e1000g_suspend(devinfo)); 921 922 case DDI_DETACH: 923 break; 924 } 925 926 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 927 if (Adapter == NULL) 928 return (DDI_FAILURE); 929 930 rx_drain = e1000g_rx_drain(Adapter); 931 if (!rx_drain && !e1000g_force_detach) 932 return (DDI_FAILURE); 933 934 if (mac_unregister(Adapter->mh) != 0) { 935 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 936 return (DDI_FAILURE); 937 } 938 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 939 940 ASSERT(!(Adapter->e1000g_state & E1000G_STARTED)); 941 942 /* 943 * If e1000g_force_detach is enabled, driver detach is safe. 944 * We will let e1000g_free_priv_devi_node routine determine 945 * whether we need to free the priv_dip entry for current 946 * driver instance. 947 */ 948 if (e1000g_force_detach) { 949 e1000g_free_priv_devi_node(Adapter, rx_drain); 950 } 951 952 e1000g_unattach(devinfo, Adapter); 953 954 return (DDI_SUCCESS); 955 } 956 957 /* 958 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 959 * 960 * If free_flag is true, that indicates the upper layer is not holding 961 * the rx buffers, we could free the priv_dip entry safely. 962 * 963 * Otherwise, we have to keep this entry even after driver detached, 964 * and we also need to mark this entry with E1000G_PRIV_DEVI_DETACH flag, 965 * so that driver could free it while all of rx buffers are returned 966 * by upper layer later. 967 */ 968 static void 969 e1000g_free_priv_devi_node(struct e1000g *Adapter, boolean_t free_flag) 970 { 971 private_devi_list_t *devi_node, *devi_del; 972 973 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 974 ASSERT(e1000g_private_devi_list != NULL); 975 ASSERT(Adapter->priv_dip != NULL); 976 977 devi_node = e1000g_private_devi_list; 978 if (devi_node->priv_dip == Adapter->priv_dip) { 979 if (free_flag) { 980 e1000g_private_devi_list = 981 devi_node->next; 982 kmem_free(devi_node->priv_dip, 983 sizeof (struct dev_info)); 984 kmem_free(devi_node, 985 sizeof (private_devi_list_t)); 986 } else { 987 ASSERT(e1000g_mblks_pending != 0); 988 devi_node->flag = 989 E1000G_PRIV_DEVI_DETACH; 990 } 991 rw_exit(&e1000g_rx_detach_lock); 992 return; 993 } 994 995 devi_node = e1000g_private_devi_list; 996 while (devi_node->next != NULL) { 997 if (devi_node->next->priv_dip == Adapter->priv_dip) { 998 if (free_flag) { 999 devi_del = devi_node->next; 1000 devi_node->next = devi_del->next; 1001 kmem_free(devi_del->priv_dip, 1002 sizeof (struct dev_info)); 1003 kmem_free(devi_del, 1004 sizeof (private_devi_list_t)); 1005 } else { 1006 ASSERT(e1000g_mblks_pending != 0); 1007 devi_node->next->flag = 1008 E1000G_PRIV_DEVI_DETACH; 1009 } 1010 break; 1011 } 1012 devi_node = devi_node->next; 1013 } 1014 rw_exit(&e1000g_rx_detach_lock); 1015 } 1016 1017 static void 1018 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1019 { 1020 int result; 1021 1022 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1023 (void) e1000g_disable_intrs(Adapter); 1024 } 1025 1026 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1027 (void) mac_unregister(Adapter->mh); 1028 } 1029 1030 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1031 (void) e1000g_rem_intrs(Adapter); 1032 } 1033 1034 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1035 (void) ddi_prop_remove_all(devinfo); 1036 } 1037 1038 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1039 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1040 } 1041 1042 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1043 stop_link_timer(Adapter); 1044 1045 mutex_enter(&e1000g_nvm_lock); 1046 result = e1000_reset_hw(&Adapter->shared); 1047 mutex_exit(&e1000g_nvm_lock); 1048 1049 if (result != E1000_SUCCESS) { 1050 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1051 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1052 } 1053 } 1054 1055 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1056 if (Adapter->osdep.reg_handle != NULL) 1057 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1058 if (Adapter->osdep.ich_flash_handle != NULL) 1059 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1060 } 1061 1062 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1063 if (Adapter->osdep.cfg_handle != NULL) 1064 pci_config_teardown(&Adapter->osdep.cfg_handle); 1065 } 1066 1067 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1068 e1000g_destroy_locks(Adapter); 1069 } 1070 1071 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1072 e1000g_fm_fini(Adapter); 1073 } 1074 1075 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1076 1077 /* 1078 * Another hotplug spec requirement, 1079 * run ddi_set_driver_private(devinfo, null); 1080 */ 1081 ddi_set_driver_private(devinfo, NULL); 1082 } 1083 1084 static void 1085 e1000g_init_locks(struct e1000g *Adapter) 1086 { 1087 e1000g_tx_ring_t *tx_ring; 1088 e1000g_rx_ring_t *rx_ring; 1089 1090 rw_init(&Adapter->chip_lock, NULL, 1091 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1092 mutex_init(&Adapter->link_lock, NULL, 1093 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1094 mutex_init(&Adapter->watchdog_lock, NULL, 1095 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1096 1097 tx_ring = Adapter->tx_ring; 1098 1099 mutex_init(&tx_ring->tx_lock, NULL, 1100 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1101 mutex_init(&tx_ring->usedlist_lock, NULL, 1102 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1103 mutex_init(&tx_ring->freelist_lock, NULL, 1104 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1105 1106 rx_ring = Adapter->rx_ring; 1107 1108 mutex_init(&rx_ring->rx_lock, NULL, 1109 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1110 mutex_init(&rx_ring->freelist_lock, NULL, 1111 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1112 mutex_init(&rx_ring->recycle_lock, NULL, 1113 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1114 } 1115 1116 static void 1117 e1000g_destroy_locks(struct e1000g *Adapter) 1118 { 1119 e1000g_tx_ring_t *tx_ring; 1120 e1000g_rx_ring_t *rx_ring; 1121 1122 tx_ring = Adapter->tx_ring; 1123 mutex_destroy(&tx_ring->tx_lock); 1124 mutex_destroy(&tx_ring->usedlist_lock); 1125 mutex_destroy(&tx_ring->freelist_lock); 1126 1127 rx_ring = Adapter->rx_ring; 1128 mutex_destroy(&rx_ring->rx_lock); 1129 mutex_destroy(&rx_ring->freelist_lock); 1130 mutex_destroy(&rx_ring->recycle_lock); 1131 1132 mutex_destroy(&Adapter->link_lock); 1133 mutex_destroy(&Adapter->watchdog_lock); 1134 rw_destroy(&Adapter->chip_lock); 1135 } 1136 1137 static int 1138 e1000g_resume(dev_info_t *devinfo) 1139 { 1140 struct e1000g *Adapter; 1141 1142 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1143 if (Adapter == NULL) 1144 e1000g_log(Adapter, CE_PANIC, 1145 "Instance pointer is null\n"); 1146 1147 if (Adapter->dip != devinfo) 1148 e1000g_log(Adapter, CE_PANIC, 1149 "Devinfo is not the same as saved devinfo\n"); 1150 1151 rw_enter(&Adapter->chip_lock, RW_WRITER); 1152 1153 if (Adapter->e1000g_state & E1000G_STARTED) { 1154 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1155 rw_exit(&Adapter->chip_lock); 1156 /* 1157 * We note the failure, but return success, as the 1158 * system is still usable without this controller. 1159 */ 1160 e1000g_log(Adapter, CE_WARN, 1161 "e1000g_resume: failed to restart controller\n"); 1162 return (DDI_SUCCESS); 1163 } 1164 /* Enable and start the watchdog timer */ 1165 enable_watchdog_timer(Adapter); 1166 } 1167 1168 Adapter->e1000g_state &= ~E1000G_SUSPENDED; 1169 1170 rw_exit(&Adapter->chip_lock); 1171 1172 return (DDI_SUCCESS); 1173 } 1174 1175 static int 1176 e1000g_suspend(dev_info_t *devinfo) 1177 { 1178 struct e1000g *Adapter; 1179 1180 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1181 if (Adapter == NULL) 1182 return (DDI_FAILURE); 1183 1184 rw_enter(&Adapter->chip_lock, RW_WRITER); 1185 1186 Adapter->e1000g_state |= E1000G_SUSPENDED; 1187 1188 /* if the port isn't plumbed, we can simply return */ 1189 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 1190 rw_exit(&Adapter->chip_lock); 1191 return (DDI_SUCCESS); 1192 } 1193 1194 e1000g_stop(Adapter, B_FALSE); 1195 1196 rw_exit(&Adapter->chip_lock); 1197 1198 /* Disable and stop all the timers */ 1199 disable_watchdog_timer(Adapter); 1200 stop_link_timer(Adapter); 1201 stop_82547_timer(Adapter->tx_ring); 1202 1203 return (DDI_SUCCESS); 1204 } 1205 1206 static int 1207 e1000g_init(struct e1000g *Adapter) 1208 { 1209 uint32_t pba; 1210 uint32_t high_water; 1211 struct e1000_hw *hw; 1212 clock_t link_timeout; 1213 int result; 1214 1215 hw = &Adapter->shared; 1216 1217 /* 1218 * reset to put the hardware in a known state 1219 * before we try to do anything with the eeprom 1220 */ 1221 mutex_enter(&e1000g_nvm_lock); 1222 result = e1000_reset_hw(hw); 1223 mutex_exit(&e1000g_nvm_lock); 1224 1225 if (result != E1000_SUCCESS) { 1226 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1227 goto init_fail; 1228 } 1229 1230 mutex_enter(&e1000g_nvm_lock); 1231 result = e1000_validate_nvm_checksum(hw); 1232 if (result < E1000_SUCCESS) { 1233 /* 1234 * Some PCI-E parts fail the first check due to 1235 * the link being in sleep state. Call it again, 1236 * if it fails a second time its a real issue. 1237 */ 1238 result = e1000_validate_nvm_checksum(hw); 1239 } 1240 mutex_exit(&e1000g_nvm_lock); 1241 1242 if (result < E1000_SUCCESS) { 1243 e1000g_log(Adapter, CE_WARN, 1244 "Invalid NVM checksum. Please contact " 1245 "the vendor to update the NVM."); 1246 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1247 goto init_fail; 1248 } 1249 1250 result = 0; 1251 #ifdef __sparc 1252 /* 1253 * First, we try to get the local ethernet address from OBP. If 1254 * failed, then we get it from the EEPROM of NIC card. 1255 */ 1256 result = e1000g_find_mac_address(Adapter); 1257 #endif 1258 /* Get the local ethernet address. */ 1259 if (!result) { 1260 mutex_enter(&e1000g_nvm_lock); 1261 result = e1000_read_mac_addr(hw); 1262 mutex_exit(&e1000g_nvm_lock); 1263 } 1264 1265 if (result < E1000_SUCCESS) { 1266 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1267 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1268 goto init_fail; 1269 } 1270 1271 /* check for valid mac address */ 1272 if (!is_valid_mac_addr(hw->mac.addr)) { 1273 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1274 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1275 goto init_fail; 1276 } 1277 1278 /* Set LAA state for 82571 chipset */ 1279 e1000_set_laa_state_82571(hw, B_TRUE); 1280 1281 /* Master Latency Timer implementation */ 1282 if (Adapter->master_latency_timer) { 1283 pci_config_put8(Adapter->osdep.cfg_handle, 1284 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1285 } 1286 1287 if (hw->mac.type < e1000_82547) { 1288 /* 1289 * Total FIFO is 64K 1290 */ 1291 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1292 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1293 else 1294 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1295 } else if ((hw->mac.type == e1000_82571) || 1296 (hw->mac.type == e1000_82572) || 1297 (hw->mac.type == e1000_80003es2lan)) { 1298 /* 1299 * Total FIFO is 48K 1300 */ 1301 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1302 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1303 else 1304 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1305 } else if (hw->mac.type == e1000_82573) { 1306 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1307 } else if (hw->mac.type == e1000_82574) { 1308 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1309 pba = E1000_READ_REG(hw, E1000_PBA); 1310 } else if (hw->mac.type == e1000_ich8lan) { 1311 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1312 } else if (hw->mac.type == e1000_ich9lan) { 1313 pba = E1000_PBA_10K; 1314 } else if (hw->mac.type == e1000_ich10lan) { 1315 pba = E1000_PBA_10K; 1316 } else { 1317 /* 1318 * Total FIFO is 40K 1319 */ 1320 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1321 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1322 else 1323 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1324 } 1325 E1000_WRITE_REG(hw, E1000_PBA, pba); 1326 1327 /* 1328 * These parameters set thresholds for the adapter's generation(Tx) 1329 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1330 * settings. Flow control is enabled or disabled in the configuration 1331 * file. 1332 * High-water mark is set down from the top of the rx fifo (not 1333 * sensitive to max_frame_size) and low-water is set just below 1334 * high-water mark. 1335 * The high water mark must be low enough to fit one full frame above 1336 * it in the rx FIFO. Should be the lower of: 1337 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1338 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1339 * Rx FIFO size minus one full frame. 1340 */ 1341 high_water = min(((pba << 10) * 9 / 10), 1342 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 || 1343 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ? 1344 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1345 ((pba << 10) - Adapter->max_frame_size))); 1346 1347 hw->fc.high_water = high_water & 0xFFF8; 1348 hw->fc.low_water = hw->fc.high_water - 8; 1349 1350 if (hw->mac.type == e1000_80003es2lan) 1351 hw->fc.pause_time = 0xFFFF; 1352 else 1353 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1354 hw->fc.send_xon = B_TRUE; 1355 1356 /* 1357 * Reset the adapter hardware the second time. 1358 */ 1359 mutex_enter(&e1000g_nvm_lock); 1360 result = e1000_reset_hw(hw); 1361 mutex_exit(&e1000g_nvm_lock); 1362 1363 if (result != E1000_SUCCESS) { 1364 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1365 goto init_fail; 1366 } 1367 1368 /* disable wakeup control by default */ 1369 if (hw->mac.type >= e1000_82544) 1370 E1000_WRITE_REG(hw, E1000_WUC, 0); 1371 1372 /* 1373 * MWI should be disabled on 82546. 1374 */ 1375 if (hw->mac.type == e1000_82546) 1376 e1000_pci_clear_mwi(hw); 1377 else 1378 e1000_pci_set_mwi(hw); 1379 1380 /* 1381 * Configure/Initialize hardware 1382 */ 1383 mutex_enter(&e1000g_nvm_lock); 1384 result = e1000_init_hw(hw); 1385 mutex_exit(&e1000g_nvm_lock); 1386 1387 if (result < E1000_SUCCESS) { 1388 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1389 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1390 goto init_fail; 1391 } 1392 1393 /* 1394 * Restore LED settings to the default from EEPROM 1395 * to meet the standard for Sun platforms. 1396 */ 1397 if ((hw->mac.type != e1000_82541) && 1398 (hw->mac.type != e1000_82541_rev_2) && 1399 (hw->mac.type != e1000_82547) && 1400 (hw->mac.type != e1000_82547_rev_2)) 1401 (void) e1000_cleanup_led(hw); 1402 1403 /* Disable Smart Power Down */ 1404 phy_spd_state(hw, B_FALSE); 1405 1406 /* Make sure driver has control */ 1407 e1000g_get_driver_control(hw); 1408 1409 /* 1410 * Initialize unicast addresses. 1411 */ 1412 e1000g_init_unicst(Adapter); 1413 1414 /* 1415 * Setup and initialize the mctable structures. After this routine 1416 * completes Multicast table will be set 1417 */ 1418 e1000g_setup_multicast(Adapter); 1419 msec_delay(5); 1420 1421 /* 1422 * Implement Adaptive IFS 1423 */ 1424 e1000_reset_adaptive(hw); 1425 1426 /* Setup Interrupt Throttling Register */ 1427 if (hw->mac.type >= e1000_82540) { 1428 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1429 } else 1430 Adapter->intr_adaptive = B_FALSE; 1431 1432 /* Start the timer for link setup */ 1433 if (hw->mac.autoneg) 1434 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1435 else 1436 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1437 1438 mutex_enter(&Adapter->link_lock); 1439 if (hw->phy.autoneg_wait_to_complete) { 1440 Adapter->link_complete = B_TRUE; 1441 } else { 1442 Adapter->link_complete = B_FALSE; 1443 Adapter->link_tid = timeout(e1000g_link_timer, 1444 (void *)Adapter, link_timeout); 1445 } 1446 mutex_exit(&Adapter->link_lock); 1447 1448 /* Enable PCI-Ex master */ 1449 if (hw->bus.type == e1000_bus_type_pci_express) { 1450 e1000_enable_pciex_master(hw); 1451 } 1452 1453 /* Save the state of the phy */ 1454 e1000g_get_phy_state(Adapter); 1455 1456 e1000g_param_sync(Adapter); 1457 1458 Adapter->init_count++; 1459 1460 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1461 goto init_fail; 1462 } 1463 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1464 goto init_fail; 1465 } 1466 1467 Adapter->poll_mode = e1000g_poll_mode; 1468 1469 return (DDI_SUCCESS); 1470 1471 init_fail: 1472 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1473 return (DDI_FAILURE); 1474 } 1475 1476 /* 1477 * Check if the link is up 1478 */ 1479 static boolean_t 1480 e1000g_link_up(struct e1000g *Adapter) 1481 { 1482 struct e1000_hw *hw; 1483 boolean_t link_up; 1484 1485 hw = &Adapter->shared; 1486 1487 (void) e1000_check_for_link(hw); 1488 1489 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1490 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1491 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1492 (hw->mac.serdes_has_link))) { 1493 link_up = B_TRUE; 1494 } else { 1495 link_up = B_FALSE; 1496 } 1497 1498 return (link_up); 1499 } 1500 1501 static void 1502 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1503 { 1504 struct iocblk *iocp; 1505 struct e1000g *e1000gp; 1506 enum ioc_reply status; 1507 1508 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1509 iocp->ioc_error = 0; 1510 e1000gp = (struct e1000g *)arg; 1511 1512 ASSERT(e1000gp); 1513 if (e1000gp == NULL) { 1514 miocnak(q, mp, 0, EINVAL); 1515 return; 1516 } 1517 1518 rw_enter(&e1000gp->chip_lock, RW_READER); 1519 if (e1000gp->e1000g_state & E1000G_SUSPENDED) { 1520 rw_exit(&e1000gp->chip_lock); 1521 miocnak(q, mp, 0, EINVAL); 1522 return; 1523 } 1524 rw_exit(&e1000gp->chip_lock); 1525 1526 switch (iocp->ioc_cmd) { 1527 1528 case LB_GET_INFO_SIZE: 1529 case LB_GET_INFO: 1530 case LB_GET_MODE: 1531 case LB_SET_MODE: 1532 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1533 break; 1534 1535 1536 #ifdef E1000G_DEBUG 1537 case E1000G_IOC_REG_PEEK: 1538 case E1000G_IOC_REG_POKE: 1539 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1540 break; 1541 case E1000G_IOC_CHIP_RESET: 1542 e1000gp->reset_count++; 1543 if (e1000g_reset_adapter(e1000gp)) 1544 status = IOC_ACK; 1545 else 1546 status = IOC_INVAL; 1547 break; 1548 #endif 1549 default: 1550 status = IOC_INVAL; 1551 break; 1552 } 1553 1554 /* 1555 * Decide how to reply 1556 */ 1557 switch (status) { 1558 default: 1559 case IOC_INVAL: 1560 /* 1561 * Error, reply with a NAK and EINVAL or the specified error 1562 */ 1563 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1564 EINVAL : iocp->ioc_error); 1565 break; 1566 1567 case IOC_DONE: 1568 /* 1569 * OK, reply already sent 1570 */ 1571 break; 1572 1573 case IOC_ACK: 1574 /* 1575 * OK, reply with an ACK 1576 */ 1577 miocack(q, mp, 0, 0); 1578 break; 1579 1580 case IOC_REPLY: 1581 /* 1582 * OK, send prepared reply as ACK or NAK 1583 */ 1584 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1585 M_IOCACK : M_IOCNAK; 1586 qreply(q, mp); 1587 break; 1588 } 1589 } 1590 1591 /* 1592 * The default value of e1000g_poll_mode == 0 assumes that the NIC is 1593 * capable of supporting only one interrupt and we shouldn't disable 1594 * the physical interrupt. In this case we let the interrupt come and 1595 * we queue the packets in the rx ring itself in case we are in polling 1596 * mode (better latency but slightly lower performance and a very 1597 * high intrrupt count in mpstat which is harmless). 1598 * 1599 * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt 1600 * which can be disabled in poll mode. This gives better overall 1601 * throughput (compared to the mode above), shows very low interrupt 1602 * count but has slightly higher latency since we pick the packets when 1603 * the poll thread does polling. 1604 * 1605 * Currently, this flag should be enabled only while doing performance 1606 * measurement or when it can be guaranteed that entire NIC going 1607 * in poll mode will not harm any traffic like cluster heartbeat etc. 1608 */ 1609 int e1000g_poll_mode = 0; 1610 1611 /* 1612 * Called from the upper layers when driver is in polling mode to 1613 * pick up any queued packets. Care should be taken to not block 1614 * this thread. 1615 */ 1616 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup) 1617 { 1618 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)arg; 1619 mblk_t *mp = NULL; 1620 mblk_t *tail; 1621 struct e1000g *adapter; 1622 1623 adapter = rx_ring->adapter; 1624 1625 rw_enter(&adapter->chip_lock, RW_READER); 1626 1627 if (adapter->e1000g_state & E1000G_SUSPENDED) { 1628 rw_exit(&adapter->chip_lock); 1629 return (NULL); 1630 } 1631 1632 mutex_enter(&rx_ring->rx_lock); 1633 mp = e1000g_receive(rx_ring, &tail, bytes_to_pickup); 1634 mutex_exit(&rx_ring->rx_lock); 1635 rw_exit(&adapter->chip_lock); 1636 return (mp); 1637 } 1638 1639 static int 1640 e1000g_m_start(void *arg) 1641 { 1642 struct e1000g *Adapter = (struct e1000g *)arg; 1643 1644 rw_enter(&Adapter->chip_lock, RW_WRITER); 1645 1646 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1647 rw_exit(&Adapter->chip_lock); 1648 return (ECANCELED); 1649 } 1650 1651 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1652 rw_exit(&Adapter->chip_lock); 1653 return (ENOTACTIVE); 1654 } 1655 1656 Adapter->e1000g_state |= E1000G_STARTED; 1657 1658 rw_exit(&Adapter->chip_lock); 1659 1660 /* Enable and start the watchdog timer */ 1661 enable_watchdog_timer(Adapter); 1662 1663 return (0); 1664 } 1665 1666 static int 1667 e1000g_start(struct e1000g *Adapter, boolean_t global) 1668 { 1669 if (global) { 1670 /* Allocate dma resources for descriptors and buffers */ 1671 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1672 e1000g_log(Adapter, CE_WARN, 1673 "Alloc DMA resources failed"); 1674 return (DDI_FAILURE); 1675 } 1676 Adapter->rx_buffer_setup = B_FALSE; 1677 } 1678 1679 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1680 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1681 e1000g_log(Adapter, CE_WARN, 1682 "Adapter initialization failed"); 1683 if (global) 1684 e1000g_release_dma_resources(Adapter); 1685 return (DDI_FAILURE); 1686 } 1687 } 1688 1689 /* Setup and initialize the transmit structures */ 1690 e1000g_tx_setup(Adapter); 1691 msec_delay(5); 1692 1693 /* Setup and initialize the receive structures */ 1694 e1000g_rx_setup(Adapter); 1695 msec_delay(5); 1696 1697 /* Restore the e1000g promiscuous mode */ 1698 e1000g_restore_promisc(Adapter); 1699 1700 e1000g_mask_interrupt(Adapter); 1701 1702 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1703 1704 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1705 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1706 return (DDI_FAILURE); 1707 } 1708 1709 return (DDI_SUCCESS); 1710 } 1711 1712 static void 1713 e1000g_m_stop(void *arg) 1714 { 1715 struct e1000g *Adapter = (struct e1000g *)arg; 1716 1717 /* Drain tx sessions */ 1718 (void) e1000g_tx_drain(Adapter); 1719 1720 rw_enter(&Adapter->chip_lock, RW_WRITER); 1721 1722 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1723 rw_exit(&Adapter->chip_lock); 1724 return; 1725 } 1726 Adapter->e1000g_state &= ~E1000G_STARTED; 1727 e1000g_stop(Adapter, B_TRUE); 1728 1729 rw_exit(&Adapter->chip_lock); 1730 1731 /* Disable and stop all the timers */ 1732 disable_watchdog_timer(Adapter); 1733 stop_link_timer(Adapter); 1734 stop_82547_timer(Adapter->tx_ring); 1735 } 1736 1737 static void 1738 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1739 { 1740 int result; 1741 1742 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1743 1744 /* Stop the chip and release pending resources */ 1745 1746 /* Tell firmware driver is no longer in control */ 1747 e1000g_release_driver_control(&Adapter->shared); 1748 1749 e1000g_clear_all_interrupts(Adapter); 1750 1751 mutex_enter(&e1000g_nvm_lock); 1752 result = e1000_reset_hw(&Adapter->shared); 1753 mutex_exit(&e1000g_nvm_lock); 1754 1755 if (result != E1000_SUCCESS) { 1756 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1757 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1758 } 1759 1760 /* Release resources still held by the TX descriptors */ 1761 e1000g_tx_clean(Adapter); 1762 1763 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1764 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1765 1766 /* Clean the pending rx jumbo packet fragment */ 1767 e1000g_rx_clean(Adapter); 1768 1769 if (global) 1770 e1000g_release_dma_resources(Adapter); 1771 } 1772 1773 static void 1774 e1000g_rx_clean(struct e1000g *Adapter) 1775 { 1776 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 1777 1778 if (rx_ring->rx_mblk != NULL) { 1779 freemsg(rx_ring->rx_mblk); 1780 rx_ring->rx_mblk = NULL; 1781 rx_ring->rx_mblk_tail = NULL; 1782 rx_ring->rx_mblk_len = 0; 1783 } 1784 } 1785 1786 static void 1787 e1000g_tx_clean(struct e1000g *Adapter) 1788 { 1789 e1000g_tx_ring_t *tx_ring; 1790 p_tx_sw_packet_t packet; 1791 mblk_t *mp; 1792 mblk_t *nmp; 1793 uint32_t packet_count; 1794 1795 tx_ring = Adapter->tx_ring; 1796 1797 /* 1798 * Here we don't need to protect the lists using 1799 * the usedlist_lock and freelist_lock, for they 1800 * have been protected by the chip_lock. 1801 */ 1802 mp = NULL; 1803 nmp = NULL; 1804 packet_count = 0; 1805 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1806 while (packet != NULL) { 1807 if (packet->mp != NULL) { 1808 /* Assemble the message chain */ 1809 if (mp == NULL) { 1810 mp = packet->mp; 1811 nmp = packet->mp; 1812 } else { 1813 nmp->b_next = packet->mp; 1814 nmp = packet->mp; 1815 } 1816 /* Disconnect the message from the sw packet */ 1817 packet->mp = NULL; 1818 } 1819 1820 e1000g_free_tx_swpkt(packet); 1821 packet_count++; 1822 1823 packet = (p_tx_sw_packet_t) 1824 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1825 } 1826 1827 if (mp != NULL) 1828 freemsgchain(mp); 1829 1830 if (packet_count > 0) { 1831 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1832 QUEUE_INIT_LIST(&tx_ring->used_list); 1833 1834 /* Setup TX descriptor pointers */ 1835 tx_ring->tbd_next = tx_ring->tbd_first; 1836 tx_ring->tbd_oldest = tx_ring->tbd_first; 1837 1838 /* Setup our HW Tx Head & Tail descriptor pointers */ 1839 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1840 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1841 } 1842 } 1843 1844 static boolean_t 1845 e1000g_tx_drain(struct e1000g *Adapter) 1846 { 1847 int i; 1848 boolean_t done; 1849 e1000g_tx_ring_t *tx_ring; 1850 1851 tx_ring = Adapter->tx_ring; 1852 1853 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1854 for (i = 0; i < TX_DRAIN_TIME; i++) { 1855 mutex_enter(&tx_ring->usedlist_lock); 1856 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1857 mutex_exit(&tx_ring->usedlist_lock); 1858 1859 if (done) 1860 break; 1861 1862 msec_delay(1); 1863 } 1864 1865 return (done); 1866 } 1867 1868 static boolean_t 1869 e1000g_rx_drain(struct e1000g *Adapter) 1870 { 1871 e1000g_rx_ring_t *rx_ring; 1872 p_rx_sw_packet_t packet; 1873 boolean_t done; 1874 1875 rx_ring = Adapter->rx_ring; 1876 done = B_TRUE; 1877 1878 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 1879 1880 while (rx_ring->pending_list != NULL) { 1881 packet = rx_ring->pending_list; 1882 rx_ring->pending_list = 1883 rx_ring->pending_list->next; 1884 1885 if (packet->flag == E1000G_RX_SW_STOP) { 1886 packet->flag = E1000G_RX_SW_DETACH; 1887 done = B_FALSE; 1888 } else { 1889 ASSERT(packet->flag == E1000G_RX_SW_FREE); 1890 ASSERT(packet->mp == NULL); 1891 e1000g_free_rx_sw_packet(packet); 1892 } 1893 } 1894 1895 rw_exit(&e1000g_rx_detach_lock); 1896 1897 return (done); 1898 } 1899 1900 static boolean_t 1901 e1000g_reset_adapter(struct e1000g *Adapter) 1902 { 1903 /* Disable and stop all the timers */ 1904 disable_watchdog_timer(Adapter); 1905 stop_link_timer(Adapter); 1906 stop_82547_timer(Adapter->tx_ring); 1907 1908 rw_enter(&Adapter->chip_lock, RW_WRITER); 1909 1910 e1000g_stop(Adapter, B_FALSE); 1911 1912 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1913 rw_exit(&Adapter->chip_lock); 1914 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1915 return (B_FALSE); 1916 } 1917 1918 rw_exit(&Adapter->chip_lock); 1919 1920 /* Enable and start the watchdog timer */ 1921 enable_watchdog_timer(Adapter); 1922 1923 return (B_TRUE); 1924 } 1925 1926 boolean_t 1927 e1000g_global_reset(struct e1000g *Adapter) 1928 { 1929 /* Disable and stop all the timers */ 1930 disable_watchdog_timer(Adapter); 1931 stop_link_timer(Adapter); 1932 stop_82547_timer(Adapter->tx_ring); 1933 1934 rw_enter(&Adapter->chip_lock, RW_WRITER); 1935 1936 e1000g_stop(Adapter, B_TRUE); 1937 1938 Adapter->init_count = 0; 1939 1940 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1941 rw_exit(&Adapter->chip_lock); 1942 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1943 return (B_FALSE); 1944 } 1945 1946 rw_exit(&Adapter->chip_lock); 1947 1948 /* Enable and start the watchdog timer */ 1949 enable_watchdog_timer(Adapter); 1950 1951 return (B_TRUE); 1952 } 1953 1954 /* 1955 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 1956 * 1957 * This interrupt service routine is for PCI-Express adapters. 1958 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 1959 * bit is set. 1960 */ 1961 static uint_t 1962 e1000g_intr_pciexpress(caddr_t arg) 1963 { 1964 struct e1000g *Adapter; 1965 uint32_t icr; 1966 1967 Adapter = (struct e1000g *)(uintptr_t)arg; 1968 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1969 1970 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1971 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1972 1973 if (icr & E1000_ICR_INT_ASSERTED) { 1974 /* 1975 * E1000_ICR_INT_ASSERTED bit was set: 1976 * Read(Clear) the ICR, claim this interrupt, 1977 * look for work to do. 1978 */ 1979 e1000g_intr_work(Adapter, icr); 1980 return (DDI_INTR_CLAIMED); 1981 } else { 1982 /* 1983 * E1000_ICR_INT_ASSERTED bit was not set: 1984 * Don't claim this interrupt, return immediately. 1985 */ 1986 return (DDI_INTR_UNCLAIMED); 1987 } 1988 } 1989 1990 /* 1991 * e1000g_intr - ISR for PCI/PCI-X chipsets 1992 * 1993 * This interrupt service routine is for PCI/PCI-X adapters. 1994 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 1995 * bit is set or not. 1996 */ 1997 static uint_t 1998 e1000g_intr(caddr_t arg) 1999 { 2000 struct e1000g *Adapter; 2001 uint32_t icr; 2002 2003 Adapter = (struct e1000g *)(uintptr_t)arg; 2004 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2005 2006 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2007 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2008 2009 if (icr) { 2010 /* 2011 * Any bit was set in ICR: 2012 * Read(Clear) the ICR, claim this interrupt, 2013 * look for work to do. 2014 */ 2015 e1000g_intr_work(Adapter, icr); 2016 return (DDI_INTR_CLAIMED); 2017 } else { 2018 /* 2019 * No bit was set in ICR: 2020 * Don't claim this interrupt, return immediately. 2021 */ 2022 return (DDI_INTR_UNCLAIMED); 2023 } 2024 } 2025 2026 /* 2027 * e1000g_intr_work - actual processing of ISR 2028 * 2029 * Read(clear) the ICR contents and call appropriate interrupt 2030 * processing routines. 2031 */ 2032 static void 2033 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 2034 { 2035 struct e1000_hw *hw; 2036 hw = &Adapter->shared; 2037 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2038 2039 Adapter->rx_pkt_cnt = 0; 2040 Adapter->tx_pkt_cnt = 0; 2041 2042 rw_enter(&Adapter->chip_lock, RW_READER); 2043 2044 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2045 rw_exit(&Adapter->chip_lock); 2046 return; 2047 } 2048 /* 2049 * Here we need to check the "e1000g_state" flag within the chip_lock to 2050 * ensure the receive routine will not execute when the adapter is 2051 * being reset. 2052 */ 2053 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2054 rw_exit(&Adapter->chip_lock); 2055 return; 2056 } 2057 2058 if (icr & E1000_ICR_RXT0) { 2059 mblk_t *mp = NULL; 2060 mblk_t *tail = NULL; 2061 e1000g_rx_ring_t *rx_ring; 2062 2063 rx_ring = Adapter->rx_ring; 2064 mutex_enter(&rx_ring->rx_lock); 2065 /* 2066 * Sometimes with legacy interrupts, it possible that 2067 * there is a single interrupt for Rx/Tx. In which 2068 * case, if poll flag is set, we shouldn't really 2069 * be doing Rx processing. 2070 */ 2071 if (!rx_ring->poll_flag) 2072 mp = e1000g_receive(rx_ring, &tail, 2073 E1000G_CHAIN_NO_LIMIT); 2074 mutex_exit(&rx_ring->rx_lock); 2075 rw_exit(&Adapter->chip_lock); 2076 if (mp != NULL) 2077 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2078 mp, rx_ring->ring_gen_num); 2079 } else 2080 rw_exit(&Adapter->chip_lock); 2081 2082 if (icr & E1000_ICR_TXDW) { 2083 if (!Adapter->tx_intr_enable) 2084 e1000g_clear_tx_interrupt(Adapter); 2085 2086 /* Recycle the tx descriptors */ 2087 rw_enter(&Adapter->chip_lock, RW_READER); 2088 (void) e1000g_recycle(tx_ring); 2089 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 2090 rw_exit(&Adapter->chip_lock); 2091 2092 if (tx_ring->resched_needed && 2093 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 2094 tx_ring->resched_needed = B_FALSE; 2095 mac_tx_update(Adapter->mh); 2096 E1000G_STAT(tx_ring->stat_reschedule); 2097 } 2098 } 2099 2100 /* 2101 * The Receive Sequence errors RXSEQ and the link status change LSC 2102 * are checked to detect that the cable has been pulled out. For 2103 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 2104 * are an indication that cable is not connected. 2105 */ 2106 if ((icr & E1000_ICR_RXSEQ) || 2107 (icr & E1000_ICR_LSC) || 2108 (icr & E1000_ICR_GPI_EN1)) { 2109 boolean_t link_changed; 2110 timeout_id_t tid = 0; 2111 2112 stop_watchdog_timer(Adapter); 2113 2114 rw_enter(&Adapter->chip_lock, RW_WRITER); 2115 2116 /* 2117 * Because we got a link-status-change interrupt, force 2118 * e1000_check_for_link() to look at phy 2119 */ 2120 Adapter->shared.mac.get_link_status = B_TRUE; 2121 2122 /* e1000g_link_check takes care of link status change */ 2123 link_changed = e1000g_link_check(Adapter); 2124 2125 /* Get new phy state */ 2126 e1000g_get_phy_state(Adapter); 2127 2128 /* 2129 * If the link timer has not timed out, we'll not notify 2130 * the upper layer with any link state until the link is up. 2131 */ 2132 if (link_changed && !Adapter->link_complete) { 2133 if (Adapter->link_state == LINK_STATE_UP) { 2134 mutex_enter(&Adapter->link_lock); 2135 Adapter->link_complete = B_TRUE; 2136 tid = Adapter->link_tid; 2137 Adapter->link_tid = 0; 2138 mutex_exit(&Adapter->link_lock); 2139 } else { 2140 link_changed = B_FALSE; 2141 } 2142 } 2143 rw_exit(&Adapter->chip_lock); 2144 2145 if (link_changed) { 2146 if (tid != 0) 2147 (void) untimeout(tid); 2148 2149 /* 2150 * Workaround for esb2. Data stuck in fifo on a link 2151 * down event. Stop receiver here and reset in watchdog. 2152 */ 2153 if ((Adapter->link_state == LINK_STATE_DOWN) && 2154 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2155 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2156 E1000_WRITE_REG(hw, E1000_RCTL, 2157 rctl & ~E1000_RCTL_EN); 2158 e1000g_log(Adapter, CE_WARN, 2159 "ESB2 receiver disabled"); 2160 Adapter->esb2_workaround = B_TRUE; 2161 } 2162 2163 mac_link_update(Adapter->mh, Adapter->link_state); 2164 } 2165 2166 start_watchdog_timer(Adapter); 2167 } 2168 } 2169 2170 static void 2171 e1000g_init_unicst(struct e1000g *Adapter) 2172 { 2173 struct e1000_hw *hw; 2174 int slot; 2175 2176 hw = &Adapter->shared; 2177 2178 if (Adapter->init_count == 0) { 2179 /* Initialize the multiple unicast addresses */ 2180 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2181 2182 /* Workaround for an erratum of 82571 chipst */ 2183 if ((hw->mac.type == e1000_82571) && 2184 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2185 Adapter->unicst_total--; 2186 2187 Adapter->unicst_avail = Adapter->unicst_total; 2188 2189 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2190 /* Clear both the flag and MAC address */ 2191 Adapter->unicst_addr[slot].reg.high = 0; 2192 Adapter->unicst_addr[slot].reg.low = 0; 2193 } 2194 } else { 2195 /* Workaround for an erratum of 82571 chipst */ 2196 if ((hw->mac.type == e1000_82571) && 2197 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2198 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2199 2200 /* Re-configure the RAR registers */ 2201 for (slot = 0; slot < Adapter->unicst_total; slot++) 2202 if (Adapter->unicst_addr[slot].mac.set == 1) 2203 e1000_rar_set(hw, 2204 Adapter->unicst_addr[slot].mac.addr, slot); 2205 } 2206 2207 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2208 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2209 } 2210 2211 static int 2212 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2213 int slot) 2214 { 2215 struct e1000_hw *hw; 2216 2217 hw = &Adapter->shared; 2218 2219 /* 2220 * The first revision of Wiseman silicon (rev 2.0) has an errata 2221 * that requires the receiver to be in reset when any of the 2222 * receive address registers (RAR regs) are accessed. The first 2223 * rev of Wiseman silicon also requires MWI to be disabled when 2224 * a global reset or a receive reset is issued. So before we 2225 * initialize the RARs, we check the rev of the Wiseman controller 2226 * and work around any necessary HW errata. 2227 */ 2228 if ((hw->mac.type == e1000_82542) && 2229 (hw->revision_id == E1000_REVISION_2)) { 2230 e1000_pci_clear_mwi(hw); 2231 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2232 msec_delay(5); 2233 } 2234 if (mac_addr == NULL) { 2235 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0); 2236 E1000_WRITE_FLUSH(hw); 2237 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0); 2238 E1000_WRITE_FLUSH(hw); 2239 /* Clear both the flag and MAC address */ 2240 Adapter->unicst_addr[slot].reg.high = 0; 2241 Adapter->unicst_addr[slot].reg.low = 0; 2242 } else { 2243 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, 2244 ETHERADDRL); 2245 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2246 Adapter->unicst_addr[slot].mac.set = 1; 2247 } 2248 2249 /* Workaround for an erratum of 82571 chipst */ 2250 if (slot == 0) { 2251 if ((hw->mac.type == e1000_82571) && 2252 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2253 if (mac_addr == NULL) { 2254 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2255 slot << 1, 0); 2256 E1000_WRITE_FLUSH(hw); 2257 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2258 (slot << 1) + 1, 0); 2259 E1000_WRITE_FLUSH(hw); 2260 } else { 2261 e1000_rar_set(hw, (uint8_t *)mac_addr, 2262 LAST_RAR_ENTRY); 2263 } 2264 } 2265 2266 /* 2267 * If we are using Wiseman rev 2.0 silicon, we will have previously 2268 * put the receive in reset, and disabled MWI, to work around some 2269 * HW errata. Now we should take the receiver out of reset, and 2270 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2271 */ 2272 if ((hw->mac.type == e1000_82542) && 2273 (hw->revision_id == E1000_REVISION_2)) { 2274 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2275 msec_delay(1); 2276 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2277 e1000_pci_set_mwi(hw); 2278 e1000g_rx_setup(Adapter); 2279 } 2280 2281 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2282 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2283 return (EIO); 2284 } 2285 2286 return (0); 2287 } 2288 2289 static int 2290 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2291 { 2292 struct e1000_hw *hw = &Adapter->shared; 2293 int res = 0; 2294 2295 if ((multiaddr[0] & 01) == 0) { 2296 res = EINVAL; 2297 goto done; 2298 } 2299 2300 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2301 res = ENOENT; 2302 goto done; 2303 } 2304 2305 bcopy(multiaddr, 2306 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2307 Adapter->mcast_count++; 2308 2309 /* 2310 * Update the MC table in the hardware 2311 */ 2312 e1000g_clear_interrupt(Adapter); 2313 2314 e1000g_setup_multicast(Adapter); 2315 2316 if ((hw->mac.type == e1000_82542) && 2317 (hw->revision_id == E1000_REVISION_2)) 2318 e1000g_rx_setup(Adapter); 2319 2320 e1000g_mask_interrupt(Adapter); 2321 2322 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2323 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2324 res = EIO; 2325 } 2326 2327 done: 2328 return (res); 2329 } 2330 2331 static int 2332 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2333 { 2334 struct e1000_hw *hw = &Adapter->shared; 2335 unsigned i; 2336 2337 for (i = 0; i < Adapter->mcast_count; i++) { 2338 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2339 ETHERADDRL) == 0) { 2340 for (i++; i < Adapter->mcast_count; i++) { 2341 Adapter->mcast_table[i - 1] = 2342 Adapter->mcast_table[i]; 2343 } 2344 Adapter->mcast_count--; 2345 break; 2346 } 2347 } 2348 2349 /* 2350 * Update the MC table in the hardware 2351 */ 2352 e1000g_clear_interrupt(Adapter); 2353 2354 e1000g_setup_multicast(Adapter); 2355 2356 if ((hw->mac.type == e1000_82542) && 2357 (hw->revision_id == E1000_REVISION_2)) 2358 e1000g_rx_setup(Adapter); 2359 2360 e1000g_mask_interrupt(Adapter); 2361 2362 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2363 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2364 return (EIO); 2365 } 2366 2367 return (0); 2368 } 2369 2370 /* 2371 * e1000g_setup_multicast - setup multicast data structures 2372 * 2373 * This routine initializes all of the multicast related structures. 2374 */ 2375 void 2376 e1000g_setup_multicast(struct e1000g *Adapter) 2377 { 2378 uint8_t *mc_addr_list; 2379 uint32_t mc_addr_count; 2380 uint32_t rctl; 2381 struct e1000_hw *hw; 2382 2383 hw = &Adapter->shared; 2384 2385 /* 2386 * The e1000g has the ability to do perfect filtering of 16 2387 * addresses. The driver uses one of the e1000g's 16 receive 2388 * address registers for its node/network/mac/individual address. 2389 * So, we have room for up to 15 multicast addresses in the CAM, 2390 * additional MC addresses are handled by the MTA (Multicast Table 2391 * Array) 2392 */ 2393 2394 rctl = E1000_READ_REG(hw, E1000_RCTL); 2395 2396 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2397 2398 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2399 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2400 "Adapter requested more than %d MC Addresses.\n", 2401 MAX_NUM_MULTICAST_ADDRESSES); 2402 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2403 } else { 2404 /* 2405 * Set the number of MC addresses that we are being 2406 * requested to use 2407 */ 2408 mc_addr_count = Adapter->mcast_count; 2409 } 2410 /* 2411 * The Wiseman 2.0 silicon has an errata by which the receiver will 2412 * hang while writing to the receive address registers if the receiver 2413 * is not in reset before writing to the registers. Updating the RAR 2414 * is done during the setting up of the multicast table, hence the 2415 * receiver has to be put in reset before updating the multicast table 2416 * and then taken out of reset at the end 2417 */ 2418 /* 2419 * if WMI was enabled then dis able it before issueing the global 2420 * reset to the hardware. 2421 */ 2422 /* 2423 * Only required for WISEMAN_2_0 2424 */ 2425 if ((hw->mac.type == e1000_82542) && 2426 (hw->revision_id == E1000_REVISION_2)) { 2427 e1000_pci_clear_mwi(hw); 2428 /* 2429 * The e1000g must be in reset before changing any RA 2430 * registers. Reset receive unit. The chip will remain in 2431 * the reset state until software explicitly restarts it. 2432 */ 2433 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2434 /* Allow receiver time to go in to reset */ 2435 msec_delay(5); 2436 } 2437 2438 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2439 Adapter->unicst_total, hw->mac.rar_entry_count); 2440 2441 /* 2442 * Only for Wiseman_2_0 2443 * If MWI was enabled then re-enable it after issueing (as we 2444 * disabled it up there) the receive reset command. 2445 * Wainwright does not have a receive reset command and only thing 2446 * close to it is global reset which will require tx setup also 2447 */ 2448 if ((hw->mac.type == e1000_82542) && 2449 (hw->revision_id == E1000_REVISION_2)) { 2450 /* 2451 * if WMI was enabled then reenable it after issueing the 2452 * global or receive reset to the hardware. 2453 */ 2454 2455 /* 2456 * Take receiver out of reset 2457 * clear E1000_RCTL_RST bit (and all others) 2458 */ 2459 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2460 msec_delay(5); 2461 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2462 e1000_pci_set_mwi(hw); 2463 } 2464 2465 /* 2466 * Restore original value 2467 */ 2468 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2469 } 2470 2471 int 2472 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2473 { 2474 struct e1000g *Adapter = (struct e1000g *)arg; 2475 int result; 2476 2477 rw_enter(&Adapter->chip_lock, RW_WRITER); 2478 2479 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2480 result = ECANCELED; 2481 goto done; 2482 } 2483 2484 result = (add) ? multicst_add(Adapter, addr) 2485 : multicst_remove(Adapter, addr); 2486 2487 done: 2488 rw_exit(&Adapter->chip_lock); 2489 return (result); 2490 2491 } 2492 2493 int 2494 e1000g_m_promisc(void *arg, boolean_t on) 2495 { 2496 struct e1000g *Adapter = (struct e1000g *)arg; 2497 uint32_t rctl; 2498 2499 rw_enter(&Adapter->chip_lock, RW_WRITER); 2500 2501 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2502 rw_exit(&Adapter->chip_lock); 2503 return (ECANCELED); 2504 } 2505 2506 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2507 2508 if (on) 2509 rctl |= 2510 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2511 else 2512 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2513 2514 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2515 2516 Adapter->e1000g_promisc = on; 2517 2518 rw_exit(&Adapter->chip_lock); 2519 2520 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2521 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2522 return (EIO); 2523 } 2524 2525 return (0); 2526 } 2527 2528 /* 2529 * Entry points to enable and disable interrupts at the granularity of 2530 * a group. 2531 * Turns the poll_mode for the whole adapter on and off to enable or 2532 * override the ring level polling control over the hardware interrupts. 2533 */ 2534 static int 2535 e1000g_rx_group_intr_enable(mac_intr_handle_t arg) 2536 { 2537 struct e1000g *adapter = (struct e1000g *)arg; 2538 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2539 2540 /* 2541 * Later interrupts at the granularity of the this ring will 2542 * invoke mac_rx() with NULL, indicating the need for another 2543 * software classification. 2544 * We have a single ring usable per adapter now, so we only need to 2545 * reset the rx handle for that one. 2546 * When more RX rings can be used, we should update each one of them. 2547 */ 2548 mutex_enter(&rx_ring->rx_lock); 2549 rx_ring->mrh = NULL; 2550 adapter->poll_mode = B_FALSE; 2551 mutex_exit(&rx_ring->rx_lock); 2552 return (0); 2553 } 2554 2555 static int 2556 e1000g_rx_group_intr_disable(mac_intr_handle_t arg) 2557 { 2558 struct e1000g *adapter = (struct e1000g *)arg; 2559 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2560 2561 mutex_enter(&rx_ring->rx_lock); 2562 2563 /* 2564 * Later interrupts at the granularity of the this ring will 2565 * invoke mac_rx() with the handle for this ring; 2566 */ 2567 adapter->poll_mode = B_TRUE; 2568 rx_ring->mrh = rx_ring->mrh_init; 2569 mutex_exit(&rx_ring->rx_lock); 2570 return (0); 2571 } 2572 2573 /* 2574 * Entry points to enable and disable interrupts at the granularity of 2575 * a ring. 2576 * adapter poll_mode controls whether we actually proceed with hardware 2577 * interrupt toggling. 2578 */ 2579 static int 2580 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh) 2581 { 2582 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2583 struct e1000g *adapter = rx_ring->adapter; 2584 struct e1000_hw *hw = &adapter->shared; 2585 uint32_t intr_mask; 2586 2587 rw_enter(&adapter->chip_lock, RW_READER); 2588 2589 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2590 rw_exit(&adapter->chip_lock); 2591 return (0); 2592 } 2593 2594 mutex_enter(&rx_ring->rx_lock); 2595 rx_ring->poll_flag = 0; 2596 mutex_exit(&rx_ring->rx_lock); 2597 2598 /* Rx interrupt enabling for MSI and legacy */ 2599 intr_mask = E1000_READ_REG(hw, E1000_IMS); 2600 intr_mask |= E1000_IMS_RXT0; 2601 E1000_WRITE_REG(hw, E1000_IMS, intr_mask); 2602 E1000_WRITE_FLUSH(hw); 2603 2604 /* Trigger a Rx interrupt to check Rx ring */ 2605 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2606 E1000_WRITE_FLUSH(hw); 2607 2608 rw_exit(&adapter->chip_lock); 2609 return (0); 2610 } 2611 2612 static int 2613 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh) 2614 { 2615 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2616 struct e1000g *adapter = rx_ring->adapter; 2617 struct e1000_hw *hw = &adapter->shared; 2618 2619 rw_enter(&adapter->chip_lock, RW_READER); 2620 2621 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2622 rw_exit(&adapter->chip_lock); 2623 return (0); 2624 } 2625 mutex_enter(&rx_ring->rx_lock); 2626 rx_ring->poll_flag = 1; 2627 mutex_exit(&rx_ring->rx_lock); 2628 2629 /* Rx interrupt disabling for MSI and legacy */ 2630 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0); 2631 E1000_WRITE_FLUSH(hw); 2632 2633 rw_exit(&adapter->chip_lock); 2634 return (0); 2635 } 2636 2637 /* 2638 * e1000g_unicst_find - Find the slot for the specified unicast address 2639 */ 2640 static int 2641 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr) 2642 { 2643 int slot; 2644 2645 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2646 if ((Adapter->unicst_addr[slot].mac.set == 1) && 2647 (bcmp(Adapter->unicst_addr[slot].mac.addr, 2648 mac_addr, ETHERADDRL) == 0)) 2649 return (slot); 2650 } 2651 2652 return (-1); 2653 } 2654 2655 /* 2656 * Entry points to add and remove a MAC address to a ring group. 2657 * The caller takes care of adding and removing the MAC addresses 2658 * to the filter via these two routines. 2659 */ 2660 2661 static int 2662 e1000g_addmac(void *arg, const uint8_t *mac_addr) 2663 { 2664 struct e1000g *Adapter = (struct e1000g *)arg; 2665 int slot, err; 2666 2667 rw_enter(&Adapter->chip_lock, RW_WRITER); 2668 2669 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2670 rw_exit(&Adapter->chip_lock); 2671 return (ECANCELED); 2672 } 2673 2674 if (e1000g_unicst_find(Adapter, mac_addr) != -1) { 2675 /* The same address is already in slot */ 2676 rw_exit(&Adapter->chip_lock); 2677 return (0); 2678 } 2679 2680 if (Adapter->unicst_avail == 0) { 2681 /* no slots available */ 2682 rw_exit(&Adapter->chip_lock); 2683 return (ENOSPC); 2684 } 2685 2686 /* Search for a free slot */ 2687 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2688 if (Adapter->unicst_addr[slot].mac.set == 0) 2689 break; 2690 } 2691 ASSERT(slot < Adapter->unicst_total); 2692 2693 err = e1000g_unicst_set(Adapter, mac_addr, slot); 2694 if (err == 0) 2695 Adapter->unicst_avail--; 2696 2697 rw_exit(&Adapter->chip_lock); 2698 2699 return (err); 2700 } 2701 2702 static int 2703 e1000g_remmac(void *arg, const uint8_t *mac_addr) 2704 { 2705 struct e1000g *Adapter = (struct e1000g *)arg; 2706 int slot, err; 2707 2708 rw_enter(&Adapter->chip_lock, RW_WRITER); 2709 2710 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2711 rw_exit(&Adapter->chip_lock); 2712 return (ECANCELED); 2713 } 2714 2715 slot = e1000g_unicst_find(Adapter, mac_addr); 2716 if (slot == -1) { 2717 rw_exit(&Adapter->chip_lock); 2718 return (EINVAL); 2719 } 2720 2721 ASSERT(Adapter->unicst_addr[slot].mac.set); 2722 2723 /* Clear this slot */ 2724 err = e1000g_unicst_set(Adapter, NULL, slot); 2725 if (err == 0) 2726 Adapter->unicst_avail++; 2727 2728 rw_exit(&Adapter->chip_lock); 2729 2730 return (err); 2731 } 2732 2733 static int 2734 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num) 2735 { 2736 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh; 2737 2738 mutex_enter(&rx_ring->rx_lock); 2739 rx_ring->ring_gen_num = mr_gen_num; 2740 mutex_exit(&rx_ring->rx_lock); 2741 return (0); 2742 } 2743 2744 /* 2745 * Callback funtion for MAC layer to register all rings. 2746 * 2747 * The hardware supports a single group with currently only one ring 2748 * available. 2749 * Though not offering virtualization ability per se, exposing the 2750 * group/ring still enables the polling and interrupt toggling. 2751 */ 2752 void 2753 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index, 2754 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh) 2755 { 2756 struct e1000g *Adapter = (struct e1000g *)arg; 2757 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 2758 mac_intr_t *mintr; 2759 2760 /* 2761 * We advertised only RX group/rings, so the MAC framework shouldn't 2762 * ask for any thing else. 2763 */ 2764 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0); 2765 2766 rx_ring->mrh = rx_ring->mrh_init = rh; 2767 infop->mri_driver = (mac_ring_driver_t)rx_ring; 2768 infop->mri_start = e1000g_ring_start; 2769 infop->mri_stop = NULL; 2770 infop->mri_poll = e1000g_poll_ring; 2771 2772 /* Ring level interrupts */ 2773 mintr = &infop->mri_intr; 2774 mintr->mi_handle = (mac_intr_handle_t)rx_ring; 2775 mintr->mi_enable = e1000g_rx_ring_intr_enable; 2776 mintr->mi_disable = e1000g_rx_ring_intr_disable; 2777 } 2778 2779 static void 2780 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index, 2781 mac_group_info_t *infop, mac_group_handle_t gh) 2782 { 2783 struct e1000g *Adapter = (struct e1000g *)arg; 2784 mac_intr_t *mintr; 2785 2786 /* 2787 * We advertised a single RX ring. Getting a request for anything else 2788 * signifies a bug in the MAC framework. 2789 */ 2790 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0); 2791 2792 Adapter->rx_group = gh; 2793 2794 infop->mgi_driver = (mac_group_driver_t)Adapter; 2795 infop->mgi_start = NULL; 2796 infop->mgi_stop = NULL; 2797 infop->mgi_addmac = e1000g_addmac; 2798 infop->mgi_remmac = e1000g_remmac; 2799 infop->mgi_count = 1; 2800 2801 /* Group level interrupts */ 2802 mintr = &infop->mgi_intr; 2803 mintr->mi_handle = (mac_intr_handle_t)Adapter; 2804 mintr->mi_enable = e1000g_rx_group_intr_enable; 2805 mintr->mi_disable = e1000g_rx_group_intr_disable; 2806 } 2807 2808 static boolean_t 2809 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2810 { 2811 struct e1000g *Adapter = (struct e1000g *)arg; 2812 2813 switch (cap) { 2814 case MAC_CAPAB_HCKSUM: { 2815 uint32_t *txflags = cap_data; 2816 2817 if (Adapter->tx_hcksum_enable) 2818 *txflags = HCKSUM_IPHDRCKSUM | 2819 HCKSUM_INET_PARTIAL; 2820 else 2821 return (B_FALSE); 2822 break; 2823 } 2824 2825 case MAC_CAPAB_LSO: { 2826 mac_capab_lso_t *cap_lso = cap_data; 2827 2828 if (Adapter->lso_enable) { 2829 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2830 cap_lso->lso_basic_tcp_ipv4.lso_max = 2831 E1000_LSO_MAXLEN; 2832 } else 2833 return (B_FALSE); 2834 break; 2835 } 2836 case MAC_CAPAB_RINGS: { 2837 mac_capab_rings_t *cap_rings = cap_data; 2838 2839 /* No TX rings exposed yet */ 2840 if (cap_rings->mr_type != MAC_RING_TYPE_RX) 2841 return (B_FALSE); 2842 2843 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC; 2844 cap_rings->mr_rnum = 1; 2845 cap_rings->mr_gnum = 1; 2846 cap_rings->mr_rget = e1000g_fill_ring; 2847 cap_rings->mr_gget = e1000g_fill_group; 2848 break; 2849 } 2850 default: 2851 return (B_FALSE); 2852 } 2853 return (B_TRUE); 2854 } 2855 2856 static boolean_t 2857 e1000g_param_locked(mac_prop_id_t pr_num) 2858 { 2859 /* 2860 * All en_* parameters are locked (read-only) while 2861 * the device is in any sort of loopback mode ... 2862 */ 2863 switch (pr_num) { 2864 case MAC_PROP_EN_1000FDX_CAP: 2865 case MAC_PROP_EN_1000HDX_CAP: 2866 case MAC_PROP_EN_100FDX_CAP: 2867 case MAC_PROP_EN_100HDX_CAP: 2868 case MAC_PROP_EN_10FDX_CAP: 2869 case MAC_PROP_EN_10HDX_CAP: 2870 case MAC_PROP_AUTONEG: 2871 case MAC_PROP_FLOWCTRL: 2872 return (B_TRUE); 2873 } 2874 return (B_FALSE); 2875 } 2876 2877 /* 2878 * callback function for set/get of properties 2879 */ 2880 static int 2881 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2882 uint_t pr_valsize, const void *pr_val) 2883 { 2884 struct e1000g *Adapter = arg; 2885 struct e1000_mac_info *mac = &Adapter->shared.mac; 2886 struct e1000_phy_info *phy = &Adapter->shared.phy; 2887 struct e1000_fc_info *fc = &Adapter->shared.fc; 2888 int err = 0; 2889 link_flowctrl_t flowctrl; 2890 uint32_t cur_mtu, new_mtu; 2891 uint64_t tmp = 0; 2892 2893 rw_enter(&Adapter->chip_lock, RW_WRITER); 2894 2895 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2896 rw_exit(&Adapter->chip_lock); 2897 return (ECANCELED); 2898 } 2899 2900 if (Adapter->loopback_mode != E1000G_LB_NONE && 2901 e1000g_param_locked(pr_num)) { 2902 /* 2903 * All en_* parameters are locked (read-only) 2904 * while the device is in any sort of loopback mode. 2905 */ 2906 rw_exit(&Adapter->chip_lock); 2907 return (EBUSY); 2908 } 2909 2910 switch (pr_num) { 2911 case MAC_PROP_EN_1000FDX_CAP: 2912 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 2913 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 2914 goto reset; 2915 case MAC_PROP_EN_100FDX_CAP: 2916 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 2917 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 2918 goto reset; 2919 case MAC_PROP_EN_100HDX_CAP: 2920 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 2921 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 2922 goto reset; 2923 case MAC_PROP_EN_10FDX_CAP: 2924 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 2925 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 2926 goto reset; 2927 case MAC_PROP_EN_10HDX_CAP: 2928 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 2929 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 2930 goto reset; 2931 case MAC_PROP_AUTONEG: 2932 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 2933 goto reset; 2934 case MAC_PROP_FLOWCTRL: 2935 fc->send_xon = B_TRUE; 2936 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 2937 2938 switch (flowctrl) { 2939 default: 2940 err = EINVAL; 2941 break; 2942 case LINK_FLOWCTRL_NONE: 2943 fc->requested_mode = e1000_fc_none; 2944 break; 2945 case LINK_FLOWCTRL_RX: 2946 fc->requested_mode = e1000_fc_rx_pause; 2947 break; 2948 case LINK_FLOWCTRL_TX: 2949 fc->requested_mode = e1000_fc_tx_pause; 2950 break; 2951 case LINK_FLOWCTRL_BI: 2952 fc->requested_mode = e1000_fc_full; 2953 break; 2954 } 2955 reset: 2956 if (err == 0) { 2957 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 2958 err = EINVAL; 2959 } 2960 break; 2961 case MAC_PROP_ADV_1000FDX_CAP: 2962 case MAC_PROP_ADV_1000HDX_CAP: 2963 case MAC_PROP_ADV_100FDX_CAP: 2964 case MAC_PROP_ADV_100HDX_CAP: 2965 case MAC_PROP_ADV_10FDX_CAP: 2966 case MAC_PROP_ADV_10HDX_CAP: 2967 case MAC_PROP_EN_1000HDX_CAP: 2968 case MAC_PROP_STATUS: 2969 case MAC_PROP_SPEED: 2970 case MAC_PROP_DUPLEX: 2971 err = ENOTSUP; /* read-only prop. Can't set this. */ 2972 break; 2973 case MAC_PROP_MTU: 2974 cur_mtu = Adapter->default_mtu; 2975 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 2976 if (new_mtu == cur_mtu) { 2977 err = 0; 2978 break; 2979 } 2980 2981 tmp = new_mtu + sizeof (struct ether_vlan_header) + 2982 ETHERFCSL; 2983 if ((tmp < DEFAULT_FRAME_SIZE) || 2984 (tmp > MAXIMUM_FRAME_SIZE)) { 2985 err = EINVAL; 2986 break; 2987 } 2988 2989 /* ich8 does not support jumbo frames */ 2990 if ((mac->type == e1000_ich8lan) && 2991 (tmp > DEFAULT_FRAME_SIZE)) { 2992 err = EINVAL; 2993 break; 2994 } 2995 /* ich9 does not do jumbo frames on one phy type */ 2996 if ((mac->type == e1000_ich9lan) && 2997 (phy->type == e1000_phy_ife) && 2998 (tmp > DEFAULT_FRAME_SIZE)) { 2999 err = EINVAL; 3000 break; 3001 } 3002 if (Adapter->e1000g_state & E1000G_STARTED) { 3003 err = EBUSY; 3004 break; 3005 } 3006 3007 err = mac_maxsdu_update(Adapter->mh, new_mtu); 3008 if (err == 0) { 3009 Adapter->max_frame_size = (uint32_t)tmp; 3010 Adapter->default_mtu = new_mtu; 3011 e1000g_set_bufsize(Adapter); 3012 } 3013 break; 3014 case MAC_PROP_PRIVATE: 3015 err = e1000g_set_priv_prop(Adapter, pr_name, 3016 pr_valsize, pr_val); 3017 break; 3018 default: 3019 err = ENOTSUP; 3020 break; 3021 } 3022 rw_exit(&Adapter->chip_lock); 3023 return (err); 3024 } 3025 3026 static int 3027 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3028 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3029 { 3030 struct e1000g *Adapter = arg; 3031 struct e1000_fc_info *fc = &Adapter->shared.fc; 3032 int err = 0; 3033 link_flowctrl_t flowctrl; 3034 uint64_t tmp = 0; 3035 3036 if (pr_valsize == 0) 3037 return (EINVAL); 3038 3039 *perm = MAC_PROP_PERM_RW; 3040 3041 bzero(pr_val, pr_valsize); 3042 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 3043 return (e1000g_get_def_val(Adapter, pr_num, 3044 pr_valsize, pr_val)); 3045 } 3046 3047 switch (pr_num) { 3048 case MAC_PROP_DUPLEX: 3049 *perm = MAC_PROP_PERM_READ; 3050 if (pr_valsize >= sizeof (link_duplex_t)) { 3051 bcopy(&Adapter->link_duplex, pr_val, 3052 sizeof (link_duplex_t)); 3053 } else 3054 err = EINVAL; 3055 break; 3056 case MAC_PROP_SPEED: 3057 *perm = MAC_PROP_PERM_READ; 3058 if (pr_valsize >= sizeof (uint64_t)) { 3059 tmp = Adapter->link_speed * 1000000ull; 3060 bcopy(&tmp, pr_val, sizeof (tmp)); 3061 } else 3062 err = EINVAL; 3063 break; 3064 case MAC_PROP_AUTONEG: 3065 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 3066 break; 3067 case MAC_PROP_FLOWCTRL: 3068 if (pr_valsize >= sizeof (link_flowctrl_t)) { 3069 switch (fc->current_mode) { 3070 case e1000_fc_none: 3071 flowctrl = LINK_FLOWCTRL_NONE; 3072 break; 3073 case e1000_fc_rx_pause: 3074 flowctrl = LINK_FLOWCTRL_RX; 3075 break; 3076 case e1000_fc_tx_pause: 3077 flowctrl = LINK_FLOWCTRL_TX; 3078 break; 3079 case e1000_fc_full: 3080 flowctrl = LINK_FLOWCTRL_BI; 3081 break; 3082 } 3083 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 3084 } else 3085 err = EINVAL; 3086 break; 3087 case MAC_PROP_ADV_1000FDX_CAP: 3088 *perm = MAC_PROP_PERM_READ; 3089 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 3090 break; 3091 case MAC_PROP_EN_1000FDX_CAP: 3092 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 3093 break; 3094 case MAC_PROP_ADV_1000HDX_CAP: 3095 *perm = MAC_PROP_PERM_READ; 3096 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 3097 break; 3098 case MAC_PROP_EN_1000HDX_CAP: 3099 *perm = MAC_PROP_PERM_READ; 3100 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 3101 break; 3102 case MAC_PROP_ADV_100FDX_CAP: 3103 *perm = MAC_PROP_PERM_READ; 3104 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 3105 break; 3106 case MAC_PROP_EN_100FDX_CAP: 3107 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 3108 break; 3109 case MAC_PROP_ADV_100HDX_CAP: 3110 *perm = MAC_PROP_PERM_READ; 3111 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 3112 break; 3113 case MAC_PROP_EN_100HDX_CAP: 3114 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 3115 break; 3116 case MAC_PROP_ADV_10FDX_CAP: 3117 *perm = MAC_PROP_PERM_READ; 3118 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 3119 break; 3120 case MAC_PROP_EN_10FDX_CAP: 3121 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 3122 break; 3123 case MAC_PROP_ADV_10HDX_CAP: 3124 *perm = MAC_PROP_PERM_READ; 3125 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 3126 break; 3127 case MAC_PROP_EN_10HDX_CAP: 3128 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 3129 break; 3130 case MAC_PROP_ADV_100T4_CAP: 3131 case MAC_PROP_EN_100T4_CAP: 3132 *perm = MAC_PROP_PERM_READ; 3133 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 3134 break; 3135 case MAC_PROP_PRIVATE: 3136 err = e1000g_get_priv_prop(Adapter, pr_name, 3137 pr_flags, pr_valsize, pr_val, perm); 3138 break; 3139 default: 3140 err = ENOTSUP; 3141 break; 3142 } 3143 return (err); 3144 } 3145 3146 /* ARGSUSED2 */ 3147 static int 3148 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 3149 uint_t pr_valsize, const void *pr_val) 3150 { 3151 int err = 0; 3152 long result; 3153 struct e1000_hw *hw = &Adapter->shared; 3154 3155 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3156 if (pr_val == NULL) { 3157 err = EINVAL; 3158 return (err); 3159 } 3160 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3161 if (result < MIN_TX_BCOPY_THRESHOLD || 3162 result > MAX_TX_BCOPY_THRESHOLD) 3163 err = EINVAL; 3164 else { 3165 Adapter->tx_bcopy_thresh = (uint32_t)result; 3166 } 3167 return (err); 3168 } 3169 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3170 if (pr_val == NULL) { 3171 err = EINVAL; 3172 return (err); 3173 } 3174 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3175 if (result < 0 || result > 1) 3176 err = EINVAL; 3177 else { 3178 Adapter->tx_intr_enable = (result == 1) ? 3179 B_TRUE: B_FALSE; 3180 if (Adapter->tx_intr_enable) 3181 e1000g_mask_tx_interrupt(Adapter); 3182 else 3183 e1000g_clear_tx_interrupt(Adapter); 3184 if (e1000g_check_acc_handle( 3185 Adapter->osdep.reg_handle) != DDI_FM_OK) 3186 ddi_fm_service_impact(Adapter->dip, 3187 DDI_SERVICE_DEGRADED); 3188 } 3189 return (err); 3190 } 3191 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3192 if (pr_val == NULL) { 3193 err = EINVAL; 3194 return (err); 3195 } 3196 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3197 if (result < MIN_TX_INTR_DELAY || 3198 result > MAX_TX_INTR_DELAY) 3199 err = EINVAL; 3200 else { 3201 Adapter->tx_intr_delay = (uint32_t)result; 3202 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 3203 if (e1000g_check_acc_handle( 3204 Adapter->osdep.reg_handle) != DDI_FM_OK) 3205 ddi_fm_service_impact(Adapter->dip, 3206 DDI_SERVICE_DEGRADED); 3207 } 3208 return (err); 3209 } 3210 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3211 if (pr_val == NULL) { 3212 err = EINVAL; 3213 return (err); 3214 } 3215 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3216 if (result < MIN_TX_INTR_ABS_DELAY || 3217 result > MAX_TX_INTR_ABS_DELAY) 3218 err = EINVAL; 3219 else { 3220 Adapter->tx_intr_abs_delay = (uint32_t)result; 3221 E1000_WRITE_REG(hw, E1000_TADV, 3222 Adapter->tx_intr_abs_delay); 3223 if (e1000g_check_acc_handle( 3224 Adapter->osdep.reg_handle) != DDI_FM_OK) 3225 ddi_fm_service_impact(Adapter->dip, 3226 DDI_SERVICE_DEGRADED); 3227 } 3228 return (err); 3229 } 3230 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3231 if (pr_val == NULL) { 3232 err = EINVAL; 3233 return (err); 3234 } 3235 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3236 if (result < MIN_RX_BCOPY_THRESHOLD || 3237 result > MAX_RX_BCOPY_THRESHOLD) 3238 err = EINVAL; 3239 else 3240 Adapter->rx_bcopy_thresh = (uint32_t)result; 3241 return (err); 3242 } 3243 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3244 if (pr_val == NULL) { 3245 err = EINVAL; 3246 return (err); 3247 } 3248 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3249 if (result < MIN_RX_LIMIT_ON_INTR || 3250 result > MAX_RX_LIMIT_ON_INTR) 3251 err = EINVAL; 3252 else 3253 Adapter->rx_limit_onintr = (uint32_t)result; 3254 return (err); 3255 } 3256 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3257 if (pr_val == NULL) { 3258 err = EINVAL; 3259 return (err); 3260 } 3261 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3262 if (result < MIN_RX_INTR_DELAY || 3263 result > MAX_RX_INTR_DELAY) 3264 err = EINVAL; 3265 else { 3266 Adapter->rx_intr_delay = (uint32_t)result; 3267 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3268 if (e1000g_check_acc_handle( 3269 Adapter->osdep.reg_handle) != DDI_FM_OK) 3270 ddi_fm_service_impact(Adapter->dip, 3271 DDI_SERVICE_DEGRADED); 3272 } 3273 return (err); 3274 } 3275 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3276 if (pr_val == NULL) { 3277 err = EINVAL; 3278 return (err); 3279 } 3280 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3281 if (result < MIN_RX_INTR_ABS_DELAY || 3282 result > MAX_RX_INTR_ABS_DELAY) 3283 err = EINVAL; 3284 else { 3285 Adapter->rx_intr_abs_delay = (uint32_t)result; 3286 E1000_WRITE_REG(hw, E1000_RADV, 3287 Adapter->rx_intr_abs_delay); 3288 if (e1000g_check_acc_handle( 3289 Adapter->osdep.reg_handle) != DDI_FM_OK) 3290 ddi_fm_service_impact(Adapter->dip, 3291 DDI_SERVICE_DEGRADED); 3292 } 3293 return (err); 3294 } 3295 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3296 if (pr_val == NULL) { 3297 err = EINVAL; 3298 return (err); 3299 } 3300 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3301 if (result < MIN_INTR_THROTTLING || 3302 result > MAX_INTR_THROTTLING) 3303 err = EINVAL; 3304 else { 3305 if (hw->mac.type >= e1000_82540) { 3306 Adapter->intr_throttling_rate = 3307 (uint32_t)result; 3308 E1000_WRITE_REG(hw, E1000_ITR, 3309 Adapter->intr_throttling_rate); 3310 if (e1000g_check_acc_handle( 3311 Adapter->osdep.reg_handle) != DDI_FM_OK) 3312 ddi_fm_service_impact(Adapter->dip, 3313 DDI_SERVICE_DEGRADED); 3314 } else 3315 err = EINVAL; 3316 } 3317 return (err); 3318 } 3319 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3320 if (pr_val == NULL) { 3321 err = EINVAL; 3322 return (err); 3323 } 3324 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3325 if (result < 0 || result > 1) 3326 err = EINVAL; 3327 else { 3328 if (hw->mac.type >= e1000_82540) { 3329 Adapter->intr_adaptive = (result == 1) ? 3330 B_TRUE : B_FALSE; 3331 } else { 3332 err = EINVAL; 3333 } 3334 } 3335 return (err); 3336 } 3337 return (ENOTSUP); 3338 } 3339 3340 static int 3341 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3342 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3343 { 3344 int err = ENOTSUP; 3345 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3346 int value; 3347 3348 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3349 *perm = MAC_PROP_PERM_READ; 3350 if (is_default) 3351 goto done; 3352 value = Adapter->param_adv_pause; 3353 err = 0; 3354 goto done; 3355 } 3356 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3357 *perm = MAC_PROP_PERM_READ; 3358 if (is_default) 3359 goto done; 3360 value = Adapter->param_adv_asym_pause; 3361 err = 0; 3362 goto done; 3363 } 3364 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3365 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3366 Adapter->tx_bcopy_thresh); 3367 err = 0; 3368 goto done; 3369 } 3370 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3371 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3372 Adapter->tx_intr_enable); 3373 err = 0; 3374 goto done; 3375 } 3376 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3377 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3378 Adapter->tx_intr_delay); 3379 err = 0; 3380 goto done; 3381 } 3382 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3383 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3384 Adapter->tx_intr_abs_delay); 3385 err = 0; 3386 goto done; 3387 } 3388 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3389 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3390 Adapter->rx_bcopy_thresh); 3391 err = 0; 3392 goto done; 3393 } 3394 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3395 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3396 Adapter->rx_limit_onintr); 3397 err = 0; 3398 goto done; 3399 } 3400 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3401 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3402 Adapter->rx_intr_delay); 3403 err = 0; 3404 goto done; 3405 } 3406 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3407 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3408 Adapter->rx_intr_abs_delay); 3409 err = 0; 3410 goto done; 3411 } 3412 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3413 value = (is_default ? DEFAULT_INTR_THROTTLING : 3414 Adapter->intr_throttling_rate); 3415 err = 0; 3416 goto done; 3417 } 3418 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3419 value = (is_default ? 1 : Adapter->intr_adaptive); 3420 err = 0; 3421 goto done; 3422 } 3423 done: 3424 if (err == 0) { 3425 (void) snprintf(pr_val, pr_valsize, "%d", value); 3426 } 3427 return (err); 3428 } 3429 3430 /* 3431 * e1000g_get_conf - get configurations set in e1000g.conf 3432 * This routine gets user-configured values out of the configuration 3433 * file e1000g.conf. 3434 * 3435 * For each configurable value, there is a minimum, a maximum, and a 3436 * default. 3437 * If user does not configure a value, use the default. 3438 * If user configures below the minimum, use the minumum. 3439 * If user configures above the maximum, use the maxumum. 3440 */ 3441 static void 3442 e1000g_get_conf(struct e1000g *Adapter) 3443 { 3444 struct e1000_hw *hw = &Adapter->shared; 3445 boolean_t tbi_compatibility = B_FALSE; 3446 3447 /* 3448 * get each configurable property from e1000g.conf 3449 */ 3450 3451 /* 3452 * NumTxDescriptors 3453 */ 3454 Adapter->tx_desc_num = 3455 e1000g_get_prop(Adapter, "NumTxDescriptors", 3456 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3457 DEFAULT_NUM_TX_DESCRIPTOR); 3458 3459 /* 3460 * NumRxDescriptors 3461 */ 3462 Adapter->rx_desc_num = 3463 e1000g_get_prop(Adapter, "NumRxDescriptors", 3464 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3465 DEFAULT_NUM_RX_DESCRIPTOR); 3466 3467 /* 3468 * NumRxFreeList 3469 */ 3470 Adapter->rx_freelist_num = 3471 e1000g_get_prop(Adapter, "NumRxFreeList", 3472 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3473 DEFAULT_NUM_RX_FREELIST); 3474 3475 /* 3476 * NumTxPacketList 3477 */ 3478 Adapter->tx_freelist_num = 3479 e1000g_get_prop(Adapter, "NumTxPacketList", 3480 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3481 DEFAULT_NUM_TX_FREELIST); 3482 3483 /* 3484 * FlowControl 3485 */ 3486 hw->fc.send_xon = B_TRUE; 3487 hw->fc.requested_mode = 3488 e1000g_get_prop(Adapter, "FlowControl", 3489 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3490 /* 4 is the setting that says "let the eeprom decide" */ 3491 if (hw->fc.requested_mode == 4) 3492 hw->fc.requested_mode = e1000_fc_default; 3493 3494 /* 3495 * Max Num Receive Packets on Interrupt 3496 */ 3497 Adapter->rx_limit_onintr = 3498 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3499 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3500 DEFAULT_RX_LIMIT_ON_INTR); 3501 3502 /* 3503 * PHY master slave setting 3504 */ 3505 hw->phy.ms_type = 3506 e1000g_get_prop(Adapter, "SetMasterSlave", 3507 e1000_ms_hw_default, e1000_ms_auto, 3508 e1000_ms_hw_default); 3509 3510 /* 3511 * Parameter which controls TBI mode workaround, which is only 3512 * needed on certain switches such as Cisco 6500/Foundry 3513 */ 3514 tbi_compatibility = 3515 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3516 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3517 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3518 3519 /* 3520 * MSI Enable 3521 */ 3522 Adapter->msi_enable = 3523 e1000g_get_prop(Adapter, "MSIEnable", 3524 0, 1, DEFAULT_MSI_ENABLE); 3525 3526 /* 3527 * Interrupt Throttling Rate 3528 */ 3529 Adapter->intr_throttling_rate = 3530 e1000g_get_prop(Adapter, "intr_throttling_rate", 3531 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3532 DEFAULT_INTR_THROTTLING); 3533 3534 /* 3535 * Adaptive Interrupt Blanking Enable/Disable 3536 * It is enabled by default 3537 */ 3538 Adapter->intr_adaptive = 3539 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3540 B_TRUE : B_FALSE; 3541 3542 /* 3543 * Hardware checksum enable/disable parameter 3544 */ 3545 Adapter->tx_hcksum_enable = 3546 e1000g_get_prop(Adapter, "tx_hcksum_enable", 3547 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3548 /* 3549 * Checksum on/off selection via global parameters. 3550 * 3551 * If the chip is flagged as not capable of (correctly) 3552 * handling checksumming, we don't enable it on either 3553 * Rx or Tx side. Otherwise, we take this chip's settings 3554 * from the patchable global defaults. 3555 * 3556 * We advertise our capabilities only if TX offload is 3557 * enabled. On receive, the stack will accept checksummed 3558 * packets anyway, even if we haven't said we can deliver 3559 * them. 3560 */ 3561 switch (hw->mac.type) { 3562 case e1000_82540: 3563 case e1000_82544: 3564 case e1000_82545: 3565 case e1000_82545_rev_3: 3566 case e1000_82546: 3567 case e1000_82546_rev_3: 3568 case e1000_82571: 3569 case e1000_82572: 3570 case e1000_82573: 3571 case e1000_80003es2lan: 3572 break; 3573 /* 3574 * For the following Intel PRO/1000 chipsets, we have not 3575 * tested the hardware checksum offload capability, so we 3576 * disable the capability for them. 3577 * e1000_82542, 3578 * e1000_82543, 3579 * e1000_82541, 3580 * e1000_82541_rev_2, 3581 * e1000_82547, 3582 * e1000_82547_rev_2, 3583 */ 3584 default: 3585 Adapter->tx_hcksum_enable = B_FALSE; 3586 } 3587 3588 /* 3589 * Large Send Offloading(LSO) Enable/Disable 3590 * If the tx hardware checksum is not enabled, LSO should be 3591 * disabled. 3592 */ 3593 Adapter->lso_enable = 3594 e1000g_get_prop(Adapter, "lso_enable", 3595 0, 1, DEFAULT_LSO_ENABLE); 3596 3597 switch (hw->mac.type) { 3598 case e1000_82546: 3599 case e1000_82546_rev_3: 3600 if (Adapter->lso_enable) 3601 Adapter->lso_premature_issue = B_TRUE; 3602 /* FALLTHRU */ 3603 case e1000_82571: 3604 case e1000_82572: 3605 case e1000_82573: 3606 case e1000_80003es2lan: 3607 break; 3608 default: 3609 Adapter->lso_enable = B_FALSE; 3610 } 3611 3612 if (!Adapter->tx_hcksum_enable) { 3613 Adapter->lso_premature_issue = B_FALSE; 3614 Adapter->lso_enable = B_FALSE; 3615 } 3616 3617 /* 3618 * If mem_workaround_82546 is enabled, the rx buffer allocated by 3619 * e1000_82545, e1000_82546 and e1000_82546_rev_3 3620 * will not cross 64k boundary. 3621 */ 3622 Adapter->mem_workaround_82546 = 3623 e1000g_get_prop(Adapter, "mem_workaround_82546", 3624 0, 1, DEFAULT_MEM_WORKAROUND_82546); 3625 } 3626 3627 /* 3628 * e1000g_get_prop - routine to read properties 3629 * 3630 * Get a user-configure property value out of the configuration 3631 * file e1000g.conf. 3632 * 3633 * Caller provides name of the property, a default value, a minimum 3634 * value, and a maximum value. 3635 * 3636 * Return configured value of the property, with default, minimum and 3637 * maximum properly applied. 3638 */ 3639 static int 3640 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3641 char *propname, /* name of the property */ 3642 int minval, /* minimum acceptable value */ 3643 int maxval, /* maximim acceptable value */ 3644 int defval) /* default value */ 3645 { 3646 int propval; /* value returned for requested property */ 3647 int *props; /* point to array of properties returned */ 3648 uint_t nprops; /* number of property value returned */ 3649 3650 /* 3651 * get the array of properties from the config file 3652 */ 3653 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3654 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3655 /* got some properties, test if we got enough */ 3656 if (Adapter->instance < nprops) { 3657 propval = props[Adapter->instance]; 3658 } else { 3659 /* not enough properties configured */ 3660 propval = defval; 3661 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3662 "Not Enough %s values found in e1000g.conf" 3663 " - set to %d\n", 3664 propname, propval); 3665 } 3666 3667 /* free memory allocated for properties */ 3668 ddi_prop_free(props); 3669 3670 } else { 3671 propval = defval; 3672 } 3673 3674 /* 3675 * enforce limits 3676 */ 3677 if (propval > maxval) { 3678 propval = maxval; 3679 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3680 "Too High %s value in e1000g.conf - set to %d\n", 3681 propname, propval); 3682 } 3683 3684 if (propval < minval) { 3685 propval = minval; 3686 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3687 "Too Low %s value in e1000g.conf - set to %d\n", 3688 propname, propval); 3689 } 3690 3691 return (propval); 3692 } 3693 3694 static boolean_t 3695 e1000g_link_check(struct e1000g *Adapter) 3696 { 3697 uint16_t speed, duplex, phydata; 3698 boolean_t link_changed = B_FALSE; 3699 struct e1000_hw *hw; 3700 uint32_t reg_tarc; 3701 3702 hw = &Adapter->shared; 3703 3704 if (e1000g_link_up(Adapter)) { 3705 /* 3706 * The Link is up, check whether it was marked as down earlier 3707 */ 3708 if (Adapter->link_state != LINK_STATE_UP) { 3709 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3710 Adapter->link_speed = speed; 3711 Adapter->link_duplex = duplex; 3712 Adapter->link_state = LINK_STATE_UP; 3713 link_changed = B_TRUE; 3714 3715 Adapter->tx_link_down_timeout = 0; 3716 3717 if ((hw->mac.type == e1000_82571) || 3718 (hw->mac.type == e1000_82572)) { 3719 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3720 if (speed == SPEED_1000) 3721 reg_tarc |= (1 << 21); 3722 else 3723 reg_tarc &= ~(1 << 21); 3724 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3725 } 3726 } 3727 Adapter->smartspeed = 0; 3728 } else { 3729 if (Adapter->link_state != LINK_STATE_DOWN) { 3730 Adapter->link_speed = 0; 3731 Adapter->link_duplex = 0; 3732 Adapter->link_state = LINK_STATE_DOWN; 3733 link_changed = B_TRUE; 3734 3735 /* 3736 * SmartSpeed workaround for Tabor/TanaX, When the 3737 * driver loses link disable auto master/slave 3738 * resolution. 3739 */ 3740 if (hw->phy.type == e1000_phy_igp) { 3741 (void) e1000_read_phy_reg(hw, 3742 PHY_1000T_CTRL, &phydata); 3743 phydata |= CR_1000T_MS_ENABLE; 3744 (void) e1000_write_phy_reg(hw, 3745 PHY_1000T_CTRL, phydata); 3746 } 3747 } else { 3748 e1000g_smartspeed(Adapter); 3749 } 3750 3751 if (Adapter->e1000g_state & E1000G_STARTED) { 3752 if (Adapter->tx_link_down_timeout < 3753 MAX_TX_LINK_DOWN_TIMEOUT) { 3754 Adapter->tx_link_down_timeout++; 3755 } else if (Adapter->tx_link_down_timeout == 3756 MAX_TX_LINK_DOWN_TIMEOUT) { 3757 e1000g_tx_clean(Adapter); 3758 Adapter->tx_link_down_timeout++; 3759 } 3760 } 3761 } 3762 3763 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3764 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3765 3766 return (link_changed); 3767 } 3768 3769 /* 3770 * e1000g_reset_link - Using the link properties to setup the link 3771 */ 3772 int 3773 e1000g_reset_link(struct e1000g *Adapter) 3774 { 3775 struct e1000_mac_info *mac; 3776 struct e1000_phy_info *phy; 3777 boolean_t invalid; 3778 3779 mac = &Adapter->shared.mac; 3780 phy = &Adapter->shared.phy; 3781 invalid = B_FALSE; 3782 3783 if (Adapter->param_adv_autoneg == 1) { 3784 mac->autoneg = B_TRUE; 3785 phy->autoneg_advertised = 0; 3786 3787 /* 3788 * 1000hdx is not supported for autonegotiation 3789 */ 3790 if (Adapter->param_adv_1000fdx == 1) 3791 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3792 3793 if (Adapter->param_adv_100fdx == 1) 3794 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3795 3796 if (Adapter->param_adv_100hdx == 1) 3797 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3798 3799 if (Adapter->param_adv_10fdx == 1) 3800 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3801 3802 if (Adapter->param_adv_10hdx == 1) 3803 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3804 3805 if (phy->autoneg_advertised == 0) 3806 invalid = B_TRUE; 3807 } else { 3808 mac->autoneg = B_FALSE; 3809 3810 /* 3811 * 1000fdx and 1000hdx are not supported for forced link 3812 */ 3813 if (Adapter->param_adv_100fdx == 1) 3814 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3815 else if (Adapter->param_adv_100hdx == 1) 3816 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3817 else if (Adapter->param_adv_10fdx == 1) 3818 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3819 else if (Adapter->param_adv_10hdx == 1) 3820 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3821 else 3822 invalid = B_TRUE; 3823 3824 } 3825 3826 if (invalid) { 3827 e1000g_log(Adapter, CE_WARN, 3828 "Invalid link sets. Setup link to" 3829 "support autonegotiation with all link capabilities."); 3830 mac->autoneg = B_TRUE; 3831 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3832 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3833 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3834 } 3835 3836 return (e1000_setup_link(&Adapter->shared)); 3837 } 3838 3839 static void 3840 e1000g_timer_tx_resched(struct e1000g *Adapter) 3841 { 3842 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 3843 3844 rw_enter(&Adapter->chip_lock, RW_READER); 3845 3846 if (tx_ring->resched_needed && 3847 ((ddi_get_lbolt() - tx_ring->resched_timestamp) > 3848 drv_usectohz(1000000)) && 3849 (Adapter->e1000g_state & E1000G_STARTED) && 3850 (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) { 3851 tx_ring->resched_needed = B_FALSE; 3852 mac_tx_update(Adapter->mh); 3853 E1000G_STAT(tx_ring->stat_reschedule); 3854 E1000G_STAT(tx_ring->stat_timer_reschedule); 3855 } 3856 3857 rw_exit(&Adapter->chip_lock); 3858 } 3859 3860 static void 3861 e1000g_local_timer(void *ws) 3862 { 3863 struct e1000g *Adapter = (struct e1000g *)ws; 3864 struct e1000_hw *hw; 3865 e1000g_ether_addr_t ether_addr; 3866 boolean_t link_changed; 3867 3868 hw = &Adapter->shared; 3869 3870 if (Adapter->e1000g_state & E1000G_ERROR) { 3871 rw_enter(&Adapter->chip_lock, RW_WRITER); 3872 Adapter->e1000g_state &= ~E1000G_ERROR; 3873 rw_exit(&Adapter->chip_lock); 3874 3875 Adapter->reset_count++; 3876 if (e1000g_global_reset(Adapter)) { 3877 ddi_fm_service_impact(Adapter->dip, 3878 DDI_SERVICE_RESTORED); 3879 e1000g_timer_tx_resched(Adapter); 3880 } else 3881 ddi_fm_service_impact(Adapter->dip, 3882 DDI_SERVICE_LOST); 3883 return; 3884 } 3885 3886 if (e1000g_stall_check(Adapter)) { 3887 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3888 "Tx stall detected. Activate automatic recovery.\n"); 3889 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 3890 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 3891 Adapter->reset_count++; 3892 if (e1000g_reset_adapter(Adapter)) { 3893 ddi_fm_service_impact(Adapter->dip, 3894 DDI_SERVICE_RESTORED); 3895 e1000g_timer_tx_resched(Adapter); 3896 } 3897 return; 3898 } 3899 3900 link_changed = B_FALSE; 3901 rw_enter(&Adapter->chip_lock, RW_READER); 3902 if (Adapter->link_complete) 3903 link_changed = e1000g_link_check(Adapter); 3904 rw_exit(&Adapter->chip_lock); 3905 3906 if (link_changed) 3907 mac_link_update(Adapter->mh, Adapter->link_state); 3908 3909 /* 3910 * Workaround for esb2. Data stuck in fifo on a link 3911 * down event. Reset the adapter to recover it. 3912 */ 3913 if (Adapter->esb2_workaround) { 3914 Adapter->esb2_workaround = B_FALSE; 3915 (void) e1000g_reset_adapter(Adapter); 3916 return; 3917 } 3918 3919 /* 3920 * With 82571 controllers, any locally administered address will 3921 * be overwritten when there is a reset on the other port. 3922 * Detect this circumstance and correct it. 3923 */ 3924 if ((hw->mac.type == e1000_82571) && 3925 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 3926 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 3927 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 3928 3929 ether_addr.reg.low = ntohl(ether_addr.reg.low); 3930 ether_addr.reg.high = ntohl(ether_addr.reg.high); 3931 3932 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 3933 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 3934 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 3935 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 3936 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 3937 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 3938 e1000_rar_set(hw, hw->mac.addr, 0); 3939 } 3940 } 3941 3942 /* 3943 * Long TTL workaround for 82541/82547 3944 */ 3945 (void) e1000_igp_ttl_workaround_82547(hw); 3946 3947 /* 3948 * Check for Adaptive IFS settings If there are lots of collisions 3949 * change the value in steps... 3950 * These properties should only be set for 10/100 3951 */ 3952 if ((hw->phy.media_type == e1000_media_type_copper) && 3953 ((Adapter->link_speed == SPEED_100) || 3954 (Adapter->link_speed == SPEED_10))) { 3955 e1000_update_adaptive(hw); 3956 } 3957 /* 3958 * Set Timer Interrupts 3959 */ 3960 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 3961 3962 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3963 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3964 else 3965 e1000g_timer_tx_resched(Adapter); 3966 3967 restart_watchdog_timer(Adapter); 3968 } 3969 3970 /* 3971 * The function e1000g_link_timer() is called when the timer for link setup 3972 * is expired, which indicates the completion of the link setup. The link 3973 * state will not be updated until the link setup is completed. And the 3974 * link state will not be sent to the upper layer through mac_link_update() 3975 * in this function. It will be updated in the local timer routine or the 3976 * interrupt service routine after the interface is started (plumbed). 3977 */ 3978 static void 3979 e1000g_link_timer(void *arg) 3980 { 3981 struct e1000g *Adapter = (struct e1000g *)arg; 3982 3983 mutex_enter(&Adapter->link_lock); 3984 Adapter->link_complete = B_TRUE; 3985 Adapter->link_tid = 0; 3986 mutex_exit(&Adapter->link_lock); 3987 } 3988 3989 /* 3990 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 3991 * 3992 * This function read the forced speed and duplex for 10/100 Mbps speeds 3993 * and also for 1000 Mbps speeds from the e1000g.conf file 3994 */ 3995 static void 3996 e1000g_force_speed_duplex(struct e1000g *Adapter) 3997 { 3998 int forced; 3999 struct e1000_mac_info *mac = &Adapter->shared.mac; 4000 struct e1000_phy_info *phy = &Adapter->shared.phy; 4001 4002 /* 4003 * get value out of config file 4004 */ 4005 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 4006 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 4007 4008 switch (forced) { 4009 case GDIAG_10_HALF: 4010 /* 4011 * Disable Auto Negotiation 4012 */ 4013 mac->autoneg = B_FALSE; 4014 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4015 break; 4016 case GDIAG_10_FULL: 4017 /* 4018 * Disable Auto Negotiation 4019 */ 4020 mac->autoneg = B_FALSE; 4021 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4022 break; 4023 case GDIAG_100_HALF: 4024 /* 4025 * Disable Auto Negotiation 4026 */ 4027 mac->autoneg = B_FALSE; 4028 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4029 break; 4030 case GDIAG_100_FULL: 4031 /* 4032 * Disable Auto Negotiation 4033 */ 4034 mac->autoneg = B_FALSE; 4035 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4036 break; 4037 case GDIAG_1000_FULL: 4038 /* 4039 * The gigabit spec requires autonegotiation. Therefore, 4040 * when the user wants to force the speed to 1000Mbps, we 4041 * enable AutoNeg, but only allow the harware to advertise 4042 * 1000Mbps. This is different from 10/100 operation, where 4043 * we are allowed to link without any negotiation. 4044 */ 4045 mac->autoneg = B_TRUE; 4046 phy->autoneg_advertised = ADVERTISE_1000_FULL; 4047 break; 4048 default: /* obey the setting of AutoNegAdvertised */ 4049 mac->autoneg = B_TRUE; 4050 phy->autoneg_advertised = 4051 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 4052 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 4053 AUTONEG_ADVERTISE_SPEED_DEFAULT); 4054 break; 4055 } /* switch */ 4056 } 4057 4058 /* 4059 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 4060 * 4061 * This function reads MaxFrameSize from e1000g.conf 4062 */ 4063 static void 4064 e1000g_get_max_frame_size(struct e1000g *Adapter) 4065 { 4066 int max_frame; 4067 struct e1000_mac_info *mac = &Adapter->shared.mac; 4068 struct e1000_phy_info *phy = &Adapter->shared.phy; 4069 4070 /* 4071 * get value out of config file 4072 */ 4073 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 4074 4075 switch (max_frame) { 4076 case 0: 4077 Adapter->default_mtu = ETHERMTU; 4078 break; 4079 /* 4080 * To avoid excessive memory allocation for rx buffers, 4081 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 4082 */ 4083 case 1: 4084 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 4085 sizeof (struct ether_vlan_header) - ETHERFCSL - 4086 E1000G_IPALIGNPRESERVEROOM; 4087 break; 4088 case 2: 4089 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 4090 sizeof (struct ether_vlan_header) - ETHERFCSL - 4091 E1000G_IPALIGNPRESERVEROOM; 4092 break; 4093 case 3: 4094 if (mac->type >= e1000_82571) 4095 Adapter->default_mtu = MAXIMUM_MTU; 4096 else 4097 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 4098 sizeof (struct ether_vlan_header) - ETHERFCSL - 4099 E1000G_IPALIGNPRESERVEROOM; 4100 break; 4101 default: 4102 Adapter->default_mtu = ETHERMTU; 4103 break; 4104 } /* switch */ 4105 4106 Adapter->max_frame_size = Adapter->default_mtu + 4107 sizeof (struct ether_vlan_header) + ETHERFCSL; 4108 4109 /* ich8 does not do jumbo frames */ 4110 if (mac->type == e1000_ich8lan) { 4111 Adapter->default_mtu = ETHERMTU; 4112 Adapter->max_frame_size = ETHERMTU + 4113 sizeof (struct ether_vlan_header) + ETHERFCSL; 4114 } 4115 4116 /* ich9 does not do jumbo frames on one phy type */ 4117 if ((mac->type == e1000_ich9lan) && 4118 (phy->type == e1000_phy_ife)) { 4119 Adapter->default_mtu = ETHERMTU; 4120 Adapter->max_frame_size = ETHERMTU + 4121 sizeof (struct ether_vlan_header) + ETHERFCSL; 4122 } 4123 } 4124 4125 static void 4126 arm_watchdog_timer(struct e1000g *Adapter) 4127 { 4128 Adapter->watchdog_tid = 4129 timeout(e1000g_local_timer, 4130 (void *)Adapter, 1 * drv_usectohz(1000000)); 4131 } 4132 #pragma inline(arm_watchdog_timer) 4133 4134 static void 4135 enable_watchdog_timer(struct e1000g *Adapter) 4136 { 4137 mutex_enter(&Adapter->watchdog_lock); 4138 4139 if (!Adapter->watchdog_timer_enabled) { 4140 Adapter->watchdog_timer_enabled = B_TRUE; 4141 Adapter->watchdog_timer_started = B_TRUE; 4142 arm_watchdog_timer(Adapter); 4143 } 4144 4145 mutex_exit(&Adapter->watchdog_lock); 4146 } 4147 4148 static void 4149 disable_watchdog_timer(struct e1000g *Adapter) 4150 { 4151 timeout_id_t tid; 4152 4153 mutex_enter(&Adapter->watchdog_lock); 4154 4155 Adapter->watchdog_timer_enabled = B_FALSE; 4156 Adapter->watchdog_timer_started = B_FALSE; 4157 tid = Adapter->watchdog_tid; 4158 Adapter->watchdog_tid = 0; 4159 4160 mutex_exit(&Adapter->watchdog_lock); 4161 4162 if (tid != 0) 4163 (void) untimeout(tid); 4164 } 4165 4166 static void 4167 start_watchdog_timer(struct e1000g *Adapter) 4168 { 4169 mutex_enter(&Adapter->watchdog_lock); 4170 4171 if (Adapter->watchdog_timer_enabled) { 4172 if (!Adapter->watchdog_timer_started) { 4173 Adapter->watchdog_timer_started = B_TRUE; 4174 arm_watchdog_timer(Adapter); 4175 } 4176 } 4177 4178 mutex_exit(&Adapter->watchdog_lock); 4179 } 4180 4181 static void 4182 restart_watchdog_timer(struct e1000g *Adapter) 4183 { 4184 mutex_enter(&Adapter->watchdog_lock); 4185 4186 if (Adapter->watchdog_timer_started) 4187 arm_watchdog_timer(Adapter); 4188 4189 mutex_exit(&Adapter->watchdog_lock); 4190 } 4191 4192 static void 4193 stop_watchdog_timer(struct e1000g *Adapter) 4194 { 4195 timeout_id_t tid; 4196 4197 mutex_enter(&Adapter->watchdog_lock); 4198 4199 Adapter->watchdog_timer_started = B_FALSE; 4200 tid = Adapter->watchdog_tid; 4201 Adapter->watchdog_tid = 0; 4202 4203 mutex_exit(&Adapter->watchdog_lock); 4204 4205 if (tid != 0) 4206 (void) untimeout(tid); 4207 } 4208 4209 static void 4210 stop_link_timer(struct e1000g *Adapter) 4211 { 4212 timeout_id_t tid; 4213 4214 /* Disable the link timer */ 4215 mutex_enter(&Adapter->link_lock); 4216 4217 tid = Adapter->link_tid; 4218 Adapter->link_tid = 0; 4219 4220 mutex_exit(&Adapter->link_lock); 4221 4222 if (tid != 0) 4223 (void) untimeout(tid); 4224 } 4225 4226 static void 4227 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4228 { 4229 timeout_id_t tid; 4230 4231 /* Disable the tx timer for 82547 chipset */ 4232 mutex_enter(&tx_ring->tx_lock); 4233 4234 tx_ring->timer_enable_82547 = B_FALSE; 4235 tid = tx_ring->timer_id_82547; 4236 tx_ring->timer_id_82547 = 0; 4237 4238 mutex_exit(&tx_ring->tx_lock); 4239 4240 if (tid != 0) 4241 (void) untimeout(tid); 4242 } 4243 4244 void 4245 e1000g_clear_interrupt(struct e1000g *Adapter) 4246 { 4247 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4248 0xffffffff & ~E1000_IMS_RXSEQ); 4249 } 4250 4251 void 4252 e1000g_mask_interrupt(struct e1000g *Adapter) 4253 { 4254 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4255 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4256 4257 if (Adapter->tx_intr_enable) 4258 e1000g_mask_tx_interrupt(Adapter); 4259 } 4260 4261 /* 4262 * This routine is called by e1000g_quiesce(), therefore must not block. 4263 */ 4264 void 4265 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4266 { 4267 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4268 } 4269 4270 void 4271 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4272 { 4273 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4274 } 4275 4276 void 4277 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4278 { 4279 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4280 } 4281 4282 static void 4283 e1000g_smartspeed(struct e1000g *Adapter) 4284 { 4285 struct e1000_hw *hw = &Adapter->shared; 4286 uint16_t phy_status; 4287 uint16_t phy_ctrl; 4288 4289 /* 4290 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4291 * advertising 1000Full, we don't even use the workaround 4292 */ 4293 if ((hw->phy.type != e1000_phy_igp) || 4294 !hw->mac.autoneg || 4295 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4296 return; 4297 4298 /* 4299 * True if this is the first call of this function or after every 4300 * 30 seconds of not having link 4301 */ 4302 if (Adapter->smartspeed == 0) { 4303 /* 4304 * If Master/Slave config fault is asserted twice, we 4305 * assume back-to-back 4306 */ 4307 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4308 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4309 return; 4310 4311 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4312 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4313 return; 4314 /* 4315 * We're assuming back-2-back because our status register 4316 * insists! there's a fault in the master/slave 4317 * relationship that was "negotiated" 4318 */ 4319 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4320 /* 4321 * Is the phy configured for manual configuration of 4322 * master/slave? 4323 */ 4324 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4325 /* 4326 * Yes. Then disable manual configuration (enable 4327 * auto configuration) of master/slave 4328 */ 4329 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4330 (void) e1000_write_phy_reg(hw, 4331 PHY_1000T_CTRL, phy_ctrl); 4332 /* 4333 * Effectively starting the clock 4334 */ 4335 Adapter->smartspeed++; 4336 /* 4337 * Restart autonegotiation 4338 */ 4339 if (!e1000_phy_setup_autoneg(hw) && 4340 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4341 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4342 MII_CR_RESTART_AUTO_NEG); 4343 (void) e1000_write_phy_reg(hw, 4344 PHY_CONTROL, phy_ctrl); 4345 } 4346 } 4347 return; 4348 /* 4349 * Has 6 seconds transpired still without link? Remember, 4350 * you should reset the smartspeed counter once you obtain 4351 * link 4352 */ 4353 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4354 /* 4355 * Yes. Remember, we did at the start determine that 4356 * there's a master/slave configuration fault, so we're 4357 * still assuming there's someone on the other end, but we 4358 * just haven't yet been able to talk to it. We then 4359 * re-enable auto configuration of master/slave to see if 4360 * we're running 2/3 pair cables. 4361 */ 4362 /* 4363 * If still no link, perhaps using 2/3 pair cable 4364 */ 4365 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4366 phy_ctrl |= CR_1000T_MS_ENABLE; 4367 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4368 /* 4369 * Restart autoneg with phy enabled for manual 4370 * configuration of master/slave 4371 */ 4372 if (!e1000_phy_setup_autoneg(hw) && 4373 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4374 phy_ctrl |= 4375 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4376 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4377 } 4378 /* 4379 * Hopefully, there are no more faults and we've obtained 4380 * link as a result. 4381 */ 4382 } 4383 /* 4384 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4385 * seconds) 4386 */ 4387 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4388 Adapter->smartspeed = 0; 4389 } 4390 4391 static boolean_t 4392 is_valid_mac_addr(uint8_t *mac_addr) 4393 { 4394 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4395 const uint8_t addr_test2[6] = 4396 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4397 4398 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4399 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4400 return (B_FALSE); 4401 4402 return (B_TRUE); 4403 } 4404 4405 /* 4406 * e1000g_stall_check - check for tx stall 4407 * 4408 * This function checks if the adapter is stalled (in transmit). 4409 * 4410 * It is called each time the watchdog timeout is invoked. 4411 * If the transmit descriptor reclaim continuously fails, 4412 * the watchdog value will increment by 1. If the watchdog 4413 * value exceeds the threshold, the adapter is assumed to 4414 * have stalled and need to be reset. 4415 */ 4416 static boolean_t 4417 e1000g_stall_check(struct e1000g *Adapter) 4418 { 4419 e1000g_tx_ring_t *tx_ring; 4420 4421 tx_ring = Adapter->tx_ring; 4422 4423 if (Adapter->link_state != LINK_STATE_UP) 4424 return (B_FALSE); 4425 4426 if (tx_ring->recycle_fail > 0) 4427 tx_ring->stall_watchdog++; 4428 else 4429 tx_ring->stall_watchdog = 0; 4430 4431 if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) 4432 return (B_FALSE); 4433 4434 tx_ring->stall_watchdog = 0; 4435 tx_ring->recycle_fail = 0; 4436 4437 return (B_TRUE); 4438 } 4439 4440 #ifdef E1000G_DEBUG 4441 static enum ioc_reply 4442 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4443 { 4444 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4445 e1000g_peekpoke_t *ppd; 4446 uint64_t mem_va; 4447 uint64_t maxoff; 4448 boolean_t peek; 4449 4450 switch (iocp->ioc_cmd) { 4451 4452 case E1000G_IOC_REG_PEEK: 4453 peek = B_TRUE; 4454 break; 4455 4456 case E1000G_IOC_REG_POKE: 4457 peek = B_FALSE; 4458 break; 4459 4460 deault: 4461 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4462 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4463 iocp->ioc_cmd); 4464 return (IOC_INVAL); 4465 } 4466 4467 /* 4468 * Validate format of ioctl 4469 */ 4470 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4471 return (IOC_INVAL); 4472 if (mp->b_cont == NULL) 4473 return (IOC_INVAL); 4474 4475 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4476 4477 /* 4478 * Validate request parameters 4479 */ 4480 switch (ppd->pp_acc_space) { 4481 4482 default: 4483 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4484 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4485 ppd->pp_acc_space); 4486 return (IOC_INVAL); 4487 4488 case E1000G_PP_SPACE_REG: 4489 /* 4490 * Memory-mapped I/O space 4491 */ 4492 ASSERT(ppd->pp_acc_size == 4); 4493 if (ppd->pp_acc_size != 4) 4494 return (IOC_INVAL); 4495 4496 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4497 return (IOC_INVAL); 4498 4499 mem_va = 0; 4500 maxoff = 0x10000; 4501 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4502 break; 4503 4504 case E1000G_PP_SPACE_E1000G: 4505 /* 4506 * E1000g data structure! 4507 */ 4508 mem_va = (uintptr_t)e1000gp; 4509 maxoff = sizeof (struct e1000g); 4510 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4511 break; 4512 4513 } 4514 4515 if (ppd->pp_acc_offset >= maxoff) 4516 return (IOC_INVAL); 4517 4518 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4519 return (IOC_INVAL); 4520 4521 /* 4522 * All OK - go! 4523 */ 4524 ppd->pp_acc_offset += mem_va; 4525 (*ppfn)(e1000gp, ppd); 4526 return (peek ? IOC_REPLY : IOC_ACK); 4527 } 4528 4529 static void 4530 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4531 { 4532 ddi_acc_handle_t handle; 4533 uint32_t *regaddr; 4534 4535 handle = e1000gp->osdep.reg_handle; 4536 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4537 (uintptr_t)ppd->pp_acc_offset); 4538 4539 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4540 } 4541 4542 static void 4543 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4544 { 4545 ddi_acc_handle_t handle; 4546 uint32_t *regaddr; 4547 uint32_t value; 4548 4549 handle = e1000gp->osdep.reg_handle; 4550 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4551 (uintptr_t)ppd->pp_acc_offset); 4552 value = (uint32_t)ppd->pp_acc_data; 4553 4554 ddi_put32(handle, regaddr, value); 4555 } 4556 4557 static void 4558 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4559 { 4560 uint64_t value; 4561 void *vaddr; 4562 4563 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4564 4565 switch (ppd->pp_acc_size) { 4566 case 1: 4567 value = *(uint8_t *)vaddr; 4568 break; 4569 4570 case 2: 4571 value = *(uint16_t *)vaddr; 4572 break; 4573 4574 case 4: 4575 value = *(uint32_t *)vaddr; 4576 break; 4577 4578 case 8: 4579 value = *(uint64_t *)vaddr; 4580 break; 4581 } 4582 4583 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4584 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4585 (void *)e1000gp, (void *)ppd, value, vaddr); 4586 4587 ppd->pp_acc_data = value; 4588 } 4589 4590 static void 4591 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4592 { 4593 uint64_t value; 4594 void *vaddr; 4595 4596 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4597 value = ppd->pp_acc_data; 4598 4599 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4600 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4601 (void *)e1000gp, (void *)ppd, value, vaddr); 4602 4603 switch (ppd->pp_acc_size) { 4604 case 1: 4605 *(uint8_t *)vaddr = (uint8_t)value; 4606 break; 4607 4608 case 2: 4609 *(uint16_t *)vaddr = (uint16_t)value; 4610 break; 4611 4612 case 4: 4613 *(uint32_t *)vaddr = (uint32_t)value; 4614 break; 4615 4616 case 8: 4617 *(uint64_t *)vaddr = (uint64_t)value; 4618 break; 4619 } 4620 } 4621 #endif 4622 4623 /* 4624 * Loopback Support 4625 */ 4626 static lb_property_t lb_normal = 4627 { normal, "normal", E1000G_LB_NONE }; 4628 static lb_property_t lb_external1000 = 4629 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4630 static lb_property_t lb_external100 = 4631 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4632 static lb_property_t lb_external10 = 4633 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4634 static lb_property_t lb_phy = 4635 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4636 4637 static enum ioc_reply 4638 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4639 { 4640 lb_info_sz_t *lbsp; 4641 lb_property_t *lbpp; 4642 struct e1000_hw *hw; 4643 uint32_t *lbmp; 4644 uint32_t size; 4645 uint32_t value; 4646 4647 hw = &Adapter->shared; 4648 4649 if (mp->b_cont == NULL) 4650 return (IOC_INVAL); 4651 4652 if (!e1000g_check_loopback_support(hw)) { 4653 e1000g_log(NULL, CE_WARN, 4654 "Loopback is not supported on e1000g%d", Adapter->instance); 4655 return (IOC_INVAL); 4656 } 4657 4658 switch (iocp->ioc_cmd) { 4659 default: 4660 return (IOC_INVAL); 4661 4662 case LB_GET_INFO_SIZE: 4663 size = sizeof (lb_info_sz_t); 4664 if (iocp->ioc_count != size) 4665 return (IOC_INVAL); 4666 4667 rw_enter(&Adapter->chip_lock, RW_WRITER); 4668 e1000g_get_phy_state(Adapter); 4669 4670 /* 4671 * Workaround for hardware faults. In order to get a stable 4672 * state of phy, we will wait for a specific interval and 4673 * try again. The time delay is an experiential value based 4674 * on our testing. 4675 */ 4676 msec_delay(100); 4677 e1000g_get_phy_state(Adapter); 4678 rw_exit(&Adapter->chip_lock); 4679 4680 value = sizeof (lb_normal); 4681 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4682 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4683 (hw->phy.media_type == e1000_media_type_fiber) || 4684 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4685 value += sizeof (lb_phy); 4686 switch (hw->mac.type) { 4687 case e1000_82571: 4688 case e1000_82572: 4689 case e1000_80003es2lan: 4690 value += sizeof (lb_external1000); 4691 break; 4692 } 4693 } 4694 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4695 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4696 value += sizeof (lb_external100); 4697 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4698 value += sizeof (lb_external10); 4699 4700 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 4701 *lbsp = value; 4702 break; 4703 4704 case LB_GET_INFO: 4705 value = sizeof (lb_normal); 4706 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4707 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4708 (hw->phy.media_type == e1000_media_type_fiber) || 4709 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4710 value += sizeof (lb_phy); 4711 switch (hw->mac.type) { 4712 case e1000_82571: 4713 case e1000_82572: 4714 case e1000_80003es2lan: 4715 value += sizeof (lb_external1000); 4716 break; 4717 } 4718 } 4719 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4720 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4721 value += sizeof (lb_external100); 4722 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4723 value += sizeof (lb_external10); 4724 4725 size = value; 4726 if (iocp->ioc_count != size) 4727 return (IOC_INVAL); 4728 4729 value = 0; 4730 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 4731 lbpp[value++] = lb_normal; 4732 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4733 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4734 (hw->phy.media_type == e1000_media_type_fiber) || 4735 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4736 lbpp[value++] = lb_phy; 4737 switch (hw->mac.type) { 4738 case e1000_82571: 4739 case e1000_82572: 4740 case e1000_80003es2lan: 4741 lbpp[value++] = lb_external1000; 4742 break; 4743 } 4744 } 4745 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4746 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4747 lbpp[value++] = lb_external100; 4748 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4749 lbpp[value++] = lb_external10; 4750 break; 4751 4752 case LB_GET_MODE: 4753 size = sizeof (uint32_t); 4754 if (iocp->ioc_count != size) 4755 return (IOC_INVAL); 4756 4757 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4758 *lbmp = Adapter->loopback_mode; 4759 break; 4760 4761 case LB_SET_MODE: 4762 size = 0; 4763 if (iocp->ioc_count != sizeof (uint32_t)) 4764 return (IOC_INVAL); 4765 4766 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4767 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4768 return (IOC_INVAL); 4769 break; 4770 } 4771 4772 iocp->ioc_count = size; 4773 iocp->ioc_error = 0; 4774 4775 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4776 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4777 return (IOC_INVAL); 4778 } 4779 4780 return (IOC_REPLY); 4781 } 4782 4783 static boolean_t 4784 e1000g_check_loopback_support(struct e1000_hw *hw) 4785 { 4786 switch (hw->mac.type) { 4787 case e1000_82540: 4788 case e1000_82545: 4789 case e1000_82545_rev_3: 4790 case e1000_82546: 4791 case e1000_82546_rev_3: 4792 case e1000_82541: 4793 case e1000_82541_rev_2: 4794 case e1000_82547: 4795 case e1000_82547_rev_2: 4796 case e1000_82571: 4797 case e1000_82572: 4798 case e1000_82573: 4799 case e1000_82574: 4800 case e1000_80003es2lan: 4801 case e1000_ich9lan: 4802 case e1000_ich10lan: 4803 return (B_TRUE); 4804 } 4805 return (B_FALSE); 4806 } 4807 4808 static boolean_t 4809 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 4810 { 4811 struct e1000_hw *hw; 4812 int i, times; 4813 boolean_t link_up; 4814 4815 if (mode == Adapter->loopback_mode) 4816 return (B_TRUE); 4817 4818 hw = &Adapter->shared; 4819 times = 0; 4820 4821 Adapter->loopback_mode = mode; 4822 4823 if (mode == E1000G_LB_NONE) { 4824 /* Reset the chip */ 4825 hw->phy.autoneg_wait_to_complete = B_TRUE; 4826 (void) e1000g_reset_adapter(Adapter); 4827 hw->phy.autoneg_wait_to_complete = B_FALSE; 4828 return (B_TRUE); 4829 } 4830 4831 again: 4832 4833 rw_enter(&Adapter->chip_lock, RW_WRITER); 4834 4835 switch (mode) { 4836 default: 4837 rw_exit(&Adapter->chip_lock); 4838 return (B_FALSE); 4839 4840 case E1000G_LB_EXTERNAL_1000: 4841 e1000g_set_external_loopback_1000(Adapter); 4842 break; 4843 4844 case E1000G_LB_EXTERNAL_100: 4845 e1000g_set_external_loopback_100(Adapter); 4846 break; 4847 4848 case E1000G_LB_EXTERNAL_10: 4849 e1000g_set_external_loopback_10(Adapter); 4850 break; 4851 4852 case E1000G_LB_INTERNAL_PHY: 4853 e1000g_set_internal_loopback(Adapter); 4854 break; 4855 } 4856 4857 times++; 4858 4859 rw_exit(&Adapter->chip_lock); 4860 4861 /* Wait for link up */ 4862 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 4863 msec_delay(100); 4864 4865 rw_enter(&Adapter->chip_lock, RW_WRITER); 4866 4867 link_up = e1000g_link_up(Adapter); 4868 4869 rw_exit(&Adapter->chip_lock); 4870 4871 if (!link_up) { 4872 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4873 "Failed to get the link up"); 4874 if (times < 2) { 4875 /* Reset the link */ 4876 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4877 "Reset the link ..."); 4878 (void) e1000g_reset_adapter(Adapter); 4879 goto again; 4880 } 4881 } 4882 4883 return (B_TRUE); 4884 } 4885 4886 /* 4887 * The following loopback settings are from Intel's technical 4888 * document - "How To Loopback". All the register settings and 4889 * time delay values are directly inherited from the document 4890 * without more explanations available. 4891 */ 4892 static void 4893 e1000g_set_internal_loopback(struct e1000g *Adapter) 4894 { 4895 struct e1000_hw *hw; 4896 uint32_t ctrl; 4897 uint32_t status; 4898 uint16_t phy_ctrl; 4899 uint16_t phy_reg; 4900 uint32_t txcw; 4901 4902 hw = &Adapter->shared; 4903 4904 /* Disable Smart Power Down */ 4905 phy_spd_state(hw, B_FALSE); 4906 4907 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4908 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 4909 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 4910 4911 switch (hw->mac.type) { 4912 case e1000_82540: 4913 case e1000_82545: 4914 case e1000_82545_rev_3: 4915 case e1000_82546: 4916 case e1000_82546_rev_3: 4917 case e1000_82573: 4918 /* Auto-MDI/MDIX off */ 4919 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 4920 /* Reset PHY to update Auto-MDI/MDIX */ 4921 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4922 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 4923 /* Reset PHY to auto-neg off and force 1000 */ 4924 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4925 phy_ctrl | MII_CR_RESET); 4926 /* 4927 * Disable PHY receiver for 82540/545/546 and 82573 Family. 4928 * See comments above e1000g_set_internal_loopback() for the 4929 * background. 4930 */ 4931 (void) e1000_write_phy_reg(hw, 29, 0x001F); 4932 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 4933 (void) e1000_write_phy_reg(hw, 29, 0x001A); 4934 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 4935 break; 4936 case e1000_80003es2lan: 4937 /* Force Link Up */ 4938 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 4939 0x1CC); 4940 /* Sets PCS loopback at 1Gbs */ 4941 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 4942 0x1046); 4943 break; 4944 } 4945 4946 /* 4947 * The following registers should be set for e1000_phy_bm phy type. 4948 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy. 4949 * For others, we do not need to set these registers. 4950 */ 4951 if (hw->phy.type == e1000_phy_bm) { 4952 /* Set Default MAC Interface speed to 1GB */ 4953 e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg); 4954 phy_reg &= ~0x0007; 4955 phy_reg |= 0x006; 4956 e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg); 4957 /* Assert SW reset for above settings to take effect */ 4958 e1000_phy_commit(hw); 4959 msec_delay(1); 4960 /* Force Full Duplex */ 4961 e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 4962 e1000_write_phy_reg(hw, PHY_REG(769, 16), phy_reg | 0x000C); 4963 /* Set Link Up (in force link) */ 4964 e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg); 4965 e1000_write_phy_reg(hw, PHY_REG(776, 16), phy_reg | 0x0040); 4966 /* Force Link */ 4967 e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 4968 e1000_write_phy_reg(hw, PHY_REG(769, 16), phy_reg | 0x0040); 4969 /* Set Early Link Enable */ 4970 e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg); 4971 e1000_write_phy_reg(hw, PHY_REG(769, 20), phy_reg | 0x0400); 4972 } 4973 4974 /* Set loopback */ 4975 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 4976 4977 msec_delay(250); 4978 4979 /* Now set up the MAC to the same speed/duplex as the PHY. */ 4980 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4981 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4982 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4983 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4984 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 4985 E1000_CTRL_FD); /* Force Duplex to FULL */ 4986 4987 switch (hw->mac.type) { 4988 case e1000_82540: 4989 case e1000_82545: 4990 case e1000_82545_rev_3: 4991 case e1000_82546: 4992 case e1000_82546_rev_3: 4993 /* 4994 * For some serdes we'll need to commit the writes now 4995 * so that the status is updated on link 4996 */ 4997 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 4998 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4999 msec_delay(100); 5000 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5001 } 5002 5003 if (hw->phy.media_type == e1000_media_type_copper) { 5004 /* Invert Loss of Signal */ 5005 ctrl |= E1000_CTRL_ILOS; 5006 } else { 5007 /* Set ILOS on fiber nic if half duplex is detected */ 5008 status = E1000_READ_REG(hw, E1000_STATUS); 5009 if ((status & E1000_STATUS_FD) == 0) 5010 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5011 } 5012 break; 5013 5014 case e1000_82571: 5015 case e1000_82572: 5016 /* 5017 * The fiber/SerDes versions of this adapter do not contain an 5018 * accessible PHY. Therefore, loopback beyond MAC must be done 5019 * using SerDes analog loopback. 5020 */ 5021 if (hw->phy.media_type != e1000_media_type_copper) { 5022 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5023 txcw = E1000_READ_REG(hw, E1000_TXCW); 5024 txcw &= ~((uint32_t)1 << 31); 5025 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5026 5027 /* 5028 * Write 0x410 to Serdes Control register 5029 * to enable Serdes analog loopback 5030 */ 5031 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5032 msec_delay(10); 5033 } 5034 5035 status = E1000_READ_REG(hw, E1000_STATUS); 5036 /* Set ILOS on fiber nic if half duplex is detected */ 5037 if ((hw->phy.media_type == e1000_media_type_fiber) && 5038 ((status & E1000_STATUS_FD) == 0 || 5039 (status & E1000_STATUS_LU) == 0)) 5040 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5041 else if (hw->phy.media_type == e1000_media_type_internal_serdes) 5042 ctrl |= E1000_CTRL_SLU; 5043 break; 5044 5045 case e1000_82573: 5046 ctrl |= E1000_CTRL_ILOS; 5047 break; 5048 case e1000_ich9lan: 5049 case e1000_ich10lan: 5050 ctrl |= E1000_CTRL_SLU; 5051 break; 5052 } 5053 if (hw->phy.type == e1000_phy_bm) 5054 ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS; 5055 5056 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5057 } 5058 5059 static void 5060 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 5061 { 5062 struct e1000_hw *hw; 5063 uint32_t rctl; 5064 uint32_t ctrl_ext; 5065 uint32_t ctrl; 5066 uint32_t status; 5067 uint32_t txcw; 5068 uint16_t phydata; 5069 5070 hw = &Adapter->shared; 5071 5072 /* Disable Smart Power Down */ 5073 phy_spd_state(hw, B_FALSE); 5074 5075 switch (hw->mac.type) { 5076 case e1000_82571: 5077 case e1000_82572: 5078 switch (hw->phy.media_type) { 5079 case e1000_media_type_copper: 5080 /* Force link up (Must be done before the PHY writes) */ 5081 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5082 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 5083 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5084 5085 rctl = E1000_READ_REG(hw, E1000_RCTL); 5086 rctl |= (E1000_RCTL_EN | 5087 E1000_RCTL_SBP | 5088 E1000_RCTL_UPE | 5089 E1000_RCTL_MPE | 5090 E1000_RCTL_LPE | 5091 E1000_RCTL_BAM); /* 0x803E */ 5092 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 5093 5094 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5095 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 5096 E1000_CTRL_EXT_SDP6_DATA | 5097 E1000_CTRL_EXT_SDP7_DATA | 5098 E1000_CTRL_EXT_SDP4_DIR | 5099 E1000_CTRL_EXT_SDP6_DIR | 5100 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 5101 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5102 5103 /* 5104 * This sequence tunes the PHY's SDP and no customer 5105 * settable values. For background, see comments above 5106 * e1000g_set_internal_loopback(). 5107 */ 5108 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 5109 msec_delay(10); 5110 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 5111 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 5112 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 5113 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 5114 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 5115 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 5116 5117 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 5118 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 5119 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 5120 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 5121 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 5122 5123 msec_delay(50); 5124 break; 5125 case e1000_media_type_fiber: 5126 case e1000_media_type_internal_serdes: 5127 status = E1000_READ_REG(hw, E1000_STATUS); 5128 if (((status & E1000_STATUS_LU) == 0) || 5129 (hw->phy.media_type == 5130 e1000_media_type_internal_serdes)) { 5131 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5132 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5133 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5134 } 5135 5136 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5137 txcw = E1000_READ_REG(hw, E1000_TXCW); 5138 txcw &= ~((uint32_t)1 << 31); 5139 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5140 5141 /* 5142 * Write 0x410 to Serdes Control register 5143 * to enable Serdes analog loopback 5144 */ 5145 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5146 msec_delay(10); 5147 break; 5148 default: 5149 break; 5150 } 5151 break; 5152 case e1000_82574: 5153 case e1000_80003es2lan: 5154 case e1000_ich9lan: 5155 case e1000_ich10lan: 5156 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 5157 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 5158 phydata | (1 << 5)); 5159 Adapter->param_adv_autoneg = 1; 5160 Adapter->param_adv_1000fdx = 1; 5161 (void) e1000g_reset_link(Adapter); 5162 break; 5163 } 5164 } 5165 5166 static void 5167 e1000g_set_external_loopback_100(struct e1000g *Adapter) 5168 { 5169 struct e1000_hw *hw; 5170 uint32_t ctrl; 5171 uint16_t phy_ctrl; 5172 5173 hw = &Adapter->shared; 5174 5175 /* Disable Smart Power Down */ 5176 phy_spd_state(hw, B_FALSE); 5177 5178 phy_ctrl = (MII_CR_FULL_DUPLEX | 5179 MII_CR_SPEED_100); 5180 5181 /* Force 100/FD, reset PHY */ 5182 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5183 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 5184 msec_delay(10); 5185 5186 /* Force 100/FD */ 5187 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5188 phy_ctrl); /* 0x2100 */ 5189 msec_delay(10); 5190 5191 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5192 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5193 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5194 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5195 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5196 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5197 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 5198 E1000_CTRL_FD); /* Force Duplex to FULL */ 5199 5200 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5201 } 5202 5203 static void 5204 e1000g_set_external_loopback_10(struct e1000g *Adapter) 5205 { 5206 struct e1000_hw *hw; 5207 uint32_t ctrl; 5208 uint16_t phy_ctrl; 5209 5210 hw = &Adapter->shared; 5211 5212 /* Disable Smart Power Down */ 5213 phy_spd_state(hw, B_FALSE); 5214 5215 phy_ctrl = (MII_CR_FULL_DUPLEX | 5216 MII_CR_SPEED_10); 5217 5218 /* Force 10/FD, reset PHY */ 5219 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5220 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 5221 msec_delay(10); 5222 5223 /* Force 10/FD */ 5224 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5225 phy_ctrl); /* 0x0100 */ 5226 msec_delay(10); 5227 5228 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5229 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5230 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5231 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5232 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5233 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5234 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 5235 E1000_CTRL_FD); /* Force Duplex to FULL */ 5236 5237 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5238 } 5239 5240 #ifdef __sparc 5241 static boolean_t 5242 e1000g_find_mac_address(struct e1000g *Adapter) 5243 { 5244 struct e1000_hw *hw = &Adapter->shared; 5245 uchar_t *bytes; 5246 struct ether_addr sysaddr; 5247 uint_t nelts; 5248 int err; 5249 boolean_t found = B_FALSE; 5250 5251 /* 5252 * The "vendor's factory-set address" may already have 5253 * been extracted from the chip, but if the property 5254 * "local-mac-address" is set we use that instead. 5255 * 5256 * We check whether it looks like an array of 6 5257 * bytes (which it should, if OBP set it). If we can't 5258 * make sense of it this way, we'll ignore it. 5259 */ 5260 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5261 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 5262 if (err == DDI_PROP_SUCCESS) { 5263 if (nelts == ETHERADDRL) { 5264 while (nelts--) 5265 hw->mac.addr[nelts] = bytes[nelts]; 5266 found = B_TRUE; 5267 } 5268 ddi_prop_free(bytes); 5269 } 5270 5271 /* 5272 * Look up the OBP property "local-mac-address?". If the user has set 5273 * 'local-mac-address? = false', use "the system address" instead. 5274 */ 5275 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5276 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5277 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5278 if (localetheraddr(NULL, &sysaddr) != 0) { 5279 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5280 found = B_TRUE; 5281 } 5282 } 5283 ddi_prop_free(bytes); 5284 } 5285 5286 /* 5287 * Finally(!), if there's a valid "mac-address" property (created 5288 * if we netbooted from this interface), we must use this instead 5289 * of any of the above to ensure that the NFS/install server doesn't 5290 * get confused by the address changing as Solaris takes over! 5291 */ 5292 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5293 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5294 if (err == DDI_PROP_SUCCESS) { 5295 if (nelts == ETHERADDRL) { 5296 while (nelts--) 5297 hw->mac.addr[nelts] = bytes[nelts]; 5298 found = B_TRUE; 5299 } 5300 ddi_prop_free(bytes); 5301 } 5302 5303 if (found) { 5304 bcopy(hw->mac.addr, hw->mac.perm_addr, 5305 ETHERADDRL); 5306 } 5307 5308 return (found); 5309 } 5310 #endif 5311 5312 static int 5313 e1000g_add_intrs(struct e1000g *Adapter) 5314 { 5315 dev_info_t *devinfo; 5316 int intr_types; 5317 int rc; 5318 5319 devinfo = Adapter->dip; 5320 5321 /* Get supported interrupt types */ 5322 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5323 5324 if (rc != DDI_SUCCESS) { 5325 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5326 "Get supported interrupt types failed: %d\n", rc); 5327 return (DDI_FAILURE); 5328 } 5329 5330 /* 5331 * Based on Intel Technical Advisory document (TA-160), there are some 5332 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5333 * that it supports MSI, but in fact has problems. 5334 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5335 * PCI/PCI-X NICs. 5336 */ 5337 if (Adapter->shared.mac.type < e1000_82571) 5338 Adapter->msi_enable = B_FALSE; 5339 5340 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5341 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5342 5343 if (rc != DDI_SUCCESS) { 5344 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5345 "Add MSI failed, trying Legacy interrupts\n"); 5346 } else { 5347 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5348 } 5349 } 5350 5351 if ((Adapter->intr_type == 0) && 5352 (intr_types & DDI_INTR_TYPE_FIXED)) { 5353 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5354 5355 if (rc != DDI_SUCCESS) { 5356 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5357 "Add Legacy interrupts failed\n"); 5358 return (DDI_FAILURE); 5359 } 5360 5361 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5362 } 5363 5364 if (Adapter->intr_type == 0) { 5365 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5366 "No interrupts registered\n"); 5367 return (DDI_FAILURE); 5368 } 5369 5370 return (DDI_SUCCESS); 5371 } 5372 5373 /* 5374 * e1000g_intr_add() handles MSI/Legacy interrupts 5375 */ 5376 static int 5377 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5378 { 5379 dev_info_t *devinfo; 5380 int count, avail, actual; 5381 int x, y, rc, inum = 0; 5382 int flag; 5383 ddi_intr_handler_t *intr_handler; 5384 5385 devinfo = Adapter->dip; 5386 5387 /* get number of interrupts */ 5388 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5389 if ((rc != DDI_SUCCESS) || (count == 0)) { 5390 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5391 "Get interrupt number failed. Return: %d, count: %d\n", 5392 rc, count); 5393 return (DDI_FAILURE); 5394 } 5395 5396 /* get number of available interrupts */ 5397 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5398 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5399 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5400 "Get interrupt available number failed. " 5401 "Return: %d, available: %d\n", rc, avail); 5402 return (DDI_FAILURE); 5403 } 5404 5405 if (avail < count) { 5406 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5407 "Interrupts count: %d, available: %d\n", 5408 count, avail); 5409 } 5410 5411 /* Allocate an array of interrupt handles */ 5412 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5413 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5414 5415 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5416 flag = DDI_INTR_ALLOC_NORMAL; 5417 5418 /* call ddi_intr_alloc() */ 5419 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5420 count, &actual, flag); 5421 5422 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5423 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5424 "Allocate interrupts failed: %d\n", rc); 5425 5426 kmem_free(Adapter->htable, Adapter->intr_size); 5427 return (DDI_FAILURE); 5428 } 5429 5430 if (actual < count) { 5431 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5432 "Interrupts requested: %d, received: %d\n", 5433 count, actual); 5434 } 5435 5436 Adapter->intr_cnt = actual; 5437 5438 /* Get priority for first msi, assume remaining are all the same */ 5439 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5440 5441 if (rc != DDI_SUCCESS) { 5442 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5443 "Get interrupt priority failed: %d\n", rc); 5444 5445 /* Free already allocated intr */ 5446 for (y = 0; y < actual; y++) 5447 (void) ddi_intr_free(Adapter->htable[y]); 5448 5449 kmem_free(Adapter->htable, Adapter->intr_size); 5450 return (DDI_FAILURE); 5451 } 5452 5453 /* 5454 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5455 * use the interrupt service routine e1000g_intr_pciexpress() 5456 * to avoid interrupt stealing when sharing interrupt with other 5457 * devices. 5458 */ 5459 if (Adapter->shared.mac.type < e1000_82571) 5460 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5461 else 5462 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5463 5464 /* Call ddi_intr_add_handler() */ 5465 for (x = 0; x < actual; x++) { 5466 rc = ddi_intr_add_handler(Adapter->htable[x], 5467 intr_handler, (caddr_t)Adapter, NULL); 5468 5469 if (rc != DDI_SUCCESS) { 5470 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5471 "Add interrupt handler failed: %d\n", rc); 5472 5473 /* Remove already added handler */ 5474 for (y = 0; y < x; y++) 5475 (void) ddi_intr_remove_handler( 5476 Adapter->htable[y]); 5477 5478 /* Free already allocated intr */ 5479 for (y = 0; y < actual; y++) 5480 (void) ddi_intr_free(Adapter->htable[y]); 5481 5482 kmem_free(Adapter->htable, Adapter->intr_size); 5483 return (DDI_FAILURE); 5484 } 5485 } 5486 5487 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5488 5489 if (rc != DDI_SUCCESS) { 5490 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5491 "Get interrupt cap failed: %d\n", rc); 5492 5493 /* Free already allocated intr */ 5494 for (y = 0; y < actual; y++) { 5495 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5496 (void) ddi_intr_free(Adapter->htable[y]); 5497 } 5498 5499 kmem_free(Adapter->htable, Adapter->intr_size); 5500 return (DDI_FAILURE); 5501 } 5502 5503 return (DDI_SUCCESS); 5504 } 5505 5506 static int 5507 e1000g_rem_intrs(struct e1000g *Adapter) 5508 { 5509 int x; 5510 int rc; 5511 5512 for (x = 0; x < Adapter->intr_cnt; x++) { 5513 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5514 if (rc != DDI_SUCCESS) { 5515 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5516 "Remove intr handler failed: %d\n", rc); 5517 return (DDI_FAILURE); 5518 } 5519 5520 rc = ddi_intr_free(Adapter->htable[x]); 5521 if (rc != DDI_SUCCESS) { 5522 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5523 "Free intr failed: %d\n", rc); 5524 return (DDI_FAILURE); 5525 } 5526 } 5527 5528 kmem_free(Adapter->htable, Adapter->intr_size); 5529 5530 return (DDI_SUCCESS); 5531 } 5532 5533 static int 5534 e1000g_enable_intrs(struct e1000g *Adapter) 5535 { 5536 int x; 5537 int rc; 5538 5539 /* Enable interrupts */ 5540 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5541 /* Call ddi_intr_block_enable() for MSI */ 5542 rc = ddi_intr_block_enable(Adapter->htable, 5543 Adapter->intr_cnt); 5544 if (rc != DDI_SUCCESS) { 5545 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5546 "Enable block intr failed: %d\n", rc); 5547 return (DDI_FAILURE); 5548 } 5549 } else { 5550 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5551 for (x = 0; x < Adapter->intr_cnt; x++) { 5552 rc = ddi_intr_enable(Adapter->htable[x]); 5553 if (rc != DDI_SUCCESS) { 5554 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5555 "Enable intr failed: %d\n", rc); 5556 return (DDI_FAILURE); 5557 } 5558 } 5559 } 5560 5561 return (DDI_SUCCESS); 5562 } 5563 5564 static int 5565 e1000g_disable_intrs(struct e1000g *Adapter) 5566 { 5567 int x; 5568 int rc; 5569 5570 /* Disable all interrupts */ 5571 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5572 rc = ddi_intr_block_disable(Adapter->htable, 5573 Adapter->intr_cnt); 5574 if (rc != DDI_SUCCESS) { 5575 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5576 "Disable block intr failed: %d\n", rc); 5577 return (DDI_FAILURE); 5578 } 5579 } else { 5580 for (x = 0; x < Adapter->intr_cnt; x++) { 5581 rc = ddi_intr_disable(Adapter->htable[x]); 5582 if (rc != DDI_SUCCESS) { 5583 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5584 "Disable intr failed: %d\n", rc); 5585 return (DDI_FAILURE); 5586 } 5587 } 5588 } 5589 5590 return (DDI_SUCCESS); 5591 } 5592 5593 /* 5594 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5595 */ 5596 static void 5597 e1000g_get_phy_state(struct e1000g *Adapter) 5598 { 5599 struct e1000_hw *hw = &Adapter->shared; 5600 5601 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5602 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5603 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 5604 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 5605 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 5606 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 5607 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5608 &Adapter->phy_1000t_status); 5609 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 5610 5611 Adapter->param_autoneg_cap = 5612 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5613 Adapter->param_pause_cap = 5614 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5615 Adapter->param_asym_pause_cap = 5616 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5617 Adapter->param_1000fdx_cap = 5618 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5619 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5620 Adapter->param_1000hdx_cap = 5621 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5622 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5623 Adapter->param_100t4_cap = 5624 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5625 Adapter->param_100fdx_cap = 5626 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5627 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5628 Adapter->param_100hdx_cap = 5629 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5630 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5631 Adapter->param_10fdx_cap = 5632 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5633 Adapter->param_10hdx_cap = 5634 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5635 5636 Adapter->param_adv_autoneg = hw->mac.autoneg; 5637 Adapter->param_adv_pause = 5638 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5639 Adapter->param_adv_asym_pause = 5640 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5641 Adapter->param_adv_1000hdx = 5642 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5643 Adapter->param_adv_100t4 = 5644 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5645 if (Adapter->param_adv_autoneg == 1) { 5646 Adapter->param_adv_1000fdx = 5647 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5648 Adapter->param_adv_100fdx = 5649 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5650 Adapter->param_adv_100hdx = 5651 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5652 Adapter->param_adv_10fdx = 5653 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5654 Adapter->param_adv_10hdx = 5655 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5656 } 5657 5658 Adapter->param_lp_autoneg = 5659 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5660 Adapter->param_lp_pause = 5661 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5662 Adapter->param_lp_asym_pause = 5663 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5664 Adapter->param_lp_1000fdx = 5665 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5666 Adapter->param_lp_1000hdx = 5667 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5668 Adapter->param_lp_100t4 = 5669 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5670 Adapter->param_lp_100fdx = 5671 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5672 Adapter->param_lp_100hdx = 5673 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5674 Adapter->param_lp_10fdx = 5675 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5676 Adapter->param_lp_10hdx = 5677 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5678 } 5679 5680 /* 5681 * FMA support 5682 */ 5683 5684 int 5685 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5686 { 5687 ddi_fm_error_t de; 5688 5689 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5690 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5691 return (de.fme_status); 5692 } 5693 5694 int 5695 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5696 { 5697 ddi_fm_error_t de; 5698 5699 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5700 return (de.fme_status); 5701 } 5702 5703 /* 5704 * The IO fault service error handling callback function 5705 */ 5706 /* ARGSUSED2 */ 5707 static int 5708 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5709 { 5710 /* 5711 * as the driver can always deal with an error in any dma or 5712 * access handle, we can just return the fme_status value. 5713 */ 5714 pci_ereport_post(dip, err, NULL); 5715 return (err->fme_status); 5716 } 5717 5718 static void 5719 e1000g_fm_init(struct e1000g *Adapter) 5720 { 5721 ddi_iblock_cookie_t iblk; 5722 int fma_acc_flag, fma_dma_flag; 5723 5724 /* Only register with IO Fault Services if we have some capability */ 5725 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5726 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5727 fma_acc_flag = 1; 5728 } else { 5729 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5730 fma_acc_flag = 0; 5731 } 5732 5733 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5734 fma_dma_flag = 1; 5735 } else { 5736 fma_dma_flag = 0; 5737 } 5738 5739 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5740 5741 if (Adapter->fm_capabilities) { 5742 5743 /* Register capabilities with IO Fault Services */ 5744 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5745 5746 /* 5747 * Initialize pci ereport capabilities if ereport capable 5748 */ 5749 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5750 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5751 pci_ereport_setup(Adapter->dip); 5752 5753 /* 5754 * Register error callback if error callback capable 5755 */ 5756 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5757 ddi_fm_handler_register(Adapter->dip, 5758 e1000g_fm_error_cb, (void*) Adapter); 5759 } 5760 } 5761 5762 static void 5763 e1000g_fm_fini(struct e1000g *Adapter) 5764 { 5765 /* Only unregister FMA capabilities if we registered some */ 5766 if (Adapter->fm_capabilities) { 5767 5768 /* 5769 * Release any resources allocated by pci_ereport_setup() 5770 */ 5771 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5772 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5773 pci_ereport_teardown(Adapter->dip); 5774 5775 /* 5776 * Un-register error callback if error callback capable 5777 */ 5778 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5779 ddi_fm_handler_unregister(Adapter->dip); 5780 5781 /* Unregister from IO Fault Services */ 5782 ddi_fm_fini(Adapter->dip); 5783 } 5784 } 5785 5786 void 5787 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 5788 { 5789 uint64_t ena; 5790 char buf[FM_MAX_CLASS]; 5791 5792 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5793 ena = fm_ena_generate(0, FM_ENA_FMT1); 5794 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 5795 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 5796 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5797 } 5798 } 5799 5800 /* 5801 * quiesce(9E) entry point. 5802 * 5803 * This function is called when the system is single-threaded at high 5804 * PIL with preemption disabled. Therefore, this function must not be 5805 * blocked. 5806 * 5807 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 5808 * DDI_FAILURE indicates an error condition and should almost never happen. 5809 */ 5810 static int 5811 e1000g_quiesce(dev_info_t *devinfo) 5812 { 5813 struct e1000g *Adapter; 5814 5815 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 5816 5817 if (Adapter == NULL) 5818 return (DDI_FAILURE); 5819 5820 e1000g_clear_all_interrupts(Adapter); 5821 5822 (void) e1000_reset_hw(&Adapter->shared); 5823 5824 /* Setup our HW Tx Head & Tail descriptor pointers */ 5825 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 5826 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 5827 5828 /* Setup our HW Rx Head & Tail descriptor pointers */ 5829 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 5830 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 5831 5832 return (DDI_SUCCESS); 5833 } 5834 5835 static int 5836 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 5837 uint_t pr_valsize, void *pr_val) 5838 { 5839 link_flowctrl_t fl; 5840 int err = 0; 5841 5842 ASSERT(pr_valsize > 0); 5843 switch (pr_num) { 5844 case MAC_PROP_AUTONEG: 5845 *(uint8_t *)pr_val = 5846 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0); 5847 break; 5848 case MAC_PROP_FLOWCTRL: 5849 if (pr_valsize < sizeof (link_flowctrl_t)) 5850 return (EINVAL); 5851 fl = LINK_FLOWCTRL_BI; 5852 bcopy(&fl, pr_val, sizeof (fl)); 5853 break; 5854 case MAC_PROP_ADV_1000FDX_CAP: 5855 case MAC_PROP_EN_1000FDX_CAP: 5856 *(uint8_t *)pr_val = 5857 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5858 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5859 break; 5860 case MAC_PROP_ADV_1000HDX_CAP: 5861 case MAC_PROP_EN_1000HDX_CAP: 5862 *(uint8_t *)pr_val = 5863 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5864 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5865 break; 5866 case MAC_PROP_ADV_100FDX_CAP: 5867 case MAC_PROP_EN_100FDX_CAP: 5868 *(uint8_t *)pr_val = 5869 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5870 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5871 break; 5872 case MAC_PROP_ADV_100HDX_CAP: 5873 case MAC_PROP_EN_100HDX_CAP: 5874 *(uint8_t *)pr_val = 5875 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5876 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5877 break; 5878 case MAC_PROP_ADV_10FDX_CAP: 5879 case MAC_PROP_EN_10FDX_CAP: 5880 *(uint8_t *)pr_val = 5881 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5882 break; 5883 case MAC_PROP_ADV_10HDX_CAP: 5884 case MAC_PROP_EN_10HDX_CAP: 5885 *(uint8_t *)pr_val = 5886 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5887 break; 5888 default: 5889 err = ENOTSUP; 5890 break; 5891 } 5892 return (err); 5893 } 5894 5895 /* 5896 * synchronize the adv* and en* parameters. 5897 * 5898 * See comments in <sys/dld.h> for details of the *_en_* 5899 * parameters. The usage of ndd for setting adv parameters will 5900 * synchronize all the en parameters with the e1000g parameters, 5901 * implicitly disabling any settings made via dladm. 5902 */ 5903 static void 5904 e1000g_param_sync(struct e1000g *Adapter) 5905 { 5906 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 5907 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 5908 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 5909 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 5910 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 5911 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 5912 } 5913 5914 /* 5915 * e1000g_get_driver_control - tell manageability firmware that the driver 5916 * has control. 5917 */ 5918 static void 5919 e1000g_get_driver_control(struct e1000_hw *hw) 5920 { 5921 uint32_t ctrl_ext; 5922 uint32_t swsm; 5923 5924 /* tell manageability firmware the driver has taken over */ 5925 switch (hw->mac.type) { 5926 case e1000_82573: 5927 swsm = E1000_READ_REG(hw, E1000_SWSM); 5928 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 5929 break; 5930 case e1000_82571: 5931 case e1000_82572: 5932 case e1000_82574: 5933 case e1000_80003es2lan: 5934 case e1000_ich8lan: 5935 case e1000_ich9lan: 5936 case e1000_ich10lan: 5937 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5938 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 5939 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 5940 break; 5941 default: 5942 /* no manageability firmware: do nothing */ 5943 break; 5944 } 5945 } 5946 5947 /* 5948 * e1000g_release_driver_control - tell manageability firmware that the driver 5949 * has released control. 5950 */ 5951 static void 5952 e1000g_release_driver_control(struct e1000_hw *hw) 5953 { 5954 uint32_t ctrl_ext; 5955 uint32_t swsm; 5956 5957 /* tell manageability firmware the driver has released control */ 5958 switch (hw->mac.type) { 5959 case e1000_82573: 5960 swsm = E1000_READ_REG(hw, E1000_SWSM); 5961 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 5962 break; 5963 case e1000_82571: 5964 case e1000_82572: 5965 case e1000_82574: 5966 case e1000_80003es2lan: 5967 case e1000_ich8lan: 5968 case e1000_ich9lan: 5969 case e1000_ich10lan: 5970 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5971 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 5972 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 5973 break; 5974 default: 5975 /* no manageability firmware: do nothing */ 5976 break; 5977 } 5978 } 5979 5980 /* 5981 * Restore e1000g promiscuous mode. 5982 */ 5983 static void 5984 e1000g_restore_promisc(struct e1000g *Adapter) 5985 { 5986 if (Adapter->e1000g_promisc) { 5987 uint32_t rctl; 5988 5989 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 5990 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 5991 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 5992 } 5993 } 5994