1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * ********************************************************************** 30 * * 31 * Module Name: * 32 * e1000g_main.c * 33 * * 34 * Abstract: * 35 * This file contains the interface routine for the solaris OS. * 36 * It has all DDI entry point routines and GLD entry point * 37 * routines. * 38 * This file also contains routines that takes care of initialization * 39 * uninit routine and interrupt routine * 40 * * 41 * * 42 * Environment: * 43 * Kernel Mode - * 44 * * 45 * ********************************************************************** 46 */ 47 48 #include <sys/dlpi.h> 49 #include <sys/mac.h> 50 #include "e1000g_sw.h" 51 #include "e1000g_debug.h" 52 53 #define E1000_RX_INTPT_TIME 128 54 #define E1000_RX_PKT_CNT 8 55 56 static char ident[] = "Intel PRO/1000 Ethernet 5.1.8"; 57 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 58 static char e1000g_version[] = "Driver Ver. 5.1.8"; 59 60 /* 61 * Proto types for DDI entry points 62 */ 63 static int e1000gattach(dev_info_t *, ddi_attach_cmd_t); 64 static int e1000gdetach(dev_info_t *, ddi_detach_cmd_t); 65 66 /* 67 * init and intr routines prototype 68 */ 69 static int e1000g_resume(dev_info_t *devinfo); 70 static int e1000g_suspend(dev_info_t *devinfo); 71 static uint_t e1000g_intr_pciexpress(caddr_t); 72 static uint_t e1000g_intr(caddr_t); 73 static void e1000g_intr_work(struct e1000g *, uint32_t); 74 #pragma inline(e1000g_intr_work) 75 static int e1000g_init(struct e1000g *); 76 static int e1000g_start(struct e1000g *); 77 static void e1000g_stop(struct e1000g *); 78 static int e1000g_m_start(void *); 79 static void e1000g_m_stop(void *); 80 static int e1000g_m_promisc(void *, boolean_t); 81 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 82 static int e1000g_m_unicst(void *, const uint8_t *); 83 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 84 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 85 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 86 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 87 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 88 static void e1000g_m_blank(void *, time_t, uint32_t); 89 static void e1000g_m_resources(void *); 90 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 91 static void e1000g_init_locks(struct e1000g *Adapter); 92 static void e1000g_destroy_locks(struct e1000g *Adapter); 93 static int e1000g_set_driver_params(struct e1000g *Adapter); 94 static int e1000g_register_mac(struct e1000g *Adapter); 95 static boolean_t e1000g_rx_drain(struct e1000g *Adapter); 96 static boolean_t e1000g_tx_drain(struct e1000g *Adapter); 97 static void e1000g_init_unicst(struct e1000g *Adapter); 98 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 99 100 /* 101 * Local routines 102 */ 103 static void e1000g_tx_drop(struct e1000g *Adapter); 104 static void e1000g_link_timer(void *); 105 static void e1000g_LocalTimer(void *); 106 static boolean_t e1000g_link_check(struct e1000g *); 107 static boolean_t e1000g_stall_check(struct e1000g *); 108 static void e1000g_smartspeed(struct e1000g *); 109 static void e1000g_getparam(struct e1000g *Adapter); 110 static int e1000g_getprop(struct e1000g *, char *, int, int, int); 111 static void e1000g_error(dev_info_t *dip, char *fmt, char *a1, 112 char *a2, char *a3, char *a4, char *a5, char *a6); 113 static void enable_timeout(struct e1000g *Adapter); 114 static void disable_timeout(struct e1000g *Adapter); 115 static void start_timeout(struct e1000g *Adapter); 116 static void restart_timeout(struct e1000g *Adapter); 117 static void stop_timeout(struct e1000g *Adapter); 118 static void e1000g_force_speed_duplex(struct e1000g *Adapter); 119 static void e1000g_get_max_frame_size(struct e1000g *Adapter); 120 static boolean_t is_valid_mac_addr(uint8_t *mac_addr); 121 static void e1000g_unattach(dev_info_t *, struct e1000g *); 122 static void e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 123 static void e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 124 static void e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 125 static void e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 126 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *e1000gp, 127 struct iocblk *iocp, mblk_t *mp); 128 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *Adapter, 129 struct iocblk *iocp, mblk_t *mp); 130 static boolean_t e1000g_set_loopback_mode(struct e1000g *Adapter, 131 uint32_t mode); 132 static void e1000g_set_internal_loopback(struct e1000g *Adapter); 133 static void e1000g_set_external_loopback_1000(struct e1000g *Adapter); 134 static void e1000g_set_external_loopback_100(struct e1000g *Adapter); 135 static void e1000g_set_external_loopback_10(struct e1000g *Adapter); 136 static int e1000g_add_intrs(struct e1000g *Adapter); 137 static int e1000g_intr_add(struct e1000g *Adapter, int intr_type); 138 static int e1000g_rem_intrs(struct e1000g *Adapter); 139 static int e1000g_enable_intrs(struct e1000g *Adapter); 140 static int e1000g_disable_intrs(struct e1000g *Adapter); 141 static boolean_t e1000g_link_up(struct e1000g *Adapter); 142 #ifdef __sparc 143 static boolean_t e1000g_find_mac_address(struct e1000g *Adapter); 144 #endif 145 146 static struct cb_ops cb_ws_ops = { 147 nulldev, /* cb_open */ 148 nulldev, /* cb_close */ 149 nodev, /* cb_strategy */ 150 nodev, /* cb_print */ 151 nodev, /* cb_dump */ 152 nodev, /* cb_read */ 153 nodev, /* cb_write */ 154 nodev, /* cb_ioctl */ 155 nodev, /* cb_devmap */ 156 nodev, /* cb_mmap */ 157 nodev, /* cb_segmap */ 158 nochpoll, /* cb_chpoll */ 159 ddi_prop_op, /* cb_prop_op */ 160 NULL, /* cb_stream */ 161 D_MP | D_HOTPLUG, /* cb_flag */ 162 CB_REV, /* cb_rev */ 163 nodev, /* cb_aread */ 164 nodev /* cb_awrite */ 165 }; 166 167 static struct dev_ops ws_ops = { 168 DEVO_REV, /* devo_rev */ 169 0, /* devo_refcnt */ 170 NULL, /* devo_getinfo */ 171 nulldev, /* devo_identify */ 172 nulldev, /* devo_probe */ 173 e1000gattach, /* devo_attach */ 174 e1000gdetach, /* devo_detach */ 175 nodev, /* devo_reset */ 176 &cb_ws_ops, /* devo_cb_ops */ 177 NULL, /* devo_bus_ops */ 178 ddi_power /* devo_power */ 179 }; 180 181 static struct modldrv modldrv = { 182 &mod_driverops, /* Type of module. This one is a driver */ 183 ident, /* Discription string */ 184 &ws_ops, /* driver ops */ 185 }; 186 187 static struct modlinkage modlinkage = { 188 MODREV_1, &modldrv, NULL 189 }; 190 191 /* 192 * DMA access attributes <Little Endian Card> 193 */ 194 static ddi_device_acc_attr_t accattr1 = { 195 DDI_DEVICE_ATTR_V0, 196 DDI_STRUCTURE_LE_ACC, 197 DDI_STRICTORDER_ACC, 198 }; 199 200 #define E1000G_M_CALLBACK_FLAGS (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB) 201 202 static mac_callbacks_t e1000g_m_callbacks = { 203 E1000G_M_CALLBACK_FLAGS, 204 e1000g_m_stat, 205 e1000g_m_start, 206 e1000g_m_stop, 207 e1000g_m_promisc, 208 e1000g_m_multicst, 209 e1000g_m_unicst, 210 e1000g_m_tx, 211 e1000g_m_resources, 212 e1000g_m_ioctl, 213 e1000g_m_getcapab 214 }; 215 216 /* 217 * Global variables 218 */ 219 boolean_t force_detach_enabled = B_FALSE; 220 uint32_t e1000g_mblks_pending = 0; 221 /* 222 * The rwlock is defined to protect the whole processing of rx recycling 223 * and the rx packets release in detach processing to make them mutually 224 * exclusive. 225 * The rx recycling processes different rx packets in different threads, 226 * so it will be protected with RW_READER and it won't block any other rx 227 * recycling threads. 228 * While the detach processing will be protected with RW_WRITER to make 229 * it mutually exclusive with the rx recycling. 230 */ 231 krwlock_t e1000g_rx_detach_lock; 232 /* 233 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 234 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 235 * If there are many e1000g instances, the system may run out of DVMA 236 * resources during the initialization of the instances, then the flag will 237 * be changed to "USE_DMA". Because different e1000g instances are initialized 238 * in parallel, we need to use this lock to protect the flag. 239 */ 240 krwlock_t e1000g_dma_type_lock; 241 242 243 /* 244 * Loadable module configuration entry points for the driver 245 */ 246 247 /* 248 * ********************************************************************** 249 * Name: _init * 250 * * 251 * Description: * 252 * Initializes a loadable module. It is called before * 253 * any other routine in a loadable module. * 254 * All global locks are intialised here and it returns the retun * 255 * value from mod_install() * 256 * This is mandotary function for the driver * 257 * Parameter Passed: * 258 * None * 259 * Return Value: * 260 * 0 on success * 261 * Functions called * 262 * mod_install() (system call) * 263 * * 264 * ********************************************************************** 265 */ 266 int 267 _init(void) 268 { 269 int status; 270 271 mac_init_ops(&ws_ops, WSNAME); 272 status = mod_install(&modlinkage); 273 if (status != DDI_SUCCESS) 274 mac_fini_ops(&ws_ops); 275 else { 276 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 277 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 278 } 279 280 return (status); 281 } 282 283 /* 284 * ********************************************************************** 285 * Name: _fini * 286 * * 287 * Description: * 288 * Prepares a loadable module for unloading. It is * 289 * called when the system wants to unload a module. * 290 * This is mandotary function for the driver * 291 * Parameter Passed: * 292 * None * 293 * Return Value: * 294 * 0 on success * 295 * Functions called * 296 * mod_remove() (system call) * 297 * * 298 * * 299 * * 300 * ********************************************************************** 301 */ 302 int 303 _fini(void) 304 { 305 int status; 306 307 rw_enter(&e1000g_rx_detach_lock, RW_READER); 308 if (e1000g_mblks_pending != 0) { 309 rw_exit(&e1000g_rx_detach_lock); 310 return (EBUSY); 311 } 312 rw_exit(&e1000g_rx_detach_lock); 313 314 status = mod_remove(&modlinkage); 315 if (status == DDI_SUCCESS) { 316 mac_fini_ops(&ws_ops); 317 rw_destroy(&e1000g_rx_detach_lock); 318 rw_destroy(&e1000g_dma_type_lock); 319 } 320 321 return (status); 322 } 323 324 /* 325 * ********************************************************************** 326 * Name: _info * 327 * * 328 * Description: * 329 * Returns information about a loadable module. * 330 * This is mandotary function for the driver * 331 * Parameter Passed: * 332 * module info structure * 333 * Return Value: * 334 * 0 on success * 335 * Functions called * 336 * mod_info() (system call) * 337 * * 338 * * 339 * ********************************************************************** 340 */ 341 int 342 _info(struct modinfo *modinfop) 343 { 344 return (mod_info(&modlinkage, modinfop)); 345 } 346 347 /* 348 * Interface exists: make available by filling in network interface 349 * record. System will initialize the interface when it is ready 350 * to accept packets. 351 */ 352 353 /* 354 * ********************************************************************** 355 * Name: e1000gattach * 356 * * 357 * Description: * 358 * This function is the device-specific initialization * 359 * entry point. This entry point is required and must be writ- * 360 * ten. The DDI_ATTACH command must be provided in the attach * 361 * entry point. When attach() is called with cmd set to DDI_ATTACH, * 362 * all normal kernel services (such as kmem_alloc(9F)) are * 363 * available for use by the driver. Device interrupts are not * 364 * blocked when attaching a device to the system. * 365 * * 366 * The attach() function will be called once for each instance * 367 * of the device on the system with cmd set to DDI_ATTACH. * 368 * Until attach() succeeds, the only driver entry points which * 369 * may be called are open(9E) and getinfo(9E). * 370 * * 371 * * 372 * * 373 * Parameter Passed: * 374 * * 375 * Return Value: * 376 * * 377 * Functions called * 378 * * 379 * * 380 * ********************************************************************** 381 */ 382 static int 383 e1000gattach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 384 { 385 struct e1000g *Adapter; 386 struct e1000_hw *hw; 387 ddi_acc_handle_t handle; 388 off_t mem_size; 389 int instance; 390 391 switch (cmd) { 392 default: 393 e1000g_log(NULL, CE_WARN, 394 "Unsupported command send to e1000gattach... "); 395 return (DDI_FAILURE); 396 397 case DDI_RESUME: 398 return (e1000g_resume(devinfo)); 399 400 case DDI_ATTACH: 401 break; 402 } 403 404 /* 405 * get device instance number 406 */ 407 instance = ddi_get_instance(devinfo); 408 409 /* 410 * Allocate soft data structure 411 */ 412 Adapter = 413 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 414 415 Adapter->dip = devinfo; 416 Adapter->AdapterInstance = instance; 417 Adapter->tx_ring->adapter = Adapter; 418 Adapter->rx_ring->adapter = Adapter; 419 420 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 421 422 hw = &Adapter->Shared; 423 424 /* 425 * Map in the device registers. 426 * 427 * first get the size of device register to be mapped. The 428 * second parameter is the register we are interested. I our 429 * wiseman 0 is for config registers and 1 is for memory mapped 430 * registers Mem size should have memory mapped region size 431 */ 432 ddi_dev_regsize(devinfo, 1, /* register of interest */ 433 (off_t *)&mem_size); 434 435 if ((ddi_regs_map_setup(devinfo, 1, /* register of interest */ 436 (caddr_t *)&hw->hw_addr, 437 0, mem_size, &accattr1, &Adapter->E1000_handle)) 438 != DDI_SUCCESS) { 439 e1000g_log(Adapter, CE_WARN, "ddi_regs_map_setup failed"); 440 goto attach_fail; 441 } 442 Adapter->attach_progress |= ATTACH_PROGRESS_REGSMAPPED; 443 444 Adapter->osdep.E1000_handle = Adapter->E1000_handle; 445 hw->back = &Adapter->osdep; 446 447 /* 448 * PCI Configure 449 */ 450 if (pci_config_setup(devinfo, &handle) != DDI_SUCCESS) { 451 e1000g_log(Adapter, CE_WARN, 452 "PCI configuration could not be read."); 453 goto attach_fail; 454 } 455 456 Adapter->handle = handle; 457 Adapter->osdep.handle = handle; 458 459 hw->vendor_id = 460 pci_config_get16(handle, PCI_CONF_VENID); 461 hw->device_id = 462 pci_config_get16(handle, PCI_CONF_DEVID); 463 hw->revision_id = 464 pci_config_get8(handle, PCI_CONF_REVID); 465 hw->subsystem_id = 466 pci_config_get16(handle, PCI_CONF_SUBSYSID); 467 hw->subsystem_vendor_id = 468 pci_config_get16(handle, PCI_CONF_SUBVENID); 469 470 Adapter->attach_progress |= ATTACH_PROGRESS_PCICONFIG; 471 472 /* 473 * Initialize driver parameters 474 */ 475 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 476 goto attach_fail; 477 } 478 Adapter->attach_progress |= ATTACH_PROGRESS_PROP; 479 480 /* 481 * Initialize interrupts 482 */ 483 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 484 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 485 goto attach_fail; 486 } 487 Adapter->tx_softint_pri = DDI_INTR_SOFTPRI_MAX; 488 Adapter->attach_progress |= ATTACH_PROGRESS_INTRADDED; 489 490 /* 491 * Initialize mutex's for this device. 492 * Do this before enabling the interrupt handler and 493 * register the softint to avoid the condition where 494 * interrupt handler can try using uninitialized mutex 495 */ 496 e1000g_init_locks(Adapter); 497 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 498 499 if (ddi_intr_add_softint(devinfo, 500 &Adapter->tx_softint_handle, Adapter->tx_softint_pri, 501 e1000g_tx_freemsg, (caddr_t)Adapter) != DDI_SUCCESS) { 502 e1000g_log(Adapter, CE_WARN, "Add soft intr failed"); 503 goto attach_fail; 504 } 505 Adapter->attach_progress |= ATTACH_PROGRESS_SOFTINTR; 506 507 /* 508 * Initialize Driver Counters 509 */ 510 if (InitStatsCounters(Adapter) != DDI_SUCCESS) { 511 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 512 goto attach_fail; 513 } 514 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 515 516 /* 517 * Allocate dma resources for descriptors and buffers 518 */ 519 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 520 e1000g_log(Adapter, CE_WARN, "Alloc dma resources failed"); 521 goto attach_fail; 522 } 523 Adapter->attach_progress |= ATTACH_PROGRESS_ALLOC; 524 525 /* 526 * Initialize chip hardware and software structures 527 */ 528 if (e1000g_init(Adapter) != DDI_SUCCESS) { 529 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 530 goto attach_fail; 531 } 532 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 533 534 /* 535 * Initialize NDD parameters 536 */ 537 if (e1000g_nd_init(Adapter) != DDI_SUCCESS) { 538 e1000g_log(Adapter, CE_WARN, "Init NDD failed"); 539 goto attach_fail; 540 } 541 Adapter->attach_progress |= ATTACH_PROGRESS_NDD; 542 543 /* 544 * Register the driver to the MAC 545 */ 546 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 547 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 548 goto attach_fail; 549 } 550 Adapter->attach_progress |= ATTACH_PROGRESS_MACREGISTERED; 551 552 /* 553 * Now that mutex locks are initialized, and the chip is also 554 * initialized, enable interrupts. 555 */ 556 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 557 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 558 goto attach_fail; 559 } 560 Adapter->attach_progress |= ATTACH_PROGRESS_INTRENABLED; 561 562 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 563 564 return (DDI_SUCCESS); 565 566 attach_fail: 567 e1000g_unattach(devinfo, Adapter); 568 return (DDI_FAILURE); 569 } 570 571 static int 572 e1000g_register_mac(struct e1000g *Adapter) 573 { 574 struct e1000_hw *hw = &Adapter->Shared; 575 mac_register_t *mac; 576 int err; 577 578 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 579 return (DDI_FAILURE); 580 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 581 mac->m_driver = Adapter; 582 mac->m_dip = Adapter->dip; 583 mac->m_src_addr = hw->mac_addr; 584 mac->m_callbacks = &e1000g_m_callbacks; 585 mac->m_min_sdu = 0; 586 mac->m_max_sdu = 587 (hw->max_frame_size > FRAME_SIZE_UPTO_8K) ? 588 hw->max_frame_size - 256 : 589 (hw->max_frame_size != ETHERMAX) ? 590 hw->max_frame_size - 24 : ETHERMTU; 591 err = mac_register(mac, &Adapter->mh); 592 mac_free(mac); 593 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 594 } 595 596 static int 597 e1000g_set_driver_params(struct e1000g *Adapter) 598 { 599 dev_info_t *devinfo; 600 ddi_acc_handle_t handle; 601 struct e1000_hw *hw; 602 uint32_t mem_bar, io_bar; 603 #ifdef __sparc 604 ulong_t iommu_pagesize; 605 #endif 606 607 devinfo = Adapter->dip; 608 handle = Adapter->handle; 609 hw = &Adapter->Shared; 610 611 /* Set Mac Type */ 612 if (e1000_set_mac_type(hw) != 0) { 613 e1000g_log(Adapter, CE_WARN, 614 "Could not identify hardware"); 615 return (DDI_FAILURE); 616 } 617 618 /* ich8 needs to map flash memory */ 619 if (hw->mac_type == e1000_ich8lan) { 620 /* get flash size */ 621 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 622 &Adapter->osdep.ich_flash_size) != DDI_SUCCESS) { 623 e1000g_log(Adapter, CE_WARN, 624 "ddi_dev_regsize for ich8 flash failed"); 625 return (DDI_FAILURE); 626 } 627 628 /* map flash in */ 629 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 630 &Adapter->osdep.ich_flash_base, 0, 631 Adapter->osdep.ich_flash_size, 632 &accattr1, 633 &Adapter->osdep.ich_flash_handle) != DDI_SUCCESS) { 634 e1000g_log(Adapter, CE_WARN, 635 "ddi_regs_map_setup for for ich8 flash failed"); 636 return (DDI_FAILURE); 637 } 638 } 639 640 /* get mem_base addr */ 641 mem_bar = pci_config_get32(handle, PCI_CONF_BASE0); 642 Adapter->bar64 = mem_bar & PCI_BASE_TYPE_ALL; 643 644 /* get io_base addr */ 645 if (hw->mac_type >= e1000_82544) { 646 if (Adapter->bar64) { 647 /* IO BAR is different for 64 bit BAR mode */ 648 io_bar = pci_config_get32(handle, PCI_CONF_BASE4); 649 } else { 650 /* normal 32-bit BAR mode */ 651 io_bar = pci_config_get32(handle, PCI_CONF_BASE2); 652 } 653 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 654 } else { 655 /* no I/O access for adapters prior to 82544 */ 656 hw->io_base = 0x0; 657 } 658 659 e1000_read_pci_cfg(hw, 660 PCI_COMMAND_REGISTER, &(hw->pci_cmd_word)); 661 662 /* Set the wait_autoneg_complete flag to B_FALSE */ 663 hw->wait_autoneg_complete = B_FALSE; 664 665 /* Adaptive IFS related changes */ 666 hw->adaptive_ifs = B_TRUE; 667 668 /* set phy init script revision */ 669 if ((hw->mac_type == e1000_82547) || 670 (hw->mac_type == e1000_82541) || 671 (hw->mac_type == e1000_82547_rev_2) || 672 (hw->mac_type == e1000_82541_rev_2)) 673 hw->phy_init_script = 1; 674 675 /* Enable the TTL workaround for TnT: DCR 49 */ 676 hw->ttl_wa_activation = 1; 677 678 if (hw->mac_type == e1000_82571) 679 hw->laa_is_present = B_TRUE; 680 681 /* Get conf file properties */ 682 e1000g_getparam(Adapter); 683 684 hw->forced_speed_duplex = e1000_100_full; 685 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 686 e1000g_force_speed_duplex(Adapter); 687 688 e1000g_get_max_frame_size(Adapter); 689 hw->min_frame_size = 690 MINIMUM_ETHERNET_PACKET_SIZE + CRC_LENGTH; 691 692 #ifdef __sparc 693 /* Get the system page size */ 694 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 695 iommu_pagesize = dvma_pagesize(devinfo); 696 if (iommu_pagesize != 0) { 697 if (Adapter->sys_page_sz == iommu_pagesize) { 698 if (iommu_pagesize > 0x4000) 699 Adapter->sys_page_sz = 0x4000; 700 } else { 701 if (Adapter->sys_page_sz > iommu_pagesize) 702 Adapter->sys_page_sz = iommu_pagesize; 703 } 704 } 705 Adapter->dvma_page_num = hw->max_frame_size / 706 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 707 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 708 #endif 709 710 /* Set Rx/Tx buffer size */ 711 switch (hw->max_frame_size) { 712 case ETHERMAX: 713 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_2K; 714 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_2K; 715 break; 716 case FRAME_SIZE_UPTO_4K: 717 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_4K; 718 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_4K; 719 break; 720 case FRAME_SIZE_UPTO_8K: 721 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_8K; 722 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_8K; 723 break; 724 case FRAME_SIZE_UPTO_10K: 725 case FRAME_SIZE_UPTO_16K: 726 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_16K; 727 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_16K; 728 break; 729 default: 730 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_2K; 731 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_2K; 732 break; 733 } 734 Adapter->RxBufferSize += E1000G_IPALIGNPRESERVEROOM; 735 736 /* 737 * For Wiseman adapters we have an requirement of having receive 738 * buffers aligned at 256 byte boundary. Since Livengood does not 739 * require this and forcing it for all hardwares will have 740 * performance implications, I am making it applicable only for 741 * Wiseman and for Jumbo frames enabled mode as rest of the time, 742 * it is okay to have normal frames...but it does involve a 743 * potential risk where we may loose data if buffer is not 744 * aligned...so all wiseman boards to have 256 byte aligned 745 * buffers 746 */ 747 if (hw->mac_type < e1000_82543) 748 Adapter->RcvBufferAlignment = RECEIVE_BUFFER_ALIGN_SIZE; 749 else 750 /* 751 * For livengood, there is no such Rcv buf alignment 752 * requirement 753 */ 754 Adapter->RcvBufferAlignment = 1; 755 756 /* DmaFairness */ 757 if (hw->mac_type <= e1000_82543) 758 hw->dma_fairness = DEFAULTRXPCIPRIORITYVAL; 759 else 760 hw->dma_fairness = 0; 761 762 /* MasterLatencyTimer */ 763 Adapter->MasterLatencyTimer = DEFAULTMASTERLATENCYTIMERVAL; 764 765 /* MWIEnable */ 766 Adapter->MWIEnable = DEFAULTMWIENABLEVAL; 767 768 /* profile jumbo traffic */ 769 Adapter->ProfileJumboTraffic = DEFAULTPROFILEJUMBOTRAFFIC; 770 771 e1000_set_media_type(hw); 772 /* copper options */ 773 if (hw->media_type == e1000_media_type_copper) { 774 hw->mdix = 0; /* AUTO_ALL_MODES */ 775 hw->disable_polarity_correction = B_FALSE; 776 hw->master_slave = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 777 } 778 779 Adapter->link_state = LINK_STATE_UNKNOWN; 780 781 return (DDI_SUCCESS); 782 } 783 784 /* 785 * ********************************************************************** 786 * Name: e1000gdettach * 787 * * 788 * Description: * 789 * The detach() function is the complement of the attach routine. * 790 * If cmd is set to DDI_DETACH, detach() is used to remove the * 791 * state associated with a given instance of a device node * 792 * prior to the removal of that instance from the system. * 793 * * 794 * The detach() function will be called once for each instance * 795 * of the device for which there has been a successful attach() * 796 * once there are no longer any opens on the device. * 797 * * 798 * Interrupts routine are disabled, All memory allocated by this * 799 * driver are freed. * 800 * * 801 * Parameter Passed: * 802 * devinfo structure, cmd * 803 * * 804 * Return Value: * 805 * DDI_SUCCESS on success * 806 * * 807 * Functions called * 808 * * 809 * * 810 * ********************************************************************** 811 */ 812 static int 813 e1000gdetach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 814 { 815 struct e1000g *Adapter; 816 817 switch (cmd) { 818 default: 819 return (DDI_FAILURE); 820 821 case DDI_SUSPEND: 822 return (e1000g_suspend(devinfo)); 823 824 case DDI_DETACH: 825 break; 826 } 827 828 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 829 if (Adapter == NULL) 830 return (DDI_FAILURE); 831 832 if (Adapter->started) 833 e1000g_stop(Adapter); 834 835 if (!e1000g_rx_drain(Adapter)) { 836 if (!force_detach_enabled) 837 return (DDI_FAILURE); 838 } 839 840 if (e1000g_disable_intrs(Adapter) != DDI_SUCCESS) { 841 e1000g_log(Adapter, CE_WARN, 842 "Disable DDI interrupts failed"); 843 return (DDI_FAILURE); 844 } 845 Adapter->attach_progress &= ~ATTACH_PROGRESS_INTRENABLED; 846 847 if (mac_unregister(Adapter->mh) != 0) { 848 e1000g_log(Adapter, CE_WARN, 849 "Unregister MAC failed"); 850 return (DDI_FAILURE); 851 } 852 Adapter->attach_progress &= ~ATTACH_PROGRESS_MACREGISTERED; 853 854 e1000g_unattach(devinfo, Adapter); 855 856 return (DDI_SUCCESS); 857 } 858 859 static void 860 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 861 { 862 if (Adapter->attach_progress & ATTACH_PROGRESS_INTRENABLED) { 863 (void) e1000g_disable_intrs(Adapter); 864 } 865 866 if (Adapter->attach_progress & ATTACH_PROGRESS_MACREGISTERED) { 867 (void) mac_unregister(Adapter->mh); 868 } 869 870 if (Adapter->attach_progress & ATTACH_PROGRESS_NDD) { 871 e1000g_nd_cleanup(Adapter); 872 } 873 874 if (Adapter->attach_progress & ATTACH_PROGRESS_INTRADDED) { 875 (void) e1000g_rem_intrs(Adapter); 876 } 877 878 if (Adapter->attach_progress & ATTACH_PROGRESS_SOFTINTR) { 879 (void) ddi_intr_remove_softint(Adapter->tx_softint_handle); 880 } 881 882 if (Adapter->attach_progress & ATTACH_PROGRESS_PROP) { 883 (void) ddi_prop_remove_all(devinfo); 884 } 885 886 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 887 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 888 } 889 890 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 891 timeout_id_t tid = 0; 892 893 /* Disable the link timer */ 894 mutex_enter(&Adapter->e1000g_linklock); 895 tid = Adapter->link_tid; 896 Adapter->link_tid = 0; 897 mutex_exit(&Adapter->e1000g_linklock); 898 899 if (tid != 0) 900 (void) untimeout(tid); 901 902 e1000_reset_hw(&Adapter->Shared); 903 } 904 905 if (Adapter->attach_progress & ATTACH_PROGRESS_REGSMAPPED) { 906 ddi_regs_map_free(&Adapter->E1000_handle); 907 } 908 909 if (Adapter->attach_progress & ATTACH_PROGRESS_PCICONFIG) { 910 pci_config_teardown(&Adapter->handle); 911 } 912 913 if (Adapter->attach_progress & ATTACH_PROGRESS_ALLOC) { 914 e1000g_release_dma_resources(Adapter); 915 } 916 917 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 918 e1000g_destroy_locks(Adapter); 919 } 920 921 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 922 923 /* 924 * Another hotplug spec requirement, 925 * run ddi_set_driver_private(devinfo, null); 926 */ 927 ddi_set_driver_private(devinfo, NULL); 928 } 929 930 static void 931 e1000g_init_locks(struct e1000g *Adapter) 932 { 933 e1000g_tx_ring_t *tx_ring; 934 e1000g_rx_ring_t *rx_ring; 935 936 rw_init(&Adapter->chip_lock, NULL, 937 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 938 mutex_init(&Adapter->e1000g_linklock, NULL, 939 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 940 mutex_init(&Adapter->e1000g_timeout_lock, NULL, 941 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 942 mutex_init(&Adapter->TbiCntrMutex, NULL, 943 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 944 945 mutex_init(&Adapter->tx_msg_chain->lock, NULL, 946 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->tx_softint_pri)); 947 948 tx_ring = Adapter->tx_ring; 949 950 mutex_init(&tx_ring->tx_lock, NULL, 951 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 952 mutex_init(&tx_ring->usedlist_lock, NULL, 953 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 954 mutex_init(&tx_ring->freelist_lock, NULL, 955 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 956 957 rx_ring = Adapter->rx_ring; 958 959 mutex_init(&rx_ring->rx_lock, NULL, 960 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 961 mutex_init(&rx_ring->freelist_lock, NULL, 962 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 963 } 964 965 static void 966 e1000g_destroy_locks(struct e1000g *Adapter) 967 { 968 e1000g_tx_ring_t *tx_ring; 969 e1000g_rx_ring_t *rx_ring; 970 971 tx_ring = Adapter->tx_ring; 972 mutex_destroy(&tx_ring->tx_lock); 973 mutex_destroy(&tx_ring->usedlist_lock); 974 mutex_destroy(&tx_ring->freelist_lock); 975 976 rx_ring = Adapter->rx_ring; 977 mutex_destroy(&rx_ring->rx_lock); 978 mutex_destroy(&rx_ring->freelist_lock); 979 980 mutex_destroy(&Adapter->tx_msg_chain->lock); 981 mutex_destroy(&Adapter->e1000g_linklock); 982 mutex_destroy(&Adapter->TbiCntrMutex); 983 mutex_destroy(&Adapter->e1000g_timeout_lock); 984 rw_destroy(&Adapter->chip_lock); 985 } 986 987 static int 988 e1000g_resume(dev_info_t *devinfo) 989 { 990 struct e1000g *Adapter; 991 992 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 993 if (Adapter == NULL) 994 return (DDI_FAILURE); 995 996 if (e1000g_start(Adapter)) 997 return (DDI_FAILURE); 998 999 return (DDI_SUCCESS); 1000 } 1001 1002 static int 1003 e1000g_suspend(dev_info_t *devinfo) 1004 { 1005 struct e1000g *Adapter; 1006 1007 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1008 if (Adapter == NULL) 1009 return (DDI_FAILURE); 1010 1011 e1000g_stop(Adapter); 1012 1013 return (DDI_SUCCESS); 1014 } 1015 1016 static int 1017 e1000g_init(struct e1000g *Adapter) 1018 { 1019 uint32_t pba; 1020 uint32_t ctrl; 1021 struct e1000_hw *hw; 1022 clock_t link_timeout; 1023 1024 hw = &Adapter->Shared; 1025 1026 rw_enter(&Adapter->chip_lock, RW_WRITER); 1027 1028 /* Preserve manageability features */ 1029 e1000_check_phy_reset_block(hw); 1030 1031 /* 1032 * reset to put the hardware in a known state 1033 * before we try to do anything with the eeprom 1034 */ 1035 (void) e1000_reset_hw(hw); 1036 1037 (void) e1000_init_eeprom_params(hw); 1038 1039 if (e1000_validate_eeprom_checksum(hw) < 0) { 1040 /* 1041 * Some PCI-E parts fail the first check due to 1042 * the link being in sleep state. Call it again, 1043 * if it fails a second time its a real issue. 1044 */ 1045 if (e1000_validate_eeprom_checksum(hw) < 0) { 1046 e1000g_log(Adapter, CE_WARN, 1047 "Invalid EEPROM checksum. Please contact " 1048 "the vendor to update the EEPROM."); 1049 goto init_fail; 1050 } 1051 } 1052 1053 #ifdef __sparc 1054 /* 1055 * Firstly, we try to get the local ethernet address from OBP. If 1056 * fail, we get from EEPROM of NIC card. 1057 */ 1058 if (!e1000g_find_mac_address(Adapter)) { 1059 if (e1000_read_mac_addr(hw) < 0) { 1060 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1061 goto init_fail; 1062 } 1063 } 1064 #else 1065 /* Get the local ethernet address. */ 1066 if (e1000_read_mac_addr(hw) < 0) { 1067 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1068 goto init_fail; 1069 } 1070 #endif 1071 1072 /* check for valid mac address */ 1073 if (!is_valid_mac_addr(hw->mac_addr)) { 1074 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1075 goto init_fail; 1076 } 1077 1078 e1000_get_bus_info(hw); 1079 1080 /* Master Latency Timer implementation */ 1081 if (Adapter->MasterLatencyTimer) { 1082 pci_config_put8(Adapter->handle, PCI_CONF_LATENCY_TIMER, 1083 Adapter->MasterLatencyTimer); 1084 } 1085 1086 if (hw->mac_type < e1000_82547) { 1087 /* 1088 * Total FIFO is 64K 1089 */ 1090 if (hw->max_frame_size > FRAME_SIZE_UPTO_8K) 1091 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1092 else 1093 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1094 } else if (hw->mac_type >= e1000_82571 && 1095 hw->mac_type <= e1000_82572) { 1096 /* 1097 * Total FIFO is 48K 1098 */ 1099 if (hw->max_frame_size > FRAME_SIZE_UPTO_8K) 1100 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1101 else 1102 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1103 } else if (hw->mac_type == e1000_ich8lan) { 1104 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1105 } else { 1106 /* 1107 * Total FIFO is 40K 1108 */ 1109 if (hw->max_frame_size > FRAME_SIZE_UPTO_8K) 1110 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1111 else 1112 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1113 } 1114 E1000_WRITE_REG(hw, PBA, pba); 1115 1116 /* 1117 * These parameters set thresholds for the adapter's generation(Tx) 1118 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1119 * settings. Flow control is enabled or disabled in the configuration 1120 * file. 1121 * High-water mark is set down from the top of the rx fifo (not 1122 * sensitive to max_frame_size) and low-water is set just below 1123 * high-water mark. 1124 */ 1125 hw->fc_high_water = 1126 ((pba & E1000_PBA_MASK) << E1000_PBA_SHIFT) - 1127 E1000_FC_HIGH_DIFF; 1128 hw->fc_low_water = 1129 ((pba & E1000_PBA_MASK) << E1000_PBA_SHIFT) - 1130 E1000_FC_LOW_DIFF; 1131 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 1132 hw->fc_send_xon = B_TRUE; 1133 1134 /* 1135 * Reset the adapter hardware the second time. 1136 */ 1137 (void) e1000_reset_hw(hw); 1138 1139 /* disable wakeup control by default */ 1140 if (hw->mac_type >= e1000_82544) 1141 E1000_WRITE_REG(hw, WUC, 0); 1142 1143 /* MWI setup */ 1144 if (Adapter->MWIEnable) { 1145 hw->pci_cmd_word |= CMD_MEM_WRT_INVALIDATE; 1146 e1000_pci_set_mwi(hw); 1147 } else 1148 e1000_pci_clear_mwi(hw); 1149 1150 /* 1151 * Configure/Initialize hardware 1152 */ 1153 if (e1000_init_hw(hw) < 0) { 1154 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1155 goto init_fail; 1156 } 1157 1158 /* Disable Smart Power Down */ 1159 phy_spd_state(hw, B_FALSE); 1160 1161 /* 1162 * Initialize unicast addresses. 1163 */ 1164 e1000g_init_unicst(Adapter); 1165 1166 /* 1167 * Setup and initialize the transmit structures. 1168 */ 1169 SetupTransmitStructures(Adapter); 1170 DelayInMilliseconds(5); 1171 1172 /* 1173 * Setup and initialize the mctable structures. After this routine 1174 * completes Multicast table will be set 1175 */ 1176 SetupMulticastTable(Adapter); 1177 DelayInMilliseconds(5); 1178 1179 /* 1180 * Setup and initialize the receive structures. After this routine 1181 * completes we can receive packets off of the wire. 1182 */ 1183 SetupReceiveStructures(Adapter); 1184 DelayInMilliseconds(5); 1185 1186 /* 1187 * Implement Adaptive IFS 1188 */ 1189 e1000_reset_adaptive(hw); 1190 1191 /* Setup Interrupt Throttling Register */ 1192 E1000_WRITE_REG(hw, ITR, Adapter->intr_throttling_rate); 1193 1194 /* Start the timer for link setup */ 1195 if (hw->autoneg) 1196 link_timeout = PHY_AUTO_NEG_TIME * drv_usectohz(100000); 1197 else 1198 link_timeout = PHY_FORCE_TIME * drv_usectohz(100000); 1199 1200 mutex_enter(&Adapter->e1000g_linklock); 1201 if (hw->wait_autoneg_complete) { 1202 Adapter->link_complete = B_TRUE; 1203 } else { 1204 Adapter->link_complete = B_FALSE; 1205 Adapter->link_tid = timeout(e1000g_link_timer, 1206 (void *)Adapter, link_timeout); 1207 } 1208 mutex_exit(&Adapter->e1000g_linklock); 1209 1210 /* Enable PCI-Ex master */ 1211 if (hw->bus_type == e1000_bus_type_pci_express) { 1212 e1000_enable_pciex_master(hw); 1213 } 1214 1215 Adapter->init_count++; 1216 1217 rw_exit(&Adapter->chip_lock); 1218 1219 return (DDI_SUCCESS); 1220 1221 init_fail: 1222 rw_exit(&Adapter->chip_lock); 1223 return (DDI_FAILURE); 1224 } 1225 1226 /* 1227 * Check if the link is up 1228 */ 1229 static boolean_t 1230 e1000g_link_up(struct e1000g *Adapter) 1231 { 1232 struct e1000_hw *hw; 1233 boolean_t link_up; 1234 1235 hw = &Adapter->Shared; 1236 1237 /* Ensure this is set to get accurate copper link status */ 1238 hw->get_link_status = B_TRUE; 1239 1240 e1000_check_for_link(hw); 1241 1242 if ((E1000_READ_REG(hw, STATUS) & E1000_STATUS_LU) || 1243 ((!hw->get_link_status) && (hw->mac_type == e1000_82543)) || 1244 ((hw->media_type == e1000_media_type_internal_serdes) && 1245 (!hw->serdes_link_down))) { 1246 link_up = B_TRUE; 1247 } else { 1248 link_up = B_FALSE; 1249 } 1250 1251 return (link_up); 1252 } 1253 1254 static void 1255 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1256 { 1257 struct iocblk *iocp; 1258 struct e1000g *e1000gp; 1259 enum ioc_reply status; 1260 int err; 1261 1262 iocp = (struct iocblk *)mp->b_rptr; 1263 iocp->ioc_error = 0; 1264 e1000gp = (struct e1000g *)arg; 1265 1266 ASSERT(e1000gp); 1267 if (e1000gp == NULL) { 1268 miocnak(q, mp, 0, EINVAL); 1269 return; 1270 } 1271 1272 switch (iocp->ioc_cmd) { 1273 1274 case LB_GET_INFO_SIZE: 1275 case LB_GET_INFO: 1276 case LB_GET_MODE: 1277 case LB_SET_MODE: 1278 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1279 break; 1280 1281 case ND_GET: 1282 case ND_SET: 1283 status = e1000g_nd_ioctl(e1000gp, q, mp, iocp); 1284 break; 1285 1286 case E1000G_IOC_REG_PEEK: 1287 case E1000G_IOC_REG_POKE: 1288 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1289 break; 1290 case E1000G_IOC_CHIP_RESET: 1291 e1000gp->reset_count++; 1292 if (e1000g_reset(e1000gp)) 1293 status = IOC_ACK; 1294 else 1295 status = IOC_INVAL; 1296 break; 1297 default: 1298 status = IOC_INVAL; 1299 break; 1300 } 1301 1302 /* 1303 * Decide how to reply 1304 */ 1305 switch (status) { 1306 default: 1307 case IOC_INVAL: 1308 /* 1309 * Error, reply with a NAK and EINVAL or the specified error 1310 */ 1311 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1312 EINVAL : iocp->ioc_error); 1313 break; 1314 1315 case IOC_DONE: 1316 /* 1317 * OK, reply already sent 1318 */ 1319 break; 1320 1321 case IOC_ACK: 1322 /* 1323 * OK, reply with an ACK 1324 */ 1325 miocack(q, mp, 0, 0); 1326 break; 1327 1328 case IOC_REPLY: 1329 /* 1330 * OK, send prepared reply as ACK or NAK 1331 */ 1332 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1333 M_IOCACK : M_IOCNAK; 1334 qreply(q, mp); 1335 break; 1336 } 1337 } 1338 1339 static void e1000g_m_blank(void *arg, time_t ticks, uint32_t count) 1340 { 1341 struct e1000g *Adapter; 1342 1343 Adapter = (struct e1000g *)arg; 1344 1345 /* 1346 * Adjust ITR (Interrupt Throttling Register) to coalesce 1347 * interrupts. This formula and its coefficient come from 1348 * our experiments. 1349 */ 1350 if (Adapter->intr_adaptive) { 1351 Adapter->intr_throttling_rate = count << 5; 1352 E1000_WRITE_REG(&Adapter->Shared, ITR, 1353 Adapter->intr_throttling_rate); 1354 } 1355 } 1356 1357 static void 1358 e1000g_m_resources(void *arg) 1359 { 1360 struct e1000g *adapter = (struct e1000g *)arg; 1361 mac_rx_fifo_t mrf; 1362 1363 mrf.mrf_type = MAC_RX_FIFO; 1364 mrf.mrf_blank = e1000g_m_blank; 1365 mrf.mrf_arg = (void *)adapter; 1366 mrf.mrf_normal_blank_time = E1000_RX_INTPT_TIME; 1367 mrf.mrf_normal_pkt_count = E1000_RX_PKT_CNT; 1368 1369 adapter->mrh = mac_resource_add(adapter->mh, (mac_resource_t *)&mrf); 1370 } 1371 1372 static int 1373 e1000g_m_start(void *arg) 1374 { 1375 struct e1000g *Adapter = (struct e1000g *)arg; 1376 1377 return (e1000g_start(Adapter)); 1378 } 1379 1380 static int 1381 e1000g_start(struct e1000g *Adapter) 1382 { 1383 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1384 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1385 e1000g_log(Adapter, CE_WARN, 1386 "Adapter initialization failed"); 1387 return (ENOTACTIVE); 1388 } 1389 } 1390 1391 enable_timeout(Adapter); 1392 1393 rw_enter(&Adapter->chip_lock, RW_WRITER); 1394 1395 e1000g_EnableInterrupt(Adapter); 1396 if (Adapter->tx_intr_enable) 1397 e1000g_EnableTxInterrupt(Adapter); 1398 1399 Adapter->started = B_TRUE; 1400 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1401 1402 rw_exit(&Adapter->chip_lock); 1403 1404 return (0); 1405 } 1406 1407 static void 1408 e1000g_m_stop(void *arg) 1409 { 1410 struct e1000g *Adapter = (struct e1000g *)arg; 1411 1412 e1000g_stop(Adapter); 1413 } 1414 1415 static void 1416 e1000g_stop(struct e1000g *Adapter) 1417 { 1418 timeout_id_t tid; 1419 e1000g_tx_ring_t *tx_ring; 1420 boolean_t link_changed; 1421 1422 tx_ring = Adapter->tx_ring; 1423 1424 /* Set stop flags */ 1425 rw_enter(&Adapter->chip_lock, RW_WRITER); 1426 1427 Adapter->started = B_FALSE; 1428 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1429 1430 rw_exit(&Adapter->chip_lock); 1431 1432 /* Drain tx sessions */ 1433 (void) e1000g_tx_drain(Adapter); 1434 1435 /* Disable timers */ 1436 disable_timeout(Adapter); 1437 1438 /* Disable the tx timer for 82547 chipset */ 1439 mutex_enter(&tx_ring->tx_lock); 1440 tx_ring->timer_enable_82547 = B_FALSE; 1441 tid = tx_ring->timer_id_82547; 1442 tx_ring->timer_id_82547 = 0; 1443 mutex_exit(&tx_ring->tx_lock); 1444 1445 if (tid != 0) 1446 (void) untimeout(tid); 1447 1448 /* Disable the link timer */ 1449 mutex_enter(&Adapter->e1000g_linklock); 1450 tid = Adapter->link_tid; 1451 Adapter->link_tid = 0; 1452 mutex_exit(&Adapter->e1000g_linklock); 1453 1454 if (tid != 0) 1455 (void) untimeout(tid); 1456 1457 /* Stop the chip and release pending resources */ 1458 rw_enter(&Adapter->chip_lock, RW_WRITER); 1459 1460 e1000g_DisableAllInterrupts(Adapter); 1461 1462 e1000_reset_hw(&Adapter->Shared); 1463 1464 /* Release resources still held by the TX descriptors */ 1465 e1000g_tx_drop(Adapter); 1466 1467 /* Clean the pending rx jumbo packet fragment */ 1468 if (Adapter->rx_mblk != NULL) { 1469 freemsg(Adapter->rx_mblk); 1470 Adapter->rx_mblk = NULL; 1471 Adapter->rx_mblk_tail = NULL; 1472 Adapter->rx_packet_len = 0; 1473 } 1474 1475 rw_exit(&Adapter->chip_lock); 1476 } 1477 1478 static void 1479 e1000g_tx_drop(struct e1000g *Adapter) 1480 { 1481 e1000g_tx_ring_t *tx_ring; 1482 e1000g_msg_chain_t *msg_chain; 1483 PTX_SW_PACKET packet; 1484 mblk_t *mp; 1485 mblk_t *nmp; 1486 uint32_t packet_count; 1487 1488 tx_ring = Adapter->tx_ring; 1489 1490 /* 1491 * Here we don't need to protect the lists using 1492 * the usedlist_lock and freelist_lock, for they 1493 * have been protected by the chip_lock. 1494 */ 1495 mp = NULL; 1496 nmp = NULL; 1497 packet_count = 0; 1498 packet = (PTX_SW_PACKET) QUEUE_GET_HEAD(&tx_ring->used_list); 1499 while (packet != NULL) { 1500 if (packet->mp != NULL) { 1501 /* Assemble the message chain */ 1502 if (mp == NULL) { 1503 mp = packet->mp; 1504 nmp = packet->mp; 1505 } else { 1506 nmp->b_next = packet->mp; 1507 nmp = packet->mp; 1508 } 1509 /* Disconnect the message from the sw packet */ 1510 packet->mp = NULL; 1511 } 1512 1513 FreeTxSwPacket(packet); 1514 packet_count++; 1515 1516 packet = (PTX_SW_PACKET) 1517 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1518 } 1519 1520 if (mp != NULL) { 1521 msg_chain = Adapter->tx_msg_chain; 1522 mutex_enter(&msg_chain->lock); 1523 if (msg_chain->head == NULL) { 1524 msg_chain->head = mp; 1525 msg_chain->tail = nmp; 1526 } else { 1527 msg_chain->tail->b_next = mp; 1528 msg_chain->tail = nmp; 1529 } 1530 mutex_exit(&msg_chain->lock); 1531 } 1532 1533 ddi_intr_trigger_softint(Adapter->tx_softint_handle, NULL); 1534 1535 if (packet_count > 0) { 1536 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1537 QUEUE_INIT_LIST(&tx_ring->used_list); 1538 1539 /* Setup TX descriptor pointers */ 1540 tx_ring->tbd_next = tx_ring->tbd_first; 1541 tx_ring->tbd_oldest = tx_ring->tbd_first; 1542 1543 /* Setup our HW Tx Head & Tail descriptor pointers */ 1544 E1000_WRITE_REG(&Adapter->Shared, TDH, 0); 1545 E1000_WRITE_REG(&Adapter->Shared, TDT, 0); 1546 } 1547 } 1548 1549 static boolean_t 1550 e1000g_tx_drain(struct e1000g *Adapter) 1551 { 1552 int i; 1553 boolean_t done; 1554 e1000g_tx_ring_t *tx_ring; 1555 1556 tx_ring = Adapter->tx_ring; 1557 1558 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1559 for (i = 0; i < WSDRAINTIME; i++) { 1560 mutex_enter(&tx_ring->usedlist_lock); 1561 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1562 mutex_exit(&tx_ring->usedlist_lock); 1563 1564 if (done) 1565 break; 1566 1567 msec_delay(1); 1568 } 1569 1570 return (done); 1571 } 1572 1573 static boolean_t 1574 e1000g_rx_drain(struct e1000g *Adapter) 1575 { 1576 boolean_t done; 1577 1578 mutex_enter(&Adapter->rx_ring->freelist_lock); 1579 done = (Adapter->rx_avail_freepkt == Adapter->NumRxFreeList); 1580 mutex_exit(&Adapter->rx_ring->freelist_lock); 1581 1582 return (done); 1583 } 1584 1585 boolean_t 1586 e1000g_reset(struct e1000g *Adapter) 1587 { 1588 e1000g_stop(Adapter); 1589 1590 if (e1000g_start(Adapter)) { 1591 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1592 return (B_FALSE); 1593 } 1594 1595 return (B_TRUE); 1596 } 1597 1598 /* 1599 * ********************************************************************** 1600 * Name: e1000g_intr_pciexpress * 1601 * * 1602 * Description: * 1603 * This interrupt service routine is for PCI-Express adapters. * 1604 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED * 1605 * bit is set. * 1606 * * 1607 * Parameter Passed: * 1608 * * 1609 * Return Value: * 1610 * * 1611 * Functions called: * 1612 * e1000g_intr_work * 1613 * * 1614 * ********************************************************************** 1615 */ 1616 static uint_t 1617 e1000g_intr_pciexpress(caddr_t arg) 1618 { 1619 struct e1000g *Adapter; 1620 uint32_t ICRContents; 1621 1622 Adapter = (struct e1000g *)arg; 1623 ICRContents = E1000_READ_REG(&Adapter->Shared, ICR); 1624 1625 if (ICRContents & E1000_ICR_INT_ASSERTED) { 1626 /* 1627 * E1000_ICR_INT_ASSERTED bit was set: 1628 * Read(Clear) the ICR, claim this interrupt, 1629 * look for work to do. 1630 */ 1631 e1000g_intr_work(Adapter, ICRContents); 1632 return (DDI_INTR_CLAIMED); 1633 } else { 1634 /* 1635 * E1000_ICR_INT_ASSERTED bit was not set: 1636 * Don't claim this interrupt, return immediately. 1637 */ 1638 return (DDI_INTR_UNCLAIMED); 1639 } 1640 } 1641 1642 /* 1643 * ********************************************************************** 1644 * Name: e1000g_intr * 1645 * * 1646 * Description: * 1647 * This interrupt service routine is for PCI/PCI-X adapters. * 1648 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED * 1649 * bit is set or not. * 1650 * * 1651 * Parameter Passed: * 1652 * * 1653 * Return Value: * 1654 * * 1655 * Functions called: * 1656 * e1000g_intr_work * 1657 * * 1658 * ********************************************************************** 1659 */ 1660 static uint_t 1661 e1000g_intr(caddr_t arg) 1662 { 1663 struct e1000g *Adapter; 1664 uint32_t ICRContents; 1665 1666 Adapter = (struct e1000g *)arg; 1667 ICRContents = E1000_READ_REG(&Adapter->Shared, ICR); 1668 1669 if (ICRContents) { 1670 /* 1671 * Any bit was set in ICR: 1672 * Read(Clear) the ICR, claim this interrupt, 1673 * look for work to do. 1674 */ 1675 e1000g_intr_work(Adapter, ICRContents); 1676 return (DDI_INTR_CLAIMED); 1677 } else { 1678 /* 1679 * No bit was set in ICR: 1680 * Don't claim this interrupt, return immediately. 1681 */ 1682 return (DDI_INTR_UNCLAIMED); 1683 } 1684 } 1685 1686 /* 1687 * ********************************************************************** 1688 * Name: e1000g_intr_work * 1689 * * 1690 * Description: * 1691 * Called from interrupt service routines. * 1692 * Read(clear) the ICR contents and call appropriate interrupt * 1693 * processing routines. * 1694 * * 1695 * Parameter Passed: * 1696 * * 1697 * Return Value: * 1698 * * 1699 * Functions called: * 1700 * e1000g_receive * 1701 * e1000g_link_check * 1702 * e1000g_recycle * 1703 * * 1704 * ********************************************************************** 1705 */ 1706 static void 1707 e1000g_intr_work(struct e1000g *Adapter, uint32_t ICRContents) 1708 { 1709 if (ICRContents & E1000_ICR_RXT0) { 1710 mblk_t *mp; 1711 1712 rw_enter(&Adapter->chip_lock, RW_READER); 1713 /* 1714 * Here we need to check the "started" flag to ensure the 1715 * receive routine will not execute when the adapter is 1716 * stopped or being reset. 1717 */ 1718 if (Adapter->started) { 1719 mutex_enter(&Adapter->rx_ring->rx_lock); 1720 mp = e1000g_receive(Adapter); 1721 mutex_exit(&Adapter->rx_ring->rx_lock); 1722 1723 rw_exit(&Adapter->chip_lock); 1724 1725 if (mp != NULL) 1726 mac_rx(Adapter->mh, Adapter->mrh, mp); 1727 } else { 1728 rw_exit(&Adapter->chip_lock); 1729 } 1730 } 1731 1732 /* 1733 * The Receive Sequence errors RXSEQ and the link status change LSC 1734 * are checked to detect that the cable has been pulled out. For 1735 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1736 * are an indication that cable is not connected. 1737 */ 1738 if ((ICRContents & E1000_ICR_RXSEQ) || 1739 (ICRContents & E1000_ICR_LSC) || 1740 (ICRContents & E1000_ICR_GPI_EN1)) { 1741 boolean_t link_changed; 1742 timeout_id_t tid = 0; 1743 1744 /* 1745 * Encountered RX Sequence Error!!! Link maybe forced and 1746 * the cable may have just been disconnected so we will 1747 * read the LOS to see. 1748 */ 1749 if (ICRContents & E1000_ICR_RXSEQ) 1750 Adapter->rx_seq_intr++; 1751 1752 stop_timeout(Adapter); 1753 1754 mutex_enter(&Adapter->e1000g_linklock); 1755 /* e1000g_link_check takes care of link status change */ 1756 link_changed = e1000g_link_check(Adapter); 1757 /* 1758 * If the link timer has not timed out, we'll not notify 1759 * the upper layer with any link state until the link 1760 * is up. 1761 */ 1762 if (link_changed && !Adapter->link_complete) { 1763 if (Adapter->link_state == LINK_STATE_UP) { 1764 Adapter->link_complete = B_TRUE; 1765 tid = Adapter->link_tid; 1766 Adapter->link_tid = 0; 1767 } else { 1768 link_changed = B_FALSE; 1769 } 1770 } 1771 mutex_exit(&Adapter->e1000g_linklock); 1772 1773 if (link_changed) { 1774 if (tid != 0) 1775 (void) untimeout(tid); 1776 1777 /* 1778 * Workaround for esb2. Data stuck in fifo on a link 1779 * down event. Reset the adapter to recover it. 1780 */ 1781 if ((Adapter->link_state == LINK_STATE_DOWN) && 1782 (Adapter->Shared.mac_type == e1000_80003es2lan)) 1783 (void) e1000g_reset(Adapter); 1784 1785 mac_link_update(Adapter->mh, Adapter->link_state); 1786 } 1787 1788 start_timeout(Adapter); 1789 } 1790 1791 if (ICRContents & E1000G_ICR_TX_INTR) { 1792 if (!Adapter->tx_intr_enable) 1793 e1000g_DisableTxInterrupt(Adapter); 1794 /* Schedule the re-transmit */ 1795 if (Adapter->resched_needed) { 1796 Adapter->tx_reschedule++; 1797 Adapter->resched_needed = B_FALSE; 1798 mac_tx_update(Adapter->mh); 1799 } 1800 if (Adapter->tx_intr_enable) { 1801 /* Recycle the tx descriptors */ 1802 rw_enter(&Adapter->chip_lock, RW_READER); 1803 Adapter->tx_recycle_intr++; 1804 e1000g_recycle(Adapter->tx_ring); 1805 rw_exit(&Adapter->chip_lock); 1806 /* Free the recycled messages */ 1807 ddi_intr_trigger_softint(Adapter->tx_softint_handle, 1808 NULL); 1809 } 1810 } 1811 } 1812 1813 static void 1814 e1000g_init_unicst(struct e1000g *Adapter) 1815 { 1816 struct e1000_hw *hw; 1817 int slot; 1818 1819 hw = &Adapter->Shared; 1820 1821 if (Adapter->init_count == 0) { 1822 /* Initialize the multiple unicast addresses */ 1823 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 1824 1825 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1826 Adapter->unicst_total--; 1827 1828 Adapter->unicst_avail = Adapter->unicst_total - 1; 1829 1830 /* Store the default mac address */ 1831 e1000_rar_set(hw, hw->mac_addr, 0); 1832 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1833 e1000_rar_set(hw, hw->mac_addr, LAST_RAR_ENTRY); 1834 1835 bcopy(hw->mac_addr, Adapter->unicst_addr[0].mac.addr, 1836 ETHERADDRL); 1837 Adapter->unicst_addr[0].mac.set = 1; 1838 1839 for (slot = 1; slot < Adapter->unicst_total; slot++) 1840 Adapter->unicst_addr[slot].mac.set = 0; 1841 } else { 1842 /* Recover the default mac address */ 1843 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac_addr, 1844 ETHERADDRL); 1845 1846 /* Store the default mac address */ 1847 e1000_rar_set(hw, hw->mac_addr, 0); 1848 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1849 e1000_rar_set(hw, hw->mac_addr, LAST_RAR_ENTRY); 1850 1851 /* Re-configure the RAR registers */ 1852 for (slot = 1; slot < Adapter->unicst_total; slot++) 1853 e1000_rar_set(hw, 1854 Adapter->unicst_addr[slot].mac.addr, slot); 1855 } 1856 } 1857 1858 static int 1859 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 1860 { 1861 struct e1000g *Adapter; 1862 1863 Adapter = (struct e1000g *)arg; 1864 1865 /* Store the default MAC address */ 1866 bcopy(mac_addr, Adapter->Shared.mac_addr, ETHERADDRL); 1867 1868 /* Set MAC address in address slot 0, which is the default address */ 1869 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 1870 } 1871 1872 static int 1873 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 1874 mac_addr_slot_t slot) 1875 { 1876 struct e1000_hw *hw; 1877 1878 hw = &Adapter->Shared; 1879 1880 /* 1881 * Error if the address specified is a multicast or broadcast 1882 * address. 1883 */ 1884 if (((mac_addr[0] & 01) == 1) || 1885 (bcmp(mac_addr, ðerbroadcastaddr, ETHERADDRL) == 0)) 1886 return (EINVAL); 1887 1888 rw_enter(&Adapter->chip_lock, RW_WRITER); 1889 1890 /* 1891 * The first revision of Wiseman silicon (rev 2.0) has an errata 1892 * that requires the receiver to be in reset when any of the 1893 * receive address registers (RAR regs) are accessed. The first 1894 * rev of Wiseman silicon also requires MWI to be disabled when 1895 * a global reset or a receive reset is issued. So before we 1896 * initialize the RARs, we check the rev of the Wiseman controller 1897 * and work around any necessary HW errata. 1898 */ 1899 if (hw->mac_type == e1000_82542_rev2_0) { 1900 e1000_pci_clear_mwi(hw); 1901 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1902 DelayInMilliseconds(5); 1903 } 1904 1905 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 1906 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 1907 1908 if (slot == 0) { 1909 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1910 e1000_rar_set(hw, hw->mac_addr, LAST_RAR_ENTRY); 1911 } 1912 1913 /* 1914 * If we are using Wiseman rev 2.0 silicon, we will have previously 1915 * put the receive in reset, and disabled MWI, to work around some 1916 * HW errata. Now we should take the receiver out of reset, and 1917 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 1918 */ 1919 if (hw->mac_type == e1000_82542_rev2_0) { 1920 E1000_WRITE_REG(hw, RCTL, 0); 1921 DelayInMilliseconds(1); 1922 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1923 e1000_pci_set_mwi(hw); 1924 SetupReceiveStructures(Adapter); 1925 } 1926 1927 rw_exit(&Adapter->chip_lock); 1928 1929 return (0); 1930 } 1931 1932 /* 1933 * e1000g_m_unicst_add() - will find an unused address slot, set the 1934 * address value to the one specified, reserve that slot and enable 1935 * the NIC to start filtering on the new MAC address. 1936 * Returns 0 on success. 1937 */ 1938 static int 1939 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 1940 { 1941 struct e1000g *Adapter = (struct e1000g *)arg; 1942 mac_addr_slot_t slot; 1943 int err; 1944 1945 if (mac_unicst_verify(Adapter->mh, 1946 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 1947 return (EINVAL); 1948 1949 rw_enter(&Adapter->chip_lock, RW_WRITER); 1950 if (Adapter->unicst_avail == 0) { 1951 /* no slots available */ 1952 rw_exit(&Adapter->chip_lock); 1953 return (ENOSPC); 1954 } 1955 1956 /* 1957 * Primary/default address is in slot 0. The next addresses 1958 * are the multiple MAC addresses. So multiple MAC address 0 1959 * is in slot 1, 1 in slot 2, and so on. So the first multiple 1960 * MAC address resides in slot 1. 1961 */ 1962 for (slot = 1; slot < Adapter->unicst_total; slot++) { 1963 if (Adapter->unicst_addr[slot].mac.set == 0) { 1964 Adapter->unicst_addr[slot].mac.set = 1; 1965 break; 1966 } 1967 } 1968 1969 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 1970 1971 Adapter->unicst_avail--; 1972 rw_exit(&Adapter->chip_lock); 1973 1974 maddr->mma_slot = slot; 1975 1976 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 1977 rw_enter(&Adapter->chip_lock, RW_WRITER); 1978 Adapter->unicst_addr[slot].mac.set = 0; 1979 Adapter->unicst_avail++; 1980 rw_exit(&Adapter->chip_lock); 1981 } 1982 1983 return (err); 1984 } 1985 1986 /* 1987 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 1988 * call to e1000g_m_unicst_add(). The slot number that was returned in 1989 * e1000g_m_unicst_add() is passed in the call to remove the address. 1990 * Returns 0 on success. 1991 */ 1992 static int 1993 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 1994 { 1995 struct e1000g *Adapter = (struct e1000g *)arg; 1996 int err; 1997 1998 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 1999 return (EINVAL); 2000 2001 rw_enter(&Adapter->chip_lock, RW_WRITER); 2002 if (Adapter->unicst_addr[slot].mac.set == 1) { 2003 Adapter->unicst_addr[slot].mac.set = 0; 2004 Adapter->unicst_avail++; 2005 rw_exit(&Adapter->chip_lock); 2006 2007 /* Copy the default address to the passed slot */ 2008 if (err = e1000g_unicst_set(Adapter, 2009 Adapter->unicst_addr[0].mac.addr, slot) != 0) { 2010 rw_enter(&Adapter->chip_lock, RW_WRITER); 2011 Adapter->unicst_addr[slot].mac.set = 1; 2012 Adapter->unicst_avail--; 2013 rw_exit(&Adapter->chip_lock); 2014 } 2015 return (err); 2016 } 2017 rw_exit(&Adapter->chip_lock); 2018 2019 return (EINVAL); 2020 } 2021 2022 /* 2023 * e1000g_m_unicst_modify() - modifies the value of an address that 2024 * has been added by e1000g_m_unicst_add(). The new address, address 2025 * length and the slot number that was returned in the call to add 2026 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2027 * set to 0. Returns 0 on success. 2028 */ 2029 static int 2030 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2031 { 2032 struct e1000g *Adapter = (struct e1000g *)arg; 2033 mac_addr_slot_t slot; 2034 2035 if (mac_unicst_verify(Adapter->mh, 2036 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2037 return (EINVAL); 2038 2039 slot = maddr->mma_slot; 2040 2041 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2042 return (EINVAL); 2043 2044 rw_enter(&Adapter->chip_lock, RW_WRITER); 2045 if (Adapter->unicst_addr[slot].mac.set == 1) { 2046 rw_exit(&Adapter->chip_lock); 2047 2048 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2049 } 2050 rw_exit(&Adapter->chip_lock); 2051 2052 return (EINVAL); 2053 } 2054 2055 /* 2056 * e1000g_m_unicst_get() - will get the MAC address and all other 2057 * information related to the address slot passed in mac_multi_addr_t. 2058 * mma_flags should be set to 0 in the call. 2059 * On return, mma_flags can take the following values: 2060 * 1) MMAC_SLOT_UNUSED 2061 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2062 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2063 * 4) MMAC_SLOT_USED 2064 */ 2065 static int 2066 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2067 { 2068 struct e1000g *Adapter = (struct e1000g *)arg; 2069 mac_addr_slot_t slot; 2070 2071 slot = maddr->mma_slot; 2072 2073 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2074 return (EINVAL); 2075 2076 rw_enter(&Adapter->chip_lock, RW_WRITER); 2077 if (Adapter->unicst_addr[slot].mac.set == 1) { 2078 bcopy(Adapter->unicst_addr[slot].mac.addr, 2079 maddr->mma_addr, ETHERADDRL); 2080 maddr->mma_flags = MMAC_SLOT_USED; 2081 } else { 2082 maddr->mma_flags = MMAC_SLOT_UNUSED; 2083 } 2084 rw_exit(&Adapter->chip_lock); 2085 2086 return (0); 2087 } 2088 2089 static int 2090 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2091 { 2092 unsigned i; 2093 int res = 0; 2094 2095 rw_enter(&Adapter->chip_lock, RW_WRITER); 2096 2097 if ((multiaddr[0] & 01) == 0) { 2098 res = EINVAL; 2099 goto done; 2100 } 2101 2102 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2103 res = ENOENT; 2104 goto done; 2105 } 2106 2107 bcopy(multiaddr, 2108 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2109 Adapter->mcast_count++; 2110 2111 /* 2112 * Update the MC table in the hardware 2113 */ 2114 e1000g_DisableInterrupt(Adapter); 2115 2116 SetupMulticastTable(Adapter); 2117 2118 if (Adapter->Shared.mac_type == e1000_82542_rev2_0) 2119 SetupReceiveStructures(Adapter); 2120 2121 e1000g_EnableInterrupt(Adapter); 2122 2123 done: 2124 rw_exit(&Adapter->chip_lock); 2125 return (res); 2126 } 2127 2128 static int 2129 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2130 { 2131 unsigned i; 2132 2133 rw_enter(&Adapter->chip_lock, RW_WRITER); 2134 2135 for (i = 0; i < Adapter->mcast_count; i++) { 2136 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2137 ETHERADDRL) == 0) { 2138 for (i++; i < Adapter->mcast_count; i++) { 2139 Adapter->mcast_table[i - 1] = 2140 Adapter->mcast_table[i]; 2141 } 2142 Adapter->mcast_count--; 2143 break; 2144 } 2145 } 2146 2147 /* 2148 * Update the MC table in the hardware 2149 */ 2150 e1000g_DisableInterrupt(Adapter); 2151 2152 SetupMulticastTable(Adapter); 2153 2154 if (Adapter->Shared.mac_type == e1000_82542_rev2_0) 2155 SetupReceiveStructures(Adapter); 2156 2157 e1000g_EnableInterrupt(Adapter); 2158 2159 done: 2160 rw_exit(&Adapter->chip_lock); 2161 return (0); 2162 } 2163 2164 int 2165 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2166 { 2167 struct e1000g *Adapter = (struct e1000g *)arg; 2168 2169 return ((add) ? multicst_add(Adapter, addr) 2170 : multicst_remove(Adapter, addr)); 2171 } 2172 2173 int 2174 e1000g_m_promisc(void *arg, boolean_t on) 2175 { 2176 struct e1000g *Adapter = (struct e1000g *)arg; 2177 ULONG RctlRegValue; 2178 2179 rw_enter(&Adapter->chip_lock, RW_WRITER); 2180 2181 RctlRegValue = E1000_READ_REG(&Adapter->Shared, RCTL); 2182 2183 if (on) 2184 RctlRegValue |= 2185 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2186 else 2187 RctlRegValue &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2188 2189 E1000_WRITE_REG(&Adapter->Shared, RCTL, RctlRegValue); 2190 2191 Adapter->e1000g_promisc = on; 2192 2193 rw_exit(&Adapter->chip_lock); 2194 2195 return (0); 2196 } 2197 2198 static boolean_t 2199 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2200 { 2201 struct e1000g *Adapter = (struct e1000g *)arg; 2202 2203 switch (cap) { 2204 case MAC_CAPAB_HCKSUM: { 2205 uint32_t *txflags = cap_data; 2206 2207 /* 2208 * In Jumbo mode, enabling hardware checksum will cause 2209 * port hang. 2210 */ 2211 if (Adapter->Shared.max_frame_size > ETHERMAX) 2212 return (B_FALSE); 2213 2214 /* 2215 * Checksum on/off selection via global parameters. 2216 * 2217 * If the chip is flagged as not capable of (correctly) 2218 * handling FULL checksumming, we don't enable it on either 2219 * Rx or Tx side. Otherwise, we take this chip's settings 2220 * from the patchable global defaults. 2221 * 2222 * We advertise our capabilities only if TX offload is 2223 * enabled. On receive, the stack will accept checksummed 2224 * packets anyway, even if we haven't said we can deliver 2225 * them. 2226 */ 2227 switch (Adapter->Shared.mac_type) { 2228 /* 2229 * Switch on hardware checksum offload of 2230 * chip 82540, 82545, 82546 2231 */ 2232 case e1000_82540: 2233 case e1000_82544: /* pci8086,1008 */ 2234 case e1000_82545: 2235 case e1000_82545_rev_3: /* pci8086,1026 */ 2236 case e1000_82571: 2237 case e1000_82572: 2238 case e1000_82573: 2239 case e1000_80003es2lan: 2240 *txflags = HCKSUM_IPHDRCKSUM | HCKSUM_INET_PARTIAL; 2241 break; 2242 2243 case e1000_82546: /* 82546EB. devID: 1010, 101d */ 2244 case e1000_82546_rev_3: /* 82546GB. devID: 1079, 107a */ 2245 #if !defined(__sparc) && !defined(__amd64) 2246 /* Workaround for Galaxy on 32bit */ 2247 return (B_FALSE); 2248 #else 2249 *txflags = HCKSUM_IPHDRCKSUM | HCKSUM_INET_PARTIAL; 2250 break; 2251 #endif 2252 2253 /* 2254 * We don't have the following PRO 1000 chip types at 2255 * hand and haven't tested their hardware checksum 2256 * offload capability. We had better switch them off. 2257 * e1000_undefined = 0, 2258 * e1000_82542_rev2_0, 2259 * e1000_82542_rev2_1, 2260 * e1000_82543, 2261 * e1000_82541, 2262 * e1000_82541_rev_2, 2263 * e1000_82547, 2264 * e1000_82547_rev_2, 2265 * e1000_num_macs 2266 */ 2267 default: 2268 return (B_FALSE); 2269 } 2270 2271 break; 2272 } 2273 case MAC_CAPAB_POLL: 2274 /* 2275 * There's nothing for us to fill in, simply returning 2276 * B_TRUE stating that we support polling is sufficient. 2277 */ 2278 break; 2279 2280 case MAC_CAPAB_MULTIADDRESS: { 2281 multiaddress_capab_t *mmacp = cap_data; 2282 2283 /* 2284 * The number of MAC addresses made available by 2285 * this capability is one less than the total as 2286 * the primary address in slot 0 is counted in 2287 * the total. 2288 */ 2289 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2290 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2291 /* No multiple factory addresses, set mma_flag to 0 */ 2292 mmacp->maddr_flag = 0; 2293 mmacp->maddr_handle = Adapter; 2294 mmacp->maddr_add = e1000g_m_unicst_add; 2295 mmacp->maddr_remove = e1000g_m_unicst_remove; 2296 mmacp->maddr_modify = e1000g_m_unicst_modify; 2297 mmacp->maddr_get = e1000g_m_unicst_get; 2298 mmacp->maddr_reserve = NULL; 2299 break; 2300 } 2301 default: 2302 return (B_FALSE); 2303 } 2304 return (B_TRUE); 2305 } 2306 2307 /* 2308 * ********************************************************************** 2309 * Name: e1000g_getparam * 2310 * * 2311 * Description: This routine gets user-configured values out of the * 2312 * configuration file e1000g.conf. * 2313 * For each configurable value, there is a minimum, a maximum, and a * 2314 * default. * 2315 * If user does not configure a value, use the default. * 2316 * If user configures below the minimum, use the minumum. * 2317 * If user configures above the maximum, use the maxumum. * 2318 * * 2319 * Arguments: * 2320 * Adapter - A pointer to our adapter structure * 2321 * * 2322 * Returns: None * 2323 * ********************************************************************** 2324 */ 2325 static void 2326 e1000g_getparam(struct e1000g *Adapter) 2327 { 2328 /* 2329 * get each configurable property from e1000g.conf 2330 */ 2331 2332 /* 2333 * NumTxDescriptors 2334 */ 2335 Adapter->NumTxDescriptors = 2336 e1000g_getprop(Adapter, "NumTxDescriptors", 2337 MINNUMTXDESCRIPTOR, MAXNUMTXDESCRIPTOR, 2338 DEFAULTNUMTXDESCRIPTOR); 2339 2340 /* 2341 * NumRxDescriptors 2342 */ 2343 Adapter->NumRxDescriptors = 2344 e1000g_getprop(Adapter, "NumRxDescriptors", 2345 MINNUMRXDESCRIPTOR, MAXNUMRXDESCRIPTOR, 2346 DEFAULTNUMRXDESCRIPTOR); 2347 2348 /* 2349 * NumRxFreeList 2350 */ 2351 Adapter->NumRxFreeList = 2352 e1000g_getprop(Adapter, "NumRxFreeList", 2353 MINNUMRXFREELIST, MAXNUMRXFREELIST, 2354 DEFAULTNUMRXFREELIST); 2355 2356 /* 2357 * NumTxPacketList 2358 */ 2359 Adapter->NumTxSwPacket = 2360 e1000g_getprop(Adapter, "NumTxPacketList", 2361 MINNUMTXSWPACKET, MAXNUMTXSWPACKET, 2362 DEFAULTNUMTXSWPACKET); 2363 2364 /* 2365 * FlowControl 2366 */ 2367 Adapter->Shared.fc_send_xon = B_TRUE; 2368 Adapter->Shared.fc = 2369 e1000g_getprop(Adapter, "FlowControl", 2370 E1000_FC_NONE, 4, DEFAULTFLOWCONTROLVAL); 2371 /* 4 is the setting that says "let the eeprom decide" */ 2372 if (Adapter->Shared.fc == 4) 2373 Adapter->Shared.fc = E1000_FC_DEFAULT; 2374 2375 /* 2376 * MaxNumReceivePackets 2377 */ 2378 Adapter->MaxNumReceivePackets = 2379 e1000g_getprop(Adapter, "MaxNumReceivePackets", 2380 MINNUMRCVPKTONINTR, MAXNUMRCVPKTONINTR, 2381 DEFAULTMAXNUMRCVPKTONINTR); 2382 2383 /* 2384 * TxInterruptDelay 2385 */ 2386 Adapter->TxInterruptDelay = 2387 e1000g_getprop(Adapter, "TxInterruptDelay", 2388 MINTXINTERRUPTDELAYVAL, MAXTXINTERRUPTDELAYVAL, 2389 DEFAULTTXINTERRUPTDELAYVAL); 2390 2391 /* 2392 * PHY master slave setting 2393 */ 2394 Adapter->Shared.master_slave = 2395 e1000g_getprop(Adapter, "SetMasterSlave", 2396 e1000_ms_hw_default, e1000_ms_auto, 2397 e1000_ms_hw_default); 2398 2399 /* 2400 * Parameter which controls TBI mode workaround, which is only 2401 * needed on certain switches such as Cisco 6500/Foundry 2402 */ 2403 Adapter->Shared.tbi_compatibility_en = 2404 e1000g_getprop(Adapter, "TbiCompatibilityEnable", 2405 0, 1, DEFAULTTBICOMPATIBILITYENABLE); 2406 2407 /* 2408 * MSI Enable 2409 */ 2410 Adapter->msi_enabled = 2411 e1000g_getprop(Adapter, "MSIEnable", 2412 0, 1, DEFAULTMSIENABLE); 2413 2414 /* 2415 * Interrupt Throttling Rate 2416 */ 2417 Adapter->intr_throttling_rate = 2418 e1000g_getprop(Adapter, "intr_throttling_rate", 2419 MININTERRUPTTHROTTLINGVAL, MAXINTERRUPTTHROTTLINGVAL, 2420 DEFAULTINTERRUPTTHROTTLINGVAL); 2421 2422 /* 2423 * Adaptive Interrupt Blanking Enable/Disable 2424 * It is enabled by default 2425 */ 2426 Adapter->intr_adaptive = 2427 (e1000g_getprop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 2428 B_TRUE : B_FALSE; 2429 } 2430 2431 /* 2432 * ********************************************************************** 2433 * Name: e1000g_getprop * 2434 * * 2435 * Description: get a user-configure property value out of the * 2436 * configuration file e1000g.conf. * 2437 * Caller provides name of the property, a default value, a * 2438 * minimum value, and a maximum value. * 2439 * * 2440 * Returns: configured value of the property, with default, minimum and * 2441 * maximum properly applied. * 2442 * ********************************************************************** 2443 */ 2444 static int 2445 e1000g_getprop(struct e1000g *Adapter, /* point to per-adapter structure */ 2446 char *propname, /* name of the property */ 2447 int minval, /* minimum acceptable value */ 2448 int maxval, /* maximim acceptable value */ 2449 int defval) /* default value */ 2450 { 2451 int propval; /* value returned for requested property */ 2452 int *props; /* point to array of properties returned */ 2453 uint_t nprops; /* number of property value returned */ 2454 2455 /* 2456 * get the array of properties from the config file 2457 */ 2458 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 2459 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 2460 /* got some properties, test if we got enough */ 2461 if (Adapter->AdapterInstance < nprops) { 2462 propval = props[Adapter->AdapterInstance]; 2463 } else { 2464 /* not enough properties configured */ 2465 propval = defval; 2466 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 2467 "Not Enough %s values found in e1000g.conf" 2468 " - set to %d\n", 2469 propname, propval); 2470 } 2471 2472 /* free memory allocated for properties */ 2473 ddi_prop_free(props); 2474 2475 } else { 2476 propval = defval; 2477 } 2478 2479 /* 2480 * enforce limits 2481 */ 2482 if (propval > maxval) { 2483 propval = maxval; 2484 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 2485 "Too High %s value in e1000g.conf - set to %d\n", 2486 propname, propval); 2487 } 2488 2489 if (propval < minval) { 2490 propval = minval; 2491 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 2492 "Too Low %s value in e1000g.conf - set to %d\n", 2493 propname, propval); 2494 } 2495 2496 return (propval); 2497 } 2498 2499 static boolean_t 2500 e1000g_link_check(struct e1000g *Adapter) 2501 { 2502 uint16_t speed, duplex, phydata; 2503 boolean_t link_changed = B_FALSE; 2504 struct e1000_hw *hw; 2505 uint32_t reg_tarc; 2506 2507 hw = &Adapter->Shared; 2508 2509 if (e1000g_link_up(Adapter)) { 2510 /* 2511 * The Link is up, check whether it was marked as down earlier 2512 */ 2513 if (Adapter->link_state != LINK_STATE_UP) { 2514 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2515 Adapter->link_speed = speed; 2516 Adapter->link_duplex = duplex; 2517 Adapter->link_state = LINK_STATE_UP; 2518 link_changed = B_TRUE; 2519 2520 Adapter->tx_link_down_timeout = 0; 2521 2522 if ((hw->mac_type == e1000_82571) || 2523 (hw->mac_type == e1000_82572)) { 2524 reg_tarc = E1000_READ_REG(hw, TARC0); 2525 if (speed == SPEED_1000) 2526 reg_tarc |= (1 << 21); 2527 else 2528 reg_tarc &= ~(1 << 21); 2529 E1000_WRITE_REG(hw, TARC0, reg_tarc); 2530 } 2531 2532 e1000g_log(Adapter, CE_NOTE, 2533 "Adapter %dMbps %s %s link is up.", speed, 2534 ((duplex == FULL_DUPLEX) ? 2535 "full duplex" : "half duplex"), 2536 ((hw->media_type == e1000_media_type_copper) ? 2537 "copper" : "fiber")); 2538 } 2539 Adapter->smartspeed = 0; 2540 } else { 2541 if (Adapter->link_state != LINK_STATE_DOWN) { 2542 Adapter->link_speed = 0; 2543 Adapter->link_duplex = 0; 2544 Adapter->link_state = LINK_STATE_DOWN; 2545 link_changed = B_TRUE; 2546 2547 e1000g_log(Adapter, CE_NOTE, 2548 "Adapter %s link is down.", 2549 ((hw->media_type == e1000_media_type_copper) ? 2550 "copper" : "fiber")); 2551 2552 /* 2553 * SmartSpeed workaround for Tabor/TanaX, When the 2554 * driver loses link disable auto master/slave 2555 * resolution. 2556 */ 2557 if (hw->phy_type == e1000_phy_igp) { 2558 e1000_read_phy_reg(hw, 2559 PHY_1000T_CTRL, &phydata); 2560 phydata |= CR_1000T_MS_ENABLE; 2561 e1000_write_phy_reg(hw, 2562 PHY_1000T_CTRL, phydata); 2563 } 2564 } else { 2565 e1000g_smartspeed(Adapter); 2566 } 2567 2568 if (Adapter->started) { 2569 if (Adapter->tx_link_down_timeout < 2570 MAX_TX_LINK_DOWN_TIMEOUT) { 2571 Adapter->tx_link_down_timeout++; 2572 } else if (Adapter->tx_link_down_timeout == 2573 MAX_TX_LINK_DOWN_TIMEOUT) { 2574 rw_enter(&Adapter->chip_lock, RW_WRITER); 2575 e1000g_tx_drop(Adapter); 2576 rw_exit(&Adapter->chip_lock); 2577 Adapter->tx_link_down_timeout++; 2578 } 2579 } 2580 } 2581 2582 return (link_changed); 2583 } 2584 2585 static void 2586 e1000g_LocalTimer(void *ws) 2587 { 2588 struct e1000g *Adapter = (struct e1000g *)ws; 2589 struct e1000_hw *hw; 2590 e1000g_ether_addr_t ether_addr; 2591 boolean_t link_changed; 2592 2593 hw = &Adapter->Shared; 2594 2595 (void) e1000g_tx_freemsg((caddr_t)Adapter, NULL); 2596 2597 if (e1000g_stall_check(Adapter)) { 2598 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 2599 "Tx stall detected. Activate automatic recovery.\n"); 2600 Adapter->StallWatchdog = 0; 2601 Adapter->tx_recycle_fail = 0; 2602 Adapter->reset_count++; 2603 (void) e1000g_reset(Adapter); 2604 } 2605 2606 link_changed = B_FALSE; 2607 mutex_enter(&Adapter->e1000g_linklock); 2608 if (Adapter->link_complete) 2609 link_changed = e1000g_link_check(Adapter); 2610 mutex_exit(&Adapter->e1000g_linklock); 2611 2612 if (link_changed) { 2613 /* 2614 * Workaround for esb2. Data stuck in fifo on a link 2615 * down event. Reset the adapter to recover it. 2616 */ 2617 if ((Adapter->link_state == LINK_STATE_DOWN) && 2618 (hw->mac_type == e1000_80003es2lan)) 2619 (void) e1000g_reset(Adapter); 2620 2621 mac_link_update(Adapter->mh, Adapter->link_state); 2622 } 2623 2624 /* 2625 * With 82571 controllers, any locally administered address will 2626 * be overwritten when there is a reset on the other port. 2627 * Detect this circumstance and correct it. 2628 */ 2629 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) { 2630 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, RA, 0); 2631 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, RA, 1); 2632 2633 ether_addr.reg.low = ntohl(ether_addr.reg.low); 2634 ether_addr.reg.high = ntohl(ether_addr.reg.high); 2635 2636 if ((ether_addr.mac.addr[5] != hw->mac_addr[0]) || 2637 (ether_addr.mac.addr[4] != hw->mac_addr[1]) || 2638 (ether_addr.mac.addr[3] != hw->mac_addr[2]) || 2639 (ether_addr.mac.addr[2] != hw->mac_addr[3]) || 2640 (ether_addr.mac.addr[1] != hw->mac_addr[4]) || 2641 (ether_addr.mac.addr[0] != hw->mac_addr[5])) { 2642 e1000_rar_set(hw, hw->mac_addr, 0); 2643 } 2644 } 2645 2646 /* 2647 * RP: ttl_workaround : DCR 49 2648 */ 2649 e1000_igp_ttl_workaround(hw); 2650 2651 /* 2652 * Check for Adaptive IFS settings If there are lots of collisions 2653 * change the value in steps... 2654 * These properties should only be set for 10/100 2655 */ 2656 if ((hw->media_type == e1000_media_type_copper) && 2657 ((Adapter->link_speed == SPEED_100) || 2658 (Adapter->link_speed == SPEED_10))) { 2659 e1000_update_adaptive(hw); 2660 } 2661 /* 2662 * Set Timer Interrupts 2663 */ 2664 E1000_WRITE_REG(hw, ICS, E1000_IMS_RXT0); 2665 2666 restart_timeout(Adapter); 2667 } 2668 2669 /* 2670 * The function e1000g_link_timer() is called when the timer for link setup 2671 * is expired, which indicates the completion of the link setup. The link 2672 * state will not be updated until the link setup is completed. And the 2673 * link state will not be sent to the upper layer through mac_link_update() 2674 * in this function. It will be updated in the local timer routine or the 2675 * interrupt service routine after the interface is started (plumbed). 2676 */ 2677 static void 2678 e1000g_link_timer(void *arg) 2679 { 2680 struct e1000g *Adapter = (struct e1000g *)arg; 2681 2682 mutex_enter(&Adapter->e1000g_linklock); 2683 Adapter->link_complete = B_TRUE; 2684 Adapter->link_tid = 0; 2685 mutex_exit(&Adapter->e1000g_linklock); 2686 } 2687 2688 /* 2689 * ********************************************************************** 2690 * Name: e1000g_force_speed_duplex * 2691 * * 2692 * Description: * 2693 * This function forces speed and duplex for 10/100 Mbps speeds * 2694 * and also for 1000 Mbps speeds, it advertises half or full duplex * 2695 * * 2696 * Parameter Passed: * 2697 * struct e1000g* (information of adpater) * 2698 * * 2699 * Return Value: * 2700 * * 2701 * Functions called: * 2702 * ********************************************************************** 2703 */ 2704 static void 2705 e1000g_force_speed_duplex(struct e1000g *Adapter) 2706 { 2707 int forced; 2708 2709 /* 2710 * get value out of config file 2711 */ 2712 forced = e1000g_getprop(Adapter, "ForceSpeedDuplex", 2713 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 2714 2715 switch (forced) { 2716 case GDIAG_10_HALF: 2717 /* 2718 * Disable Auto Negotiation 2719 */ 2720 Adapter->Shared.autoneg = B_FALSE; 2721 Adapter->Shared.forced_speed_duplex = e1000_10_half; 2722 break; 2723 case GDIAG_10_FULL: 2724 /* 2725 * Disable Auto Negotiation 2726 */ 2727 Adapter->Shared.autoneg = B_FALSE; 2728 Adapter->Shared.forced_speed_duplex = e1000_10_full; 2729 break; 2730 case GDIAG_100_HALF: 2731 /* 2732 * Disable Auto Negotiation 2733 */ 2734 Adapter->Shared.autoneg = B_FALSE; 2735 Adapter->Shared.forced_speed_duplex = e1000_100_half; 2736 break; 2737 case GDIAG_100_FULL: 2738 /* 2739 * Disable Auto Negotiation 2740 */ 2741 Adapter->Shared.autoneg = B_FALSE; 2742 Adapter->Shared.forced_speed_duplex = e1000_100_full; 2743 break; 2744 case GDIAG_1000_FULL: 2745 /* 2746 * The gigabit spec requires autonegotiation. Therefore, 2747 * when the user wants to force the speed to 1000Mbps, we 2748 * enable AutoNeg, but only allow the harware to advertise 2749 * 1000Mbps. This is different from 10/100 operation, where 2750 * we are allowed to link without any negotiation. 2751 */ 2752 Adapter->Shared.autoneg = B_TRUE; 2753 Adapter->Shared.autoneg_advertised = ADVERTISE_1000_FULL; 2754 break; 2755 default: /* obey the setting of AutoNegAdvertised */ 2756 Adapter->Shared.autoneg = B_TRUE; 2757 Adapter->Shared.autoneg_advertised = 2758 (uint16_t)e1000g_getprop(Adapter, "AutoNegAdvertised", 2759 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 2760 AUTONEG_ADVERTISE_SPEED_DEFAULT); 2761 break; 2762 } /* switch */ 2763 } 2764 2765 /* 2766 * ********************************************************************** 2767 * Name: e1000g_get_max_frame_size * 2768 * * 2769 * Description: * 2770 * This function reads MaxFrameSize from e1000g.conf and sets it for * 2771 * adapter. * 2772 * * 2773 * Parameter Passed: * 2774 * struct e1000g* (information of adpater) * 2775 * * 2776 * Return Value: * 2777 * * 2778 * Functions called: * 2779 * ********************************************************************** 2780 */ 2781 static void 2782 e1000g_get_max_frame_size(struct e1000g *Adapter) 2783 { 2784 int max_frame; 2785 2786 /* 2787 * get value out of config file 2788 */ 2789 max_frame = e1000g_getprop(Adapter, "MaxFrameSize", 0, 3, 0); 2790 2791 switch (max_frame) { 2792 case 0: 2793 Adapter->Shared.max_frame_size = ETHERMAX; 2794 break; 2795 case 1: 2796 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_4K; 2797 break; 2798 case 2: 2799 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_8K; 2800 break; 2801 case 3: 2802 if (Adapter->Shared.mac_type < e1000_82571) 2803 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_16K; 2804 else 2805 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_10K; 2806 break; 2807 default: 2808 Adapter->Shared.max_frame_size = ETHERMAX; 2809 break; 2810 } /* switch */ 2811 2812 /* ich8 does not do jumbo frames */ 2813 if (Adapter->Shared.mac_type == e1000_ich8lan) { 2814 Adapter->Shared.max_frame_size = ETHERMAX; 2815 } 2816 } 2817 2818 static void 2819 arm_timer(struct e1000g *Adapter) 2820 { 2821 Adapter->WatchDogTimer_id = 2822 timeout(e1000g_LocalTimer, 2823 (void *)Adapter, 1 * drv_usectohz(1000000)); 2824 } 2825 2826 static void 2827 enable_timeout(struct e1000g *Adapter) 2828 { 2829 mutex_enter(&Adapter->e1000g_timeout_lock); 2830 2831 if (!Adapter->timeout_enabled) { 2832 Adapter->timeout_enabled = B_TRUE; 2833 Adapter->timeout_started = B_TRUE; 2834 2835 arm_timer(Adapter); 2836 } 2837 2838 mutex_exit(&Adapter->e1000g_timeout_lock); 2839 } 2840 2841 static void 2842 disable_timeout(struct e1000g *Adapter) 2843 { 2844 timeout_id_t tid; 2845 2846 mutex_enter(&Adapter->e1000g_timeout_lock); 2847 2848 Adapter->timeout_enabled = B_FALSE; 2849 Adapter->timeout_started = B_FALSE; 2850 2851 tid = Adapter->WatchDogTimer_id; 2852 Adapter->WatchDogTimer_id = 0; 2853 2854 mutex_exit(&Adapter->e1000g_timeout_lock); 2855 2856 if (tid != 0) 2857 (void) untimeout(tid); 2858 } 2859 2860 static void 2861 start_timeout(struct e1000g *Adapter) 2862 { 2863 mutex_enter(&Adapter->e1000g_timeout_lock); 2864 2865 if (Adapter->timeout_enabled) { 2866 if (!Adapter->timeout_started) { 2867 Adapter->timeout_started = B_TRUE; 2868 arm_timer(Adapter); 2869 } 2870 } 2871 2872 mutex_exit(&Adapter->e1000g_timeout_lock); 2873 } 2874 2875 static void 2876 restart_timeout(struct e1000g *Adapter) 2877 { 2878 mutex_enter(&Adapter->e1000g_timeout_lock); 2879 2880 if (Adapter->timeout_started) 2881 arm_timer(Adapter); 2882 2883 mutex_exit(&Adapter->e1000g_timeout_lock); 2884 } 2885 2886 static void 2887 stop_timeout(struct e1000g *Adapter) 2888 { 2889 timeout_id_t tid; 2890 2891 mutex_enter(&Adapter->e1000g_timeout_lock); 2892 2893 Adapter->timeout_started = B_FALSE; 2894 2895 tid = Adapter->WatchDogTimer_id; 2896 Adapter->WatchDogTimer_id = 0; 2897 2898 mutex_exit(&Adapter->e1000g_timeout_lock); 2899 2900 if (tid != 0) 2901 (void) untimeout(tid); 2902 } 2903 2904 void 2905 e1000g_DisableInterrupt(struct e1000g *Adapter) 2906 { 2907 E1000_WRITE_REG(&Adapter->Shared, IMC, 2908 0xffffffff & ~E1000_IMC_RXSEQ); 2909 } 2910 2911 void 2912 e1000g_EnableInterrupt(struct e1000g *Adapter) 2913 { 2914 E1000_WRITE_REG(&Adapter->Shared, IMS, 2915 IMS_ENABLE_MASK & ~E1000_IMS_TXDW & ~E1000_IMS_TXQE); 2916 } 2917 2918 void 2919 e1000g_DisableAllInterrupts(struct e1000g *Adapter) 2920 { 2921 E1000_WRITE_REG(&Adapter->Shared, IMC, 0xffffffff) 2922 } 2923 2924 void 2925 e1000g_EnableTxInterrupt(struct e1000g *Adapter) 2926 { 2927 E1000_WRITE_REG(&Adapter->Shared, IMS, E1000G_IMS_TX_INTR); 2928 } 2929 2930 void 2931 e1000g_DisableTxInterrupt(struct e1000g *Adapter) 2932 { 2933 E1000_WRITE_REG(&Adapter->Shared, IMC, E1000G_IMC_TX_INTR); 2934 } 2935 2936 void 2937 e1000_pci_set_mwi(struct e1000_hw *hw) 2938 { 2939 uint16_t val = hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE; 2940 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); 2941 } 2942 2943 void 2944 e1000_pci_clear_mwi(struct e1000_hw *hw) 2945 { 2946 uint16_t val = hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE; 2947 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); 2948 } 2949 2950 void 2951 e1000_write_pci_cfg(struct e1000_hw *adapter, 2952 uint32_t reg, uint16_t *value) 2953 { 2954 pci_config_put16(((struct e1000g_osdep *)(adapter->back))->handle, 2955 reg, *value); 2956 } 2957 2958 void 2959 e1000_read_pci_cfg(struct e1000_hw *adapter, 2960 uint32_t reg, uint16_t *value) 2961 { 2962 *value = 2963 pci_config_get16(((struct e1000g_osdep *)(adapter->back))-> 2964 handle, reg); 2965 } 2966 2967 #ifndef __sparc 2968 void 2969 e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value) 2970 { 2971 outl(port, value); 2972 } 2973 2974 uint32_t 2975 e1000_io_read(struct e1000_hw *hw, unsigned long port) 2976 { 2977 return (inl(port)); 2978 } 2979 #endif 2980 2981 static void 2982 e1000g_smartspeed(struct e1000g *adapter) 2983 { 2984 uint16_t phy_status; 2985 uint16_t phy_ctrl; 2986 2987 /* 2988 * If we're not T-or-T, or we're not autoneg'ing, or we're not 2989 * advertising 1000Full, we don't even use the workaround 2990 */ 2991 if ((adapter->Shared.phy_type != e1000_phy_igp) || 2992 !adapter->Shared.autoneg || 2993 !(adapter->Shared.autoneg_advertised & ADVERTISE_1000_FULL)) 2994 return; 2995 2996 /* 2997 * True if this is the first call of this function or after every 2998 * 30 seconds of not having link 2999 */ 3000 if (adapter->smartspeed == 0) { 3001 /* 3002 * If Master/Slave config fault is asserted twice, we 3003 * assume back-to-back 3004 */ 3005 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_STATUS, 3006 &phy_status); 3007 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3008 return; 3009 3010 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_STATUS, 3011 &phy_status); 3012 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3013 return; 3014 /* 3015 * We're assuming back-2-back because our status register 3016 * insists! there's a fault in the master/slave 3017 * relationship that was "negotiated" 3018 */ 3019 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_CTRL, 3020 &phy_ctrl); 3021 /* 3022 * Is the phy configured for manual configuration of 3023 * master/slave? 3024 */ 3025 if (phy_ctrl & CR_1000T_MS_ENABLE) { 3026 /* 3027 * Yes. Then disable manual configuration (enable 3028 * auto configuration) of master/slave 3029 */ 3030 phy_ctrl &= ~CR_1000T_MS_ENABLE; 3031 e1000_write_phy_reg(&adapter->Shared, 3032 PHY_1000T_CTRL, phy_ctrl); 3033 /* 3034 * Effectively starting the clock 3035 */ 3036 adapter->smartspeed++; 3037 /* 3038 * Restart autonegotiation 3039 */ 3040 if (!e1000_phy_setup_autoneg(&adapter->Shared) && 3041 !e1000_read_phy_reg(&adapter->Shared, PHY_CTRL, 3042 &phy_ctrl)) { 3043 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 3044 MII_CR_RESTART_AUTO_NEG); 3045 e1000_write_phy_reg(&adapter->Shared, 3046 PHY_CTRL, phy_ctrl); 3047 } 3048 } 3049 return; 3050 /* 3051 * Has 6 seconds transpired still without link? Remember, 3052 * you should reset the smartspeed counter once you obtain 3053 * link 3054 */ 3055 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 3056 /* 3057 * Yes. Remember, we did at the start determine that 3058 * there's a master/slave configuration fault, so we're 3059 * still assuming there's someone on the other end, but we 3060 * just haven't yet been able to talk to it. We then 3061 * re-enable auto configuration of master/slave to see if 3062 * we're running 2/3 pair cables. 3063 */ 3064 /* 3065 * If still no link, perhaps using 2/3 pair cable 3066 */ 3067 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_CTRL, 3068 &phy_ctrl); 3069 phy_ctrl |= CR_1000T_MS_ENABLE; 3070 e1000_write_phy_reg(&adapter->Shared, PHY_1000T_CTRL, 3071 phy_ctrl); 3072 /* 3073 * Restart autoneg with phy enabled for manual 3074 * configuration of master/slave 3075 */ 3076 if (!e1000_phy_setup_autoneg(&adapter->Shared) && 3077 !e1000_read_phy_reg(&adapter->Shared, PHY_CTRL, 3078 &phy_ctrl)) { 3079 phy_ctrl |= 3080 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 3081 e1000_write_phy_reg(&adapter->Shared, PHY_CTRL, 3082 phy_ctrl); 3083 } 3084 /* 3085 * Hopefully, there are no more faults and we've obtained 3086 * link as a result. 3087 */ 3088 } 3089 /* 3090 * Restart process after E1000_SMARTSPEED_MAX iterations (30 3091 * seconds) 3092 */ 3093 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 3094 adapter->smartspeed = 0; 3095 } 3096 3097 static boolean_t 3098 is_valid_mac_addr(uint8_t *mac_addr) 3099 { 3100 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 3101 const uint8_t addr_test2[6] = 3102 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 3103 3104 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 3105 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 3106 return (B_FALSE); 3107 3108 return (B_TRUE); 3109 } 3110 3111 /* 3112 * ********************************************************************** 3113 * Name: * 3114 * e1000g_stall_check * 3115 * * 3116 * Description: * 3117 * This function checks if the adapter is stalled. (In transmit) * 3118 * * 3119 * It is called each time the timeout is invoked. * 3120 * If the transmit descriptor reclaim continuously fails, * 3121 * the watchdog value will increment by 1. If the watchdog * 3122 * value exceeds the threshold, the adapter is assumed to * 3123 * have stalled and need to be reset. * 3124 * * 3125 * Arguments: * 3126 * Adapter - A pointer to our context sensitive "Adapter" * 3127 * structure. * 3128 * * 3129 * Returns: * 3130 * B_TRUE - The dapter is assumed to have stalled. * 3131 * B_FALSE * 3132 * * 3133 * ********************************************************************** 3134 */ 3135 static boolean_t 3136 e1000g_stall_check(struct e1000g *Adapter) 3137 { 3138 if (Adapter->link_state != LINK_STATE_UP) 3139 return (B_FALSE); 3140 3141 if (Adapter->tx_recycle_fail > 0) 3142 Adapter->StallWatchdog++; 3143 else 3144 Adapter->StallWatchdog = 0; 3145 3146 if (Adapter->StallWatchdog < E1000G_STALL_WATCHDOG_COUNT) 3147 return (B_FALSE); 3148 3149 return (B_TRUE); 3150 } 3151 3152 3153 static enum ioc_reply 3154 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 3155 { 3156 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 3157 e1000g_peekpoke_t *ppd; 3158 uint64_t mem_va; 3159 uint64_t maxoff; 3160 boolean_t peek; 3161 3162 switch (iocp->ioc_cmd) { 3163 3164 case E1000G_IOC_REG_PEEK: 3165 peek = B_TRUE; 3166 break; 3167 3168 case E1000G_IOC_REG_POKE: 3169 peek = B_FALSE; 3170 break; 3171 3172 deault: 3173 e1000g_DEBUGLOG_1(e1000gp, e1000g_INFO_LEVEL, 3174 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 3175 iocp->ioc_cmd); 3176 return (IOC_INVAL); 3177 } 3178 3179 /* 3180 * Validate format of ioctl 3181 */ 3182 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 3183 return (IOC_INVAL); 3184 if (mp->b_cont == NULL) 3185 return (IOC_INVAL); 3186 3187 ppd = (e1000g_peekpoke_t *)mp->b_cont->b_rptr; 3188 3189 /* 3190 * Validate request parameters 3191 */ 3192 switch (ppd->pp_acc_space) { 3193 3194 default: 3195 e1000g_DEBUGLOG_1(e1000gp, e1000g_INFO_LEVEL, 3196 "e1000g_diag_ioctl: invalid access space 0x%X\n", 3197 ppd->pp_acc_space); 3198 return (IOC_INVAL); 3199 3200 case E1000G_PP_SPACE_REG: 3201 /* 3202 * Memory-mapped I/O space 3203 */ 3204 ASSERT(ppd->pp_acc_size == 4); 3205 if (ppd->pp_acc_size != 4) 3206 return (IOC_INVAL); 3207 3208 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 3209 return (IOC_INVAL); 3210 3211 mem_va = 0; 3212 maxoff = 0x10000; 3213 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 3214 break; 3215 3216 case E1000G_PP_SPACE_E1000G: 3217 /* 3218 * E1000g data structure! 3219 */ 3220 mem_va = (uintptr_t)e1000gp; 3221 maxoff = sizeof (struct e1000g); 3222 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 3223 break; 3224 3225 } 3226 3227 if (ppd->pp_acc_offset >= maxoff) 3228 return (IOC_INVAL); 3229 3230 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 3231 return (IOC_INVAL); 3232 3233 /* 3234 * All OK - go! 3235 */ 3236 ppd->pp_acc_offset += mem_va; 3237 (*ppfn)(e1000gp, ppd); 3238 return (peek ? IOC_REPLY : IOC_ACK); 3239 } 3240 3241 static void 3242 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3243 { 3244 ddi_acc_handle_t handle; 3245 uint32_t *regaddr; 3246 3247 handle = 3248 ((struct e1000g_osdep *)(&e1000gp->Shared)->back)->E1000_handle, 3249 regaddr = 3250 (uint32_t *)((&e1000gp->Shared)->hw_addr + ppd->pp_acc_offset); 3251 3252 ppd->pp_acc_data = ddi_get32(handle, regaddr); 3253 } 3254 3255 static void 3256 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3257 { 3258 ddi_acc_handle_t handle; 3259 uint32_t *regaddr; 3260 uint32_t value; 3261 3262 handle = 3263 ((struct e1000g_osdep *)(&e1000gp->Shared)->back)->E1000_handle, 3264 regaddr = 3265 (uint32_t *)((&e1000gp->Shared)->hw_addr + ppd->pp_acc_offset); 3266 value = (uint32_t)ppd->pp_acc_data; 3267 3268 ddi_put32(handle, regaddr, value); 3269 } 3270 3271 static void 3272 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3273 { 3274 uint64_t value; 3275 void *vaddr; 3276 3277 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 3278 3279 switch (ppd->pp_acc_size) { 3280 case 1: 3281 value = *(uint8_t *)vaddr; 3282 break; 3283 3284 case 2: 3285 value = *(uint16_t *)vaddr; 3286 break; 3287 3288 case 4: 3289 value = *(uint32_t *)vaddr; 3290 break; 3291 3292 case 8: 3293 value = *(uint64_t *)vaddr; 3294 break; 3295 } 3296 3297 e1000g_DEBUGLOG_4(e1000gp, e1000g_INFO_LEVEL, 3298 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 3299 (void *)e1000gp, (void *)ppd, value, vaddr); 3300 3301 ppd->pp_acc_data = value; 3302 } 3303 3304 static void 3305 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3306 { 3307 uint64_t value; 3308 void *vaddr; 3309 3310 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 3311 value = ppd->pp_acc_data; 3312 3313 e1000g_DEBUGLOG_4(e1000gp, e1000g_INFO_LEVEL, 3314 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 3315 (void *)e1000gp, (void *)ppd, value, vaddr); 3316 3317 switch (ppd->pp_acc_size) { 3318 case 1: 3319 *(uint8_t *)vaddr = (uint8_t)value; 3320 break; 3321 3322 case 2: 3323 *(uint16_t *)vaddr = (uint16_t)value; 3324 break; 3325 3326 case 4: 3327 *(uint32_t *)vaddr = (uint32_t)value; 3328 break; 3329 3330 case 8: 3331 *(uint64_t *)vaddr = (uint64_t)value; 3332 break; 3333 } 3334 } 3335 3336 /* 3337 * Loopback Support 3338 */ 3339 static lb_property_t lb_normal = 3340 { normal, "normal", E1000G_LB_NONE }; 3341 static lb_property_t lb_external1000 = 3342 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 3343 static lb_property_t lb_external100 = 3344 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 3345 static lb_property_t lb_external10 = 3346 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 3347 static lb_property_t lb_phy = 3348 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 3349 3350 static enum ioc_reply 3351 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 3352 { 3353 lb_info_sz_t *lbsp; 3354 lb_property_t *lbpp; 3355 struct e1000_hw *hw; 3356 uint32_t *lbmp; 3357 uint32_t size; 3358 uint32_t value; 3359 uint16_t phy_status; 3360 uint16_t phy_ext_status; 3361 3362 hw = &Adapter->Shared; 3363 3364 if (mp->b_cont == NULL) 3365 return (IOC_INVAL); 3366 3367 switch (iocp->ioc_cmd) { 3368 default: 3369 return (IOC_INVAL); 3370 3371 case LB_GET_INFO_SIZE: 3372 size = sizeof (lb_info_sz_t); 3373 if (iocp->ioc_count != size) 3374 return (IOC_INVAL); 3375 3376 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 3377 e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3378 3379 value = sizeof (lb_normal); 3380 if ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3381 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3382 (hw->media_type == e1000_media_type_fiber) || 3383 (hw->media_type == e1000_media_type_internal_serdes)) { 3384 value += sizeof (lb_phy); 3385 switch (hw->mac_type) { 3386 case e1000_82571: 3387 case e1000_82572: 3388 value += sizeof (lb_external1000); 3389 break; 3390 } 3391 } 3392 if ((phy_status & MII_SR_100X_FD_CAPS) || 3393 (phy_status & MII_SR_100T2_FD_CAPS)) 3394 value += sizeof (lb_external100); 3395 if (phy_status & MII_SR_10T_FD_CAPS) 3396 value += sizeof (lb_external10); 3397 3398 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 3399 *lbsp = value; 3400 break; 3401 3402 case LB_GET_INFO: 3403 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 3404 e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3405 3406 value = sizeof (lb_normal); 3407 if ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3408 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3409 (hw->media_type == e1000_media_type_fiber) || 3410 (hw->media_type == e1000_media_type_internal_serdes)) { 3411 value += sizeof (lb_phy); 3412 switch (hw->mac_type) { 3413 case e1000_82571: 3414 case e1000_82572: 3415 value += sizeof (lb_external1000); 3416 break; 3417 } 3418 } 3419 if ((phy_status & MII_SR_100X_FD_CAPS) || 3420 (phy_status & MII_SR_100T2_FD_CAPS)) 3421 value += sizeof (lb_external100); 3422 if (phy_status & MII_SR_10T_FD_CAPS) 3423 value += sizeof (lb_external10); 3424 3425 size = value; 3426 if (iocp->ioc_count != size) 3427 return (IOC_INVAL); 3428 3429 value = 0; 3430 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 3431 lbpp[value++] = lb_normal; 3432 if ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3433 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3434 (hw->media_type == e1000_media_type_fiber) || 3435 (hw->media_type == e1000_media_type_internal_serdes)) { 3436 lbpp[value++] = lb_phy; 3437 switch (hw->mac_type) { 3438 case e1000_82571: 3439 case e1000_82572: 3440 lbpp[value++] = lb_external1000; 3441 break; 3442 } 3443 } 3444 if ((phy_status & MII_SR_100X_FD_CAPS) || 3445 (phy_status & MII_SR_100T2_FD_CAPS)) 3446 lbpp[value++] = lb_external100; 3447 if (phy_status & MII_SR_10T_FD_CAPS) 3448 lbpp[value++] = lb_external10; 3449 break; 3450 3451 case LB_GET_MODE: 3452 size = sizeof (uint32_t); 3453 if (iocp->ioc_count != size) 3454 return (IOC_INVAL); 3455 3456 lbmp = (uint32_t *)mp->b_cont->b_rptr; 3457 *lbmp = Adapter->loopback_mode; 3458 break; 3459 3460 case LB_SET_MODE: 3461 size = 0; 3462 if (iocp->ioc_count != sizeof (uint32_t)) 3463 return (IOC_INVAL); 3464 3465 lbmp = (uint32_t *)mp->b_cont->b_rptr; 3466 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 3467 return (IOC_INVAL); 3468 break; 3469 } 3470 3471 iocp->ioc_count = size; 3472 iocp->ioc_error = 0; 3473 3474 return (IOC_REPLY); 3475 } 3476 3477 static boolean_t 3478 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 3479 { 3480 struct e1000_hw *hw; 3481 #ifndef __sparc 3482 uint32_t reg_rctl; 3483 #endif 3484 int i, times; 3485 3486 if (mode == Adapter->loopback_mode) 3487 return (B_TRUE); 3488 3489 hw = &Adapter->Shared; 3490 times = 0; 3491 3492 again: 3493 switch (mode) { 3494 default: 3495 return (B_FALSE); 3496 3497 case E1000G_LB_NONE: 3498 /* Get original speed and duplex settings */ 3499 e1000g_force_speed_duplex(Adapter); 3500 /* Reset the chip */ 3501 hw->wait_autoneg_complete = B_TRUE; 3502 (void) e1000g_reset(Adapter); 3503 hw->wait_autoneg_complete = B_FALSE; 3504 break; 3505 3506 case E1000G_LB_EXTERNAL_1000: 3507 e1000g_set_external_loopback_1000(Adapter); 3508 break; 3509 3510 case E1000G_LB_EXTERNAL_100: 3511 e1000g_set_external_loopback_100(Adapter); 3512 break; 3513 3514 case E1000G_LB_EXTERNAL_10: 3515 e1000g_set_external_loopback_10(Adapter); 3516 break; 3517 3518 case E1000G_LB_INTERNAL_PHY: 3519 e1000g_set_internal_loopback(Adapter); 3520 break; 3521 } 3522 3523 times++; 3524 3525 switch (mode) { 3526 case E1000G_LB_EXTERNAL_1000: 3527 case E1000G_LB_EXTERNAL_100: 3528 case E1000G_LB_EXTERNAL_10: 3529 case E1000G_LB_INTERNAL_PHY: 3530 #ifndef __sparc 3531 /* Enable the CRC stripping for loopback */ 3532 reg_rctl = E1000_READ_REG(hw, RCTL); 3533 reg_rctl |= E1000_RCTL_SECRC; 3534 E1000_WRITE_REG(hw, RCTL, reg_rctl); 3535 #endif 3536 /* Wait for link up */ 3537 for (i = (PHY_FORCE_TIME * 2); i > 0; i--) 3538 msec_delay(100); 3539 3540 if (!e1000g_link_up(Adapter)) { 3541 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3542 "Failed to get the link up"); 3543 if (times < 2) { 3544 /* Reset the link */ 3545 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3546 "Reset the link ..."); 3547 (void) e1000g_reset(Adapter); 3548 goto again; 3549 } 3550 } 3551 break; 3552 } 3553 3554 Adapter->loopback_mode = mode; 3555 3556 return (B_TRUE); 3557 } 3558 3559 /* 3560 * The following loopback settings are from Intel's technical 3561 * document - "How To Loopback". All the register settings and 3562 * time delay values are directly inherited from the document 3563 * without more explanations available. 3564 */ 3565 static void 3566 e1000g_set_internal_loopback(struct e1000g *Adapter) 3567 { 3568 struct e1000_hw *hw; 3569 uint32_t ctrl; 3570 uint32_t status; 3571 uint16_t phy_ctrl; 3572 3573 hw = &Adapter->Shared; 3574 3575 /* Disable Smart Power Down */ 3576 phy_spd_state(hw, B_FALSE); 3577 3578 e1000_read_phy_reg(hw, PHY_CTRL, &phy_ctrl); 3579 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 3580 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 3581 3582 switch (hw->mac_type) { 3583 case e1000_82540: 3584 case e1000_82545: 3585 case e1000_82545_rev_3: 3586 case e1000_82546: 3587 case e1000_82546_rev_3: 3588 case e1000_82573: 3589 /* Auto-MDI/MDIX off */ 3590 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 3591 /* Reset PHY to update Auto-MDI/MDIX */ 3592 e1000_write_phy_reg(hw, PHY_CTRL, 3593 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 3594 /* Reset PHY to auto-neg off and force 1000 */ 3595 e1000_write_phy_reg(hw, PHY_CTRL, 3596 phy_ctrl | MII_CR_RESET); 3597 break; 3598 } 3599 3600 /* Set loopback */ 3601 e1000_write_phy_reg(hw, PHY_CTRL, phy_ctrl | MII_CR_LOOPBACK); 3602 3603 msec_delay(250); 3604 3605 /* Now set up the MAC to the same speed/duplex as the PHY. */ 3606 ctrl = E1000_READ_REG(hw, CTRL); 3607 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3608 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3609 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3610 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 3611 E1000_CTRL_FD); /* Force Duplex to FULL */ 3612 3613 switch (hw->mac_type) { 3614 case e1000_82540: 3615 case e1000_82545: 3616 case e1000_82545_rev_3: 3617 case e1000_82546: 3618 case e1000_82546_rev_3: 3619 /* 3620 * For some serdes we'll need to commit the writes now 3621 * so that the status is updated on link 3622 */ 3623 if (hw->media_type == e1000_media_type_internal_serdes) { 3624 E1000_WRITE_REG(hw, CTRL, ctrl); 3625 msec_delay(100); 3626 ctrl = E1000_READ_REG(hw, CTRL); 3627 } 3628 3629 if (hw->media_type == e1000_media_type_copper) { 3630 /* Invert Loss of Signal */ 3631 ctrl |= E1000_CTRL_ILOS; 3632 } else { 3633 /* Set ILOS on fiber nic if half duplex is detected */ 3634 status = E1000_READ_REG(hw, STATUS); 3635 if ((status & E1000_STATUS_FD) == 0) 3636 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3637 } 3638 break; 3639 3640 case e1000_82571: 3641 case e1000_82572: 3642 if (hw->media_type != e1000_media_type_copper) { 3643 /* Set ILOS on fiber nic if half duplex is detected */ 3644 status = E1000_READ_REG(hw, STATUS); 3645 if ((status & E1000_STATUS_FD) == 0) 3646 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3647 } 3648 break; 3649 3650 case e1000_82573: 3651 ctrl |= E1000_CTRL_ILOS; 3652 break; 3653 } 3654 3655 E1000_WRITE_REG(hw, CTRL, ctrl); 3656 3657 /* 3658 * Disable PHY receiver for 82540/545/546 and 82573 Family. 3659 * For background, see comments above e1000g_set_internal_loopback(). 3660 */ 3661 switch (hw->mac_type) { 3662 case e1000_82540: 3663 case e1000_82545: 3664 case e1000_82545_rev_3: 3665 case e1000_82546: 3666 case e1000_82546_rev_3: 3667 case e1000_82573: 3668 e1000_write_phy_reg(hw, 29, 0x001F); 3669 e1000_write_phy_reg(hw, 30, 0x8FFC); 3670 e1000_write_phy_reg(hw, 29, 0x001A); 3671 e1000_write_phy_reg(hw, 30, 0x8FF0); 3672 break; 3673 } 3674 } 3675 3676 static void 3677 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 3678 { 3679 struct e1000_hw *hw; 3680 uint32_t rctl; 3681 uint32_t ctrl_ext; 3682 uint32_t ctrl; 3683 uint32_t status; 3684 uint32_t txcw; 3685 3686 hw = &Adapter->Shared; 3687 3688 /* Disable Smart Power Down */ 3689 phy_spd_state(hw, B_FALSE); 3690 3691 switch (hw->media_type) { 3692 case e1000_media_type_copper: 3693 /* Force link up (Must be done before the PHY writes) */ 3694 ctrl = E1000_READ_REG(hw, CTRL); 3695 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 3696 E1000_WRITE_REG(hw, CTRL, ctrl); 3697 3698 rctl = E1000_READ_REG(hw, RCTL); 3699 rctl |= (E1000_RCTL_EN | 3700 E1000_RCTL_SBP | 3701 E1000_RCTL_UPE | 3702 E1000_RCTL_MPE | 3703 E1000_RCTL_LPE | 3704 E1000_RCTL_BAM); /* 0x803E */ 3705 E1000_WRITE_REG(hw, RCTL, rctl); 3706 3707 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 3708 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 3709 E1000_CTRL_EXT_SDP6_DATA | 3710 E1000_CTRL_EXT_SDP7_DATA | 3711 E1000_CTRL_EXT_SDP4_DIR | 3712 E1000_CTRL_EXT_SDP6_DIR | 3713 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 3714 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 3715 3716 /* 3717 * This sequence tunes the PHY's SDP and no customer 3718 * settable values. For background, see comments above 3719 * e1000g_set_internal_loopback(). 3720 */ 3721 e1000_write_phy_reg(hw, 0x0, 0x140); 3722 msec_delay(10); 3723 e1000_write_phy_reg(hw, 0x9, 0x1A00); 3724 e1000_write_phy_reg(hw, 0x12, 0xC10); 3725 e1000_write_phy_reg(hw, 0x12, 0x1C10); 3726 e1000_write_phy_reg(hw, 0x1F37, 0x76); 3727 e1000_write_phy_reg(hw, 0x1F33, 0x1); 3728 e1000_write_phy_reg(hw, 0x1F33, 0x0); 3729 3730 e1000_write_phy_reg(hw, 0x1F35, 0x65); 3731 e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 3732 e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 3733 e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 3734 e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 3735 3736 msec_delay(50); 3737 break; 3738 case e1000_media_type_fiber: 3739 case e1000_media_type_internal_serdes: 3740 status = E1000_READ_REG(hw, STATUS); 3741 if (((status & E1000_STATUS_LU) == 0) || 3742 (hw->media_type == e1000_media_type_internal_serdes)) { 3743 ctrl = E1000_READ_REG(hw, CTRL); 3744 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3745 E1000_WRITE_REG(hw, CTRL, ctrl); 3746 } 3747 3748 /* Disable autoneg by setting bit 31 of TXCW to zero */ 3749 txcw = E1000_READ_REG(hw, TXCW); 3750 txcw &= ~((uint32_t)1 << 31); 3751 E1000_WRITE_REG(hw, TXCW, txcw); 3752 3753 /* 3754 * Write 0x410 to Serdes Control register 3755 * to enable Serdes analog loopback 3756 */ 3757 E1000_WRITE_REG(hw, SCTL, 0x0410); 3758 msec_delay(10); 3759 break; 3760 default: 3761 break; 3762 } 3763 } 3764 3765 static void 3766 e1000g_set_external_loopback_100(struct e1000g *Adapter) 3767 { 3768 struct e1000_hw *hw; 3769 uint32_t ctrl; 3770 uint16_t phy_ctrl; 3771 3772 hw = &Adapter->Shared; 3773 3774 /* Disable Smart Power Down */ 3775 phy_spd_state(hw, B_FALSE); 3776 3777 phy_ctrl = (MII_CR_FULL_DUPLEX | 3778 MII_CR_SPEED_100); 3779 3780 /* Force 100/FD, reset PHY */ 3781 e1000_write_phy_reg(hw, PHY_CTRL, 3782 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 3783 msec_delay(10); 3784 3785 /* Force 100/FD */ 3786 e1000_write_phy_reg(hw, PHY_CTRL, 3787 phy_ctrl); /* 0x2100 */ 3788 msec_delay(10); 3789 3790 /* Now setup the MAC to the same speed/duplex as the PHY. */ 3791 ctrl = E1000_READ_REG(hw, CTRL); 3792 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3793 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 3794 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3795 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3796 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 3797 E1000_CTRL_FD); /* Force Duplex to FULL */ 3798 3799 E1000_WRITE_REG(hw, CTRL, ctrl); 3800 } 3801 3802 static void 3803 e1000g_set_external_loopback_10(struct e1000g *Adapter) 3804 { 3805 struct e1000_hw *hw; 3806 uint32_t ctrl; 3807 uint16_t phy_ctrl; 3808 3809 hw = &Adapter->Shared; 3810 3811 /* Disable Smart Power Down */ 3812 phy_spd_state(hw, B_FALSE); 3813 3814 phy_ctrl = (MII_CR_FULL_DUPLEX | 3815 MII_CR_SPEED_10); 3816 3817 /* Force 10/FD, reset PHY */ 3818 e1000_write_phy_reg(hw, PHY_CTRL, 3819 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 3820 msec_delay(10); 3821 3822 /* Force 10/FD */ 3823 e1000_write_phy_reg(hw, PHY_CTRL, 3824 phy_ctrl); /* 0x0100 */ 3825 msec_delay(10); 3826 3827 /* Now setup the MAC to the same speed/duplex as the PHY. */ 3828 ctrl = E1000_READ_REG(hw, CTRL); 3829 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3830 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 3831 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3832 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3833 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 3834 E1000_CTRL_FD); /* Force Duplex to FULL */ 3835 3836 E1000_WRITE_REG(hw, CTRL, ctrl); 3837 } 3838 3839 #ifdef __sparc 3840 static boolean_t 3841 e1000g_find_mac_address(struct e1000g *Adapter) 3842 { 3843 uchar_t *bytes; 3844 struct ether_addr sysaddr; 3845 uint_t nelts; 3846 int err; 3847 boolean_t found = B_FALSE; 3848 3849 /* 3850 * The "vendor's factory-set address" may already have 3851 * been extracted from the chip, but if the property 3852 * "local-mac-address" is set we use that instead. 3853 * 3854 * We check whether it looks like an array of 6 3855 * bytes (which it should, if OBP set it). If we can't 3856 * make sense of it this way, we'll ignore it. 3857 */ 3858 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 3859 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 3860 if (err == DDI_PROP_SUCCESS) { 3861 if (nelts == ETHERADDRL) { 3862 while (nelts--) 3863 Adapter->Shared.mac_addr[nelts] = bytes[nelts]; 3864 found = B_TRUE; 3865 } 3866 ddi_prop_free(bytes); 3867 } 3868 3869 /* 3870 * Look up the OBP property "local-mac-address?". If the user has set 3871 * 'local-mac-address? = false', use "the system address" instead. 3872 */ 3873 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 3874 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 3875 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 3876 if (localetheraddr(NULL, &sysaddr) != 0) { 3877 bcopy(&sysaddr, Adapter->Shared.mac_addr, 3878 ETHERADDRL); 3879 found = B_TRUE; 3880 } 3881 } 3882 ddi_prop_free(bytes); 3883 } 3884 3885 /* 3886 * Finally(!), if there's a valid "mac-address" property (created 3887 * if we netbooted from this interface), we must use this instead 3888 * of any of the above to ensure that the NFS/install server doesn't 3889 * get confused by the address changing as Solaris takes over! 3890 */ 3891 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 3892 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 3893 if (err == DDI_PROP_SUCCESS) { 3894 if (nelts == ETHERADDRL) { 3895 while (nelts--) 3896 Adapter->Shared.mac_addr[nelts] = bytes[nelts]; 3897 found = B_TRUE; 3898 } 3899 ddi_prop_free(bytes); 3900 } 3901 3902 if (found) { 3903 bcopy(Adapter->Shared.mac_addr, Adapter->Shared.perm_mac_addr, 3904 ETHERADDRL); 3905 } 3906 3907 return (found); 3908 } 3909 #endif 3910 3911 static int 3912 e1000g_add_intrs(struct e1000g *Adapter) 3913 { 3914 dev_info_t *devinfo; 3915 int intr_types; 3916 int rc; 3917 3918 devinfo = Adapter->dip; 3919 3920 /* Get supported interrupt types */ 3921 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 3922 3923 if (rc != DDI_SUCCESS) { 3924 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 3925 "Get supported interrupt types failed: %d\n", rc); 3926 return (DDI_FAILURE); 3927 } 3928 3929 /* 3930 * Based on Intel Technical Advisory document (TA-160), there are some 3931 * cases where some older Intel PCI-X NICs may "advertise" to the OS 3932 * that it supports MSI, but in fact has problems. 3933 * So we should only enable MSI for PCI-E NICs and disable MSI for old 3934 * PCI/PCI-X NICs. 3935 */ 3936 if (Adapter->Shared.mac_type < e1000_82571) 3937 Adapter->msi_enabled = B_FALSE; 3938 3939 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enabled) { 3940 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 3941 3942 if (rc != DDI_SUCCESS) { 3943 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3944 "Add MSI failed, trying Legacy interrupts\n"); 3945 } else { 3946 Adapter->intr_type = DDI_INTR_TYPE_MSI; 3947 } 3948 } 3949 3950 if ((Adapter->intr_type == 0) && 3951 (intr_types & DDI_INTR_TYPE_FIXED)) { 3952 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 3953 3954 if (rc != DDI_SUCCESS) { 3955 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3956 "Add Legacy interrupts failed\n"); 3957 return (DDI_FAILURE); 3958 } 3959 3960 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 3961 } 3962 3963 if (Adapter->intr_type == 0) { 3964 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3965 "No interrupts registered\n"); 3966 return (DDI_FAILURE); 3967 } 3968 3969 return (DDI_SUCCESS); 3970 } 3971 3972 /* 3973 * e1000g_intr_add() handles MSI/Legacy interrupts 3974 */ 3975 static int 3976 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 3977 { 3978 dev_info_t *devinfo; 3979 int count, avail, actual; 3980 int x, y, rc, inum = 0; 3981 int flag; 3982 ddi_intr_handler_t *intr_handler; 3983 3984 devinfo = Adapter->dip; 3985 3986 /* get number of interrupts */ 3987 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 3988 if ((rc != DDI_SUCCESS) || (count == 0)) { 3989 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 3990 "Get interrupt number failed. Return: %d, count: %d\n", 3991 rc, count); 3992 return (DDI_FAILURE); 3993 } 3994 3995 /* get number of available interrupts */ 3996 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 3997 if ((rc != DDI_SUCCESS) || (avail == 0)) { 3998 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 3999 "Get interrupt available number failed. " 4000 "Return: %d, available: %d\n", rc, avail); 4001 return (DDI_FAILURE); 4002 } 4003 4004 if (avail < count) { 4005 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 4006 "Interrupts count: %d, available: %d\n", 4007 count, avail); 4008 } 4009 4010 /* Allocate an array of interrupt handles */ 4011 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 4012 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 4013 4014 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 4015 flag = DDI_INTR_ALLOC_NORMAL; 4016 4017 /* call ddi_intr_alloc() */ 4018 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 4019 count, &actual, flag); 4020 4021 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4022 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4023 "Allocate interrupts failed: %d\n", rc); 4024 4025 kmem_free(Adapter->htable, Adapter->intr_size); 4026 return (DDI_FAILURE); 4027 } 4028 4029 if (actual < count) { 4030 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 4031 "Interrupts requested: %d, received: %d\n", 4032 count, actual); 4033 } 4034 4035 Adapter->intr_cnt = actual; 4036 4037 /* Get priority for first msi, assume remaining are all the same */ 4038 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 4039 4040 if (rc != DDI_SUCCESS) { 4041 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4042 "Get interrupt priority failed: %d\n", rc); 4043 4044 /* Free already allocated intr */ 4045 for (y = 0; y < actual; y++) 4046 (void) ddi_intr_free(Adapter->htable[y]); 4047 4048 kmem_free(Adapter->htable, Adapter->intr_size); 4049 return (DDI_FAILURE); 4050 } 4051 4052 /* 4053 * In Legacy Interrupt mode, for PCI-Express adapters, we should 4054 * use the interrupt service routine e1000g_intr_pciexpress() 4055 * to avoid interrupt stealing when sharing interrupt with other 4056 * devices. 4057 */ 4058 if (Adapter->Shared.mac_type < e1000_82571) 4059 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 4060 else 4061 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 4062 4063 /* Call ddi_intr_add_handler() */ 4064 for (x = 0; x < actual; x++) { 4065 rc = ddi_intr_add_handler(Adapter->htable[x], 4066 intr_handler, (caddr_t)Adapter, NULL); 4067 4068 if (rc != DDI_SUCCESS) { 4069 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4070 "Add interrupt handler failed: %d\n", rc); 4071 4072 /* Remove already added handler */ 4073 for (y = 0; y < x; y++) 4074 (void) ddi_intr_remove_handler( 4075 Adapter->htable[y]); 4076 4077 /* Free already allocated intr */ 4078 for (y = 0; y < actual; y++) 4079 (void) ddi_intr_free(Adapter->htable[y]); 4080 4081 kmem_free(Adapter->htable, Adapter->intr_size); 4082 return (DDI_FAILURE); 4083 } 4084 } 4085 4086 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 4087 4088 if (rc != DDI_SUCCESS) { 4089 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4090 "Get interrupt cap failed: %d\n", rc); 4091 4092 /* Free already allocated intr */ 4093 for (y = 0; y < actual; y++) { 4094 (void) ddi_intr_remove_handler(Adapter->htable[y]); 4095 (void) ddi_intr_free(Adapter->htable[y]); 4096 } 4097 4098 kmem_free(Adapter->htable, Adapter->intr_size); 4099 return (DDI_FAILURE); 4100 } 4101 4102 return (DDI_SUCCESS); 4103 } 4104 4105 static int 4106 e1000g_rem_intrs(struct e1000g *Adapter) 4107 { 4108 int x; 4109 int rc; 4110 4111 for (x = 0; x < Adapter->intr_cnt; x++) { 4112 rc = ddi_intr_remove_handler(Adapter->htable[x]); 4113 if (rc != DDI_SUCCESS) { 4114 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4115 "Remove intr handler failed: %d\n", rc); 4116 return (DDI_FAILURE); 4117 } 4118 4119 rc = ddi_intr_free(Adapter->htable[x]); 4120 if (rc != DDI_SUCCESS) { 4121 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4122 "Free intr failed: %d\n", rc); 4123 return (DDI_FAILURE); 4124 } 4125 } 4126 4127 kmem_free(Adapter->htable, Adapter->intr_size); 4128 4129 return (DDI_SUCCESS); 4130 } 4131 4132 static int 4133 e1000g_enable_intrs(struct e1000g *Adapter) 4134 { 4135 int x; 4136 int rc; 4137 4138 /* Enable interrupts */ 4139 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 4140 /* Call ddi_intr_block_enable() for MSI */ 4141 rc = ddi_intr_block_enable(Adapter->htable, 4142 Adapter->intr_cnt); 4143 if (rc != DDI_SUCCESS) { 4144 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4145 "Enable block intr failed: %d\n", rc); 4146 return (DDI_FAILURE); 4147 } 4148 } else { 4149 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 4150 for (x = 0; x < Adapter->intr_cnt; x++) { 4151 rc = ddi_intr_enable(Adapter->htable[x]); 4152 if (rc != DDI_SUCCESS) { 4153 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4154 "Enable intr failed: %d\n", rc); 4155 return (DDI_FAILURE); 4156 } 4157 } 4158 } 4159 4160 return (DDI_SUCCESS); 4161 } 4162 4163 static int 4164 e1000g_disable_intrs(struct e1000g *Adapter) 4165 { 4166 int x; 4167 int rc; 4168 4169 /* Disable all interrupts */ 4170 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 4171 rc = ddi_intr_block_disable(Adapter->htable, 4172 Adapter->intr_cnt); 4173 if (rc != DDI_SUCCESS) { 4174 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4175 "Disable block intr failed: %d\n", rc); 4176 return (DDI_FAILURE); 4177 } 4178 } else { 4179 for (x = 0; x < Adapter->intr_cnt; x++) { 4180 rc = ddi_intr_disable(Adapter->htable[x]); 4181 if (rc != DDI_SUCCESS) { 4182 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4183 "Disable intr failed: %d\n", rc); 4184 return (DDI_FAILURE); 4185 } 4186 } 4187 } 4188 4189 return (DDI_SUCCESS); 4190 } 4191 4192 /* 4193 * phy_spd_state - set smart-power-down (SPD) state 4194 * 4195 * This only acts on the 82541/47 family and the 82571/72 family. 4196 * For any others, return without doing anything. 4197 */ 4198 void 4199 phy_spd_state(struct e1000_hw *hw, boolean_t enable) 4200 { 4201 int32_t offset; /* offset to register */ 4202 uint16_t spd_bit; /* bit to be set */ 4203 uint16_t reg; /* register contents */ 4204 4205 switch (hw->mac_type) { 4206 case e1000_82541: 4207 case e1000_82547: 4208 case e1000_82541_rev_2: 4209 case e1000_82547_rev_2: 4210 offset = IGP01E1000_GMII_FIFO; 4211 spd_bit = IGP01E1000_GMII_SPD; 4212 break; 4213 case e1000_82571: 4214 case e1000_82572: 4215 offset = IGP02E1000_PHY_POWER_MGMT; 4216 spd_bit = IGP02E1000_PM_SPD; 4217 break; 4218 default: 4219 return; /* no action */ 4220 } 4221 4222 e1000_read_phy_reg(hw, offset, ®); 4223 4224 if (enable) 4225 reg |= spd_bit; /* enable: set the spd bit */ 4226 else 4227 reg &= ~spd_bit; /* disable: clear the spd bit */ 4228 4229 e1000_write_phy_reg(hw, offset, reg); 4230 } 4231 4232 /* 4233 * The real intent of this routine is to return the value from pci-e 4234 * config space at offset reg into the capability space. 4235 * ICH devices are "PCI Express"-ish. They have a configuration space, 4236 * but do not contain PCI Express Capability registers, so this returns 4237 * the equivalent of "not supported" 4238 */ 4239 int32_t 4240 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 4241 { 4242 *value = pci_config_get16(((struct e1000g_osdep *)hw->back)->handle, 4243 PCI_EX_CONF_CAP + reg); 4244 4245 return (0); 4246 } 4247 4248 /* 4249 * Enables PCI-Express master access. 4250 * 4251 * hw: Struct containing variables accessed by shared code 4252 * 4253 * returns: - none. 4254 */ 4255 void 4256 e1000_enable_pciex_master(struct e1000_hw *hw) 4257 { 4258 uint32_t ctrl; 4259 4260 if (hw->bus_type != e1000_bus_type_pci_express) 4261 return; 4262 4263 ctrl = E1000_READ_REG(hw, CTRL); 4264 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; 4265 E1000_WRITE_REG(hw, CTRL, ctrl); 4266 } 4267