1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * ********************************************************************** 30 * * 31 * Module Name: * 32 * e1000g_main.c * 33 * * 34 * Abstract: * 35 * This file contains the interface routines for the solaris OS. * 36 * It has all DDI entry point routines and GLD entry point routines. * 37 * * 38 * This file also contains routines that take care of initialization * 39 * uninit routine and interrupt routine. * 40 * * 41 * ********************************************************************** 42 */ 43 44 #include <sys/dlpi.h> 45 #include <sys/mac.h> 46 #include <sys/dld.h> 47 #include "e1000g_sw.h" 48 #include "e1000g_debug.h" 49 50 static char ident[] = "Intel PRO/1000 Ethernet 5.2.8"; 51 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 52 static char e1000g_version[] = "Driver Ver. 5.2.8"; 53 54 /* 55 * Proto types for DDI entry points 56 */ 57 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 58 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 59 60 /* 61 * init and intr routines prototype 62 */ 63 static int e1000g_resume(dev_info_t *); 64 static int e1000g_suspend(dev_info_t *); 65 static uint_t e1000g_intr_pciexpress(caddr_t); 66 static uint_t e1000g_intr(caddr_t); 67 static void e1000g_intr_work(struct e1000g *, uint32_t); 68 #pragma inline(e1000g_intr_work) 69 static uint32_t e1000g_get_itr(uint32_t, uint32_t, uint32_t); 70 #pragma inline(e1000g_get_itr) 71 static int e1000g_init(struct e1000g *); 72 static int e1000g_start(struct e1000g *, boolean_t); 73 static void e1000g_stop(struct e1000g *, boolean_t); 74 static int e1000g_m_start(void *); 75 static void e1000g_m_stop(void *); 76 static int e1000g_m_promisc(void *, boolean_t); 77 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 78 static int e1000g_m_unicst(void *, const uint8_t *); 79 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 80 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 81 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 82 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 83 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 84 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 85 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 86 uint_t, const void *); 87 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 88 uint_t, uint_t, void *); 89 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 90 const void *); 91 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 92 uint_t, void *); 93 static void e1000g_init_locks(struct e1000g *); 94 static void e1000g_destroy_locks(struct e1000g *); 95 static int e1000g_identify_hardware(struct e1000g *); 96 static int e1000g_regs_map(struct e1000g *); 97 static int e1000g_set_driver_params(struct e1000g *); 98 static void e1000g_set_bufsize(struct e1000g *); 99 static int e1000g_register_mac(struct e1000g *); 100 static boolean_t e1000g_rx_drain(struct e1000g *); 101 static boolean_t e1000g_tx_drain(struct e1000g *); 102 static void e1000g_init_unicst(struct e1000g *); 103 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 104 105 /* 106 * Local routines 107 */ 108 static void e1000g_tx_clean(struct e1000g *); 109 static void e1000g_rx_clean(struct e1000g *); 110 static void e1000g_link_timer(void *); 111 static void e1000g_local_timer(void *); 112 static boolean_t e1000g_link_check(struct e1000g *); 113 static boolean_t e1000g_stall_check(struct e1000g *); 114 static void e1000g_smartspeed(struct e1000g *); 115 static void e1000g_get_conf(struct e1000g *); 116 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 117 static void enable_watchdog_timer(struct e1000g *); 118 static void disable_watchdog_timer(struct e1000g *); 119 static void start_watchdog_timer(struct e1000g *); 120 static void restart_watchdog_timer(struct e1000g *); 121 static void stop_watchdog_timer(struct e1000g *); 122 static void stop_link_timer(struct e1000g *); 123 static void stop_82547_timer(e1000g_tx_ring_t *); 124 static void e1000g_force_speed_duplex(struct e1000g *); 125 static void e1000g_get_max_frame_size(struct e1000g *); 126 static boolean_t is_valid_mac_addr(uint8_t *); 127 static void e1000g_unattach(dev_info_t *, struct e1000g *); 128 #ifdef E1000G_DEBUG 129 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 130 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 131 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 132 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 133 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 134 struct iocblk *, mblk_t *); 135 #endif 136 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 137 struct iocblk *, mblk_t *); 138 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 139 static void e1000g_set_internal_loopback(struct e1000g *); 140 static void e1000g_set_external_loopback_1000(struct e1000g *); 141 static void e1000g_set_external_loopback_100(struct e1000g *); 142 static void e1000g_set_external_loopback_10(struct e1000g *); 143 static int e1000g_add_intrs(struct e1000g *); 144 static int e1000g_intr_add(struct e1000g *, int); 145 static int e1000g_rem_intrs(struct e1000g *); 146 static int e1000g_enable_intrs(struct e1000g *); 147 static int e1000g_disable_intrs(struct e1000g *); 148 static boolean_t e1000g_link_up(struct e1000g *); 149 #ifdef __sparc 150 static boolean_t e1000g_find_mac_address(struct e1000g *); 151 #endif 152 static void e1000g_get_phy_state(struct e1000g *); 153 static void e1000g_free_priv_devi_node(struct e1000g *, boolean_t); 154 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 155 const void *impl_data); 156 static void e1000g_fm_init(struct e1000g *Adapter); 157 static void e1000g_fm_fini(struct e1000g *Adapter); 158 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 159 static void e1000g_param_sync(struct e1000g *); 160 161 mac_priv_prop_t e1000g_priv_props[] = { 162 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 163 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 164 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 165 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 166 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 167 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 168 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 169 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 170 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 171 {"_intr_adaptive", MAC_PROP_PERM_RW}, 172 {"_tx_recycle_thresh", MAC_PROP_PERM_RW}, 173 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 174 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 175 {"_tx_recycle_num", MAC_PROP_PERM_RW} 176 }; 177 #define E1000G_MAX_PRIV_PROPS \ 178 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 179 180 181 static struct cb_ops cb_ws_ops = { 182 nulldev, /* cb_open */ 183 nulldev, /* cb_close */ 184 nodev, /* cb_strategy */ 185 nodev, /* cb_print */ 186 nodev, /* cb_dump */ 187 nodev, /* cb_read */ 188 nodev, /* cb_write */ 189 nodev, /* cb_ioctl */ 190 nodev, /* cb_devmap */ 191 nodev, /* cb_mmap */ 192 nodev, /* cb_segmap */ 193 nochpoll, /* cb_chpoll */ 194 ddi_prop_op, /* cb_prop_op */ 195 NULL, /* cb_stream */ 196 D_MP | D_HOTPLUG, /* cb_flag */ 197 CB_REV, /* cb_rev */ 198 nodev, /* cb_aread */ 199 nodev /* cb_awrite */ 200 }; 201 202 static struct dev_ops ws_ops = { 203 DEVO_REV, /* devo_rev */ 204 0, /* devo_refcnt */ 205 NULL, /* devo_getinfo */ 206 nulldev, /* devo_identify */ 207 nulldev, /* devo_probe */ 208 e1000g_attach, /* devo_attach */ 209 e1000g_detach, /* devo_detach */ 210 nodev, /* devo_reset */ 211 &cb_ws_ops, /* devo_cb_ops */ 212 NULL, /* devo_bus_ops */ 213 ddi_power /* devo_power */ 214 }; 215 216 static struct modldrv modldrv = { 217 &mod_driverops, /* Type of module. This one is a driver */ 218 ident, /* Discription string */ 219 &ws_ops, /* driver ops */ 220 }; 221 222 static struct modlinkage modlinkage = { 223 MODREV_1, &modldrv, NULL 224 }; 225 226 /* Access attributes for register mapping */ 227 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 228 DDI_DEVICE_ATTR_V0, 229 DDI_STRUCTURE_LE_ACC, 230 DDI_STRICTORDER_ACC, 231 DDI_FLAGERR_ACC 232 }; 233 234 #define E1000G_M_CALLBACK_FLAGS \ 235 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 236 237 static mac_callbacks_t e1000g_m_callbacks = { 238 E1000G_M_CALLBACK_FLAGS, 239 e1000g_m_stat, 240 e1000g_m_start, 241 e1000g_m_stop, 242 e1000g_m_promisc, 243 e1000g_m_multicst, 244 e1000g_m_unicst, 245 e1000g_m_tx, 246 NULL, 247 e1000g_m_ioctl, 248 e1000g_m_getcapab, 249 NULL, 250 NULL, 251 e1000g_m_setprop, 252 e1000g_m_getprop 253 }; 254 255 /* 256 * Global variables 257 */ 258 uint32_t e1000g_mblks_pending = 0; 259 /* 260 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 261 * Here we maintain a private dev_info list if e1000g_force_detach is 262 * enabled. If we force the driver to detach while there are still some 263 * rx buffers retained in the upper layer, we have to keep a copy of the 264 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 265 * structure will be freed after the driver is detached. However when we 266 * finally free those rx buffers released by the upper layer, we need to 267 * refer to the dev_info to free the dma buffers. So we save a copy of 268 * the dev_info for this purpose. On x86 platform, we assume this copy 269 * of dev_info is always valid, but on SPARC platform, it could be invalid 270 * after the system board level DR operation. For this reason, the global 271 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 272 */ 273 #ifdef __sparc 274 boolean_t e1000g_force_detach = B_FALSE; 275 #else 276 boolean_t e1000g_force_detach = B_TRUE; 277 #endif 278 private_devi_list_t *e1000g_private_devi_list = NULL; 279 280 /* 281 * The rwlock is defined to protect the whole processing of rx recycling 282 * and the rx packets release in detach processing to make them mutually 283 * exclusive. 284 * The rx recycling processes different rx packets in different threads, 285 * so it will be protected with RW_READER and it won't block any other rx 286 * recycling threads. 287 * While the detach processing will be protected with RW_WRITER to make 288 * it mutually exclusive with the rx recycling. 289 */ 290 krwlock_t e1000g_rx_detach_lock; 291 /* 292 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 293 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 294 * If there are many e1000g instances, the system may run out of DVMA 295 * resources during the initialization of the instances, then the flag will 296 * be changed to "USE_DMA". Because different e1000g instances are initialized 297 * in parallel, we need to use this lock to protect the flag. 298 */ 299 krwlock_t e1000g_dma_type_lock; 300 301 302 /* 303 * Loadable module configuration entry points for the driver 304 */ 305 306 /* 307 * _init - module initialization 308 */ 309 int 310 _init(void) 311 { 312 int status; 313 314 mac_init_ops(&ws_ops, WSNAME); 315 status = mod_install(&modlinkage); 316 if (status != DDI_SUCCESS) 317 mac_fini_ops(&ws_ops); 318 else { 319 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 320 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 321 } 322 323 return (status); 324 } 325 326 /* 327 * _fini - module finalization 328 */ 329 int 330 _fini(void) 331 { 332 int status; 333 334 rw_enter(&e1000g_rx_detach_lock, RW_READER); 335 if (e1000g_mblks_pending != 0) { 336 rw_exit(&e1000g_rx_detach_lock); 337 return (EBUSY); 338 } 339 rw_exit(&e1000g_rx_detach_lock); 340 341 status = mod_remove(&modlinkage); 342 if (status == DDI_SUCCESS) { 343 mac_fini_ops(&ws_ops); 344 345 if (e1000g_force_detach) { 346 private_devi_list_t *devi_node; 347 348 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 349 while (e1000g_private_devi_list != NULL) { 350 devi_node = e1000g_private_devi_list; 351 e1000g_private_devi_list = 352 e1000g_private_devi_list->next; 353 354 kmem_free(devi_node->priv_dip, 355 sizeof (struct dev_info)); 356 kmem_free(devi_node, 357 sizeof (private_devi_list_t)); 358 } 359 rw_exit(&e1000g_rx_detach_lock); 360 } 361 362 rw_destroy(&e1000g_rx_detach_lock); 363 rw_destroy(&e1000g_dma_type_lock); 364 } 365 366 return (status); 367 } 368 369 /* 370 * _info - module information 371 */ 372 int 373 _info(struct modinfo *modinfop) 374 { 375 return (mod_info(&modlinkage, modinfop)); 376 } 377 378 /* 379 * e1000g_attach - driver attach 380 * 381 * This function is the device-specific initialization entry 382 * point. This entry point is required and must be written. 383 * The DDI_ATTACH command must be provided in the attach entry 384 * point. When attach() is called with cmd set to DDI_ATTACH, 385 * all normal kernel services (such as kmem_alloc(9F)) are 386 * available for use by the driver. 387 * 388 * The attach() function will be called once for each instance 389 * of the device on the system with cmd set to DDI_ATTACH. 390 * Until attach() succeeds, the only driver entry points which 391 * may be called are open(9E) and getinfo(9E). 392 */ 393 static int 394 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 395 { 396 struct e1000g *Adapter; 397 struct e1000_hw *hw; 398 struct e1000g_osdep *osdep; 399 int instance; 400 401 switch (cmd) { 402 default: 403 e1000g_log(NULL, CE_WARN, 404 "Unsupported command send to e1000g_attach... "); 405 return (DDI_FAILURE); 406 407 case DDI_RESUME: 408 return (e1000g_resume(devinfo)); 409 410 case DDI_ATTACH: 411 break; 412 } 413 414 /* 415 * get device instance number 416 */ 417 instance = ddi_get_instance(devinfo); 418 419 /* 420 * Allocate soft data structure 421 */ 422 Adapter = 423 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 424 425 Adapter->dip = devinfo; 426 Adapter->instance = instance; 427 Adapter->tx_ring->adapter = Adapter; 428 Adapter->rx_ring->adapter = Adapter; 429 430 hw = &Adapter->shared; 431 osdep = &Adapter->osdep; 432 hw->back = osdep; 433 osdep->adapter = Adapter; 434 435 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 436 437 /* 438 * Initialize for fma support 439 */ 440 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 441 0, 0x0f, 442 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 443 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 444 e1000g_fm_init(Adapter); 445 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 446 447 /* 448 * PCI Configure 449 */ 450 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 451 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 452 goto attach_fail; 453 } 454 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 455 456 /* 457 * Setup hardware 458 */ 459 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 460 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 461 goto attach_fail; 462 } 463 464 /* 465 * Map in the device registers. 466 */ 467 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 468 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 469 goto attach_fail; 470 } 471 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 472 473 /* 474 * Initialize driver parameters 475 */ 476 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 477 goto attach_fail; 478 } 479 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 480 481 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 482 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 483 goto attach_fail; 484 } 485 486 /* 487 * Initialize interrupts 488 */ 489 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 490 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 491 goto attach_fail; 492 } 493 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 494 495 /* 496 * Initialize mutex's for this device. 497 * Do this before enabling the interrupt handler and 498 * register the softint to avoid the condition where 499 * interrupt handler can try using uninitialized mutex 500 */ 501 e1000g_init_locks(Adapter); 502 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 503 504 /* 505 * Initialize Driver Counters 506 */ 507 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 508 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 509 goto attach_fail; 510 } 511 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 512 513 /* 514 * Initialize chip hardware and software structures 515 */ 516 if (e1000g_init(Adapter) != DDI_SUCCESS) { 517 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 518 goto attach_fail; 519 } 520 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 521 522 /* 523 * Register the driver to the MAC 524 */ 525 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 526 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 527 goto attach_fail; 528 } 529 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 530 531 /* 532 * Now that mutex locks are initialized, and the chip is also 533 * initialized, enable interrupts. 534 */ 535 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 536 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 537 goto attach_fail; 538 } 539 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 540 541 /* 542 * If e1000g_force_detach is enabled, in global private dip list, 543 * we will create a new entry, which maintains the priv_dip for DR 544 * supports after driver detached. 545 */ 546 if (e1000g_force_detach) { 547 private_devi_list_t *devi_node; 548 549 Adapter->priv_dip = 550 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 551 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 552 sizeof (struct dev_info)); 553 554 devi_node = 555 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 556 557 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 558 devi_node->priv_dip = Adapter->priv_dip; 559 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 560 devi_node->next = e1000g_private_devi_list; 561 e1000g_private_devi_list = devi_node; 562 rw_exit(&e1000g_rx_detach_lock); 563 } 564 565 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 566 567 return (DDI_SUCCESS); 568 569 attach_fail: 570 e1000g_unattach(devinfo, Adapter); 571 return (DDI_FAILURE); 572 } 573 574 static int 575 e1000g_register_mac(struct e1000g *Adapter) 576 { 577 struct e1000_hw *hw = &Adapter->shared; 578 mac_register_t *mac; 579 int err; 580 581 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 582 return (DDI_FAILURE); 583 584 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 585 mac->m_driver = Adapter; 586 mac->m_dip = Adapter->dip; 587 mac->m_src_addr = hw->mac.addr; 588 mac->m_callbacks = &e1000g_m_callbacks; 589 mac->m_min_sdu = 0; 590 mac->m_max_sdu = Adapter->default_mtu; 591 mac->m_margin = VLAN_TAGSZ; 592 mac->m_priv_props = e1000g_priv_props; 593 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 594 595 err = mac_register(mac, &Adapter->mh); 596 mac_free(mac); 597 598 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 599 } 600 601 static int 602 e1000g_identify_hardware(struct e1000g *Adapter) 603 { 604 struct e1000_hw *hw = &Adapter->shared; 605 struct e1000g_osdep *osdep = &Adapter->osdep; 606 607 /* Get the device id */ 608 hw->vendor_id = 609 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 610 hw->device_id = 611 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 612 hw->revision_id = 613 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 614 hw->subsystem_device_id = 615 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 616 hw->subsystem_vendor_id = 617 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 618 619 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 620 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 621 "MAC type could not be set properly."); 622 return (DDI_FAILURE); 623 } 624 625 return (DDI_SUCCESS); 626 } 627 628 static int 629 e1000g_regs_map(struct e1000g *Adapter) 630 { 631 dev_info_t *devinfo = Adapter->dip; 632 struct e1000_hw *hw = &Adapter->shared; 633 struct e1000g_osdep *osdep = &Adapter->osdep; 634 off_t mem_size; 635 636 /* 637 * first get the size of device register to be mapped. The 638 * second parameter is the register we are interested. I our 639 * wiseman 0 is for config registers and 1 is for memory mapped 640 * registers Mem size should have memory mapped region size 641 */ 642 if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { 643 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 644 "ddi_dev_regsize for registers failed"); 645 return (DDI_FAILURE); 646 } 647 648 if ((ddi_regs_map_setup(devinfo, 1, /* register of interest */ 649 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 650 &osdep->reg_handle)) != DDI_SUCCESS) { 651 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 652 "ddi_regs_map_setup for registers failed"); 653 goto regs_map_fail; 654 } 655 656 /* ICH needs to map flash memory */ 657 if (hw->mac.type == e1000_ich8lan || hw->mac.type == e1000_ich9lan) { 658 /* get flash size */ 659 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 660 &mem_size) != DDI_SUCCESS) { 661 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 662 "ddi_dev_regsize for ICH flash failed"); 663 goto regs_map_fail; 664 } 665 666 /* map flash in */ 667 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 668 (caddr_t *)&hw->flash_address, 0, 669 mem_size, &e1000g_regs_acc_attr, 670 &osdep->ich_flash_handle) != DDI_SUCCESS) { 671 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 672 "ddi_regs_map_setup for ICH flash failed"); 673 goto regs_map_fail; 674 } 675 } 676 677 return (DDI_SUCCESS); 678 679 regs_map_fail: 680 if (osdep->reg_handle != NULL) 681 ddi_regs_map_free(&osdep->reg_handle); 682 683 return (DDI_FAILURE); 684 } 685 686 static int 687 e1000g_set_driver_params(struct e1000g *Adapter) 688 { 689 struct e1000_hw *hw; 690 e1000g_tx_ring_t *tx_ring; 691 uint32_t mem_bar, io_bar, bar64; 692 693 hw = &Adapter->shared; 694 695 /* Set MAC type and initialize hardware functions */ 696 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 697 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 698 "Could not setup hardware functions"); 699 return (DDI_FAILURE); 700 } 701 702 /* Get bus information */ 703 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 704 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 705 "Could not get bus information"); 706 return (DDI_FAILURE); 707 } 708 709 /* get mem_base addr */ 710 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 711 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 712 713 /* get io_base addr */ 714 if (hw->mac.type >= e1000_82544) { 715 if (bar64) { 716 /* IO BAR is different for 64 bit BAR mode */ 717 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 718 PCI_CONF_BASE4); 719 } else { 720 /* normal 32-bit BAR mode */ 721 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 722 PCI_CONF_BASE2); 723 } 724 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 725 } else { 726 /* no I/O access for adapters prior to 82544 */ 727 hw->io_base = 0x0; 728 } 729 730 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 731 732 hw->mac.autoneg_failed = B_TRUE; 733 734 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 735 hw->phy.autoneg_wait_to_complete = B_FALSE; 736 737 /* Adaptive IFS related changes */ 738 hw->mac.adaptive_ifs = B_TRUE; 739 740 /* Enable phy init script for IGP phy of 82541/82547 */ 741 if ((hw->mac.type == e1000_82547) || 742 (hw->mac.type == e1000_82541) || 743 (hw->mac.type == e1000_82547_rev_2) || 744 (hw->mac.type == e1000_82541_rev_2)) 745 e1000_init_script_state_82541(hw, B_TRUE); 746 747 /* Enable the TTL workaround for 82541/82547 */ 748 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 749 750 #ifdef __sparc 751 Adapter->strip_crc = B_TRUE; 752 #else 753 Adapter->strip_crc = B_FALSE; 754 #endif 755 756 /* Get conf file properties */ 757 e1000g_get_conf(Adapter); 758 759 /* Get speed/duplex settings in conf file */ 760 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 761 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 762 e1000g_force_speed_duplex(Adapter); 763 764 /* Get Jumbo Frames settings in conf file */ 765 e1000g_get_max_frame_size(Adapter); 766 767 /* Set Rx/Tx buffer size */ 768 e1000g_set_bufsize(Adapter); 769 770 /* Master Latency Timer */ 771 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 772 773 /* copper options */ 774 if (hw->phy.media_type == e1000_media_type_copper) { 775 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 776 hw->phy.disable_polarity_correction = B_FALSE; 777 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 778 } 779 780 /* The initial link state should be "unknown" */ 781 Adapter->link_state = LINK_STATE_UNKNOWN; 782 783 /* Initialize rx parameters */ 784 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 785 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 786 787 /* Initialize tx parameters */ 788 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 789 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 790 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 791 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 792 793 tx_ring = Adapter->tx_ring; 794 tx_ring->frags_limit = 795 (Adapter->max_frame_size / Adapter->tx_bcopy_thresh) + 2; 796 if (tx_ring->frags_limit > (MAX_TX_DESC_PER_PACKET >> 1)) 797 tx_ring->frags_limit = (MAX_TX_DESC_PER_PACKET >> 1); 798 799 /* Initialize rx parameters */ 800 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 801 802 return (DDI_SUCCESS); 803 } 804 805 static void 806 e1000g_set_bufsize(struct e1000g *Adapter) 807 { 808 struct e1000_mac_info *mac = &Adapter->shared.mac; 809 uint64_t rx_size; 810 uint64_t tx_size; 811 812 #ifdef __sparc 813 dev_info_t *devinfo = Adapter->dip; 814 ulong_t iommu_pagesize; 815 816 /* Get the system page size */ 817 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 818 iommu_pagesize = dvma_pagesize(devinfo); 819 if (iommu_pagesize != 0) { 820 if (Adapter->sys_page_sz == iommu_pagesize) { 821 if (iommu_pagesize > 0x4000) 822 Adapter->sys_page_sz = 0x4000; 823 } else { 824 if (Adapter->sys_page_sz > iommu_pagesize) 825 Adapter->sys_page_sz = iommu_pagesize; 826 } 827 } 828 Adapter->dvma_page_num = Adapter->max_frame_size / 829 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 830 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 831 #endif 832 833 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 834 835 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 836 if ((rx_size > FRAME_SIZE_UPTO_2K) && (rx_size <= FRAME_SIZE_UPTO_4K)) 837 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 838 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 839 (rx_size <= FRAME_SIZE_UPTO_8K)) 840 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 841 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 842 (rx_size <= FRAME_SIZE_UPTO_16K)) 843 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 844 else 845 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 846 847 tx_size = Adapter->max_frame_size; 848 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 849 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 850 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 851 (tx_size <= FRAME_SIZE_UPTO_8K)) 852 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 853 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 854 (tx_size <= FRAME_SIZE_UPTO_16K)) 855 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 856 else 857 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 858 859 /* 860 * For Wiseman adapters we have an requirement of having receive 861 * buffers aligned at 256 byte boundary. Since Livengood does not 862 * require this and forcing it for all hardwares will have 863 * performance implications, I am making it applicable only for 864 * Wiseman and for Jumbo frames enabled mode as rest of the time, 865 * it is okay to have normal frames...but it does involve a 866 * potential risk where we may loose data if buffer is not 867 * aligned...so all wiseman boards to have 256 byte aligned 868 * buffers 869 */ 870 if (mac->type < e1000_82543) 871 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 872 else 873 Adapter->rx_buf_align = 1; 874 } 875 876 /* 877 * e1000g_detach - driver detach 878 * 879 * The detach() function is the complement of the attach routine. 880 * If cmd is set to DDI_DETACH, detach() is used to remove the 881 * state associated with a given instance of a device node 882 * prior to the removal of that instance from the system. 883 * 884 * The detach() function will be called once for each instance 885 * of the device for which there has been a successful attach() 886 * once there are no longer any opens on the device. 887 * 888 * Interrupts routine are disabled, All memory allocated by this 889 * driver are freed. 890 */ 891 static int 892 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 893 { 894 struct e1000g *Adapter; 895 boolean_t rx_drain; 896 897 switch (cmd) { 898 default: 899 return (DDI_FAILURE); 900 901 case DDI_SUSPEND: 902 return (e1000g_suspend(devinfo)); 903 904 case DDI_DETACH: 905 break; 906 } 907 908 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 909 if (Adapter == NULL) 910 return (DDI_FAILURE); 911 912 if (mac_unregister(Adapter->mh) != 0) { 913 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 914 return (DDI_FAILURE); 915 } 916 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 917 918 919 if (Adapter->chip_state != E1000G_STOP) 920 e1000g_stop(Adapter, B_TRUE); 921 922 rx_drain = e1000g_rx_drain(Adapter); 923 924 /* 925 * If e1000g_force_detach is enabled, driver detach is safe. 926 * We will let e1000g_free_priv_devi_node routine determine 927 * whether we need to free the priv_dip entry for current 928 * driver instance. 929 */ 930 if (e1000g_force_detach) { 931 e1000g_free_priv_devi_node(Adapter, rx_drain); 932 } else { 933 if (!rx_drain) 934 return (DDI_FAILURE); 935 } 936 937 e1000g_unattach(devinfo, Adapter); 938 939 return (DDI_SUCCESS); 940 } 941 942 /* 943 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 944 * 945 * If free_flag is true, that indicates the upper layer is not holding 946 * the rx buffers, we could free the priv_dip entry safely. 947 * 948 * Otherwise, we have to keep this entry even after driver detached, 949 * and we also need to mark this entry with E1000G_PRIV_DEVI_DETACH flag, 950 * so that driver could free it while all of rx buffers are returned 951 * by upper layer later. 952 */ 953 static void 954 e1000g_free_priv_devi_node(struct e1000g *Adapter, boolean_t free_flag) 955 { 956 private_devi_list_t *devi_node, *devi_del; 957 958 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 959 ASSERT(e1000g_private_devi_list != NULL); 960 ASSERT(Adapter->priv_dip != NULL); 961 962 devi_node = e1000g_private_devi_list; 963 if (devi_node->priv_dip == Adapter->priv_dip) { 964 if (free_flag) { 965 e1000g_private_devi_list = 966 devi_node->next; 967 kmem_free(devi_node->priv_dip, 968 sizeof (struct dev_info)); 969 kmem_free(devi_node, 970 sizeof (private_devi_list_t)); 971 } else { 972 ASSERT(e1000g_mblks_pending != 0); 973 devi_node->flag = 974 E1000G_PRIV_DEVI_DETACH; 975 } 976 rw_exit(&e1000g_rx_detach_lock); 977 return; 978 } 979 980 devi_node = e1000g_private_devi_list; 981 while (devi_node->next != NULL) { 982 if (devi_node->next->priv_dip == Adapter->priv_dip) { 983 if (free_flag) { 984 devi_del = devi_node->next; 985 devi_node->next = devi_del->next; 986 kmem_free(devi_del->priv_dip, 987 sizeof (struct dev_info)); 988 kmem_free(devi_del, 989 sizeof (private_devi_list_t)); 990 } else { 991 ASSERT(e1000g_mblks_pending != 0); 992 devi_node->next->flag = 993 E1000G_PRIV_DEVI_DETACH; 994 } 995 break; 996 } 997 devi_node = devi_node->next; 998 } 999 rw_exit(&e1000g_rx_detach_lock); 1000 } 1001 1002 static void 1003 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1004 { 1005 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1006 (void) e1000g_disable_intrs(Adapter); 1007 } 1008 1009 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1010 (void) mac_unregister(Adapter->mh); 1011 } 1012 1013 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1014 (void) e1000g_rem_intrs(Adapter); 1015 } 1016 1017 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1018 (void) ddi_prop_remove_all(devinfo); 1019 } 1020 1021 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1022 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1023 } 1024 1025 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1026 stop_link_timer(Adapter); 1027 if (e1000_reset_hw(&Adapter->shared) != 0) { 1028 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1029 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1030 } 1031 } 1032 1033 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1034 if (Adapter->osdep.reg_handle != NULL) 1035 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1036 if (Adapter->osdep.ich_flash_handle != NULL) 1037 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1038 } 1039 1040 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1041 if (Adapter->osdep.cfg_handle != NULL) 1042 pci_config_teardown(&Adapter->osdep.cfg_handle); 1043 } 1044 1045 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1046 e1000g_destroy_locks(Adapter); 1047 } 1048 1049 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1050 e1000g_fm_fini(Adapter); 1051 } 1052 1053 e1000_remove_device(&Adapter->shared); 1054 1055 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1056 1057 /* 1058 * Another hotplug spec requirement, 1059 * run ddi_set_driver_private(devinfo, null); 1060 */ 1061 ddi_set_driver_private(devinfo, NULL); 1062 } 1063 1064 static void 1065 e1000g_init_locks(struct e1000g *Adapter) 1066 { 1067 e1000g_tx_ring_t *tx_ring; 1068 e1000g_rx_ring_t *rx_ring; 1069 1070 rw_init(&Adapter->chip_lock, NULL, 1071 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1072 mutex_init(&Adapter->link_lock, NULL, 1073 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1074 mutex_init(&Adapter->watchdog_lock, NULL, 1075 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1076 1077 tx_ring = Adapter->tx_ring; 1078 1079 mutex_init(&tx_ring->tx_lock, NULL, 1080 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1081 mutex_init(&tx_ring->usedlist_lock, NULL, 1082 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1083 mutex_init(&tx_ring->freelist_lock, NULL, 1084 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1085 1086 rx_ring = Adapter->rx_ring; 1087 1088 mutex_init(&rx_ring->freelist_lock, NULL, 1089 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1090 } 1091 1092 static void 1093 e1000g_destroy_locks(struct e1000g *Adapter) 1094 { 1095 e1000g_tx_ring_t *tx_ring; 1096 e1000g_rx_ring_t *rx_ring; 1097 1098 tx_ring = Adapter->tx_ring; 1099 mutex_destroy(&tx_ring->tx_lock); 1100 mutex_destroy(&tx_ring->usedlist_lock); 1101 mutex_destroy(&tx_ring->freelist_lock); 1102 1103 rx_ring = Adapter->rx_ring; 1104 mutex_destroy(&rx_ring->freelist_lock); 1105 1106 mutex_destroy(&Adapter->link_lock); 1107 mutex_destroy(&Adapter->watchdog_lock); 1108 rw_destroy(&Adapter->chip_lock); 1109 } 1110 1111 static int 1112 e1000g_resume(dev_info_t *devinfo) 1113 { 1114 struct e1000g *Adapter; 1115 1116 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1117 if (Adapter == NULL) 1118 return (DDI_FAILURE); 1119 1120 if (e1000g_start(Adapter, B_TRUE)) 1121 return (DDI_FAILURE); 1122 1123 return (DDI_SUCCESS); 1124 } 1125 1126 static int 1127 e1000g_suspend(dev_info_t *devinfo) 1128 { 1129 struct e1000g *Adapter; 1130 1131 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1132 if (Adapter == NULL) 1133 return (DDI_FAILURE); 1134 1135 e1000g_stop(Adapter, B_TRUE); 1136 1137 return (DDI_SUCCESS); 1138 } 1139 1140 static int 1141 e1000g_init(struct e1000g *Adapter) 1142 { 1143 uint32_t pba; 1144 uint32_t high_water; 1145 struct e1000_hw *hw; 1146 clock_t link_timeout; 1147 1148 hw = &Adapter->shared; 1149 1150 rw_enter(&Adapter->chip_lock, RW_WRITER); 1151 1152 /* 1153 * reset to put the hardware in a known state 1154 * before we try to do anything with the eeprom 1155 */ 1156 if (e1000_reset_hw(hw) != 0) { 1157 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1158 goto init_fail; 1159 } 1160 1161 if (e1000_validate_nvm_checksum(hw) < 0) { 1162 /* 1163 * Some PCI-E parts fail the first check due to 1164 * the link being in sleep state. Call it again, 1165 * if it fails a second time its a real issue. 1166 */ 1167 if (e1000_validate_nvm_checksum(hw) < 0) { 1168 e1000g_log(Adapter, CE_WARN, 1169 "Invalid NVM checksum. Please contact " 1170 "the vendor to update the NVM."); 1171 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1172 goto init_fail; 1173 } 1174 } 1175 1176 #ifdef __sparc 1177 /* 1178 * Firstly, we try to get the local ethernet address from OBP. If 1179 * fail, we get from EEPROM of NIC card. 1180 */ 1181 if (!e1000g_find_mac_address(Adapter)) { 1182 if (e1000_read_mac_addr(hw) < 0) { 1183 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1184 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1185 goto init_fail; 1186 } 1187 } 1188 #else 1189 /* Get the local ethernet address. */ 1190 if (e1000_read_mac_addr(hw) < 0) { 1191 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1192 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1193 goto init_fail; 1194 } 1195 #endif 1196 1197 /* check for valid mac address */ 1198 if (!is_valid_mac_addr(hw->mac.addr)) { 1199 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1200 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1201 goto init_fail; 1202 } 1203 1204 /* Set LAA state for 82571 chipset */ 1205 e1000_set_laa_state_82571(hw, B_TRUE); 1206 1207 /* Master Latency Timer implementation */ 1208 if (Adapter->master_latency_timer) { 1209 pci_config_put8(Adapter->osdep.cfg_handle, 1210 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1211 } 1212 1213 if (hw->mac.type < e1000_82547) { 1214 /* 1215 * Total FIFO is 64K 1216 */ 1217 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1218 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1219 else 1220 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1221 } else if (hw->mac.type >= e1000_82571 && 1222 hw->mac.type <= e1000_82572) { 1223 /* 1224 * Total FIFO is 48K 1225 */ 1226 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1227 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1228 else 1229 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1230 } else if (hw->mac.type == e1000_ich8lan) { 1231 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1232 } else if (hw->mac.type == e1000_ich9lan) { 1233 pba = E1000_PBA_12K; 1234 } else { 1235 /* 1236 * Total FIFO is 40K 1237 */ 1238 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1239 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1240 else 1241 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1242 } 1243 E1000_WRITE_REG(hw, E1000_PBA, pba); 1244 1245 /* 1246 * These parameters set thresholds for the adapter's generation(Tx) 1247 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1248 * settings. Flow control is enabled or disabled in the configuration 1249 * file. 1250 * High-water mark is set down from the top of the rx fifo (not 1251 * sensitive to max_frame_size) and low-water is set just below 1252 * high-water mark. 1253 * The high water mark must be low enough to fit one full frame above 1254 * it in the rx FIFO. Should be the lower of: 1255 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1256 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1257 * Rx FIFO size minus one full frame. 1258 */ 1259 high_water = min(((pba << 10) * 9 / 10), 1260 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_ich9lan) ? 1261 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1262 ((pba << 10) - Adapter->max_frame_size))); 1263 1264 hw->fc.high_water = high_water & 0xFFF8; 1265 hw->fc.low_water = hw->fc.high_water - 8; 1266 1267 if (hw->mac.type == e1000_80003es2lan) 1268 hw->fc.pause_time = 0xFFFF; 1269 else 1270 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1271 hw->fc.send_xon = B_TRUE; 1272 1273 /* 1274 * Reset the adapter hardware the second time. 1275 */ 1276 if (e1000_reset_hw(hw) != 0) { 1277 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1278 goto init_fail; 1279 } 1280 1281 /* disable wakeup control by default */ 1282 if (hw->mac.type >= e1000_82544) 1283 E1000_WRITE_REG(hw, E1000_WUC, 0); 1284 1285 /* MWI setup */ 1286 e1000_pci_set_mwi(hw); 1287 1288 /* 1289 * Configure/Initialize hardware 1290 */ 1291 if (e1000_init_hw(hw) < 0) { 1292 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1293 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1294 goto init_fail; 1295 } 1296 1297 /* Disable Smart Power Down */ 1298 phy_spd_state(hw, B_FALSE); 1299 1300 /* Make sure driver has control */ 1301 e1000g_get_driver_control(hw); 1302 1303 /* 1304 * Initialize unicast addresses. 1305 */ 1306 e1000g_init_unicst(Adapter); 1307 1308 /* 1309 * Setup and initialize the mctable structures. After this routine 1310 * completes Multicast table will be set 1311 */ 1312 e1000g_setup_multicast(Adapter); 1313 msec_delay(5); 1314 1315 /* 1316 * Implement Adaptive IFS 1317 */ 1318 e1000_reset_adaptive(hw); 1319 1320 /* Setup Interrupt Throttling Register */ 1321 if (hw->mac.type >= e1000_82540) { 1322 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1323 } else 1324 Adapter->intr_adaptive = B_FALSE; 1325 1326 /* Start the timer for link setup */ 1327 if (hw->mac.autoneg) 1328 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1329 else 1330 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1331 1332 mutex_enter(&Adapter->link_lock); 1333 if (hw->phy.autoneg_wait_to_complete) { 1334 Adapter->link_complete = B_TRUE; 1335 } else { 1336 Adapter->link_complete = B_FALSE; 1337 Adapter->link_tid = timeout(e1000g_link_timer, 1338 (void *)Adapter, link_timeout); 1339 } 1340 mutex_exit(&Adapter->link_lock); 1341 1342 /* Enable PCI-Ex master */ 1343 if (hw->bus.type == e1000_bus_type_pci_express) { 1344 e1000_enable_pciex_master(hw); 1345 } 1346 1347 /* Save the state of the phy */ 1348 e1000g_get_phy_state(Adapter); 1349 1350 e1000g_param_sync(Adapter); 1351 1352 Adapter->init_count++; 1353 1354 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1355 goto init_fail; 1356 } 1357 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1358 goto init_fail; 1359 } 1360 1361 rw_exit(&Adapter->chip_lock); 1362 1363 return (DDI_SUCCESS); 1364 1365 init_fail: 1366 rw_exit(&Adapter->chip_lock); 1367 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1368 return (DDI_FAILURE); 1369 } 1370 1371 /* 1372 * Check if the link is up 1373 */ 1374 static boolean_t 1375 e1000g_link_up(struct e1000g *Adapter) 1376 { 1377 struct e1000_hw *hw; 1378 boolean_t link_up; 1379 1380 hw = &Adapter->shared; 1381 1382 e1000_check_for_link(hw); 1383 1384 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1385 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1386 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1387 (hw->mac.serdes_has_link))) { 1388 link_up = B_TRUE; 1389 } else { 1390 link_up = B_FALSE; 1391 } 1392 1393 return (link_up); 1394 } 1395 1396 static void 1397 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1398 { 1399 struct iocblk *iocp; 1400 struct e1000g *e1000gp; 1401 enum ioc_reply status; 1402 int err; 1403 1404 iocp = (struct iocblk *)mp->b_rptr; 1405 iocp->ioc_error = 0; 1406 e1000gp = (struct e1000g *)arg; 1407 1408 ASSERT(e1000gp); 1409 if (e1000gp == NULL) { 1410 miocnak(q, mp, 0, EINVAL); 1411 return; 1412 } 1413 1414 switch (iocp->ioc_cmd) { 1415 1416 case LB_GET_INFO_SIZE: 1417 case LB_GET_INFO: 1418 case LB_GET_MODE: 1419 case LB_SET_MODE: 1420 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1421 break; 1422 1423 1424 #ifdef E1000G_DEBUG 1425 case E1000G_IOC_REG_PEEK: 1426 case E1000G_IOC_REG_POKE: 1427 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1428 break; 1429 case E1000G_IOC_CHIP_RESET: 1430 e1000gp->reset_count++; 1431 if (e1000g_reset(e1000gp)) 1432 status = IOC_ACK; 1433 else 1434 status = IOC_INVAL; 1435 break; 1436 #endif 1437 default: 1438 status = IOC_INVAL; 1439 break; 1440 } 1441 1442 /* 1443 * Decide how to reply 1444 */ 1445 switch (status) { 1446 default: 1447 case IOC_INVAL: 1448 /* 1449 * Error, reply with a NAK and EINVAL or the specified error 1450 */ 1451 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1452 EINVAL : iocp->ioc_error); 1453 break; 1454 1455 case IOC_DONE: 1456 /* 1457 * OK, reply already sent 1458 */ 1459 break; 1460 1461 case IOC_ACK: 1462 /* 1463 * OK, reply with an ACK 1464 */ 1465 miocack(q, mp, 0, 0); 1466 break; 1467 1468 case IOC_REPLY: 1469 /* 1470 * OK, send prepared reply as ACK or NAK 1471 */ 1472 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1473 M_IOCACK : M_IOCNAK; 1474 qreply(q, mp); 1475 break; 1476 } 1477 } 1478 1479 static int 1480 e1000g_m_start(void *arg) 1481 { 1482 struct e1000g *Adapter = (struct e1000g *)arg; 1483 1484 return (e1000g_start(Adapter, B_TRUE)); 1485 } 1486 1487 static int 1488 e1000g_start(struct e1000g *Adapter, boolean_t global) 1489 { 1490 if (global) { 1491 /* Allocate dma resources for descriptors and buffers */ 1492 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1493 e1000g_log(Adapter, CE_WARN, 1494 "Alloc DMA resources failed"); 1495 return (ENOTACTIVE); 1496 } 1497 Adapter->rx_buffer_setup = B_FALSE; 1498 } 1499 1500 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1501 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1502 e1000g_log(Adapter, CE_WARN, 1503 "Adapter initialization failed"); 1504 if (global) 1505 e1000g_release_dma_resources(Adapter); 1506 return (ENOTACTIVE); 1507 } 1508 } 1509 1510 rw_enter(&Adapter->chip_lock, RW_WRITER); 1511 1512 /* Setup and initialize the transmit structures */ 1513 e1000g_tx_setup(Adapter); 1514 msec_delay(5); 1515 1516 /* Setup and initialize the receive structures */ 1517 e1000g_rx_setup(Adapter); 1518 msec_delay(5); 1519 1520 e1000g_mask_interrupt(Adapter); 1521 1522 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1523 rw_exit(&Adapter->chip_lock); 1524 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1525 return (ENOTACTIVE); 1526 } 1527 1528 Adapter->chip_state = E1000G_START; 1529 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1530 1531 rw_exit(&Adapter->chip_lock); 1532 1533 /* Enable and start the watchdog timer */ 1534 enable_watchdog_timer(Adapter); 1535 1536 return (0); 1537 } 1538 1539 static void 1540 e1000g_m_stop(void *arg) 1541 { 1542 struct e1000g *Adapter = (struct e1000g *)arg; 1543 1544 e1000g_stop(Adapter, B_TRUE); 1545 } 1546 1547 static void 1548 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1549 { 1550 /* Set stop flags */ 1551 rw_enter(&Adapter->chip_lock, RW_WRITER); 1552 1553 Adapter->chip_state = E1000G_STOP; 1554 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1555 1556 rw_exit(&Adapter->chip_lock); 1557 1558 /* Drain tx sessions */ 1559 (void) e1000g_tx_drain(Adapter); 1560 1561 /* Disable and stop all the timers */ 1562 disable_watchdog_timer(Adapter); 1563 stop_link_timer(Adapter); 1564 stop_82547_timer(Adapter->tx_ring); 1565 1566 /* Stop the chip and release pending resources */ 1567 rw_enter(&Adapter->chip_lock, RW_WRITER); 1568 1569 e1000g_clear_all_interrupts(Adapter); 1570 if (e1000_reset_hw(&Adapter->shared) != 0) { 1571 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1572 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1573 } 1574 1575 /* Release resources still held by the TX descriptors */ 1576 e1000g_tx_clean(Adapter); 1577 1578 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1579 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1580 1581 /* Clean the pending rx jumbo packet fragment */ 1582 e1000g_rx_clean(Adapter); 1583 1584 rw_exit(&Adapter->chip_lock); 1585 1586 if (global) 1587 e1000g_release_dma_resources(Adapter); 1588 } 1589 1590 static void 1591 e1000g_rx_clean(struct e1000g *Adapter) 1592 { 1593 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 1594 1595 if (rx_ring->rx_mblk != NULL) { 1596 freemsg(rx_ring->rx_mblk); 1597 rx_ring->rx_mblk = NULL; 1598 rx_ring->rx_mblk_tail = NULL; 1599 rx_ring->rx_mblk_len = 0; 1600 } 1601 } 1602 1603 static void 1604 e1000g_tx_clean(struct e1000g *Adapter) 1605 { 1606 e1000g_tx_ring_t *tx_ring; 1607 p_tx_sw_packet_t packet; 1608 mblk_t *mp; 1609 mblk_t *nmp; 1610 uint32_t packet_count; 1611 1612 tx_ring = Adapter->tx_ring; 1613 1614 /* 1615 * Here we don't need to protect the lists using 1616 * the usedlist_lock and freelist_lock, for they 1617 * have been protected by the chip_lock. 1618 */ 1619 mp = NULL; 1620 nmp = NULL; 1621 packet_count = 0; 1622 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1623 while (packet != NULL) { 1624 if (packet->mp != NULL) { 1625 /* Assemble the message chain */ 1626 if (mp == NULL) { 1627 mp = packet->mp; 1628 nmp = packet->mp; 1629 } else { 1630 nmp->b_next = packet->mp; 1631 nmp = packet->mp; 1632 } 1633 /* Disconnect the message from the sw packet */ 1634 packet->mp = NULL; 1635 } 1636 1637 e1000g_free_tx_swpkt(packet); 1638 packet_count++; 1639 1640 packet = (p_tx_sw_packet_t) 1641 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1642 } 1643 1644 if (mp != NULL) 1645 freemsgchain(mp); 1646 1647 if (packet_count > 0) { 1648 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1649 QUEUE_INIT_LIST(&tx_ring->used_list); 1650 1651 /* Setup TX descriptor pointers */ 1652 tx_ring->tbd_next = tx_ring->tbd_first; 1653 tx_ring->tbd_oldest = tx_ring->tbd_first; 1654 1655 /* Setup our HW Tx Head & Tail descriptor pointers */ 1656 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1657 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1658 } 1659 } 1660 1661 static boolean_t 1662 e1000g_tx_drain(struct e1000g *Adapter) 1663 { 1664 int i; 1665 boolean_t done; 1666 e1000g_tx_ring_t *tx_ring; 1667 1668 tx_ring = Adapter->tx_ring; 1669 1670 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1671 for (i = 0; i < TX_DRAIN_TIME; i++) { 1672 mutex_enter(&tx_ring->usedlist_lock); 1673 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1674 mutex_exit(&tx_ring->usedlist_lock); 1675 1676 if (done) 1677 break; 1678 1679 msec_delay(1); 1680 } 1681 1682 return (done); 1683 } 1684 1685 static boolean_t 1686 e1000g_rx_drain(struct e1000g *Adapter) 1687 { 1688 e1000g_rx_ring_t *rx_ring; 1689 p_rx_sw_packet_t packet; 1690 boolean_t done; 1691 1692 rx_ring = Adapter->rx_ring; 1693 done = B_TRUE; 1694 1695 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 1696 1697 while (rx_ring->pending_list != NULL) { 1698 packet = rx_ring->pending_list; 1699 rx_ring->pending_list = 1700 rx_ring->pending_list->next; 1701 1702 if (packet->flag == E1000G_RX_SW_STOP) { 1703 packet->flag = E1000G_RX_SW_DETACH; 1704 done = B_FALSE; 1705 } else { 1706 ASSERT(packet->flag == E1000G_RX_SW_FREE); 1707 ASSERT(packet->mp == NULL); 1708 e1000g_free_rx_sw_packet(packet); 1709 } 1710 } 1711 1712 rw_exit(&e1000g_rx_detach_lock); 1713 1714 return (done); 1715 } 1716 1717 boolean_t 1718 e1000g_reset(struct e1000g *Adapter) 1719 { 1720 e1000g_stop(Adapter, B_FALSE); 1721 1722 if (e1000g_start(Adapter, B_FALSE)) { 1723 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1724 return (B_FALSE); 1725 } 1726 1727 return (B_TRUE); 1728 } 1729 1730 boolean_t 1731 e1000g_global_reset(struct e1000g *Adapter) 1732 { 1733 e1000g_stop(Adapter, B_TRUE); 1734 1735 Adapter->init_count = 0; 1736 1737 if (e1000g_start(Adapter, B_TRUE)) { 1738 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1739 return (B_FALSE); 1740 } 1741 1742 return (B_TRUE); 1743 } 1744 1745 /* 1746 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 1747 * 1748 * This interrupt service routine is for PCI-Express adapters. 1749 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 1750 * bit is set. 1751 */ 1752 static uint_t 1753 e1000g_intr_pciexpress(caddr_t arg) 1754 { 1755 struct e1000g *Adapter; 1756 uint32_t icr; 1757 1758 Adapter = (struct e1000g *)arg; 1759 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1760 1761 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1762 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1763 1764 if (icr & E1000_ICR_INT_ASSERTED) { 1765 /* 1766 * E1000_ICR_INT_ASSERTED bit was set: 1767 * Read(Clear) the ICR, claim this interrupt, 1768 * look for work to do. 1769 */ 1770 e1000g_intr_work(Adapter, icr); 1771 return (DDI_INTR_CLAIMED); 1772 } else { 1773 /* 1774 * E1000_ICR_INT_ASSERTED bit was not set: 1775 * Don't claim this interrupt, return immediately. 1776 */ 1777 return (DDI_INTR_UNCLAIMED); 1778 } 1779 } 1780 1781 /* 1782 * e1000g_intr - ISR for PCI/PCI-X chipsets 1783 * 1784 * This interrupt service routine is for PCI/PCI-X adapters. 1785 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 1786 * bit is set or not. 1787 */ 1788 static uint_t 1789 e1000g_intr(caddr_t arg) 1790 { 1791 struct e1000g *Adapter; 1792 uint32_t icr; 1793 1794 Adapter = (struct e1000g *)arg; 1795 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1796 1797 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1798 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1799 1800 if (icr) { 1801 /* 1802 * Any bit was set in ICR: 1803 * Read(Clear) the ICR, claim this interrupt, 1804 * look for work to do. 1805 */ 1806 e1000g_intr_work(Adapter, icr); 1807 return (DDI_INTR_CLAIMED); 1808 } else { 1809 /* 1810 * No bit was set in ICR: 1811 * Don't claim this interrupt, return immediately. 1812 */ 1813 return (DDI_INTR_UNCLAIMED); 1814 } 1815 } 1816 1817 /* 1818 * e1000g_intr_work - actual processing of ISR 1819 * 1820 * Read(clear) the ICR contents and call appropriate interrupt 1821 * processing routines. 1822 */ 1823 static void 1824 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 1825 { 1826 struct e1000_hw *hw; 1827 hw = &Adapter->shared; 1828 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 1829 uint32_t itr; 1830 1831 Adapter->rx_pkt_cnt = 0; 1832 Adapter->tx_pkt_cnt = 0; 1833 1834 rw_enter(&Adapter->chip_lock, RW_READER); 1835 /* 1836 * Here we need to check the "chip_state" flag within the chip_lock to 1837 * ensure the receive routine will not execute when the adapter is 1838 * being reset. 1839 */ 1840 if (Adapter->chip_state != E1000G_START) { 1841 rw_exit(&Adapter->chip_lock); 1842 return; 1843 } 1844 1845 if (icr & E1000_ICR_RXT0) { 1846 mblk_t *mp; 1847 1848 mutex_enter(&Adapter->rx_ring->rx_lock); 1849 mp = e1000g_receive(Adapter); 1850 mutex_exit(&Adapter->rx_ring->rx_lock); 1851 1852 rw_exit(&Adapter->chip_lock); 1853 1854 if (mp != NULL) 1855 mac_rx(Adapter->mh, Adapter->mrh, mp); 1856 } else 1857 rw_exit(&Adapter->chip_lock); 1858 1859 if (icr & E1000_ICR_TXDW) { 1860 if (!Adapter->tx_intr_enable) 1861 e1000g_clear_tx_interrupt(Adapter); 1862 1863 /* Recycle the tx descriptors */ 1864 rw_enter(&Adapter->chip_lock, RW_READER); 1865 e1000g_recycle(tx_ring); 1866 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 1867 rw_exit(&Adapter->chip_lock); 1868 1869 /* Schedule the re-transmit */ 1870 if (tx_ring->resched_needed && 1871 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 1872 tx_ring->resched_needed = B_FALSE; 1873 mac_tx_update(Adapter->mh); 1874 E1000G_STAT(tx_ring->stat_reschedule); 1875 } 1876 } 1877 1878 if (Adapter->intr_adaptive) { 1879 itr = e1000g_get_itr(Adapter->rx_pkt_cnt, Adapter->tx_pkt_cnt, 1880 Adapter->intr_throttling_rate); 1881 if (itr) { 1882 E1000_WRITE_REG(hw, E1000_ITR, itr); 1883 Adapter->intr_throttling_rate = itr; 1884 } 1885 } 1886 1887 /* 1888 * The Receive Sequence errors RXSEQ and the link status change LSC 1889 * are checked to detect that the cable has been pulled out. For 1890 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1891 * are an indication that cable is not connected. 1892 */ 1893 if ((icr & E1000_ICR_RXSEQ) || 1894 (icr & E1000_ICR_LSC) || 1895 (icr & E1000_ICR_GPI_EN1)) { 1896 boolean_t link_changed; 1897 timeout_id_t tid = 0; 1898 1899 stop_watchdog_timer(Adapter); 1900 1901 rw_enter(&Adapter->chip_lock, RW_WRITER); 1902 1903 /* 1904 * Because we got a link-status-change interrupt, force 1905 * e1000_check_for_link() to look at phy 1906 */ 1907 Adapter->shared.mac.get_link_status = B_TRUE; 1908 1909 /* e1000g_link_check takes care of link status change */ 1910 link_changed = e1000g_link_check(Adapter); 1911 1912 /* Get new phy state */ 1913 e1000g_get_phy_state(Adapter); 1914 1915 /* 1916 * If the link timer has not timed out, we'll not notify 1917 * the upper layer with any link state until the link is up. 1918 */ 1919 if (link_changed && !Adapter->link_complete) { 1920 if (Adapter->link_state == LINK_STATE_UP) { 1921 mutex_enter(&Adapter->link_lock); 1922 Adapter->link_complete = B_TRUE; 1923 tid = Adapter->link_tid; 1924 Adapter->link_tid = 0; 1925 mutex_exit(&Adapter->link_lock); 1926 } else { 1927 link_changed = B_FALSE; 1928 } 1929 } 1930 rw_exit(&Adapter->chip_lock); 1931 1932 if (link_changed) { 1933 if (tid != 0) 1934 (void) untimeout(tid); 1935 1936 /* 1937 * Workaround for esb2. Data stuck in fifo on a link 1938 * down event. Reset the adapter to recover it. 1939 */ 1940 if ((Adapter->link_state == LINK_STATE_DOWN) && 1941 (Adapter->shared.mac.type == e1000_80003es2lan)) 1942 (void) e1000g_reset(Adapter); 1943 1944 mac_link_update(Adapter->mh, Adapter->link_state); 1945 } 1946 1947 start_watchdog_timer(Adapter); 1948 } 1949 } 1950 1951 static uint32_t 1952 e1000g_get_itr(uint32_t rx_packet, uint32_t tx_packet, uint32_t cur_itr) 1953 { 1954 uint32_t new_itr; 1955 1956 /* 1957 * Determine a propper itr according to rx/tx packet count 1958 * per interrupt, the value of itr are based on document 1959 * and testing. 1960 */ 1961 if ((rx_packet < DEFAULT_INTR_PACKET_LOW) || 1962 (tx_packet < DEFAULT_INTR_PACKET_LOW)) { 1963 new_itr = DEFAULT_INTR_THROTTLING_LOW; 1964 goto itr_done; 1965 } 1966 if ((rx_packet > DEFAULT_INTR_PACKET_HIGH) || 1967 (tx_packet > DEFAULT_INTR_PACKET_HIGH)) { 1968 new_itr = DEFAULT_INTR_THROTTLING_LOW; 1969 goto itr_done; 1970 } 1971 if (cur_itr < DEFAULT_INTR_THROTTLING_HIGH) { 1972 new_itr = cur_itr + (DEFAULT_INTR_THROTTLING_HIGH >> 2); 1973 if (new_itr > DEFAULT_INTR_THROTTLING_HIGH) 1974 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 1975 } else 1976 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 1977 1978 itr_done: 1979 if (cur_itr == new_itr) 1980 return (0); 1981 else 1982 return (new_itr); 1983 } 1984 1985 static void 1986 e1000g_init_unicst(struct e1000g *Adapter) 1987 { 1988 struct e1000_hw *hw; 1989 int slot; 1990 1991 hw = &Adapter->shared; 1992 1993 if (!Adapter->unicst_init) { 1994 /* Initialize the multiple unicast addresses */ 1995 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 1996 1997 if ((hw->mac.type == e1000_82571) && 1998 (e1000_get_laa_state_82571(hw) == B_TRUE)) 1999 Adapter->unicst_total--; 2000 2001 Adapter->unicst_avail = Adapter->unicst_total - 1; 2002 2003 /* Store the default mac address */ 2004 e1000_rar_set(hw, hw->mac.addr, 0); 2005 if ((hw->mac.type == e1000_82571) && 2006 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2007 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2008 2009 bcopy(hw->mac.addr, Adapter->unicst_addr[0].mac.addr, 2010 ETHERADDRL); 2011 Adapter->unicst_addr[0].mac.set = 1; 2012 2013 for (slot = 1; slot < Adapter->unicst_total; slot++) 2014 Adapter->unicst_addr[slot].mac.set = 0; 2015 2016 Adapter->unicst_init = B_TRUE; 2017 } else { 2018 /* Recover the default mac address */ 2019 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac.addr, 2020 ETHERADDRL); 2021 2022 /* Store the default mac address */ 2023 e1000_rar_set(hw, hw->mac.addr, 0); 2024 if ((hw->mac.type == e1000_82571) && 2025 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2026 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2027 2028 /* Re-configure the RAR registers */ 2029 for (slot = 1; slot < Adapter->unicst_total; slot++) 2030 e1000_rar_set(hw, 2031 Adapter->unicst_addr[slot].mac.addr, slot); 2032 } 2033 2034 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2035 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2036 } 2037 2038 static int 2039 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 2040 { 2041 struct e1000g *Adapter; 2042 2043 Adapter = (struct e1000g *)arg; 2044 2045 /* Store the default MAC address */ 2046 bcopy(mac_addr, Adapter->shared.mac.addr, ETHERADDRL); 2047 2048 /* Set MAC address in address slot 0, which is the default address */ 2049 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 2050 } 2051 2052 static int 2053 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2054 mac_addr_slot_t slot) 2055 { 2056 struct e1000_hw *hw; 2057 2058 hw = &Adapter->shared; 2059 2060 rw_enter(&Adapter->chip_lock, RW_WRITER); 2061 2062 /* 2063 * The first revision of Wiseman silicon (rev 2.0) has an errata 2064 * that requires the receiver to be in reset when any of the 2065 * receive address registers (RAR regs) are accessed. The first 2066 * rev of Wiseman silicon also requires MWI to be disabled when 2067 * a global reset or a receive reset is issued. So before we 2068 * initialize the RARs, we check the rev of the Wiseman controller 2069 * and work around any necessary HW errata. 2070 */ 2071 if ((hw->mac.type == e1000_82542) && 2072 (hw->revision_id == E1000_REVISION_2)) { 2073 e1000_pci_clear_mwi(hw); 2074 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2075 msec_delay(5); 2076 } 2077 2078 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 2079 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2080 2081 if (slot == 0) { 2082 if ((hw->mac.type == e1000_82571) && 2083 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2084 e1000_rar_set(hw, (uint8_t *)mac_addr, LAST_RAR_ENTRY); 2085 } 2086 2087 /* 2088 * If we are using Wiseman rev 2.0 silicon, we will have previously 2089 * put the receive in reset, and disabled MWI, to work around some 2090 * HW errata. Now we should take the receiver out of reset, and 2091 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2092 */ 2093 if ((hw->mac.type == e1000_82542) && 2094 (hw->revision_id == E1000_REVISION_2)) { 2095 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2096 msec_delay(1); 2097 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2098 e1000_pci_set_mwi(hw); 2099 e1000g_rx_setup(Adapter); 2100 } 2101 2102 rw_exit(&Adapter->chip_lock); 2103 2104 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2105 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2106 return (EIO); 2107 } 2108 2109 return (0); 2110 } 2111 2112 /* 2113 * e1000g_m_unicst_add() - will find an unused address slot, set the 2114 * address value to the one specified, reserve that slot and enable 2115 * the NIC to start filtering on the new MAC address. 2116 * Returns 0 on success. 2117 */ 2118 static int 2119 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 2120 { 2121 struct e1000g *Adapter = (struct e1000g *)arg; 2122 mac_addr_slot_t slot; 2123 int err; 2124 2125 if (mac_unicst_verify(Adapter->mh, 2126 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2127 return (EINVAL); 2128 2129 rw_enter(&Adapter->chip_lock, RW_WRITER); 2130 if (Adapter->unicst_avail == 0) { 2131 /* no slots available */ 2132 rw_exit(&Adapter->chip_lock); 2133 return (ENOSPC); 2134 } 2135 2136 /* 2137 * Primary/default address is in slot 0. The next addresses 2138 * are the multiple MAC addresses. So multiple MAC address 0 2139 * is in slot 1, 1 in slot 2, and so on. So the first multiple 2140 * MAC address resides in slot 1. 2141 */ 2142 for (slot = 1; slot < Adapter->unicst_total; slot++) { 2143 if (Adapter->unicst_addr[slot].mac.set == 0) { 2144 Adapter->unicst_addr[slot].mac.set = 1; 2145 break; 2146 } 2147 } 2148 2149 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 2150 2151 Adapter->unicst_avail--; 2152 rw_exit(&Adapter->chip_lock); 2153 2154 maddr->mma_slot = slot; 2155 2156 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 2157 rw_enter(&Adapter->chip_lock, RW_WRITER); 2158 Adapter->unicst_addr[slot].mac.set = 0; 2159 Adapter->unicst_avail++; 2160 rw_exit(&Adapter->chip_lock); 2161 } 2162 2163 return (err); 2164 } 2165 2166 /* 2167 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 2168 * call to e1000g_m_unicst_add(). The slot number that was returned in 2169 * e1000g_m_unicst_add() is passed in the call to remove the address. 2170 * Returns 0 on success. 2171 */ 2172 static int 2173 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 2174 { 2175 struct e1000g *Adapter = (struct e1000g *)arg; 2176 int err; 2177 2178 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2179 return (EINVAL); 2180 2181 rw_enter(&Adapter->chip_lock, RW_WRITER); 2182 if (Adapter->unicst_addr[slot].mac.set == 1) { 2183 Adapter->unicst_addr[slot].mac.set = 0; 2184 Adapter->unicst_avail++; 2185 rw_exit(&Adapter->chip_lock); 2186 2187 /* Copy the default address to the passed slot */ 2188 if (err = e1000g_unicst_set(Adapter, 2189 Adapter->unicst_addr[0].mac.addr, slot) != 0) { 2190 rw_enter(&Adapter->chip_lock, RW_WRITER); 2191 Adapter->unicst_addr[slot].mac.set = 1; 2192 Adapter->unicst_avail--; 2193 rw_exit(&Adapter->chip_lock); 2194 } 2195 return (err); 2196 } 2197 rw_exit(&Adapter->chip_lock); 2198 2199 return (EINVAL); 2200 } 2201 2202 /* 2203 * e1000g_m_unicst_modify() - modifies the value of an address that 2204 * has been added by e1000g_m_unicst_add(). The new address, address 2205 * length and the slot number that was returned in the call to add 2206 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2207 * set to 0. Returns 0 on success. 2208 */ 2209 static int 2210 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2211 { 2212 struct e1000g *Adapter = (struct e1000g *)arg; 2213 mac_addr_slot_t slot; 2214 2215 if (mac_unicst_verify(Adapter->mh, 2216 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2217 return (EINVAL); 2218 2219 slot = maddr->mma_slot; 2220 2221 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2222 return (EINVAL); 2223 2224 rw_enter(&Adapter->chip_lock, RW_WRITER); 2225 if (Adapter->unicst_addr[slot].mac.set == 1) { 2226 rw_exit(&Adapter->chip_lock); 2227 2228 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2229 } 2230 rw_exit(&Adapter->chip_lock); 2231 2232 return (EINVAL); 2233 } 2234 2235 /* 2236 * e1000g_m_unicst_get() - will get the MAC address and all other 2237 * information related to the address slot passed in mac_multi_addr_t. 2238 * mma_flags should be set to 0 in the call. 2239 * On return, mma_flags can take the following values: 2240 * 1) MMAC_SLOT_UNUSED 2241 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2242 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2243 * 4) MMAC_SLOT_USED 2244 */ 2245 static int 2246 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2247 { 2248 struct e1000g *Adapter = (struct e1000g *)arg; 2249 mac_addr_slot_t slot; 2250 2251 slot = maddr->mma_slot; 2252 2253 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2254 return (EINVAL); 2255 2256 rw_enter(&Adapter->chip_lock, RW_WRITER); 2257 if (Adapter->unicst_addr[slot].mac.set == 1) { 2258 bcopy(Adapter->unicst_addr[slot].mac.addr, 2259 maddr->mma_addr, ETHERADDRL); 2260 maddr->mma_flags = MMAC_SLOT_USED; 2261 } else { 2262 maddr->mma_flags = MMAC_SLOT_UNUSED; 2263 } 2264 rw_exit(&Adapter->chip_lock); 2265 2266 return (0); 2267 } 2268 2269 static int 2270 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2271 { 2272 struct e1000_hw *hw = &Adapter->shared; 2273 unsigned i; 2274 int res = 0; 2275 2276 rw_enter(&Adapter->chip_lock, RW_WRITER); 2277 2278 if ((multiaddr[0] & 01) == 0) { 2279 res = EINVAL; 2280 goto done; 2281 } 2282 2283 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2284 res = ENOENT; 2285 goto done; 2286 } 2287 2288 bcopy(multiaddr, 2289 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2290 Adapter->mcast_count++; 2291 2292 /* 2293 * Update the MC table in the hardware 2294 */ 2295 e1000g_clear_interrupt(Adapter); 2296 2297 e1000g_setup_multicast(Adapter); 2298 2299 if ((hw->mac.type == e1000_82542) && 2300 (hw->revision_id == E1000_REVISION_2)) 2301 e1000g_rx_setup(Adapter); 2302 2303 e1000g_mask_interrupt(Adapter); 2304 2305 done: 2306 rw_exit(&Adapter->chip_lock); 2307 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2308 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2309 res = EIO; 2310 } 2311 2312 return (res); 2313 } 2314 2315 static int 2316 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2317 { 2318 struct e1000_hw *hw = &Adapter->shared; 2319 unsigned i; 2320 2321 rw_enter(&Adapter->chip_lock, RW_WRITER); 2322 2323 for (i = 0; i < Adapter->mcast_count; i++) { 2324 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2325 ETHERADDRL) == 0) { 2326 for (i++; i < Adapter->mcast_count; i++) { 2327 Adapter->mcast_table[i - 1] = 2328 Adapter->mcast_table[i]; 2329 } 2330 Adapter->mcast_count--; 2331 break; 2332 } 2333 } 2334 2335 /* 2336 * Update the MC table in the hardware 2337 */ 2338 e1000g_clear_interrupt(Adapter); 2339 2340 e1000g_setup_multicast(Adapter); 2341 2342 if ((hw->mac.type == e1000_82542) && 2343 (hw->revision_id == E1000_REVISION_2)) 2344 e1000g_rx_setup(Adapter); 2345 2346 e1000g_mask_interrupt(Adapter); 2347 2348 done: 2349 rw_exit(&Adapter->chip_lock); 2350 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2351 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2352 return (EIO); 2353 } 2354 2355 return (0); 2356 } 2357 2358 /* 2359 * e1000g_setup_multicast - setup multicast data structures 2360 * 2361 * This routine initializes all of the multicast related structures. 2362 */ 2363 void 2364 e1000g_setup_multicast(struct e1000g *Adapter) 2365 { 2366 uint8_t *mc_addr_list; 2367 uint32_t mc_addr_count; 2368 uint32_t rctl; 2369 struct e1000_hw *hw; 2370 2371 hw = &Adapter->shared; 2372 2373 /* 2374 * The e1000g has the ability to do perfect filtering of 16 2375 * addresses. The driver uses one of the e1000g's 16 receive 2376 * address registers for its node/network/mac/individual address. 2377 * So, we have room for up to 15 multicast addresses in the CAM, 2378 * additional MC addresses are handled by the MTA (Multicast Table 2379 * Array) 2380 */ 2381 2382 rctl = E1000_READ_REG(hw, E1000_RCTL); 2383 2384 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2385 2386 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2387 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2388 "Adapter requested more than %d MC Addresses.\n", 2389 MAX_NUM_MULTICAST_ADDRESSES); 2390 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2391 } else { 2392 /* 2393 * Set the number of MC addresses that we are being 2394 * requested to use 2395 */ 2396 mc_addr_count = Adapter->mcast_count; 2397 } 2398 /* 2399 * The Wiseman 2.0 silicon has an errata by which the receiver will 2400 * hang while writing to the receive address registers if the receiver 2401 * is not in reset before writing to the registers. Updating the RAR 2402 * is done during the setting up of the multicast table, hence the 2403 * receiver has to be put in reset before updating the multicast table 2404 * and then taken out of reset at the end 2405 */ 2406 /* 2407 * if WMI was enabled then dis able it before issueing the global 2408 * reset to the hardware. 2409 */ 2410 /* 2411 * Only required for WISEMAN_2_0 2412 */ 2413 if ((hw->mac.type == e1000_82542) && 2414 (hw->revision_id == E1000_REVISION_2)) { 2415 e1000_pci_clear_mwi(hw); 2416 /* 2417 * The e1000g must be in reset before changing any RA 2418 * registers. Reset receive unit. The chip will remain in 2419 * the reset state until software explicitly restarts it. 2420 */ 2421 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2422 /* Allow receiver time to go in to reset */ 2423 msec_delay(5); 2424 } 2425 2426 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2427 Adapter->unicst_total, hw->mac.rar_entry_count); 2428 2429 /* 2430 * Only for Wiseman_2_0 2431 * If MWI was enabled then re-enable it after issueing (as we 2432 * disabled it up there) the receive reset command. 2433 * Wainwright does not have a receive reset command and only thing 2434 * close to it is global reset which will require tx setup also 2435 */ 2436 if ((hw->mac.type == e1000_82542) && 2437 (hw->revision_id == E1000_REVISION_2)) { 2438 /* 2439 * if WMI was enabled then reenable it after issueing the 2440 * global or receive reset to the hardware. 2441 */ 2442 2443 /* 2444 * Take receiver out of reset 2445 * clear E1000_RCTL_RST bit (and all others) 2446 */ 2447 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2448 msec_delay(5); 2449 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2450 e1000_pci_set_mwi(hw); 2451 } 2452 2453 /* 2454 * Restore original value 2455 */ 2456 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2457 } 2458 2459 int 2460 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2461 { 2462 struct e1000g *Adapter = (struct e1000g *)arg; 2463 2464 return ((add) ? multicst_add(Adapter, addr) 2465 : multicst_remove(Adapter, addr)); 2466 } 2467 2468 int 2469 e1000g_m_promisc(void *arg, boolean_t on) 2470 { 2471 struct e1000g *Adapter = (struct e1000g *)arg; 2472 uint32_t rctl; 2473 2474 rw_enter(&Adapter->chip_lock, RW_WRITER); 2475 2476 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2477 2478 if (on) 2479 rctl |= 2480 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2481 else 2482 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2483 2484 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2485 2486 Adapter->e1000g_promisc = on; 2487 2488 rw_exit(&Adapter->chip_lock); 2489 2490 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2491 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2492 return (EIO); 2493 } 2494 2495 return (0); 2496 } 2497 2498 static boolean_t 2499 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2500 { 2501 struct e1000g *Adapter = (struct e1000g *)arg; 2502 struct e1000_hw *hw = &Adapter->shared; 2503 2504 switch (cap) { 2505 case MAC_CAPAB_HCKSUM: { 2506 uint32_t *txflags = cap_data; 2507 /* 2508 * Checksum on/off selection via global parameters. 2509 * 2510 * If the chip is flagged as not capable of (correctly) 2511 * handling checksumming, we don't enable it on either 2512 * Rx or Tx side. Otherwise, we take this chip's settings 2513 * from the patchable global defaults. 2514 * 2515 * We advertise our capabilities only if TX offload is 2516 * enabled. On receive, the stack will accept checksummed 2517 * packets anyway, even if we haven't said we can deliver 2518 * them. 2519 */ 2520 switch (hw->mac.type) { 2521 case e1000_82540: 2522 case e1000_82544: 2523 case e1000_82545: 2524 case e1000_82545_rev_3: 2525 case e1000_82546: 2526 case e1000_82546_rev_3: 2527 case e1000_82571: 2528 case e1000_82572: 2529 case e1000_82573: 2530 case e1000_80003es2lan: 2531 if (Adapter->tx_hcksum_enabled) 2532 *txflags = HCKSUM_IPHDRCKSUM | 2533 HCKSUM_INET_PARTIAL; 2534 else 2535 return (B_FALSE); 2536 break; 2537 2538 /* 2539 * For the following Intel PRO/1000 chipsets, we have not 2540 * tested the hardware checksum offload capability, so we 2541 * disable the capability for them. 2542 * e1000_82542, 2543 * e1000_82543, 2544 * e1000_82541, 2545 * e1000_82541_rev_2, 2546 * e1000_82547, 2547 * e1000_82547_rev_2, 2548 */ 2549 default: 2550 return (B_FALSE); 2551 } 2552 2553 break; 2554 } 2555 case MAC_CAPAB_POLL: 2556 /* 2557 * There's nothing for us to fill in, simply returning 2558 * B_TRUE stating that we support polling is sufficient. 2559 */ 2560 break; 2561 2562 case MAC_CAPAB_MULTIADDRESS: { 2563 multiaddress_capab_t *mmacp = cap_data; 2564 2565 /* 2566 * The number of MAC addresses made available by 2567 * this capability is one less than the total as 2568 * the primary address in slot 0 is counted in 2569 * the total. 2570 */ 2571 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2572 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2573 /* No multiple factory addresses, set mma_flag to 0 */ 2574 mmacp->maddr_flag = 0; 2575 mmacp->maddr_handle = Adapter; 2576 mmacp->maddr_add = e1000g_m_unicst_add; 2577 mmacp->maddr_remove = e1000g_m_unicst_remove; 2578 mmacp->maddr_modify = e1000g_m_unicst_modify; 2579 mmacp->maddr_get = e1000g_m_unicst_get; 2580 mmacp->maddr_reserve = NULL; 2581 break; 2582 } 2583 default: 2584 return (B_FALSE); 2585 } 2586 return (B_TRUE); 2587 } 2588 2589 static boolean_t 2590 e1000g_param_locked(mac_prop_id_t pr_num) 2591 { 2592 /* 2593 * All en_* parameters are locked (read-only) while 2594 * the device is in any sort of loopback mode ... 2595 */ 2596 switch (pr_num) { 2597 case DLD_PROP_EN_1000FDX_CAP: 2598 case DLD_PROP_EN_1000HDX_CAP: 2599 case DLD_PROP_EN_100FDX_CAP: 2600 case DLD_PROP_EN_100HDX_CAP: 2601 case DLD_PROP_EN_10FDX_CAP: 2602 case DLD_PROP_EN_10HDX_CAP: 2603 case DLD_PROP_AUTONEG: 2604 case DLD_PROP_FLOWCTRL: 2605 return (B_TRUE); 2606 } 2607 return (B_FALSE); 2608 } 2609 2610 /* 2611 * callback function for set/get of properties 2612 */ 2613 static int 2614 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2615 uint_t pr_valsize, const void *pr_val) 2616 { 2617 struct e1000g *Adapter = arg; 2618 struct e1000_mac_info *mac = &Adapter->shared.mac; 2619 struct e1000_phy_info *phy = &Adapter->shared.phy; 2620 struct e1000_fc_info *fc = &Adapter->shared.fc; 2621 e1000g_tx_ring_t *tx_ring; 2622 int err = 0; 2623 link_flowctrl_t flowctrl; 2624 uint32_t cur_mtu, new_mtu; 2625 uint64_t tmp = 0; 2626 2627 rw_enter(&Adapter->chip_lock, RW_WRITER); 2628 if (Adapter->loopback_mode != E1000G_LB_NONE && 2629 e1000g_param_locked(pr_num)) { 2630 /* 2631 * All en_* parameters are locked (read-only) 2632 * while the device is in any sort of loopback mode. 2633 */ 2634 rw_exit(&Adapter->chip_lock); 2635 return (EBUSY); 2636 } 2637 2638 switch (pr_num) { 2639 case DLD_PROP_EN_1000FDX_CAP: 2640 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 2641 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 2642 goto reset; 2643 case DLD_PROP_EN_1000HDX_CAP: 2644 Adapter->param_en_1000hdx = *(uint8_t *)pr_val; 2645 Adapter->param_adv_1000hdx = *(uint8_t *)pr_val; 2646 goto reset; 2647 case DLD_PROP_EN_100FDX_CAP: 2648 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 2649 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 2650 goto reset; 2651 case DLD_PROP_EN_100HDX_CAP: 2652 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 2653 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 2654 goto reset; 2655 case DLD_PROP_EN_10FDX_CAP: 2656 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 2657 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 2658 goto reset; 2659 case DLD_PROP_EN_10HDX_CAP: 2660 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 2661 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 2662 goto reset; 2663 case DLD_PROP_AUTONEG: 2664 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 2665 goto reset; 2666 case DLD_PROP_FLOWCTRL: 2667 fc->send_xon = B_TRUE; 2668 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 2669 2670 switch (flowctrl) { 2671 default: 2672 err = EINVAL; 2673 break; 2674 case LINK_FLOWCTRL_NONE: 2675 fc->type = e1000_fc_none; 2676 break; 2677 case LINK_FLOWCTRL_RX: 2678 fc->type = e1000_fc_rx_pause; 2679 break; 2680 case LINK_FLOWCTRL_TX: 2681 fc->type = e1000_fc_tx_pause; 2682 break; 2683 case LINK_FLOWCTRL_BI: 2684 fc->type = e1000_fc_full; 2685 break; 2686 } 2687 reset: 2688 if (err == 0) { 2689 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 2690 err = EINVAL; 2691 } 2692 break; 2693 case DLD_PROP_ADV_1000FDX_CAP: 2694 case DLD_PROP_ADV_1000HDX_CAP: 2695 case DLD_PROP_ADV_100FDX_CAP: 2696 case DLD_PROP_ADV_100HDX_CAP: 2697 case DLD_PROP_ADV_10FDX_CAP: 2698 case DLD_PROP_ADV_10HDX_CAP: 2699 case DLD_PROP_STATUS: 2700 case DLD_PROP_SPEED: 2701 case DLD_PROP_DUPLEX: 2702 err = ENOTSUP; /* read-only prop. Can't set this. */ 2703 break; 2704 case DLD_PROP_MTU: 2705 cur_mtu = Adapter->default_mtu; 2706 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 2707 if (new_mtu == cur_mtu) { 2708 err = 0; 2709 break; 2710 } 2711 2712 tmp = new_mtu + sizeof (struct ether_vlan_header) + 2713 ETHERFCSL; 2714 if ((tmp < DEFAULT_FRAME_SIZE) || 2715 (tmp > MAXIMUM_FRAME_SIZE)) { 2716 err = EINVAL; 2717 break; 2718 } 2719 2720 /* ich8 doed not support jumbo frames */ 2721 if ((mac->type == e1000_ich8lan) && 2722 (tmp > DEFAULT_FRAME_SIZE)) { 2723 err = EINVAL; 2724 break; 2725 } 2726 /* ich9 does not do jumbo frames on one phy type */ 2727 if ((mac->type == e1000_ich9lan) && 2728 (phy->type == e1000_phy_ife) && 2729 (tmp > DEFAULT_FRAME_SIZE)) { 2730 err = EINVAL; 2731 break; 2732 } 2733 if (Adapter->chip_state != E1000G_STOP) { 2734 err = EBUSY; 2735 break; 2736 } 2737 2738 err = mac_maxsdu_update(Adapter->mh, new_mtu); 2739 if (err == 0) { 2740 Adapter->max_frame_size = tmp; 2741 Adapter->default_mtu = new_mtu; 2742 e1000g_set_bufsize(Adapter); 2743 tx_ring = Adapter->tx_ring; 2744 tx_ring->frags_limit = 2745 (Adapter->max_frame_size / 2746 Adapter->tx_bcopy_thresh) + 2; 2747 if (tx_ring->frags_limit > 2748 (MAX_TX_DESC_PER_PACKET >> 1)) 2749 tx_ring->frags_limit = 2750 (MAX_TX_DESC_PER_PACKET >> 1); 2751 } 2752 break; 2753 case DLD_PROP_PRIVATE: 2754 err = e1000g_set_priv_prop(Adapter, pr_name, 2755 pr_valsize, pr_val); 2756 break; 2757 default: 2758 err = ENOTSUP; 2759 break; 2760 } 2761 rw_exit(&Adapter->chip_lock); 2762 return (err); 2763 } 2764 2765 static int 2766 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2767 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 2768 { 2769 struct e1000g *Adapter = arg; 2770 struct e1000_mac_info *mac = &Adapter->shared.mac; 2771 struct e1000_fc_info *fc = &Adapter->shared.fc; 2772 int err = 0; 2773 link_flowctrl_t flowctrl; 2774 uint64_t tmp = 0; 2775 2776 if (pr_valsize == 0) 2777 return (EINVAL); 2778 2779 bzero(pr_val, pr_valsize); 2780 if ((pr_flags & DLD_DEFAULT) && (pr_num != DLD_PROP_PRIVATE)) { 2781 return (e1000g_get_def_val(Adapter, pr_num, 2782 pr_valsize, pr_val)); 2783 } 2784 2785 switch (pr_num) { 2786 case DLD_PROP_DUPLEX: 2787 if (pr_valsize >= sizeof (link_duplex_t)) { 2788 bcopy(&Adapter->link_duplex, pr_val, 2789 sizeof (link_duplex_t)); 2790 } else 2791 err = EINVAL; 2792 break; 2793 case DLD_PROP_SPEED: 2794 if (pr_valsize >= sizeof (uint64_t)) { 2795 tmp = Adapter->link_speed * 1000000ull; 2796 bcopy(&tmp, pr_val, sizeof (tmp)); 2797 } else 2798 err = EINVAL; 2799 break; 2800 case DLD_PROP_AUTONEG: 2801 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 2802 break; 2803 case DLD_PROP_FLOWCTRL: 2804 if (pr_valsize >= sizeof (link_flowctrl_t)) { 2805 switch (fc->type) { 2806 case e1000_fc_none: 2807 flowctrl = LINK_FLOWCTRL_NONE; 2808 break; 2809 case e1000_fc_rx_pause: 2810 flowctrl = LINK_FLOWCTRL_RX; 2811 break; 2812 case e1000_fc_tx_pause: 2813 flowctrl = LINK_FLOWCTRL_TX; 2814 break; 2815 case e1000_fc_full: 2816 flowctrl = LINK_FLOWCTRL_BI; 2817 break; 2818 } 2819 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 2820 } else 2821 err = EINVAL; 2822 break; 2823 case DLD_PROP_ADV_1000FDX_CAP: 2824 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 2825 break; 2826 case DLD_PROP_EN_1000FDX_CAP: 2827 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 2828 break; 2829 case DLD_PROP_ADV_1000HDX_CAP: 2830 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 2831 break; 2832 case DLD_PROP_EN_1000HDX_CAP: 2833 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 2834 break; 2835 case DLD_PROP_ADV_100FDX_CAP: 2836 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 2837 break; 2838 case DLD_PROP_EN_100FDX_CAP: 2839 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 2840 break; 2841 case DLD_PROP_ADV_100HDX_CAP: 2842 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 2843 break; 2844 case DLD_PROP_EN_100HDX_CAP: 2845 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 2846 break; 2847 case DLD_PROP_ADV_10FDX_CAP: 2848 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 2849 break; 2850 case DLD_PROP_EN_10FDX_CAP: 2851 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 2852 break; 2853 case DLD_PROP_ADV_10HDX_CAP: 2854 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 2855 break; 2856 case DLD_PROP_EN_10HDX_CAP: 2857 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 2858 break; 2859 case DLD_PROP_ADV_100T4_CAP: 2860 case DLD_PROP_EN_100T4_CAP: 2861 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 2862 break; 2863 case DLD_PROP_PRIVATE: 2864 err = e1000g_get_priv_prop(Adapter, pr_name, 2865 pr_flags, pr_valsize, pr_val); 2866 break; 2867 default: 2868 err = ENOTSUP; 2869 break; 2870 } 2871 return (err); 2872 } 2873 2874 /* ARGUSED */ 2875 static int 2876 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 2877 uint_t pr_valsize, const void *pr_val) 2878 { 2879 int err = 0; 2880 long result; 2881 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2882 struct e1000_hw *hw = &Adapter->shared; 2883 2884 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 2885 if (pr_val == NULL) { 2886 err = EINVAL; 2887 return (err); 2888 } 2889 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2890 if (result < MIN_TX_BCOPY_THRESHOLD || 2891 result > MAX_TX_BCOPY_THRESHOLD) 2892 err = EINVAL; 2893 else { 2894 Adapter->tx_bcopy_thresh = (uint32_t)result; 2895 tx_ring->frags_limit = 2896 (Adapter->max_frame_size / 2897 Adapter->tx_bcopy_thresh) + 2; 2898 if (tx_ring->frags_limit > 2899 (MAX_TX_DESC_PER_PACKET >> 1)) 2900 tx_ring->frags_limit = 2901 (MAX_TX_DESC_PER_PACKET >> 1); 2902 } 2903 return (err); 2904 } 2905 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 2906 if (pr_val == NULL) { 2907 err = EINVAL; 2908 return (err); 2909 } 2910 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2911 if (result < 0 || result > 1) 2912 err = EINVAL; 2913 else { 2914 Adapter->tx_intr_enable = (result == 1) ? 2915 B_TRUE: B_FALSE; 2916 if (Adapter->tx_intr_enable) 2917 e1000g_mask_tx_interrupt(Adapter); 2918 else 2919 e1000g_clear_tx_interrupt(Adapter); 2920 if (e1000g_check_acc_handle( 2921 Adapter->osdep.reg_handle) != DDI_FM_OK) 2922 ddi_fm_service_impact(Adapter->dip, 2923 DDI_SERVICE_DEGRADED); 2924 } 2925 return (err); 2926 } 2927 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 2928 if (pr_val == NULL) { 2929 err = EINVAL; 2930 return (err); 2931 } 2932 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2933 if (result < MIN_TX_INTR_DELAY || 2934 result > MAX_TX_INTR_DELAY) 2935 err = EINVAL; 2936 else { 2937 Adapter->tx_intr_delay = (uint32_t)result; 2938 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 2939 if (e1000g_check_acc_handle( 2940 Adapter->osdep.reg_handle) != DDI_FM_OK) 2941 ddi_fm_service_impact(Adapter->dip, 2942 DDI_SERVICE_DEGRADED); 2943 } 2944 return (err); 2945 } 2946 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 2947 if (pr_val == NULL) { 2948 err = EINVAL; 2949 return (err); 2950 } 2951 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2952 if (result < MIN_TX_INTR_ABS_DELAY || 2953 result > MAX_TX_INTR_ABS_DELAY) 2954 err = EINVAL; 2955 else { 2956 Adapter->tx_intr_abs_delay = (uint32_t)result; 2957 E1000_WRITE_REG(hw, E1000_TADV, 2958 Adapter->tx_intr_abs_delay); 2959 if (e1000g_check_acc_handle( 2960 Adapter->osdep.reg_handle) != DDI_FM_OK) 2961 ddi_fm_service_impact(Adapter->dip, 2962 DDI_SERVICE_DEGRADED); 2963 } 2964 return (err); 2965 } 2966 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 2967 if (pr_val == NULL) { 2968 err = EINVAL; 2969 return (err); 2970 } 2971 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2972 if (result < MIN_RX_BCOPY_THRESHOLD || 2973 result > MAX_RX_BCOPY_THRESHOLD) 2974 err = EINVAL; 2975 else 2976 Adapter->rx_bcopy_thresh = (uint32_t)result; 2977 return (err); 2978 } 2979 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 2980 if (pr_val == NULL) { 2981 err = EINVAL; 2982 return (err); 2983 } 2984 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2985 if (result < MIN_RX_LIMIT_ON_INTR || 2986 result > MAX_RX_LIMIT_ON_INTR) 2987 err = EINVAL; 2988 else 2989 Adapter->rx_limit_onintr = (uint32_t)result; 2990 return (err); 2991 } 2992 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 2993 if (pr_val == NULL) { 2994 err = EINVAL; 2995 return (err); 2996 } 2997 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2998 if (result < MIN_RX_INTR_DELAY || 2999 result > MAX_RX_INTR_DELAY) 3000 err = EINVAL; 3001 else { 3002 Adapter->rx_intr_delay = (uint32_t)result; 3003 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3004 if (e1000g_check_acc_handle( 3005 Adapter->osdep.reg_handle) != DDI_FM_OK) 3006 ddi_fm_service_impact(Adapter->dip, 3007 DDI_SERVICE_DEGRADED); 3008 } 3009 return (err); 3010 } 3011 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3012 if (pr_val == NULL) { 3013 err = EINVAL; 3014 return (err); 3015 } 3016 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3017 if (result < MIN_RX_INTR_ABS_DELAY || 3018 result > MAX_RX_INTR_ABS_DELAY) 3019 err = EINVAL; 3020 else { 3021 Adapter->rx_intr_abs_delay = (uint32_t)result; 3022 E1000_WRITE_REG(hw, E1000_RADV, 3023 Adapter->rx_intr_abs_delay); 3024 if (e1000g_check_acc_handle( 3025 Adapter->osdep.reg_handle) != DDI_FM_OK) 3026 ddi_fm_service_impact(Adapter->dip, 3027 DDI_SERVICE_DEGRADED); 3028 } 3029 return (err); 3030 } 3031 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3032 if (pr_val == NULL) { 3033 err = EINVAL; 3034 return (err); 3035 } 3036 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3037 if (result < MIN_INTR_THROTTLING || 3038 result > MAX_INTR_THROTTLING) 3039 err = EINVAL; 3040 else { 3041 if (hw->mac.type >= e1000_82540) { 3042 Adapter->intr_throttling_rate = 3043 (uint32_t)result; 3044 E1000_WRITE_REG(hw, E1000_ITR, 3045 Adapter->intr_throttling_rate); 3046 if (e1000g_check_acc_handle( 3047 Adapter->osdep.reg_handle) != DDI_FM_OK) 3048 ddi_fm_service_impact(Adapter->dip, 3049 DDI_SERVICE_DEGRADED); 3050 } else 3051 err = EINVAL; 3052 } 3053 return (err); 3054 } 3055 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3056 if (pr_val == NULL) { 3057 err = EINVAL; 3058 return (err); 3059 } 3060 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3061 if (result < 0 || result > 1) 3062 err = EINVAL; 3063 else { 3064 if (hw->mac.type >= e1000_82540) { 3065 Adapter->intr_adaptive = (result == 1) ? 3066 B_TRUE : B_FALSE; 3067 } else { 3068 err = EINVAL; 3069 } 3070 } 3071 return (err); 3072 } 3073 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3074 if (pr_val == NULL) { 3075 err = EINVAL; 3076 return (err); 3077 } 3078 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3079 if (result < MIN_TX_RECYCLE_THRESHOLD || 3080 result > MAX_TX_RECYCLE_THRESHOLD) 3081 err = EINVAL; 3082 else 3083 Adapter->tx_recycle_thresh = (uint32_t)result; 3084 return (err); 3085 } 3086 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3087 if (pr_val == NULL) { 3088 err = EINVAL; 3089 return (err); 3090 } 3091 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3092 if (result < MIN_TX_RECYCLE_NUM || 3093 result > MAX_TX_RECYCLE_NUM) 3094 err = EINVAL; 3095 else 3096 Adapter->tx_recycle_num = (uint32_t)result; 3097 return (err); 3098 } 3099 return (ENOTSUP); 3100 } 3101 3102 static int 3103 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3104 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 3105 { 3106 char valstr[MAXNAMELEN]; 3107 int err = ENOTSUP; 3108 uint_t strsize; 3109 boolean_t is_default = (pr_flags & DLD_DEFAULT); 3110 int value; 3111 3112 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3113 if (is_default) 3114 goto done; 3115 value = Adapter->param_adv_pause; 3116 err = 0; 3117 goto done; 3118 } 3119 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3120 if (is_default) 3121 goto done; 3122 value = Adapter->param_adv_asym_pause; 3123 err = 0; 3124 goto done; 3125 } 3126 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3127 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3128 Adapter->tx_bcopy_thresh); 3129 err = 0; 3130 goto done; 3131 } 3132 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3133 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3134 Adapter->tx_intr_enable); 3135 err = 0; 3136 goto done; 3137 } 3138 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3139 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3140 Adapter->tx_intr_delay); 3141 err = 0; 3142 goto done; 3143 } 3144 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3145 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3146 Adapter->tx_intr_abs_delay); 3147 err = 0; 3148 goto done; 3149 } 3150 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3151 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3152 Adapter->rx_bcopy_thresh); 3153 err = 0; 3154 goto done; 3155 } 3156 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3157 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3158 Adapter->rx_limit_onintr); 3159 err = 0; 3160 goto done; 3161 } 3162 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3163 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3164 Adapter->rx_intr_delay); 3165 err = 0; 3166 goto done; 3167 } 3168 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3169 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3170 Adapter->rx_intr_abs_delay); 3171 err = 0; 3172 goto done; 3173 } 3174 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3175 value = (is_default ? DEFAULT_INTR_THROTTLING : 3176 Adapter->intr_throttling_rate); 3177 err = 0; 3178 goto done; 3179 } 3180 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3181 value = (is_default ? 1 : Adapter->intr_adaptive); 3182 err = 0; 3183 goto done; 3184 } 3185 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3186 value = (is_default ? DEFAULT_TX_RECYCLE_THRESHOLD : 3187 Adapter->tx_recycle_thresh); 3188 err = 0; 3189 goto done; 3190 } 3191 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3192 value = (is_default ? DEFAULT_TX_RECYCLE_NUM : 3193 Adapter->tx_recycle_num); 3194 err = 0; 3195 goto done; 3196 } 3197 done: 3198 if (err == 0) { 3199 (void) snprintf(pr_val, pr_valsize, "%d", value); 3200 } 3201 return (err); 3202 } 3203 3204 /* 3205 * e1000g_get_conf - get configurations set in e1000g.conf 3206 * This routine gets user-configured values out of the configuration 3207 * file e1000g.conf. 3208 * 3209 * For each configurable value, there is a minimum, a maximum, and a 3210 * default. 3211 * If user does not configure a value, use the default. 3212 * If user configures below the minimum, use the minumum. 3213 * If user configures above the maximum, use the maxumum. 3214 */ 3215 static void 3216 e1000g_get_conf(struct e1000g *Adapter) 3217 { 3218 struct e1000_hw *hw = &Adapter->shared; 3219 boolean_t tbi_compatibility = B_FALSE; 3220 3221 /* 3222 * get each configurable property from e1000g.conf 3223 */ 3224 3225 /* 3226 * NumTxDescriptors 3227 */ 3228 Adapter->tx_desc_num = 3229 e1000g_get_prop(Adapter, "NumTxDescriptors", 3230 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3231 DEFAULT_NUM_TX_DESCRIPTOR); 3232 3233 /* 3234 * NumRxDescriptors 3235 */ 3236 Adapter->rx_desc_num = 3237 e1000g_get_prop(Adapter, "NumRxDescriptors", 3238 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3239 DEFAULT_NUM_RX_DESCRIPTOR); 3240 3241 /* 3242 * NumRxFreeList 3243 */ 3244 Adapter->rx_freelist_num = 3245 e1000g_get_prop(Adapter, "NumRxFreeList", 3246 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3247 DEFAULT_NUM_RX_FREELIST); 3248 3249 /* 3250 * NumTxPacketList 3251 */ 3252 Adapter->tx_freelist_num = 3253 e1000g_get_prop(Adapter, "NumTxPacketList", 3254 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3255 DEFAULT_NUM_TX_FREELIST); 3256 3257 /* 3258 * FlowControl 3259 */ 3260 hw->fc.send_xon = B_TRUE; 3261 hw->fc.type = 3262 e1000g_get_prop(Adapter, "FlowControl", 3263 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3264 /* 4 is the setting that says "let the eeprom decide" */ 3265 if (hw->fc.type == 4) 3266 hw->fc.type = e1000_fc_default; 3267 3268 /* 3269 * Max Num Receive Packets on Interrupt 3270 */ 3271 Adapter->rx_limit_onintr = 3272 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3273 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3274 DEFAULT_RX_LIMIT_ON_INTR); 3275 3276 /* 3277 * PHY master slave setting 3278 */ 3279 hw->phy.ms_type = 3280 e1000g_get_prop(Adapter, "SetMasterSlave", 3281 e1000_ms_hw_default, e1000_ms_auto, 3282 e1000_ms_hw_default); 3283 3284 /* 3285 * Parameter which controls TBI mode workaround, which is only 3286 * needed on certain switches such as Cisco 6500/Foundry 3287 */ 3288 tbi_compatibility = 3289 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3290 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3291 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3292 3293 /* 3294 * MSI Enable 3295 */ 3296 Adapter->msi_enabled = 3297 e1000g_get_prop(Adapter, "MSIEnable", 3298 0, 1, DEFAULT_MSI_ENABLE); 3299 3300 /* 3301 * Interrupt Throttling Rate 3302 */ 3303 Adapter->intr_throttling_rate = 3304 e1000g_get_prop(Adapter, "intr_throttling_rate", 3305 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3306 DEFAULT_INTR_THROTTLING); 3307 3308 /* 3309 * Adaptive Interrupt Blanking Enable/Disable 3310 * It is enabled by default 3311 */ 3312 Adapter->intr_adaptive = 3313 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3314 B_TRUE : B_FALSE; 3315 3316 /* 3317 * Tx recycle threshold 3318 */ 3319 Adapter->tx_recycle_thresh = 3320 e1000g_get_prop(Adapter, "tx_recycle_thresh", 3321 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 3322 DEFAULT_TX_RECYCLE_THRESHOLD); 3323 3324 /* 3325 * Tx recycle descriptor number 3326 */ 3327 Adapter->tx_recycle_num = 3328 e1000g_get_prop(Adapter, "tx_recycle_num", 3329 MIN_TX_RECYCLE_NUM, MAX_TX_RECYCLE_NUM, 3330 DEFAULT_TX_RECYCLE_NUM); 3331 3332 /* 3333 * Hardware checksum enable/disable parameter 3334 */ 3335 Adapter->tx_hcksum_enabled = 3336 e1000g_get_prop(Adapter, "tx_hcksum_enabled", 3337 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3338 3339 } 3340 3341 /* 3342 * e1000g_get_prop - routine to read properties 3343 * 3344 * Get a user-configure property value out of the configuration 3345 * file e1000g.conf. 3346 * 3347 * Caller provides name of the property, a default value, a minimum 3348 * value, and a maximum value. 3349 * 3350 * Return configured value of the property, with default, minimum and 3351 * maximum properly applied. 3352 */ 3353 static int 3354 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3355 char *propname, /* name of the property */ 3356 int minval, /* minimum acceptable value */ 3357 int maxval, /* maximim acceptable value */ 3358 int defval) /* default value */ 3359 { 3360 int propval; /* value returned for requested property */ 3361 int *props; /* point to array of properties returned */ 3362 uint_t nprops; /* number of property value returned */ 3363 3364 /* 3365 * get the array of properties from the config file 3366 */ 3367 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3368 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3369 /* got some properties, test if we got enough */ 3370 if (Adapter->instance < nprops) { 3371 propval = props[Adapter->instance]; 3372 } else { 3373 /* not enough properties configured */ 3374 propval = defval; 3375 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3376 "Not Enough %s values found in e1000g.conf" 3377 " - set to %d\n", 3378 propname, propval); 3379 } 3380 3381 /* free memory allocated for properties */ 3382 ddi_prop_free(props); 3383 3384 } else { 3385 propval = defval; 3386 } 3387 3388 /* 3389 * enforce limits 3390 */ 3391 if (propval > maxval) { 3392 propval = maxval; 3393 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3394 "Too High %s value in e1000g.conf - set to %d\n", 3395 propname, propval); 3396 } 3397 3398 if (propval < minval) { 3399 propval = minval; 3400 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3401 "Too Low %s value in e1000g.conf - set to %d\n", 3402 propname, propval); 3403 } 3404 3405 return (propval); 3406 } 3407 3408 static boolean_t 3409 e1000g_link_check(struct e1000g *Adapter) 3410 { 3411 uint16_t speed, duplex, phydata; 3412 boolean_t link_changed = B_FALSE; 3413 struct e1000_hw *hw; 3414 uint32_t reg_tarc; 3415 3416 hw = &Adapter->shared; 3417 3418 if (e1000g_link_up(Adapter)) { 3419 /* 3420 * The Link is up, check whether it was marked as down earlier 3421 */ 3422 if (Adapter->link_state != LINK_STATE_UP) { 3423 e1000_get_speed_and_duplex(hw, &speed, &duplex); 3424 Adapter->link_speed = speed; 3425 Adapter->link_duplex = duplex; 3426 Adapter->link_state = LINK_STATE_UP; 3427 link_changed = B_TRUE; 3428 3429 Adapter->tx_link_down_timeout = 0; 3430 3431 if ((hw->mac.type == e1000_82571) || 3432 (hw->mac.type == e1000_82572)) { 3433 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3434 if (speed == SPEED_1000) 3435 reg_tarc |= (1 << 21); 3436 else 3437 reg_tarc &= ~(1 << 21); 3438 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3439 } 3440 } 3441 Adapter->smartspeed = 0; 3442 } else { 3443 if (Adapter->link_state != LINK_STATE_DOWN) { 3444 Adapter->link_speed = 0; 3445 Adapter->link_duplex = 0; 3446 Adapter->link_state = LINK_STATE_DOWN; 3447 link_changed = B_TRUE; 3448 3449 /* 3450 * SmartSpeed workaround for Tabor/TanaX, When the 3451 * driver loses link disable auto master/slave 3452 * resolution. 3453 */ 3454 if (hw->phy.type == e1000_phy_igp) { 3455 e1000_read_phy_reg(hw, 3456 PHY_1000T_CTRL, &phydata); 3457 phydata |= CR_1000T_MS_ENABLE; 3458 e1000_write_phy_reg(hw, 3459 PHY_1000T_CTRL, phydata); 3460 } 3461 } else { 3462 e1000g_smartspeed(Adapter); 3463 } 3464 3465 if (Adapter->chip_state == E1000G_START) { 3466 if (Adapter->tx_link_down_timeout < 3467 MAX_TX_LINK_DOWN_TIMEOUT) { 3468 Adapter->tx_link_down_timeout++; 3469 } else if (Adapter->tx_link_down_timeout == 3470 MAX_TX_LINK_DOWN_TIMEOUT) { 3471 e1000g_tx_clean(Adapter); 3472 Adapter->tx_link_down_timeout++; 3473 } 3474 } 3475 } 3476 3477 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3478 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3479 3480 return (link_changed); 3481 } 3482 3483 /* 3484 * e1000g_reset_link - Using the link properties to setup the link 3485 */ 3486 int 3487 e1000g_reset_link(struct e1000g *Adapter) 3488 { 3489 struct e1000_mac_info *mac; 3490 struct e1000_phy_info *phy; 3491 boolean_t invalid; 3492 3493 mac = &Adapter->shared.mac; 3494 phy = &Adapter->shared.phy; 3495 invalid = B_FALSE; 3496 3497 if (Adapter->param_adv_autoneg == 1) { 3498 mac->autoneg = B_TRUE; 3499 phy->autoneg_advertised = 0; 3500 3501 /* 3502 * 1000hdx is not supported for autonegotiation 3503 */ 3504 if (Adapter->param_adv_1000fdx == 1) 3505 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3506 3507 if (Adapter->param_adv_100fdx == 1) 3508 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3509 3510 if (Adapter->param_adv_100hdx == 1) 3511 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3512 3513 if (Adapter->param_adv_10fdx == 1) 3514 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3515 3516 if (Adapter->param_adv_10hdx == 1) 3517 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3518 3519 if (phy->autoneg_advertised == 0) 3520 invalid = B_TRUE; 3521 } else { 3522 mac->autoneg = B_FALSE; 3523 3524 /* 3525 * 1000fdx and 1000hdx are not supported for forced link 3526 */ 3527 if (Adapter->param_adv_100fdx == 1) 3528 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3529 else if (Adapter->param_adv_100hdx == 1) 3530 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3531 else if (Adapter->param_adv_10fdx == 1) 3532 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3533 else if (Adapter->param_adv_10hdx == 1) 3534 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3535 else 3536 invalid = B_TRUE; 3537 3538 } 3539 3540 if (invalid) { 3541 e1000g_log(Adapter, CE_WARN, 3542 "Invalid link sets. Setup link to" 3543 "support autonegotiation with all link capabilities."); 3544 mac->autoneg = B_TRUE; 3545 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3546 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3547 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3548 } 3549 3550 return (e1000_setup_link(&Adapter->shared)); 3551 } 3552 3553 static void 3554 e1000g_local_timer(void *ws) 3555 { 3556 struct e1000g *Adapter = (struct e1000g *)ws; 3557 struct e1000_hw *hw; 3558 e1000g_ether_addr_t ether_addr; 3559 boolean_t link_changed; 3560 3561 hw = &Adapter->shared; 3562 3563 if (Adapter->chip_state == E1000G_ERROR) { 3564 Adapter->reset_count++; 3565 if (e1000g_global_reset(Adapter)) 3566 ddi_fm_service_impact(Adapter->dip, 3567 DDI_SERVICE_RESTORED); 3568 else 3569 ddi_fm_service_impact(Adapter->dip, 3570 DDI_SERVICE_LOST); 3571 return; 3572 } 3573 3574 if (e1000g_stall_check(Adapter)) { 3575 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3576 "Tx stall detected. Activate automatic recovery.\n"); 3577 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 3578 Adapter->reset_count++; 3579 if (e1000g_reset(Adapter)) 3580 ddi_fm_service_impact(Adapter->dip, 3581 DDI_SERVICE_RESTORED); 3582 else 3583 ddi_fm_service_impact(Adapter->dip, 3584 DDI_SERVICE_LOST); 3585 return; 3586 } 3587 3588 link_changed = B_FALSE; 3589 rw_enter(&Adapter->chip_lock, RW_READER); 3590 if (Adapter->link_complete) 3591 link_changed = e1000g_link_check(Adapter); 3592 rw_exit(&Adapter->chip_lock); 3593 3594 if (link_changed) { 3595 /* 3596 * Workaround for esb2. Data stuck in fifo on a link 3597 * down event. Reset the adapter to recover it. 3598 */ 3599 if ((Adapter->link_state == LINK_STATE_DOWN) && 3600 (hw->mac.type == e1000_80003es2lan)) 3601 (void) e1000g_reset(Adapter); 3602 3603 mac_link_update(Adapter->mh, Adapter->link_state); 3604 } 3605 3606 /* 3607 * With 82571 controllers, any locally administered address will 3608 * be overwritten when there is a reset on the other port. 3609 * Detect this circumstance and correct it. 3610 */ 3611 if ((hw->mac.type == e1000_82571) && 3612 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 3613 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 3614 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 3615 3616 ether_addr.reg.low = ntohl(ether_addr.reg.low); 3617 ether_addr.reg.high = ntohl(ether_addr.reg.high); 3618 3619 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 3620 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 3621 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 3622 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 3623 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 3624 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 3625 e1000_rar_set(hw, hw->mac.addr, 0); 3626 } 3627 } 3628 3629 /* 3630 * Long TTL workaround for 82541/82547 3631 */ 3632 e1000_igp_ttl_workaround_82547(hw); 3633 3634 /* 3635 * Check for Adaptive IFS settings If there are lots of collisions 3636 * change the value in steps... 3637 * These properties should only be set for 10/100 3638 */ 3639 if ((hw->phy.media_type == e1000_media_type_copper) && 3640 ((Adapter->link_speed == SPEED_100) || 3641 (Adapter->link_speed == SPEED_10))) { 3642 e1000_update_adaptive(hw); 3643 } 3644 /* 3645 * Set Timer Interrupts 3646 */ 3647 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 3648 3649 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3650 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3651 3652 restart_watchdog_timer(Adapter); 3653 } 3654 3655 /* 3656 * The function e1000g_link_timer() is called when the timer for link setup 3657 * is expired, which indicates the completion of the link setup. The link 3658 * state will not be updated until the link setup is completed. And the 3659 * link state will not be sent to the upper layer through mac_link_update() 3660 * in this function. It will be updated in the local timer routine or the 3661 * interrupt service routine after the interface is started (plumbed). 3662 */ 3663 static void 3664 e1000g_link_timer(void *arg) 3665 { 3666 struct e1000g *Adapter = (struct e1000g *)arg; 3667 3668 mutex_enter(&Adapter->link_lock); 3669 Adapter->link_complete = B_TRUE; 3670 Adapter->link_tid = 0; 3671 mutex_exit(&Adapter->link_lock); 3672 } 3673 3674 /* 3675 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 3676 * 3677 * This function read the forced speed and duplex for 10/100 Mbps speeds 3678 * and also for 1000 Mbps speeds from the e1000g.conf file 3679 */ 3680 static void 3681 e1000g_force_speed_duplex(struct e1000g *Adapter) 3682 { 3683 int forced; 3684 struct e1000_mac_info *mac = &Adapter->shared.mac; 3685 struct e1000_phy_info *phy = &Adapter->shared.phy; 3686 3687 /* 3688 * get value out of config file 3689 */ 3690 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 3691 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 3692 3693 switch (forced) { 3694 case GDIAG_10_HALF: 3695 /* 3696 * Disable Auto Negotiation 3697 */ 3698 mac->autoneg = B_FALSE; 3699 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3700 break; 3701 case GDIAG_10_FULL: 3702 /* 3703 * Disable Auto Negotiation 3704 */ 3705 mac->autoneg = B_FALSE; 3706 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3707 break; 3708 case GDIAG_100_HALF: 3709 /* 3710 * Disable Auto Negotiation 3711 */ 3712 mac->autoneg = B_FALSE; 3713 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3714 break; 3715 case GDIAG_100_FULL: 3716 /* 3717 * Disable Auto Negotiation 3718 */ 3719 mac->autoneg = B_FALSE; 3720 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3721 break; 3722 case GDIAG_1000_FULL: 3723 /* 3724 * The gigabit spec requires autonegotiation. Therefore, 3725 * when the user wants to force the speed to 1000Mbps, we 3726 * enable AutoNeg, but only allow the harware to advertise 3727 * 1000Mbps. This is different from 10/100 operation, where 3728 * we are allowed to link without any negotiation. 3729 */ 3730 mac->autoneg = B_TRUE; 3731 phy->autoneg_advertised = ADVERTISE_1000_FULL; 3732 break; 3733 default: /* obey the setting of AutoNegAdvertised */ 3734 mac->autoneg = B_TRUE; 3735 phy->autoneg_advertised = 3736 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 3737 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 3738 AUTONEG_ADVERTISE_SPEED_DEFAULT); 3739 break; 3740 } /* switch */ 3741 } 3742 3743 /* 3744 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 3745 * 3746 * This function reads MaxFrameSize from e1000g.conf 3747 */ 3748 static void 3749 e1000g_get_max_frame_size(struct e1000g *Adapter) 3750 { 3751 int max_frame; 3752 struct e1000_mac_info *mac = &Adapter->shared.mac; 3753 struct e1000_phy_info *phy = &Adapter->shared.phy; 3754 3755 /* 3756 * get value out of config file 3757 */ 3758 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 3759 3760 switch (max_frame) { 3761 case 0: 3762 Adapter->default_mtu = ETHERMTU; 3763 break; 3764 /* 3765 * To avoid excessive memory allocation for rx buffers, 3766 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 3767 */ 3768 case 1: 3769 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 3770 sizeof (struct ether_vlan_header) - ETHERFCSL - 3771 E1000G_IPALIGNPRESERVEROOM; 3772 break; 3773 case 2: 3774 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 3775 sizeof (struct ether_vlan_header) - ETHERFCSL - 3776 E1000G_IPALIGNPRESERVEROOM; 3777 break; 3778 case 3: 3779 if (mac->type >= e1000_82571) 3780 Adapter->default_mtu = MAXIMUM_MTU; 3781 else 3782 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 3783 sizeof (struct ether_vlan_header) - ETHERFCSL - 3784 E1000G_IPALIGNPRESERVEROOM; 3785 break; 3786 default: 3787 Adapter->default_mtu = ETHERMTU; 3788 break; 3789 } /* switch */ 3790 3791 Adapter->max_frame_size = Adapter->default_mtu + 3792 sizeof (struct ether_vlan_header) + ETHERFCSL; 3793 3794 /* ich8 does not do jumbo frames */ 3795 if (mac->type == e1000_ich8lan) { 3796 Adapter->max_frame_size = ETHERMAX; 3797 } 3798 3799 /* ich9 does not do jumbo frames on one phy type */ 3800 if ((mac->type == e1000_ich9lan) && 3801 (phy->type == e1000_phy_ife)) { 3802 Adapter->max_frame_size = ETHERMAX; 3803 } 3804 } 3805 3806 static void 3807 arm_watchdog_timer(struct e1000g *Adapter) 3808 { 3809 Adapter->watchdog_tid = 3810 timeout(e1000g_local_timer, 3811 (void *)Adapter, 1 * drv_usectohz(1000000)); 3812 } 3813 #pragma inline(arm_watchdog_timer) 3814 3815 static void 3816 enable_watchdog_timer(struct e1000g *Adapter) 3817 { 3818 mutex_enter(&Adapter->watchdog_lock); 3819 3820 if (!Adapter->watchdog_timer_enabled) { 3821 Adapter->watchdog_timer_enabled = B_TRUE; 3822 Adapter->watchdog_timer_started = B_TRUE; 3823 arm_watchdog_timer(Adapter); 3824 } 3825 3826 mutex_exit(&Adapter->watchdog_lock); 3827 } 3828 3829 static void 3830 disable_watchdog_timer(struct e1000g *Adapter) 3831 { 3832 timeout_id_t tid; 3833 3834 mutex_enter(&Adapter->watchdog_lock); 3835 3836 Adapter->watchdog_timer_enabled = B_FALSE; 3837 Adapter->watchdog_timer_started = B_FALSE; 3838 tid = Adapter->watchdog_tid; 3839 Adapter->watchdog_tid = 0; 3840 3841 mutex_exit(&Adapter->watchdog_lock); 3842 3843 if (tid != 0) 3844 (void) untimeout(tid); 3845 } 3846 3847 static void 3848 start_watchdog_timer(struct e1000g *Adapter) 3849 { 3850 mutex_enter(&Adapter->watchdog_lock); 3851 3852 if (Adapter->watchdog_timer_enabled) { 3853 if (!Adapter->watchdog_timer_started) { 3854 Adapter->watchdog_timer_started = B_TRUE; 3855 arm_watchdog_timer(Adapter); 3856 } 3857 } 3858 3859 mutex_exit(&Adapter->watchdog_lock); 3860 } 3861 3862 static void 3863 restart_watchdog_timer(struct e1000g *Adapter) 3864 { 3865 mutex_enter(&Adapter->watchdog_lock); 3866 3867 if (Adapter->watchdog_timer_started) 3868 arm_watchdog_timer(Adapter); 3869 3870 mutex_exit(&Adapter->watchdog_lock); 3871 } 3872 3873 static void 3874 stop_watchdog_timer(struct e1000g *Adapter) 3875 { 3876 timeout_id_t tid; 3877 3878 mutex_enter(&Adapter->watchdog_lock); 3879 3880 Adapter->watchdog_timer_started = B_FALSE; 3881 tid = Adapter->watchdog_tid; 3882 Adapter->watchdog_tid = 0; 3883 3884 mutex_exit(&Adapter->watchdog_lock); 3885 3886 if (tid != 0) 3887 (void) untimeout(tid); 3888 } 3889 3890 static void 3891 stop_link_timer(struct e1000g *Adapter) 3892 { 3893 timeout_id_t tid; 3894 3895 /* Disable the link timer */ 3896 mutex_enter(&Adapter->link_lock); 3897 3898 tid = Adapter->link_tid; 3899 Adapter->link_tid = 0; 3900 3901 mutex_exit(&Adapter->link_lock); 3902 3903 if (tid != 0) 3904 (void) untimeout(tid); 3905 } 3906 3907 static void 3908 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 3909 { 3910 timeout_id_t tid; 3911 3912 /* Disable the tx timer for 82547 chipset */ 3913 mutex_enter(&tx_ring->tx_lock); 3914 3915 tx_ring->timer_enable_82547 = B_FALSE; 3916 tid = tx_ring->timer_id_82547; 3917 tx_ring->timer_id_82547 = 0; 3918 3919 mutex_exit(&tx_ring->tx_lock); 3920 3921 if (tid != 0) 3922 (void) untimeout(tid); 3923 } 3924 3925 void 3926 e1000g_clear_interrupt(struct e1000g *Adapter) 3927 { 3928 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 3929 0xffffffff & ~E1000_IMS_RXSEQ); 3930 } 3931 3932 void 3933 e1000g_mask_interrupt(struct e1000g *Adapter) 3934 { 3935 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 3936 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 3937 3938 if (Adapter->tx_intr_enable) 3939 e1000g_mask_tx_interrupt(Adapter); 3940 } 3941 3942 void 3943 e1000g_clear_all_interrupts(struct e1000g *Adapter) 3944 { 3945 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 3946 } 3947 3948 void 3949 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 3950 { 3951 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 3952 } 3953 3954 void 3955 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 3956 { 3957 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 3958 } 3959 3960 static void 3961 e1000g_smartspeed(struct e1000g *Adapter) 3962 { 3963 struct e1000_hw *hw = &Adapter->shared; 3964 uint16_t phy_status; 3965 uint16_t phy_ctrl; 3966 3967 /* 3968 * If we're not T-or-T, or we're not autoneg'ing, or we're not 3969 * advertising 1000Full, we don't even use the workaround 3970 */ 3971 if ((hw->phy.type != e1000_phy_igp) || 3972 !hw->mac.autoneg || 3973 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 3974 return; 3975 3976 /* 3977 * True if this is the first call of this function or after every 3978 * 30 seconds of not having link 3979 */ 3980 if (Adapter->smartspeed == 0) { 3981 /* 3982 * If Master/Slave config fault is asserted twice, we 3983 * assume back-to-back 3984 */ 3985 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 3986 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3987 return; 3988 3989 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 3990 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3991 return; 3992 /* 3993 * We're assuming back-2-back because our status register 3994 * insists! there's a fault in the master/slave 3995 * relationship that was "negotiated" 3996 */ 3997 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 3998 /* 3999 * Is the phy configured for manual configuration of 4000 * master/slave? 4001 */ 4002 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4003 /* 4004 * Yes. Then disable manual configuration (enable 4005 * auto configuration) of master/slave 4006 */ 4007 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4008 e1000_write_phy_reg(hw, 4009 PHY_1000T_CTRL, phy_ctrl); 4010 /* 4011 * Effectively starting the clock 4012 */ 4013 Adapter->smartspeed++; 4014 /* 4015 * Restart autonegotiation 4016 */ 4017 if (!e1000_phy_setup_autoneg(hw) && 4018 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4019 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4020 MII_CR_RESTART_AUTO_NEG); 4021 e1000_write_phy_reg(hw, 4022 PHY_CONTROL, phy_ctrl); 4023 } 4024 } 4025 return; 4026 /* 4027 * Has 6 seconds transpired still without link? Remember, 4028 * you should reset the smartspeed counter once you obtain 4029 * link 4030 */ 4031 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4032 /* 4033 * Yes. Remember, we did at the start determine that 4034 * there's a master/slave configuration fault, so we're 4035 * still assuming there's someone on the other end, but we 4036 * just haven't yet been able to talk to it. We then 4037 * re-enable auto configuration of master/slave to see if 4038 * we're running 2/3 pair cables. 4039 */ 4040 /* 4041 * If still no link, perhaps using 2/3 pair cable 4042 */ 4043 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4044 phy_ctrl |= CR_1000T_MS_ENABLE; 4045 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4046 /* 4047 * Restart autoneg with phy enabled for manual 4048 * configuration of master/slave 4049 */ 4050 if (!e1000_phy_setup_autoneg(hw) && 4051 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4052 phy_ctrl |= 4053 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4054 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4055 } 4056 /* 4057 * Hopefully, there are no more faults and we've obtained 4058 * link as a result. 4059 */ 4060 } 4061 /* 4062 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4063 * seconds) 4064 */ 4065 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4066 Adapter->smartspeed = 0; 4067 } 4068 4069 static boolean_t 4070 is_valid_mac_addr(uint8_t *mac_addr) 4071 { 4072 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4073 const uint8_t addr_test2[6] = 4074 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4075 4076 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4077 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4078 return (B_FALSE); 4079 4080 return (B_TRUE); 4081 } 4082 4083 /* 4084 * e1000g_stall_check - check for tx stall 4085 * 4086 * This function checks if the adapter is stalled (in transmit). 4087 * 4088 * It is called each time the watchdog timeout is invoked. 4089 * If the transmit descriptor reclaim continuously fails, 4090 * the watchdog value will increment by 1. If the watchdog 4091 * value exceeds the threshold, the adapter is assumed to 4092 * have stalled and need to be reset. 4093 */ 4094 static boolean_t 4095 e1000g_stall_check(struct e1000g *Adapter) 4096 { 4097 e1000g_tx_ring_t *tx_ring; 4098 4099 tx_ring = Adapter->tx_ring; 4100 4101 if (Adapter->link_state != LINK_STATE_UP) 4102 return (B_FALSE); 4103 4104 if (tx_ring->recycle_fail > 0) 4105 tx_ring->stall_watchdog++; 4106 else 4107 tx_ring->stall_watchdog = 0; 4108 4109 if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) 4110 return (B_FALSE); 4111 4112 tx_ring->stall_watchdog = 0; 4113 tx_ring->recycle_fail = 0; 4114 4115 return (B_TRUE); 4116 } 4117 4118 #ifdef E1000G_DEBUG 4119 static enum ioc_reply 4120 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4121 { 4122 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4123 e1000g_peekpoke_t *ppd; 4124 uint64_t mem_va; 4125 uint64_t maxoff; 4126 boolean_t peek; 4127 4128 switch (iocp->ioc_cmd) { 4129 4130 case E1000G_IOC_REG_PEEK: 4131 peek = B_TRUE; 4132 break; 4133 4134 case E1000G_IOC_REG_POKE: 4135 peek = B_FALSE; 4136 break; 4137 4138 deault: 4139 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4140 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4141 iocp->ioc_cmd); 4142 return (IOC_INVAL); 4143 } 4144 4145 /* 4146 * Validate format of ioctl 4147 */ 4148 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4149 return (IOC_INVAL); 4150 if (mp->b_cont == NULL) 4151 return (IOC_INVAL); 4152 4153 ppd = (e1000g_peekpoke_t *)mp->b_cont->b_rptr; 4154 4155 /* 4156 * Validate request parameters 4157 */ 4158 switch (ppd->pp_acc_space) { 4159 4160 default: 4161 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4162 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4163 ppd->pp_acc_space); 4164 return (IOC_INVAL); 4165 4166 case E1000G_PP_SPACE_REG: 4167 /* 4168 * Memory-mapped I/O space 4169 */ 4170 ASSERT(ppd->pp_acc_size == 4); 4171 if (ppd->pp_acc_size != 4) 4172 return (IOC_INVAL); 4173 4174 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4175 return (IOC_INVAL); 4176 4177 mem_va = 0; 4178 maxoff = 0x10000; 4179 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4180 break; 4181 4182 case E1000G_PP_SPACE_E1000G: 4183 /* 4184 * E1000g data structure! 4185 */ 4186 mem_va = (uintptr_t)e1000gp; 4187 maxoff = sizeof (struct e1000g); 4188 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4189 break; 4190 4191 } 4192 4193 if (ppd->pp_acc_offset >= maxoff) 4194 return (IOC_INVAL); 4195 4196 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4197 return (IOC_INVAL); 4198 4199 /* 4200 * All OK - go! 4201 */ 4202 ppd->pp_acc_offset += mem_va; 4203 (*ppfn)(e1000gp, ppd); 4204 return (peek ? IOC_REPLY : IOC_ACK); 4205 } 4206 4207 static void 4208 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4209 { 4210 ddi_acc_handle_t handle; 4211 uint32_t *regaddr; 4212 4213 handle = e1000gp->osdep.reg_handle; 4214 regaddr = 4215 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 4216 4217 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4218 } 4219 4220 static void 4221 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4222 { 4223 ddi_acc_handle_t handle; 4224 uint32_t *regaddr; 4225 uint32_t value; 4226 4227 handle = e1000gp->osdep.reg_handle; 4228 regaddr = 4229 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 4230 value = (uint32_t)ppd->pp_acc_data; 4231 4232 ddi_put32(handle, regaddr, value); 4233 } 4234 4235 static void 4236 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4237 { 4238 uint64_t value; 4239 void *vaddr; 4240 4241 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4242 4243 switch (ppd->pp_acc_size) { 4244 case 1: 4245 value = *(uint8_t *)vaddr; 4246 break; 4247 4248 case 2: 4249 value = *(uint16_t *)vaddr; 4250 break; 4251 4252 case 4: 4253 value = *(uint32_t *)vaddr; 4254 break; 4255 4256 case 8: 4257 value = *(uint64_t *)vaddr; 4258 break; 4259 } 4260 4261 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4262 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4263 (void *)e1000gp, (void *)ppd, value, vaddr); 4264 4265 ppd->pp_acc_data = value; 4266 } 4267 4268 static void 4269 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4270 { 4271 uint64_t value; 4272 void *vaddr; 4273 4274 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4275 value = ppd->pp_acc_data; 4276 4277 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4278 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4279 (void *)e1000gp, (void *)ppd, value, vaddr); 4280 4281 switch (ppd->pp_acc_size) { 4282 case 1: 4283 *(uint8_t *)vaddr = (uint8_t)value; 4284 break; 4285 4286 case 2: 4287 *(uint16_t *)vaddr = (uint16_t)value; 4288 break; 4289 4290 case 4: 4291 *(uint32_t *)vaddr = (uint32_t)value; 4292 break; 4293 4294 case 8: 4295 *(uint64_t *)vaddr = (uint64_t)value; 4296 break; 4297 } 4298 } 4299 #endif 4300 4301 /* 4302 * Loopback Support 4303 */ 4304 static lb_property_t lb_normal = 4305 { normal, "normal", E1000G_LB_NONE }; 4306 static lb_property_t lb_external1000 = 4307 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4308 static lb_property_t lb_external100 = 4309 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4310 static lb_property_t lb_external10 = 4311 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4312 static lb_property_t lb_phy = 4313 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4314 4315 static enum ioc_reply 4316 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4317 { 4318 lb_info_sz_t *lbsp; 4319 lb_property_t *lbpp; 4320 struct e1000_hw *hw; 4321 uint32_t *lbmp; 4322 uint32_t size; 4323 uint32_t value; 4324 4325 hw = &Adapter->shared; 4326 4327 if (mp->b_cont == NULL) 4328 return (IOC_INVAL); 4329 4330 switch (iocp->ioc_cmd) { 4331 default: 4332 return (IOC_INVAL); 4333 4334 case LB_GET_INFO_SIZE: 4335 size = sizeof (lb_info_sz_t); 4336 if (iocp->ioc_count != size) 4337 return (IOC_INVAL); 4338 4339 rw_enter(&Adapter->chip_lock, RW_WRITER); 4340 e1000g_get_phy_state(Adapter); 4341 4342 /* 4343 * Workaround for hardware faults. In order to get a stable 4344 * state of phy, we will wait for a specific interval and 4345 * try again. The time delay is an experiential value based 4346 * on our testing. 4347 */ 4348 msec_delay(100); 4349 e1000g_get_phy_state(Adapter); 4350 rw_exit(&Adapter->chip_lock); 4351 4352 value = sizeof (lb_normal); 4353 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4354 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4355 (hw->phy.media_type == e1000_media_type_fiber) || 4356 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4357 value += sizeof (lb_phy); 4358 switch (hw->mac.type) { 4359 case e1000_82571: 4360 case e1000_82572: 4361 value += sizeof (lb_external1000); 4362 break; 4363 } 4364 } 4365 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4366 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4367 value += sizeof (lb_external100); 4368 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4369 value += sizeof (lb_external10); 4370 4371 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 4372 *lbsp = value; 4373 break; 4374 4375 case LB_GET_INFO: 4376 value = sizeof (lb_normal); 4377 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4378 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4379 (hw->phy.media_type == e1000_media_type_fiber) || 4380 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4381 value += sizeof (lb_phy); 4382 switch (hw->mac.type) { 4383 case e1000_82571: 4384 case e1000_82572: 4385 value += sizeof (lb_external1000); 4386 break; 4387 } 4388 } 4389 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4390 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4391 value += sizeof (lb_external100); 4392 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4393 value += sizeof (lb_external10); 4394 4395 size = value; 4396 if (iocp->ioc_count != size) 4397 return (IOC_INVAL); 4398 4399 value = 0; 4400 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 4401 lbpp[value++] = lb_normal; 4402 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4403 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4404 (hw->phy.media_type == e1000_media_type_fiber) || 4405 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4406 lbpp[value++] = lb_phy; 4407 switch (hw->mac.type) { 4408 case e1000_82571: 4409 case e1000_82572: 4410 lbpp[value++] = lb_external1000; 4411 break; 4412 } 4413 } 4414 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4415 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4416 lbpp[value++] = lb_external100; 4417 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4418 lbpp[value++] = lb_external10; 4419 break; 4420 4421 case LB_GET_MODE: 4422 size = sizeof (uint32_t); 4423 if (iocp->ioc_count != size) 4424 return (IOC_INVAL); 4425 4426 lbmp = (uint32_t *)mp->b_cont->b_rptr; 4427 *lbmp = Adapter->loopback_mode; 4428 break; 4429 4430 case LB_SET_MODE: 4431 size = 0; 4432 if (iocp->ioc_count != sizeof (uint32_t)) 4433 return (IOC_INVAL); 4434 4435 lbmp = (uint32_t *)mp->b_cont->b_rptr; 4436 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4437 return (IOC_INVAL); 4438 break; 4439 } 4440 4441 iocp->ioc_count = size; 4442 iocp->ioc_error = 0; 4443 4444 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4445 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4446 return (IOC_INVAL); 4447 } 4448 4449 return (IOC_REPLY); 4450 } 4451 4452 static boolean_t 4453 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 4454 { 4455 struct e1000_hw *hw; 4456 int i, times; 4457 boolean_t link_up; 4458 4459 if (mode == Adapter->loopback_mode) 4460 return (B_TRUE); 4461 4462 hw = &Adapter->shared; 4463 times = 0; 4464 4465 Adapter->loopback_mode = mode; 4466 4467 if (mode == E1000G_LB_NONE) { 4468 /* Reset the chip */ 4469 hw->phy.autoneg_wait_to_complete = B_TRUE; 4470 (void) e1000g_reset(Adapter); 4471 hw->phy.autoneg_wait_to_complete = B_FALSE; 4472 return (B_TRUE); 4473 } 4474 4475 again: 4476 4477 rw_enter(&Adapter->chip_lock, RW_WRITER); 4478 4479 switch (mode) { 4480 default: 4481 rw_exit(&Adapter->chip_lock); 4482 return (B_FALSE); 4483 4484 case E1000G_LB_EXTERNAL_1000: 4485 e1000g_set_external_loopback_1000(Adapter); 4486 break; 4487 4488 case E1000G_LB_EXTERNAL_100: 4489 e1000g_set_external_loopback_100(Adapter); 4490 break; 4491 4492 case E1000G_LB_EXTERNAL_10: 4493 e1000g_set_external_loopback_10(Adapter); 4494 break; 4495 4496 case E1000G_LB_INTERNAL_PHY: 4497 e1000g_set_internal_loopback(Adapter); 4498 break; 4499 } 4500 4501 times++; 4502 4503 rw_exit(&Adapter->chip_lock); 4504 4505 /* Wait for link up */ 4506 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 4507 msec_delay(100); 4508 4509 rw_enter(&Adapter->chip_lock, RW_WRITER); 4510 4511 link_up = e1000g_link_up(Adapter); 4512 4513 rw_exit(&Adapter->chip_lock); 4514 4515 if (!link_up) { 4516 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4517 "Failed to get the link up"); 4518 if (times < 2) { 4519 /* Reset the link */ 4520 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4521 "Reset the link ..."); 4522 (void) e1000g_reset(Adapter); 4523 goto again; 4524 } 4525 } 4526 4527 return (B_TRUE); 4528 } 4529 4530 /* 4531 * The following loopback settings are from Intel's technical 4532 * document - "How To Loopback". All the register settings and 4533 * time delay values are directly inherited from the document 4534 * without more explanations available. 4535 */ 4536 static void 4537 e1000g_set_internal_loopback(struct e1000g *Adapter) 4538 { 4539 struct e1000_hw *hw; 4540 uint32_t ctrl; 4541 uint32_t status; 4542 uint16_t phy_ctrl; 4543 uint32_t txcw; 4544 4545 hw = &Adapter->shared; 4546 4547 /* Disable Smart Power Down */ 4548 phy_spd_state(hw, B_FALSE); 4549 4550 e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4551 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 4552 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 4553 4554 switch (hw->mac.type) { 4555 case e1000_82540: 4556 case e1000_82545: 4557 case e1000_82545_rev_3: 4558 case e1000_82546: 4559 case e1000_82546_rev_3: 4560 case e1000_82573: 4561 /* Auto-MDI/MDIX off */ 4562 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 4563 /* Reset PHY to update Auto-MDI/MDIX */ 4564 e1000_write_phy_reg(hw, PHY_CONTROL, 4565 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 4566 /* Reset PHY to auto-neg off and force 1000 */ 4567 e1000_write_phy_reg(hw, PHY_CONTROL, 4568 phy_ctrl | MII_CR_RESET); 4569 /* 4570 * Disable PHY receiver for 82540/545/546 and 82573 Family. 4571 * See comments above e1000g_set_internal_loopback() for the 4572 * background. 4573 */ 4574 e1000_write_phy_reg(hw, 29, 0x001F); 4575 e1000_write_phy_reg(hw, 30, 0x8FFC); 4576 e1000_write_phy_reg(hw, 29, 0x001A); 4577 e1000_write_phy_reg(hw, 30, 0x8FF0); 4578 break; 4579 } 4580 4581 /* Set loopback */ 4582 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 4583 4584 msec_delay(250); 4585 4586 /* Now set up the MAC to the same speed/duplex as the PHY. */ 4587 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4588 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4589 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4590 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4591 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 4592 E1000_CTRL_FD); /* Force Duplex to FULL */ 4593 4594 switch (hw->mac.type) { 4595 case e1000_82540: 4596 case e1000_82545: 4597 case e1000_82545_rev_3: 4598 case e1000_82546: 4599 case e1000_82546_rev_3: 4600 /* 4601 * For some serdes we'll need to commit the writes now 4602 * so that the status is updated on link 4603 */ 4604 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 4605 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4606 msec_delay(100); 4607 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4608 } 4609 4610 if (hw->phy.media_type == e1000_media_type_copper) { 4611 /* Invert Loss of Signal */ 4612 ctrl |= E1000_CTRL_ILOS; 4613 } else { 4614 /* Set ILOS on fiber nic if half duplex is detected */ 4615 status = E1000_READ_REG(hw, E1000_STATUS); 4616 if ((status & E1000_STATUS_FD) == 0) 4617 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4618 } 4619 break; 4620 4621 case e1000_82571: 4622 case e1000_82572: 4623 /* 4624 * The fiber/SerDes versions of this adapter do not contain an 4625 * accessible PHY. Therefore, loopback beyond MAC must be done 4626 * using SerDes analog loopback. 4627 */ 4628 if (hw->phy.media_type != e1000_media_type_copper) { 4629 status = E1000_READ_REG(hw, E1000_STATUS); 4630 /* Set ILOS on fiber nic if half duplex is detected */ 4631 if (((status & E1000_STATUS_LU) == 0) || 4632 ((status & E1000_STATUS_FD) == 0) || 4633 (hw->phy.media_type == 4634 e1000_media_type_internal_serdes)) 4635 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4636 4637 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4638 txcw = E1000_READ_REG(hw, E1000_TXCW); 4639 txcw &= ~((uint32_t)1 << 31); 4640 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4641 4642 /* 4643 * Write 0x410 to Serdes Control register 4644 * to enable Serdes analog loopback 4645 */ 4646 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4647 msec_delay(10); 4648 } 4649 break; 4650 4651 case e1000_82573: 4652 ctrl |= E1000_CTRL_ILOS; 4653 break; 4654 } 4655 4656 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4657 4658 } 4659 4660 static void 4661 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 4662 { 4663 struct e1000_hw *hw; 4664 uint32_t rctl; 4665 uint32_t ctrl_ext; 4666 uint32_t ctrl; 4667 uint32_t status; 4668 uint32_t txcw; 4669 4670 hw = &Adapter->shared; 4671 4672 /* Disable Smart Power Down */ 4673 phy_spd_state(hw, B_FALSE); 4674 4675 switch (hw->phy.media_type) { 4676 case e1000_media_type_copper: 4677 /* Force link up (Must be done before the PHY writes) */ 4678 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4679 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 4680 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4681 4682 rctl = E1000_READ_REG(hw, E1000_RCTL); 4683 rctl |= (E1000_RCTL_EN | 4684 E1000_RCTL_SBP | 4685 E1000_RCTL_UPE | 4686 E1000_RCTL_MPE | 4687 E1000_RCTL_LPE | 4688 E1000_RCTL_BAM); /* 0x803E */ 4689 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4690 4691 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4692 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 4693 E1000_CTRL_EXT_SDP6_DATA | 4694 E1000_CTRL_EXT_SDP7_DATA | 4695 E1000_CTRL_EXT_SDP4_DIR | 4696 E1000_CTRL_EXT_SDP6_DIR | 4697 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 4698 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4699 4700 /* 4701 * This sequence tunes the PHY's SDP and no customer 4702 * settable values. For background, see comments above 4703 * e1000g_set_internal_loopback(). 4704 */ 4705 e1000_write_phy_reg(hw, 0x0, 0x140); 4706 msec_delay(10); 4707 e1000_write_phy_reg(hw, 0x9, 0x1A00); 4708 e1000_write_phy_reg(hw, 0x12, 0xC10); 4709 e1000_write_phy_reg(hw, 0x12, 0x1C10); 4710 e1000_write_phy_reg(hw, 0x1F37, 0x76); 4711 e1000_write_phy_reg(hw, 0x1F33, 0x1); 4712 e1000_write_phy_reg(hw, 0x1F33, 0x0); 4713 4714 e1000_write_phy_reg(hw, 0x1F35, 0x65); 4715 e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 4716 e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 4717 e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 4718 e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 4719 4720 msec_delay(50); 4721 break; 4722 case e1000_media_type_fiber: 4723 case e1000_media_type_internal_serdes: 4724 status = E1000_READ_REG(hw, E1000_STATUS); 4725 if (((status & E1000_STATUS_LU) == 0) || 4726 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4727 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4728 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4729 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4730 } 4731 4732 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4733 txcw = E1000_READ_REG(hw, E1000_TXCW); 4734 txcw &= ~((uint32_t)1 << 31); 4735 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4736 4737 /* 4738 * Write 0x410 to Serdes Control register 4739 * to enable Serdes analog loopback 4740 */ 4741 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4742 msec_delay(10); 4743 break; 4744 default: 4745 break; 4746 } 4747 } 4748 4749 static void 4750 e1000g_set_external_loopback_100(struct e1000g *Adapter) 4751 { 4752 struct e1000_hw *hw; 4753 uint32_t ctrl; 4754 uint16_t phy_ctrl; 4755 4756 hw = &Adapter->shared; 4757 4758 /* Disable Smart Power Down */ 4759 phy_spd_state(hw, B_FALSE); 4760 4761 phy_ctrl = (MII_CR_FULL_DUPLEX | 4762 MII_CR_SPEED_100); 4763 4764 /* Force 100/FD, reset PHY */ 4765 e1000_write_phy_reg(hw, PHY_CONTROL, 4766 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 4767 msec_delay(10); 4768 4769 /* Force 100/FD */ 4770 e1000_write_phy_reg(hw, PHY_CONTROL, 4771 phy_ctrl); /* 0x2100 */ 4772 msec_delay(10); 4773 4774 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4775 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4776 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4777 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4778 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4779 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4780 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 4781 E1000_CTRL_FD); /* Force Duplex to FULL */ 4782 4783 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4784 } 4785 4786 static void 4787 e1000g_set_external_loopback_10(struct e1000g *Adapter) 4788 { 4789 struct e1000_hw *hw; 4790 uint32_t ctrl; 4791 uint16_t phy_ctrl; 4792 4793 hw = &Adapter->shared; 4794 4795 /* Disable Smart Power Down */ 4796 phy_spd_state(hw, B_FALSE); 4797 4798 phy_ctrl = (MII_CR_FULL_DUPLEX | 4799 MII_CR_SPEED_10); 4800 4801 /* Force 10/FD, reset PHY */ 4802 e1000_write_phy_reg(hw, PHY_CONTROL, 4803 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 4804 msec_delay(10); 4805 4806 /* Force 10/FD */ 4807 e1000_write_phy_reg(hw, PHY_CONTROL, 4808 phy_ctrl); /* 0x0100 */ 4809 msec_delay(10); 4810 4811 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4812 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4813 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4814 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4815 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4816 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4817 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 4818 E1000_CTRL_FD); /* Force Duplex to FULL */ 4819 4820 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4821 } 4822 4823 #ifdef __sparc 4824 static boolean_t 4825 e1000g_find_mac_address(struct e1000g *Adapter) 4826 { 4827 struct e1000_hw *hw = &Adapter->shared; 4828 uchar_t *bytes; 4829 struct ether_addr sysaddr; 4830 uint_t nelts; 4831 int err; 4832 boolean_t found = B_FALSE; 4833 4834 /* 4835 * The "vendor's factory-set address" may already have 4836 * been extracted from the chip, but if the property 4837 * "local-mac-address" is set we use that instead. 4838 * 4839 * We check whether it looks like an array of 6 4840 * bytes (which it should, if OBP set it). If we can't 4841 * make sense of it this way, we'll ignore it. 4842 */ 4843 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4844 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 4845 if (err == DDI_PROP_SUCCESS) { 4846 if (nelts == ETHERADDRL) { 4847 while (nelts--) 4848 hw->mac.addr[nelts] = bytes[nelts]; 4849 found = B_TRUE; 4850 } 4851 ddi_prop_free(bytes); 4852 } 4853 4854 /* 4855 * Look up the OBP property "local-mac-address?". If the user has set 4856 * 'local-mac-address? = false', use "the system address" instead. 4857 */ 4858 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 4859 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 4860 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 4861 if (localetheraddr(NULL, &sysaddr) != 0) { 4862 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 4863 found = B_TRUE; 4864 } 4865 } 4866 ddi_prop_free(bytes); 4867 } 4868 4869 /* 4870 * Finally(!), if there's a valid "mac-address" property (created 4871 * if we netbooted from this interface), we must use this instead 4872 * of any of the above to ensure that the NFS/install server doesn't 4873 * get confused by the address changing as Solaris takes over! 4874 */ 4875 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4876 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 4877 if (err == DDI_PROP_SUCCESS) { 4878 if (nelts == ETHERADDRL) { 4879 while (nelts--) 4880 hw->mac.addr[nelts] = bytes[nelts]; 4881 found = B_TRUE; 4882 } 4883 ddi_prop_free(bytes); 4884 } 4885 4886 if (found) { 4887 bcopy(hw->mac.addr, hw->mac.perm_addr, 4888 ETHERADDRL); 4889 } 4890 4891 return (found); 4892 } 4893 #endif 4894 4895 static int 4896 e1000g_add_intrs(struct e1000g *Adapter) 4897 { 4898 dev_info_t *devinfo; 4899 int intr_types; 4900 int rc; 4901 4902 devinfo = Adapter->dip; 4903 4904 /* Get supported interrupt types */ 4905 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 4906 4907 if (rc != DDI_SUCCESS) { 4908 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4909 "Get supported interrupt types failed: %d\n", rc); 4910 return (DDI_FAILURE); 4911 } 4912 4913 /* 4914 * Based on Intel Technical Advisory document (TA-160), there are some 4915 * cases where some older Intel PCI-X NICs may "advertise" to the OS 4916 * that it supports MSI, but in fact has problems. 4917 * So we should only enable MSI for PCI-E NICs and disable MSI for old 4918 * PCI/PCI-X NICs. 4919 */ 4920 if (Adapter->shared.mac.type < e1000_82571) 4921 Adapter->msi_enabled = B_FALSE; 4922 4923 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enabled) { 4924 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 4925 4926 if (rc != DDI_SUCCESS) { 4927 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4928 "Add MSI failed, trying Legacy interrupts\n"); 4929 } else { 4930 Adapter->intr_type = DDI_INTR_TYPE_MSI; 4931 } 4932 } 4933 4934 if ((Adapter->intr_type == 0) && 4935 (intr_types & DDI_INTR_TYPE_FIXED)) { 4936 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 4937 4938 if (rc != DDI_SUCCESS) { 4939 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4940 "Add Legacy interrupts failed\n"); 4941 return (DDI_FAILURE); 4942 } 4943 4944 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 4945 } 4946 4947 if (Adapter->intr_type == 0) { 4948 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4949 "No interrupts registered\n"); 4950 return (DDI_FAILURE); 4951 } 4952 4953 return (DDI_SUCCESS); 4954 } 4955 4956 /* 4957 * e1000g_intr_add() handles MSI/Legacy interrupts 4958 */ 4959 static int 4960 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 4961 { 4962 dev_info_t *devinfo; 4963 int count, avail, actual; 4964 int x, y, rc, inum = 0; 4965 int flag; 4966 ddi_intr_handler_t *intr_handler; 4967 4968 devinfo = Adapter->dip; 4969 4970 /* get number of interrupts */ 4971 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 4972 if ((rc != DDI_SUCCESS) || (count == 0)) { 4973 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4974 "Get interrupt number failed. Return: %d, count: %d\n", 4975 rc, count); 4976 return (DDI_FAILURE); 4977 } 4978 4979 /* get number of available interrupts */ 4980 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 4981 if ((rc != DDI_SUCCESS) || (avail == 0)) { 4982 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4983 "Get interrupt available number failed. " 4984 "Return: %d, available: %d\n", rc, avail); 4985 return (DDI_FAILURE); 4986 } 4987 4988 if (avail < count) { 4989 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4990 "Interrupts count: %d, available: %d\n", 4991 count, avail); 4992 } 4993 4994 /* Allocate an array of interrupt handles */ 4995 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 4996 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 4997 4998 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 4999 flag = DDI_INTR_ALLOC_NORMAL; 5000 5001 /* call ddi_intr_alloc() */ 5002 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5003 count, &actual, flag); 5004 5005 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5006 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5007 "Allocate interrupts failed: %d\n", rc); 5008 5009 kmem_free(Adapter->htable, Adapter->intr_size); 5010 return (DDI_FAILURE); 5011 } 5012 5013 if (actual < count) { 5014 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5015 "Interrupts requested: %d, received: %d\n", 5016 count, actual); 5017 } 5018 5019 Adapter->intr_cnt = actual; 5020 5021 /* Get priority for first msi, assume remaining are all the same */ 5022 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5023 5024 if (rc != DDI_SUCCESS) { 5025 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5026 "Get interrupt priority failed: %d\n", rc); 5027 5028 /* Free already allocated intr */ 5029 for (y = 0; y < actual; y++) 5030 (void) ddi_intr_free(Adapter->htable[y]); 5031 5032 kmem_free(Adapter->htable, Adapter->intr_size); 5033 return (DDI_FAILURE); 5034 } 5035 5036 /* 5037 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5038 * use the interrupt service routine e1000g_intr_pciexpress() 5039 * to avoid interrupt stealing when sharing interrupt with other 5040 * devices. 5041 */ 5042 if (Adapter->shared.mac.type < e1000_82571) 5043 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5044 else 5045 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5046 5047 /* Call ddi_intr_add_handler() */ 5048 for (x = 0; x < actual; x++) { 5049 rc = ddi_intr_add_handler(Adapter->htable[x], 5050 intr_handler, (caddr_t)Adapter, NULL); 5051 5052 if (rc != DDI_SUCCESS) { 5053 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5054 "Add interrupt handler failed: %d\n", rc); 5055 5056 /* Remove already added handler */ 5057 for (y = 0; y < x; y++) 5058 (void) ddi_intr_remove_handler( 5059 Adapter->htable[y]); 5060 5061 /* Free already allocated intr */ 5062 for (y = 0; y < actual; y++) 5063 (void) ddi_intr_free(Adapter->htable[y]); 5064 5065 kmem_free(Adapter->htable, Adapter->intr_size); 5066 return (DDI_FAILURE); 5067 } 5068 } 5069 5070 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5071 5072 if (rc != DDI_SUCCESS) { 5073 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5074 "Get interrupt cap failed: %d\n", rc); 5075 5076 /* Free already allocated intr */ 5077 for (y = 0; y < actual; y++) { 5078 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5079 (void) ddi_intr_free(Adapter->htable[y]); 5080 } 5081 5082 kmem_free(Adapter->htable, Adapter->intr_size); 5083 return (DDI_FAILURE); 5084 } 5085 5086 return (DDI_SUCCESS); 5087 } 5088 5089 static int 5090 e1000g_rem_intrs(struct e1000g *Adapter) 5091 { 5092 int x; 5093 int rc; 5094 5095 for (x = 0; x < Adapter->intr_cnt; x++) { 5096 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5097 if (rc != DDI_SUCCESS) { 5098 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5099 "Remove intr handler failed: %d\n", rc); 5100 return (DDI_FAILURE); 5101 } 5102 5103 rc = ddi_intr_free(Adapter->htable[x]); 5104 if (rc != DDI_SUCCESS) { 5105 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5106 "Free intr failed: %d\n", rc); 5107 return (DDI_FAILURE); 5108 } 5109 } 5110 5111 kmem_free(Adapter->htable, Adapter->intr_size); 5112 5113 return (DDI_SUCCESS); 5114 } 5115 5116 static int 5117 e1000g_enable_intrs(struct e1000g *Adapter) 5118 { 5119 int x; 5120 int rc; 5121 5122 /* Enable interrupts */ 5123 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5124 /* Call ddi_intr_block_enable() for MSI */ 5125 rc = ddi_intr_block_enable(Adapter->htable, 5126 Adapter->intr_cnt); 5127 if (rc != DDI_SUCCESS) { 5128 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5129 "Enable block intr failed: %d\n", rc); 5130 return (DDI_FAILURE); 5131 } 5132 } else { 5133 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5134 for (x = 0; x < Adapter->intr_cnt; x++) { 5135 rc = ddi_intr_enable(Adapter->htable[x]); 5136 if (rc != DDI_SUCCESS) { 5137 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5138 "Enable intr failed: %d\n", rc); 5139 return (DDI_FAILURE); 5140 } 5141 } 5142 } 5143 5144 return (DDI_SUCCESS); 5145 } 5146 5147 static int 5148 e1000g_disable_intrs(struct e1000g *Adapter) 5149 { 5150 int x; 5151 int rc; 5152 5153 /* Disable all interrupts */ 5154 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5155 rc = ddi_intr_block_disable(Adapter->htable, 5156 Adapter->intr_cnt); 5157 if (rc != DDI_SUCCESS) { 5158 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5159 "Disable block intr failed: %d\n", rc); 5160 return (DDI_FAILURE); 5161 } 5162 } else { 5163 for (x = 0; x < Adapter->intr_cnt; x++) { 5164 rc = ddi_intr_disable(Adapter->htable[x]); 5165 if (rc != DDI_SUCCESS) { 5166 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5167 "Disable intr failed: %d\n", rc); 5168 return (DDI_FAILURE); 5169 } 5170 } 5171 } 5172 5173 return (DDI_SUCCESS); 5174 } 5175 5176 /* 5177 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5178 */ 5179 static void 5180 e1000g_get_phy_state(struct e1000g *Adapter) 5181 { 5182 struct e1000_hw *hw = &Adapter->shared; 5183 5184 e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5185 e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5186 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 5187 e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 5188 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 5189 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 5190 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &Adapter->phy_1000t_status); 5191 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 5192 5193 Adapter->param_autoneg_cap = 5194 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5195 Adapter->param_pause_cap = 5196 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5197 Adapter->param_asym_pause_cap = 5198 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5199 Adapter->param_1000fdx_cap = 5200 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5201 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5202 Adapter->param_1000hdx_cap = 5203 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5204 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5205 Adapter->param_100t4_cap = 5206 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5207 Adapter->param_100fdx_cap = 5208 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5209 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5210 Adapter->param_100hdx_cap = 5211 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5212 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5213 Adapter->param_10fdx_cap = 5214 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5215 Adapter->param_10hdx_cap = 5216 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5217 5218 Adapter->param_adv_autoneg = hw->mac.autoneg; 5219 Adapter->param_adv_pause = 5220 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5221 Adapter->param_adv_asym_pause = 5222 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5223 Adapter->param_adv_1000hdx = 5224 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5225 Adapter->param_adv_100t4 = 5226 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5227 if (Adapter->param_adv_autoneg == 1) { 5228 Adapter->param_adv_1000fdx = 5229 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5230 Adapter->param_adv_100fdx = 5231 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5232 Adapter->param_adv_100hdx = 5233 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5234 Adapter->param_adv_10fdx = 5235 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5236 Adapter->param_adv_10hdx = 5237 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5238 } 5239 5240 Adapter->param_lp_autoneg = 5241 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5242 Adapter->param_lp_pause = 5243 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5244 Adapter->param_lp_asym_pause = 5245 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5246 Adapter->param_lp_1000fdx = 5247 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5248 Adapter->param_lp_1000hdx = 5249 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5250 Adapter->param_lp_100t4 = 5251 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5252 Adapter->param_lp_100fdx = 5253 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5254 Adapter->param_lp_100hdx = 5255 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5256 Adapter->param_lp_10fdx = 5257 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5258 Adapter->param_lp_10hdx = 5259 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5260 } 5261 5262 /* 5263 * FMA support 5264 */ 5265 5266 int 5267 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5268 { 5269 ddi_fm_error_t de; 5270 5271 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5272 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5273 return (de.fme_status); 5274 } 5275 5276 int 5277 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5278 { 5279 ddi_fm_error_t de; 5280 5281 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5282 return (de.fme_status); 5283 } 5284 5285 /* 5286 * The IO fault service error handling callback function 5287 */ 5288 static int 5289 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5290 { 5291 /* 5292 * as the driver can always deal with an error in any dma or 5293 * access handle, we can just return the fme_status value. 5294 */ 5295 pci_ereport_post(dip, err, NULL); 5296 return (err->fme_status); 5297 } 5298 5299 static void 5300 e1000g_fm_init(struct e1000g *Adapter) 5301 { 5302 ddi_iblock_cookie_t iblk; 5303 int fma_acc_flag, fma_dma_flag; 5304 5305 /* Only register with IO Fault Services if we have some capability */ 5306 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5307 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5308 fma_acc_flag = 1; 5309 } else { 5310 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5311 fma_acc_flag = 0; 5312 } 5313 5314 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5315 fma_dma_flag = 1; 5316 } else { 5317 fma_dma_flag = 0; 5318 } 5319 5320 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5321 5322 if (Adapter->fm_capabilities) { 5323 5324 /* Register capabilities with IO Fault Services */ 5325 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5326 5327 /* 5328 * Initialize pci ereport capabilities if ereport capable 5329 */ 5330 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5331 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5332 pci_ereport_setup(Adapter->dip); 5333 5334 /* 5335 * Register error callback if error callback capable 5336 */ 5337 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5338 ddi_fm_handler_register(Adapter->dip, 5339 e1000g_fm_error_cb, (void*) Adapter); 5340 } 5341 } 5342 5343 static void 5344 e1000g_fm_fini(struct e1000g *Adapter) 5345 { 5346 /* Only unregister FMA capabilities if we registered some */ 5347 if (Adapter->fm_capabilities) { 5348 5349 /* 5350 * Release any resources allocated by pci_ereport_setup() 5351 */ 5352 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5353 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5354 pci_ereport_teardown(Adapter->dip); 5355 5356 /* 5357 * Un-register error callback if error callback capable 5358 */ 5359 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5360 ddi_fm_handler_unregister(Adapter->dip); 5361 5362 /* Unregister from IO Fault Services */ 5363 ddi_fm_fini(Adapter->dip); 5364 } 5365 } 5366 5367 void 5368 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 5369 { 5370 uint64_t ena; 5371 char buf[FM_MAX_CLASS]; 5372 5373 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5374 ena = fm_ena_generate(0, FM_ENA_FMT1); 5375 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 5376 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 5377 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5378 } 5379 } 5380 5381 static int 5382 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 5383 uint_t pr_valsize, void *pr_val) 5384 { 5385 link_flowctrl_t fl; 5386 uint32_t fc; 5387 int err = 0; 5388 5389 ASSERT(pr_valsize > 0); 5390 switch (pr_num) { 5391 case DLD_PROP_AUTONEG: 5392 *(uint8_t *)pr_val = 5393 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0); 5394 break; 5395 case DLD_PROP_FLOWCTRL: 5396 if (pr_valsize < sizeof (link_flowctrl_t)) 5397 return (EINVAL); 5398 fl = LINK_FLOWCTRL_BI; 5399 bcopy(&fl, pr_val, sizeof (fl)); 5400 break; 5401 case DLD_PROP_ADV_1000FDX_CAP: 5402 case DLD_PROP_EN_1000FDX_CAP: 5403 *(uint8_t *)pr_val = 5404 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5405 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5406 break; 5407 case DLD_PROP_ADV_1000HDX_CAP: 5408 case DLD_PROP_EN_1000HDX_CAP: 5409 *(uint8_t *)pr_val = 5410 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5411 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5412 break; 5413 case DLD_PROP_ADV_100FDX_CAP: 5414 case DLD_PROP_EN_100FDX_CAP: 5415 *(uint8_t *)pr_val = 5416 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5417 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5418 case DLD_PROP_ADV_100HDX_CAP: 5419 case DLD_PROP_EN_100HDX_CAP: 5420 *(uint8_t *)pr_val = 5421 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5422 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5423 break; 5424 case DLD_PROP_ADV_10FDX_CAP: 5425 case DLD_PROP_EN_10FDX_CAP: 5426 *(uint8_t *)pr_val = 5427 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5428 break; 5429 case DLD_PROP_ADV_10HDX_CAP: 5430 case DLD_PROP_EN_10HDX_CAP: 5431 *(uint8_t *)pr_val = 5432 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5433 break; 5434 default: 5435 err = ENOTSUP; 5436 break; 5437 } 5438 return (err); 5439 } 5440 5441 /* 5442 * synchronize the adv* and en* parameters. 5443 * 5444 * See comments in <sys/dld.h> for details of the *_en_* 5445 * parameters. The usage of ndd for setting adv parameters will 5446 * synchronize all the en parameters with the e1000g parameters, 5447 * implicity disalbing any settings made via dladm. 5448 */ 5449 static void 5450 e1000g_param_sync(struct e1000g *Adapter) 5451 { 5452 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 5453 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 5454 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 5455 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 5456 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 5457 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 5458 } 5459