1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * ********************************************************************** 30 * * 31 * Module Name: * 32 * e1000g_main.c * 33 * * 34 * Abstract: * 35 * This file contains the interface routines for the solaris OS. * 36 * It has all DDI entry point routines and GLD entry point routines. * 37 * * 38 * This file also contains routines that take care of initialization * 39 * uninit routine and interrupt routine. * 40 * * 41 * ********************************************************************** 42 */ 43 44 #include <sys/dlpi.h> 45 #include <sys/mac.h> 46 #include "e1000g_sw.h" 47 #include "e1000g_debug.h" 48 49 static char ident[] = "Intel PRO/1000 Ethernet 5.2.9"; 50 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 51 static char e1000g_version[] = "Driver Ver. 5.2.9"; 52 53 /* 54 * Proto types for DDI entry points 55 */ 56 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 57 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 58 59 /* 60 * init and intr routines prototype 61 */ 62 static int e1000g_resume(dev_info_t *); 63 static int e1000g_suspend(dev_info_t *); 64 static uint_t e1000g_intr_pciexpress(caddr_t); 65 static uint_t e1000g_intr(caddr_t); 66 static void e1000g_intr_work(struct e1000g *, uint32_t); 67 #pragma inline(e1000g_intr_work) 68 static uint32_t e1000g_get_itr(uint32_t, uint32_t, uint32_t); 69 #pragma inline(e1000g_get_itr) 70 static int e1000g_init(struct e1000g *); 71 static int e1000g_start(struct e1000g *, boolean_t); 72 static void e1000g_stop(struct e1000g *, boolean_t); 73 static int e1000g_m_start(void *); 74 static void e1000g_m_stop(void *); 75 static int e1000g_m_promisc(void *, boolean_t); 76 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 77 static int e1000g_m_unicst(void *, const uint8_t *); 78 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 79 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 80 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 81 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 82 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 83 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 84 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 85 uint_t, const void *); 86 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 87 uint_t, uint_t, void *); 88 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 89 const void *); 90 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 91 uint_t, void *); 92 static void e1000g_init_locks(struct e1000g *); 93 static void e1000g_destroy_locks(struct e1000g *); 94 static int e1000g_identify_hardware(struct e1000g *); 95 static int e1000g_regs_map(struct e1000g *); 96 static int e1000g_set_driver_params(struct e1000g *); 97 static void e1000g_set_bufsize(struct e1000g *); 98 static int e1000g_register_mac(struct e1000g *); 99 static boolean_t e1000g_rx_drain(struct e1000g *); 100 static boolean_t e1000g_tx_drain(struct e1000g *); 101 static void e1000g_init_unicst(struct e1000g *); 102 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 103 104 /* 105 * Local routines 106 */ 107 static void e1000g_tx_clean(struct e1000g *); 108 static void e1000g_rx_clean(struct e1000g *); 109 static void e1000g_link_timer(void *); 110 static void e1000g_local_timer(void *); 111 static boolean_t e1000g_link_check(struct e1000g *); 112 static boolean_t e1000g_stall_check(struct e1000g *); 113 static void e1000g_smartspeed(struct e1000g *); 114 static void e1000g_get_conf(struct e1000g *); 115 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 116 static void enable_watchdog_timer(struct e1000g *); 117 static void disable_watchdog_timer(struct e1000g *); 118 static void start_watchdog_timer(struct e1000g *); 119 static void restart_watchdog_timer(struct e1000g *); 120 static void stop_watchdog_timer(struct e1000g *); 121 static void stop_link_timer(struct e1000g *); 122 static void stop_82547_timer(e1000g_tx_ring_t *); 123 static void e1000g_force_speed_duplex(struct e1000g *); 124 static void e1000g_get_max_frame_size(struct e1000g *); 125 static boolean_t is_valid_mac_addr(uint8_t *); 126 static void e1000g_unattach(dev_info_t *, struct e1000g *); 127 #ifdef E1000G_DEBUG 128 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 129 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 130 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 131 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 132 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 133 struct iocblk *, mblk_t *); 134 #endif 135 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 136 struct iocblk *, mblk_t *); 137 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 138 static void e1000g_set_internal_loopback(struct e1000g *); 139 static void e1000g_set_external_loopback_1000(struct e1000g *); 140 static void e1000g_set_external_loopback_100(struct e1000g *); 141 static void e1000g_set_external_loopback_10(struct e1000g *); 142 static int e1000g_add_intrs(struct e1000g *); 143 static int e1000g_intr_add(struct e1000g *, int); 144 static int e1000g_rem_intrs(struct e1000g *); 145 static int e1000g_enable_intrs(struct e1000g *); 146 static int e1000g_disable_intrs(struct e1000g *); 147 static boolean_t e1000g_link_up(struct e1000g *); 148 #ifdef __sparc 149 static boolean_t e1000g_find_mac_address(struct e1000g *); 150 #endif 151 static void e1000g_get_phy_state(struct e1000g *); 152 static void e1000g_free_priv_devi_node(struct e1000g *, boolean_t); 153 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 154 const void *impl_data); 155 static void e1000g_fm_init(struct e1000g *Adapter); 156 static void e1000g_fm_fini(struct e1000g *Adapter); 157 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 158 static void e1000g_param_sync(struct e1000g *); 159 160 mac_priv_prop_t e1000g_priv_props[] = { 161 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 162 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 163 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 164 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 165 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 166 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 167 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 168 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 169 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 170 {"_intr_adaptive", MAC_PROP_PERM_RW}, 171 {"_tx_recycle_thresh", MAC_PROP_PERM_RW}, 172 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 173 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 174 {"_tx_recycle_num", MAC_PROP_PERM_RW} 175 }; 176 #define E1000G_MAX_PRIV_PROPS \ 177 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 178 179 180 static struct cb_ops cb_ws_ops = { 181 nulldev, /* cb_open */ 182 nulldev, /* cb_close */ 183 nodev, /* cb_strategy */ 184 nodev, /* cb_print */ 185 nodev, /* cb_dump */ 186 nodev, /* cb_read */ 187 nodev, /* cb_write */ 188 nodev, /* cb_ioctl */ 189 nodev, /* cb_devmap */ 190 nodev, /* cb_mmap */ 191 nodev, /* cb_segmap */ 192 nochpoll, /* cb_chpoll */ 193 ddi_prop_op, /* cb_prop_op */ 194 NULL, /* cb_stream */ 195 D_MP | D_HOTPLUG, /* cb_flag */ 196 CB_REV, /* cb_rev */ 197 nodev, /* cb_aread */ 198 nodev /* cb_awrite */ 199 }; 200 201 static struct dev_ops ws_ops = { 202 DEVO_REV, /* devo_rev */ 203 0, /* devo_refcnt */ 204 NULL, /* devo_getinfo */ 205 nulldev, /* devo_identify */ 206 nulldev, /* devo_probe */ 207 e1000g_attach, /* devo_attach */ 208 e1000g_detach, /* devo_detach */ 209 nodev, /* devo_reset */ 210 &cb_ws_ops, /* devo_cb_ops */ 211 NULL, /* devo_bus_ops */ 212 ddi_power /* devo_power */ 213 }; 214 215 static struct modldrv modldrv = { 216 &mod_driverops, /* Type of module. This one is a driver */ 217 ident, /* Discription string */ 218 &ws_ops, /* driver ops */ 219 }; 220 221 static struct modlinkage modlinkage = { 222 MODREV_1, &modldrv, NULL 223 }; 224 225 /* Access attributes for register mapping */ 226 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 227 DDI_DEVICE_ATTR_V0, 228 DDI_STRUCTURE_LE_ACC, 229 DDI_STRICTORDER_ACC, 230 DDI_FLAGERR_ACC 231 }; 232 233 #define E1000G_M_CALLBACK_FLAGS \ 234 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 235 236 static mac_callbacks_t e1000g_m_callbacks = { 237 E1000G_M_CALLBACK_FLAGS, 238 e1000g_m_stat, 239 e1000g_m_start, 240 e1000g_m_stop, 241 e1000g_m_promisc, 242 e1000g_m_multicst, 243 e1000g_m_unicst, 244 e1000g_m_tx, 245 NULL, 246 e1000g_m_ioctl, 247 e1000g_m_getcapab, 248 NULL, 249 NULL, 250 e1000g_m_setprop, 251 e1000g_m_getprop 252 }; 253 254 /* 255 * Global variables 256 */ 257 uint32_t e1000g_mblks_pending = 0; 258 /* 259 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 260 * Here we maintain a private dev_info list if e1000g_force_detach is 261 * enabled. If we force the driver to detach while there are still some 262 * rx buffers retained in the upper layer, we have to keep a copy of the 263 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 264 * structure will be freed after the driver is detached. However when we 265 * finally free those rx buffers released by the upper layer, we need to 266 * refer to the dev_info to free the dma buffers. So we save a copy of 267 * the dev_info for this purpose. On x86 platform, we assume this copy 268 * of dev_info is always valid, but on SPARC platform, it could be invalid 269 * after the system board level DR operation. For this reason, the global 270 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 271 */ 272 #ifdef __sparc 273 boolean_t e1000g_force_detach = B_FALSE; 274 #else 275 boolean_t e1000g_force_detach = B_TRUE; 276 #endif 277 private_devi_list_t *e1000g_private_devi_list = NULL; 278 279 /* 280 * The rwlock is defined to protect the whole processing of rx recycling 281 * and the rx packets release in detach processing to make them mutually 282 * exclusive. 283 * The rx recycling processes different rx packets in different threads, 284 * so it will be protected with RW_READER and it won't block any other rx 285 * recycling threads. 286 * While the detach processing will be protected with RW_WRITER to make 287 * it mutually exclusive with the rx recycling. 288 */ 289 krwlock_t e1000g_rx_detach_lock; 290 /* 291 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 292 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 293 * If there are many e1000g instances, the system may run out of DVMA 294 * resources during the initialization of the instances, then the flag will 295 * be changed to "USE_DMA". Because different e1000g instances are initialized 296 * in parallel, we need to use this lock to protect the flag. 297 */ 298 krwlock_t e1000g_dma_type_lock; 299 300 301 /* 302 * Loadable module configuration entry points for the driver 303 */ 304 305 /* 306 * _init - module initialization 307 */ 308 int 309 _init(void) 310 { 311 int status; 312 313 mac_init_ops(&ws_ops, WSNAME); 314 status = mod_install(&modlinkage); 315 if (status != DDI_SUCCESS) 316 mac_fini_ops(&ws_ops); 317 else { 318 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 319 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 320 } 321 322 return (status); 323 } 324 325 /* 326 * _fini - module finalization 327 */ 328 int 329 _fini(void) 330 { 331 int status; 332 333 rw_enter(&e1000g_rx_detach_lock, RW_READER); 334 if (e1000g_mblks_pending != 0) { 335 rw_exit(&e1000g_rx_detach_lock); 336 return (EBUSY); 337 } 338 rw_exit(&e1000g_rx_detach_lock); 339 340 status = mod_remove(&modlinkage); 341 if (status == DDI_SUCCESS) { 342 mac_fini_ops(&ws_ops); 343 344 if (e1000g_force_detach) { 345 private_devi_list_t *devi_node; 346 347 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 348 while (e1000g_private_devi_list != NULL) { 349 devi_node = e1000g_private_devi_list; 350 e1000g_private_devi_list = 351 e1000g_private_devi_list->next; 352 353 kmem_free(devi_node->priv_dip, 354 sizeof (struct dev_info)); 355 kmem_free(devi_node, 356 sizeof (private_devi_list_t)); 357 } 358 rw_exit(&e1000g_rx_detach_lock); 359 } 360 361 rw_destroy(&e1000g_rx_detach_lock); 362 rw_destroy(&e1000g_dma_type_lock); 363 } 364 365 return (status); 366 } 367 368 /* 369 * _info - module information 370 */ 371 int 372 _info(struct modinfo *modinfop) 373 { 374 return (mod_info(&modlinkage, modinfop)); 375 } 376 377 /* 378 * e1000g_attach - driver attach 379 * 380 * This function is the device-specific initialization entry 381 * point. This entry point is required and must be written. 382 * The DDI_ATTACH command must be provided in the attach entry 383 * point. When attach() is called with cmd set to DDI_ATTACH, 384 * all normal kernel services (such as kmem_alloc(9F)) are 385 * available for use by the driver. 386 * 387 * The attach() function will be called once for each instance 388 * of the device on the system with cmd set to DDI_ATTACH. 389 * Until attach() succeeds, the only driver entry points which 390 * may be called are open(9E) and getinfo(9E). 391 */ 392 static int 393 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 394 { 395 struct e1000g *Adapter; 396 struct e1000_hw *hw; 397 struct e1000g_osdep *osdep; 398 int instance; 399 400 switch (cmd) { 401 default: 402 e1000g_log(NULL, CE_WARN, 403 "Unsupported command send to e1000g_attach... "); 404 return (DDI_FAILURE); 405 406 case DDI_RESUME: 407 return (e1000g_resume(devinfo)); 408 409 case DDI_ATTACH: 410 break; 411 } 412 413 /* 414 * get device instance number 415 */ 416 instance = ddi_get_instance(devinfo); 417 418 /* 419 * Allocate soft data structure 420 */ 421 Adapter = 422 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 423 424 Adapter->dip = devinfo; 425 Adapter->instance = instance; 426 Adapter->tx_ring->adapter = Adapter; 427 Adapter->rx_ring->adapter = Adapter; 428 429 hw = &Adapter->shared; 430 osdep = &Adapter->osdep; 431 hw->back = osdep; 432 osdep->adapter = Adapter; 433 434 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 435 436 /* 437 * Initialize for fma support 438 */ 439 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 440 0, 0x0f, 441 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 442 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 443 e1000g_fm_init(Adapter); 444 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 445 446 /* 447 * PCI Configure 448 */ 449 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 450 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 451 goto attach_fail; 452 } 453 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 454 455 /* 456 * Setup hardware 457 */ 458 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 459 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 460 goto attach_fail; 461 } 462 463 /* 464 * Map in the device registers. 465 */ 466 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 467 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 468 goto attach_fail; 469 } 470 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 471 472 /* 473 * Initialize driver parameters 474 */ 475 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 476 goto attach_fail; 477 } 478 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 479 480 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 481 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 482 goto attach_fail; 483 } 484 485 /* 486 * Initialize interrupts 487 */ 488 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 489 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 490 goto attach_fail; 491 } 492 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 493 494 /* 495 * Initialize mutex's for this device. 496 * Do this before enabling the interrupt handler and 497 * register the softint to avoid the condition where 498 * interrupt handler can try using uninitialized mutex 499 */ 500 e1000g_init_locks(Adapter); 501 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 502 503 /* 504 * Initialize Driver Counters 505 */ 506 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 507 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 508 goto attach_fail; 509 } 510 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 511 512 /* 513 * Initialize chip hardware and software structures 514 */ 515 if (e1000g_init(Adapter) != DDI_SUCCESS) { 516 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 517 goto attach_fail; 518 } 519 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 520 521 /* 522 * Register the driver to the MAC 523 */ 524 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 525 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 526 goto attach_fail; 527 } 528 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 529 530 /* 531 * Now that mutex locks are initialized, and the chip is also 532 * initialized, enable interrupts. 533 */ 534 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 535 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 536 goto attach_fail; 537 } 538 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 539 540 /* 541 * If e1000g_force_detach is enabled, in global private dip list, 542 * we will create a new entry, which maintains the priv_dip for DR 543 * supports after driver detached. 544 */ 545 if (e1000g_force_detach) { 546 private_devi_list_t *devi_node; 547 548 Adapter->priv_dip = 549 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 550 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 551 sizeof (struct dev_info)); 552 553 devi_node = 554 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 555 556 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 557 devi_node->priv_dip = Adapter->priv_dip; 558 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 559 devi_node->next = e1000g_private_devi_list; 560 e1000g_private_devi_list = devi_node; 561 rw_exit(&e1000g_rx_detach_lock); 562 } 563 564 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 565 566 return (DDI_SUCCESS); 567 568 attach_fail: 569 e1000g_unattach(devinfo, Adapter); 570 return (DDI_FAILURE); 571 } 572 573 static int 574 e1000g_register_mac(struct e1000g *Adapter) 575 { 576 struct e1000_hw *hw = &Adapter->shared; 577 mac_register_t *mac; 578 int err; 579 580 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 581 return (DDI_FAILURE); 582 583 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 584 mac->m_driver = Adapter; 585 mac->m_dip = Adapter->dip; 586 mac->m_src_addr = hw->mac.addr; 587 mac->m_callbacks = &e1000g_m_callbacks; 588 mac->m_min_sdu = 0; 589 mac->m_max_sdu = Adapter->default_mtu; 590 mac->m_margin = VLAN_TAGSZ; 591 mac->m_priv_props = e1000g_priv_props; 592 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 593 594 err = mac_register(mac, &Adapter->mh); 595 mac_free(mac); 596 597 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 598 } 599 600 static int 601 e1000g_identify_hardware(struct e1000g *Adapter) 602 { 603 struct e1000_hw *hw = &Adapter->shared; 604 struct e1000g_osdep *osdep = &Adapter->osdep; 605 606 /* Get the device id */ 607 hw->vendor_id = 608 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 609 hw->device_id = 610 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 611 hw->revision_id = 612 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 613 hw->subsystem_device_id = 614 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 615 hw->subsystem_vendor_id = 616 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 617 618 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 619 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 620 "MAC type could not be set properly."); 621 return (DDI_FAILURE); 622 } 623 624 return (DDI_SUCCESS); 625 } 626 627 static int 628 e1000g_regs_map(struct e1000g *Adapter) 629 { 630 dev_info_t *devinfo = Adapter->dip; 631 struct e1000_hw *hw = &Adapter->shared; 632 struct e1000g_osdep *osdep = &Adapter->osdep; 633 off_t mem_size; 634 635 /* 636 * first get the size of device register to be mapped. The 637 * second parameter is the register we are interested. I our 638 * wiseman 0 is for config registers and 1 is for memory mapped 639 * registers Mem size should have memory mapped region size 640 */ 641 if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { 642 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 643 "ddi_dev_regsize for registers failed"); 644 return (DDI_FAILURE); 645 } 646 647 if ((ddi_regs_map_setup(devinfo, 1, /* register of interest */ 648 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 649 &osdep->reg_handle)) != DDI_SUCCESS) { 650 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 651 "ddi_regs_map_setup for registers failed"); 652 goto regs_map_fail; 653 } 654 655 /* ICH needs to map flash memory */ 656 if (hw->mac.type == e1000_ich8lan || hw->mac.type == e1000_ich9lan) { 657 /* get flash size */ 658 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 659 &mem_size) != DDI_SUCCESS) { 660 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 661 "ddi_dev_regsize for ICH flash failed"); 662 goto regs_map_fail; 663 } 664 665 /* map flash in */ 666 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 667 (caddr_t *)&hw->flash_address, 0, 668 mem_size, &e1000g_regs_acc_attr, 669 &osdep->ich_flash_handle) != DDI_SUCCESS) { 670 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 671 "ddi_regs_map_setup for ICH flash failed"); 672 goto regs_map_fail; 673 } 674 } 675 676 return (DDI_SUCCESS); 677 678 regs_map_fail: 679 if (osdep->reg_handle != NULL) 680 ddi_regs_map_free(&osdep->reg_handle); 681 682 return (DDI_FAILURE); 683 } 684 685 static int 686 e1000g_set_driver_params(struct e1000g *Adapter) 687 { 688 struct e1000_hw *hw; 689 e1000g_tx_ring_t *tx_ring; 690 uint32_t mem_bar, io_bar, bar64; 691 692 hw = &Adapter->shared; 693 694 /* Set MAC type and initialize hardware functions */ 695 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 696 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 697 "Could not setup hardware functions"); 698 return (DDI_FAILURE); 699 } 700 701 /* Get bus information */ 702 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 703 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 704 "Could not get bus information"); 705 return (DDI_FAILURE); 706 } 707 708 /* get mem_base addr */ 709 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 710 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 711 712 /* get io_base addr */ 713 if (hw->mac.type >= e1000_82544) { 714 if (bar64) { 715 /* IO BAR is different for 64 bit BAR mode */ 716 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 717 PCI_CONF_BASE4); 718 } else { 719 /* normal 32-bit BAR mode */ 720 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 721 PCI_CONF_BASE2); 722 } 723 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 724 } else { 725 /* no I/O access for adapters prior to 82544 */ 726 hw->io_base = 0x0; 727 } 728 729 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 730 731 hw->mac.autoneg_failed = B_TRUE; 732 733 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 734 hw->phy.autoneg_wait_to_complete = B_FALSE; 735 736 /* Adaptive IFS related changes */ 737 hw->mac.adaptive_ifs = B_TRUE; 738 739 /* Enable phy init script for IGP phy of 82541/82547 */ 740 if ((hw->mac.type == e1000_82547) || 741 (hw->mac.type == e1000_82541) || 742 (hw->mac.type == e1000_82547_rev_2) || 743 (hw->mac.type == e1000_82541_rev_2)) 744 e1000_init_script_state_82541(hw, B_TRUE); 745 746 /* Enable the TTL workaround for 82541/82547 */ 747 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 748 749 #ifdef __sparc 750 Adapter->strip_crc = B_TRUE; 751 #else 752 Adapter->strip_crc = B_FALSE; 753 #endif 754 755 /* Get conf file properties */ 756 e1000g_get_conf(Adapter); 757 758 /* Get speed/duplex settings in conf file */ 759 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 760 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 761 e1000g_force_speed_duplex(Adapter); 762 763 /* Get Jumbo Frames settings in conf file */ 764 e1000g_get_max_frame_size(Adapter); 765 766 /* Set Rx/Tx buffer size */ 767 e1000g_set_bufsize(Adapter); 768 769 /* Master Latency Timer */ 770 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 771 772 /* copper options */ 773 if (hw->phy.media_type == e1000_media_type_copper) { 774 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 775 hw->phy.disable_polarity_correction = B_FALSE; 776 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 777 } 778 779 /* The initial link state should be "unknown" */ 780 Adapter->link_state = LINK_STATE_UNKNOWN; 781 782 /* Initialize rx parameters */ 783 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 784 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 785 786 /* Initialize tx parameters */ 787 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 788 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 789 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 790 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 791 792 tx_ring = Adapter->tx_ring; 793 tx_ring->frags_limit = 794 (Adapter->max_frame_size / Adapter->tx_bcopy_thresh) + 2; 795 if (tx_ring->frags_limit > (MAX_TX_DESC_PER_PACKET >> 1)) 796 tx_ring->frags_limit = (MAX_TX_DESC_PER_PACKET >> 1); 797 798 /* Initialize rx parameters */ 799 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 800 801 return (DDI_SUCCESS); 802 } 803 804 static void 805 e1000g_set_bufsize(struct e1000g *Adapter) 806 { 807 struct e1000_mac_info *mac = &Adapter->shared.mac; 808 uint64_t rx_size; 809 uint64_t tx_size; 810 811 #ifdef __sparc 812 dev_info_t *devinfo = Adapter->dip; 813 ulong_t iommu_pagesize; 814 815 /* Get the system page size */ 816 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 817 iommu_pagesize = dvma_pagesize(devinfo); 818 if (iommu_pagesize != 0) { 819 if (Adapter->sys_page_sz == iommu_pagesize) { 820 if (iommu_pagesize > 0x4000) 821 Adapter->sys_page_sz = 0x4000; 822 } else { 823 if (Adapter->sys_page_sz > iommu_pagesize) 824 Adapter->sys_page_sz = iommu_pagesize; 825 } 826 } 827 Adapter->dvma_page_num = Adapter->max_frame_size / 828 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 829 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 830 #endif 831 832 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 833 834 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 835 if ((rx_size > FRAME_SIZE_UPTO_2K) && (rx_size <= FRAME_SIZE_UPTO_4K)) 836 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 837 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 838 (rx_size <= FRAME_SIZE_UPTO_8K)) 839 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 840 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 841 (rx_size <= FRAME_SIZE_UPTO_16K)) 842 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 843 else 844 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 845 846 tx_size = Adapter->max_frame_size; 847 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 848 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 849 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 850 (tx_size <= FRAME_SIZE_UPTO_8K)) 851 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 852 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 853 (tx_size <= FRAME_SIZE_UPTO_16K)) 854 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 855 else 856 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 857 858 /* 859 * For Wiseman adapters we have an requirement of having receive 860 * buffers aligned at 256 byte boundary. Since Livengood does not 861 * require this and forcing it for all hardwares will have 862 * performance implications, I am making it applicable only for 863 * Wiseman and for Jumbo frames enabled mode as rest of the time, 864 * it is okay to have normal frames...but it does involve a 865 * potential risk where we may loose data if buffer is not 866 * aligned...so all wiseman boards to have 256 byte aligned 867 * buffers 868 */ 869 if (mac->type < e1000_82543) 870 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 871 else 872 Adapter->rx_buf_align = 1; 873 } 874 875 /* 876 * e1000g_detach - driver detach 877 * 878 * The detach() function is the complement of the attach routine. 879 * If cmd is set to DDI_DETACH, detach() is used to remove the 880 * state associated with a given instance of a device node 881 * prior to the removal of that instance from the system. 882 * 883 * The detach() function will be called once for each instance 884 * of the device for which there has been a successful attach() 885 * once there are no longer any opens on the device. 886 * 887 * Interrupts routine are disabled, All memory allocated by this 888 * driver are freed. 889 */ 890 static int 891 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 892 { 893 struct e1000g *Adapter; 894 boolean_t rx_drain; 895 896 switch (cmd) { 897 default: 898 return (DDI_FAILURE); 899 900 case DDI_SUSPEND: 901 return (e1000g_suspend(devinfo)); 902 903 case DDI_DETACH: 904 break; 905 } 906 907 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 908 if (Adapter == NULL) 909 return (DDI_FAILURE); 910 911 if (mac_unregister(Adapter->mh) != 0) { 912 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 913 return (DDI_FAILURE); 914 } 915 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 916 917 918 if (Adapter->chip_state != E1000G_STOP) 919 e1000g_stop(Adapter, B_TRUE); 920 921 rx_drain = e1000g_rx_drain(Adapter); 922 923 /* 924 * If e1000g_force_detach is enabled, driver detach is safe. 925 * We will let e1000g_free_priv_devi_node routine determine 926 * whether we need to free the priv_dip entry for current 927 * driver instance. 928 */ 929 if (e1000g_force_detach) { 930 e1000g_free_priv_devi_node(Adapter, rx_drain); 931 } else { 932 if (!rx_drain) 933 return (DDI_FAILURE); 934 } 935 936 e1000g_unattach(devinfo, Adapter); 937 938 return (DDI_SUCCESS); 939 } 940 941 /* 942 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 943 * 944 * If free_flag is true, that indicates the upper layer is not holding 945 * the rx buffers, we could free the priv_dip entry safely. 946 * 947 * Otherwise, we have to keep this entry even after driver detached, 948 * and we also need to mark this entry with E1000G_PRIV_DEVI_DETACH flag, 949 * so that driver could free it while all of rx buffers are returned 950 * by upper layer later. 951 */ 952 static void 953 e1000g_free_priv_devi_node(struct e1000g *Adapter, boolean_t free_flag) 954 { 955 private_devi_list_t *devi_node, *devi_del; 956 957 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 958 ASSERT(e1000g_private_devi_list != NULL); 959 ASSERT(Adapter->priv_dip != NULL); 960 961 devi_node = e1000g_private_devi_list; 962 if (devi_node->priv_dip == Adapter->priv_dip) { 963 if (free_flag) { 964 e1000g_private_devi_list = 965 devi_node->next; 966 kmem_free(devi_node->priv_dip, 967 sizeof (struct dev_info)); 968 kmem_free(devi_node, 969 sizeof (private_devi_list_t)); 970 } else { 971 ASSERT(e1000g_mblks_pending != 0); 972 devi_node->flag = 973 E1000G_PRIV_DEVI_DETACH; 974 } 975 rw_exit(&e1000g_rx_detach_lock); 976 return; 977 } 978 979 devi_node = e1000g_private_devi_list; 980 while (devi_node->next != NULL) { 981 if (devi_node->next->priv_dip == Adapter->priv_dip) { 982 if (free_flag) { 983 devi_del = devi_node->next; 984 devi_node->next = devi_del->next; 985 kmem_free(devi_del->priv_dip, 986 sizeof (struct dev_info)); 987 kmem_free(devi_del, 988 sizeof (private_devi_list_t)); 989 } else { 990 ASSERT(e1000g_mblks_pending != 0); 991 devi_node->next->flag = 992 E1000G_PRIV_DEVI_DETACH; 993 } 994 break; 995 } 996 devi_node = devi_node->next; 997 } 998 rw_exit(&e1000g_rx_detach_lock); 999 } 1000 1001 static void 1002 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1003 { 1004 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1005 (void) e1000g_disable_intrs(Adapter); 1006 } 1007 1008 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1009 (void) mac_unregister(Adapter->mh); 1010 } 1011 1012 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1013 (void) e1000g_rem_intrs(Adapter); 1014 } 1015 1016 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1017 (void) ddi_prop_remove_all(devinfo); 1018 } 1019 1020 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1021 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1022 } 1023 1024 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1025 stop_link_timer(Adapter); 1026 if (e1000_reset_hw(&Adapter->shared) != 0) { 1027 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1028 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1029 } 1030 } 1031 1032 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1033 if (Adapter->osdep.reg_handle != NULL) 1034 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1035 if (Adapter->osdep.ich_flash_handle != NULL) 1036 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1037 } 1038 1039 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1040 if (Adapter->osdep.cfg_handle != NULL) 1041 pci_config_teardown(&Adapter->osdep.cfg_handle); 1042 } 1043 1044 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1045 e1000g_destroy_locks(Adapter); 1046 } 1047 1048 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1049 e1000g_fm_fini(Adapter); 1050 } 1051 1052 e1000_remove_device(&Adapter->shared); 1053 1054 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1055 1056 /* 1057 * Another hotplug spec requirement, 1058 * run ddi_set_driver_private(devinfo, null); 1059 */ 1060 ddi_set_driver_private(devinfo, NULL); 1061 } 1062 1063 static void 1064 e1000g_init_locks(struct e1000g *Adapter) 1065 { 1066 e1000g_tx_ring_t *tx_ring; 1067 e1000g_rx_ring_t *rx_ring; 1068 1069 rw_init(&Adapter->chip_lock, NULL, 1070 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1071 mutex_init(&Adapter->link_lock, NULL, 1072 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1073 mutex_init(&Adapter->watchdog_lock, NULL, 1074 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1075 1076 tx_ring = Adapter->tx_ring; 1077 1078 mutex_init(&tx_ring->tx_lock, NULL, 1079 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1080 mutex_init(&tx_ring->usedlist_lock, NULL, 1081 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1082 mutex_init(&tx_ring->freelist_lock, NULL, 1083 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1084 1085 rx_ring = Adapter->rx_ring; 1086 1087 mutex_init(&rx_ring->freelist_lock, NULL, 1088 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1089 } 1090 1091 static void 1092 e1000g_destroy_locks(struct e1000g *Adapter) 1093 { 1094 e1000g_tx_ring_t *tx_ring; 1095 e1000g_rx_ring_t *rx_ring; 1096 1097 tx_ring = Adapter->tx_ring; 1098 mutex_destroy(&tx_ring->tx_lock); 1099 mutex_destroy(&tx_ring->usedlist_lock); 1100 mutex_destroy(&tx_ring->freelist_lock); 1101 1102 rx_ring = Adapter->rx_ring; 1103 mutex_destroy(&rx_ring->freelist_lock); 1104 1105 mutex_destroy(&Adapter->link_lock); 1106 mutex_destroy(&Adapter->watchdog_lock); 1107 rw_destroy(&Adapter->chip_lock); 1108 } 1109 1110 static int 1111 e1000g_resume(dev_info_t *devinfo) 1112 { 1113 struct e1000g *Adapter; 1114 1115 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1116 if (Adapter == NULL) 1117 return (DDI_FAILURE); 1118 1119 if (e1000g_start(Adapter, B_TRUE)) 1120 return (DDI_FAILURE); 1121 1122 return (DDI_SUCCESS); 1123 } 1124 1125 static int 1126 e1000g_suspend(dev_info_t *devinfo) 1127 { 1128 struct e1000g *Adapter; 1129 1130 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1131 if (Adapter == NULL) 1132 return (DDI_FAILURE); 1133 1134 e1000g_stop(Adapter, B_TRUE); 1135 1136 return (DDI_SUCCESS); 1137 } 1138 1139 static int 1140 e1000g_init(struct e1000g *Adapter) 1141 { 1142 uint32_t pba; 1143 uint32_t high_water; 1144 struct e1000_hw *hw; 1145 clock_t link_timeout; 1146 1147 hw = &Adapter->shared; 1148 1149 rw_enter(&Adapter->chip_lock, RW_WRITER); 1150 1151 /* 1152 * reset to put the hardware in a known state 1153 * before we try to do anything with the eeprom 1154 */ 1155 if (e1000_reset_hw(hw) != 0) { 1156 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1157 goto init_fail; 1158 } 1159 1160 if (e1000_validate_nvm_checksum(hw) < 0) { 1161 /* 1162 * Some PCI-E parts fail the first check due to 1163 * the link being in sleep state. Call it again, 1164 * if it fails a second time its a real issue. 1165 */ 1166 if (e1000_validate_nvm_checksum(hw) < 0) { 1167 e1000g_log(Adapter, CE_WARN, 1168 "Invalid NVM checksum. Please contact " 1169 "the vendor to update the NVM."); 1170 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1171 goto init_fail; 1172 } 1173 } 1174 1175 #ifdef __sparc 1176 /* 1177 * Firstly, we try to get the local ethernet address from OBP. If 1178 * fail, we get from EEPROM of NIC card. 1179 */ 1180 if (!e1000g_find_mac_address(Adapter)) { 1181 if (e1000_read_mac_addr(hw) < 0) { 1182 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1183 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1184 goto init_fail; 1185 } 1186 } 1187 #else 1188 /* Get the local ethernet address. */ 1189 if (e1000_read_mac_addr(hw) < 0) { 1190 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1191 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1192 goto init_fail; 1193 } 1194 #endif 1195 1196 /* check for valid mac address */ 1197 if (!is_valid_mac_addr(hw->mac.addr)) { 1198 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1199 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1200 goto init_fail; 1201 } 1202 1203 /* Set LAA state for 82571 chipset */ 1204 e1000_set_laa_state_82571(hw, B_TRUE); 1205 1206 /* Master Latency Timer implementation */ 1207 if (Adapter->master_latency_timer) { 1208 pci_config_put8(Adapter->osdep.cfg_handle, 1209 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1210 } 1211 1212 if (hw->mac.type < e1000_82547) { 1213 /* 1214 * Total FIFO is 64K 1215 */ 1216 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1217 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1218 else 1219 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1220 } else if (hw->mac.type >= e1000_82571 && 1221 hw->mac.type <= e1000_82572) { 1222 /* 1223 * Total FIFO is 48K 1224 */ 1225 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1226 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1227 else 1228 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1229 } else if (hw->mac.type == e1000_ich8lan) { 1230 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1231 } else if (hw->mac.type == e1000_ich9lan) { 1232 pba = E1000_PBA_12K; 1233 } else { 1234 /* 1235 * Total FIFO is 40K 1236 */ 1237 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1238 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1239 else 1240 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1241 } 1242 E1000_WRITE_REG(hw, E1000_PBA, pba); 1243 1244 /* 1245 * These parameters set thresholds for the adapter's generation(Tx) 1246 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1247 * settings. Flow control is enabled or disabled in the configuration 1248 * file. 1249 * High-water mark is set down from the top of the rx fifo (not 1250 * sensitive to max_frame_size) and low-water is set just below 1251 * high-water mark. 1252 * The high water mark must be low enough to fit one full frame above 1253 * it in the rx FIFO. Should be the lower of: 1254 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1255 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1256 * Rx FIFO size minus one full frame. 1257 */ 1258 high_water = min(((pba << 10) * 9 / 10), 1259 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_ich9lan) ? 1260 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1261 ((pba << 10) - Adapter->max_frame_size))); 1262 1263 hw->fc.high_water = high_water & 0xFFF8; 1264 hw->fc.low_water = hw->fc.high_water - 8; 1265 1266 if (hw->mac.type == e1000_80003es2lan) 1267 hw->fc.pause_time = 0xFFFF; 1268 else 1269 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1270 hw->fc.send_xon = B_TRUE; 1271 1272 /* 1273 * Reset the adapter hardware the second time. 1274 */ 1275 if (e1000_reset_hw(hw) != 0) { 1276 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1277 goto init_fail; 1278 } 1279 1280 /* disable wakeup control by default */ 1281 if (hw->mac.type >= e1000_82544) 1282 E1000_WRITE_REG(hw, E1000_WUC, 0); 1283 1284 /* MWI setup */ 1285 e1000_pci_set_mwi(hw); 1286 1287 /* 1288 * Configure/Initialize hardware 1289 */ 1290 if (e1000_init_hw(hw) < 0) { 1291 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1292 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1293 goto init_fail; 1294 } 1295 1296 /* Disable Smart Power Down */ 1297 phy_spd_state(hw, B_FALSE); 1298 1299 /* Make sure driver has control */ 1300 e1000g_get_driver_control(hw); 1301 1302 /* 1303 * Initialize unicast addresses. 1304 */ 1305 e1000g_init_unicst(Adapter); 1306 1307 /* 1308 * Setup and initialize the mctable structures. After this routine 1309 * completes Multicast table will be set 1310 */ 1311 e1000g_setup_multicast(Adapter); 1312 msec_delay(5); 1313 1314 /* 1315 * Implement Adaptive IFS 1316 */ 1317 e1000_reset_adaptive(hw); 1318 1319 /* Setup Interrupt Throttling Register */ 1320 if (hw->mac.type >= e1000_82540) { 1321 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1322 } else 1323 Adapter->intr_adaptive = B_FALSE; 1324 1325 /* Start the timer for link setup */ 1326 if (hw->mac.autoneg) 1327 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1328 else 1329 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1330 1331 mutex_enter(&Adapter->link_lock); 1332 if (hw->phy.autoneg_wait_to_complete) { 1333 Adapter->link_complete = B_TRUE; 1334 } else { 1335 Adapter->link_complete = B_FALSE; 1336 Adapter->link_tid = timeout(e1000g_link_timer, 1337 (void *)Adapter, link_timeout); 1338 } 1339 mutex_exit(&Adapter->link_lock); 1340 1341 /* Enable PCI-Ex master */ 1342 if (hw->bus.type == e1000_bus_type_pci_express) { 1343 e1000_enable_pciex_master(hw); 1344 } 1345 1346 /* Save the state of the phy */ 1347 e1000g_get_phy_state(Adapter); 1348 1349 e1000g_param_sync(Adapter); 1350 1351 Adapter->init_count++; 1352 1353 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1354 goto init_fail; 1355 } 1356 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1357 goto init_fail; 1358 } 1359 1360 rw_exit(&Adapter->chip_lock); 1361 1362 return (DDI_SUCCESS); 1363 1364 init_fail: 1365 rw_exit(&Adapter->chip_lock); 1366 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1367 return (DDI_FAILURE); 1368 } 1369 1370 /* 1371 * Check if the link is up 1372 */ 1373 static boolean_t 1374 e1000g_link_up(struct e1000g *Adapter) 1375 { 1376 struct e1000_hw *hw; 1377 boolean_t link_up; 1378 1379 hw = &Adapter->shared; 1380 1381 e1000_check_for_link(hw); 1382 1383 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1384 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1385 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1386 (hw->mac.serdes_has_link))) { 1387 link_up = B_TRUE; 1388 } else { 1389 link_up = B_FALSE; 1390 } 1391 1392 return (link_up); 1393 } 1394 1395 static void 1396 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1397 { 1398 struct iocblk *iocp; 1399 struct e1000g *e1000gp; 1400 enum ioc_reply status; 1401 int err; 1402 1403 iocp = (struct iocblk *)mp->b_rptr; 1404 iocp->ioc_error = 0; 1405 e1000gp = (struct e1000g *)arg; 1406 1407 ASSERT(e1000gp); 1408 if (e1000gp == NULL) { 1409 miocnak(q, mp, 0, EINVAL); 1410 return; 1411 } 1412 1413 switch (iocp->ioc_cmd) { 1414 1415 case LB_GET_INFO_SIZE: 1416 case LB_GET_INFO: 1417 case LB_GET_MODE: 1418 case LB_SET_MODE: 1419 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1420 break; 1421 1422 1423 #ifdef E1000G_DEBUG 1424 case E1000G_IOC_REG_PEEK: 1425 case E1000G_IOC_REG_POKE: 1426 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1427 break; 1428 case E1000G_IOC_CHIP_RESET: 1429 e1000gp->reset_count++; 1430 if (e1000g_reset(e1000gp)) 1431 status = IOC_ACK; 1432 else 1433 status = IOC_INVAL; 1434 break; 1435 #endif 1436 default: 1437 status = IOC_INVAL; 1438 break; 1439 } 1440 1441 /* 1442 * Decide how to reply 1443 */ 1444 switch (status) { 1445 default: 1446 case IOC_INVAL: 1447 /* 1448 * Error, reply with a NAK and EINVAL or the specified error 1449 */ 1450 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1451 EINVAL : iocp->ioc_error); 1452 break; 1453 1454 case IOC_DONE: 1455 /* 1456 * OK, reply already sent 1457 */ 1458 break; 1459 1460 case IOC_ACK: 1461 /* 1462 * OK, reply with an ACK 1463 */ 1464 miocack(q, mp, 0, 0); 1465 break; 1466 1467 case IOC_REPLY: 1468 /* 1469 * OK, send prepared reply as ACK or NAK 1470 */ 1471 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1472 M_IOCACK : M_IOCNAK; 1473 qreply(q, mp); 1474 break; 1475 } 1476 } 1477 1478 static int 1479 e1000g_m_start(void *arg) 1480 { 1481 struct e1000g *Adapter = (struct e1000g *)arg; 1482 1483 return (e1000g_start(Adapter, B_TRUE)); 1484 } 1485 1486 static int 1487 e1000g_start(struct e1000g *Adapter, boolean_t global) 1488 { 1489 if (global) { 1490 /* Allocate dma resources for descriptors and buffers */ 1491 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1492 e1000g_log(Adapter, CE_WARN, 1493 "Alloc DMA resources failed"); 1494 return (ENOTACTIVE); 1495 } 1496 Adapter->rx_buffer_setup = B_FALSE; 1497 } 1498 1499 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1500 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1501 e1000g_log(Adapter, CE_WARN, 1502 "Adapter initialization failed"); 1503 if (global) 1504 e1000g_release_dma_resources(Adapter); 1505 return (ENOTACTIVE); 1506 } 1507 } 1508 1509 rw_enter(&Adapter->chip_lock, RW_WRITER); 1510 1511 /* Setup and initialize the transmit structures */ 1512 e1000g_tx_setup(Adapter); 1513 msec_delay(5); 1514 1515 /* Setup and initialize the receive structures */ 1516 e1000g_rx_setup(Adapter); 1517 msec_delay(5); 1518 1519 e1000g_mask_interrupt(Adapter); 1520 1521 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1522 rw_exit(&Adapter->chip_lock); 1523 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1524 return (ENOTACTIVE); 1525 } 1526 1527 Adapter->chip_state = E1000G_START; 1528 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1529 1530 rw_exit(&Adapter->chip_lock); 1531 1532 /* Enable and start the watchdog timer */ 1533 enable_watchdog_timer(Adapter); 1534 1535 return (0); 1536 } 1537 1538 static void 1539 e1000g_m_stop(void *arg) 1540 { 1541 struct e1000g *Adapter = (struct e1000g *)arg; 1542 1543 e1000g_stop(Adapter, B_TRUE); 1544 } 1545 1546 static void 1547 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1548 { 1549 /* Set stop flags */ 1550 rw_enter(&Adapter->chip_lock, RW_WRITER); 1551 1552 Adapter->chip_state = E1000G_STOP; 1553 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1554 1555 rw_exit(&Adapter->chip_lock); 1556 1557 /* Drain tx sessions */ 1558 (void) e1000g_tx_drain(Adapter); 1559 1560 /* Disable and stop all the timers */ 1561 disable_watchdog_timer(Adapter); 1562 stop_link_timer(Adapter); 1563 stop_82547_timer(Adapter->tx_ring); 1564 1565 /* Stop the chip and release pending resources */ 1566 rw_enter(&Adapter->chip_lock, RW_WRITER); 1567 1568 e1000g_clear_all_interrupts(Adapter); 1569 if (e1000_reset_hw(&Adapter->shared) != 0) { 1570 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1571 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1572 } 1573 1574 /* Release resources still held by the TX descriptors */ 1575 e1000g_tx_clean(Adapter); 1576 1577 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1578 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1579 1580 /* Clean the pending rx jumbo packet fragment */ 1581 e1000g_rx_clean(Adapter); 1582 1583 rw_exit(&Adapter->chip_lock); 1584 1585 if (global) 1586 e1000g_release_dma_resources(Adapter); 1587 } 1588 1589 static void 1590 e1000g_rx_clean(struct e1000g *Adapter) 1591 { 1592 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 1593 1594 if (rx_ring->rx_mblk != NULL) { 1595 freemsg(rx_ring->rx_mblk); 1596 rx_ring->rx_mblk = NULL; 1597 rx_ring->rx_mblk_tail = NULL; 1598 rx_ring->rx_mblk_len = 0; 1599 } 1600 } 1601 1602 static void 1603 e1000g_tx_clean(struct e1000g *Adapter) 1604 { 1605 e1000g_tx_ring_t *tx_ring; 1606 p_tx_sw_packet_t packet; 1607 mblk_t *mp; 1608 mblk_t *nmp; 1609 uint32_t packet_count; 1610 1611 tx_ring = Adapter->tx_ring; 1612 1613 /* 1614 * Here we don't need to protect the lists using 1615 * the usedlist_lock and freelist_lock, for they 1616 * have been protected by the chip_lock. 1617 */ 1618 mp = NULL; 1619 nmp = NULL; 1620 packet_count = 0; 1621 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1622 while (packet != NULL) { 1623 if (packet->mp != NULL) { 1624 /* Assemble the message chain */ 1625 if (mp == NULL) { 1626 mp = packet->mp; 1627 nmp = packet->mp; 1628 } else { 1629 nmp->b_next = packet->mp; 1630 nmp = packet->mp; 1631 } 1632 /* Disconnect the message from the sw packet */ 1633 packet->mp = NULL; 1634 } 1635 1636 e1000g_free_tx_swpkt(packet); 1637 packet_count++; 1638 1639 packet = (p_tx_sw_packet_t) 1640 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1641 } 1642 1643 if (mp != NULL) 1644 freemsgchain(mp); 1645 1646 if (packet_count > 0) { 1647 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1648 QUEUE_INIT_LIST(&tx_ring->used_list); 1649 1650 /* Setup TX descriptor pointers */ 1651 tx_ring->tbd_next = tx_ring->tbd_first; 1652 tx_ring->tbd_oldest = tx_ring->tbd_first; 1653 1654 /* Setup our HW Tx Head & Tail descriptor pointers */ 1655 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1656 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1657 } 1658 } 1659 1660 static boolean_t 1661 e1000g_tx_drain(struct e1000g *Adapter) 1662 { 1663 int i; 1664 boolean_t done; 1665 e1000g_tx_ring_t *tx_ring; 1666 1667 tx_ring = Adapter->tx_ring; 1668 1669 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1670 for (i = 0; i < TX_DRAIN_TIME; i++) { 1671 mutex_enter(&tx_ring->usedlist_lock); 1672 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1673 mutex_exit(&tx_ring->usedlist_lock); 1674 1675 if (done) 1676 break; 1677 1678 msec_delay(1); 1679 } 1680 1681 return (done); 1682 } 1683 1684 static boolean_t 1685 e1000g_rx_drain(struct e1000g *Adapter) 1686 { 1687 e1000g_rx_ring_t *rx_ring; 1688 p_rx_sw_packet_t packet; 1689 boolean_t done; 1690 1691 rx_ring = Adapter->rx_ring; 1692 done = B_TRUE; 1693 1694 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 1695 1696 while (rx_ring->pending_list != NULL) { 1697 packet = rx_ring->pending_list; 1698 rx_ring->pending_list = 1699 rx_ring->pending_list->next; 1700 1701 if (packet->flag == E1000G_RX_SW_STOP) { 1702 packet->flag = E1000G_RX_SW_DETACH; 1703 done = B_FALSE; 1704 } else { 1705 ASSERT(packet->flag == E1000G_RX_SW_FREE); 1706 ASSERT(packet->mp == NULL); 1707 e1000g_free_rx_sw_packet(packet); 1708 } 1709 } 1710 1711 rw_exit(&e1000g_rx_detach_lock); 1712 1713 return (done); 1714 } 1715 1716 boolean_t 1717 e1000g_reset(struct e1000g *Adapter) 1718 { 1719 e1000g_stop(Adapter, B_FALSE); 1720 1721 if (e1000g_start(Adapter, B_FALSE)) { 1722 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1723 return (B_FALSE); 1724 } 1725 1726 return (B_TRUE); 1727 } 1728 1729 boolean_t 1730 e1000g_global_reset(struct e1000g *Adapter) 1731 { 1732 e1000g_stop(Adapter, B_TRUE); 1733 1734 Adapter->init_count = 0; 1735 1736 if (e1000g_start(Adapter, B_TRUE)) { 1737 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1738 return (B_FALSE); 1739 } 1740 1741 return (B_TRUE); 1742 } 1743 1744 /* 1745 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 1746 * 1747 * This interrupt service routine is for PCI-Express adapters. 1748 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 1749 * bit is set. 1750 */ 1751 static uint_t 1752 e1000g_intr_pciexpress(caddr_t arg) 1753 { 1754 struct e1000g *Adapter; 1755 uint32_t icr; 1756 1757 Adapter = (struct e1000g *)arg; 1758 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1759 1760 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1761 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1762 1763 if (icr & E1000_ICR_INT_ASSERTED) { 1764 /* 1765 * E1000_ICR_INT_ASSERTED bit was set: 1766 * Read(Clear) the ICR, claim this interrupt, 1767 * look for work to do. 1768 */ 1769 e1000g_intr_work(Adapter, icr); 1770 return (DDI_INTR_CLAIMED); 1771 } else { 1772 /* 1773 * E1000_ICR_INT_ASSERTED bit was not set: 1774 * Don't claim this interrupt, return immediately. 1775 */ 1776 return (DDI_INTR_UNCLAIMED); 1777 } 1778 } 1779 1780 /* 1781 * e1000g_intr - ISR for PCI/PCI-X chipsets 1782 * 1783 * This interrupt service routine is for PCI/PCI-X adapters. 1784 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 1785 * bit is set or not. 1786 */ 1787 static uint_t 1788 e1000g_intr(caddr_t arg) 1789 { 1790 struct e1000g *Adapter; 1791 uint32_t icr; 1792 1793 Adapter = (struct e1000g *)arg; 1794 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1795 1796 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1797 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1798 1799 if (icr) { 1800 /* 1801 * Any bit was set in ICR: 1802 * Read(Clear) the ICR, claim this interrupt, 1803 * look for work to do. 1804 */ 1805 e1000g_intr_work(Adapter, icr); 1806 return (DDI_INTR_CLAIMED); 1807 } else { 1808 /* 1809 * No bit was set in ICR: 1810 * Don't claim this interrupt, return immediately. 1811 */ 1812 return (DDI_INTR_UNCLAIMED); 1813 } 1814 } 1815 1816 /* 1817 * e1000g_intr_work - actual processing of ISR 1818 * 1819 * Read(clear) the ICR contents and call appropriate interrupt 1820 * processing routines. 1821 */ 1822 static void 1823 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 1824 { 1825 struct e1000_hw *hw; 1826 hw = &Adapter->shared; 1827 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 1828 uint32_t itr; 1829 1830 Adapter->rx_pkt_cnt = 0; 1831 Adapter->tx_pkt_cnt = 0; 1832 1833 rw_enter(&Adapter->chip_lock, RW_READER); 1834 /* 1835 * Here we need to check the "chip_state" flag within the chip_lock to 1836 * ensure the receive routine will not execute when the adapter is 1837 * being reset. 1838 */ 1839 if (Adapter->chip_state != E1000G_START) { 1840 rw_exit(&Adapter->chip_lock); 1841 return; 1842 } 1843 1844 if (icr & E1000_ICR_RXT0) { 1845 mblk_t *mp; 1846 1847 mutex_enter(&Adapter->rx_ring->rx_lock); 1848 mp = e1000g_receive(Adapter); 1849 mutex_exit(&Adapter->rx_ring->rx_lock); 1850 1851 rw_exit(&Adapter->chip_lock); 1852 1853 if (mp != NULL) 1854 mac_rx(Adapter->mh, Adapter->mrh, mp); 1855 } else 1856 rw_exit(&Adapter->chip_lock); 1857 1858 if (icr & E1000_ICR_TXDW) { 1859 if (!Adapter->tx_intr_enable) 1860 e1000g_clear_tx_interrupt(Adapter); 1861 1862 /* Recycle the tx descriptors */ 1863 rw_enter(&Adapter->chip_lock, RW_READER); 1864 e1000g_recycle(tx_ring); 1865 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 1866 rw_exit(&Adapter->chip_lock); 1867 1868 /* Schedule the re-transmit */ 1869 if (tx_ring->resched_needed && 1870 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 1871 tx_ring->resched_needed = B_FALSE; 1872 mac_tx_update(Adapter->mh); 1873 E1000G_STAT(tx_ring->stat_reschedule); 1874 } 1875 } 1876 1877 if (Adapter->intr_adaptive) { 1878 itr = e1000g_get_itr(Adapter->rx_pkt_cnt, Adapter->tx_pkt_cnt, 1879 Adapter->intr_throttling_rate); 1880 if (itr) { 1881 E1000_WRITE_REG(hw, E1000_ITR, itr); 1882 Adapter->intr_throttling_rate = itr; 1883 } 1884 } 1885 1886 /* 1887 * The Receive Sequence errors RXSEQ and the link status change LSC 1888 * are checked to detect that the cable has been pulled out. For 1889 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1890 * are an indication that cable is not connected. 1891 */ 1892 if ((icr & E1000_ICR_RXSEQ) || 1893 (icr & E1000_ICR_LSC) || 1894 (icr & E1000_ICR_GPI_EN1)) { 1895 boolean_t link_changed; 1896 timeout_id_t tid = 0; 1897 1898 stop_watchdog_timer(Adapter); 1899 1900 rw_enter(&Adapter->chip_lock, RW_WRITER); 1901 1902 /* 1903 * Because we got a link-status-change interrupt, force 1904 * e1000_check_for_link() to look at phy 1905 */ 1906 Adapter->shared.mac.get_link_status = B_TRUE; 1907 1908 /* e1000g_link_check takes care of link status change */ 1909 link_changed = e1000g_link_check(Adapter); 1910 1911 /* Get new phy state */ 1912 e1000g_get_phy_state(Adapter); 1913 1914 /* 1915 * If the link timer has not timed out, we'll not notify 1916 * the upper layer with any link state until the link is up. 1917 */ 1918 if (link_changed && !Adapter->link_complete) { 1919 if (Adapter->link_state == LINK_STATE_UP) { 1920 mutex_enter(&Adapter->link_lock); 1921 Adapter->link_complete = B_TRUE; 1922 tid = Adapter->link_tid; 1923 Adapter->link_tid = 0; 1924 mutex_exit(&Adapter->link_lock); 1925 } else { 1926 link_changed = B_FALSE; 1927 } 1928 } 1929 rw_exit(&Adapter->chip_lock); 1930 1931 if (link_changed) { 1932 if (tid != 0) 1933 (void) untimeout(tid); 1934 1935 /* 1936 * Workaround for esb2. Data stuck in fifo on a link 1937 * down event. Reset the adapter to recover it. 1938 */ 1939 if ((Adapter->link_state == LINK_STATE_DOWN) && 1940 (Adapter->shared.mac.type == e1000_80003es2lan)) 1941 (void) e1000g_reset(Adapter); 1942 1943 mac_link_update(Adapter->mh, Adapter->link_state); 1944 } 1945 1946 start_watchdog_timer(Adapter); 1947 } 1948 } 1949 1950 static uint32_t 1951 e1000g_get_itr(uint32_t rx_packet, uint32_t tx_packet, uint32_t cur_itr) 1952 { 1953 uint32_t new_itr; 1954 1955 /* 1956 * Determine a propper itr according to rx/tx packet count 1957 * per interrupt, the value of itr are based on document 1958 * and testing. 1959 */ 1960 if ((rx_packet < DEFAULT_INTR_PACKET_LOW) || 1961 (tx_packet < DEFAULT_INTR_PACKET_LOW)) { 1962 new_itr = DEFAULT_INTR_THROTTLING_LOW; 1963 goto itr_done; 1964 } 1965 if ((rx_packet > DEFAULT_INTR_PACKET_HIGH) || 1966 (tx_packet > DEFAULT_INTR_PACKET_HIGH)) { 1967 new_itr = DEFAULT_INTR_THROTTLING_LOW; 1968 goto itr_done; 1969 } 1970 if (cur_itr < DEFAULT_INTR_THROTTLING_HIGH) { 1971 new_itr = cur_itr + (DEFAULT_INTR_THROTTLING_HIGH >> 2); 1972 if (new_itr > DEFAULT_INTR_THROTTLING_HIGH) 1973 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 1974 } else 1975 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 1976 1977 itr_done: 1978 if (cur_itr == new_itr) 1979 return (0); 1980 else 1981 return (new_itr); 1982 } 1983 1984 static void 1985 e1000g_init_unicst(struct e1000g *Adapter) 1986 { 1987 struct e1000_hw *hw; 1988 int slot; 1989 1990 hw = &Adapter->shared; 1991 1992 if (!Adapter->unicst_init) { 1993 /* Initialize the multiple unicast addresses */ 1994 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 1995 1996 if ((hw->mac.type == e1000_82571) && 1997 (e1000_get_laa_state_82571(hw) == B_TRUE)) 1998 Adapter->unicst_total--; 1999 2000 Adapter->unicst_avail = Adapter->unicst_total - 1; 2001 2002 /* Store the default mac address */ 2003 e1000_rar_set(hw, hw->mac.addr, 0); 2004 if ((hw->mac.type == e1000_82571) && 2005 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2006 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2007 2008 bcopy(hw->mac.addr, Adapter->unicst_addr[0].mac.addr, 2009 ETHERADDRL); 2010 Adapter->unicst_addr[0].mac.set = 1; 2011 2012 for (slot = 1; slot < Adapter->unicst_total; slot++) 2013 Adapter->unicst_addr[slot].mac.set = 0; 2014 2015 Adapter->unicst_init = B_TRUE; 2016 } else { 2017 /* Recover the default mac address */ 2018 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac.addr, 2019 ETHERADDRL); 2020 2021 /* Store the default mac address */ 2022 e1000_rar_set(hw, hw->mac.addr, 0); 2023 if ((hw->mac.type == e1000_82571) && 2024 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2025 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2026 2027 /* Re-configure the RAR registers */ 2028 for (slot = 1; slot < Adapter->unicst_total; slot++) 2029 e1000_rar_set(hw, 2030 Adapter->unicst_addr[slot].mac.addr, slot); 2031 } 2032 2033 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2034 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2035 } 2036 2037 static int 2038 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 2039 { 2040 struct e1000g *Adapter; 2041 2042 Adapter = (struct e1000g *)arg; 2043 2044 /* Store the default MAC address */ 2045 bcopy(mac_addr, Adapter->shared.mac.addr, ETHERADDRL); 2046 2047 /* Set MAC address in address slot 0, which is the default address */ 2048 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 2049 } 2050 2051 static int 2052 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2053 mac_addr_slot_t slot) 2054 { 2055 struct e1000_hw *hw; 2056 2057 hw = &Adapter->shared; 2058 2059 rw_enter(&Adapter->chip_lock, RW_WRITER); 2060 2061 /* 2062 * The first revision of Wiseman silicon (rev 2.0) has an errata 2063 * that requires the receiver to be in reset when any of the 2064 * receive address registers (RAR regs) are accessed. The first 2065 * rev of Wiseman silicon also requires MWI to be disabled when 2066 * a global reset or a receive reset is issued. So before we 2067 * initialize the RARs, we check the rev of the Wiseman controller 2068 * and work around any necessary HW errata. 2069 */ 2070 if ((hw->mac.type == e1000_82542) && 2071 (hw->revision_id == E1000_REVISION_2)) { 2072 e1000_pci_clear_mwi(hw); 2073 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2074 msec_delay(5); 2075 } 2076 2077 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 2078 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2079 2080 if (slot == 0) { 2081 if ((hw->mac.type == e1000_82571) && 2082 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2083 e1000_rar_set(hw, (uint8_t *)mac_addr, LAST_RAR_ENTRY); 2084 } 2085 2086 /* 2087 * If we are using Wiseman rev 2.0 silicon, we will have previously 2088 * put the receive in reset, and disabled MWI, to work around some 2089 * HW errata. Now we should take the receiver out of reset, and 2090 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2091 */ 2092 if ((hw->mac.type == e1000_82542) && 2093 (hw->revision_id == E1000_REVISION_2)) { 2094 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2095 msec_delay(1); 2096 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2097 e1000_pci_set_mwi(hw); 2098 e1000g_rx_setup(Adapter); 2099 } 2100 2101 rw_exit(&Adapter->chip_lock); 2102 2103 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2104 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2105 return (EIO); 2106 } 2107 2108 return (0); 2109 } 2110 2111 /* 2112 * e1000g_m_unicst_add() - will find an unused address slot, set the 2113 * address value to the one specified, reserve that slot and enable 2114 * the NIC to start filtering on the new MAC address. 2115 * Returns 0 on success. 2116 */ 2117 static int 2118 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 2119 { 2120 struct e1000g *Adapter = (struct e1000g *)arg; 2121 mac_addr_slot_t slot; 2122 int err; 2123 2124 if (mac_unicst_verify(Adapter->mh, 2125 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2126 return (EINVAL); 2127 2128 rw_enter(&Adapter->chip_lock, RW_WRITER); 2129 if (Adapter->unicst_avail == 0) { 2130 /* no slots available */ 2131 rw_exit(&Adapter->chip_lock); 2132 return (ENOSPC); 2133 } 2134 2135 /* 2136 * Primary/default address is in slot 0. The next addresses 2137 * are the multiple MAC addresses. So multiple MAC address 0 2138 * is in slot 1, 1 in slot 2, and so on. So the first multiple 2139 * MAC address resides in slot 1. 2140 */ 2141 for (slot = 1; slot < Adapter->unicst_total; slot++) { 2142 if (Adapter->unicst_addr[slot].mac.set == 0) { 2143 Adapter->unicst_addr[slot].mac.set = 1; 2144 break; 2145 } 2146 } 2147 2148 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 2149 2150 Adapter->unicst_avail--; 2151 rw_exit(&Adapter->chip_lock); 2152 2153 maddr->mma_slot = slot; 2154 2155 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 2156 rw_enter(&Adapter->chip_lock, RW_WRITER); 2157 Adapter->unicst_addr[slot].mac.set = 0; 2158 Adapter->unicst_avail++; 2159 rw_exit(&Adapter->chip_lock); 2160 } 2161 2162 return (err); 2163 } 2164 2165 /* 2166 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 2167 * call to e1000g_m_unicst_add(). The slot number that was returned in 2168 * e1000g_m_unicst_add() is passed in the call to remove the address. 2169 * Returns 0 on success. 2170 */ 2171 static int 2172 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 2173 { 2174 struct e1000g *Adapter = (struct e1000g *)arg; 2175 int err; 2176 2177 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2178 return (EINVAL); 2179 2180 rw_enter(&Adapter->chip_lock, RW_WRITER); 2181 if (Adapter->unicst_addr[slot].mac.set == 1) { 2182 Adapter->unicst_addr[slot].mac.set = 0; 2183 Adapter->unicst_avail++; 2184 rw_exit(&Adapter->chip_lock); 2185 2186 /* Copy the default address to the passed slot */ 2187 if (err = e1000g_unicst_set(Adapter, 2188 Adapter->unicst_addr[0].mac.addr, slot) != 0) { 2189 rw_enter(&Adapter->chip_lock, RW_WRITER); 2190 Adapter->unicst_addr[slot].mac.set = 1; 2191 Adapter->unicst_avail--; 2192 rw_exit(&Adapter->chip_lock); 2193 } 2194 return (err); 2195 } 2196 rw_exit(&Adapter->chip_lock); 2197 2198 return (EINVAL); 2199 } 2200 2201 /* 2202 * e1000g_m_unicst_modify() - modifies the value of an address that 2203 * has been added by e1000g_m_unicst_add(). The new address, address 2204 * length and the slot number that was returned in the call to add 2205 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2206 * set to 0. Returns 0 on success. 2207 */ 2208 static int 2209 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2210 { 2211 struct e1000g *Adapter = (struct e1000g *)arg; 2212 mac_addr_slot_t slot; 2213 2214 if (mac_unicst_verify(Adapter->mh, 2215 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2216 return (EINVAL); 2217 2218 slot = maddr->mma_slot; 2219 2220 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2221 return (EINVAL); 2222 2223 rw_enter(&Adapter->chip_lock, RW_WRITER); 2224 if (Adapter->unicst_addr[slot].mac.set == 1) { 2225 rw_exit(&Adapter->chip_lock); 2226 2227 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2228 } 2229 rw_exit(&Adapter->chip_lock); 2230 2231 return (EINVAL); 2232 } 2233 2234 /* 2235 * e1000g_m_unicst_get() - will get the MAC address and all other 2236 * information related to the address slot passed in mac_multi_addr_t. 2237 * mma_flags should be set to 0 in the call. 2238 * On return, mma_flags can take the following values: 2239 * 1) MMAC_SLOT_UNUSED 2240 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2241 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2242 * 4) MMAC_SLOT_USED 2243 */ 2244 static int 2245 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2246 { 2247 struct e1000g *Adapter = (struct e1000g *)arg; 2248 mac_addr_slot_t slot; 2249 2250 slot = maddr->mma_slot; 2251 2252 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2253 return (EINVAL); 2254 2255 rw_enter(&Adapter->chip_lock, RW_WRITER); 2256 if (Adapter->unicst_addr[slot].mac.set == 1) { 2257 bcopy(Adapter->unicst_addr[slot].mac.addr, 2258 maddr->mma_addr, ETHERADDRL); 2259 maddr->mma_flags = MMAC_SLOT_USED; 2260 } else { 2261 maddr->mma_flags = MMAC_SLOT_UNUSED; 2262 } 2263 rw_exit(&Adapter->chip_lock); 2264 2265 return (0); 2266 } 2267 2268 static int 2269 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2270 { 2271 struct e1000_hw *hw = &Adapter->shared; 2272 unsigned i; 2273 int res = 0; 2274 2275 rw_enter(&Adapter->chip_lock, RW_WRITER); 2276 2277 if ((multiaddr[0] & 01) == 0) { 2278 res = EINVAL; 2279 goto done; 2280 } 2281 2282 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2283 res = ENOENT; 2284 goto done; 2285 } 2286 2287 bcopy(multiaddr, 2288 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2289 Adapter->mcast_count++; 2290 2291 /* 2292 * Update the MC table in the hardware 2293 */ 2294 e1000g_clear_interrupt(Adapter); 2295 2296 e1000g_setup_multicast(Adapter); 2297 2298 if ((hw->mac.type == e1000_82542) && 2299 (hw->revision_id == E1000_REVISION_2)) 2300 e1000g_rx_setup(Adapter); 2301 2302 e1000g_mask_interrupt(Adapter); 2303 2304 done: 2305 rw_exit(&Adapter->chip_lock); 2306 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2307 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2308 res = EIO; 2309 } 2310 2311 return (res); 2312 } 2313 2314 static int 2315 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2316 { 2317 struct e1000_hw *hw = &Adapter->shared; 2318 unsigned i; 2319 2320 rw_enter(&Adapter->chip_lock, RW_WRITER); 2321 2322 for (i = 0; i < Adapter->mcast_count; i++) { 2323 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2324 ETHERADDRL) == 0) { 2325 for (i++; i < Adapter->mcast_count; i++) { 2326 Adapter->mcast_table[i - 1] = 2327 Adapter->mcast_table[i]; 2328 } 2329 Adapter->mcast_count--; 2330 break; 2331 } 2332 } 2333 2334 /* 2335 * Update the MC table in the hardware 2336 */ 2337 e1000g_clear_interrupt(Adapter); 2338 2339 e1000g_setup_multicast(Adapter); 2340 2341 if ((hw->mac.type == e1000_82542) && 2342 (hw->revision_id == E1000_REVISION_2)) 2343 e1000g_rx_setup(Adapter); 2344 2345 e1000g_mask_interrupt(Adapter); 2346 2347 done: 2348 rw_exit(&Adapter->chip_lock); 2349 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2350 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2351 return (EIO); 2352 } 2353 2354 return (0); 2355 } 2356 2357 /* 2358 * e1000g_setup_multicast - setup multicast data structures 2359 * 2360 * This routine initializes all of the multicast related structures. 2361 */ 2362 void 2363 e1000g_setup_multicast(struct e1000g *Adapter) 2364 { 2365 uint8_t *mc_addr_list; 2366 uint32_t mc_addr_count; 2367 uint32_t rctl; 2368 struct e1000_hw *hw; 2369 2370 hw = &Adapter->shared; 2371 2372 /* 2373 * The e1000g has the ability to do perfect filtering of 16 2374 * addresses. The driver uses one of the e1000g's 16 receive 2375 * address registers for its node/network/mac/individual address. 2376 * So, we have room for up to 15 multicast addresses in the CAM, 2377 * additional MC addresses are handled by the MTA (Multicast Table 2378 * Array) 2379 */ 2380 2381 rctl = E1000_READ_REG(hw, E1000_RCTL); 2382 2383 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2384 2385 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2386 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2387 "Adapter requested more than %d MC Addresses.\n", 2388 MAX_NUM_MULTICAST_ADDRESSES); 2389 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2390 } else { 2391 /* 2392 * Set the number of MC addresses that we are being 2393 * requested to use 2394 */ 2395 mc_addr_count = Adapter->mcast_count; 2396 } 2397 /* 2398 * The Wiseman 2.0 silicon has an errata by which the receiver will 2399 * hang while writing to the receive address registers if the receiver 2400 * is not in reset before writing to the registers. Updating the RAR 2401 * is done during the setting up of the multicast table, hence the 2402 * receiver has to be put in reset before updating the multicast table 2403 * and then taken out of reset at the end 2404 */ 2405 /* 2406 * if WMI was enabled then dis able it before issueing the global 2407 * reset to the hardware. 2408 */ 2409 /* 2410 * Only required for WISEMAN_2_0 2411 */ 2412 if ((hw->mac.type == e1000_82542) && 2413 (hw->revision_id == E1000_REVISION_2)) { 2414 e1000_pci_clear_mwi(hw); 2415 /* 2416 * The e1000g must be in reset before changing any RA 2417 * registers. Reset receive unit. The chip will remain in 2418 * the reset state until software explicitly restarts it. 2419 */ 2420 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2421 /* Allow receiver time to go in to reset */ 2422 msec_delay(5); 2423 } 2424 2425 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2426 Adapter->unicst_total, hw->mac.rar_entry_count); 2427 2428 /* 2429 * Only for Wiseman_2_0 2430 * If MWI was enabled then re-enable it after issueing (as we 2431 * disabled it up there) the receive reset command. 2432 * Wainwright does not have a receive reset command and only thing 2433 * close to it is global reset which will require tx setup also 2434 */ 2435 if ((hw->mac.type == e1000_82542) && 2436 (hw->revision_id == E1000_REVISION_2)) { 2437 /* 2438 * if WMI was enabled then reenable it after issueing the 2439 * global or receive reset to the hardware. 2440 */ 2441 2442 /* 2443 * Take receiver out of reset 2444 * clear E1000_RCTL_RST bit (and all others) 2445 */ 2446 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2447 msec_delay(5); 2448 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2449 e1000_pci_set_mwi(hw); 2450 } 2451 2452 /* 2453 * Restore original value 2454 */ 2455 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2456 } 2457 2458 int 2459 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2460 { 2461 struct e1000g *Adapter = (struct e1000g *)arg; 2462 2463 return ((add) ? multicst_add(Adapter, addr) 2464 : multicst_remove(Adapter, addr)); 2465 } 2466 2467 int 2468 e1000g_m_promisc(void *arg, boolean_t on) 2469 { 2470 struct e1000g *Adapter = (struct e1000g *)arg; 2471 uint32_t rctl; 2472 2473 rw_enter(&Adapter->chip_lock, RW_WRITER); 2474 2475 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2476 2477 if (on) 2478 rctl |= 2479 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2480 else 2481 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2482 2483 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2484 2485 Adapter->e1000g_promisc = on; 2486 2487 rw_exit(&Adapter->chip_lock); 2488 2489 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2490 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2491 return (EIO); 2492 } 2493 2494 return (0); 2495 } 2496 2497 static boolean_t 2498 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2499 { 2500 struct e1000g *Adapter = (struct e1000g *)arg; 2501 struct e1000_hw *hw = &Adapter->shared; 2502 2503 switch (cap) { 2504 case MAC_CAPAB_HCKSUM: { 2505 uint32_t *txflags = cap_data; 2506 /* 2507 * Checksum on/off selection via global parameters. 2508 * 2509 * If the chip is flagged as not capable of (correctly) 2510 * handling checksumming, we don't enable it on either 2511 * Rx or Tx side. Otherwise, we take this chip's settings 2512 * from the patchable global defaults. 2513 * 2514 * We advertise our capabilities only if TX offload is 2515 * enabled. On receive, the stack will accept checksummed 2516 * packets anyway, even if we haven't said we can deliver 2517 * them. 2518 */ 2519 switch (hw->mac.type) { 2520 case e1000_82540: 2521 case e1000_82544: 2522 case e1000_82545: 2523 case e1000_82545_rev_3: 2524 case e1000_82546: 2525 case e1000_82546_rev_3: 2526 case e1000_82571: 2527 case e1000_82572: 2528 case e1000_82573: 2529 case e1000_80003es2lan: 2530 if (Adapter->tx_hcksum_enabled) 2531 *txflags = HCKSUM_IPHDRCKSUM | 2532 HCKSUM_INET_PARTIAL; 2533 else 2534 return (B_FALSE); 2535 break; 2536 2537 /* 2538 * For the following Intel PRO/1000 chipsets, we have not 2539 * tested the hardware checksum offload capability, so we 2540 * disable the capability for them. 2541 * e1000_82542, 2542 * e1000_82543, 2543 * e1000_82541, 2544 * e1000_82541_rev_2, 2545 * e1000_82547, 2546 * e1000_82547_rev_2, 2547 */ 2548 default: 2549 return (B_FALSE); 2550 } 2551 2552 break; 2553 } 2554 case MAC_CAPAB_POLL: 2555 /* 2556 * There's nothing for us to fill in, simply returning 2557 * B_TRUE stating that we support polling is sufficient. 2558 */ 2559 break; 2560 2561 case MAC_CAPAB_MULTIADDRESS: { 2562 multiaddress_capab_t *mmacp = cap_data; 2563 2564 /* 2565 * The number of MAC addresses made available by 2566 * this capability is one less than the total as 2567 * the primary address in slot 0 is counted in 2568 * the total. 2569 */ 2570 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2571 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2572 /* No multiple factory addresses, set mma_flag to 0 */ 2573 mmacp->maddr_flag = 0; 2574 mmacp->maddr_handle = Adapter; 2575 mmacp->maddr_add = e1000g_m_unicst_add; 2576 mmacp->maddr_remove = e1000g_m_unicst_remove; 2577 mmacp->maddr_modify = e1000g_m_unicst_modify; 2578 mmacp->maddr_get = e1000g_m_unicst_get; 2579 mmacp->maddr_reserve = NULL; 2580 break; 2581 } 2582 default: 2583 return (B_FALSE); 2584 } 2585 return (B_TRUE); 2586 } 2587 2588 static boolean_t 2589 e1000g_param_locked(mac_prop_id_t pr_num) 2590 { 2591 /* 2592 * All en_* parameters are locked (read-only) while 2593 * the device is in any sort of loopback mode ... 2594 */ 2595 switch (pr_num) { 2596 case MAC_PROP_EN_1000FDX_CAP: 2597 case MAC_PROP_EN_1000HDX_CAP: 2598 case MAC_PROP_EN_100FDX_CAP: 2599 case MAC_PROP_EN_100HDX_CAP: 2600 case MAC_PROP_EN_10FDX_CAP: 2601 case MAC_PROP_EN_10HDX_CAP: 2602 case MAC_PROP_AUTONEG: 2603 case MAC_PROP_FLOWCTRL: 2604 return (B_TRUE); 2605 } 2606 return (B_FALSE); 2607 } 2608 2609 /* 2610 * callback function for set/get of properties 2611 */ 2612 static int 2613 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2614 uint_t pr_valsize, const void *pr_val) 2615 { 2616 struct e1000g *Adapter = arg; 2617 struct e1000_mac_info *mac = &Adapter->shared.mac; 2618 struct e1000_phy_info *phy = &Adapter->shared.phy; 2619 struct e1000_fc_info *fc = &Adapter->shared.fc; 2620 e1000g_tx_ring_t *tx_ring; 2621 int err = 0; 2622 link_flowctrl_t flowctrl; 2623 uint32_t cur_mtu, new_mtu; 2624 uint64_t tmp = 0; 2625 2626 rw_enter(&Adapter->chip_lock, RW_WRITER); 2627 if (Adapter->loopback_mode != E1000G_LB_NONE && 2628 e1000g_param_locked(pr_num)) { 2629 /* 2630 * All en_* parameters are locked (read-only) 2631 * while the device is in any sort of loopback mode. 2632 */ 2633 rw_exit(&Adapter->chip_lock); 2634 return (EBUSY); 2635 } 2636 2637 switch (pr_num) { 2638 case MAC_PROP_EN_1000FDX_CAP: 2639 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 2640 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 2641 goto reset; 2642 case MAC_PROP_EN_1000HDX_CAP: 2643 Adapter->param_en_1000hdx = *(uint8_t *)pr_val; 2644 Adapter->param_adv_1000hdx = *(uint8_t *)pr_val; 2645 goto reset; 2646 case MAC_PROP_EN_100FDX_CAP: 2647 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 2648 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 2649 goto reset; 2650 case MAC_PROP_EN_100HDX_CAP: 2651 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 2652 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 2653 goto reset; 2654 case MAC_PROP_EN_10FDX_CAP: 2655 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 2656 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 2657 goto reset; 2658 case MAC_PROP_EN_10HDX_CAP: 2659 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 2660 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 2661 goto reset; 2662 case MAC_PROP_AUTONEG: 2663 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 2664 goto reset; 2665 case MAC_PROP_FLOWCTRL: 2666 fc->send_xon = B_TRUE; 2667 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 2668 2669 switch (flowctrl) { 2670 default: 2671 err = EINVAL; 2672 break; 2673 case LINK_FLOWCTRL_NONE: 2674 fc->type = e1000_fc_none; 2675 break; 2676 case LINK_FLOWCTRL_RX: 2677 fc->type = e1000_fc_rx_pause; 2678 break; 2679 case LINK_FLOWCTRL_TX: 2680 fc->type = e1000_fc_tx_pause; 2681 break; 2682 case LINK_FLOWCTRL_BI: 2683 fc->type = e1000_fc_full; 2684 break; 2685 } 2686 reset: 2687 if (err == 0) { 2688 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 2689 err = EINVAL; 2690 } 2691 break; 2692 case MAC_PROP_ADV_1000FDX_CAP: 2693 case MAC_PROP_ADV_1000HDX_CAP: 2694 case MAC_PROP_ADV_100FDX_CAP: 2695 case MAC_PROP_ADV_100HDX_CAP: 2696 case MAC_PROP_ADV_10FDX_CAP: 2697 case MAC_PROP_ADV_10HDX_CAP: 2698 case MAC_PROP_STATUS: 2699 case MAC_PROP_SPEED: 2700 case MAC_PROP_DUPLEX: 2701 err = ENOTSUP; /* read-only prop. Can't set this. */ 2702 break; 2703 case MAC_PROP_MTU: 2704 cur_mtu = Adapter->default_mtu; 2705 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 2706 if (new_mtu == cur_mtu) { 2707 err = 0; 2708 break; 2709 } 2710 2711 tmp = new_mtu + sizeof (struct ether_vlan_header) + 2712 ETHERFCSL; 2713 if ((tmp < DEFAULT_FRAME_SIZE) || 2714 (tmp > MAXIMUM_FRAME_SIZE)) { 2715 err = EINVAL; 2716 break; 2717 } 2718 2719 /* ich8 doed not support jumbo frames */ 2720 if ((mac->type == e1000_ich8lan) && 2721 (tmp > DEFAULT_FRAME_SIZE)) { 2722 err = EINVAL; 2723 break; 2724 } 2725 /* ich9 does not do jumbo frames on one phy type */ 2726 if ((mac->type == e1000_ich9lan) && 2727 (phy->type == e1000_phy_ife) && 2728 (tmp > DEFAULT_FRAME_SIZE)) { 2729 err = EINVAL; 2730 break; 2731 } 2732 if (Adapter->chip_state != E1000G_STOP) { 2733 err = EBUSY; 2734 break; 2735 } 2736 2737 err = mac_maxsdu_update(Adapter->mh, new_mtu); 2738 if (err == 0) { 2739 Adapter->max_frame_size = tmp; 2740 Adapter->default_mtu = new_mtu; 2741 e1000g_set_bufsize(Adapter); 2742 tx_ring = Adapter->tx_ring; 2743 tx_ring->frags_limit = 2744 (Adapter->max_frame_size / 2745 Adapter->tx_bcopy_thresh) + 2; 2746 if (tx_ring->frags_limit > 2747 (MAX_TX_DESC_PER_PACKET >> 1)) 2748 tx_ring->frags_limit = 2749 (MAX_TX_DESC_PER_PACKET >> 1); 2750 } 2751 break; 2752 case MAC_PROP_PRIVATE: 2753 err = e1000g_set_priv_prop(Adapter, pr_name, 2754 pr_valsize, pr_val); 2755 break; 2756 default: 2757 err = ENOTSUP; 2758 break; 2759 } 2760 rw_exit(&Adapter->chip_lock); 2761 return (err); 2762 } 2763 2764 static int 2765 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2766 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 2767 { 2768 struct e1000g *Adapter = arg; 2769 struct e1000_mac_info *mac = &Adapter->shared.mac; 2770 struct e1000_fc_info *fc = &Adapter->shared.fc; 2771 int err = 0; 2772 link_flowctrl_t flowctrl; 2773 uint64_t tmp = 0; 2774 2775 if (pr_valsize == 0) 2776 return (EINVAL); 2777 2778 bzero(pr_val, pr_valsize); 2779 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 2780 return (e1000g_get_def_val(Adapter, pr_num, 2781 pr_valsize, pr_val)); 2782 } 2783 2784 switch (pr_num) { 2785 case MAC_PROP_DUPLEX: 2786 if (pr_valsize >= sizeof (link_duplex_t)) { 2787 bcopy(&Adapter->link_duplex, pr_val, 2788 sizeof (link_duplex_t)); 2789 } else 2790 err = EINVAL; 2791 break; 2792 case MAC_PROP_SPEED: 2793 if (pr_valsize >= sizeof (uint64_t)) { 2794 tmp = Adapter->link_speed * 1000000ull; 2795 bcopy(&tmp, pr_val, sizeof (tmp)); 2796 } else 2797 err = EINVAL; 2798 break; 2799 case MAC_PROP_AUTONEG: 2800 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 2801 break; 2802 case MAC_PROP_FLOWCTRL: 2803 if (pr_valsize >= sizeof (link_flowctrl_t)) { 2804 switch (fc->type) { 2805 case e1000_fc_none: 2806 flowctrl = LINK_FLOWCTRL_NONE; 2807 break; 2808 case e1000_fc_rx_pause: 2809 flowctrl = LINK_FLOWCTRL_RX; 2810 break; 2811 case e1000_fc_tx_pause: 2812 flowctrl = LINK_FLOWCTRL_TX; 2813 break; 2814 case e1000_fc_full: 2815 flowctrl = LINK_FLOWCTRL_BI; 2816 break; 2817 } 2818 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 2819 } else 2820 err = EINVAL; 2821 break; 2822 case MAC_PROP_ADV_1000FDX_CAP: 2823 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 2824 break; 2825 case MAC_PROP_EN_1000FDX_CAP: 2826 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 2827 break; 2828 case MAC_PROP_ADV_1000HDX_CAP: 2829 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 2830 break; 2831 case MAC_PROP_EN_1000HDX_CAP: 2832 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 2833 break; 2834 case MAC_PROP_ADV_100FDX_CAP: 2835 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 2836 break; 2837 case MAC_PROP_EN_100FDX_CAP: 2838 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 2839 break; 2840 case MAC_PROP_ADV_100HDX_CAP: 2841 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 2842 break; 2843 case MAC_PROP_EN_100HDX_CAP: 2844 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 2845 break; 2846 case MAC_PROP_ADV_10FDX_CAP: 2847 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 2848 break; 2849 case MAC_PROP_EN_10FDX_CAP: 2850 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 2851 break; 2852 case MAC_PROP_ADV_10HDX_CAP: 2853 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 2854 break; 2855 case MAC_PROP_EN_10HDX_CAP: 2856 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 2857 break; 2858 case MAC_PROP_ADV_100T4_CAP: 2859 case MAC_PROP_EN_100T4_CAP: 2860 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 2861 break; 2862 case MAC_PROP_PRIVATE: 2863 err = e1000g_get_priv_prop(Adapter, pr_name, 2864 pr_flags, pr_valsize, pr_val); 2865 break; 2866 default: 2867 err = ENOTSUP; 2868 break; 2869 } 2870 return (err); 2871 } 2872 2873 /* ARGUSED */ 2874 static int 2875 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 2876 uint_t pr_valsize, const void *pr_val) 2877 { 2878 int err = 0; 2879 long result; 2880 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2881 struct e1000_hw *hw = &Adapter->shared; 2882 2883 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 2884 if (pr_val == NULL) { 2885 err = EINVAL; 2886 return (err); 2887 } 2888 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2889 if (result < MIN_TX_BCOPY_THRESHOLD || 2890 result > MAX_TX_BCOPY_THRESHOLD) 2891 err = EINVAL; 2892 else { 2893 Adapter->tx_bcopy_thresh = (uint32_t)result; 2894 tx_ring->frags_limit = 2895 (Adapter->max_frame_size / 2896 Adapter->tx_bcopy_thresh) + 2; 2897 if (tx_ring->frags_limit > 2898 (MAX_TX_DESC_PER_PACKET >> 1)) 2899 tx_ring->frags_limit = 2900 (MAX_TX_DESC_PER_PACKET >> 1); 2901 } 2902 return (err); 2903 } 2904 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 2905 if (pr_val == NULL) { 2906 err = EINVAL; 2907 return (err); 2908 } 2909 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2910 if (result < 0 || result > 1) 2911 err = EINVAL; 2912 else { 2913 Adapter->tx_intr_enable = (result == 1) ? 2914 B_TRUE: B_FALSE; 2915 if (Adapter->tx_intr_enable) 2916 e1000g_mask_tx_interrupt(Adapter); 2917 else 2918 e1000g_clear_tx_interrupt(Adapter); 2919 if (e1000g_check_acc_handle( 2920 Adapter->osdep.reg_handle) != DDI_FM_OK) 2921 ddi_fm_service_impact(Adapter->dip, 2922 DDI_SERVICE_DEGRADED); 2923 } 2924 return (err); 2925 } 2926 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 2927 if (pr_val == NULL) { 2928 err = EINVAL; 2929 return (err); 2930 } 2931 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2932 if (result < MIN_TX_INTR_DELAY || 2933 result > MAX_TX_INTR_DELAY) 2934 err = EINVAL; 2935 else { 2936 Adapter->tx_intr_delay = (uint32_t)result; 2937 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 2938 if (e1000g_check_acc_handle( 2939 Adapter->osdep.reg_handle) != DDI_FM_OK) 2940 ddi_fm_service_impact(Adapter->dip, 2941 DDI_SERVICE_DEGRADED); 2942 } 2943 return (err); 2944 } 2945 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 2946 if (pr_val == NULL) { 2947 err = EINVAL; 2948 return (err); 2949 } 2950 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2951 if (result < MIN_TX_INTR_ABS_DELAY || 2952 result > MAX_TX_INTR_ABS_DELAY) 2953 err = EINVAL; 2954 else { 2955 Adapter->tx_intr_abs_delay = (uint32_t)result; 2956 E1000_WRITE_REG(hw, E1000_TADV, 2957 Adapter->tx_intr_abs_delay); 2958 if (e1000g_check_acc_handle( 2959 Adapter->osdep.reg_handle) != DDI_FM_OK) 2960 ddi_fm_service_impact(Adapter->dip, 2961 DDI_SERVICE_DEGRADED); 2962 } 2963 return (err); 2964 } 2965 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 2966 if (pr_val == NULL) { 2967 err = EINVAL; 2968 return (err); 2969 } 2970 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2971 if (result < MIN_RX_BCOPY_THRESHOLD || 2972 result > MAX_RX_BCOPY_THRESHOLD) 2973 err = EINVAL; 2974 else 2975 Adapter->rx_bcopy_thresh = (uint32_t)result; 2976 return (err); 2977 } 2978 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 2979 if (pr_val == NULL) { 2980 err = EINVAL; 2981 return (err); 2982 } 2983 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2984 if (result < MIN_RX_LIMIT_ON_INTR || 2985 result > MAX_RX_LIMIT_ON_INTR) 2986 err = EINVAL; 2987 else 2988 Adapter->rx_limit_onintr = (uint32_t)result; 2989 return (err); 2990 } 2991 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 2992 if (pr_val == NULL) { 2993 err = EINVAL; 2994 return (err); 2995 } 2996 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2997 if (result < MIN_RX_INTR_DELAY || 2998 result > MAX_RX_INTR_DELAY) 2999 err = EINVAL; 3000 else { 3001 Adapter->rx_intr_delay = (uint32_t)result; 3002 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3003 if (e1000g_check_acc_handle( 3004 Adapter->osdep.reg_handle) != DDI_FM_OK) 3005 ddi_fm_service_impact(Adapter->dip, 3006 DDI_SERVICE_DEGRADED); 3007 } 3008 return (err); 3009 } 3010 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3011 if (pr_val == NULL) { 3012 err = EINVAL; 3013 return (err); 3014 } 3015 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3016 if (result < MIN_RX_INTR_ABS_DELAY || 3017 result > MAX_RX_INTR_ABS_DELAY) 3018 err = EINVAL; 3019 else { 3020 Adapter->rx_intr_abs_delay = (uint32_t)result; 3021 E1000_WRITE_REG(hw, E1000_RADV, 3022 Adapter->rx_intr_abs_delay); 3023 if (e1000g_check_acc_handle( 3024 Adapter->osdep.reg_handle) != DDI_FM_OK) 3025 ddi_fm_service_impact(Adapter->dip, 3026 DDI_SERVICE_DEGRADED); 3027 } 3028 return (err); 3029 } 3030 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3031 if (pr_val == NULL) { 3032 err = EINVAL; 3033 return (err); 3034 } 3035 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3036 if (result < MIN_INTR_THROTTLING || 3037 result > MAX_INTR_THROTTLING) 3038 err = EINVAL; 3039 else { 3040 if (hw->mac.type >= e1000_82540) { 3041 Adapter->intr_throttling_rate = 3042 (uint32_t)result; 3043 E1000_WRITE_REG(hw, E1000_ITR, 3044 Adapter->intr_throttling_rate); 3045 if (e1000g_check_acc_handle( 3046 Adapter->osdep.reg_handle) != DDI_FM_OK) 3047 ddi_fm_service_impact(Adapter->dip, 3048 DDI_SERVICE_DEGRADED); 3049 } else 3050 err = EINVAL; 3051 } 3052 return (err); 3053 } 3054 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3055 if (pr_val == NULL) { 3056 err = EINVAL; 3057 return (err); 3058 } 3059 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3060 if (result < 0 || result > 1) 3061 err = EINVAL; 3062 else { 3063 if (hw->mac.type >= e1000_82540) { 3064 Adapter->intr_adaptive = (result == 1) ? 3065 B_TRUE : B_FALSE; 3066 } else { 3067 err = EINVAL; 3068 } 3069 } 3070 return (err); 3071 } 3072 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3073 if (pr_val == NULL) { 3074 err = EINVAL; 3075 return (err); 3076 } 3077 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3078 if (result < MIN_TX_RECYCLE_THRESHOLD || 3079 result > MAX_TX_RECYCLE_THRESHOLD) 3080 err = EINVAL; 3081 else 3082 Adapter->tx_recycle_thresh = (uint32_t)result; 3083 return (err); 3084 } 3085 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3086 if (pr_val == NULL) { 3087 err = EINVAL; 3088 return (err); 3089 } 3090 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3091 if (result < MIN_TX_RECYCLE_NUM || 3092 result > MAX_TX_RECYCLE_NUM) 3093 err = EINVAL; 3094 else 3095 Adapter->tx_recycle_num = (uint32_t)result; 3096 return (err); 3097 } 3098 return (ENOTSUP); 3099 } 3100 3101 static int 3102 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3103 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 3104 { 3105 char valstr[MAXNAMELEN]; 3106 int err = ENOTSUP; 3107 uint_t strsize; 3108 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3109 int value; 3110 3111 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3112 if (is_default) 3113 goto done; 3114 value = Adapter->param_adv_pause; 3115 err = 0; 3116 goto done; 3117 } 3118 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3119 if (is_default) 3120 goto done; 3121 value = Adapter->param_adv_asym_pause; 3122 err = 0; 3123 goto done; 3124 } 3125 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3126 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3127 Adapter->tx_bcopy_thresh); 3128 err = 0; 3129 goto done; 3130 } 3131 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3132 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3133 Adapter->tx_intr_enable); 3134 err = 0; 3135 goto done; 3136 } 3137 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3138 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3139 Adapter->tx_intr_delay); 3140 err = 0; 3141 goto done; 3142 } 3143 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3144 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3145 Adapter->tx_intr_abs_delay); 3146 err = 0; 3147 goto done; 3148 } 3149 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3150 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3151 Adapter->rx_bcopy_thresh); 3152 err = 0; 3153 goto done; 3154 } 3155 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3156 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3157 Adapter->rx_limit_onintr); 3158 err = 0; 3159 goto done; 3160 } 3161 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3162 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3163 Adapter->rx_intr_delay); 3164 err = 0; 3165 goto done; 3166 } 3167 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3168 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3169 Adapter->rx_intr_abs_delay); 3170 err = 0; 3171 goto done; 3172 } 3173 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3174 value = (is_default ? DEFAULT_INTR_THROTTLING : 3175 Adapter->intr_throttling_rate); 3176 err = 0; 3177 goto done; 3178 } 3179 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3180 value = (is_default ? 1 : Adapter->intr_adaptive); 3181 err = 0; 3182 goto done; 3183 } 3184 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3185 value = (is_default ? DEFAULT_TX_RECYCLE_THRESHOLD : 3186 Adapter->tx_recycle_thresh); 3187 err = 0; 3188 goto done; 3189 } 3190 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3191 value = (is_default ? DEFAULT_TX_RECYCLE_NUM : 3192 Adapter->tx_recycle_num); 3193 err = 0; 3194 goto done; 3195 } 3196 done: 3197 if (err == 0) { 3198 (void) snprintf(pr_val, pr_valsize, "%d", value); 3199 } 3200 return (err); 3201 } 3202 3203 /* 3204 * e1000g_get_conf - get configurations set in e1000g.conf 3205 * This routine gets user-configured values out of the configuration 3206 * file e1000g.conf. 3207 * 3208 * For each configurable value, there is a minimum, a maximum, and a 3209 * default. 3210 * If user does not configure a value, use the default. 3211 * If user configures below the minimum, use the minumum. 3212 * If user configures above the maximum, use the maxumum. 3213 */ 3214 static void 3215 e1000g_get_conf(struct e1000g *Adapter) 3216 { 3217 struct e1000_hw *hw = &Adapter->shared; 3218 boolean_t tbi_compatibility = B_FALSE; 3219 3220 /* 3221 * get each configurable property from e1000g.conf 3222 */ 3223 3224 /* 3225 * NumTxDescriptors 3226 */ 3227 Adapter->tx_desc_num = 3228 e1000g_get_prop(Adapter, "NumTxDescriptors", 3229 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3230 DEFAULT_NUM_TX_DESCRIPTOR); 3231 3232 /* 3233 * NumRxDescriptors 3234 */ 3235 Adapter->rx_desc_num = 3236 e1000g_get_prop(Adapter, "NumRxDescriptors", 3237 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3238 DEFAULT_NUM_RX_DESCRIPTOR); 3239 3240 /* 3241 * NumRxFreeList 3242 */ 3243 Adapter->rx_freelist_num = 3244 e1000g_get_prop(Adapter, "NumRxFreeList", 3245 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3246 DEFAULT_NUM_RX_FREELIST); 3247 3248 /* 3249 * NumTxPacketList 3250 */ 3251 Adapter->tx_freelist_num = 3252 e1000g_get_prop(Adapter, "NumTxPacketList", 3253 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3254 DEFAULT_NUM_TX_FREELIST); 3255 3256 /* 3257 * FlowControl 3258 */ 3259 hw->fc.send_xon = B_TRUE; 3260 hw->fc.type = 3261 e1000g_get_prop(Adapter, "FlowControl", 3262 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3263 /* 4 is the setting that says "let the eeprom decide" */ 3264 if (hw->fc.type == 4) 3265 hw->fc.type = e1000_fc_default; 3266 3267 /* 3268 * Max Num Receive Packets on Interrupt 3269 */ 3270 Adapter->rx_limit_onintr = 3271 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3272 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3273 DEFAULT_RX_LIMIT_ON_INTR); 3274 3275 /* 3276 * PHY master slave setting 3277 */ 3278 hw->phy.ms_type = 3279 e1000g_get_prop(Adapter, "SetMasterSlave", 3280 e1000_ms_hw_default, e1000_ms_auto, 3281 e1000_ms_hw_default); 3282 3283 /* 3284 * Parameter which controls TBI mode workaround, which is only 3285 * needed on certain switches such as Cisco 6500/Foundry 3286 */ 3287 tbi_compatibility = 3288 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3289 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3290 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3291 3292 /* 3293 * MSI Enable 3294 */ 3295 Adapter->msi_enabled = 3296 e1000g_get_prop(Adapter, "MSIEnable", 3297 0, 1, DEFAULT_MSI_ENABLE); 3298 3299 /* 3300 * Interrupt Throttling Rate 3301 */ 3302 Adapter->intr_throttling_rate = 3303 e1000g_get_prop(Adapter, "intr_throttling_rate", 3304 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3305 DEFAULT_INTR_THROTTLING); 3306 3307 /* 3308 * Adaptive Interrupt Blanking Enable/Disable 3309 * It is enabled by default 3310 */ 3311 Adapter->intr_adaptive = 3312 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3313 B_TRUE : B_FALSE; 3314 3315 /* 3316 * Tx recycle threshold 3317 */ 3318 Adapter->tx_recycle_thresh = 3319 e1000g_get_prop(Adapter, "tx_recycle_thresh", 3320 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 3321 DEFAULT_TX_RECYCLE_THRESHOLD); 3322 3323 /* 3324 * Tx recycle descriptor number 3325 */ 3326 Adapter->tx_recycle_num = 3327 e1000g_get_prop(Adapter, "tx_recycle_num", 3328 MIN_TX_RECYCLE_NUM, MAX_TX_RECYCLE_NUM, 3329 DEFAULT_TX_RECYCLE_NUM); 3330 3331 /* 3332 * Hardware checksum enable/disable parameter 3333 */ 3334 Adapter->tx_hcksum_enabled = 3335 e1000g_get_prop(Adapter, "tx_hcksum_enabled", 3336 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3337 3338 } 3339 3340 /* 3341 * e1000g_get_prop - routine to read properties 3342 * 3343 * Get a user-configure property value out of the configuration 3344 * file e1000g.conf. 3345 * 3346 * Caller provides name of the property, a default value, a minimum 3347 * value, and a maximum value. 3348 * 3349 * Return configured value of the property, with default, minimum and 3350 * maximum properly applied. 3351 */ 3352 static int 3353 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3354 char *propname, /* name of the property */ 3355 int minval, /* minimum acceptable value */ 3356 int maxval, /* maximim acceptable value */ 3357 int defval) /* default value */ 3358 { 3359 int propval; /* value returned for requested property */ 3360 int *props; /* point to array of properties returned */ 3361 uint_t nprops; /* number of property value returned */ 3362 3363 /* 3364 * get the array of properties from the config file 3365 */ 3366 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3367 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3368 /* got some properties, test if we got enough */ 3369 if (Adapter->instance < nprops) { 3370 propval = props[Adapter->instance]; 3371 } else { 3372 /* not enough properties configured */ 3373 propval = defval; 3374 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3375 "Not Enough %s values found in e1000g.conf" 3376 " - set to %d\n", 3377 propname, propval); 3378 } 3379 3380 /* free memory allocated for properties */ 3381 ddi_prop_free(props); 3382 3383 } else { 3384 propval = defval; 3385 } 3386 3387 /* 3388 * enforce limits 3389 */ 3390 if (propval > maxval) { 3391 propval = maxval; 3392 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3393 "Too High %s value in e1000g.conf - set to %d\n", 3394 propname, propval); 3395 } 3396 3397 if (propval < minval) { 3398 propval = minval; 3399 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3400 "Too Low %s value in e1000g.conf - set to %d\n", 3401 propname, propval); 3402 } 3403 3404 return (propval); 3405 } 3406 3407 static boolean_t 3408 e1000g_link_check(struct e1000g *Adapter) 3409 { 3410 uint16_t speed, duplex, phydata; 3411 boolean_t link_changed = B_FALSE; 3412 struct e1000_hw *hw; 3413 uint32_t reg_tarc; 3414 3415 hw = &Adapter->shared; 3416 3417 if (e1000g_link_up(Adapter)) { 3418 /* 3419 * The Link is up, check whether it was marked as down earlier 3420 */ 3421 if (Adapter->link_state != LINK_STATE_UP) { 3422 e1000_get_speed_and_duplex(hw, &speed, &duplex); 3423 Adapter->link_speed = speed; 3424 Adapter->link_duplex = duplex; 3425 Adapter->link_state = LINK_STATE_UP; 3426 link_changed = B_TRUE; 3427 3428 Adapter->tx_link_down_timeout = 0; 3429 3430 if ((hw->mac.type == e1000_82571) || 3431 (hw->mac.type == e1000_82572)) { 3432 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3433 if (speed == SPEED_1000) 3434 reg_tarc |= (1 << 21); 3435 else 3436 reg_tarc &= ~(1 << 21); 3437 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3438 } 3439 } 3440 Adapter->smartspeed = 0; 3441 } else { 3442 if (Adapter->link_state != LINK_STATE_DOWN) { 3443 Adapter->link_speed = 0; 3444 Adapter->link_duplex = 0; 3445 Adapter->link_state = LINK_STATE_DOWN; 3446 link_changed = B_TRUE; 3447 3448 /* 3449 * SmartSpeed workaround for Tabor/TanaX, When the 3450 * driver loses link disable auto master/slave 3451 * resolution. 3452 */ 3453 if (hw->phy.type == e1000_phy_igp) { 3454 e1000_read_phy_reg(hw, 3455 PHY_1000T_CTRL, &phydata); 3456 phydata |= CR_1000T_MS_ENABLE; 3457 e1000_write_phy_reg(hw, 3458 PHY_1000T_CTRL, phydata); 3459 } 3460 } else { 3461 e1000g_smartspeed(Adapter); 3462 } 3463 3464 if (Adapter->chip_state == E1000G_START) { 3465 if (Adapter->tx_link_down_timeout < 3466 MAX_TX_LINK_DOWN_TIMEOUT) { 3467 Adapter->tx_link_down_timeout++; 3468 } else if (Adapter->tx_link_down_timeout == 3469 MAX_TX_LINK_DOWN_TIMEOUT) { 3470 e1000g_tx_clean(Adapter); 3471 Adapter->tx_link_down_timeout++; 3472 } 3473 } 3474 } 3475 3476 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3477 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3478 3479 return (link_changed); 3480 } 3481 3482 /* 3483 * e1000g_reset_link - Using the link properties to setup the link 3484 */ 3485 int 3486 e1000g_reset_link(struct e1000g *Adapter) 3487 { 3488 struct e1000_mac_info *mac; 3489 struct e1000_phy_info *phy; 3490 boolean_t invalid; 3491 3492 mac = &Adapter->shared.mac; 3493 phy = &Adapter->shared.phy; 3494 invalid = B_FALSE; 3495 3496 if (Adapter->param_adv_autoneg == 1) { 3497 mac->autoneg = B_TRUE; 3498 phy->autoneg_advertised = 0; 3499 3500 /* 3501 * 1000hdx is not supported for autonegotiation 3502 */ 3503 if (Adapter->param_adv_1000fdx == 1) 3504 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3505 3506 if (Adapter->param_adv_100fdx == 1) 3507 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3508 3509 if (Adapter->param_adv_100hdx == 1) 3510 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3511 3512 if (Adapter->param_adv_10fdx == 1) 3513 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3514 3515 if (Adapter->param_adv_10hdx == 1) 3516 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3517 3518 if (phy->autoneg_advertised == 0) 3519 invalid = B_TRUE; 3520 } else { 3521 mac->autoneg = B_FALSE; 3522 3523 /* 3524 * 1000fdx and 1000hdx are not supported for forced link 3525 */ 3526 if (Adapter->param_adv_100fdx == 1) 3527 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3528 else if (Adapter->param_adv_100hdx == 1) 3529 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3530 else if (Adapter->param_adv_10fdx == 1) 3531 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3532 else if (Adapter->param_adv_10hdx == 1) 3533 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3534 else 3535 invalid = B_TRUE; 3536 3537 } 3538 3539 if (invalid) { 3540 e1000g_log(Adapter, CE_WARN, 3541 "Invalid link sets. Setup link to" 3542 "support autonegotiation with all link capabilities."); 3543 mac->autoneg = B_TRUE; 3544 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3545 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3546 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3547 } 3548 3549 return (e1000_setup_link(&Adapter->shared)); 3550 } 3551 3552 static void 3553 e1000g_local_timer(void *ws) 3554 { 3555 struct e1000g *Adapter = (struct e1000g *)ws; 3556 struct e1000_hw *hw; 3557 e1000g_ether_addr_t ether_addr; 3558 boolean_t link_changed; 3559 3560 hw = &Adapter->shared; 3561 3562 if (Adapter->chip_state == E1000G_ERROR) { 3563 Adapter->reset_count++; 3564 if (e1000g_global_reset(Adapter)) 3565 ddi_fm_service_impact(Adapter->dip, 3566 DDI_SERVICE_RESTORED); 3567 else 3568 ddi_fm_service_impact(Adapter->dip, 3569 DDI_SERVICE_LOST); 3570 return; 3571 } 3572 3573 if (e1000g_stall_check(Adapter)) { 3574 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3575 "Tx stall detected. Activate automatic recovery.\n"); 3576 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 3577 Adapter->reset_count++; 3578 if (e1000g_reset(Adapter)) 3579 ddi_fm_service_impact(Adapter->dip, 3580 DDI_SERVICE_RESTORED); 3581 else 3582 ddi_fm_service_impact(Adapter->dip, 3583 DDI_SERVICE_LOST); 3584 return; 3585 } 3586 3587 link_changed = B_FALSE; 3588 rw_enter(&Adapter->chip_lock, RW_READER); 3589 if (Adapter->link_complete) 3590 link_changed = e1000g_link_check(Adapter); 3591 rw_exit(&Adapter->chip_lock); 3592 3593 if (link_changed) { 3594 /* 3595 * Workaround for esb2. Data stuck in fifo on a link 3596 * down event. Reset the adapter to recover it. 3597 */ 3598 if ((Adapter->link_state == LINK_STATE_DOWN) && 3599 (hw->mac.type == e1000_80003es2lan)) 3600 (void) e1000g_reset(Adapter); 3601 3602 mac_link_update(Adapter->mh, Adapter->link_state); 3603 } 3604 3605 /* 3606 * With 82571 controllers, any locally administered address will 3607 * be overwritten when there is a reset on the other port. 3608 * Detect this circumstance and correct it. 3609 */ 3610 if ((hw->mac.type == e1000_82571) && 3611 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 3612 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 3613 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 3614 3615 ether_addr.reg.low = ntohl(ether_addr.reg.low); 3616 ether_addr.reg.high = ntohl(ether_addr.reg.high); 3617 3618 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 3619 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 3620 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 3621 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 3622 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 3623 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 3624 e1000_rar_set(hw, hw->mac.addr, 0); 3625 } 3626 } 3627 3628 /* 3629 * Long TTL workaround for 82541/82547 3630 */ 3631 e1000_igp_ttl_workaround_82547(hw); 3632 3633 /* 3634 * Check for Adaptive IFS settings If there are lots of collisions 3635 * change the value in steps... 3636 * These properties should only be set for 10/100 3637 */ 3638 if ((hw->phy.media_type == e1000_media_type_copper) && 3639 ((Adapter->link_speed == SPEED_100) || 3640 (Adapter->link_speed == SPEED_10))) { 3641 e1000_update_adaptive(hw); 3642 } 3643 /* 3644 * Set Timer Interrupts 3645 */ 3646 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 3647 3648 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3649 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3650 3651 restart_watchdog_timer(Adapter); 3652 } 3653 3654 /* 3655 * The function e1000g_link_timer() is called when the timer for link setup 3656 * is expired, which indicates the completion of the link setup. The link 3657 * state will not be updated until the link setup is completed. And the 3658 * link state will not be sent to the upper layer through mac_link_update() 3659 * in this function. It will be updated in the local timer routine or the 3660 * interrupt service routine after the interface is started (plumbed). 3661 */ 3662 static void 3663 e1000g_link_timer(void *arg) 3664 { 3665 struct e1000g *Adapter = (struct e1000g *)arg; 3666 3667 mutex_enter(&Adapter->link_lock); 3668 Adapter->link_complete = B_TRUE; 3669 Adapter->link_tid = 0; 3670 mutex_exit(&Adapter->link_lock); 3671 } 3672 3673 /* 3674 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 3675 * 3676 * This function read the forced speed and duplex for 10/100 Mbps speeds 3677 * and also for 1000 Mbps speeds from the e1000g.conf file 3678 */ 3679 static void 3680 e1000g_force_speed_duplex(struct e1000g *Adapter) 3681 { 3682 int forced; 3683 struct e1000_mac_info *mac = &Adapter->shared.mac; 3684 struct e1000_phy_info *phy = &Adapter->shared.phy; 3685 3686 /* 3687 * get value out of config file 3688 */ 3689 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 3690 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 3691 3692 switch (forced) { 3693 case GDIAG_10_HALF: 3694 /* 3695 * Disable Auto Negotiation 3696 */ 3697 mac->autoneg = B_FALSE; 3698 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3699 break; 3700 case GDIAG_10_FULL: 3701 /* 3702 * Disable Auto Negotiation 3703 */ 3704 mac->autoneg = B_FALSE; 3705 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3706 break; 3707 case GDIAG_100_HALF: 3708 /* 3709 * Disable Auto Negotiation 3710 */ 3711 mac->autoneg = B_FALSE; 3712 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3713 break; 3714 case GDIAG_100_FULL: 3715 /* 3716 * Disable Auto Negotiation 3717 */ 3718 mac->autoneg = B_FALSE; 3719 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3720 break; 3721 case GDIAG_1000_FULL: 3722 /* 3723 * The gigabit spec requires autonegotiation. Therefore, 3724 * when the user wants to force the speed to 1000Mbps, we 3725 * enable AutoNeg, but only allow the harware to advertise 3726 * 1000Mbps. This is different from 10/100 operation, where 3727 * we are allowed to link without any negotiation. 3728 */ 3729 mac->autoneg = B_TRUE; 3730 phy->autoneg_advertised = ADVERTISE_1000_FULL; 3731 break; 3732 default: /* obey the setting of AutoNegAdvertised */ 3733 mac->autoneg = B_TRUE; 3734 phy->autoneg_advertised = 3735 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 3736 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 3737 AUTONEG_ADVERTISE_SPEED_DEFAULT); 3738 break; 3739 } /* switch */ 3740 } 3741 3742 /* 3743 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 3744 * 3745 * This function reads MaxFrameSize from e1000g.conf 3746 */ 3747 static void 3748 e1000g_get_max_frame_size(struct e1000g *Adapter) 3749 { 3750 int max_frame; 3751 struct e1000_mac_info *mac = &Adapter->shared.mac; 3752 struct e1000_phy_info *phy = &Adapter->shared.phy; 3753 3754 /* 3755 * get value out of config file 3756 */ 3757 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 3758 3759 switch (max_frame) { 3760 case 0: 3761 Adapter->default_mtu = ETHERMTU; 3762 break; 3763 /* 3764 * To avoid excessive memory allocation for rx buffers, 3765 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 3766 */ 3767 case 1: 3768 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 3769 sizeof (struct ether_vlan_header) - ETHERFCSL - 3770 E1000G_IPALIGNPRESERVEROOM; 3771 break; 3772 case 2: 3773 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 3774 sizeof (struct ether_vlan_header) - ETHERFCSL - 3775 E1000G_IPALIGNPRESERVEROOM; 3776 break; 3777 case 3: 3778 if (mac->type >= e1000_82571) 3779 Adapter->default_mtu = MAXIMUM_MTU; 3780 else 3781 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 3782 sizeof (struct ether_vlan_header) - ETHERFCSL - 3783 E1000G_IPALIGNPRESERVEROOM; 3784 break; 3785 default: 3786 Adapter->default_mtu = ETHERMTU; 3787 break; 3788 } /* switch */ 3789 3790 Adapter->max_frame_size = Adapter->default_mtu + 3791 sizeof (struct ether_vlan_header) + ETHERFCSL; 3792 3793 /* ich8 does not do jumbo frames */ 3794 if (mac->type == e1000_ich8lan) { 3795 Adapter->max_frame_size = ETHERMAX; 3796 } 3797 3798 /* ich9 does not do jumbo frames on one phy type */ 3799 if ((mac->type == e1000_ich9lan) && 3800 (phy->type == e1000_phy_ife)) { 3801 Adapter->max_frame_size = ETHERMAX; 3802 } 3803 } 3804 3805 static void 3806 arm_watchdog_timer(struct e1000g *Adapter) 3807 { 3808 Adapter->watchdog_tid = 3809 timeout(e1000g_local_timer, 3810 (void *)Adapter, 1 * drv_usectohz(1000000)); 3811 } 3812 #pragma inline(arm_watchdog_timer) 3813 3814 static void 3815 enable_watchdog_timer(struct e1000g *Adapter) 3816 { 3817 mutex_enter(&Adapter->watchdog_lock); 3818 3819 if (!Adapter->watchdog_timer_enabled) { 3820 Adapter->watchdog_timer_enabled = B_TRUE; 3821 Adapter->watchdog_timer_started = B_TRUE; 3822 arm_watchdog_timer(Adapter); 3823 } 3824 3825 mutex_exit(&Adapter->watchdog_lock); 3826 } 3827 3828 static void 3829 disable_watchdog_timer(struct e1000g *Adapter) 3830 { 3831 timeout_id_t tid; 3832 3833 mutex_enter(&Adapter->watchdog_lock); 3834 3835 Adapter->watchdog_timer_enabled = B_FALSE; 3836 Adapter->watchdog_timer_started = B_FALSE; 3837 tid = Adapter->watchdog_tid; 3838 Adapter->watchdog_tid = 0; 3839 3840 mutex_exit(&Adapter->watchdog_lock); 3841 3842 if (tid != 0) 3843 (void) untimeout(tid); 3844 } 3845 3846 static void 3847 start_watchdog_timer(struct e1000g *Adapter) 3848 { 3849 mutex_enter(&Adapter->watchdog_lock); 3850 3851 if (Adapter->watchdog_timer_enabled) { 3852 if (!Adapter->watchdog_timer_started) { 3853 Adapter->watchdog_timer_started = B_TRUE; 3854 arm_watchdog_timer(Adapter); 3855 } 3856 } 3857 3858 mutex_exit(&Adapter->watchdog_lock); 3859 } 3860 3861 static void 3862 restart_watchdog_timer(struct e1000g *Adapter) 3863 { 3864 mutex_enter(&Adapter->watchdog_lock); 3865 3866 if (Adapter->watchdog_timer_started) 3867 arm_watchdog_timer(Adapter); 3868 3869 mutex_exit(&Adapter->watchdog_lock); 3870 } 3871 3872 static void 3873 stop_watchdog_timer(struct e1000g *Adapter) 3874 { 3875 timeout_id_t tid; 3876 3877 mutex_enter(&Adapter->watchdog_lock); 3878 3879 Adapter->watchdog_timer_started = B_FALSE; 3880 tid = Adapter->watchdog_tid; 3881 Adapter->watchdog_tid = 0; 3882 3883 mutex_exit(&Adapter->watchdog_lock); 3884 3885 if (tid != 0) 3886 (void) untimeout(tid); 3887 } 3888 3889 static void 3890 stop_link_timer(struct e1000g *Adapter) 3891 { 3892 timeout_id_t tid; 3893 3894 /* Disable the link timer */ 3895 mutex_enter(&Adapter->link_lock); 3896 3897 tid = Adapter->link_tid; 3898 Adapter->link_tid = 0; 3899 3900 mutex_exit(&Adapter->link_lock); 3901 3902 if (tid != 0) 3903 (void) untimeout(tid); 3904 } 3905 3906 static void 3907 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 3908 { 3909 timeout_id_t tid; 3910 3911 /* Disable the tx timer for 82547 chipset */ 3912 mutex_enter(&tx_ring->tx_lock); 3913 3914 tx_ring->timer_enable_82547 = B_FALSE; 3915 tid = tx_ring->timer_id_82547; 3916 tx_ring->timer_id_82547 = 0; 3917 3918 mutex_exit(&tx_ring->tx_lock); 3919 3920 if (tid != 0) 3921 (void) untimeout(tid); 3922 } 3923 3924 void 3925 e1000g_clear_interrupt(struct e1000g *Adapter) 3926 { 3927 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 3928 0xffffffff & ~E1000_IMS_RXSEQ); 3929 } 3930 3931 void 3932 e1000g_mask_interrupt(struct e1000g *Adapter) 3933 { 3934 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 3935 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 3936 3937 if (Adapter->tx_intr_enable) 3938 e1000g_mask_tx_interrupt(Adapter); 3939 } 3940 3941 void 3942 e1000g_clear_all_interrupts(struct e1000g *Adapter) 3943 { 3944 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 3945 } 3946 3947 void 3948 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 3949 { 3950 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 3951 } 3952 3953 void 3954 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 3955 { 3956 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 3957 } 3958 3959 static void 3960 e1000g_smartspeed(struct e1000g *Adapter) 3961 { 3962 struct e1000_hw *hw = &Adapter->shared; 3963 uint16_t phy_status; 3964 uint16_t phy_ctrl; 3965 3966 /* 3967 * If we're not T-or-T, or we're not autoneg'ing, or we're not 3968 * advertising 1000Full, we don't even use the workaround 3969 */ 3970 if ((hw->phy.type != e1000_phy_igp) || 3971 !hw->mac.autoneg || 3972 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 3973 return; 3974 3975 /* 3976 * True if this is the first call of this function or after every 3977 * 30 seconds of not having link 3978 */ 3979 if (Adapter->smartspeed == 0) { 3980 /* 3981 * If Master/Slave config fault is asserted twice, we 3982 * assume back-to-back 3983 */ 3984 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 3985 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3986 return; 3987 3988 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 3989 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3990 return; 3991 /* 3992 * We're assuming back-2-back because our status register 3993 * insists! there's a fault in the master/slave 3994 * relationship that was "negotiated" 3995 */ 3996 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 3997 /* 3998 * Is the phy configured for manual configuration of 3999 * master/slave? 4000 */ 4001 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4002 /* 4003 * Yes. Then disable manual configuration (enable 4004 * auto configuration) of master/slave 4005 */ 4006 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4007 e1000_write_phy_reg(hw, 4008 PHY_1000T_CTRL, phy_ctrl); 4009 /* 4010 * Effectively starting the clock 4011 */ 4012 Adapter->smartspeed++; 4013 /* 4014 * Restart autonegotiation 4015 */ 4016 if (!e1000_phy_setup_autoneg(hw) && 4017 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4018 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4019 MII_CR_RESTART_AUTO_NEG); 4020 e1000_write_phy_reg(hw, 4021 PHY_CONTROL, phy_ctrl); 4022 } 4023 } 4024 return; 4025 /* 4026 * Has 6 seconds transpired still without link? Remember, 4027 * you should reset the smartspeed counter once you obtain 4028 * link 4029 */ 4030 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4031 /* 4032 * Yes. Remember, we did at the start determine that 4033 * there's a master/slave configuration fault, so we're 4034 * still assuming there's someone on the other end, but we 4035 * just haven't yet been able to talk to it. We then 4036 * re-enable auto configuration of master/slave to see if 4037 * we're running 2/3 pair cables. 4038 */ 4039 /* 4040 * If still no link, perhaps using 2/3 pair cable 4041 */ 4042 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4043 phy_ctrl |= CR_1000T_MS_ENABLE; 4044 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4045 /* 4046 * Restart autoneg with phy enabled for manual 4047 * configuration of master/slave 4048 */ 4049 if (!e1000_phy_setup_autoneg(hw) && 4050 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4051 phy_ctrl |= 4052 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4053 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4054 } 4055 /* 4056 * Hopefully, there are no more faults and we've obtained 4057 * link as a result. 4058 */ 4059 } 4060 /* 4061 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4062 * seconds) 4063 */ 4064 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4065 Adapter->smartspeed = 0; 4066 } 4067 4068 static boolean_t 4069 is_valid_mac_addr(uint8_t *mac_addr) 4070 { 4071 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4072 const uint8_t addr_test2[6] = 4073 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4074 4075 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4076 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4077 return (B_FALSE); 4078 4079 return (B_TRUE); 4080 } 4081 4082 /* 4083 * e1000g_stall_check - check for tx stall 4084 * 4085 * This function checks if the adapter is stalled (in transmit). 4086 * 4087 * It is called each time the watchdog timeout is invoked. 4088 * If the transmit descriptor reclaim continuously fails, 4089 * the watchdog value will increment by 1. If the watchdog 4090 * value exceeds the threshold, the adapter is assumed to 4091 * have stalled and need to be reset. 4092 */ 4093 static boolean_t 4094 e1000g_stall_check(struct e1000g *Adapter) 4095 { 4096 e1000g_tx_ring_t *tx_ring; 4097 4098 tx_ring = Adapter->tx_ring; 4099 4100 if (Adapter->link_state != LINK_STATE_UP) 4101 return (B_FALSE); 4102 4103 if (tx_ring->recycle_fail > 0) 4104 tx_ring->stall_watchdog++; 4105 else 4106 tx_ring->stall_watchdog = 0; 4107 4108 if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) 4109 return (B_FALSE); 4110 4111 tx_ring->stall_watchdog = 0; 4112 tx_ring->recycle_fail = 0; 4113 4114 return (B_TRUE); 4115 } 4116 4117 #ifdef E1000G_DEBUG 4118 static enum ioc_reply 4119 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4120 { 4121 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4122 e1000g_peekpoke_t *ppd; 4123 uint64_t mem_va; 4124 uint64_t maxoff; 4125 boolean_t peek; 4126 4127 switch (iocp->ioc_cmd) { 4128 4129 case E1000G_IOC_REG_PEEK: 4130 peek = B_TRUE; 4131 break; 4132 4133 case E1000G_IOC_REG_POKE: 4134 peek = B_FALSE; 4135 break; 4136 4137 deault: 4138 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4139 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4140 iocp->ioc_cmd); 4141 return (IOC_INVAL); 4142 } 4143 4144 /* 4145 * Validate format of ioctl 4146 */ 4147 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4148 return (IOC_INVAL); 4149 if (mp->b_cont == NULL) 4150 return (IOC_INVAL); 4151 4152 ppd = (e1000g_peekpoke_t *)mp->b_cont->b_rptr; 4153 4154 /* 4155 * Validate request parameters 4156 */ 4157 switch (ppd->pp_acc_space) { 4158 4159 default: 4160 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4161 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4162 ppd->pp_acc_space); 4163 return (IOC_INVAL); 4164 4165 case E1000G_PP_SPACE_REG: 4166 /* 4167 * Memory-mapped I/O space 4168 */ 4169 ASSERT(ppd->pp_acc_size == 4); 4170 if (ppd->pp_acc_size != 4) 4171 return (IOC_INVAL); 4172 4173 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4174 return (IOC_INVAL); 4175 4176 mem_va = 0; 4177 maxoff = 0x10000; 4178 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4179 break; 4180 4181 case E1000G_PP_SPACE_E1000G: 4182 /* 4183 * E1000g data structure! 4184 */ 4185 mem_va = (uintptr_t)e1000gp; 4186 maxoff = sizeof (struct e1000g); 4187 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4188 break; 4189 4190 } 4191 4192 if (ppd->pp_acc_offset >= maxoff) 4193 return (IOC_INVAL); 4194 4195 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4196 return (IOC_INVAL); 4197 4198 /* 4199 * All OK - go! 4200 */ 4201 ppd->pp_acc_offset += mem_va; 4202 (*ppfn)(e1000gp, ppd); 4203 return (peek ? IOC_REPLY : IOC_ACK); 4204 } 4205 4206 static void 4207 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4208 { 4209 ddi_acc_handle_t handle; 4210 uint32_t *regaddr; 4211 4212 handle = e1000gp->osdep.reg_handle; 4213 regaddr = 4214 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 4215 4216 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4217 } 4218 4219 static void 4220 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4221 { 4222 ddi_acc_handle_t handle; 4223 uint32_t *regaddr; 4224 uint32_t value; 4225 4226 handle = e1000gp->osdep.reg_handle; 4227 regaddr = 4228 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 4229 value = (uint32_t)ppd->pp_acc_data; 4230 4231 ddi_put32(handle, regaddr, value); 4232 } 4233 4234 static void 4235 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4236 { 4237 uint64_t value; 4238 void *vaddr; 4239 4240 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4241 4242 switch (ppd->pp_acc_size) { 4243 case 1: 4244 value = *(uint8_t *)vaddr; 4245 break; 4246 4247 case 2: 4248 value = *(uint16_t *)vaddr; 4249 break; 4250 4251 case 4: 4252 value = *(uint32_t *)vaddr; 4253 break; 4254 4255 case 8: 4256 value = *(uint64_t *)vaddr; 4257 break; 4258 } 4259 4260 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4261 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4262 (void *)e1000gp, (void *)ppd, value, vaddr); 4263 4264 ppd->pp_acc_data = value; 4265 } 4266 4267 static void 4268 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4269 { 4270 uint64_t value; 4271 void *vaddr; 4272 4273 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4274 value = ppd->pp_acc_data; 4275 4276 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4277 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4278 (void *)e1000gp, (void *)ppd, value, vaddr); 4279 4280 switch (ppd->pp_acc_size) { 4281 case 1: 4282 *(uint8_t *)vaddr = (uint8_t)value; 4283 break; 4284 4285 case 2: 4286 *(uint16_t *)vaddr = (uint16_t)value; 4287 break; 4288 4289 case 4: 4290 *(uint32_t *)vaddr = (uint32_t)value; 4291 break; 4292 4293 case 8: 4294 *(uint64_t *)vaddr = (uint64_t)value; 4295 break; 4296 } 4297 } 4298 #endif 4299 4300 /* 4301 * Loopback Support 4302 */ 4303 static lb_property_t lb_normal = 4304 { normal, "normal", E1000G_LB_NONE }; 4305 static lb_property_t lb_external1000 = 4306 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4307 static lb_property_t lb_external100 = 4308 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4309 static lb_property_t lb_external10 = 4310 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4311 static lb_property_t lb_phy = 4312 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4313 4314 static enum ioc_reply 4315 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4316 { 4317 lb_info_sz_t *lbsp; 4318 lb_property_t *lbpp; 4319 struct e1000_hw *hw; 4320 uint32_t *lbmp; 4321 uint32_t size; 4322 uint32_t value; 4323 4324 hw = &Adapter->shared; 4325 4326 if (mp->b_cont == NULL) 4327 return (IOC_INVAL); 4328 4329 switch (iocp->ioc_cmd) { 4330 default: 4331 return (IOC_INVAL); 4332 4333 case LB_GET_INFO_SIZE: 4334 size = sizeof (lb_info_sz_t); 4335 if (iocp->ioc_count != size) 4336 return (IOC_INVAL); 4337 4338 rw_enter(&Adapter->chip_lock, RW_WRITER); 4339 e1000g_get_phy_state(Adapter); 4340 4341 /* 4342 * Workaround for hardware faults. In order to get a stable 4343 * state of phy, we will wait for a specific interval and 4344 * try again. The time delay is an experiential value based 4345 * on our testing. 4346 */ 4347 msec_delay(100); 4348 e1000g_get_phy_state(Adapter); 4349 rw_exit(&Adapter->chip_lock); 4350 4351 value = sizeof (lb_normal); 4352 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4353 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4354 (hw->phy.media_type == e1000_media_type_fiber) || 4355 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4356 value += sizeof (lb_phy); 4357 switch (hw->mac.type) { 4358 case e1000_82571: 4359 case e1000_82572: 4360 value += sizeof (lb_external1000); 4361 break; 4362 } 4363 } 4364 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4365 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4366 value += sizeof (lb_external100); 4367 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4368 value += sizeof (lb_external10); 4369 4370 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 4371 *lbsp = value; 4372 break; 4373 4374 case LB_GET_INFO: 4375 value = sizeof (lb_normal); 4376 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4377 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4378 (hw->phy.media_type == e1000_media_type_fiber) || 4379 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4380 value += sizeof (lb_phy); 4381 switch (hw->mac.type) { 4382 case e1000_82571: 4383 case e1000_82572: 4384 value += sizeof (lb_external1000); 4385 break; 4386 } 4387 } 4388 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4389 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4390 value += sizeof (lb_external100); 4391 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4392 value += sizeof (lb_external10); 4393 4394 size = value; 4395 if (iocp->ioc_count != size) 4396 return (IOC_INVAL); 4397 4398 value = 0; 4399 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 4400 lbpp[value++] = lb_normal; 4401 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4402 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4403 (hw->phy.media_type == e1000_media_type_fiber) || 4404 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4405 lbpp[value++] = lb_phy; 4406 switch (hw->mac.type) { 4407 case e1000_82571: 4408 case e1000_82572: 4409 lbpp[value++] = lb_external1000; 4410 break; 4411 } 4412 } 4413 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4414 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4415 lbpp[value++] = lb_external100; 4416 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4417 lbpp[value++] = lb_external10; 4418 break; 4419 4420 case LB_GET_MODE: 4421 size = sizeof (uint32_t); 4422 if (iocp->ioc_count != size) 4423 return (IOC_INVAL); 4424 4425 lbmp = (uint32_t *)mp->b_cont->b_rptr; 4426 *lbmp = Adapter->loopback_mode; 4427 break; 4428 4429 case LB_SET_MODE: 4430 size = 0; 4431 if (iocp->ioc_count != sizeof (uint32_t)) 4432 return (IOC_INVAL); 4433 4434 lbmp = (uint32_t *)mp->b_cont->b_rptr; 4435 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4436 return (IOC_INVAL); 4437 break; 4438 } 4439 4440 iocp->ioc_count = size; 4441 iocp->ioc_error = 0; 4442 4443 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4444 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4445 return (IOC_INVAL); 4446 } 4447 4448 return (IOC_REPLY); 4449 } 4450 4451 static boolean_t 4452 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 4453 { 4454 struct e1000_hw *hw; 4455 int i, times; 4456 boolean_t link_up; 4457 4458 if (mode == Adapter->loopback_mode) 4459 return (B_TRUE); 4460 4461 hw = &Adapter->shared; 4462 times = 0; 4463 4464 Adapter->loopback_mode = mode; 4465 4466 if (mode == E1000G_LB_NONE) { 4467 /* Reset the chip */ 4468 hw->phy.autoneg_wait_to_complete = B_TRUE; 4469 (void) e1000g_reset(Adapter); 4470 hw->phy.autoneg_wait_to_complete = B_FALSE; 4471 return (B_TRUE); 4472 } 4473 4474 again: 4475 4476 rw_enter(&Adapter->chip_lock, RW_WRITER); 4477 4478 switch (mode) { 4479 default: 4480 rw_exit(&Adapter->chip_lock); 4481 return (B_FALSE); 4482 4483 case E1000G_LB_EXTERNAL_1000: 4484 e1000g_set_external_loopback_1000(Adapter); 4485 break; 4486 4487 case E1000G_LB_EXTERNAL_100: 4488 e1000g_set_external_loopback_100(Adapter); 4489 break; 4490 4491 case E1000G_LB_EXTERNAL_10: 4492 e1000g_set_external_loopback_10(Adapter); 4493 break; 4494 4495 case E1000G_LB_INTERNAL_PHY: 4496 e1000g_set_internal_loopback(Adapter); 4497 break; 4498 } 4499 4500 times++; 4501 4502 rw_exit(&Adapter->chip_lock); 4503 4504 /* Wait for link up */ 4505 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 4506 msec_delay(100); 4507 4508 rw_enter(&Adapter->chip_lock, RW_WRITER); 4509 4510 link_up = e1000g_link_up(Adapter); 4511 4512 rw_exit(&Adapter->chip_lock); 4513 4514 if (!link_up) { 4515 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4516 "Failed to get the link up"); 4517 if (times < 2) { 4518 /* Reset the link */ 4519 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4520 "Reset the link ..."); 4521 (void) e1000g_reset(Adapter); 4522 goto again; 4523 } 4524 } 4525 4526 return (B_TRUE); 4527 } 4528 4529 /* 4530 * The following loopback settings are from Intel's technical 4531 * document - "How To Loopback". All the register settings and 4532 * time delay values are directly inherited from the document 4533 * without more explanations available. 4534 */ 4535 static void 4536 e1000g_set_internal_loopback(struct e1000g *Adapter) 4537 { 4538 struct e1000_hw *hw; 4539 uint32_t ctrl; 4540 uint32_t status; 4541 uint16_t phy_ctrl; 4542 uint32_t txcw; 4543 4544 hw = &Adapter->shared; 4545 4546 /* Disable Smart Power Down */ 4547 phy_spd_state(hw, B_FALSE); 4548 4549 e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4550 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 4551 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 4552 4553 switch (hw->mac.type) { 4554 case e1000_82540: 4555 case e1000_82545: 4556 case e1000_82545_rev_3: 4557 case e1000_82546: 4558 case e1000_82546_rev_3: 4559 case e1000_82573: 4560 /* Auto-MDI/MDIX off */ 4561 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 4562 /* Reset PHY to update Auto-MDI/MDIX */ 4563 e1000_write_phy_reg(hw, PHY_CONTROL, 4564 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 4565 /* Reset PHY to auto-neg off and force 1000 */ 4566 e1000_write_phy_reg(hw, PHY_CONTROL, 4567 phy_ctrl | MII_CR_RESET); 4568 /* 4569 * Disable PHY receiver for 82540/545/546 and 82573 Family. 4570 * See comments above e1000g_set_internal_loopback() for the 4571 * background. 4572 */ 4573 e1000_write_phy_reg(hw, 29, 0x001F); 4574 e1000_write_phy_reg(hw, 30, 0x8FFC); 4575 e1000_write_phy_reg(hw, 29, 0x001A); 4576 e1000_write_phy_reg(hw, 30, 0x8FF0); 4577 break; 4578 } 4579 4580 /* Set loopback */ 4581 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 4582 4583 msec_delay(250); 4584 4585 /* Now set up the MAC to the same speed/duplex as the PHY. */ 4586 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4587 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4588 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4589 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4590 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 4591 E1000_CTRL_FD); /* Force Duplex to FULL */ 4592 4593 switch (hw->mac.type) { 4594 case e1000_82540: 4595 case e1000_82545: 4596 case e1000_82545_rev_3: 4597 case e1000_82546: 4598 case e1000_82546_rev_3: 4599 /* 4600 * For some serdes we'll need to commit the writes now 4601 * so that the status is updated on link 4602 */ 4603 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 4604 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4605 msec_delay(100); 4606 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4607 } 4608 4609 if (hw->phy.media_type == e1000_media_type_copper) { 4610 /* Invert Loss of Signal */ 4611 ctrl |= E1000_CTRL_ILOS; 4612 } else { 4613 /* Set ILOS on fiber nic if half duplex is detected */ 4614 status = E1000_READ_REG(hw, E1000_STATUS); 4615 if ((status & E1000_STATUS_FD) == 0) 4616 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4617 } 4618 break; 4619 4620 case e1000_82571: 4621 case e1000_82572: 4622 /* 4623 * The fiber/SerDes versions of this adapter do not contain an 4624 * accessible PHY. Therefore, loopback beyond MAC must be done 4625 * using SerDes analog loopback. 4626 */ 4627 if (hw->phy.media_type != e1000_media_type_copper) { 4628 status = E1000_READ_REG(hw, E1000_STATUS); 4629 /* Set ILOS on fiber nic if half duplex is detected */ 4630 if (((status & E1000_STATUS_LU) == 0) || 4631 ((status & E1000_STATUS_FD) == 0) || 4632 (hw->phy.media_type == 4633 e1000_media_type_internal_serdes)) 4634 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4635 4636 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4637 txcw = E1000_READ_REG(hw, E1000_TXCW); 4638 txcw &= ~((uint32_t)1 << 31); 4639 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4640 4641 /* 4642 * Write 0x410 to Serdes Control register 4643 * to enable Serdes analog loopback 4644 */ 4645 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4646 msec_delay(10); 4647 } 4648 break; 4649 4650 case e1000_82573: 4651 ctrl |= E1000_CTRL_ILOS; 4652 break; 4653 } 4654 4655 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4656 4657 } 4658 4659 static void 4660 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 4661 { 4662 struct e1000_hw *hw; 4663 uint32_t rctl; 4664 uint32_t ctrl_ext; 4665 uint32_t ctrl; 4666 uint32_t status; 4667 uint32_t txcw; 4668 4669 hw = &Adapter->shared; 4670 4671 /* Disable Smart Power Down */ 4672 phy_spd_state(hw, B_FALSE); 4673 4674 switch (hw->phy.media_type) { 4675 case e1000_media_type_copper: 4676 /* Force link up (Must be done before the PHY writes) */ 4677 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4678 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 4679 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4680 4681 rctl = E1000_READ_REG(hw, E1000_RCTL); 4682 rctl |= (E1000_RCTL_EN | 4683 E1000_RCTL_SBP | 4684 E1000_RCTL_UPE | 4685 E1000_RCTL_MPE | 4686 E1000_RCTL_LPE | 4687 E1000_RCTL_BAM); /* 0x803E */ 4688 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4689 4690 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4691 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 4692 E1000_CTRL_EXT_SDP6_DATA | 4693 E1000_CTRL_EXT_SDP7_DATA | 4694 E1000_CTRL_EXT_SDP4_DIR | 4695 E1000_CTRL_EXT_SDP6_DIR | 4696 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 4697 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4698 4699 /* 4700 * This sequence tunes the PHY's SDP and no customer 4701 * settable values. For background, see comments above 4702 * e1000g_set_internal_loopback(). 4703 */ 4704 e1000_write_phy_reg(hw, 0x0, 0x140); 4705 msec_delay(10); 4706 e1000_write_phy_reg(hw, 0x9, 0x1A00); 4707 e1000_write_phy_reg(hw, 0x12, 0xC10); 4708 e1000_write_phy_reg(hw, 0x12, 0x1C10); 4709 e1000_write_phy_reg(hw, 0x1F37, 0x76); 4710 e1000_write_phy_reg(hw, 0x1F33, 0x1); 4711 e1000_write_phy_reg(hw, 0x1F33, 0x0); 4712 4713 e1000_write_phy_reg(hw, 0x1F35, 0x65); 4714 e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 4715 e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 4716 e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 4717 e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 4718 4719 msec_delay(50); 4720 break; 4721 case e1000_media_type_fiber: 4722 case e1000_media_type_internal_serdes: 4723 status = E1000_READ_REG(hw, E1000_STATUS); 4724 if (((status & E1000_STATUS_LU) == 0) || 4725 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4726 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4727 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4728 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4729 } 4730 4731 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4732 txcw = E1000_READ_REG(hw, E1000_TXCW); 4733 txcw &= ~((uint32_t)1 << 31); 4734 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4735 4736 /* 4737 * Write 0x410 to Serdes Control register 4738 * to enable Serdes analog loopback 4739 */ 4740 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4741 msec_delay(10); 4742 break; 4743 default: 4744 break; 4745 } 4746 } 4747 4748 static void 4749 e1000g_set_external_loopback_100(struct e1000g *Adapter) 4750 { 4751 struct e1000_hw *hw; 4752 uint32_t ctrl; 4753 uint16_t phy_ctrl; 4754 4755 hw = &Adapter->shared; 4756 4757 /* Disable Smart Power Down */ 4758 phy_spd_state(hw, B_FALSE); 4759 4760 phy_ctrl = (MII_CR_FULL_DUPLEX | 4761 MII_CR_SPEED_100); 4762 4763 /* Force 100/FD, reset PHY */ 4764 e1000_write_phy_reg(hw, PHY_CONTROL, 4765 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 4766 msec_delay(10); 4767 4768 /* Force 100/FD */ 4769 e1000_write_phy_reg(hw, PHY_CONTROL, 4770 phy_ctrl); /* 0x2100 */ 4771 msec_delay(10); 4772 4773 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4774 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4775 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4776 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4777 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4778 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4779 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 4780 E1000_CTRL_FD); /* Force Duplex to FULL */ 4781 4782 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4783 } 4784 4785 static void 4786 e1000g_set_external_loopback_10(struct e1000g *Adapter) 4787 { 4788 struct e1000_hw *hw; 4789 uint32_t ctrl; 4790 uint16_t phy_ctrl; 4791 4792 hw = &Adapter->shared; 4793 4794 /* Disable Smart Power Down */ 4795 phy_spd_state(hw, B_FALSE); 4796 4797 phy_ctrl = (MII_CR_FULL_DUPLEX | 4798 MII_CR_SPEED_10); 4799 4800 /* Force 10/FD, reset PHY */ 4801 e1000_write_phy_reg(hw, PHY_CONTROL, 4802 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 4803 msec_delay(10); 4804 4805 /* Force 10/FD */ 4806 e1000_write_phy_reg(hw, PHY_CONTROL, 4807 phy_ctrl); /* 0x0100 */ 4808 msec_delay(10); 4809 4810 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4811 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4812 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4813 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4814 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4815 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4816 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 4817 E1000_CTRL_FD); /* Force Duplex to FULL */ 4818 4819 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4820 } 4821 4822 #ifdef __sparc 4823 static boolean_t 4824 e1000g_find_mac_address(struct e1000g *Adapter) 4825 { 4826 struct e1000_hw *hw = &Adapter->shared; 4827 uchar_t *bytes; 4828 struct ether_addr sysaddr; 4829 uint_t nelts; 4830 int err; 4831 boolean_t found = B_FALSE; 4832 4833 /* 4834 * The "vendor's factory-set address" may already have 4835 * been extracted from the chip, but if the property 4836 * "local-mac-address" is set we use that instead. 4837 * 4838 * We check whether it looks like an array of 6 4839 * bytes (which it should, if OBP set it). If we can't 4840 * make sense of it this way, we'll ignore it. 4841 */ 4842 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4843 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 4844 if (err == DDI_PROP_SUCCESS) { 4845 if (nelts == ETHERADDRL) { 4846 while (nelts--) 4847 hw->mac.addr[nelts] = bytes[nelts]; 4848 found = B_TRUE; 4849 } 4850 ddi_prop_free(bytes); 4851 } 4852 4853 /* 4854 * Look up the OBP property "local-mac-address?". If the user has set 4855 * 'local-mac-address? = false', use "the system address" instead. 4856 */ 4857 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 4858 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 4859 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 4860 if (localetheraddr(NULL, &sysaddr) != 0) { 4861 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 4862 found = B_TRUE; 4863 } 4864 } 4865 ddi_prop_free(bytes); 4866 } 4867 4868 /* 4869 * Finally(!), if there's a valid "mac-address" property (created 4870 * if we netbooted from this interface), we must use this instead 4871 * of any of the above to ensure that the NFS/install server doesn't 4872 * get confused by the address changing as Solaris takes over! 4873 */ 4874 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4875 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 4876 if (err == DDI_PROP_SUCCESS) { 4877 if (nelts == ETHERADDRL) { 4878 while (nelts--) 4879 hw->mac.addr[nelts] = bytes[nelts]; 4880 found = B_TRUE; 4881 } 4882 ddi_prop_free(bytes); 4883 } 4884 4885 if (found) { 4886 bcopy(hw->mac.addr, hw->mac.perm_addr, 4887 ETHERADDRL); 4888 } 4889 4890 return (found); 4891 } 4892 #endif 4893 4894 static int 4895 e1000g_add_intrs(struct e1000g *Adapter) 4896 { 4897 dev_info_t *devinfo; 4898 int intr_types; 4899 int rc; 4900 4901 devinfo = Adapter->dip; 4902 4903 /* Get supported interrupt types */ 4904 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 4905 4906 if (rc != DDI_SUCCESS) { 4907 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4908 "Get supported interrupt types failed: %d\n", rc); 4909 return (DDI_FAILURE); 4910 } 4911 4912 /* 4913 * Based on Intel Technical Advisory document (TA-160), there are some 4914 * cases where some older Intel PCI-X NICs may "advertise" to the OS 4915 * that it supports MSI, but in fact has problems. 4916 * So we should only enable MSI for PCI-E NICs and disable MSI for old 4917 * PCI/PCI-X NICs. 4918 */ 4919 if (Adapter->shared.mac.type < e1000_82571) 4920 Adapter->msi_enabled = B_FALSE; 4921 4922 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enabled) { 4923 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 4924 4925 if (rc != DDI_SUCCESS) { 4926 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4927 "Add MSI failed, trying Legacy interrupts\n"); 4928 } else { 4929 Adapter->intr_type = DDI_INTR_TYPE_MSI; 4930 } 4931 } 4932 4933 if ((Adapter->intr_type == 0) && 4934 (intr_types & DDI_INTR_TYPE_FIXED)) { 4935 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 4936 4937 if (rc != DDI_SUCCESS) { 4938 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4939 "Add Legacy interrupts failed\n"); 4940 return (DDI_FAILURE); 4941 } 4942 4943 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 4944 } 4945 4946 if (Adapter->intr_type == 0) { 4947 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4948 "No interrupts registered\n"); 4949 return (DDI_FAILURE); 4950 } 4951 4952 return (DDI_SUCCESS); 4953 } 4954 4955 /* 4956 * e1000g_intr_add() handles MSI/Legacy interrupts 4957 */ 4958 static int 4959 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 4960 { 4961 dev_info_t *devinfo; 4962 int count, avail, actual; 4963 int x, y, rc, inum = 0; 4964 int flag; 4965 ddi_intr_handler_t *intr_handler; 4966 4967 devinfo = Adapter->dip; 4968 4969 /* get number of interrupts */ 4970 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 4971 if ((rc != DDI_SUCCESS) || (count == 0)) { 4972 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4973 "Get interrupt number failed. Return: %d, count: %d\n", 4974 rc, count); 4975 return (DDI_FAILURE); 4976 } 4977 4978 /* get number of available interrupts */ 4979 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 4980 if ((rc != DDI_SUCCESS) || (avail == 0)) { 4981 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4982 "Get interrupt available number failed. " 4983 "Return: %d, available: %d\n", rc, avail); 4984 return (DDI_FAILURE); 4985 } 4986 4987 if (avail < count) { 4988 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4989 "Interrupts count: %d, available: %d\n", 4990 count, avail); 4991 } 4992 4993 /* Allocate an array of interrupt handles */ 4994 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 4995 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 4996 4997 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 4998 flag = DDI_INTR_ALLOC_NORMAL; 4999 5000 /* call ddi_intr_alloc() */ 5001 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5002 count, &actual, flag); 5003 5004 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5005 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5006 "Allocate interrupts failed: %d\n", rc); 5007 5008 kmem_free(Adapter->htable, Adapter->intr_size); 5009 return (DDI_FAILURE); 5010 } 5011 5012 if (actual < count) { 5013 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5014 "Interrupts requested: %d, received: %d\n", 5015 count, actual); 5016 } 5017 5018 Adapter->intr_cnt = actual; 5019 5020 /* Get priority for first msi, assume remaining are all the same */ 5021 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5022 5023 if (rc != DDI_SUCCESS) { 5024 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5025 "Get interrupt priority failed: %d\n", rc); 5026 5027 /* Free already allocated intr */ 5028 for (y = 0; y < actual; y++) 5029 (void) ddi_intr_free(Adapter->htable[y]); 5030 5031 kmem_free(Adapter->htable, Adapter->intr_size); 5032 return (DDI_FAILURE); 5033 } 5034 5035 /* 5036 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5037 * use the interrupt service routine e1000g_intr_pciexpress() 5038 * to avoid interrupt stealing when sharing interrupt with other 5039 * devices. 5040 */ 5041 if (Adapter->shared.mac.type < e1000_82571) 5042 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5043 else 5044 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5045 5046 /* Call ddi_intr_add_handler() */ 5047 for (x = 0; x < actual; x++) { 5048 rc = ddi_intr_add_handler(Adapter->htable[x], 5049 intr_handler, (caddr_t)Adapter, NULL); 5050 5051 if (rc != DDI_SUCCESS) { 5052 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5053 "Add interrupt handler failed: %d\n", rc); 5054 5055 /* Remove already added handler */ 5056 for (y = 0; y < x; y++) 5057 (void) ddi_intr_remove_handler( 5058 Adapter->htable[y]); 5059 5060 /* Free already allocated intr */ 5061 for (y = 0; y < actual; y++) 5062 (void) ddi_intr_free(Adapter->htable[y]); 5063 5064 kmem_free(Adapter->htable, Adapter->intr_size); 5065 return (DDI_FAILURE); 5066 } 5067 } 5068 5069 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5070 5071 if (rc != DDI_SUCCESS) { 5072 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5073 "Get interrupt cap failed: %d\n", rc); 5074 5075 /* Free already allocated intr */ 5076 for (y = 0; y < actual; y++) { 5077 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5078 (void) ddi_intr_free(Adapter->htable[y]); 5079 } 5080 5081 kmem_free(Adapter->htable, Adapter->intr_size); 5082 return (DDI_FAILURE); 5083 } 5084 5085 return (DDI_SUCCESS); 5086 } 5087 5088 static int 5089 e1000g_rem_intrs(struct e1000g *Adapter) 5090 { 5091 int x; 5092 int rc; 5093 5094 for (x = 0; x < Adapter->intr_cnt; x++) { 5095 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5096 if (rc != DDI_SUCCESS) { 5097 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5098 "Remove intr handler failed: %d\n", rc); 5099 return (DDI_FAILURE); 5100 } 5101 5102 rc = ddi_intr_free(Adapter->htable[x]); 5103 if (rc != DDI_SUCCESS) { 5104 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5105 "Free intr failed: %d\n", rc); 5106 return (DDI_FAILURE); 5107 } 5108 } 5109 5110 kmem_free(Adapter->htable, Adapter->intr_size); 5111 5112 return (DDI_SUCCESS); 5113 } 5114 5115 static int 5116 e1000g_enable_intrs(struct e1000g *Adapter) 5117 { 5118 int x; 5119 int rc; 5120 5121 /* Enable interrupts */ 5122 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5123 /* Call ddi_intr_block_enable() for MSI */ 5124 rc = ddi_intr_block_enable(Adapter->htable, 5125 Adapter->intr_cnt); 5126 if (rc != DDI_SUCCESS) { 5127 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5128 "Enable block intr failed: %d\n", rc); 5129 return (DDI_FAILURE); 5130 } 5131 } else { 5132 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5133 for (x = 0; x < Adapter->intr_cnt; x++) { 5134 rc = ddi_intr_enable(Adapter->htable[x]); 5135 if (rc != DDI_SUCCESS) { 5136 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5137 "Enable intr failed: %d\n", rc); 5138 return (DDI_FAILURE); 5139 } 5140 } 5141 } 5142 5143 return (DDI_SUCCESS); 5144 } 5145 5146 static int 5147 e1000g_disable_intrs(struct e1000g *Adapter) 5148 { 5149 int x; 5150 int rc; 5151 5152 /* Disable all interrupts */ 5153 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5154 rc = ddi_intr_block_disable(Adapter->htable, 5155 Adapter->intr_cnt); 5156 if (rc != DDI_SUCCESS) { 5157 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5158 "Disable block intr failed: %d\n", rc); 5159 return (DDI_FAILURE); 5160 } 5161 } else { 5162 for (x = 0; x < Adapter->intr_cnt; x++) { 5163 rc = ddi_intr_disable(Adapter->htable[x]); 5164 if (rc != DDI_SUCCESS) { 5165 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5166 "Disable intr failed: %d\n", rc); 5167 return (DDI_FAILURE); 5168 } 5169 } 5170 } 5171 5172 return (DDI_SUCCESS); 5173 } 5174 5175 /* 5176 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5177 */ 5178 static void 5179 e1000g_get_phy_state(struct e1000g *Adapter) 5180 { 5181 struct e1000_hw *hw = &Adapter->shared; 5182 5183 e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5184 e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5185 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 5186 e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 5187 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 5188 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 5189 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &Adapter->phy_1000t_status); 5190 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 5191 5192 Adapter->param_autoneg_cap = 5193 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5194 Adapter->param_pause_cap = 5195 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5196 Adapter->param_asym_pause_cap = 5197 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5198 Adapter->param_1000fdx_cap = 5199 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5200 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5201 Adapter->param_1000hdx_cap = 5202 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5203 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5204 Adapter->param_100t4_cap = 5205 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5206 Adapter->param_100fdx_cap = 5207 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5208 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5209 Adapter->param_100hdx_cap = 5210 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5211 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5212 Adapter->param_10fdx_cap = 5213 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5214 Adapter->param_10hdx_cap = 5215 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5216 5217 Adapter->param_adv_autoneg = hw->mac.autoneg; 5218 Adapter->param_adv_pause = 5219 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5220 Adapter->param_adv_asym_pause = 5221 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5222 Adapter->param_adv_1000hdx = 5223 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5224 Adapter->param_adv_100t4 = 5225 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5226 if (Adapter->param_adv_autoneg == 1) { 5227 Adapter->param_adv_1000fdx = 5228 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5229 Adapter->param_adv_100fdx = 5230 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5231 Adapter->param_adv_100hdx = 5232 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5233 Adapter->param_adv_10fdx = 5234 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5235 Adapter->param_adv_10hdx = 5236 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5237 } 5238 5239 Adapter->param_lp_autoneg = 5240 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5241 Adapter->param_lp_pause = 5242 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5243 Adapter->param_lp_asym_pause = 5244 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5245 Adapter->param_lp_1000fdx = 5246 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5247 Adapter->param_lp_1000hdx = 5248 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5249 Adapter->param_lp_100t4 = 5250 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5251 Adapter->param_lp_100fdx = 5252 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5253 Adapter->param_lp_100hdx = 5254 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5255 Adapter->param_lp_10fdx = 5256 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5257 Adapter->param_lp_10hdx = 5258 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5259 } 5260 5261 /* 5262 * FMA support 5263 */ 5264 5265 int 5266 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5267 { 5268 ddi_fm_error_t de; 5269 5270 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5271 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5272 return (de.fme_status); 5273 } 5274 5275 int 5276 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5277 { 5278 ddi_fm_error_t de; 5279 5280 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5281 return (de.fme_status); 5282 } 5283 5284 /* 5285 * The IO fault service error handling callback function 5286 */ 5287 static int 5288 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5289 { 5290 /* 5291 * as the driver can always deal with an error in any dma or 5292 * access handle, we can just return the fme_status value. 5293 */ 5294 pci_ereport_post(dip, err, NULL); 5295 return (err->fme_status); 5296 } 5297 5298 static void 5299 e1000g_fm_init(struct e1000g *Adapter) 5300 { 5301 ddi_iblock_cookie_t iblk; 5302 int fma_acc_flag, fma_dma_flag; 5303 5304 /* Only register with IO Fault Services if we have some capability */ 5305 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5306 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5307 fma_acc_flag = 1; 5308 } else { 5309 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5310 fma_acc_flag = 0; 5311 } 5312 5313 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5314 fma_dma_flag = 1; 5315 } else { 5316 fma_dma_flag = 0; 5317 } 5318 5319 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5320 5321 if (Adapter->fm_capabilities) { 5322 5323 /* Register capabilities with IO Fault Services */ 5324 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5325 5326 /* 5327 * Initialize pci ereport capabilities if ereport capable 5328 */ 5329 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5330 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5331 pci_ereport_setup(Adapter->dip); 5332 5333 /* 5334 * Register error callback if error callback capable 5335 */ 5336 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5337 ddi_fm_handler_register(Adapter->dip, 5338 e1000g_fm_error_cb, (void*) Adapter); 5339 } 5340 } 5341 5342 static void 5343 e1000g_fm_fini(struct e1000g *Adapter) 5344 { 5345 /* Only unregister FMA capabilities if we registered some */ 5346 if (Adapter->fm_capabilities) { 5347 5348 /* 5349 * Release any resources allocated by pci_ereport_setup() 5350 */ 5351 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5352 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5353 pci_ereport_teardown(Adapter->dip); 5354 5355 /* 5356 * Un-register error callback if error callback capable 5357 */ 5358 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5359 ddi_fm_handler_unregister(Adapter->dip); 5360 5361 /* Unregister from IO Fault Services */ 5362 ddi_fm_fini(Adapter->dip); 5363 } 5364 } 5365 5366 void 5367 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 5368 { 5369 uint64_t ena; 5370 char buf[FM_MAX_CLASS]; 5371 5372 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5373 ena = fm_ena_generate(0, FM_ENA_FMT1); 5374 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 5375 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 5376 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5377 } 5378 } 5379 5380 static int 5381 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 5382 uint_t pr_valsize, void *pr_val) 5383 { 5384 link_flowctrl_t fl; 5385 uint32_t fc; 5386 int err = 0; 5387 5388 ASSERT(pr_valsize > 0); 5389 switch (pr_num) { 5390 case MAC_PROP_AUTONEG: 5391 *(uint8_t *)pr_val = 5392 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0); 5393 break; 5394 case MAC_PROP_FLOWCTRL: 5395 if (pr_valsize < sizeof (link_flowctrl_t)) 5396 return (EINVAL); 5397 fl = LINK_FLOWCTRL_BI; 5398 bcopy(&fl, pr_val, sizeof (fl)); 5399 break; 5400 case MAC_PROP_ADV_1000FDX_CAP: 5401 case MAC_PROP_EN_1000FDX_CAP: 5402 *(uint8_t *)pr_val = 5403 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5404 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5405 break; 5406 case MAC_PROP_ADV_1000HDX_CAP: 5407 case MAC_PROP_EN_1000HDX_CAP: 5408 *(uint8_t *)pr_val = 5409 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5410 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5411 break; 5412 case MAC_PROP_ADV_100FDX_CAP: 5413 case MAC_PROP_EN_100FDX_CAP: 5414 *(uint8_t *)pr_val = 5415 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5416 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5417 case MAC_PROP_ADV_100HDX_CAP: 5418 case MAC_PROP_EN_100HDX_CAP: 5419 *(uint8_t *)pr_val = 5420 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5421 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5422 break; 5423 case MAC_PROP_ADV_10FDX_CAP: 5424 case MAC_PROP_EN_10FDX_CAP: 5425 *(uint8_t *)pr_val = 5426 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5427 break; 5428 case MAC_PROP_ADV_10HDX_CAP: 5429 case MAC_PROP_EN_10HDX_CAP: 5430 *(uint8_t *)pr_val = 5431 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5432 break; 5433 default: 5434 err = ENOTSUP; 5435 break; 5436 } 5437 return (err); 5438 } 5439 5440 /* 5441 * synchronize the adv* and en* parameters. 5442 * 5443 * See comments in <sys/dld.h> for details of the *_en_* 5444 * parameters. The usage of ndd for setting adv parameters will 5445 * synchronize all the en parameters with the e1000g parameters, 5446 * implicity disalbing any settings made via dladm. 5447 */ 5448 static void 5449 e1000g_param_sync(struct e1000g *Adapter) 5450 { 5451 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 5452 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 5453 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 5454 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 5455 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 5456 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 5457 } 5458