1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 * 25 * Copyright 2016 Joyent, Inc. 26 */ 27 28 #ifndef _E1000_OSDEP_H 29 #define _E1000_OSDEP_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/types.h> 36 #include <sys/conf.h> 37 #include <sys/debug.h> 38 #include <sys/stropts.h> 39 #include <sys/stream.h> 40 #include <sys/strlog.h> 41 #include <sys/kmem.h> 42 #include <sys/stat.h> 43 #include <sys/kstat.h> 44 #include <sys/modctl.h> 45 #include <sys/errno.h> 46 #include <sys/ddi.h> 47 #include <sys/sunddi.h> 48 #include <sys/pci.h> 49 #include <sys/atomic.h> 50 #include <sys/note.h> 51 #include <sys/mutex.h> 52 #include <sys/pci_cap.h> 53 #include "e1000g_debug.h" 54 55 #define usec_delay(x) drv_usecwait(x) 56 #define usec_delay_irq usec_delay 57 #define msec_delay(x) drv_usecwait(x * 1000) 58 #define msec_delay_irq msec_delay 59 60 #ifdef E1000G_DEBUG 61 #define DEBUGOUT(S) \ 62 E1000G_DEBUGLOG_0(NULL, E1000G_INFO_LEVEL, S) 63 #define DEBUGOUT1(S, A) \ 64 E1000G_DEBUGLOG_1(NULL, E1000G_INFO_LEVEL, S, A) 65 #define DEBUGOUT2(S, A, B) \ 66 E1000G_DEBUGLOG_2(NULL, E1000G_INFO_LEVEL, S, A, B) 67 #define DEBUGOUT3(S, A, B, C) \ 68 E1000G_DEBUGLOG_3(NULL, E1000G_INFO_LEVEL, S, A, B, C) 69 #define DEBUGFUNC(F) \ 70 E1000G_DEBUGLOG_0(NULL, E1000G_TRACE_LEVEL, F) 71 #else 72 #define DEBUGOUT(S) 73 #define DEBUGOUT1(S, A) 74 #define DEBUGOUT2(S, A, B) 75 #define DEBUGOUT3(S, A, B, C) 76 #define DEBUGFUNC(F) 77 #endif 78 79 #define OS_DEP(hw) ((struct e1000g_osdep *)((hw)->back)) 80 81 #define false 0 82 #define true 1 83 #define FALSE false 84 #define TRUE true 85 86 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ 87 #define PCI_COMMAND_REGISTER 0x04 88 #define PCI_EX_CONF_CAP 0xE0 89 #define ADAPTER_REG_SET 1 /* solaris mapping of adapter registers */ 90 #define ICH_FLASH_REG_SET 2 /* solaris mapping of flash memory */ 91 92 #define RECEIVE_BUFFER_ALIGN_SIZE 256 93 #define E1000_MDALIGN 4096 94 #define E1000_MDALIGN_82546 65536 95 #define E1000_ERT_2048 0x100 96 97 /* PHY Extended Status Register */ 98 #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 99 #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 100 #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 101 #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 102 103 /* 104 * required by shared code 105 */ 106 #define E1000_WRITE_FLUSH(a) (void)E1000_READ_REG(a, E1000_STATUS) 107 108 /* 109 * Note, for all of the following register defines, it's important that these be 110 * in do {} while loops that only run a single time. Previously they were formed 111 * as normal blocks. Unfortunately this would fail in the following form which 112 * is used in the common code: 113 * 114 * if (cond) 115 * E1000_WRITE_REG 116 * else 117 * ... 118 * 119 * When the E1000_WRITE_REG macros was missing the do keyword, the compiler 120 * would end up associating the outer brace of the block with the if statement 121 * and thus the else clause would get left behind. 122 */ 123 #define E1000_WRITE_REG(hw, reg, value) \ 124 do { \ 125 if ((hw)->mac.type != e1000_82542) \ 126 ddi_put32((OS_DEP(hw))->reg_handle, \ 127 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg), \ 128 value); \ 129 else \ 130 ddi_put32((OS_DEP(hw))->reg_handle, \ 131 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 132 e1000_translate_register_82542(reg)), \ 133 value); \ 134 } while (0) 135 136 #define E1000_READ_REG(hw, reg) (\ 137 ((hw)->mac.type != e1000_82542) ? \ 138 ddi_get32((OS_DEP(hw))->reg_handle, \ 139 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg)) : \ 140 ddi_get32((OS_DEP(hw))->reg_handle, \ 141 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 142 e1000_translate_register_82542(reg)))) 143 144 #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ 145 do {\ 146 if ((hw)->mac.type != e1000_82542) \ 147 ddi_put32((OS_DEP(hw))->reg_handle, \ 148 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 149 reg + ((offset) << 2)),\ 150 value); \ 151 else \ 152 ddi_put32((OS_DEP(hw))->reg_handle, \ 153 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 154 e1000_translate_register_82542(reg) + \ 155 ((offset) << 2)), value); \ 156 } while (0) 157 158 #define E1000_READ_REG_ARRAY(hw, reg, offset) (\ 159 ((hw)->mac.type != e1000_82542) ? \ 160 ddi_get32((OS_DEP(hw))->reg_handle, \ 161 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg + \ 162 ((offset) << 2))) : \ 163 ddi_get32((OS_DEP(hw))->reg_handle, \ 164 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 165 e1000_translate_register_82542(reg) + \ 166 ((offset) << 2)))) 167 168 169 #define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value) \ 170 E1000_WRITE_REG_ARRAY(a, reg, offset, value) 171 #define E1000_READ_REG_ARRAY_DWORD(a, reg, offset) \ 172 E1000_READ_REG_ARRAY(a, reg, offset) 173 174 175 #define E1000_READ_FLASH_REG(hw, reg) \ 176 ddi_get32((OS_DEP(hw))->ich_flash_handle, \ 177 (uint32_t *)((uintptr_t)(hw)->flash_address + (reg))) 178 179 #define E1000_READ_FLASH_REG16(hw, reg) \ 180 ddi_get16((OS_DEP(hw))->ich_flash_handle, \ 181 (uint16_t *)((uintptr_t)(hw)->flash_address + (reg))) 182 183 #define E1000_WRITE_FLASH_REG(hw, reg, value) \ 184 ddi_put32((OS_DEP(hw))->ich_flash_handle, \ 185 (uint32_t *)((uintptr_t)(hw)->flash_address + (reg)), (value)) 186 187 #define E1000_WRITE_FLASH_REG16(hw, reg, value) \ 188 ddi_put16((OS_DEP(hw))->ich_flash_handle, \ 189 (uint16_t *)((uintptr_t)(hw)->flash_address + (reg)), (value)) 190 191 #define UNREFERENCED_1PARAMETER(_p) _NOTE(ARGUNUSED(_p)) 192 #define UNREFERENCED_2PARAMETER(_p, _q) _NOTE(ARGUNUSED(_p, _q)) 193 #define UNREFERENCED_3PARAMETER(_p, _q, _r) _NOTE(ARGUNUSED(_p, _q, _r)) 194 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) _NOTE(ARGUNUSED(_p, _q, _r, _s)) 195 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) \ 196 _NOTE(ARGUNUSED(_p, _q, _r, _s, _t)) 197 198 typedef int8_t s8; 199 typedef int16_t s16; 200 typedef int32_t s32; 201 typedef int64_t s64; 202 typedef uint8_t u8; 203 typedef uint16_t u16; 204 typedef uint32_t u32; 205 typedef uint64_t u64; 206 typedef boolean_t bool; 207 208 #define __le16 u16 209 #define __le32 u32 210 #define __le64 u64 211 212 struct e1000g_osdep { 213 ddi_acc_handle_t reg_handle; 214 ddi_acc_handle_t cfg_handle; 215 ddi_acc_handle_t ich_flash_handle; 216 ddi_acc_handle_t io_reg_handle; 217 struct e1000g *adapter; 218 }; 219 220 /* Shared Code Mutex Defines */ 221 #define E1000_MUTEX kmutex_t 222 #define E1000_MUTEX_INIT(mutex) mutex_init(mutex, NULL, \ 223 MUTEX_DRIVER, NULL) 224 #define E1000_MUTEX_DESTROY(mutex) mutex_destroy(mutex) 225 226 #define E1000_MUTEX_LOCK(mutex) mutex_enter(mutex) 227 #define E1000_MUTEX_TRYLOCK(mutex) mutex_tryenter(mutex) 228 #define E1000_MUTEX_UNLOCK(mutex) mutex_exit(mutex) 229 230 #ifdef __sparc /* on SPARC, use only memory-mapped routines */ 231 #define E1000_WRITE_REG_IO E1000_WRITE_REG 232 #else /* on x86, use port io routines */ 233 #define E1000_WRITE_REG_IO(a, reg, val) { \ 234 ddi_put32((OS_DEP(a))->io_reg_handle, \ 235 (uint32_t *)(a)->io_base, \ 236 reg); \ 237 ddi_put32((OS_DEP(a))->io_reg_handle, \ 238 (uint32_t *)((a)->io_base + 4), \ 239 val); \ 240 } 241 #endif /* __sparc */ 242 243 #ifdef __cplusplus 244 } 245 #endif 246 247 #endif /* _E1000_OSDEP_H */ 248