1 /****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 82562G 10/100 Network Connection 36 * 82562G-2 10/100 Network Connection 37 * 82562GT 10/100 Network Connection 38 * 82562GT-2 10/100 Network Connection 39 * 82562V 10/100 Network Connection 40 * 82562V-2 10/100 Network Connection 41 * 82566DC-2 Gigabit Network Connection 42 * 82566DC Gigabit Network Connection 43 * 82566DM-2 Gigabit Network Connection 44 * 82566DM Gigabit Network Connection 45 * 82566MC Gigabit Network Connection 46 * 82566MM Gigabit Network Connection 47 * 82567LM Gigabit Network Connection 48 * 82567LF Gigabit Network Connection 49 * 82567V Gigabit Network Connection 50 * 82567LM-2 Gigabit Network Connection 51 * 82567LF-2 Gigabit Network Connection 52 * 82567V-2 Gigabit Network Connection 53 * 82567LF-3 Gigabit Network Connection 54 * 82567LM-3 Gigabit Network Connection 55 * 82567LM-4 Gigabit Network Connection 56 * 82577LM Gigabit Network Connection 57 * 82577LC Gigabit Network Connection 58 * 82578DM Gigabit Network Connection 59 * 82578DC Gigabit Network Connection 60 * 82579LM Gigabit Network Connection 61 * 82579V Gigabit Network Connection 62 * Ethernet Connection I217-LM 63 * Ethernet Connection I217-V 64 * Ethernet Connection I218-V 65 * Ethernet Connection I218-LM 66 * Ethernet Connection (2) I218-LM 67 * Ethernet Connection (2) I218-V 68 * Ethernet Connection (3) I218-LM 69 * Ethernet Connection (3) I218-V 70 */ 71 72 #include "e1000_api.h" 73 74 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); 75 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw); 76 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw); 77 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw); 78 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 79 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 80 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 81 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 82 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw); 83 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, 84 u8 *mc_addr_list, 85 u32 mc_addr_count); 86 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); 87 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); 88 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 89 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 90 bool active); 91 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 92 bool active); 93 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 94 u16 words, u16 *data); 95 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 96 u16 *data); 97 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 98 u16 words, u16 *data); 99 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw); 100 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw); 101 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw); 102 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, 103 u16 *data); 104 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 105 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw); 106 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); 107 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); 108 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); 109 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); 110 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 111 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, 112 u16 *speed, u16 *duplex); 113 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 114 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 115 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 116 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 117 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 118 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 119 static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 120 static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 121 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 122 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 123 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 124 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 125 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, 126 u32 offset, u8 *data); 127 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 128 u8 size, u16 *data); 129 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 130 u32 *data); 131 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, 132 u32 offset, u32 *data); 133 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, 134 u32 offset, u32 data); 135 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 136 u32 offset, u32 dword); 137 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, 138 u32 offset, u16 *data); 139 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 140 u32 offset, u8 byte); 141 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); 142 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 143 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw); 144 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 145 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 146 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 147 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr); 148 149 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 150 /* Offset 04h HSFSTS */ 151 union ich8_hws_flash_status { 152 struct ich8_hsfsts { 153 u16 flcdone:1; /* bit 0 Flash Cycle Done */ 154 u16 flcerr:1; /* bit 1 Flash Cycle Error */ 155 u16 dael:1; /* bit 2 Direct Access error Log */ 156 u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 157 u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 158 u16 reserved1:2; /* bit 13:6 Reserved */ 159 u16 reserved2:6; /* bit 13:6 Reserved */ 160 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 161 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 162 } hsf_status; 163 u16 regval; 164 }; 165 166 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 167 /* Offset 06h FLCTL */ 168 union ich8_hws_flash_ctrl { 169 struct ich8_hsflctl { 170 u16 flcgo:1; /* 0 Flash Cycle Go */ 171 u16 flcycle:2; /* 2:1 Flash Cycle */ 172 u16 reserved:5; /* 7:3 Reserved */ 173 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 174 u16 flockdn:6; /* 15:10 Reserved */ 175 } hsf_ctrl; 176 u16 regval; 177 }; 178 179 /* ICH Flash Region Access Permissions */ 180 union ich8_hws_flash_regacc { 181 struct ich8_flracc { 182 u32 grra:8; /* 0:7 GbE region Read Access */ 183 u32 grwa:8; /* 8:15 GbE region Write Access */ 184 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 185 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 186 } hsf_flregacc; 187 u16 regval; 188 }; 189 190 /** 191 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 192 * @hw: pointer to the HW structure 193 * 194 * Test access to the PHY registers by reading the PHY ID registers. If 195 * the PHY ID is already known (e.g. resume path) compare it with known ID, 196 * otherwise assume the read PHY ID is correct if it is valid. 197 * 198 * Assumes the sw/fw/hw semaphore is already acquired. 199 **/ 200 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 201 { 202 u16 phy_reg = 0; 203 u32 phy_id = 0; 204 s32 ret_val = 0; 205 u16 retry_count; 206 u32 mac_reg = 0; 207 208 for (retry_count = 0; retry_count < 2; retry_count++) { 209 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg); 210 if (ret_val || (phy_reg == 0xFFFF)) 211 continue; 212 phy_id = (u32)(phy_reg << 16); 213 214 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg); 215 if (ret_val || (phy_reg == 0xFFFF)) { 216 phy_id = 0; 217 continue; 218 } 219 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 220 break; 221 } 222 223 if (hw->phy.id) { 224 if (hw->phy.id == phy_id) 225 goto out; 226 } else if (phy_id) { 227 hw->phy.id = phy_id; 228 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 229 goto out; 230 } 231 232 /* In case the PHY needs to be in mdio slow mode, 233 * set slow mode and try to get the PHY id again. 234 */ 235 if (hw->mac.type < e1000_pch_lpt) { 236 hw->phy.ops.release(hw); 237 ret_val = e1000_set_mdio_slow_mode_hv(hw); 238 if (!ret_val) 239 ret_val = e1000_get_phy_id(hw); 240 hw->phy.ops.acquire(hw); 241 } 242 243 if (ret_val) 244 return FALSE; 245 out: 246 if (hw->mac.type >= e1000_pch_lpt) { 247 /* Only unforce SMBus if ME is not active */ 248 if (!(E1000_READ_REG(hw, E1000_FWSM) & 249 E1000_ICH_FWSM_FW_VALID)) { 250 /* Unforce SMBus mode in PHY */ 251 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg); 252 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 253 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg); 254 255 /* Unforce SMBus mode in MAC */ 256 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 257 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 258 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 259 } 260 } 261 262 return TRUE; 263 } 264 265 /** 266 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 267 * @hw: pointer to the HW structure 268 * 269 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 270 * used to reset the PHY to a quiescent state when necessary. 271 **/ 272 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) 273 { 274 u32 mac_reg; 275 276 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt"); 277 278 /* Set Phy Config Counter to 50msec */ 279 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3); 280 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 281 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 282 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg); 283 284 /* Toggle LANPHYPC Value bit */ 285 mac_reg = E1000_READ_REG(hw, E1000_CTRL); 286 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 287 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 288 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg); 289 E1000_WRITE_FLUSH(hw); 290 msec_delay(1); 291 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 292 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg); 293 E1000_WRITE_FLUSH(hw); 294 295 if (hw->mac.type < e1000_pch_lpt) { 296 msec_delay(50); 297 } else { 298 u16 count = 20; 299 300 do { 301 msec_delay(5); 302 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) & 303 E1000_CTRL_EXT_LPCD) && count--); 304 305 msec_delay(30); 306 } 307 } 308 309 /** 310 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 311 * @hw: pointer to the HW structure 312 * 313 * Workarounds/flow necessary for PHY initialization during driver load 314 * and resume paths. 315 **/ 316 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 317 { 318 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM); 319 s32 ret_val; 320 321 DEBUGFUNC("e1000_init_phy_workarounds_pchlan"); 322 323 /* Gate automatic PHY configuration by hardware on managed and 324 * non-managed 82579 and newer adapters. 325 */ 326 e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 327 328 /* It is not possible to be certain of the current state of ULP 329 * so forcibly disable it. 330 */ 331 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; 332 e1000_disable_ulp_lpt_lp(hw, TRUE); 333 334 ret_val = hw->phy.ops.acquire(hw); 335 if (ret_val) { 336 DEBUGOUT("Failed to initialize PHY flow\n"); 337 goto out; 338 } 339 340 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 341 * inaccessible and resetting the PHY is not blocked, toggle the 342 * LANPHYPC Value bit to force the interconnect to PCIe mode. 343 */ 344 switch (hw->mac.type) { 345 case e1000_pch_lpt: 346 case e1000_pch_spt: 347 case e1000_pch_cnp: 348 case e1000_pch_tgp: 349 case e1000_pch_adp: 350 case e1000_pch_mtp: 351 case e1000_pch_lnp: 352 case e1000_pch_rpl: 353 if (e1000_phy_is_accessible_pchlan(hw)) 354 break; 355 356 /* Before toggling LANPHYPC, see if PHY is accessible by 357 * forcing MAC to SMBus mode first. 358 */ 359 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 360 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 361 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 362 363 /* Wait 50 milliseconds for MAC to finish any retries 364 * that it might be trying to perform from previous 365 * attempts to acknowledge any phy read requests. 366 */ 367 msec_delay(50); 368 369 /* fall-through */ 370 case e1000_pch2lan: 371 if (e1000_phy_is_accessible_pchlan(hw)) 372 break; 373 374 /* fall-through */ 375 case e1000_pchlan: 376 if ((hw->mac.type == e1000_pchlan) && 377 (fwsm & E1000_ICH_FWSM_FW_VALID)) 378 break; 379 380 if (hw->phy.ops.check_reset_block(hw)) { 381 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n"); 382 ret_val = -E1000_ERR_PHY; 383 break; 384 } 385 386 /* Toggle LANPHYPC Value bit */ 387 e1000_toggle_lanphypc_pch_lpt(hw); 388 if (hw->mac.type >= e1000_pch_lpt) { 389 if (e1000_phy_is_accessible_pchlan(hw)) 390 break; 391 392 /* Toggling LANPHYPC brings the PHY out of SMBus mode 393 * so ensure that the MAC is also out of SMBus mode 394 */ 395 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 396 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 397 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 398 399 if (e1000_phy_is_accessible_pchlan(hw)) 400 break; 401 402 ret_val = -E1000_ERR_PHY; 403 } 404 break; 405 default: 406 break; 407 } 408 409 hw->phy.ops.release(hw); 410 if (!ret_val) { 411 412 /* Check to see if able to reset PHY. Print error if not */ 413 if (hw->phy.ops.check_reset_block(hw)) { 414 ERROR_REPORT("Reset blocked by ME\n"); 415 goto out; 416 } 417 418 /* Reset the PHY before any access to it. Doing so, ensures 419 * that the PHY is in a known good state before we read/write 420 * PHY registers. The generic reset is sufficient here, 421 * because we haven't determined the PHY type yet. 422 */ 423 ret_val = e1000_phy_hw_reset_generic(hw); 424 if (ret_val) 425 goto out; 426 427 /* On a successful reset, possibly need to wait for the PHY 428 * to quiesce to an accessible state before returning control 429 * to the calling function. If the PHY does not quiesce, then 430 * return E1000E_BLK_PHY_RESET, as this is the condition that 431 * the PHY is in. 432 */ 433 ret_val = hw->phy.ops.check_reset_block(hw); 434 if (ret_val) 435 ERROR_REPORT("ME blocked access to PHY after reset\n"); 436 } 437 438 out: 439 /* Ungate automatic PHY configuration on non-managed 82579 */ 440 if ((hw->mac.type == e1000_pch2lan) && 441 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 442 msec_delay(10); 443 e1000_gate_hw_phy_config_ich8lan(hw, FALSE); 444 } 445 446 return ret_val; 447 } 448 449 /** 450 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 451 * @hw: pointer to the HW structure 452 * 453 * Initialize family-specific PHY parameters and function pointers. 454 **/ 455 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 456 { 457 struct e1000_phy_info *phy = &hw->phy; 458 s32 ret_val; 459 460 DEBUGFUNC("e1000_init_phy_params_pchlan"); 461 462 phy->addr = 1; 463 phy->reset_delay_us = 100; 464 465 phy->ops.acquire = e1000_acquire_swflag_ich8lan; 466 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 467 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 468 phy->ops.set_page = e1000_set_page_igp; 469 phy->ops.read_reg = e1000_read_phy_reg_hv; 470 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 471 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 472 phy->ops.release = e1000_release_swflag_ich8lan; 473 phy->ops.reset = e1000_phy_hw_reset_ich8lan; 474 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 475 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 476 phy->ops.write_reg = e1000_write_phy_reg_hv; 477 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 478 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 479 phy->ops.power_up = e1000_power_up_phy_copper; 480 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 481 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 482 483 phy->id = e1000_phy_unknown; 484 485 ret_val = e1000_init_phy_workarounds_pchlan(hw); 486 if (ret_val) 487 return ret_val; 488 489 if (phy->id == e1000_phy_unknown) 490 switch (hw->mac.type) { 491 default: 492 ret_val = e1000_get_phy_id(hw); 493 if (ret_val) 494 return ret_val; 495 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 496 break; 497 /* fall-through */ 498 case e1000_pch2lan: 499 case e1000_pch_lpt: 500 case e1000_pch_spt: 501 case e1000_pch_cnp: 502 case e1000_pch_tgp: 503 case e1000_pch_adp: 504 case e1000_pch_mtp: 505 case e1000_pch_lnp: 506 case e1000_pch_rpl: 507 /* In case the PHY needs to be in mdio slow mode, 508 * set slow mode and try to get the PHY id again. 509 */ 510 ret_val = e1000_set_mdio_slow_mode_hv(hw); 511 if (ret_val) 512 return ret_val; 513 ret_val = e1000_get_phy_id(hw); 514 if (ret_val) 515 return ret_val; 516 break; 517 } 518 phy->type = e1000_get_phy_type_from_id(phy->id); 519 520 switch (phy->type) { 521 case e1000_phy_82577: 522 case e1000_phy_82579: 523 case e1000_phy_i217: 524 phy->ops.check_polarity = e1000_check_polarity_82577; 525 phy->ops.force_speed_duplex = 526 e1000_phy_force_speed_duplex_82577; 527 phy->ops.get_cable_length = e1000_get_cable_length_82577; 528 phy->ops.get_info = e1000_get_phy_info_82577; 529 phy->ops.commit = e1000_phy_sw_reset_generic; 530 break; 531 case e1000_phy_82578: 532 phy->ops.check_polarity = e1000_check_polarity_m88; 533 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 534 phy->ops.get_cable_length = e1000_get_cable_length_m88; 535 phy->ops.get_info = e1000_get_phy_info_m88; 536 break; 537 default: 538 ret_val = -E1000_ERR_PHY; 539 break; 540 } 541 542 return ret_val; 543 } 544 545 /** 546 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 547 * @hw: pointer to the HW structure 548 * 549 * Initialize family-specific PHY parameters and function pointers. 550 **/ 551 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 552 { 553 struct e1000_phy_info *phy = &hw->phy; 554 s32 ret_val; 555 u16 i = 0; 556 557 DEBUGFUNC("e1000_init_phy_params_ich8lan"); 558 559 phy->addr = 1; 560 phy->reset_delay_us = 100; 561 562 phy->ops.acquire = e1000_acquire_swflag_ich8lan; 563 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 564 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 565 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 566 phy->ops.read_reg = e1000_read_phy_reg_igp; 567 phy->ops.release = e1000_release_swflag_ich8lan; 568 phy->ops.reset = e1000_phy_hw_reset_ich8lan; 569 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; 570 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; 571 phy->ops.write_reg = e1000_write_phy_reg_igp; 572 phy->ops.power_up = e1000_power_up_phy_copper; 573 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 574 575 /* We may need to do this twice - once for IGP and if that fails, 576 * we'll set BM func pointers and try again 577 */ 578 ret_val = e1000_determine_phy_address(hw); 579 if (ret_val) { 580 phy->ops.write_reg = e1000_write_phy_reg_bm; 581 phy->ops.read_reg = e1000_read_phy_reg_bm; 582 ret_val = e1000_determine_phy_address(hw); 583 if (ret_val) { 584 DEBUGOUT("Cannot determine PHY addr. Erroring out\n"); 585 return ret_val; 586 } 587 } 588 589 phy->id = 0; 590 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && 591 (i++ < 100)) { 592 msec_delay(1); 593 ret_val = e1000_get_phy_id(hw); 594 if (ret_val) 595 return ret_val; 596 } 597 598 /* Verify phy id */ 599 switch (phy->id) { 600 case IGP03E1000_E_PHY_ID: 601 phy->type = e1000_phy_igp_3; 602 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 603 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked; 604 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked; 605 phy->ops.get_info = e1000_get_phy_info_igp; 606 phy->ops.check_polarity = e1000_check_polarity_igp; 607 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 608 break; 609 case IFE_E_PHY_ID: 610 case IFE_PLUS_E_PHY_ID: 611 case IFE_C_E_PHY_ID: 612 phy->type = e1000_phy_ife; 613 phy->autoneg_mask = E1000_ALL_NOT_GIG; 614 phy->ops.get_info = e1000_get_phy_info_ife; 615 phy->ops.check_polarity = e1000_check_polarity_ife; 616 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 617 break; 618 case BME1000_E_PHY_ID: 619 phy->type = e1000_phy_bm; 620 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 621 phy->ops.read_reg = e1000_read_phy_reg_bm; 622 phy->ops.write_reg = e1000_write_phy_reg_bm; 623 phy->ops.commit = e1000_phy_sw_reset_generic; 624 phy->ops.get_info = e1000_get_phy_info_m88; 625 phy->ops.check_polarity = e1000_check_polarity_m88; 626 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 627 break; 628 default: 629 return -E1000_ERR_PHY; 630 break; 631 } 632 633 return E1000_SUCCESS; 634 } 635 636 /** 637 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 638 * @hw: pointer to the HW structure 639 * 640 * Initialize family-specific NVM parameters and function 641 * pointers. 642 **/ 643 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 644 { 645 struct e1000_nvm_info *nvm = &hw->nvm; 646 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 647 u32 gfpreg, sector_base_addr, sector_end_addr; 648 u16 i; 649 u32 nvm_size; 650 651 DEBUGFUNC("e1000_init_nvm_params_ich8lan"); 652 653 nvm->type = e1000_nvm_flash_sw; 654 655 if (hw->mac.type >= e1000_pch_spt) { 656 /* in SPT, gfpreg doesn't exist. NVM size is taken from the 657 * STRAP register. This is because in SPT the GbE Flash region 658 * is no longer accessed through the flash registers. Instead, 659 * the mechanism has changed, and the Flash region access 660 * registers are now implemented in GbE memory space. 661 */ 662 nvm->flash_base_addr = 0; 663 nvm_size = 664 (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1) 665 * NVM_SIZE_MULTIPLIER; 666 nvm->flash_bank_size = nvm_size / 2; 667 /* Adjust to word count */ 668 nvm->flash_bank_size /= sizeof(u16); 669 /* Set the base address for flash register access */ 670 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; 671 } else { 672 /* Can't read flash registers if register set isn't mapped. */ 673 if (!hw->flash_address) { 674 DEBUGOUT("ERROR: Flash registers not mapped\n"); 675 return -E1000_ERR_CONFIG; 676 } 677 678 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); 679 680 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 681 * Add 1 to sector_end_addr since this sector is included in 682 * the overall size. 683 */ 684 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 685 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 686 687 /* flash_base_addr is byte-aligned */ 688 nvm->flash_base_addr = sector_base_addr 689 << FLASH_SECTOR_ADDR_SHIFT; 690 691 /* find total size of the NVM, then cut in half since the total 692 * size represents two separate NVM banks. 693 */ 694 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 695 << FLASH_SECTOR_ADDR_SHIFT); 696 nvm->flash_bank_size /= 2; 697 /* Adjust to word count */ 698 nvm->flash_bank_size /= sizeof(u16); 699 } 700 701 nvm->word_size = E1000_SHADOW_RAM_WORDS; 702 703 /* Clear shadow ram */ 704 for (i = 0; i < nvm->word_size; i++) { 705 dev_spec->shadow_ram[i].modified = FALSE; 706 dev_spec->shadow_ram[i].value = 0xFFFF; 707 } 708 709 E1000_MUTEX_INIT(&dev_spec->nvm_mutex); 710 E1000_MUTEX_INIT(&dev_spec->swflag_mutex); 711 712 /* Function Pointers */ 713 nvm->ops.acquire = e1000_acquire_nvm_ich8lan; 714 nvm->ops.release = e1000_release_nvm_ich8lan; 715 if (hw->mac.type >= e1000_pch_spt) { 716 nvm->ops.read = e1000_read_nvm_spt; 717 nvm->ops.update = e1000_update_nvm_checksum_spt; 718 } else { 719 nvm->ops.read = e1000_read_nvm_ich8lan; 720 nvm->ops.update = e1000_update_nvm_checksum_ich8lan; 721 } 722 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan; 723 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan; 724 nvm->ops.write = e1000_write_nvm_ich8lan; 725 726 return E1000_SUCCESS; 727 } 728 729 /** 730 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 731 * @hw: pointer to the HW structure 732 * 733 * Initialize family-specific MAC parameters and function 734 * pointers. 735 **/ 736 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 737 { 738 struct e1000_mac_info *mac = &hw->mac; 739 740 DEBUGFUNC("e1000_init_mac_params_ich8lan"); 741 742 /* Set media type function pointer */ 743 hw->phy.media_type = e1000_media_type_copper; 744 745 /* Set mta register count */ 746 mac->mta_reg_count = 32; 747 /* Set rar entry count */ 748 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 749 if (mac->type == e1000_ich8lan) 750 mac->rar_entry_count--; 751 /* Set if part includes ASF firmware */ 752 mac->asf_firmware_present = TRUE; 753 /* FWSM register */ 754 mac->has_fwsm = TRUE; 755 /* ARC subsystem not supported */ 756 mac->arc_subsystem_valid = FALSE; 757 /* Adaptive IFS supported */ 758 mac->adaptive_ifs = TRUE; 759 760 /* Function pointers */ 761 762 /* bus type/speed/width */ 763 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan; 764 /* function id */ 765 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 766 /* reset */ 767 mac->ops.reset_hw = e1000_reset_hw_ich8lan; 768 /* hw initialization */ 769 mac->ops.init_hw = e1000_init_hw_ich8lan; 770 /* link setup */ 771 mac->ops.setup_link = e1000_setup_link_ich8lan; 772 /* physical interface setup */ 773 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan; 774 /* check for link */ 775 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan; 776 /* link info */ 777 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan; 778 /* multicast address update */ 779 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 780 /* clear hardware counters */ 781 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; 782 783 /* LED and other operations */ 784 switch (mac->type) { 785 case e1000_ich8lan: 786 case e1000_ich9lan: 787 case e1000_ich10lan: 788 /* check management mode */ 789 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 790 /* ID LED init */ 791 mac->ops.id_led_init = e1000_id_led_init_generic; 792 /* blink LED */ 793 mac->ops.blink_led = e1000_blink_led_generic; 794 /* setup LED */ 795 mac->ops.setup_led = e1000_setup_led_generic; 796 /* cleanup LED */ 797 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 798 /* turn on/off LED */ 799 mac->ops.led_on = e1000_led_on_ich8lan; 800 mac->ops.led_off = e1000_led_off_ich8lan; 801 break; 802 case e1000_pch2lan: 803 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 804 mac->ops.rar_set = e1000_rar_set_pch2lan; 805 /* fall-through */ 806 case e1000_pch_lpt: 807 case e1000_pch_spt: 808 case e1000_pch_cnp: 809 case e1000_pch_tgp: 810 case e1000_pch_adp: 811 case e1000_pch_mtp: 812 case e1000_pch_lnp: 813 case e1000_pch_rpl: 814 /* multicast address update for pch2 */ 815 mac->ops.update_mc_addr_list = 816 e1000_update_mc_addr_list_pch2lan; 817 /* fall-through */ 818 case e1000_pchlan: 819 /* check management mode */ 820 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 821 /* ID LED init */ 822 mac->ops.id_led_init = e1000_id_led_init_pchlan; 823 /* setup LED */ 824 mac->ops.setup_led = e1000_setup_led_pchlan; 825 /* cleanup LED */ 826 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 827 /* turn on/off LED */ 828 mac->ops.led_on = e1000_led_on_pchlan; 829 mac->ops.led_off = e1000_led_off_pchlan; 830 break; 831 default: 832 break; 833 } 834 835 if (mac->type >= e1000_pch_lpt) { 836 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 837 mac->ops.rar_set = e1000_rar_set_pch_lpt; 838 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt; 839 mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt; 840 } 841 842 /* Enable PCS Lock-loss workaround for ICH8 */ 843 if (mac->type == e1000_ich8lan) 844 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); 845 846 return E1000_SUCCESS; 847 } 848 849 /** 850 * __e1000_access_emi_reg_locked - Read/write EMI register 851 * @hw: pointer to the HW structure 852 * @addr: EMI address to program 853 * @data: pointer to value to read/write from/to the EMI address 854 * @read: boolean flag to indicate read or write 855 * 856 * This helper function assumes the SW/FW/HW Semaphore is already acquired. 857 **/ 858 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 859 u16 *data, bool read) 860 { 861 s32 ret_val; 862 863 DEBUGFUNC("__e1000_access_emi_reg_locked"); 864 865 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address); 866 if (ret_val) 867 return ret_val; 868 869 if (read) 870 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA, 871 data); 872 else 873 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 874 *data); 875 876 return ret_val; 877 } 878 879 /** 880 * e1000_read_emi_reg_locked - Read Extended Management Interface register 881 * @hw: pointer to the HW structure 882 * @addr: EMI address to program 883 * @data: value to be read from the EMI address 884 * 885 * Assumes the SW/FW/HW Semaphore is already acquired. 886 **/ 887 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 888 { 889 DEBUGFUNC("e1000_read_emi_reg_locked"); 890 891 return __e1000_access_emi_reg_locked(hw, addr, data, TRUE); 892 } 893 894 /** 895 * e1000_write_emi_reg_locked - Write Extended Management Interface register 896 * @hw: pointer to the HW structure 897 * @addr: EMI address to program 898 * @data: value to be written to the EMI address 899 * 900 * Assumes the SW/FW/HW Semaphore is already acquired. 901 **/ 902 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 903 { 904 DEBUGFUNC("e1000_read_emi_reg_locked"); 905 906 return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE); 907 } 908 909 /** 910 * e1000_set_eee_pchlan - Enable/disable EEE support 911 * @hw: pointer to the HW structure 912 * 913 * Enable/disable EEE based on setting in dev_spec structure, the duplex of 914 * the link and the EEE capabilities of the link partner. The LPI Control 915 * register bits will remain set only if/when link is up. 916 * 917 * EEE LPI must not be asserted earlier than one second after link is up. 918 * On 82579, EEE LPI should not be enabled until such time otherwise there 919 * can be link issues with some switches. Other devices can have EEE LPI 920 * enabled immediately upon link up since they have a timer in hardware which 921 * prevents LPI from being asserted too early. 922 **/ 923 s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 924 { 925 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 926 s32 ret_val; 927 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; 928 929 DEBUGFUNC("e1000_set_eee_pchlan"); 930 931 switch (hw->phy.type) { 932 case e1000_phy_82579: 933 lpa = I82579_EEE_LP_ABILITY; 934 pcs_status = I82579_EEE_PCS_STATUS; 935 adv_addr = I82579_EEE_ADVERTISEMENT; 936 break; 937 case e1000_phy_i217: 938 lpa = I217_EEE_LP_ABILITY; 939 pcs_status = I217_EEE_PCS_STATUS; 940 adv_addr = I217_EEE_ADVERTISEMENT; 941 break; 942 default: 943 return E1000_SUCCESS; 944 } 945 946 ret_val = hw->phy.ops.acquire(hw); 947 if (ret_val) 948 return ret_val; 949 950 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 951 if (ret_val) 952 goto release; 953 954 /* Clear bits that enable EEE in various speeds */ 955 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 956 957 /* Enable EEE if not disabled by user */ 958 if (!dev_spec->eee_disable) { 959 /* Save off link partner's EEE ability */ 960 ret_val = e1000_read_emi_reg_locked(hw, lpa, 961 &dev_spec->eee_lp_ability); 962 if (ret_val) 963 goto release; 964 965 /* Read EEE advertisement */ 966 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); 967 if (ret_val) 968 goto release; 969 970 /* Enable EEE only for speeds in which the link partner is 971 * EEE capable and for which we advertise EEE. 972 */ 973 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 974 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 975 976 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 977 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data); 978 if (data & NWAY_LPAR_100TX_FD_CAPS) 979 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 980 else 981 /* EEE is not supported in 100Half, so ignore 982 * partner's EEE in 100 ability if full-duplex 983 * is not advertised. 984 */ 985 dev_spec->eee_lp_ability &= 986 ~I82579_EEE_100_SUPPORTED; 987 } 988 } 989 990 if (hw->phy.type == e1000_phy_82579) { 991 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 992 &data); 993 if (ret_val) 994 goto release; 995 996 data &= ~I82579_LPI_100_PLL_SHUT; 997 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 998 data); 999 } 1000 1001 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 1002 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 1003 if (ret_val) 1004 goto release; 1005 1006 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 1007 release: 1008 hw->phy.ops.release(hw); 1009 1010 return ret_val; 1011 } 1012 1013 /** 1014 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 1015 * @hw: pointer to the HW structure 1016 * @link: link up bool flag 1017 * 1018 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 1019 * preventing further DMA write requests. Workaround the issue by disabling 1020 * the de-assertion of the clock request when in 1Gpbs mode. 1021 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 1022 * speeds in order to avoid Tx hangs. 1023 **/ 1024 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 1025 { 1026 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); 1027 u32 status = E1000_READ_REG(hw, E1000_STATUS); 1028 s32 ret_val = E1000_SUCCESS; 1029 u16 reg; 1030 1031 if (link && (status & E1000_STATUS_SPEED_1000)) { 1032 ret_val = hw->phy.ops.acquire(hw); 1033 if (ret_val) 1034 return ret_val; 1035 1036 ret_val = 1037 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 1038 ®); 1039 if (ret_val) 1040 goto release; 1041 1042 ret_val = 1043 e1000_write_kmrn_reg_locked(hw, 1044 E1000_KMRNCTRLSTA_K1_CONFIG, 1045 reg & 1046 ~E1000_KMRNCTRLSTA_K1_ENABLE); 1047 if (ret_val) 1048 goto release; 1049 1050 usec_delay(10); 1051 1052 E1000_WRITE_REG(hw, E1000_FEXTNVM6, 1053 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 1054 1055 ret_val = 1056 e1000_write_kmrn_reg_locked(hw, 1057 E1000_KMRNCTRLSTA_K1_CONFIG, 1058 reg); 1059 release: 1060 hw->phy.ops.release(hw); 1061 } else { 1062 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 1063 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 1064 1065 if ((hw->phy.revision > 5) || !link || 1066 ((status & E1000_STATUS_SPEED_100) && 1067 (status & E1000_STATUS_FD))) 1068 goto update_fextnvm6; 1069 1070 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®); 1071 if (ret_val) 1072 return ret_val; 1073 1074 /* Clear link status transmit timeout */ 1075 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 1076 1077 if (status & E1000_STATUS_SPEED_100) { 1078 /* Set inband Tx timeout to 5x10us for 100Half */ 1079 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 1080 1081 /* Do not extend the K1 entry latency for 100Half */ 1082 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 1083 } else { 1084 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 1085 reg |= 50 << 1086 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 1087 1088 /* Extend the K1 entry latency for 10 Mbps */ 1089 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 1090 } 1091 1092 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg); 1093 if (ret_val) 1094 return ret_val; 1095 1096 update_fextnvm6: 1097 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6); 1098 } 1099 1100 return ret_val; 1101 } 1102 1103 static u64 e1000_ltr2ns(u16 ltr) 1104 { 1105 u32 value, scale; 1106 1107 /* Determine the latency in nsec based on the LTR value & scale */ 1108 value = ltr & E1000_LTRV_VALUE_MASK; 1109 scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT; 1110 1111 return value * (1 << (scale * E1000_LTRV_SCALE_FACTOR)); 1112 } 1113 1114 /** 1115 * e1000_platform_pm_pch_lpt - Set platform power management values 1116 * @hw: pointer to the HW structure 1117 * @link: bool indicating link status 1118 * 1119 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 1120 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 1121 * when link is up (which must not exceed the maximum latency supported 1122 * by the platform), otherwise specify there is no LTR requirement. 1123 * Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop 1124 * latencies in the LTR Extended Capability Structure in the PCIe Extended 1125 * Capability register set, on this device LTR is set by writing the 1126 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 1127 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 1128 * message to the PMC. 1129 * 1130 * Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF) 1131 * high-water mark. 1132 **/ 1133 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 1134 { 1135 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 1136 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 1137 u16 lat_enc = 0; /* latency encoded */ 1138 s32 obff_hwm = 0; 1139 1140 DEBUGFUNC("e1000_platform_pm_pch_lpt"); 1141 1142 if (link) { 1143 u16 speed, duplex, scale = 0; 1144 u16 max_snoop, max_nosnoop; 1145 u16 max_ltr_enc; /* max LTR latency encoded */ 1146 s64 lat_ns; 1147 s64 value; 1148 u32 rxa; 1149 1150 if (!hw->mac.max_frame_size) { 1151 DEBUGOUT("max_frame_size not set.\n"); 1152 return -E1000_ERR_CONFIG; 1153 } 1154 1155 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 1156 if (!speed) { 1157 DEBUGOUT("Speed not set.\n"); 1158 return -E1000_ERR_CONFIG; 1159 } 1160 1161 /* Rx Packet Buffer Allocation size (KB) */ 1162 rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK; 1163 1164 /* Determine the maximum latency tolerated by the device. 1165 * 1166 * Per the PCIe spec, the tolerated latencies are encoded as 1167 * a 3-bit encoded scale (only 0-5 are valid) multiplied by 1168 * a 10-bit value (0-1023) to provide a range from 1 ns to 1169 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 1170 * 1=2^5ns, 2=2^10ns,...5=2^25ns. 1171 */ 1172 lat_ns = ((s64)rxa * 1024 - 1173 (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000; 1174 if (lat_ns < 0) 1175 lat_ns = 0; 1176 else 1177 lat_ns /= speed; 1178 value = lat_ns; 1179 1180 while (value > E1000_LTRV_VALUE_MASK) { 1181 scale++; 1182 value = E1000_DIVIDE_ROUND_UP(value, (1 << 5)); 1183 } 1184 if (scale > E1000_LTRV_SCALE_MAX) { 1185 DEBUGOUT1("Invalid LTR latency scale %d\n", scale); 1186 return -E1000_ERR_CONFIG; 1187 } 1188 lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value); 1189 1190 /* Determine the maximum latency tolerated by the platform */ 1191 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop); 1192 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 1193 max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop); 1194 1195 if (lat_enc > max_ltr_enc) { 1196 lat_enc = max_ltr_enc; 1197 lat_ns = e1000_ltr2ns(max_ltr_enc); 1198 } 1199 1200 if (lat_ns) { 1201 lat_ns *= speed * 1000; 1202 lat_ns /= 8; 1203 lat_ns /= 1000000000; 1204 obff_hwm = (s32)(rxa - lat_ns); 1205 } 1206 if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) { 1207 DEBUGOUT1("Invalid high water mark %d\n", obff_hwm); 1208 return -E1000_ERR_CONFIG; 1209 } 1210 } 1211 1212 /* Set Snoop and No-Snoop latencies the same */ 1213 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 1214 E1000_WRITE_REG(hw, E1000_LTRV, reg); 1215 1216 /* Set OBFF high water mark */ 1217 reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK; 1218 reg |= obff_hwm; 1219 E1000_WRITE_REG(hw, E1000_SVT, reg); 1220 1221 /* Enable OBFF */ 1222 reg = E1000_READ_REG(hw, E1000_SVCR); 1223 reg |= E1000_SVCR_OFF_EN; 1224 /* Always unblock interrupts to the CPU even when the system is 1225 * in OBFF mode. This ensures that small round-robin traffic 1226 * (like ping) does not get dropped or experience long latency. 1227 */ 1228 reg |= E1000_SVCR_OFF_MASKINT; 1229 E1000_WRITE_REG(hw, E1000_SVCR, reg); 1230 1231 return E1000_SUCCESS; 1232 } 1233 1234 /** 1235 * e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer 1236 * @hw: pointer to the HW structure 1237 * @itr: interrupt throttling rate 1238 * 1239 * Configure OBFF with the updated interrupt rate. 1240 **/ 1241 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr) 1242 { 1243 u32 svcr; 1244 s32 timer; 1245 1246 DEBUGFUNC("e1000_set_obff_timer_pch_lpt"); 1247 1248 /* Convert ITR value into microseconds for OBFF timer */ 1249 timer = itr & E1000_ITR_MASK; 1250 timer = (timer * E1000_ITR_MULT) / 1000; 1251 1252 if ((timer < 0) || (timer > E1000_ITR_MASK)) { 1253 DEBUGOUT1("Invalid OBFF timer %d\n", timer); 1254 return -E1000_ERR_CONFIG; 1255 } 1256 1257 svcr = E1000_READ_REG(hw, E1000_SVCR); 1258 svcr &= ~E1000_SVCR_OFF_TIMER_MASK; 1259 svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT; 1260 E1000_WRITE_REG(hw, E1000_SVCR, svcr); 1261 1262 return E1000_SUCCESS; 1263 } 1264 1265 /** 1266 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP 1267 * @hw: pointer to the HW structure 1268 * @to_sx: boolean indicating a system power state transition to Sx 1269 * 1270 * When link is down, configure ULP mode to significantly reduce the power 1271 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the 1272 * ME firmware to start the ULP configuration. If not on an ME enabled 1273 * system, configure the ULP mode by software. 1274 */ 1275 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) 1276 { 1277 u32 mac_reg; 1278 s32 ret_val = E1000_SUCCESS; 1279 u16 phy_reg; 1280 u16 oem_reg = 0; 1281 1282 if ((hw->mac.type < e1000_pch_lpt) || 1283 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || 1284 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || 1285 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || 1286 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) || 1287 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) 1288 return 0; 1289 1290 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) { 1291 /* Request ME configure ULP mode in the PHY */ 1292 mac_reg = E1000_READ_REG(hw, E1000_H2ME); 1293 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; 1294 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); 1295 1296 goto out; 1297 } 1298 1299 if (!to_sx) { 1300 int i = 0; 1301 1302 /* Poll up to 5 seconds for Cable Disconnected indication */ 1303 while (!(E1000_READ_REG(hw, E1000_FEXT) & 1304 E1000_FEXT_PHY_CABLE_DISCONNECTED)) { 1305 /* Bail if link is re-acquired */ 1306 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) 1307 return -E1000_ERR_PHY; 1308 1309 if (i++ == 100) 1310 break; 1311 1312 msec_delay(50); 1313 } 1314 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n", 1315 (E1000_READ_REG(hw, E1000_FEXT) & 1316 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", 1317 i * 50); 1318 } 1319 1320 ret_val = hw->phy.ops.acquire(hw); 1321 if (ret_val) 1322 goto out; 1323 1324 /* Force SMBus mode in PHY */ 1325 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1326 if (ret_val) 1327 goto release; 1328 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS; 1329 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1330 1331 /* Force SMBus mode in MAC */ 1332 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1333 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1334 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 1335 1336 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable 1337 * LPLU and disable Gig speed when entering ULP 1338 */ 1339 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { 1340 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, 1341 &oem_reg); 1342 if (ret_val) 1343 goto release; 1344 1345 phy_reg = oem_reg; 1346 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS; 1347 1348 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1349 phy_reg); 1350 1351 if (ret_val) 1352 goto release; 1353 } 1354 1355 /* Set Inband ULP Exit, Reset to SMBus mode and 1356 * Disable SMBus Release on PERST# in PHY 1357 */ 1358 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1359 if (ret_val) 1360 goto release; 1361 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | 1362 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1363 if (to_sx) { 1364 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC) 1365 phy_reg |= I218_ULP_CONFIG1_WOL_HOST; 1366 else 1367 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1368 1369 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; 1370 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT; 1371 } else { 1372 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; 1373 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP; 1374 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1375 } 1376 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1377 1378 /* Set Disable SMBus Release on PERST# in MAC */ 1379 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7); 1380 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; 1381 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg); 1382 1383 /* Commit ULP changes in PHY by starting auto ULP configuration */ 1384 phy_reg |= I218_ULP_CONFIG1_START; 1385 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1386 1387 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && 1388 to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 1389 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1390 oem_reg); 1391 if (ret_val) 1392 goto release; 1393 } 1394 1395 release: 1396 hw->phy.ops.release(hw); 1397 out: 1398 if (ret_val) 1399 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val); 1400 else 1401 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; 1402 1403 return ret_val; 1404 } 1405 1406 /** 1407 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1408 * @hw: pointer to the HW structure 1409 * @force: boolean indicating whether or not to force disabling ULP 1410 * 1411 * Un-configure ULP mode when link is up, the system is transitioned from 1412 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1413 * system, poll for an indication from ME that ULP has been un-configured. 1414 * If not on an ME enabled system, un-configure the ULP mode by software. 1415 * 1416 * During nominal operation, this function is called when link is acquired 1417 * to disable ULP mode (force=FALSE); otherwise, for example when unloading 1418 * the driver or during Sx->S0 transitions, this is called with force=TRUE 1419 * to forcibly disable ULP. 1420 */ 1421 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) 1422 { 1423 s32 ret_val = E1000_SUCCESS; 1424 u32 mac_reg; 1425 u16 phy_reg; 1426 int i = 0; 1427 1428 if ((hw->mac.type < e1000_pch_lpt) || 1429 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || 1430 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || 1431 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || 1432 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) || 1433 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) 1434 return 0; 1435 1436 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) { 1437 if (force) { 1438 /* Request ME un-configure ULP mode in the PHY */ 1439 mac_reg = E1000_READ_REG(hw, E1000_H2ME); 1440 mac_reg &= ~E1000_H2ME_ULP; 1441 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1442 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); 1443 } 1444 1445 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */ 1446 while (E1000_READ_REG(hw, E1000_FWSM) & 1447 E1000_FWSM_ULP_CFG_DONE) { 1448 if (i++ == 30) { 1449 ret_val = -E1000_ERR_PHY; 1450 goto out; 1451 } 1452 1453 msec_delay(10); 1454 } 1455 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10); 1456 1457 if (force) { 1458 mac_reg = E1000_READ_REG(hw, E1000_H2ME); 1459 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1460 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); 1461 } else { 1462 /* Clear H2ME.ULP after ME ULP configuration */ 1463 mac_reg = E1000_READ_REG(hw, E1000_H2ME); 1464 mac_reg &= ~E1000_H2ME_ULP; 1465 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); 1466 } 1467 1468 goto out; 1469 } 1470 1471 ret_val = hw->phy.ops.acquire(hw); 1472 if (ret_val) 1473 goto out; 1474 1475 if (force) 1476 /* Toggle LANPHYPC Value bit */ 1477 e1000_toggle_lanphypc_pch_lpt(hw); 1478 1479 /* Unforce SMBus mode in PHY */ 1480 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1481 if (ret_val) { 1482 /* The MAC might be in PCIe mode, so temporarily force to 1483 * SMBus mode in order to access the PHY. 1484 */ 1485 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1486 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1487 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 1488 1489 msec_delay(50); 1490 1491 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, 1492 &phy_reg); 1493 if (ret_val) 1494 goto release; 1495 } 1496 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1497 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1498 1499 /* Unforce SMBus mode in MAC */ 1500 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1501 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1502 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 1503 1504 /* When ULP mode was previously entered, K1 was disabled by the 1505 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1506 */ 1507 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); 1508 if (ret_val) 1509 goto release; 1510 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1511 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); 1512 1513 /* Clear ULP enabled configuration */ 1514 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1515 if (ret_val) 1516 goto release; 1517 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1518 I218_ULP_CONFIG1_STICKY_ULP | 1519 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1520 I218_ULP_CONFIG1_WOL_HOST | 1521 I218_ULP_CONFIG1_INBAND_EXIT | 1522 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1523 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1524 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1525 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1526 1527 /* Commit ULP changes by starting auto ULP configuration */ 1528 phy_reg |= I218_ULP_CONFIG1_START; 1529 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1530 1531 /* Clear Disable SMBus Release on PERST# in MAC */ 1532 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7); 1533 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1534 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg); 1535 1536 release: 1537 hw->phy.ops.release(hw); 1538 if (force) { 1539 hw->phy.ops.reset(hw); 1540 msec_delay(50); 1541 } 1542 out: 1543 if (ret_val) 1544 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val); 1545 else 1546 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; 1547 1548 return ret_val; 1549 } 1550 1551 /** 1552 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 1553 * @hw: pointer to the HW structure 1554 * 1555 * Checks to see of the link status of the hardware has changed. If a 1556 * change in link status has been detected, then we read the PHY registers 1557 * to get the current speed/duplex if link exists. 1558 **/ 1559 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1560 { 1561 struct e1000_mac_info *mac = &hw->mac; 1562 s32 ret_val, tipg_reg = 0; 1563 u16 emi_addr, emi_val = 0; 1564 bool link; 1565 u16 phy_reg; 1566 1567 DEBUGFUNC("e1000_check_for_copper_link_ich8lan"); 1568 1569 /* We only want to go out to the PHY registers to see if Auto-Neg 1570 * has completed and/or if our link status has changed. The 1571 * get_link_status flag is set upon receiving a Link Status 1572 * Change or Rx Sequence Error interrupt. 1573 */ 1574 if (!mac->get_link_status) 1575 return E1000_SUCCESS; 1576 1577 /* First we want to see if the MII Status Register reports 1578 * link. If so, then we want to get the current speed/duplex 1579 * of the PHY. 1580 */ 1581 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1582 if (ret_val) 1583 return ret_val; 1584 1585 if (hw->mac.type == e1000_pchlan) { 1586 ret_val = e1000_k1_gig_workaround_hv(hw, link); 1587 if (ret_val) 1588 return ret_val; 1589 } 1590 1591 /* When connected at 10Mbps half-duplex, some parts are excessively 1592 * aggressive resulting in many collisions. To avoid this, increase 1593 * the IPG and reduce Rx latency in the PHY. 1594 */ 1595 if ((hw->mac.type >= e1000_pch2lan) && link) { 1596 u16 speed, duplex; 1597 1598 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex); 1599 tipg_reg = E1000_READ_REG(hw, E1000_TIPG); 1600 tipg_reg &= ~E1000_TIPG_IPGT_MASK; 1601 1602 if (duplex == HALF_DUPLEX && speed == SPEED_10) { 1603 tipg_reg |= 0xFF; 1604 /* Reduce Rx latency in analog PHY */ 1605 emi_val = 0; 1606 } else if (hw->mac.type >= e1000_pch_spt && 1607 duplex == FULL_DUPLEX && speed != SPEED_1000) { 1608 tipg_reg |= 0xC; 1609 emi_val = 1; 1610 } else { 1611 /* Roll back the default values */ 1612 tipg_reg |= 0x08; 1613 emi_val = 1; 1614 } 1615 1616 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg); 1617 1618 ret_val = hw->phy.ops.acquire(hw); 1619 if (ret_val) 1620 return ret_val; 1621 1622 if (hw->mac.type == e1000_pch2lan) 1623 emi_addr = I82579_RX_CONFIG; 1624 else 1625 emi_addr = I217_RX_CONFIG; 1626 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); 1627 1628 if (hw->mac.type >= e1000_pch_lpt) { 1629 u16 phy_reg; 1630 1631 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG, 1632 &phy_reg); 1633 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK; 1634 if (speed == SPEED_100 || speed == SPEED_10) 1635 phy_reg |= 0x3E8; 1636 else 1637 phy_reg |= 0xFA; 1638 hw->phy.ops.write_reg_locked(hw, 1639 I217_PLL_CLOCK_GATE_REG, 1640 phy_reg); 1641 1642 if (speed == SPEED_1000) { 1643 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, 1644 &phy_reg); 1645 1646 phy_reg |= HV_PM_CTRL_K1_CLK_REQ; 1647 1648 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, 1649 phy_reg); 1650 } 1651 } 1652 hw->phy.ops.release(hw); 1653 1654 if (ret_val) 1655 return ret_val; 1656 1657 if (hw->mac.type >= e1000_pch_spt) { 1658 u16 data; 1659 u16 ptr_gap; 1660 1661 if (speed == SPEED_1000) { 1662 ret_val = hw->phy.ops.acquire(hw); 1663 if (ret_val) 1664 return ret_val; 1665 1666 ret_val = hw->phy.ops.read_reg_locked(hw, 1667 PHY_REG(776, 20), 1668 &data); 1669 if (ret_val) { 1670 hw->phy.ops.release(hw); 1671 return ret_val; 1672 } 1673 1674 ptr_gap = (data & (0x3FF << 2)) >> 2; 1675 if (ptr_gap < 0x18) { 1676 data &= ~(0x3FF << 2); 1677 data |= (0x18 << 2); 1678 ret_val = 1679 hw->phy.ops.write_reg_locked(hw, 1680 PHY_REG(776, 20), data); 1681 } 1682 hw->phy.ops.release(hw); 1683 if (ret_val) 1684 return ret_val; 1685 } else { 1686 ret_val = hw->phy.ops.acquire(hw); 1687 if (ret_val) 1688 return ret_val; 1689 1690 ret_val = hw->phy.ops.write_reg_locked(hw, 1691 PHY_REG(776, 20), 1692 0xC023); 1693 hw->phy.ops.release(hw); 1694 if (ret_val) 1695 return ret_val; 1696 1697 } 1698 } 1699 } 1700 1701 /* I217 Packet Loss issue: 1702 * ensure that FEXTNVM4 Beacon Duration is set correctly 1703 * on power up. 1704 * Set the Beacon Duration for I217 to 8 usec 1705 */ 1706 if (hw->mac.type >= e1000_pch_lpt) { 1707 u32 mac_reg; 1708 1709 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4); 1710 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1711 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1712 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg); 1713 } 1714 1715 /* Work-around I218 hang issue */ 1716 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1717 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 1718 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) || 1719 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) { 1720 ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1721 if (ret_val) 1722 return ret_val; 1723 } 1724 if (hw->mac.type >= e1000_pch_lpt) { 1725 /* Set platform power management values for 1726 * Latency Tolerance Reporting (LTR) 1727 * Optimized Buffer Flush/Fill (OBFF) 1728 */ 1729 ret_val = e1000_platform_pm_pch_lpt(hw, link); 1730 if (ret_val) 1731 return ret_val; 1732 } 1733 1734 /* Clear link partner's EEE ability */ 1735 hw->dev_spec.ich8lan.eee_lp_ability = 0; 1736 1737 /* FEXTNVM6 K1-off workaround - for SPT only */ 1738 if (hw->mac.type == e1000_pch_spt) { 1739 u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG); 1740 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); 1741 1742 if ((pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) && 1743 (hw->dev_spec.ich8lan.disable_k1_off == FALSE)) 1744 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE; 1745 else 1746 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; 1747 1748 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6); 1749 } 1750 1751 if (!link) 1752 return E1000_SUCCESS; /* No link detected */ 1753 1754 mac->get_link_status = FALSE; 1755 1756 switch (hw->mac.type) { 1757 case e1000_pch2lan: 1758 ret_val = e1000_k1_workaround_lv(hw); 1759 if (ret_val) 1760 return ret_val; 1761 /* fall-thru */ 1762 case e1000_pchlan: 1763 if (hw->phy.type == e1000_phy_82578) { 1764 ret_val = e1000_link_stall_workaround_hv(hw); 1765 if (ret_val) 1766 return ret_val; 1767 } 1768 1769 /* Workaround for PCHx parts in half-duplex: 1770 * Set the number of preambles removed from the packet 1771 * when it is passed from the PHY to the MAC to prevent 1772 * the MAC from misinterpreting the packet type. 1773 */ 1774 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1775 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1776 1777 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) != 1778 E1000_STATUS_FD) 1779 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1780 1781 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1782 break; 1783 default: 1784 break; 1785 } 1786 1787 /* Check if there was DownShift, must be checked 1788 * immediately after link-up 1789 */ 1790 e1000_check_downshift_generic(hw); 1791 1792 /* Enable/Disable EEE after link up */ 1793 if (hw->phy.type > e1000_phy_82579) { 1794 ret_val = e1000_set_eee_pchlan(hw); 1795 if (ret_val) 1796 return ret_val; 1797 } 1798 1799 /* If we are forcing speed/duplex, then we simply return since 1800 * we have already determined whether we have link or not. 1801 */ 1802 if (!mac->autoneg) 1803 return -E1000_ERR_CONFIG; 1804 1805 /* Auto-Neg is enabled. Auto Speed Detection takes care 1806 * of MAC speed/duplex configuration. So we only need to 1807 * configure Collision Distance in the MAC. 1808 */ 1809 mac->ops.config_collision_dist(hw); 1810 1811 /* Configure Flow Control now that Auto-Neg has completed. 1812 * First, we need to restore the desired flow control 1813 * settings because we may have had to re-autoneg with a 1814 * different link partner. 1815 */ 1816 ret_val = e1000_config_fc_after_link_up_generic(hw); 1817 if (ret_val) 1818 DEBUGOUT("Error configuring flow control\n"); 1819 1820 return ret_val; 1821 } 1822 1823 /** 1824 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers 1825 * @hw: pointer to the HW structure 1826 * 1827 * Initialize family-specific function pointers for PHY, MAC, and NVM. 1828 **/ 1829 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) 1830 { 1831 DEBUGFUNC("e1000_init_function_pointers_ich8lan"); 1832 1833 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; 1834 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; 1835 switch (hw->mac.type) { 1836 case e1000_ich8lan: 1837 case e1000_ich9lan: 1838 case e1000_ich10lan: 1839 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; 1840 break; 1841 case e1000_pchlan: 1842 case e1000_pch2lan: 1843 case e1000_pch_lpt: 1844 case e1000_pch_spt: 1845 case e1000_pch_cnp: 1846 case e1000_pch_tgp: 1847 case e1000_pch_adp: 1848 case e1000_pch_mtp: 1849 case e1000_pch_lnp: 1850 case e1000_pch_rpl: 1851 hw->phy.ops.init_params = e1000_init_phy_params_pchlan; 1852 break; 1853 default: 1854 break; 1855 } 1856 } 1857 1858 /** 1859 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1860 * @hw: pointer to the HW structure 1861 * 1862 * Acquires the mutex for performing NVM operations. 1863 **/ 1864 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw) 1865 { 1866 DEBUGFUNC("e1000_acquire_nvm_ich8lan"); 1867 1868 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex); 1869 1870 return E1000_SUCCESS; 1871 } 1872 1873 /** 1874 * e1000_release_nvm_ich8lan - Release NVM mutex 1875 * @hw: pointer to the HW structure 1876 * 1877 * Releases the mutex used while performing NVM operations. 1878 **/ 1879 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw) 1880 { 1881 DEBUGFUNC("e1000_release_nvm_ich8lan"); 1882 1883 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex); 1884 1885 return; 1886 } 1887 1888 /** 1889 * e1000_acquire_swflag_ich8lan - Acquire software control flag 1890 * @hw: pointer to the HW structure 1891 * 1892 * Acquires the software control flag for performing PHY and select 1893 * MAC CSR accesses. 1894 **/ 1895 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1896 { 1897 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1898 s32 ret_val = E1000_SUCCESS; 1899 1900 DEBUGFUNC("e1000_acquire_swflag_ich8lan"); 1901 1902 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex); 1903 1904 while (timeout) { 1905 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1906 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1907 break; 1908 1909 msec_delay_irq(1); 1910 timeout--; 1911 } 1912 1913 if (!timeout) { 1914 DEBUGOUT("SW has already locked the resource.\n"); 1915 ret_val = -E1000_ERR_CONFIG; 1916 goto out; 1917 } 1918 1919 timeout = SW_FLAG_TIMEOUT; 1920 1921 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1922 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 1923 1924 while (timeout) { 1925 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1926 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1927 break; 1928 1929 msec_delay_irq(1); 1930 timeout--; 1931 } 1932 1933 if (!timeout) { 1934 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1935 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl); 1936 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1937 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 1938 ret_val = -E1000_ERR_CONFIG; 1939 goto out; 1940 } 1941 1942 out: 1943 if (ret_val) 1944 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 1945 1946 return ret_val; 1947 } 1948 1949 /** 1950 * e1000_release_swflag_ich8lan - Release software control flag 1951 * @hw: pointer to the HW structure 1952 * 1953 * Releases the software control flag for performing PHY and select 1954 * MAC CSR accesses. 1955 **/ 1956 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1957 { 1958 u32 extcnf_ctrl; 1959 1960 DEBUGFUNC("e1000_release_swflag_ich8lan"); 1961 1962 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1963 1964 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1965 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1966 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 1967 } else { 1968 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n"); 1969 } 1970 1971 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 1972 1973 return; 1974 } 1975 1976 /** 1977 * e1000_check_mng_mode_ich8lan - Checks management mode 1978 * @hw: pointer to the HW structure 1979 * 1980 * This checks if the adapter has any manageability enabled. 1981 * This is a function pointer entry point only called by read/write 1982 * routines for the PHY and NVM parts. 1983 **/ 1984 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1985 { 1986 u32 fwsm; 1987 1988 DEBUGFUNC("e1000_check_mng_mode_ich8lan"); 1989 1990 fwsm = E1000_READ_REG(hw, E1000_FWSM); 1991 1992 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1993 ((fwsm & E1000_FWSM_MODE_MASK) == 1994 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1995 } 1996 1997 /** 1998 * e1000_check_mng_mode_pchlan - Checks management mode 1999 * @hw: pointer to the HW structure 2000 * 2001 * This checks if the adapter has iAMT enabled. 2002 * This is a function pointer entry point only called by read/write 2003 * routines for the PHY and NVM parts. 2004 **/ 2005 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 2006 { 2007 u32 fwsm; 2008 2009 DEBUGFUNC("e1000_check_mng_mode_pchlan"); 2010 2011 fwsm = E1000_READ_REG(hw, E1000_FWSM); 2012 2013 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 2014 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 2015 } 2016 2017 /** 2018 * e1000_rar_set_pch2lan - Set receive address register 2019 * @hw: pointer to the HW structure 2020 * @addr: pointer to the receive address 2021 * @index: receive address array register 2022 * 2023 * Sets the receive address array register at index to the address passed 2024 * in by addr. For 82579, RAR[0] is the base address register that is to 2025 * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 2026 * Use SHRA[0-3] in place of those reserved for ME. 2027 **/ 2028 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 2029 { 2030 u32 rar_low, rar_high; 2031 2032 DEBUGFUNC("e1000_rar_set_pch2lan"); 2033 2034 /* HW expects these in little endian so we reverse the byte order 2035 * from network order (big endian) to little endian 2036 */ 2037 rar_low = ((u32) addr[0] | 2038 ((u32) addr[1] << 8) | 2039 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 2040 2041 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 2042 2043 /* If MAC address zero, no need to set the AV bit */ 2044 if (rar_low || rar_high) 2045 rar_high |= E1000_RAH_AV; 2046 2047 if (index == 0) { 2048 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 2049 E1000_WRITE_FLUSH(hw); 2050 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 2051 E1000_WRITE_FLUSH(hw); 2052 return E1000_SUCCESS; 2053 } 2054 2055 /* RAR[1-6] are owned by manageability. Skip those and program the 2056 * next address into the SHRA register array. 2057 */ 2058 if (index < (u32) (hw->mac.rar_entry_count)) { 2059 s32 ret_val; 2060 2061 ret_val = e1000_acquire_swflag_ich8lan(hw); 2062 if (ret_val) 2063 goto out; 2064 2065 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low); 2066 E1000_WRITE_FLUSH(hw); 2067 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high); 2068 E1000_WRITE_FLUSH(hw); 2069 2070 e1000_release_swflag_ich8lan(hw); 2071 2072 /* verify the register updates */ 2073 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) && 2074 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high)) 2075 return E1000_SUCCESS; 2076 2077 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 2078 (index - 1), E1000_READ_REG(hw, E1000_FWSM)); 2079 } 2080 2081 out: 2082 DEBUGOUT1("Failed to write receive address at index %d\n", index); 2083 return -E1000_ERR_CONFIG; 2084 } 2085 2086 /** 2087 * e1000_rar_set_pch_lpt - Set receive address registers 2088 * @hw: pointer to the HW structure 2089 * @addr: pointer to the receive address 2090 * @index: receive address array register 2091 * 2092 * Sets the receive address register array at index to the address passed 2093 * in by addr. For LPT, RAR[0] is the base address register that is to 2094 * contain the MAC address. SHRA[0-10] are the shared receive address 2095 * registers that are shared between the Host and manageability engine (ME). 2096 **/ 2097 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 2098 { 2099 u32 rar_low, rar_high; 2100 u32 wlock_mac; 2101 2102 DEBUGFUNC("e1000_rar_set_pch_lpt"); 2103 2104 /* HW expects these in little endian so we reverse the byte order 2105 * from network order (big endian) to little endian 2106 */ 2107 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 2108 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 2109 2110 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 2111 2112 /* If MAC address zero, no need to set the AV bit */ 2113 if (rar_low || rar_high) 2114 rar_high |= E1000_RAH_AV; 2115 2116 if (index == 0) { 2117 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 2118 E1000_WRITE_FLUSH(hw); 2119 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 2120 E1000_WRITE_FLUSH(hw); 2121 return E1000_SUCCESS; 2122 } 2123 2124 /* The manageability engine (ME) can lock certain SHRAR registers that 2125 * it is using - those registers are unavailable for use. 2126 */ 2127 if (index < hw->mac.rar_entry_count) { 2128 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) & 2129 E1000_FWSM_WLOCK_MAC_MASK; 2130 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 2131 2132 /* Check if all SHRAR registers are locked */ 2133 if (wlock_mac == 1) 2134 goto out; 2135 2136 if ((wlock_mac == 0) || (index <= wlock_mac)) { 2137 s32 ret_val; 2138 2139 ret_val = e1000_acquire_swflag_ich8lan(hw); 2140 2141 if (ret_val) 2142 goto out; 2143 2144 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1), 2145 rar_low); 2146 E1000_WRITE_FLUSH(hw); 2147 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1), 2148 rar_high); 2149 E1000_WRITE_FLUSH(hw); 2150 2151 e1000_release_swflag_ich8lan(hw); 2152 2153 /* verify the register updates */ 2154 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) && 2155 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high)) 2156 return E1000_SUCCESS; 2157 } 2158 } 2159 2160 out: 2161 DEBUGOUT1("Failed to write receive address at index %d\n", index); 2162 return -E1000_ERR_CONFIG; 2163 } 2164 2165 /** 2166 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses 2167 * @hw: pointer to the HW structure 2168 * @mc_addr_list: array of multicast addresses to program 2169 * @mc_addr_count: number of multicast addresses to program 2170 * 2171 * Updates entire Multicast Table Array of the PCH2 MAC and PHY. 2172 * The caller must have a packed mc_addr_list of multicast addresses. 2173 **/ 2174 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, 2175 u8 *mc_addr_list, 2176 u32 mc_addr_count) 2177 { 2178 u16 phy_reg = 0; 2179 int i; 2180 s32 ret_val; 2181 2182 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan"); 2183 2184 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count); 2185 2186 ret_val = hw->phy.ops.acquire(hw); 2187 if (ret_val) 2188 return; 2189 2190 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2191 if (ret_val) 2192 goto release; 2193 2194 for (i = 0; i < hw->mac.mta_reg_count; i++) { 2195 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 2196 (u16)(hw->mac.mta_shadow[i] & 2197 0xFFFF)); 2198 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1), 2199 (u16)((hw->mac.mta_shadow[i] >> 16) & 2200 0xFFFF)); 2201 } 2202 2203 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2204 2205 release: 2206 hw->phy.ops.release(hw); 2207 } 2208 2209 /** 2210 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 2211 * @hw: pointer to the HW structure 2212 * 2213 * Checks if firmware is blocking the reset of the PHY. 2214 * This is a function pointer entry point only called by 2215 * reset routines. 2216 **/ 2217 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 2218 { 2219 u32 fwsm; 2220 bool blocked = FALSE; 2221 int i = 0; 2222 2223 DEBUGFUNC("e1000_check_reset_block_ich8lan"); 2224 2225 do { 2226 fwsm = E1000_READ_REG(hw, E1000_FWSM); 2227 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) { 2228 blocked = TRUE; 2229 msec_delay(10); 2230 continue; 2231 } 2232 blocked = FALSE; 2233 } while (blocked && (i++ < 30)); 2234 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS; 2235 } 2236 2237 /** 2238 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 2239 * @hw: pointer to the HW structure 2240 * 2241 * Assumes semaphore already acquired. 2242 * 2243 **/ 2244 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 2245 { 2246 u16 phy_data; 2247 u32 strap = E1000_READ_REG(hw, E1000_STRAP); 2248 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> 2249 E1000_STRAP_SMT_FREQ_SHIFT; 2250 s32 ret_val; 2251 2252 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 2253 2254 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 2255 if (ret_val) 2256 return ret_val; 2257 2258 phy_data &= ~HV_SMB_ADDR_MASK; 2259 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 2260 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 2261 2262 if (hw->phy.type == e1000_phy_i217) { 2263 /* Restore SMBus frequency */ 2264 if (freq--) { 2265 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 2266 phy_data |= (freq & (1 << 0)) << 2267 HV_SMB_ADDR_FREQ_LOW_SHIFT; 2268 phy_data |= (freq & (1 << 1)) << 2269 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 2270 } else { 2271 DEBUGOUT("Unsupported SMB frequency in PHY\n"); 2272 } 2273 } 2274 2275 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 2276 } 2277 2278 /** 2279 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 2280 * @hw: pointer to the HW structure 2281 * 2282 * SW should configure the LCD from the NVM extended configuration region 2283 * as a workaround for certain parts. 2284 **/ 2285 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 2286 { 2287 struct e1000_phy_info *phy = &hw->phy; 2288 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 2289 s32 ret_val = E1000_SUCCESS; 2290 u16 word_addr, reg_data, reg_addr, phy_page = 0; 2291 2292 DEBUGFUNC("e1000_sw_lcd_config_ich8lan"); 2293 2294 /* Initialize the PHY from the NVM on ICH platforms. This 2295 * is needed due to an issue where the NVM configuration is 2296 * not properly autoloaded after power transitions. 2297 * Therefore, after each PHY reset, we will load the 2298 * configuration data out of the NVM manually. 2299 */ 2300 switch (hw->mac.type) { 2301 case e1000_ich8lan: 2302 if (phy->type != e1000_phy_igp_3) 2303 return ret_val; 2304 2305 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) || 2306 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) { 2307 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 2308 break; 2309 } 2310 /* Fall-thru */ 2311 case e1000_pchlan: 2312 case e1000_pch2lan: 2313 case e1000_pch_lpt: 2314 case e1000_pch_spt: 2315 case e1000_pch_cnp: 2316 case e1000_pch_tgp: 2317 case e1000_pch_adp: 2318 case e1000_pch_mtp: 2319 case e1000_pch_lnp: 2320 case e1000_pch_rpl: 2321 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 2322 break; 2323 default: 2324 return ret_val; 2325 } 2326 2327 ret_val = hw->phy.ops.acquire(hw); 2328 if (ret_val) 2329 return ret_val; 2330 2331 data = E1000_READ_REG(hw, E1000_FEXTNVM); 2332 if (!(data & sw_cfg_mask)) 2333 goto release; 2334 2335 /* Make sure HW does not configure LCD from PHY 2336 * extended configuration before SW configuration 2337 */ 2338 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 2339 if ((hw->mac.type < e1000_pch2lan) && 2340 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 2341 goto release; 2342 2343 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); 2344 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 2345 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 2346 if (!cnf_size) 2347 goto release; 2348 2349 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 2350 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 2351 2352 if (((hw->mac.type == e1000_pchlan) && 2353 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 2354 (hw->mac.type > e1000_pchlan)) { 2355 /* HW configures the SMBus address and LEDs when the 2356 * OEM and LCD Write Enable bits are set in the NVM. 2357 * When both NVM bits are cleared, SW will configure 2358 * them instead. 2359 */ 2360 ret_val = e1000_write_smbus_addr(hw); 2361 if (ret_val) 2362 goto release; 2363 2364 data = E1000_READ_REG(hw, E1000_LEDCTL); 2365 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 2366 (u16)data); 2367 if (ret_val) 2368 goto release; 2369 } 2370 2371 /* Configure LCD from extended configuration region. */ 2372 2373 /* cnf_base_addr is in DWORD */ 2374 word_addr = (u16)(cnf_base_addr << 1); 2375 2376 for (i = 0; i < cnf_size; i++) { 2377 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1, 2378 ®_data); 2379 if (ret_val) 2380 goto release; 2381 2382 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1), 2383 1, ®_addr); 2384 if (ret_val) 2385 goto release; 2386 2387 /* Save off the PHY page for future writes. */ 2388 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 2389 phy_page = reg_data; 2390 continue; 2391 } 2392 2393 reg_addr &= PHY_REG_MASK; 2394 reg_addr |= phy_page; 2395 2396 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr, 2397 reg_data); 2398 if (ret_val) 2399 goto release; 2400 } 2401 2402 release: 2403 hw->phy.ops.release(hw); 2404 return ret_val; 2405 } 2406 2407 /** 2408 * e1000_k1_gig_workaround_hv - K1 Si workaround 2409 * @hw: pointer to the HW structure 2410 * @link: link up bool flag 2411 * 2412 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 2413 * from a lower speed. This workaround disables K1 whenever link is at 1Gig 2414 * If link is down, the function will restore the default K1 setting located 2415 * in the NVM. 2416 **/ 2417 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 2418 { 2419 s32 ret_val = E1000_SUCCESS; 2420 u16 status_reg = 0; 2421 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 2422 2423 DEBUGFUNC("e1000_k1_gig_workaround_hv"); 2424 2425 if (hw->mac.type != e1000_pchlan) 2426 return E1000_SUCCESS; 2427 2428 /* Wrap the whole flow with the sw flag */ 2429 ret_val = hw->phy.ops.acquire(hw); 2430 if (ret_val) 2431 return ret_val; 2432 2433 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 2434 if (link) { 2435 if (hw->phy.type == e1000_phy_82578) { 2436 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS, 2437 &status_reg); 2438 if (ret_val) 2439 goto release; 2440 2441 status_reg &= (BM_CS_STATUS_LINK_UP | 2442 BM_CS_STATUS_RESOLVED | 2443 BM_CS_STATUS_SPEED_MASK); 2444 2445 if (status_reg == (BM_CS_STATUS_LINK_UP | 2446 BM_CS_STATUS_RESOLVED | 2447 BM_CS_STATUS_SPEED_1000)) 2448 k1_enable = FALSE; 2449 } 2450 2451 if (hw->phy.type == e1000_phy_82577) { 2452 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS, 2453 &status_reg); 2454 if (ret_val) 2455 goto release; 2456 2457 status_reg &= (HV_M_STATUS_LINK_UP | 2458 HV_M_STATUS_AUTONEG_COMPLETE | 2459 HV_M_STATUS_SPEED_MASK); 2460 2461 if (status_reg == (HV_M_STATUS_LINK_UP | 2462 HV_M_STATUS_AUTONEG_COMPLETE | 2463 HV_M_STATUS_SPEED_1000)) 2464 k1_enable = FALSE; 2465 } 2466 2467 /* Link stall fix for link up */ 2468 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 2469 0x0100); 2470 if (ret_val) 2471 goto release; 2472 2473 } else { 2474 /* Link stall fix for link down */ 2475 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 2476 0x4100); 2477 if (ret_val) 2478 goto release; 2479 } 2480 2481 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 2482 2483 release: 2484 hw->phy.ops.release(hw); 2485 2486 return ret_val; 2487 } 2488 2489 /** 2490 * e1000_configure_k1_ich8lan - Configure K1 power state 2491 * @hw: pointer to the HW structure 2492 * @enable: K1 state to configure 2493 * 2494 * Configure the K1 power state based on the provided parameter. 2495 * Assumes semaphore already acquired. 2496 * 2497 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2498 **/ 2499 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 2500 { 2501 s32 ret_val; 2502 u32 ctrl_reg = 0; 2503 u32 ctrl_ext = 0; 2504 u32 reg = 0; 2505 u16 kmrn_reg = 0; 2506 2507 DEBUGFUNC("e1000_configure_k1_ich8lan"); 2508 2509 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2510 &kmrn_reg); 2511 if (ret_val) 2512 return ret_val; 2513 2514 if (k1_enable) 2515 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 2516 else 2517 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 2518 2519 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2520 kmrn_reg); 2521 if (ret_val) 2522 return ret_val; 2523 2524 usec_delay(20); 2525 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2526 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 2527 2528 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2529 reg |= E1000_CTRL_FRCSPD; 2530 E1000_WRITE_REG(hw, E1000_CTRL, reg); 2531 2532 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 2533 E1000_WRITE_FLUSH(hw); 2534 usec_delay(20); 2535 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 2536 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2537 E1000_WRITE_FLUSH(hw); 2538 usec_delay(20); 2539 2540 return E1000_SUCCESS; 2541 } 2542 2543 /** 2544 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 2545 * @hw: pointer to the HW structure 2546 * @d0_state: boolean if entering d0 or d3 device state 2547 * 2548 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 2549 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 2550 * in NVM determines whether HW should configure LPLU and Gbe Disable. 2551 **/ 2552 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 2553 { 2554 s32 ret_val = 0; 2555 u32 mac_reg; 2556 u16 oem_reg; 2557 2558 DEBUGFUNC("e1000_oem_bits_config_ich8lan"); 2559 2560 if (hw->mac.type < e1000_pchlan) 2561 return ret_val; 2562 2563 ret_val = hw->phy.ops.acquire(hw); 2564 if (ret_val) 2565 return ret_val; 2566 2567 if (hw->mac.type == e1000_pchlan) { 2568 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 2569 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 2570 goto release; 2571 } 2572 2573 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM); 2574 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 2575 goto release; 2576 2577 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 2578 2579 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg); 2580 if (ret_val) 2581 goto release; 2582 2583 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 2584 2585 if (d0_state) { 2586 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 2587 oem_reg |= HV_OEM_BITS_GBE_DIS; 2588 2589 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 2590 oem_reg |= HV_OEM_BITS_LPLU; 2591 } else { 2592 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 2593 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 2594 oem_reg |= HV_OEM_BITS_GBE_DIS; 2595 2596 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 2597 E1000_PHY_CTRL_NOND0A_LPLU)) 2598 oem_reg |= HV_OEM_BITS_LPLU; 2599 } 2600 2601 /* Set Restart auto-neg to activate the bits */ 2602 if ((d0_state || (hw->mac.type != e1000_pchlan)) && 2603 !hw->phy.ops.check_reset_block(hw)) 2604 oem_reg |= HV_OEM_BITS_RESTART_AN; 2605 2606 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg); 2607 2608 release: 2609 hw->phy.ops.release(hw); 2610 2611 return ret_val; 2612 } 2613 2614 2615 /** 2616 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 2617 * @hw: pointer to the HW structure 2618 **/ 2619 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 2620 { 2621 s32 ret_val; 2622 u16 data; 2623 2624 DEBUGFUNC("e1000_set_mdio_slow_mode_hv"); 2625 2626 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data); 2627 if (ret_val) 2628 return ret_val; 2629 2630 data |= HV_KMRN_MDIO_SLOW; 2631 2632 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data); 2633 2634 return ret_val; 2635 } 2636 2637 /** 2638 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2639 * done after every PHY reset. 2640 **/ 2641 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2642 { 2643 s32 ret_val = E1000_SUCCESS; 2644 u16 phy_data; 2645 2646 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan"); 2647 2648 if (hw->mac.type != e1000_pchlan) 2649 return E1000_SUCCESS; 2650 2651 /* Set MDIO slow mode before any other MDIO access */ 2652 if (hw->phy.type == e1000_phy_82577) { 2653 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2654 if (ret_val) 2655 return ret_val; 2656 } 2657 2658 if (((hw->phy.type == e1000_phy_82577) && 2659 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 2660 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 2661 /* Disable generation of early preamble */ 2662 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); 2663 if (ret_val) 2664 return ret_val; 2665 2666 /* Preamble tuning for SSC */ 2667 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, 2668 0xA204); 2669 if (ret_val) 2670 return ret_val; 2671 } 2672 2673 if (hw->phy.type == e1000_phy_82578) { 2674 /* Return registers to default by doing a soft reset then 2675 * writing 0x3140 to the control register. 2676 */ 2677 if (hw->phy.revision < 2) { 2678 e1000_phy_sw_reset_generic(hw); 2679 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, 2680 0x3140); 2681 } 2682 } 2683 2684 /* Select page 0 */ 2685 ret_val = hw->phy.ops.acquire(hw); 2686 if (ret_val) 2687 return ret_val; 2688 2689 hw->phy.addr = 1; 2690 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 2691 hw->phy.ops.release(hw); 2692 if (ret_val) 2693 return ret_val; 2694 2695 /* Configure the K1 Si workaround during phy reset assuming there is 2696 * link so that it disables K1 if link is in 1Gbps. 2697 */ 2698 ret_val = e1000_k1_gig_workaround_hv(hw, TRUE); 2699 if (ret_val) 2700 return ret_val; 2701 2702 /* Workaround for link disconnects on a busy hub in half duplex */ 2703 ret_val = hw->phy.ops.acquire(hw); 2704 if (ret_val) 2705 return ret_val; 2706 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data); 2707 if (ret_val) 2708 goto release; 2709 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG, 2710 phy_data & 0x00FF); 2711 if (ret_val) 2712 goto release; 2713 2714 /* set MSE higher to enable link to stay up when noise is high */ 2715 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 2716 release: 2717 hw->phy.ops.release(hw); 2718 2719 return ret_val; 2720 } 2721 2722 /** 2723 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 2724 * @hw: pointer to the HW structure 2725 **/ 2726 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 2727 { 2728 u32 mac_reg; 2729 u16 i, phy_reg = 0; 2730 s32 ret_val; 2731 2732 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan"); 2733 2734 ret_val = hw->phy.ops.acquire(hw); 2735 if (ret_val) 2736 return; 2737 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2738 if (ret_val) 2739 goto release; 2740 2741 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */ 2742 for (i = 0; i < (hw->mac.rar_entry_count); i++) { 2743 mac_reg = E1000_READ_REG(hw, E1000_RAL(i)); 2744 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 2745 (u16)(mac_reg & 0xFFFF)); 2746 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 2747 (u16)((mac_reg >> 16) & 0xFFFF)); 2748 2749 mac_reg = E1000_READ_REG(hw, E1000_RAH(i)); 2750 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 2751 (u16)(mac_reg & 0xFFFF)); 2752 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 2753 (u16)((mac_reg & E1000_RAH_AV) 2754 >> 16)); 2755 } 2756 2757 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2758 2759 release: 2760 hw->phy.ops.release(hw); 2761 } 2762 2763 static u32 e1000_calc_rx_da_crc(u8 mac[]) 2764 { 2765 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */ 2766 u32 i, j, mask, crc; 2767 2768 DEBUGFUNC("e1000_calc_rx_da_crc"); 2769 2770 crc = 0xffffffff; 2771 for (i = 0; i < 6; i++) { 2772 crc = crc ^ mac[i]; 2773 for (j = 8; j > 0; j--) { 2774 mask = (crc & 1) * (-1); 2775 crc = (crc >> 1) ^ (poly & mask); 2776 } 2777 } 2778 return ~crc; 2779 } 2780 2781 /** 2782 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 2783 * with 82579 PHY 2784 * @hw: pointer to the HW structure 2785 * @enable: flag to enable/disable workaround when enabling/disabling jumbos 2786 **/ 2787 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 2788 { 2789 s32 ret_val = E1000_SUCCESS; 2790 u16 phy_reg, data; 2791 u32 mac_reg; 2792 u16 i; 2793 2794 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan"); 2795 2796 if (hw->mac.type < e1000_pch2lan) 2797 return E1000_SUCCESS; 2798 2799 /* disable Rx path while enabling/disabling workaround */ 2800 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg); 2801 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), 2802 phy_reg | (1 << 14)); 2803 if (ret_val) 2804 return ret_val; 2805 2806 if (enable) { 2807 /* Write Rx addresses (rar_entry_count for RAL/H, and 2808 * SHRAL/H) and initial CRC values to the MAC 2809 */ 2810 for (i = 0; i < hw->mac.rar_entry_count; i++) { 2811 u8 mac_addr[ETH_ADDR_LEN] = {0}; 2812 u32 addr_high, addr_low; 2813 2814 addr_high = E1000_READ_REG(hw, E1000_RAH(i)); 2815 if (!(addr_high & E1000_RAH_AV)) 2816 continue; 2817 addr_low = E1000_READ_REG(hw, E1000_RAL(i)); 2818 mac_addr[0] = (addr_low & 0xFF); 2819 mac_addr[1] = ((addr_low >> 8) & 0xFF); 2820 mac_addr[2] = ((addr_low >> 16) & 0xFF); 2821 mac_addr[3] = ((addr_low >> 24) & 0xFF); 2822 mac_addr[4] = (addr_high & 0xFF); 2823 mac_addr[5] = ((addr_high >> 8) & 0xFF); 2824 2825 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i), 2826 e1000_calc_rx_da_crc(mac_addr)); 2827 } 2828 2829 /* Write Rx addresses to the PHY */ 2830 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 2831 2832 /* Enable jumbo frame workaround in the MAC */ 2833 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); 2834 mac_reg &= ~(1 << 14); 2835 mac_reg |= (7 << 15); 2836 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg); 2837 2838 mac_reg = E1000_READ_REG(hw, E1000_RCTL); 2839 mac_reg |= E1000_RCTL_SECRC; 2840 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg); 2841 2842 ret_val = e1000_read_kmrn_reg_generic(hw, 2843 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2844 &data); 2845 if (ret_val) 2846 return ret_val; 2847 ret_val = e1000_write_kmrn_reg_generic(hw, 2848 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2849 data | (1 << 0)); 2850 if (ret_val) 2851 return ret_val; 2852 ret_val = e1000_read_kmrn_reg_generic(hw, 2853 E1000_KMRNCTRLSTA_HD_CTRL, 2854 &data); 2855 if (ret_val) 2856 return ret_val; 2857 data &= ~(0xF << 8); 2858 data |= (0xB << 8); 2859 ret_val = e1000_write_kmrn_reg_generic(hw, 2860 E1000_KMRNCTRLSTA_HD_CTRL, 2861 data); 2862 if (ret_val) 2863 return ret_val; 2864 2865 /* Enable jumbo frame workaround in the PHY */ 2866 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); 2867 data &= ~(0x7F << 5); 2868 data |= (0x37 << 5); 2869 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); 2870 if (ret_val) 2871 return ret_val; 2872 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); 2873 data &= ~(1 << 13); 2874 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); 2875 if (ret_val) 2876 return ret_val; 2877 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); 2878 data &= ~(0x3FF << 2); 2879 data |= (E1000_TX_PTR_GAP << 2); 2880 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); 2881 if (ret_val) 2882 return ret_val; 2883 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100); 2884 if (ret_val) 2885 return ret_val; 2886 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); 2887 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data | 2888 (1 << 10)); 2889 if (ret_val) 2890 return ret_val; 2891 } else { 2892 /* Write MAC register values back to h/w defaults */ 2893 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); 2894 mac_reg &= ~(0xF << 14); 2895 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg); 2896 2897 mac_reg = E1000_READ_REG(hw, E1000_RCTL); 2898 mac_reg &= ~E1000_RCTL_SECRC; 2899 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg); 2900 2901 ret_val = e1000_read_kmrn_reg_generic(hw, 2902 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2903 &data); 2904 if (ret_val) 2905 return ret_val; 2906 ret_val = e1000_write_kmrn_reg_generic(hw, 2907 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2908 data & ~(1 << 0)); 2909 if (ret_val) 2910 return ret_val; 2911 ret_val = e1000_read_kmrn_reg_generic(hw, 2912 E1000_KMRNCTRLSTA_HD_CTRL, 2913 &data); 2914 if (ret_val) 2915 return ret_val; 2916 data &= ~(0xF << 8); 2917 data |= (0xB << 8); 2918 ret_val = e1000_write_kmrn_reg_generic(hw, 2919 E1000_KMRNCTRLSTA_HD_CTRL, 2920 data); 2921 if (ret_val) 2922 return ret_val; 2923 2924 /* Write PHY register values back to h/w defaults */ 2925 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); 2926 data &= ~(0x7F << 5); 2927 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); 2928 if (ret_val) 2929 return ret_val; 2930 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); 2931 data |= (1 << 13); 2932 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); 2933 if (ret_val) 2934 return ret_val; 2935 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); 2936 data &= ~(0x3FF << 2); 2937 data |= (0x8 << 2); 2938 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); 2939 if (ret_val) 2940 return ret_val; 2941 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00); 2942 if (ret_val) 2943 return ret_val; 2944 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); 2945 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data & 2946 ~(1 << 10)); 2947 if (ret_val) 2948 return ret_val; 2949 } 2950 2951 /* re-enable Rx path after enabling/disabling workaround */ 2952 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg & 2953 ~(1 << 14)); 2954 } 2955 2956 /** 2957 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2958 * done after every PHY reset. 2959 **/ 2960 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2961 { 2962 s32 ret_val = E1000_SUCCESS; 2963 2964 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan"); 2965 2966 if (hw->mac.type != e1000_pch2lan) 2967 return E1000_SUCCESS; 2968 2969 /* Set MDIO slow mode before any other MDIO access */ 2970 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2971 if (ret_val) 2972 return ret_val; 2973 2974 ret_val = hw->phy.ops.acquire(hw); 2975 if (ret_val) 2976 return ret_val; 2977 /* set MSE higher to enable link to stay up when noise is high */ 2978 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 2979 if (ret_val) 2980 goto release; 2981 /* drop link after 5 times MSE threshold was reached */ 2982 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 2983 release: 2984 hw->phy.ops.release(hw); 2985 2986 return ret_val; 2987 } 2988 2989 /** 2990 * e1000_k1_gig_workaround_lv - K1 Si workaround 2991 * @hw: pointer to the HW structure 2992 * 2993 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps 2994 * Disable K1 for 1000 and 100 speeds 2995 **/ 2996 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 2997 { 2998 s32 ret_val = E1000_SUCCESS; 2999 u16 status_reg = 0; 3000 3001 DEBUGFUNC("e1000_k1_workaround_lv"); 3002 3003 if (hw->mac.type != e1000_pch2lan) 3004 return E1000_SUCCESS; 3005 3006 /* Set K1 beacon duration based on 10Mbs speed */ 3007 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg); 3008 if (ret_val) 3009 return ret_val; 3010 3011 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 3012 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 3013 if (status_reg & 3014 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) { 3015 u16 pm_phy_reg; 3016 3017 /* LV 1G/100 Packet drop issue wa */ 3018 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL, 3019 &pm_phy_reg); 3020 if (ret_val) 3021 return ret_val; 3022 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE; 3023 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, 3024 pm_phy_reg); 3025 if (ret_val) 3026 return ret_val; 3027 } else { 3028 u32 mac_reg; 3029 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4); 3030 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 3031 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 3032 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg); 3033 } 3034 } 3035 3036 return ret_val; 3037 } 3038 3039 /** 3040 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 3041 * @hw: pointer to the HW structure 3042 * @gate: boolean set to TRUE to gate, FALSE to ungate 3043 * 3044 * Gate/ungate the automatic PHY configuration via hardware; perform 3045 * the configuration via software instead. 3046 **/ 3047 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 3048 { 3049 u32 extcnf_ctrl; 3050 3051 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan"); 3052 3053 if (hw->mac.type < e1000_pch2lan) 3054 return; 3055 3056 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 3057 3058 if (gate) 3059 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 3060 else 3061 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 3062 3063 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 3064 } 3065 3066 /** 3067 * e1000_lan_init_done_ich8lan - Check for PHY config completion 3068 * @hw: pointer to the HW structure 3069 * 3070 * Check the appropriate indication the MAC has finished configuring the 3071 * PHY after a software reset. 3072 **/ 3073 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 3074 { 3075 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 3076 3077 DEBUGFUNC("e1000_lan_init_done_ich8lan"); 3078 3079 /* Wait for basic configuration completes before proceeding */ 3080 do { 3081 data = E1000_READ_REG(hw, E1000_STATUS); 3082 data &= E1000_STATUS_LAN_INIT_DONE; 3083 usec_delay(100); 3084 } while ((!data) && --loop); 3085 3086 /* If basic configuration is incomplete before the above loop 3087 * count reaches 0, loading the configuration from NVM will 3088 * leave the PHY in a bad state possibly resulting in no link. 3089 */ 3090 if (loop == 0) 3091 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n"); 3092 3093 /* Clear the Init Done bit for the next init event */ 3094 data = E1000_READ_REG(hw, E1000_STATUS); 3095 data &= ~E1000_STATUS_LAN_INIT_DONE; 3096 E1000_WRITE_REG(hw, E1000_STATUS, data); 3097 } 3098 3099 /** 3100 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 3101 * @hw: pointer to the HW structure 3102 **/ 3103 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 3104 { 3105 s32 ret_val = E1000_SUCCESS; 3106 u16 reg; 3107 3108 DEBUGFUNC("e1000_post_phy_reset_ich8lan"); 3109 3110 if (hw->phy.ops.check_reset_block(hw)) 3111 return E1000_SUCCESS; 3112 3113 /* Allow time for h/w to get to quiescent state after reset */ 3114 msec_delay(10); 3115 3116 /* Perform any necessary post-reset workarounds */ 3117 switch (hw->mac.type) { 3118 case e1000_pchlan: 3119 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 3120 if (ret_val) 3121 return ret_val; 3122 break; 3123 case e1000_pch2lan: 3124 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 3125 if (ret_val) 3126 return ret_val; 3127 break; 3128 default: 3129 break; 3130 } 3131 3132 /* Clear the host wakeup bit after lcd reset */ 3133 if (hw->mac.type >= e1000_pchlan) { 3134 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®); 3135 reg &= ~BM_WUC_HOST_WU_BIT; 3136 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg); 3137 } 3138 3139 /* Configure the LCD with the extended configuration region in NVM */ 3140 ret_val = e1000_sw_lcd_config_ich8lan(hw); 3141 if (ret_val) 3142 return ret_val; 3143 3144 /* Configure the LCD with the OEM bits in NVM */ 3145 ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE); 3146 3147 if (hw->mac.type == e1000_pch2lan) { 3148 /* Ungate automatic PHY configuration on non-managed 82579 */ 3149 if (!(E1000_READ_REG(hw, E1000_FWSM) & 3150 E1000_ICH_FWSM_FW_VALID)) { 3151 msec_delay(10); 3152 e1000_gate_hw_phy_config_ich8lan(hw, FALSE); 3153 } 3154 3155 /* Set EEE LPI Update Timer to 200usec */ 3156 ret_val = hw->phy.ops.acquire(hw); 3157 if (ret_val) 3158 return ret_val; 3159 ret_val = e1000_write_emi_reg_locked(hw, 3160 I82579_LPI_UPDATE_TIMER, 3161 0x1387); 3162 hw->phy.ops.release(hw); 3163 } 3164 3165 return ret_val; 3166 } 3167 3168 /** 3169 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 3170 * @hw: pointer to the HW structure 3171 * 3172 * Resets the PHY 3173 * This is a function pointer entry point called by drivers 3174 * or other shared routines. 3175 **/ 3176 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 3177 { 3178 s32 ret_val = E1000_SUCCESS; 3179 3180 DEBUGFUNC("e1000_phy_hw_reset_ich8lan"); 3181 3182 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 3183 if ((hw->mac.type == e1000_pch2lan) && 3184 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) 3185 e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 3186 3187 ret_val = e1000_phy_hw_reset_generic(hw); 3188 if (ret_val) 3189 return ret_val; 3190 3191 return e1000_post_phy_reset_ich8lan(hw); 3192 } 3193 3194 /** 3195 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 3196 * @hw: pointer to the HW structure 3197 * @active: TRUE to enable LPLU, FALSE to disable 3198 * 3199 * Sets the LPLU state according to the active flag. For PCH, if OEM write 3200 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 3201 * the phy speed. This function will manually set the LPLU bit and restart 3202 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 3203 * since it configures the same bit. 3204 **/ 3205 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 3206 { 3207 s32 ret_val; 3208 u16 oem_reg; 3209 3210 DEBUGFUNC("e1000_set_lplu_state_pchlan"); 3211 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg); 3212 if (ret_val) 3213 return ret_val; 3214 3215 if (active) 3216 oem_reg |= HV_OEM_BITS_LPLU; 3217 else 3218 oem_reg &= ~HV_OEM_BITS_LPLU; 3219 3220 if (!hw->phy.ops.check_reset_block(hw)) 3221 oem_reg |= HV_OEM_BITS_RESTART_AN; 3222 3223 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg); 3224 } 3225 3226 /** 3227 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 3228 * @hw: pointer to the HW structure 3229 * @active: TRUE to enable LPLU, FALSE to disable 3230 * 3231 * Sets the LPLU D0 state according to the active flag. When 3232 * activating LPLU this function also disables smart speed 3233 * and vice versa. LPLU will not be activated unless the 3234 * device autonegotiation advertisement meets standards of 3235 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3236 * This is a function pointer entry point only called by 3237 * PHY setup routines. 3238 **/ 3239 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3240 { 3241 struct e1000_phy_info *phy = &hw->phy; 3242 u32 phy_ctrl; 3243 s32 ret_val = E1000_SUCCESS; 3244 u16 data; 3245 3246 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); 3247 3248 if (phy->type == e1000_phy_ife) 3249 return E1000_SUCCESS; 3250 3251 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 3252 3253 if (active) { 3254 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 3255 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3256 3257 if (phy->type != e1000_phy_igp_3) 3258 return E1000_SUCCESS; 3259 3260 /* Call gig speed drop workaround on LPLU before accessing 3261 * any PHY registers 3262 */ 3263 if (hw->mac.type == e1000_ich8lan) 3264 e1000_gig_downshift_workaround_ich8lan(hw); 3265 3266 /* When LPLU is enabled, we should disable SmartSpeed */ 3267 ret_val = phy->ops.read_reg(hw, 3268 IGP01E1000_PHY_PORT_CONFIG, 3269 &data); 3270 if (ret_val) 3271 return ret_val; 3272 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3273 ret_val = phy->ops.write_reg(hw, 3274 IGP01E1000_PHY_PORT_CONFIG, 3275 data); 3276 if (ret_val) 3277 return ret_val; 3278 } else { 3279 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 3280 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3281 3282 if (phy->type != e1000_phy_igp_3) 3283 return E1000_SUCCESS; 3284 3285 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3286 * during Dx states where the power conservation is most 3287 * important. During driver activity we should enable 3288 * SmartSpeed, so performance is maintained. 3289 */ 3290 if (phy->smart_speed == e1000_smart_speed_on) { 3291 ret_val = phy->ops.read_reg(hw, 3292 IGP01E1000_PHY_PORT_CONFIG, 3293 &data); 3294 if (ret_val) 3295 return ret_val; 3296 3297 data |= IGP01E1000_PSCFR_SMART_SPEED; 3298 ret_val = phy->ops.write_reg(hw, 3299 IGP01E1000_PHY_PORT_CONFIG, 3300 data); 3301 if (ret_val) 3302 return ret_val; 3303 } else if (phy->smart_speed == e1000_smart_speed_off) { 3304 ret_val = phy->ops.read_reg(hw, 3305 IGP01E1000_PHY_PORT_CONFIG, 3306 &data); 3307 if (ret_val) 3308 return ret_val; 3309 3310 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3311 ret_val = phy->ops.write_reg(hw, 3312 IGP01E1000_PHY_PORT_CONFIG, 3313 data); 3314 if (ret_val) 3315 return ret_val; 3316 } 3317 } 3318 3319 return E1000_SUCCESS; 3320 } 3321 3322 /** 3323 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 3324 * @hw: pointer to the HW structure 3325 * @active: TRUE to enable LPLU, FALSE to disable 3326 * 3327 * Sets the LPLU D3 state according to the active flag. When 3328 * activating LPLU this function also disables smart speed 3329 * and vice versa. LPLU will not be activated unless the 3330 * device autonegotiation advertisement meets standards of 3331 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3332 * This is a function pointer entry point only called by 3333 * PHY setup routines. 3334 **/ 3335 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3336 { 3337 struct e1000_phy_info *phy = &hw->phy; 3338 u32 phy_ctrl; 3339 s32 ret_val = E1000_SUCCESS; 3340 u16 data; 3341 3342 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan"); 3343 3344 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 3345 3346 if (!active) { 3347 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 3348 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3349 3350 if (phy->type != e1000_phy_igp_3) 3351 return E1000_SUCCESS; 3352 3353 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3354 * during Dx states where the power conservation is most 3355 * important. During driver activity we should enable 3356 * SmartSpeed, so performance is maintained. 3357 */ 3358 if (phy->smart_speed == e1000_smart_speed_on) { 3359 ret_val = phy->ops.read_reg(hw, 3360 IGP01E1000_PHY_PORT_CONFIG, 3361 &data); 3362 if (ret_val) 3363 return ret_val; 3364 3365 data |= IGP01E1000_PSCFR_SMART_SPEED; 3366 ret_val = phy->ops.write_reg(hw, 3367 IGP01E1000_PHY_PORT_CONFIG, 3368 data); 3369 if (ret_val) 3370 return ret_val; 3371 } else if (phy->smart_speed == e1000_smart_speed_off) { 3372 ret_val = phy->ops.read_reg(hw, 3373 IGP01E1000_PHY_PORT_CONFIG, 3374 &data); 3375 if (ret_val) 3376 return ret_val; 3377 3378 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3379 ret_val = phy->ops.write_reg(hw, 3380 IGP01E1000_PHY_PORT_CONFIG, 3381 data); 3382 if (ret_val) 3383 return ret_val; 3384 } 3385 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 3386 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 3387 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 3388 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 3389 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3390 3391 if (phy->type != e1000_phy_igp_3) 3392 return E1000_SUCCESS; 3393 3394 /* Call gig speed drop workaround on LPLU before accessing 3395 * any PHY registers 3396 */ 3397 if (hw->mac.type == e1000_ich8lan) 3398 e1000_gig_downshift_workaround_ich8lan(hw); 3399 3400 /* When LPLU is enabled, we should disable SmartSpeed */ 3401 ret_val = phy->ops.read_reg(hw, 3402 IGP01E1000_PHY_PORT_CONFIG, 3403 &data); 3404 if (ret_val) 3405 return ret_val; 3406 3407 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3408 ret_val = phy->ops.write_reg(hw, 3409 IGP01E1000_PHY_PORT_CONFIG, 3410 data); 3411 } 3412 3413 return ret_val; 3414 } 3415 3416 /** 3417 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 3418 * @hw: pointer to the HW structure 3419 * @bank: pointer to the variable that returns the active bank 3420 * 3421 * Reads signature byte from the NVM using the flash access registers. 3422 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 3423 **/ 3424 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 3425 { 3426 u32 eecd; 3427 struct e1000_nvm_info *nvm = &hw->nvm; 3428 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 3429 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 3430 u32 nvm_dword = 0; 3431 u8 sig_byte = 0; 3432 s32 ret_val; 3433 3434 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan"); 3435 3436 switch (hw->mac.type) { 3437 case e1000_pch_spt: 3438 case e1000_pch_cnp: 3439 case e1000_pch_tgp: 3440 case e1000_pch_adp: 3441 case e1000_pch_mtp: 3442 case e1000_pch_lnp: 3443 case e1000_pch_rpl: 3444 bank1_offset = nvm->flash_bank_size; 3445 act_offset = E1000_ICH_NVM_SIG_WORD; 3446 3447 /* set bank to 0 in case flash read fails */ 3448 *bank = 0; 3449 3450 /* Check bank 0 */ 3451 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, 3452 &nvm_dword); 3453 if (ret_val) 3454 return ret_val; 3455 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3456 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3457 E1000_ICH_NVM_SIG_VALUE) { 3458 *bank = 0; 3459 return E1000_SUCCESS; 3460 } 3461 3462 /* Check bank 1 */ 3463 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + 3464 bank1_offset, 3465 &nvm_dword); 3466 if (ret_val) 3467 return ret_val; 3468 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3469 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3470 E1000_ICH_NVM_SIG_VALUE) { 3471 *bank = 1; 3472 return E1000_SUCCESS; 3473 } 3474 3475 DEBUGOUT("ERROR: No valid NVM bank present\n"); 3476 return -E1000_ERR_NVM; 3477 case e1000_ich8lan: 3478 case e1000_ich9lan: 3479 eecd = E1000_READ_REG(hw, E1000_EECD); 3480 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 3481 E1000_EECD_SEC1VAL_VALID_MASK) { 3482 if (eecd & E1000_EECD_SEC1VAL) 3483 *bank = 1; 3484 else 3485 *bank = 0; 3486 3487 return E1000_SUCCESS; 3488 } 3489 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 3490 /* fall-thru */ 3491 default: 3492 /* set bank to 0 in case flash read fails */ 3493 *bank = 0; 3494 3495 /* Check bank 0 */ 3496 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 3497 &sig_byte); 3498 if (ret_val) 3499 return ret_val; 3500 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3501 E1000_ICH_NVM_SIG_VALUE) { 3502 *bank = 0; 3503 return E1000_SUCCESS; 3504 } 3505 3506 /* Check bank 1 */ 3507 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 3508 bank1_offset, 3509 &sig_byte); 3510 if (ret_val) 3511 return ret_val; 3512 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3513 E1000_ICH_NVM_SIG_VALUE) { 3514 *bank = 1; 3515 return E1000_SUCCESS; 3516 } 3517 3518 DEBUGOUT("ERROR: No valid NVM bank present\n"); 3519 return -E1000_ERR_NVM; 3520 } 3521 } 3522 3523 /** 3524 * e1000_read_nvm_spt - NVM access for SPT 3525 * @hw: pointer to the HW structure 3526 * @offset: The offset (in bytes) of the word(s) to read. 3527 * @words: Size of data to read in words. 3528 * @data: pointer to the word(s) to read at offset. 3529 * 3530 * Reads a word(s) from the NVM 3531 **/ 3532 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 3533 u16 *data) 3534 { 3535 struct e1000_nvm_info *nvm = &hw->nvm; 3536 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3537 u32 act_offset; 3538 s32 ret_val = E1000_SUCCESS; 3539 u32 bank = 0; 3540 u32 dword = 0; 3541 u16 offset_to_read; 3542 u16 i; 3543 3544 DEBUGFUNC("e1000_read_nvm_spt"); 3545 3546 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3547 (words == 0)) { 3548 DEBUGOUT("nvm parameter(s) out of bounds\n"); 3549 ret_val = -E1000_ERR_NVM; 3550 goto out; 3551 } 3552 3553 nvm->ops.acquire(hw); 3554 3555 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3556 if (ret_val != E1000_SUCCESS) { 3557 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 3558 bank = 0; 3559 } 3560 3561 act_offset = (bank) ? nvm->flash_bank_size : 0; 3562 act_offset += offset; 3563 3564 ret_val = E1000_SUCCESS; 3565 3566 for (i = 0; i < words; i += 2) { 3567 if (words - i == 1) { 3568 if (dev_spec->shadow_ram[offset+i].modified) { 3569 data[i] = dev_spec->shadow_ram[offset+i].value; 3570 } else { 3571 offset_to_read = act_offset + i - 3572 ((act_offset + i) % 2); 3573 ret_val = 3574 e1000_read_flash_dword_ich8lan(hw, 3575 offset_to_read, 3576 &dword); 3577 if (ret_val) 3578 break; 3579 if ((act_offset + i) % 2 == 0) 3580 data[i] = (u16)(dword & 0xFFFF); 3581 else 3582 data[i] = (u16)((dword >> 16) & 0xFFFF); 3583 } 3584 } else { 3585 offset_to_read = act_offset + i; 3586 if (!(dev_spec->shadow_ram[offset+i].modified) || 3587 !(dev_spec->shadow_ram[offset+i+1].modified)) { 3588 ret_val = 3589 e1000_read_flash_dword_ich8lan(hw, 3590 offset_to_read, 3591 &dword); 3592 if (ret_val) 3593 break; 3594 } 3595 if (dev_spec->shadow_ram[offset+i].modified) 3596 data[i] = dev_spec->shadow_ram[offset+i].value; 3597 else 3598 data[i] = (u16) (dword & 0xFFFF); 3599 if (dev_spec->shadow_ram[offset+i].modified) 3600 data[i+1] = 3601 dev_spec->shadow_ram[offset+i+1].value; 3602 else 3603 data[i+1] = (u16) (dword >> 16 & 0xFFFF); 3604 } 3605 } 3606 3607 nvm->ops.release(hw); 3608 3609 out: 3610 if (ret_val) 3611 DEBUGOUT1("NVM read error: %d\n", ret_val); 3612 3613 return ret_val; 3614 } 3615 3616 /** 3617 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 3618 * @hw: pointer to the HW structure 3619 * @offset: The offset (in bytes) of the word(s) to read. 3620 * @words: Size of data to read in words 3621 * @data: Pointer to the word(s) to read at offset. 3622 * 3623 * Reads a word(s) from the NVM using the flash access registers. 3624 **/ 3625 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3626 u16 *data) 3627 { 3628 struct e1000_nvm_info *nvm = &hw->nvm; 3629 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3630 u32 act_offset; 3631 s32 ret_val = E1000_SUCCESS; 3632 u32 bank = 0; 3633 u16 i, word; 3634 3635 DEBUGFUNC("e1000_read_nvm_ich8lan"); 3636 3637 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3638 (words == 0)) { 3639 DEBUGOUT("nvm parameter(s) out of bounds\n"); 3640 ret_val = -E1000_ERR_NVM; 3641 goto out; 3642 } 3643 3644 nvm->ops.acquire(hw); 3645 3646 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3647 if (ret_val != E1000_SUCCESS) { 3648 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 3649 bank = 0; 3650 } 3651 3652 act_offset = (bank) ? nvm->flash_bank_size : 0; 3653 act_offset += offset; 3654 3655 ret_val = E1000_SUCCESS; 3656 for (i = 0; i < words; i++) { 3657 if (dev_spec->shadow_ram[offset+i].modified) { 3658 data[i] = dev_spec->shadow_ram[offset+i].value; 3659 } else { 3660 ret_val = e1000_read_flash_word_ich8lan(hw, 3661 act_offset + i, 3662 &word); 3663 if (ret_val) 3664 break; 3665 data[i] = word; 3666 } 3667 } 3668 3669 nvm->ops.release(hw); 3670 3671 out: 3672 if (ret_val) 3673 DEBUGOUT1("NVM read error: %d\n", ret_val); 3674 3675 return ret_val; 3676 } 3677 3678 /** 3679 * e1000_flash_cycle_init_ich8lan - Initialize flash 3680 * @hw: pointer to the HW structure 3681 * 3682 * This function does initial flash setup so that a new read/write/erase cycle 3683 * can be started. 3684 **/ 3685 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 3686 { 3687 union ich8_hws_flash_status hsfsts; 3688 s32 ret_val = -E1000_ERR_NVM; 3689 3690 DEBUGFUNC("e1000_flash_cycle_init_ich8lan"); 3691 3692 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 3693 3694 /* Check if the flash descriptor is valid */ 3695 if (!hsfsts.hsf_status.fldesvalid) { 3696 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n"); 3697 return -E1000_ERR_NVM; 3698 } 3699 3700 /* Clear FCERR and DAEL in hw status by writing 1 */ 3701 hsfsts.hsf_status.flcerr = 1; 3702 hsfsts.hsf_status.dael = 1; 3703 if (hw->mac.type >= e1000_pch_spt) 3704 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3705 hsfsts.regval & 0xFFFF); 3706 else 3707 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 3708 3709 /* Either we should have a hardware SPI cycle in progress 3710 * bit to check against, in order to start a new cycle or 3711 * FDONE bit should be changed in the hardware so that it 3712 * is 1 after hardware reset, which can then be used as an 3713 * indication whether a cycle is in progress or has been 3714 * completed. 3715 */ 3716 3717 if (!hsfsts.hsf_status.flcinprog) { 3718 /* There is no cycle running at present, 3719 * so we can start a cycle. 3720 * Begin by setting Flash Cycle Done. 3721 */ 3722 hsfsts.hsf_status.flcdone = 1; 3723 if (hw->mac.type >= e1000_pch_spt) 3724 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3725 hsfsts.regval & 0xFFFF); 3726 else 3727 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 3728 hsfsts.regval); 3729 ret_val = E1000_SUCCESS; 3730 } else { 3731 s32 i; 3732 3733 /* Otherwise poll for sometime so the current 3734 * cycle has a chance to end before giving up. 3735 */ 3736 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 3737 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 3738 ICH_FLASH_HSFSTS); 3739 if (!hsfsts.hsf_status.flcinprog) { 3740 ret_val = E1000_SUCCESS; 3741 break; 3742 } 3743 usec_delay(1); 3744 } 3745 if (ret_val == E1000_SUCCESS) { 3746 /* Successful in waiting for previous cycle to timeout, 3747 * now set the Flash Cycle Done. 3748 */ 3749 hsfsts.hsf_status.flcdone = 1; 3750 if (hw->mac.type >= e1000_pch_spt) 3751 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3752 hsfsts.regval & 0xFFFF); 3753 else 3754 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 3755 hsfsts.regval); 3756 } else { 3757 DEBUGOUT("Flash controller busy, cannot get access\n"); 3758 } 3759 } 3760 3761 return ret_val; 3762 } 3763 3764 /** 3765 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 3766 * @hw: pointer to the HW structure 3767 * @timeout: maximum time to wait for completion 3768 * 3769 * This function starts a flash cycle and waits for its completion. 3770 **/ 3771 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 3772 { 3773 union ich8_hws_flash_ctrl hsflctl; 3774 union ich8_hws_flash_status hsfsts; 3775 u32 i = 0; 3776 3777 DEBUGFUNC("e1000_flash_cycle_ich8lan"); 3778 3779 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 3780 if (hw->mac.type >= e1000_pch_spt) 3781 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16; 3782 else 3783 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 3784 hsflctl.hsf_ctrl.flcgo = 1; 3785 3786 if (hw->mac.type >= e1000_pch_spt) 3787 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3788 hsflctl.regval << 16); 3789 else 3790 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 3791 3792 /* wait till FDONE bit is set to 1 */ 3793 do { 3794 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 3795 if (hsfsts.hsf_status.flcdone) 3796 break; 3797 usec_delay(1); 3798 } while (i++ < timeout); 3799 3800 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 3801 return E1000_SUCCESS; 3802 3803 return -E1000_ERR_NVM; 3804 } 3805 3806 /** 3807 * e1000_read_flash_dword_ich8lan - Read dword from flash 3808 * @hw: pointer to the HW structure 3809 * @offset: offset to data location 3810 * @data: pointer to the location for storing the data 3811 * 3812 * Reads the flash dword at offset into data. Offset is converted 3813 * to bytes before read. 3814 **/ 3815 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, 3816 u32 *data) 3817 { 3818 DEBUGFUNC("e1000_read_flash_dword_ich8lan"); 3819 3820 if (!data) 3821 return -E1000_ERR_NVM; 3822 3823 /* Must convert word offset into bytes. */ 3824 offset <<= 1; 3825 3826 return e1000_read_flash_data32_ich8lan(hw, offset, data); 3827 } 3828 3829 /** 3830 * e1000_read_flash_word_ich8lan - Read word from flash 3831 * @hw: pointer to the HW structure 3832 * @offset: offset to data location 3833 * @data: pointer to the location for storing the data 3834 * 3835 * Reads the flash word at offset into data. Offset is converted 3836 * to bytes before read. 3837 **/ 3838 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 3839 u16 *data) 3840 { 3841 DEBUGFUNC("e1000_read_flash_word_ich8lan"); 3842 3843 if (!data) 3844 return -E1000_ERR_NVM; 3845 3846 /* Must convert offset into bytes. */ 3847 offset <<= 1; 3848 3849 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 3850 } 3851 3852 /** 3853 * e1000_read_flash_byte_ich8lan - Read byte from flash 3854 * @hw: pointer to the HW structure 3855 * @offset: The offset of the byte to read. 3856 * @data: Pointer to a byte to store the value read. 3857 * 3858 * Reads a single byte from the NVM using the flash access registers. 3859 **/ 3860 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3861 u8 *data) 3862 { 3863 s32 ret_val; 3864 u16 word = 0; 3865 3866 /* In SPT, only 32 bits access is supported, 3867 * so this function should not be called. 3868 */ 3869 if (hw->mac.type >= e1000_pch_spt) 3870 return -E1000_ERR_NVM; 3871 else 3872 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 3873 3874 if (ret_val) 3875 return ret_val; 3876 3877 *data = (u8)word; 3878 3879 return E1000_SUCCESS; 3880 } 3881 3882 /** 3883 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 3884 * @hw: pointer to the HW structure 3885 * @offset: The offset (in bytes) of the byte or word to read. 3886 * @size: Size of data to read, 1=byte 2=word 3887 * @data: Pointer to the word to store the value read. 3888 * 3889 * Reads a byte or word from the NVM using the flash access registers. 3890 **/ 3891 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3892 u8 size, u16 *data) 3893 { 3894 union ich8_hws_flash_status hsfsts; 3895 union ich8_hws_flash_ctrl hsflctl; 3896 u32 flash_linear_addr; 3897 u32 flash_data = 0; 3898 s32 ret_val = -E1000_ERR_NVM; 3899 u8 count = 0; 3900 3901 DEBUGFUNC("e1000_read_flash_data_ich8lan"); 3902 3903 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 3904 return -E1000_ERR_NVM; 3905 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3906 hw->nvm.flash_base_addr); 3907 3908 do { 3909 usec_delay(1); 3910 /* Steps */ 3911 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3912 if (ret_val != E1000_SUCCESS) 3913 break; 3914 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 3915 3916 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3917 hsflctl.hsf_ctrl.fldbcount = size - 1; 3918 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3919 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 3920 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 3921 3922 ret_val = e1000_flash_cycle_ich8lan(hw, 3923 ICH_FLASH_READ_COMMAND_TIMEOUT); 3924 3925 /* Check if FCERR is set to 1, if set to 1, clear it 3926 * and try the whole sequence a few more times, else 3927 * read in (shift in) the Flash Data0, the order is 3928 * least significant byte first msb to lsb 3929 */ 3930 if (ret_val == E1000_SUCCESS) { 3931 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 3932 if (size == 1) 3933 *data = (u8)(flash_data & 0x000000FF); 3934 else if (size == 2) 3935 *data = (u16)(flash_data & 0x0000FFFF); 3936 break; 3937 } else { 3938 /* If we've gotten here, then things are probably 3939 * completely hosed, but if the error condition is 3940 * detected, it won't hurt to give it another try... 3941 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3942 */ 3943 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 3944 ICH_FLASH_HSFSTS); 3945 if (hsfsts.hsf_status.flcerr) { 3946 /* Repeat for some time before giving up. */ 3947 continue; 3948 } else if (!hsfsts.hsf_status.flcdone) { 3949 DEBUGOUT("Timeout error - flash cycle did not complete.\n"); 3950 break; 3951 } 3952 } 3953 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3954 3955 return ret_val; 3956 } 3957 3958 /** 3959 * e1000_read_flash_data32_ich8lan - Read dword from NVM 3960 * @hw: pointer to the HW structure 3961 * @offset: The offset (in bytes) of the dword to read. 3962 * @data: Pointer to the dword to store the value read. 3963 * 3964 * Reads a byte or word from the NVM using the flash access registers. 3965 **/ 3966 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 3967 u32 *data) 3968 { 3969 union ich8_hws_flash_status hsfsts; 3970 union ich8_hws_flash_ctrl hsflctl; 3971 u32 flash_linear_addr; 3972 s32 ret_val = -E1000_ERR_NVM; 3973 u8 count = 0; 3974 3975 DEBUGFUNC("e1000_read_flash_data_ich8lan"); 3976 3977 if (offset > ICH_FLASH_LINEAR_ADDR_MASK && hw->mac.type < e1000_pch_spt) 3978 return -E1000_ERR_NVM; 3979 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3980 hw->nvm.flash_base_addr); 3981 3982 do { 3983 usec_delay(1); 3984 /* Steps */ 3985 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3986 if (ret_val != E1000_SUCCESS) 3987 break; 3988 /* In SPT, This register is in Lan memory space, not flash. 3989 * Therefore, only 32 bit access is supported 3990 */ 3991 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16; 3992 3993 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3994 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 3995 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3996 /* In SPT, This register is in Lan memory space, not flash. 3997 * Therefore, only 32 bit access is supported 3998 */ 3999 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 4000 (u32)hsflctl.regval << 16); 4001 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 4002 4003 ret_val = e1000_flash_cycle_ich8lan(hw, 4004 ICH_FLASH_READ_COMMAND_TIMEOUT); 4005 4006 /* Check if FCERR is set to 1, if set to 1, clear it 4007 * and try the whole sequence a few more times, else 4008 * read in (shift in) the Flash Data0, the order is 4009 * least significant byte first msb to lsb 4010 */ 4011 if (ret_val == E1000_SUCCESS) { 4012 *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 4013 break; 4014 } else { 4015 /* If we've gotten here, then things are probably 4016 * completely hosed, but if the error condition is 4017 * detected, it won't hurt to give it another try... 4018 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 4019 */ 4020 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 4021 ICH_FLASH_HSFSTS); 4022 if (hsfsts.hsf_status.flcerr) { 4023 /* Repeat for some time before giving up. */ 4024 continue; 4025 } else if (!hsfsts.hsf_status.flcdone) { 4026 DEBUGOUT("Timeout error - flash cycle did not complete.\n"); 4027 break; 4028 } 4029 } 4030 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4031 4032 return ret_val; 4033 } 4034 4035 /** 4036 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 4037 * @hw: pointer to the HW structure 4038 * @offset: The offset (in bytes) of the word(s) to write. 4039 * @words: Size of data to write in words 4040 * @data: Pointer to the word(s) to write at offset. 4041 * 4042 * Writes a byte or word to the NVM using the flash access registers. 4043 **/ 4044 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 4045 u16 *data) 4046 { 4047 struct e1000_nvm_info *nvm = &hw->nvm; 4048 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4049 u16 i; 4050 4051 DEBUGFUNC("e1000_write_nvm_ich8lan"); 4052 4053 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 4054 (words == 0)) { 4055 DEBUGOUT("nvm parameter(s) out of bounds\n"); 4056 return -E1000_ERR_NVM; 4057 } 4058 4059 nvm->ops.acquire(hw); 4060 4061 for (i = 0; i < words; i++) { 4062 dev_spec->shadow_ram[offset+i].modified = TRUE; 4063 dev_spec->shadow_ram[offset+i].value = data[i]; 4064 } 4065 4066 nvm->ops.release(hw); 4067 4068 return E1000_SUCCESS; 4069 } 4070 4071 /** 4072 * e1000_update_nvm_checksum_spt - Update the checksum for NVM 4073 * @hw: pointer to the HW structure 4074 * 4075 * The NVM checksum is updated by calling the generic update_nvm_checksum, 4076 * which writes the checksum to the shadow ram. The changes in the shadow 4077 * ram are then committed to the EEPROM by processing each bank at a time 4078 * checking for the modified bit and writing only the pending changes. 4079 * After a successful commit, the shadow ram is cleared and is ready for 4080 * future writes. 4081 **/ 4082 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) 4083 { 4084 struct e1000_nvm_info *nvm = &hw->nvm; 4085 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4086 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 4087 s32 ret_val; 4088 u32 dword = 0; 4089 4090 DEBUGFUNC("e1000_update_nvm_checksum_spt"); 4091 4092 ret_val = e1000_update_nvm_checksum_generic(hw); 4093 if (ret_val) 4094 goto out; 4095 4096 if (nvm->type != e1000_nvm_flash_sw) 4097 goto out; 4098 4099 nvm->ops.acquire(hw); 4100 4101 /* We're writing to the opposite bank so if we're on bank 1, 4102 * write to bank 0 etc. We also need to erase the segment that 4103 * is going to be written 4104 */ 4105 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 4106 if (ret_val != E1000_SUCCESS) { 4107 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 4108 bank = 0; 4109 } 4110 4111 if (bank == 0) { 4112 new_bank_offset = nvm->flash_bank_size; 4113 old_bank_offset = 0; 4114 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 4115 if (ret_val) 4116 goto release; 4117 } else { 4118 old_bank_offset = nvm->flash_bank_size; 4119 new_bank_offset = 0; 4120 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 4121 if (ret_val) 4122 goto release; 4123 } 4124 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) { 4125 /* Determine whether to write the value stored 4126 * in the other NVM bank or a modified value stored 4127 * in the shadow RAM 4128 */ 4129 ret_val = e1000_read_flash_dword_ich8lan(hw, 4130 i + old_bank_offset, 4131 &dword); 4132 4133 if (dev_spec->shadow_ram[i].modified) { 4134 dword &= 0xffff0000; 4135 dword |= (dev_spec->shadow_ram[i].value & 0xffff); 4136 } 4137 if (dev_spec->shadow_ram[i + 1].modified) { 4138 dword &= 0x0000ffff; 4139 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) 4140 << 16); 4141 } 4142 if (ret_val) 4143 break; 4144 4145 /* If the word is 0x13, then make sure the signature bits 4146 * (15:14) are 11b until the commit has completed. 4147 * This will allow us to write 10b which indicates the 4148 * signature is valid. We want to do this after the write 4149 * has completed so that we don't mark the segment valid 4150 * while the write is still in progress 4151 */ 4152 if (i == E1000_ICH_NVM_SIG_WORD - 1) 4153 dword |= E1000_ICH_NVM_SIG_MASK << 16; 4154 4155 /* Convert offset to bytes. */ 4156 act_offset = (i + new_bank_offset) << 1; 4157 4158 usec_delay(100); 4159 4160 /* Write the data to the new bank. Offset in words*/ 4161 act_offset = i + new_bank_offset; 4162 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, 4163 dword); 4164 if (ret_val) 4165 break; 4166 } 4167 4168 /* Don't bother writing the segment valid bits if sector 4169 * programming failed. 4170 */ 4171 if (ret_val) { 4172 DEBUGOUT("Flash commit failed.\n"); 4173 goto release; 4174 } 4175 4176 /* Finally validate the new segment by setting bit 15:14 4177 * to 10b in word 0x13 , this can be done without an 4178 * erase as well since these bits are 11 to start with 4179 * and we need to change bit 14 to 0b 4180 */ 4181 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4182 4183 /*offset in words but we read dword*/ 4184 --act_offset; 4185 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 4186 4187 if (ret_val) 4188 goto release; 4189 4190 dword &= 0xBFFFFFFF; 4191 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 4192 4193 if (ret_val) 4194 goto release; 4195 4196 /* And invalidate the previously valid segment by setting 4197 * its signature word (0x13) high_byte to 0b. This can be 4198 * done without an erase because flash erase sets all bits 4199 * to 1's. We can write 1's to 0's without an erase 4200 */ 4201 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4202 4203 /* offset in words but we read dword*/ 4204 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; 4205 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 4206 4207 if (ret_val) 4208 goto release; 4209 4210 dword &= 0x00FFFFFF; 4211 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 4212 4213 if (ret_val) 4214 goto release; 4215 4216 /* Great! Everything worked, we can now clear the cached entries. */ 4217 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 4218 dev_spec->shadow_ram[i].modified = FALSE; 4219 dev_spec->shadow_ram[i].value = 0xFFFF; 4220 } 4221 4222 release: 4223 nvm->ops.release(hw); 4224 4225 /* Reload the EEPROM, or else modifications will not appear 4226 * until after the next adapter reset. 4227 */ 4228 if (!ret_val) { 4229 nvm->ops.reload(hw); 4230 msec_delay(10); 4231 } 4232 4233 out: 4234 if (ret_val) 4235 DEBUGOUT1("NVM update error: %d\n", ret_val); 4236 4237 return ret_val; 4238 } 4239 4240 /** 4241 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 4242 * @hw: pointer to the HW structure 4243 * 4244 * The NVM checksum is updated by calling the generic update_nvm_checksum, 4245 * which writes the checksum to the shadow ram. The changes in the shadow 4246 * ram are then committed to the EEPROM by processing each bank at a time 4247 * checking for the modified bit and writing only the pending changes. 4248 * After a successful commit, the shadow ram is cleared and is ready for 4249 * future writes. 4250 **/ 4251 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 4252 { 4253 struct e1000_nvm_info *nvm = &hw->nvm; 4254 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4255 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 4256 s32 ret_val; 4257 u16 data = 0; 4258 4259 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan"); 4260 4261 ret_val = e1000_update_nvm_checksum_generic(hw); 4262 if (ret_val) 4263 goto out; 4264 4265 if (nvm->type != e1000_nvm_flash_sw) 4266 goto out; 4267 4268 nvm->ops.acquire(hw); 4269 4270 /* We're writing to the opposite bank so if we're on bank 1, 4271 * write to bank 0 etc. We also need to erase the segment that 4272 * is going to be written 4273 */ 4274 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 4275 if (ret_val != E1000_SUCCESS) { 4276 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 4277 bank = 0; 4278 } 4279 4280 if (bank == 0) { 4281 new_bank_offset = nvm->flash_bank_size; 4282 old_bank_offset = 0; 4283 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 4284 if (ret_val) 4285 goto release; 4286 } else { 4287 old_bank_offset = nvm->flash_bank_size; 4288 new_bank_offset = 0; 4289 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 4290 if (ret_val) 4291 goto release; 4292 } 4293 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 4294 if (dev_spec->shadow_ram[i].modified) { 4295 data = dev_spec->shadow_ram[i].value; 4296 } else { 4297 ret_val = e1000_read_flash_word_ich8lan(hw, i + 4298 old_bank_offset, 4299 &data); 4300 if (ret_val) 4301 break; 4302 } 4303 /* If the word is 0x13, then make sure the signature bits 4304 * (15:14) are 11b until the commit has completed. 4305 * This will allow us to write 10b which indicates the 4306 * signature is valid. We want to do this after the write 4307 * has completed so that we don't mark the segment valid 4308 * while the write is still in progress 4309 */ 4310 if (i == E1000_ICH_NVM_SIG_WORD) 4311 data |= E1000_ICH_NVM_SIG_MASK; 4312 4313 /* Convert offset to bytes. */ 4314 act_offset = (i + new_bank_offset) << 1; 4315 4316 usec_delay(100); 4317 4318 /* Write the bytes to the new bank. */ 4319 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4320 act_offset, 4321 (u8)data); 4322 if (ret_val) 4323 break; 4324 4325 usec_delay(100); 4326 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4327 act_offset + 1, 4328 (u8)(data >> 8)); 4329 if (ret_val) 4330 break; 4331 } 4332 4333 /* Don't bother writing the segment valid bits if sector 4334 * programming failed. 4335 */ 4336 if (ret_val) { 4337 DEBUGOUT("Flash commit failed.\n"); 4338 goto release; 4339 } 4340 4341 /* Finally validate the new segment by setting bit 15:14 4342 * to 10b in word 0x13 , this can be done without an 4343 * erase as well since these bits are 11 to start with 4344 * and we need to change bit 14 to 0b 4345 */ 4346 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4347 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 4348 if (ret_val) 4349 goto release; 4350 4351 data &= 0xBFFF; 4352 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1, 4353 (u8)(data >> 8)); 4354 if (ret_val) 4355 goto release; 4356 4357 /* And invalidate the previously valid segment by setting 4358 * its signature word (0x13) high_byte to 0b. This can be 4359 * done without an erase because flash erase sets all bits 4360 * to 1's. We can write 1's to 0's without an erase 4361 */ 4362 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4363 4364 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 4365 4366 if (ret_val) 4367 goto release; 4368 4369 /* Great! Everything worked, we can now clear the cached entries. */ 4370 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 4371 dev_spec->shadow_ram[i].modified = FALSE; 4372 dev_spec->shadow_ram[i].value = 0xFFFF; 4373 } 4374 4375 release: 4376 nvm->ops.release(hw); 4377 4378 /* Reload the EEPROM, or else modifications will not appear 4379 * until after the next adapter reset. 4380 */ 4381 if (!ret_val) { 4382 nvm->ops.reload(hw); 4383 msec_delay(10); 4384 } 4385 4386 out: 4387 if (ret_val) 4388 DEBUGOUT1("NVM update error: %d\n", ret_val); 4389 4390 return ret_val; 4391 } 4392 4393 /** 4394 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 4395 * @hw: pointer to the HW structure 4396 * 4397 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 4398 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 4399 * calculated, in which case we need to calculate the checksum and set bit 6. 4400 **/ 4401 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 4402 { 4403 s32 ret_val; 4404 u16 data; 4405 u16 word; 4406 u16 valid_csum_mask; 4407 4408 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); 4409 4410 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 4411 * the checksum needs to be fixed. This bit is an indication that 4412 * the NVM was prepared by OEM software and did not calculate 4413 * the checksum...a likely scenario. 4414 */ 4415 switch (hw->mac.type) { 4416 case e1000_pch_lpt: 4417 case e1000_pch_spt: 4418 case e1000_pch_cnp: 4419 case e1000_pch_tgp: 4420 case e1000_pch_adp: 4421 case e1000_pch_mtp: 4422 case e1000_pch_lnp: 4423 case e1000_pch_rpl: 4424 word = NVM_COMPAT; 4425 valid_csum_mask = NVM_COMPAT_VALID_CSUM; 4426 break; 4427 default: 4428 word = NVM_FUTURE_INIT_WORD1; 4429 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 4430 break; 4431 } 4432 4433 ret_val = hw->nvm.ops.read(hw, word, 1, &data); 4434 if (ret_val) 4435 return ret_val; 4436 4437 if (!(data & valid_csum_mask)) { 4438 data |= valid_csum_mask; 4439 ret_val = hw->nvm.ops.write(hw, word, 1, &data); 4440 if (ret_val) 4441 return ret_val; 4442 ret_val = hw->nvm.ops.update(hw); 4443 if (ret_val) 4444 return ret_val; 4445 } 4446 4447 return e1000_validate_nvm_checksum_generic(hw); 4448 } 4449 4450 /** 4451 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 4452 * @hw: pointer to the HW structure 4453 * @offset: The offset (in bytes) of the byte/word to read. 4454 * @size: Size of data to read, 1=byte 2=word 4455 * @data: The byte(s) to write to the NVM. 4456 * 4457 * Writes one/two bytes to the NVM using the flash access registers. 4458 **/ 4459 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 4460 u8 size, u16 data) 4461 { 4462 union ich8_hws_flash_status hsfsts; 4463 union ich8_hws_flash_ctrl hsflctl; 4464 u32 flash_linear_addr; 4465 u32 flash_data = 0; 4466 s32 ret_val; 4467 u8 count = 0; 4468 4469 DEBUGFUNC("e1000_write_ich8_data"); 4470 4471 if (hw->mac.type >= e1000_pch_spt) { 4472 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4473 return -E1000_ERR_NVM; 4474 } else { 4475 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4476 return -E1000_ERR_NVM; 4477 } 4478 4479 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4480 hw->nvm.flash_base_addr); 4481 4482 do { 4483 usec_delay(1); 4484 /* Steps */ 4485 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4486 if (ret_val != E1000_SUCCESS) 4487 break; 4488 /* In SPT, This register is in Lan memory space, not 4489 * flash. Therefore, only 32 bit access is supported 4490 */ 4491 if (hw->mac.type >= e1000_pch_spt) 4492 hsflctl.regval = 4493 E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS) >> 16; 4494 else 4495 hsflctl.regval = 4496 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 4497 4498 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 4499 hsflctl.hsf_ctrl.fldbcount = size - 1; 4500 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4501 /* In SPT, This register is in Lan memory space, 4502 * not flash. Therefore, only 32 bit access is 4503 * supported 4504 */ 4505 if (hw->mac.type >= e1000_pch_spt) 4506 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 4507 hsflctl.regval << 16); 4508 else 4509 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 4510 hsflctl.regval); 4511 4512 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 4513 4514 if (size == 1) 4515 flash_data = (u32)data & 0x00FF; 4516 else 4517 flash_data = (u32)data; 4518 4519 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 4520 4521 /* check if FCERR is set to 1 , if set to 1, clear it 4522 * and try the whole sequence a few more times else done 4523 */ 4524 ret_val = 4525 e1000_flash_cycle_ich8lan(hw, 4526 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4527 if (ret_val == E1000_SUCCESS) 4528 break; 4529 4530 /* If we're here, then things are most likely 4531 * completely hosed, but if the error condition 4532 * is detected, it won't hurt to give it another 4533 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4534 */ 4535 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 4536 if (hsfsts.hsf_status.flcerr) 4537 /* Repeat for some time before giving up. */ 4538 continue; 4539 if (!hsfsts.hsf_status.flcdone) { 4540 DEBUGOUT("Timeout error - flash cycle did not complete.\n"); 4541 break; 4542 } 4543 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4544 4545 return ret_val; 4546 } 4547 4548 /** 4549 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM 4550 * @hw: pointer to the HW structure 4551 * @offset: The offset (in bytes) of the dwords to read. 4552 * @data: The 4 bytes to write to the NVM. 4553 * 4554 * Writes one/two/four bytes to the NVM using the flash access registers. 4555 **/ 4556 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 4557 u32 data) 4558 { 4559 union ich8_hws_flash_status hsfsts; 4560 union ich8_hws_flash_ctrl hsflctl; 4561 u32 flash_linear_addr; 4562 s32 ret_val; 4563 u8 count = 0; 4564 4565 DEBUGFUNC("e1000_write_flash_data32_ich8lan"); 4566 4567 if (hw->mac.type >= e1000_pch_spt) { 4568 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 4569 return -E1000_ERR_NVM; 4570 } 4571 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4572 hw->nvm.flash_base_addr); 4573 do { 4574 usec_delay(1); 4575 /* Steps */ 4576 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4577 if (ret_val != E1000_SUCCESS) 4578 break; 4579 4580 /* In SPT, This register is in Lan memory space, not 4581 * flash. Therefore, only 32 bit access is supported 4582 */ 4583 if (hw->mac.type >= e1000_pch_spt) 4584 hsflctl.regval = E1000_READ_FLASH_REG(hw, 4585 ICH_FLASH_HSFSTS) 4586 >> 16; 4587 else 4588 hsflctl.regval = E1000_READ_FLASH_REG16(hw, 4589 ICH_FLASH_HSFCTL); 4590 4591 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 4592 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4593 4594 /* In SPT, This register is in Lan memory space, 4595 * not flash. Therefore, only 32 bit access is 4596 * supported 4597 */ 4598 if (hw->mac.type >= e1000_pch_spt) 4599 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 4600 hsflctl.regval << 16); 4601 else 4602 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 4603 hsflctl.regval); 4604 4605 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 4606 4607 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data); 4608 4609 /* check if FCERR is set to 1 , if set to 1, clear it 4610 * and try the whole sequence a few more times else done 4611 */ 4612 ret_val = e1000_flash_cycle_ich8lan(hw, 4613 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4614 4615 if (ret_val == E1000_SUCCESS) 4616 break; 4617 4618 /* If we're here, then things are most likely 4619 * completely hosed, but if the error condition 4620 * is detected, it won't hurt to give it another 4621 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4622 */ 4623 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 4624 4625 if (hsfsts.hsf_status.flcerr) 4626 /* Repeat for some time before giving up. */ 4627 continue; 4628 if (!hsfsts.hsf_status.flcdone) { 4629 DEBUGOUT("Timeout error - flash cycle did not complete.\n"); 4630 break; 4631 } 4632 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4633 4634 return ret_val; 4635 } 4636 4637 /** 4638 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 4639 * @hw: pointer to the HW structure 4640 * @offset: The index of the byte to read. 4641 * @data: The byte to write to the NVM. 4642 * 4643 * Writes a single byte to the NVM using the flash access registers. 4644 **/ 4645 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 4646 u8 data) 4647 { 4648 u16 word = (u16)data; 4649 4650 DEBUGFUNC("e1000_write_flash_byte_ich8lan"); 4651 4652 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 4653 } 4654 4655 /** 4656 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM 4657 * @hw: pointer to the HW structure 4658 * @offset: The offset of the word to write. 4659 * @dword: The dword to write to the NVM. 4660 * 4661 * Writes a single dword to the NVM using the flash access registers. 4662 * Goes through a retry algorithm before giving up. 4663 **/ 4664 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 4665 u32 offset, u32 dword) 4666 { 4667 s32 ret_val; 4668 u16 program_retries; 4669 4670 DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan"); 4671 4672 /* Must convert word offset into bytes. */ 4673 offset <<= 1; 4674 4675 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4676 4677 if (!ret_val) 4678 return ret_val; 4679 for (program_retries = 0; program_retries < 100; program_retries++) { 4680 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset); 4681 usec_delay(100); 4682 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4683 if (ret_val == E1000_SUCCESS) 4684 break; 4685 } 4686 if (program_retries == 100) 4687 return -E1000_ERR_NVM; 4688 4689 return E1000_SUCCESS; 4690 } 4691 4692 /** 4693 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 4694 * @hw: pointer to the HW structure 4695 * @offset: The offset of the byte to write. 4696 * @byte: The byte to write to the NVM. 4697 * 4698 * Writes a single byte to the NVM using the flash access registers. 4699 * Goes through a retry algorithm before giving up. 4700 **/ 4701 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 4702 u32 offset, u8 byte) 4703 { 4704 s32 ret_val; 4705 u16 program_retries; 4706 4707 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); 4708 4709 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4710 if (!ret_val) 4711 return ret_val; 4712 4713 for (program_retries = 0; program_retries < 100; program_retries++) { 4714 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); 4715 usec_delay(100); 4716 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4717 if (ret_val == E1000_SUCCESS) 4718 break; 4719 } 4720 if (program_retries == 100) 4721 return -E1000_ERR_NVM; 4722 4723 return E1000_SUCCESS; 4724 } 4725 4726 /** 4727 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 4728 * @hw: pointer to the HW structure 4729 * @bank: 0 for first bank, 1 for second bank, etc. 4730 * 4731 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 4732 * bank N is 4096 * N + flash_reg_addr. 4733 **/ 4734 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 4735 { 4736 struct e1000_nvm_info *nvm = &hw->nvm; 4737 union ich8_hws_flash_status hsfsts; 4738 union ich8_hws_flash_ctrl hsflctl; 4739 u32 flash_linear_addr; 4740 /* bank size is in 16bit words - adjust to bytes */ 4741 u32 flash_bank_size = nvm->flash_bank_size * 2; 4742 s32 ret_val; 4743 s32 count = 0; 4744 s32 j, iteration, sector_size; 4745 4746 DEBUGFUNC("e1000_erase_flash_bank_ich8lan"); 4747 4748 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 4749 4750 /* Determine HW Sector size: Read BERASE bits of hw flash status 4751 * register 4752 * 00: The Hw sector is 256 bytes, hence we need to erase 16 4753 * consecutive sectors. The start index for the nth Hw sector 4754 * can be calculated as = bank * 4096 + n * 256 4755 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 4756 * The start index for the nth Hw sector can be calculated 4757 * as = bank * 4096 4758 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 4759 * (ich9 only, otherwise error condition) 4760 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 4761 */ 4762 switch (hsfsts.hsf_status.berasesz) { 4763 case 0: 4764 /* Hw sector size 256 */ 4765 sector_size = ICH_FLASH_SEG_SIZE_256; 4766 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 4767 break; 4768 case 1: 4769 sector_size = ICH_FLASH_SEG_SIZE_4K; 4770 iteration = 1; 4771 break; 4772 case 2: 4773 sector_size = ICH_FLASH_SEG_SIZE_8K; 4774 iteration = 1; 4775 break; 4776 case 3: 4777 sector_size = ICH_FLASH_SEG_SIZE_64K; 4778 iteration = 1; 4779 break; 4780 default: 4781 return -E1000_ERR_NVM; 4782 } 4783 4784 /* Start with the base address, then add the sector offset. */ 4785 flash_linear_addr = hw->nvm.flash_base_addr; 4786 flash_linear_addr += (bank) ? flash_bank_size : 0; 4787 4788 for (j = 0; j < iteration; j++) { 4789 do { 4790 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; 4791 4792 /* Steps */ 4793 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4794 if (ret_val) 4795 return ret_val; 4796 4797 /* Write a value 11 (block Erase) in Flash 4798 * Cycle field in hw flash control 4799 */ 4800 if (hw->mac.type >= e1000_pch_spt) 4801 hsflctl.regval = 4802 E1000_READ_FLASH_REG(hw, 4803 ICH_FLASH_HSFSTS)>>16; 4804 else 4805 hsflctl.regval = 4806 E1000_READ_FLASH_REG16(hw, 4807 ICH_FLASH_HSFCTL); 4808 4809 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 4810 if (hw->mac.type >= e1000_pch_spt) 4811 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 4812 hsflctl.regval << 16); 4813 else 4814 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 4815 hsflctl.regval); 4816 4817 /* Write the last 24 bits of an index within the 4818 * block into Flash Linear address field in Flash 4819 * Address. 4820 */ 4821 flash_linear_addr += (j * sector_size); 4822 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, 4823 flash_linear_addr); 4824 4825 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); 4826 if (ret_val == E1000_SUCCESS) 4827 break; 4828 4829 /* Check if FCERR is set to 1. If 1, 4830 * clear it and try the whole sequence 4831 * a few more times else Done 4832 */ 4833 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 4834 ICH_FLASH_HSFSTS); 4835 if (hsfsts.hsf_status.flcerr) 4836 /* repeat for some time before giving up */ 4837 continue; 4838 else if (!hsfsts.hsf_status.flcdone) 4839 return ret_val; 4840 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 4841 } 4842 4843 return E1000_SUCCESS; 4844 } 4845 4846 /** 4847 * e1000_valid_led_default_ich8lan - Set the default LED settings 4848 * @hw: pointer to the HW structure 4849 * @data: Pointer to the LED settings 4850 * 4851 * Reads the LED default settings from the NVM to data. If the NVM LED 4852 * settings is all 0's or F's, set the LED default to a valid LED default 4853 * setting. 4854 **/ 4855 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 4856 { 4857 s32 ret_val; 4858 4859 DEBUGFUNC("e1000_valid_led_default_ich8lan"); 4860 4861 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 4862 if (ret_val) { 4863 DEBUGOUT("NVM Read Error\n"); 4864 return ret_val; 4865 } 4866 4867 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 4868 *data = ID_LED_DEFAULT_ICH8LAN; 4869 4870 return E1000_SUCCESS; 4871 } 4872 4873 /** 4874 * e1000_id_led_init_pchlan - store LED configurations 4875 * @hw: pointer to the HW structure 4876 * 4877 * PCH does not control LEDs via the LEDCTL register, rather it uses 4878 * the PHY LED configuration register. 4879 * 4880 * PCH also does not have an "always on" or "always off" mode which 4881 * complicates the ID feature. Instead of using the "on" mode to indicate 4882 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()), 4883 * use "link_up" mode. The LEDs will still ID on request if there is no 4884 * link based on logic in e1000_led_[on|off]_pchlan(). 4885 **/ 4886 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 4887 { 4888 struct e1000_mac_info *mac = &hw->mac; 4889 s32 ret_val; 4890 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 4891 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 4892 u16 data, i, temp, shift; 4893 4894 DEBUGFUNC("e1000_id_led_init_pchlan"); 4895 4896 /* Get default ID LED modes */ 4897 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 4898 if (ret_val) 4899 return ret_val; 4900 4901 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 4902 mac->ledctl_mode1 = mac->ledctl_default; 4903 mac->ledctl_mode2 = mac->ledctl_default; 4904 4905 for (i = 0; i < 4; i++) { 4906 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 4907 shift = (i * 5); 4908 switch (temp) { 4909 case ID_LED_ON1_DEF2: 4910 case ID_LED_ON1_ON2: 4911 case ID_LED_ON1_OFF2: 4912 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4913 mac->ledctl_mode1 |= (ledctl_on << shift); 4914 break; 4915 case ID_LED_OFF1_DEF2: 4916 case ID_LED_OFF1_ON2: 4917 case ID_LED_OFF1_OFF2: 4918 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4919 mac->ledctl_mode1 |= (ledctl_off << shift); 4920 break; 4921 default: 4922 /* Do nothing */ 4923 break; 4924 } 4925 switch (temp) { 4926 case ID_LED_DEF1_ON2: 4927 case ID_LED_ON1_ON2: 4928 case ID_LED_OFF1_ON2: 4929 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4930 mac->ledctl_mode2 |= (ledctl_on << shift); 4931 break; 4932 case ID_LED_DEF1_OFF2: 4933 case ID_LED_ON1_OFF2: 4934 case ID_LED_OFF1_OFF2: 4935 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4936 mac->ledctl_mode2 |= (ledctl_off << shift); 4937 break; 4938 default: 4939 /* Do nothing */ 4940 break; 4941 } 4942 } 4943 4944 return E1000_SUCCESS; 4945 } 4946 4947 /** 4948 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 4949 * @hw: pointer to the HW structure 4950 * 4951 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 4952 * register, so the bus width is hard coded. 4953 **/ 4954 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 4955 { 4956 struct e1000_bus_info *bus = &hw->bus; 4957 s32 ret_val; 4958 4959 DEBUGFUNC("e1000_get_bus_info_ich8lan"); 4960 4961 ret_val = e1000_get_bus_info_pcie_generic(hw); 4962 4963 /* ICH devices are "PCI Express"-ish. They have 4964 * a configuration space, but do not contain 4965 * PCI Express Capability registers, so bus width 4966 * must be hardcoded. 4967 */ 4968 if (bus->width == e1000_bus_width_unknown) 4969 bus->width = e1000_bus_width_pcie_x1; 4970 4971 return ret_val; 4972 } 4973 4974 /** 4975 * e1000_reset_hw_ich8lan - Reset the hardware 4976 * @hw: pointer to the HW structure 4977 * 4978 * Does a full reset of the hardware which includes a reset of the PHY and 4979 * MAC. 4980 **/ 4981 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 4982 { 4983 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4984 u16 kum_cfg; 4985 u32 ctrl, reg; 4986 s32 ret_val; 4987 4988 DEBUGFUNC("e1000_reset_hw_ich8lan"); 4989 4990 /* Prevent the PCI-E bus from sticking if there is no TLP connection 4991 * on the last TLP read/write transaction when MAC is reset. 4992 */ 4993 ret_val = e1000_disable_pcie_master_generic(hw); 4994 if (ret_val) 4995 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 4996 4997 DEBUGOUT("Masking off all interrupts\n"); 4998 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4999 5000 /* Disable the Transmit and Receive units. Then delay to allow 5001 * any pending transactions to complete before we hit the MAC 5002 * with the global reset. 5003 */ 5004 E1000_WRITE_REG(hw, E1000_RCTL, 0); 5005 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 5006 E1000_WRITE_FLUSH(hw); 5007 5008 msec_delay(10); 5009 5010 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 5011 if (hw->mac.type == e1000_ich8lan) { 5012 /* Set Tx and Rx buffer allocation to 8k apiece. */ 5013 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); 5014 /* Set Packet Buffer Size to 16k. */ 5015 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); 5016 } 5017 5018 if (hw->mac.type == e1000_pchlan) { 5019 /* Save the NVM K1 bit setting*/ 5020 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 5021 if (ret_val) 5022 return ret_val; 5023 5024 if (kum_cfg & E1000_NVM_K1_ENABLE) 5025 dev_spec->nvm_k1_enabled = TRUE; 5026 else 5027 dev_spec->nvm_k1_enabled = FALSE; 5028 } 5029 5030 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5031 5032 if (!hw->phy.ops.check_reset_block(hw)) { 5033 /* Full-chip reset requires MAC and PHY reset at the same 5034 * time to make sure the interface between MAC and the 5035 * external PHY is reset. 5036 */ 5037 ctrl |= E1000_CTRL_PHY_RST; 5038 5039 /* Gate automatic PHY configuration by hardware on 5040 * non-managed 82579 5041 */ 5042 if ((hw->mac.type == e1000_pch2lan) && 5043 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) 5044 e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 5045 } 5046 ret_val = e1000_acquire_swflag_ich8lan(hw); 5047 DEBUGOUT("Issuing a global reset to ich8lan\n"); 5048 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); 5049 /* cannot issue a flush here because it hangs the hardware */ 5050 msec_delay(20); 5051 5052 /* Set Phy Config Counter to 50msec */ 5053 if (hw->mac.type == e1000_pch2lan) { 5054 reg = E1000_READ_REG(hw, E1000_FEXTNVM3); 5055 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 5056 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 5057 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg); 5058 } 5059 5060 if (!ret_val) 5061 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 5062 5063 if (ctrl & E1000_CTRL_PHY_RST) { 5064 ret_val = hw->phy.ops.get_cfg_done(hw); 5065 if (ret_val) 5066 return ret_val; 5067 5068 ret_val = e1000_post_phy_reset_ich8lan(hw); 5069 if (ret_val) 5070 return ret_val; 5071 } 5072 5073 /* For PCH, this write will make sure that any noise 5074 * will be detected as a CRC error and be dropped rather than show up 5075 * as a bad packet to the DMA engine. 5076 */ 5077 if (hw->mac.type == e1000_pchlan) 5078 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565); 5079 5080 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 5081 E1000_READ_REG(hw, E1000_ICR); 5082 5083 reg = E1000_READ_REG(hw, E1000_KABGTXD); 5084 reg |= E1000_KABGTXD_BGSQLBIAS; 5085 E1000_WRITE_REG(hw, E1000_KABGTXD, reg); 5086 5087 return E1000_SUCCESS; 5088 } 5089 5090 /** 5091 * e1000_init_hw_ich8lan - Initialize the hardware 5092 * @hw: pointer to the HW structure 5093 * 5094 * Prepares the hardware for transmit and receive by doing the following: 5095 * - initialize hardware bits 5096 * - initialize LED identification 5097 * - setup receive address registers 5098 * - setup flow control 5099 * - setup transmit descriptors 5100 * - clear statistics 5101 **/ 5102 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 5103 { 5104 struct e1000_mac_info *mac = &hw->mac; 5105 u32 ctrl_ext, txdctl, snoop; 5106 s32 ret_val; 5107 u16 i; 5108 5109 DEBUGFUNC("e1000_init_hw_ich8lan"); 5110 5111 e1000_initialize_hw_bits_ich8lan(hw); 5112 5113 /* Initialize identification LED */ 5114 ret_val = mac->ops.id_led_init(hw); 5115 /* An error is not fatal and we should not stop init due to this */ 5116 if (ret_val) 5117 DEBUGOUT("Error initializing identification LED\n"); 5118 5119 /* Setup the receive address. */ 5120 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 5121 5122 /* Zero out the Multicast HASH table */ 5123 DEBUGOUT("Zeroing the MTA\n"); 5124 for (i = 0; i < mac->mta_reg_count; i++) 5125 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 5126 5127 /* The 82578 Rx buffer will stall if wakeup is enabled in host and 5128 * the ME. Disable wakeup by clearing the host wakeup bit. 5129 * Reset the phy after disabling host wakeup to reset the Rx buffer. 5130 */ 5131 if (hw->phy.type == e1000_phy_82578) { 5132 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i); 5133 i &= ~BM_WUC_HOST_WU_BIT; 5134 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i); 5135 ret_val = e1000_phy_hw_reset_ich8lan(hw); 5136 if (ret_val) 5137 return ret_val; 5138 } 5139 5140 /* Setup link and flow control */ 5141 ret_val = mac->ops.setup_link(hw); 5142 5143 /* Set the transmit descriptor write-back policy for both queues */ 5144 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 5145 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 5146 E1000_TXDCTL_FULL_TX_DESC_WB); 5147 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 5148 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 5149 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 5150 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1)); 5151 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 5152 E1000_TXDCTL_FULL_TX_DESC_WB); 5153 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 5154 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 5155 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); 5156 5157 /* ICH8 has opposite polarity of no_snoop bits. 5158 * By default, we should use snoop behavior. 5159 */ 5160 if (mac->type == e1000_ich8lan) 5161 snoop = PCIE_ICH8_SNOOP_ALL; 5162 else 5163 snoop = (u32) ~(PCIE_NO_SNOOP_ALL); 5164 e1000_set_pcie_no_snoop_generic(hw, snoop); 5165 5166 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5167 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 5168 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5169 5170 /* Clear all of the statistics registers (clear on read). It is 5171 * important that we do this after we have tried to establish link 5172 * because the symbol error count will increment wildly if there 5173 * is no link. 5174 */ 5175 e1000_clear_hw_cntrs_ich8lan(hw); 5176 5177 return ret_val; 5178 } 5179 5180 /** 5181 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 5182 * @hw: pointer to the HW structure 5183 * 5184 * Sets/Clears required hardware bits necessary for correctly setting up the 5185 * hardware for transmit and receive. 5186 **/ 5187 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 5188 { 5189 u32 reg; 5190 5191 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan"); 5192 5193 /* Extended Device Control */ 5194 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 5195 reg |= (1 << 22); 5196 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 5197 if (hw->mac.type >= e1000_pchlan) 5198 reg |= E1000_CTRL_EXT_PHYPDEN; 5199 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 5200 5201 /* Transmit Descriptor Control 0 */ 5202 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 5203 reg |= (1 << 22); 5204 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 5205 5206 /* Transmit Descriptor Control 1 */ 5207 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 5208 reg |= (1 << 22); 5209 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 5210 5211 /* Transmit Arbitration Control 0 */ 5212 reg = E1000_READ_REG(hw, E1000_TARC(0)); 5213 if (hw->mac.type == e1000_ich8lan) 5214 reg |= (1 << 28) | (1 << 29); 5215 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 5216 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 5217 5218 /* Transmit Arbitration Control 1 */ 5219 reg = E1000_READ_REG(hw, E1000_TARC(1)); 5220 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 5221 reg &= ~(1 << 28); 5222 else 5223 reg |= (1 << 28); 5224 reg |= (1 << 24) | (1 << 26) | (1 << 30); 5225 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 5226 5227 /* Device Status */ 5228 if (hw->mac.type == e1000_ich8lan) { 5229 reg = E1000_READ_REG(hw, E1000_STATUS); 5230 reg &= ~(1UL << 31); 5231 E1000_WRITE_REG(hw, E1000_STATUS, reg); 5232 } 5233 5234 /* work-around descriptor data corruption issue during nfs v2 udp 5235 * traffic, just disable the nfs filtering capability 5236 */ 5237 reg = E1000_READ_REG(hw, E1000_RFCTL); 5238 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 5239 5240 /* Disable IPv6 extension header parsing because some malformed 5241 * IPv6 headers can hang the Rx. 5242 */ 5243 if (hw->mac.type == e1000_ich8lan) 5244 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 5245 E1000_WRITE_REG(hw, E1000_RFCTL, reg); 5246 5247 /* Enable ECC on Lynxpoint */ 5248 if (hw->mac.type >= e1000_pch_lpt) { 5249 reg = E1000_READ_REG(hw, E1000_PBECCSTS); 5250 reg |= E1000_PBECCSTS_ECC_ENABLE; 5251 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg); 5252 5253 reg = E1000_READ_REG(hw, E1000_CTRL); 5254 reg |= E1000_CTRL_MEHE; 5255 E1000_WRITE_REG(hw, E1000_CTRL, reg); 5256 } 5257 5258 return; 5259 } 5260 5261 /** 5262 * e1000_setup_link_ich8lan - Setup flow control and link settings 5263 * @hw: pointer to the HW structure 5264 * 5265 * Determines which flow control settings to use, then configures flow 5266 * control. Calls the appropriate media-specific link configuration 5267 * function. Assuming the adapter has a valid link partner, a valid link 5268 * should be established. Assumes the hardware has previously been reset 5269 * and the transmitter and receiver are not enabled. 5270 **/ 5271 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 5272 { 5273 s32 ret_val; 5274 5275 DEBUGFUNC("e1000_setup_link_ich8lan"); 5276 5277 if (hw->phy.ops.check_reset_block(hw)) 5278 return E1000_SUCCESS; 5279 5280 /* ICH parts do not have a word in the NVM to determine 5281 * the default flow control setting, so we explicitly 5282 * set it to full. 5283 */ 5284 if (hw->fc.requested_mode == e1000_fc_default) 5285 hw->fc.requested_mode = e1000_fc_full; 5286 5287 /* Save off the requested flow control mode for use later. Depending 5288 * on the link partner's capabilities, we may or may not use this mode. 5289 */ 5290 hw->fc.current_mode = hw->fc.requested_mode; 5291 5292 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 5293 hw->fc.current_mode); 5294 5295 /* Continue to configure the copper link. */ 5296 ret_val = hw->mac.ops.setup_physical_interface(hw); 5297 if (ret_val) 5298 return ret_val; 5299 5300 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 5301 if ((hw->phy.type == e1000_phy_82578) || 5302 (hw->phy.type == e1000_phy_82579) || 5303 (hw->phy.type == e1000_phy_i217) || 5304 (hw->phy.type == e1000_phy_82577)) { 5305 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time); 5306 5307 ret_val = hw->phy.ops.write_reg(hw, 5308 PHY_REG(BM_PORT_CTRL_PAGE, 27), 5309 hw->fc.pause_time); 5310 if (ret_val) 5311 return ret_val; 5312 } 5313 5314 return e1000_set_fc_watermarks_generic(hw); 5315 } 5316 5317 /** 5318 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 5319 * @hw: pointer to the HW structure 5320 * 5321 * Configures the kumeran interface to the PHY to wait the appropriate time 5322 * when polling the PHY, then call the generic setup_copper_link to finish 5323 * configuring the copper link. 5324 **/ 5325 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 5326 { 5327 u32 ctrl; 5328 s32 ret_val; 5329 u16 reg_data; 5330 5331 DEBUGFUNC("e1000_setup_copper_link_ich8lan"); 5332 5333 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5334 ctrl |= E1000_CTRL_SLU; 5335 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5336 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5337 5338 /* Set the mac to wait the maximum time between each iteration 5339 * and increase the max iterations when polling the phy; 5340 * this fixes erroneous timeouts at 10Mbps. 5341 */ 5342 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 5343 0xFFFF); 5344 if (ret_val) 5345 return ret_val; 5346 ret_val = e1000_read_kmrn_reg_generic(hw, 5347 E1000_KMRNCTRLSTA_INBAND_PARAM, 5348 ®_data); 5349 if (ret_val) 5350 return ret_val; 5351 reg_data |= 0x3F; 5352 ret_val = e1000_write_kmrn_reg_generic(hw, 5353 E1000_KMRNCTRLSTA_INBAND_PARAM, 5354 reg_data); 5355 if (ret_val) 5356 return ret_val; 5357 5358 switch (hw->phy.type) { 5359 case e1000_phy_igp_3: 5360 ret_val = e1000_copper_link_setup_igp(hw); 5361 if (ret_val) 5362 return ret_val; 5363 break; 5364 case e1000_phy_bm: 5365 case e1000_phy_82578: 5366 ret_val = e1000_copper_link_setup_m88(hw); 5367 if (ret_val) 5368 return ret_val; 5369 break; 5370 case e1000_phy_82577: 5371 case e1000_phy_82579: 5372 ret_val = e1000_copper_link_setup_82577(hw); 5373 if (ret_val) 5374 return ret_val; 5375 break; 5376 case e1000_phy_ife: 5377 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, 5378 ®_data); 5379 if (ret_val) 5380 return ret_val; 5381 5382 reg_data &= ~IFE_PMC_AUTO_MDIX; 5383 5384 switch (hw->phy.mdix) { 5385 case 1: 5386 reg_data &= ~IFE_PMC_FORCE_MDIX; 5387 break; 5388 case 2: 5389 reg_data |= IFE_PMC_FORCE_MDIX; 5390 break; 5391 case 0: 5392 default: 5393 reg_data |= IFE_PMC_AUTO_MDIX; 5394 break; 5395 } 5396 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, 5397 reg_data); 5398 if (ret_val) 5399 return ret_val; 5400 break; 5401 default: 5402 break; 5403 } 5404 5405 return e1000_setup_copper_link_generic(hw); 5406 } 5407 5408 /** 5409 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface 5410 * @hw: pointer to the HW structure 5411 * 5412 * Calls the PHY specific link setup function and then calls the 5413 * generic setup_copper_link to finish configuring the link for 5414 * Lynxpoint PCH devices 5415 **/ 5416 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) 5417 { 5418 u32 ctrl; 5419 s32 ret_val; 5420 5421 DEBUGFUNC("e1000_setup_copper_link_pch_lpt"); 5422 5423 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5424 ctrl |= E1000_CTRL_SLU; 5425 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5426 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5427 5428 ret_val = e1000_copper_link_setup_82577(hw); 5429 if (ret_val) 5430 return ret_val; 5431 5432 return e1000_setup_copper_link_generic(hw); 5433 } 5434 5435 /** 5436 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 5437 * @hw: pointer to the HW structure 5438 * @speed: pointer to store current link speed 5439 * @duplex: pointer to store the current link duplex 5440 * 5441 * Calls the generic get_speed_and_duplex to retrieve the current link 5442 * information and then calls the Kumeran lock loss workaround for links at 5443 * gigabit speeds. 5444 **/ 5445 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 5446 u16 *duplex) 5447 { 5448 s32 ret_val; 5449 5450 DEBUGFUNC("e1000_get_link_up_info_ich8lan"); 5451 5452 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 5453 if (ret_val) 5454 return ret_val; 5455 5456 if ((hw->mac.type == e1000_ich8lan) && 5457 (hw->phy.type == e1000_phy_igp_3) && 5458 (*speed == SPEED_1000)) { 5459 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 5460 } 5461 5462 return ret_val; 5463 } 5464 5465 /** 5466 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 5467 * @hw: pointer to the HW structure 5468 * 5469 * Work-around for 82566 Kumeran PCS lock loss: 5470 * On link status change (i.e. PCI reset, speed change) and link is up and 5471 * speed is gigabit- 5472 * 0) if workaround is optionally disabled do nothing 5473 * 1) wait 1ms for Kumeran link to come up 5474 * 2) check Kumeran Diagnostic register PCS lock loss bit 5475 * 3) if not set the link is locked (all is good), otherwise... 5476 * 4) reset the PHY 5477 * 5) repeat up to 10 times 5478 * Note: this is only called for IGP3 copper when speed is 1gb. 5479 **/ 5480 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 5481 { 5482 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5483 u32 phy_ctrl; 5484 s32 ret_val; 5485 u16 i, data; 5486 bool link; 5487 5488 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); 5489 5490 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 5491 return E1000_SUCCESS; 5492 5493 /* Make sure link is up before proceeding. If not just return. 5494 * Attempting this while link is negotiating fouled up link 5495 * stability 5496 */ 5497 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 5498 if (!link) 5499 return E1000_SUCCESS; 5500 5501 for (i = 0; i < 10; i++) { 5502 /* read once to clear */ 5503 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 5504 if (ret_val) 5505 return ret_val; 5506 /* and again to get new status */ 5507 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 5508 if (ret_val) 5509 return ret_val; 5510 5511 /* check for PCS lock */ 5512 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5513 return E1000_SUCCESS; 5514 5515 /* Issue PHY reset */ 5516 hw->phy.ops.reset(hw); 5517 msec_delay_irq(5); 5518 } 5519 /* Disable GigE link negotiation */ 5520 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 5521 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 5522 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5523 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 5524 5525 /* Call gig speed drop workaround on Gig disable before accessing 5526 * any PHY registers 5527 */ 5528 e1000_gig_downshift_workaround_ich8lan(hw); 5529 5530 /* unable to acquire PCS lock */ 5531 return -E1000_ERR_PHY; 5532 } 5533 5534 /** 5535 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 5536 * @hw: pointer to the HW structure 5537 * @state: boolean value used to set the current Kumeran workaround state 5538 * 5539 * If ICH8, set the current Kumeran workaround state (enabled - TRUE 5540 * /disabled - FALSE). 5541 **/ 5542 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 5543 bool state) 5544 { 5545 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5546 5547 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan"); 5548 5549 if (hw->mac.type != e1000_ich8lan) { 5550 DEBUGOUT("Workaround applies to ICH8 only.\n"); 5551 return; 5552 } 5553 5554 dev_spec->kmrn_lock_loss_workaround_enabled = state; 5555 5556 return; 5557 } 5558 5559 /** 5560 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 5561 * @hw: pointer to the HW structure 5562 * 5563 * Workaround for 82566 power-down on D3 entry: 5564 * 1) disable gigabit link 5565 * 2) write VR power-down enable 5566 * 3) read it back 5567 * Continue if successful, else issue LCD reset and repeat 5568 **/ 5569 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 5570 { 5571 u32 reg; 5572 u16 data; 5573 u8 retry = 0; 5574 5575 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); 5576 5577 if (hw->phy.type != e1000_phy_igp_3) 5578 return; 5579 5580 /* Try the workaround twice (if needed) */ 5581 do { 5582 /* Disable link */ 5583 reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 5584 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 5585 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5586 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); 5587 5588 /* Call gig speed drop workaround on Gig disable before 5589 * accessing any PHY registers 5590 */ 5591 if (hw->mac.type == e1000_ich8lan) 5592 e1000_gig_downshift_workaround_ich8lan(hw); 5593 5594 /* Write VR power-down enable */ 5595 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 5596 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5597 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL, 5598 data | IGP3_VR_CTRL_MODE_SHUTDOWN); 5599 5600 /* Read it back and test */ 5601 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 5602 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5603 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 5604 break; 5605 5606 /* Issue PHY reset and repeat at most one more time */ 5607 reg = E1000_READ_REG(hw, E1000_CTRL); 5608 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); 5609 retry++; 5610 } while (retry); 5611 } 5612 5613 /** 5614 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working 5615 * @hw: pointer to the HW structure 5616 * 5617 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 5618 * LPLU, Gig disable, MDIC PHY reset): 5619 * 1) Set Kumeran Near-end loopback 5620 * 2) Clear Kumeran Near-end loopback 5621 * Should only be called for ICH8[m] devices with any 1G Phy. 5622 **/ 5623 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 5624 { 5625 s32 ret_val; 5626 u16 reg_data; 5627 5628 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); 5629 5630 if ((hw->mac.type != e1000_ich8lan) || 5631 (hw->phy.type == e1000_phy_ife)) 5632 return; 5633 5634 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5635 ®_data); 5636 if (ret_val) 5637 return; 5638 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 5639 ret_val = e1000_write_kmrn_reg_generic(hw, 5640 E1000_KMRNCTRLSTA_DIAG_OFFSET, 5641 reg_data); 5642 if (ret_val) 5643 return; 5644 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 5645 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5646 reg_data); 5647 } 5648 5649 /** 5650 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 5651 * @hw: pointer to the HW structure 5652 * 5653 * During S0 to Sx transition, it is possible the link remains at gig 5654 * instead of negotiating to a lower speed. Before going to Sx, set 5655 * 'Gig Disable' to force link speed negotiation to a lower speed based on 5656 * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 5657 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 5658 * needs to be written. 5659 * Parts that support (and are linked to a partner which support) EEE in 5660 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 5661 * than 10Mbps w/o EEE. 5662 **/ 5663 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 5664 { 5665 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5666 u32 phy_ctrl; 5667 s32 ret_val; 5668 5669 DEBUGFUNC("e1000_suspend_workarounds_ich8lan"); 5670 5671 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 5672 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 5673 5674 if (hw->phy.type == e1000_phy_i217) { 5675 u16 phy_reg, device_id = hw->device_id; 5676 5677 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 5678 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 5679 (device_id == E1000_DEV_ID_PCH_I218_LM3) || 5680 (device_id == E1000_DEV_ID_PCH_I218_V3) || 5681 (hw->mac.type >= e1000_pch_spt)) { 5682 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); 5683 5684 E1000_WRITE_REG(hw, E1000_FEXTNVM6, 5685 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 5686 } 5687 5688 ret_val = hw->phy.ops.acquire(hw); 5689 if (ret_val) 5690 goto out; 5691 5692 if (!dev_spec->eee_disable) { 5693 u16 eee_advert; 5694 5695 ret_val = 5696 e1000_read_emi_reg_locked(hw, 5697 I217_EEE_ADVERTISEMENT, 5698 &eee_advert); 5699 if (ret_val) 5700 goto release; 5701 5702 /* Disable LPLU if both link partners support 100BaseT 5703 * EEE and 100Full is advertised on both ends of the 5704 * link, and enable Auto Enable LPI since there will 5705 * be no driver to enable LPI while in Sx. 5706 */ 5707 if ((eee_advert & I82579_EEE_100_SUPPORTED) && 5708 (dev_spec->eee_lp_ability & 5709 I82579_EEE_100_SUPPORTED) && 5710 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { 5711 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 5712 E1000_PHY_CTRL_NOND0A_LPLU); 5713 5714 /* Set Auto Enable LPI after link up */ 5715 hw->phy.ops.read_reg_locked(hw, 5716 I217_LPI_GPIO_CTRL, 5717 &phy_reg); 5718 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5719 hw->phy.ops.write_reg_locked(hw, 5720 I217_LPI_GPIO_CTRL, 5721 phy_reg); 5722 } 5723 } 5724 5725 /* For i217 Intel Rapid Start Technology support, 5726 * when the system is going into Sx and no manageability engine 5727 * is present, the driver must configure proxy to reset only on 5728 * power good. LPI (Low Power Idle) state must also reset only 5729 * on power good, as well as the MTA (Multicast table array). 5730 * The SMBus release must also be disabled on LCD reset. 5731 */ 5732 if (!(E1000_READ_REG(hw, E1000_FWSM) & 5733 E1000_ICH_FWSM_FW_VALID)) { 5734 /* Enable proxy to reset only on power good. */ 5735 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL, 5736 &phy_reg); 5737 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 5738 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 5739 phy_reg); 5740 5741 /* Set bit enable LPI (EEE) to reset only on 5742 * power good. 5743 */ 5744 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg); 5745 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 5746 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg); 5747 5748 /* Disable the SMB release on LCD reset. */ 5749 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg); 5750 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 5751 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); 5752 } 5753 5754 /* Enable MTA to reset for Intel Rapid Start Technology 5755 * Support 5756 */ 5757 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg); 5758 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 5759 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); 5760 5761 release: 5762 hw->phy.ops.release(hw); 5763 } 5764 out: 5765 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 5766 5767 if (hw->mac.type == e1000_ich8lan) 5768 e1000_gig_downshift_workaround_ich8lan(hw); 5769 5770 if (hw->mac.type >= e1000_pchlan) { 5771 e1000_oem_bits_config_ich8lan(hw, FALSE); 5772 5773 /* Reset PHY to activate OEM bits on 82577/8 */ 5774 if (hw->mac.type == e1000_pchlan) 5775 e1000_phy_hw_reset_generic(hw); 5776 5777 ret_val = hw->phy.ops.acquire(hw); 5778 if (ret_val) 5779 return; 5780 e1000_write_smbus_addr(hw); 5781 hw->phy.ops.release(hw); 5782 } 5783 5784 return; 5785 } 5786 5787 /** 5788 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 5789 * @hw: pointer to the HW structure 5790 * 5791 * During Sx to S0 transitions on non-managed devices or managed devices 5792 * on which PHY resets are not blocked, if the PHY registers cannot be 5793 * accessed properly by the s/w toggle the LANPHYPC value to power cycle 5794 * the PHY. 5795 * On i217, setup Intel Rapid Start Technology. 5796 **/ 5797 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 5798 { 5799 s32 ret_val; 5800 5801 DEBUGFUNC("e1000_resume_workarounds_pchlan"); 5802 if (hw->mac.type < e1000_pch2lan) 5803 return E1000_SUCCESS; 5804 5805 ret_val = e1000_init_phy_workarounds_pchlan(hw); 5806 if (ret_val) { 5807 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val); 5808 return ret_val; 5809 } 5810 5811 /* For i217 Intel Rapid Start Technology support when the system 5812 * is transitioning from Sx and no manageability engine is present 5813 * configure SMBus to restore on reset, disable proxy, and enable 5814 * the reset on MTA (Multicast table array). 5815 */ 5816 if (hw->phy.type == e1000_phy_i217) { 5817 u16 phy_reg; 5818 5819 ret_val = hw->phy.ops.acquire(hw); 5820 if (ret_val) { 5821 DEBUGOUT("Failed to setup iRST\n"); 5822 return ret_val; 5823 } 5824 5825 /* Clear Auto Enable LPI after link up */ 5826 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); 5827 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5828 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); 5829 5830 if (!(E1000_READ_REG(hw, E1000_FWSM) & 5831 E1000_ICH_FWSM_FW_VALID)) { 5832 /* Restore clear on SMB if no manageability engine 5833 * is present 5834 */ 5835 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, 5836 &phy_reg); 5837 if (ret_val) 5838 goto release; 5839 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 5840 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); 5841 5842 /* Disable Proxy */ 5843 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0); 5844 } 5845 /* Enable reset on MTA */ 5846 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG, 5847 &phy_reg); 5848 if (ret_val) 5849 goto release; 5850 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 5851 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); 5852 release: 5853 if (ret_val) 5854 DEBUGOUT1("Error %d in resume workarounds\n", ret_val); 5855 hw->phy.ops.release(hw); 5856 return ret_val; 5857 } 5858 return E1000_SUCCESS; 5859 } 5860 5861 /** 5862 * e1000_cleanup_led_ich8lan - Restore the default LED operation 5863 * @hw: pointer to the HW structure 5864 * 5865 * Return the LED back to the default configuration. 5866 **/ 5867 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 5868 { 5869 DEBUGFUNC("e1000_cleanup_led_ich8lan"); 5870 5871 if (hw->phy.type == e1000_phy_ife) 5872 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5873 0); 5874 5875 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 5876 return E1000_SUCCESS; 5877 } 5878 5879 /** 5880 * e1000_led_on_ich8lan - Turn LEDs on 5881 * @hw: pointer to the HW structure 5882 * 5883 * Turn on the LEDs. 5884 **/ 5885 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 5886 { 5887 DEBUGFUNC("e1000_led_on_ich8lan"); 5888 5889 if (hw->phy.type == e1000_phy_ife) 5890 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5891 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 5892 5893 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 5894 return E1000_SUCCESS; 5895 } 5896 5897 /** 5898 * e1000_led_off_ich8lan - Turn LEDs off 5899 * @hw: pointer to the HW structure 5900 * 5901 * Turn off the LEDs. 5902 **/ 5903 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 5904 { 5905 DEBUGFUNC("e1000_led_off_ich8lan"); 5906 5907 if (hw->phy.type == e1000_phy_ife) 5908 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5909 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 5910 5911 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 5912 return E1000_SUCCESS; 5913 } 5914 5915 /** 5916 * e1000_setup_led_pchlan - Configures SW controllable LED 5917 * @hw: pointer to the HW structure 5918 * 5919 * This prepares the SW controllable LED for use. 5920 **/ 5921 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 5922 { 5923 DEBUGFUNC("e1000_setup_led_pchlan"); 5924 5925 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 5926 (u16)hw->mac.ledctl_mode1); 5927 } 5928 5929 /** 5930 * e1000_cleanup_led_pchlan - Restore the default LED operation 5931 * @hw: pointer to the HW structure 5932 * 5933 * Return the LED back to the default configuration. 5934 **/ 5935 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 5936 { 5937 DEBUGFUNC("e1000_cleanup_led_pchlan"); 5938 5939 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 5940 (u16)hw->mac.ledctl_default); 5941 } 5942 5943 /** 5944 * e1000_led_on_pchlan - Turn LEDs on 5945 * @hw: pointer to the HW structure 5946 * 5947 * Turn on the LEDs. 5948 **/ 5949 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 5950 { 5951 u16 data = (u16)hw->mac.ledctl_mode2; 5952 u32 i, led; 5953 5954 DEBUGFUNC("e1000_led_on_pchlan"); 5955 5956 /* If no link, then turn LED on by setting the invert bit 5957 * for each LED that's mode is "link_up" in ledctl_mode2. 5958 */ 5959 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 5960 for (i = 0; i < 3; i++) { 5961 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5962 if ((led & E1000_PHY_LED0_MODE_MASK) != 5963 E1000_LEDCTL_MODE_LINK_UP) 5964 continue; 5965 if (led & E1000_PHY_LED0_IVRT) 5966 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5967 else 5968 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5969 } 5970 } 5971 5972 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 5973 } 5974 5975 /** 5976 * e1000_led_off_pchlan - Turn LEDs off 5977 * @hw: pointer to the HW structure 5978 * 5979 * Turn off the LEDs. 5980 **/ 5981 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 5982 { 5983 u16 data = (u16)hw->mac.ledctl_mode1; 5984 u32 i, led; 5985 5986 DEBUGFUNC("e1000_led_off_pchlan"); 5987 5988 /* If no link, then turn LED off by clearing the invert bit 5989 * for each LED that's mode is "link_up" in ledctl_mode1. 5990 */ 5991 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 5992 for (i = 0; i < 3; i++) { 5993 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5994 if ((led & E1000_PHY_LED0_MODE_MASK) != 5995 E1000_LEDCTL_MODE_LINK_UP) 5996 continue; 5997 if (led & E1000_PHY_LED0_IVRT) 5998 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5999 else 6000 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 6001 } 6002 } 6003 6004 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 6005 } 6006 6007 /** 6008 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 6009 * @hw: pointer to the HW structure 6010 * 6011 * Read appropriate register for the config done bit for completion status 6012 * and configure the PHY through s/w for EEPROM-less parts. 6013 * 6014 * NOTE: some silicon which is EEPROM-less will fail trying to read the 6015 * config done bit, so only an error is logged and continues. If we were 6016 * to return with error, EEPROM-less silicon would not be able to be reset 6017 * or change link. 6018 **/ 6019 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 6020 { 6021 s32 ret_val = E1000_SUCCESS; 6022 u32 bank = 0; 6023 u32 status; 6024 6025 DEBUGFUNC("e1000_get_cfg_done_ich8lan"); 6026 6027 e1000_get_cfg_done_generic(hw); 6028 6029 /* Wait for indication from h/w that it has completed basic config */ 6030 if (hw->mac.type >= e1000_ich10lan) { 6031 e1000_lan_init_done_ich8lan(hw); 6032 } else { 6033 ret_val = e1000_get_auto_rd_done_generic(hw); 6034 if (ret_val) { 6035 /* When auto config read does not complete, do not 6036 * return with an error. This can happen in situations 6037 * where there is no eeprom and prevents getting link. 6038 */ 6039 DEBUGOUT("Auto Read Done did not complete\n"); 6040 ret_val = E1000_SUCCESS; 6041 } 6042 } 6043 6044 /* Clear PHY Reset Asserted bit */ 6045 status = E1000_READ_REG(hw, E1000_STATUS); 6046 if (status & E1000_STATUS_PHYRA) 6047 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA); 6048 else 6049 DEBUGOUT("PHY Reset Asserted not set - needs delay\n"); 6050 6051 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 6052 if (hw->mac.type <= e1000_ich9lan) { 6053 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && 6054 (hw->phy.type == e1000_phy_igp_3)) { 6055 e1000_phy_init_script_igp3(hw); 6056 } 6057 } else { 6058 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 6059 /* Maybe we should do a basic PHY config */ 6060 DEBUGOUT("EEPROM not present\n"); 6061 ret_val = -E1000_ERR_CONFIG; 6062 } 6063 } 6064 6065 return ret_val; 6066 } 6067 6068 /** 6069 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 6070 * @hw: pointer to the HW structure 6071 * 6072 * In the case of a PHY power down to save power, or to turn off link during a 6073 * driver unload, or wake on lan is not enabled, remove the link. 6074 **/ 6075 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 6076 { 6077 /* If the management interface is not enabled, then power down */ 6078 if (!(hw->mac.ops.check_mng_mode(hw) || 6079 hw->phy.ops.check_reset_block(hw))) 6080 e1000_power_down_phy_copper(hw); 6081 6082 return; 6083 } 6084 6085 /** 6086 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 6087 * @hw: pointer to the HW structure 6088 * 6089 * Clears hardware counters specific to the silicon family and calls 6090 * clear_hw_cntrs_generic to clear all general purpose counters. 6091 **/ 6092 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 6093 { 6094 u16 phy_data; 6095 s32 ret_val; 6096 6097 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan"); 6098 6099 e1000_clear_hw_cntrs_base_generic(hw); 6100 6101 E1000_READ_REG(hw, E1000_ALGNERRC); 6102 E1000_READ_REG(hw, E1000_RXERRC); 6103 E1000_READ_REG(hw, E1000_TNCRS); 6104 E1000_READ_REG(hw, E1000_CEXTERR); 6105 E1000_READ_REG(hw, E1000_TSCTC); 6106 E1000_READ_REG(hw, E1000_TSCTFC); 6107 6108 E1000_READ_REG(hw, E1000_MGTPRC); 6109 E1000_READ_REG(hw, E1000_MGTPDC); 6110 E1000_READ_REG(hw, E1000_MGTPTC); 6111 6112 E1000_READ_REG(hw, E1000_IAC); 6113 E1000_READ_REG(hw, E1000_ICRXOC); 6114 6115 /* Clear PHY statistics registers */ 6116 if ((hw->phy.type == e1000_phy_82578) || 6117 (hw->phy.type == e1000_phy_82579) || 6118 (hw->phy.type == e1000_phy_i217) || 6119 (hw->phy.type == e1000_phy_82577)) { 6120 ret_val = hw->phy.ops.acquire(hw); 6121 if (ret_val) 6122 return; 6123 ret_val = hw->phy.ops.set_page(hw, 6124 HV_STATS_PAGE << IGP_PAGE_SHIFT); 6125 if (ret_val) 6126 goto release; 6127 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 6128 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 6129 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 6130 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 6131 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 6132 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 6133 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 6134 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 6135 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 6136 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 6137 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 6138 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 6139 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 6140 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 6141 release: 6142 hw->phy.ops.release(hw); 6143 } 6144 } 6145 6146