1 /****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 82562G 10/100 Network Connection 36 * 82562G-2 10/100 Network Connection 37 * 82562GT 10/100 Network Connection 38 * 82562GT-2 10/100 Network Connection 39 * 82562V 10/100 Network Connection 40 * 82562V-2 10/100 Network Connection 41 * 82566DC-2 Gigabit Network Connection 42 * 82566DC Gigabit Network Connection 43 * 82566DM-2 Gigabit Network Connection 44 * 82566DM Gigabit Network Connection 45 * 82566MC Gigabit Network Connection 46 * 82566MM Gigabit Network Connection 47 * 82567LM Gigabit Network Connection 48 * 82567LF Gigabit Network Connection 49 * 82567V Gigabit Network Connection 50 * 82567LM-2 Gigabit Network Connection 51 * 82567LF-2 Gigabit Network Connection 52 * 82567V-2 Gigabit Network Connection 53 * 82567LF-3 Gigabit Network Connection 54 * 82567LM-3 Gigabit Network Connection 55 * 82567LM-4 Gigabit Network Connection 56 * 82577LM Gigabit Network Connection 57 * 82577LC Gigabit Network Connection 58 * 82578DM Gigabit Network Connection 59 * 82578DC Gigabit Network Connection 60 * 82579LM Gigabit Network Connection 61 * 82579V Gigabit Network Connection 62 * Ethernet Connection I217-LM 63 * Ethernet Connection I217-V 64 * Ethernet Connection I218-V 65 * Ethernet Connection I218-LM 66 * Ethernet Connection (2) I218-LM 67 * Ethernet Connection (2) I218-V 68 * Ethernet Connection (3) I218-LM 69 * Ethernet Connection (3) I218-V 70 */ 71 72 #include "e1000_api.h" 73 74 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); 75 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw); 76 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw); 77 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw); 78 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 79 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 80 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 81 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 82 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw); 83 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, 84 u8 *mc_addr_list, 85 u32 mc_addr_count); 86 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); 87 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); 88 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 89 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 90 bool active); 91 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 92 bool active); 93 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 94 u16 words, u16 *data); 95 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 96 u16 *data); 97 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 98 u16 words, u16 *data); 99 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw); 100 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw); 101 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw); 102 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, 103 u16 *data); 104 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 105 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw); 106 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); 107 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); 108 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); 109 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); 110 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 111 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, 112 u16 *speed, u16 *duplex); 113 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 114 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 115 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 116 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 117 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 118 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 119 static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 120 static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 121 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 122 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 123 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 124 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 125 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, 126 u32 offset, u8 *data); 127 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 128 u8 size, u16 *data); 129 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 130 u32 *data); 131 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, 132 u32 offset, u32 *data); 133 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, 134 u32 offset, u32 data); 135 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 136 u32 offset, u32 dword); 137 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, 138 u32 offset, u16 *data); 139 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 140 u32 offset, u8 byte); 141 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); 142 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 143 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw); 144 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 145 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 146 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 147 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr); 148 149 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 150 /* Offset 04h HSFSTS */ 151 union ich8_hws_flash_status { 152 struct ich8_hsfsts { 153 u16 flcdone:1; /* bit 0 Flash Cycle Done */ 154 u16 flcerr:1; /* bit 1 Flash Cycle Error */ 155 u16 dael:1; /* bit 2 Direct Access error Log */ 156 u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 157 u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 158 u16 reserved1:2; /* bit 13:6 Reserved */ 159 u16 reserved2:6; /* bit 13:6 Reserved */ 160 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 161 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 162 } hsf_status; 163 u16 regval; 164 }; 165 166 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 167 /* Offset 06h FLCTL */ 168 union ich8_hws_flash_ctrl { 169 struct ich8_hsflctl { 170 u16 flcgo:1; /* 0 Flash Cycle Go */ 171 u16 flcycle:2; /* 2:1 Flash Cycle */ 172 u16 reserved:5; /* 7:3 Reserved */ 173 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 174 u16 flockdn:6; /* 15:10 Reserved */ 175 } hsf_ctrl; 176 u16 regval; 177 }; 178 179 /* ICH Flash Region Access Permissions */ 180 union ich8_hws_flash_regacc { 181 struct ich8_flracc { 182 u32 grra:8; /* 0:7 GbE region Read Access */ 183 u32 grwa:8; /* 8:15 GbE region Write Access */ 184 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 185 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 186 } hsf_flregacc; 187 u16 regval; 188 }; 189 190 /** 191 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 192 * @hw: pointer to the HW structure 193 * 194 * Test access to the PHY registers by reading the PHY ID registers. If 195 * the PHY ID is already known (e.g. resume path) compare it with known ID, 196 * otherwise assume the read PHY ID is correct if it is valid. 197 * 198 * Assumes the sw/fw/hw semaphore is already acquired. 199 **/ 200 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 201 { 202 u16 phy_reg = 0; 203 u32 phy_id = 0; 204 s32 ret_val = 0; 205 u16 retry_count; 206 u32 mac_reg = 0; 207 208 for (retry_count = 0; retry_count < 2; retry_count++) { 209 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg); 210 if (ret_val || (phy_reg == 0xFFFF)) 211 continue; 212 phy_id = (u32)(phy_reg << 16); 213 214 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg); 215 if (ret_val || (phy_reg == 0xFFFF)) { 216 phy_id = 0; 217 continue; 218 } 219 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 220 break; 221 } 222 223 if (hw->phy.id) { 224 if (hw->phy.id == phy_id) 225 goto out; 226 } else if (phy_id) { 227 hw->phy.id = phy_id; 228 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 229 goto out; 230 } 231 232 /* In case the PHY needs to be in mdio slow mode, 233 * set slow mode and try to get the PHY id again. 234 */ 235 if (hw->mac.type < e1000_pch_lpt) { 236 hw->phy.ops.release(hw); 237 ret_val = e1000_set_mdio_slow_mode_hv(hw); 238 if (!ret_val) 239 ret_val = e1000_get_phy_id(hw); 240 hw->phy.ops.acquire(hw); 241 } 242 243 if (ret_val) 244 return FALSE; 245 out: 246 if (hw->mac.type >= e1000_pch_lpt) { 247 /* Only unforce SMBus if ME is not active */ 248 if (!(E1000_READ_REG(hw, E1000_FWSM) & 249 E1000_ICH_FWSM_FW_VALID)) { 250 /* Unforce SMBus mode in PHY */ 251 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg); 252 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 253 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg); 254 255 /* Unforce SMBus mode in MAC */ 256 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 257 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 258 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 259 } 260 } 261 262 return TRUE; 263 } 264 265 /** 266 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 267 * @hw: pointer to the HW structure 268 * 269 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 270 * used to reset the PHY to a quiescent state when necessary. 271 **/ 272 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) 273 { 274 u32 mac_reg; 275 276 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt"); 277 278 /* Set Phy Config Counter to 50msec */ 279 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3); 280 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 281 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 282 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg); 283 284 /* Toggle LANPHYPC Value bit */ 285 mac_reg = E1000_READ_REG(hw, E1000_CTRL); 286 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 287 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 288 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg); 289 E1000_WRITE_FLUSH(hw); 290 msec_delay(1); 291 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 292 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg); 293 E1000_WRITE_FLUSH(hw); 294 295 if (hw->mac.type < e1000_pch_lpt) { 296 msec_delay(50); 297 } else { 298 u16 count = 20; 299 300 do { 301 msec_delay(5); 302 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) & 303 E1000_CTRL_EXT_LPCD) && count--); 304 305 msec_delay(30); 306 } 307 } 308 309 /** 310 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 311 * @hw: pointer to the HW structure 312 * 313 * Workarounds/flow necessary for PHY initialization during driver load 314 * and resume paths. 315 **/ 316 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 317 { 318 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM); 319 s32 ret_val; 320 321 DEBUGFUNC("e1000_init_phy_workarounds_pchlan"); 322 323 /* Gate automatic PHY configuration by hardware on managed and 324 * non-managed 82579 and newer adapters. 325 */ 326 e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 327 328 /* It is not possible to be certain of the current state of ULP 329 * so forcibly disable it. 330 */ 331 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; 332 e1000_disable_ulp_lpt_lp(hw, TRUE); 333 334 ret_val = hw->phy.ops.acquire(hw); 335 if (ret_val) { 336 DEBUGOUT("Failed to initialize PHY flow\n"); 337 goto out; 338 } 339 340 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 341 * inaccessible and resetting the PHY is not blocked, toggle the 342 * LANPHYPC Value bit to force the interconnect to PCIe mode. 343 */ 344 switch (hw->mac.type) { 345 case e1000_pch_lpt: 346 case e1000_pch_spt: 347 case e1000_pch_cnp: 348 if (e1000_phy_is_accessible_pchlan(hw)) 349 break; 350 351 /* Before toggling LANPHYPC, see if PHY is accessible by 352 * forcing MAC to SMBus mode first. 353 */ 354 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 355 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 356 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 357 358 /* Wait 50 milliseconds for MAC to finish any retries 359 * that it might be trying to perform from previous 360 * attempts to acknowledge any phy read requests. 361 */ 362 msec_delay(50); 363 364 /* fall-through */ 365 case e1000_pch2lan: 366 if (e1000_phy_is_accessible_pchlan(hw)) 367 break; 368 369 /* fall-through */ 370 case e1000_pchlan: 371 if ((hw->mac.type == e1000_pchlan) && 372 (fwsm & E1000_ICH_FWSM_FW_VALID)) 373 break; 374 375 if (hw->phy.ops.check_reset_block(hw)) { 376 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n"); 377 ret_val = -E1000_ERR_PHY; 378 break; 379 } 380 381 /* Toggle LANPHYPC Value bit */ 382 e1000_toggle_lanphypc_pch_lpt(hw); 383 if (hw->mac.type >= e1000_pch_lpt) { 384 if (e1000_phy_is_accessible_pchlan(hw)) 385 break; 386 387 /* Toggling LANPHYPC brings the PHY out of SMBus mode 388 * so ensure that the MAC is also out of SMBus mode 389 */ 390 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 391 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 392 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 393 394 if (e1000_phy_is_accessible_pchlan(hw)) 395 break; 396 397 ret_val = -E1000_ERR_PHY; 398 } 399 break; 400 default: 401 break; 402 } 403 404 hw->phy.ops.release(hw); 405 if (!ret_val) { 406 407 /* Check to see if able to reset PHY. Print error if not */ 408 if (hw->phy.ops.check_reset_block(hw)) { 409 ERROR_REPORT("Reset blocked by ME\n"); 410 goto out; 411 } 412 413 /* Reset the PHY before any access to it. Doing so, ensures 414 * that the PHY is in a known good state before we read/write 415 * PHY registers. The generic reset is sufficient here, 416 * because we haven't determined the PHY type yet. 417 */ 418 ret_val = e1000_phy_hw_reset_generic(hw); 419 if (ret_val) 420 goto out; 421 422 /* On a successful reset, possibly need to wait for the PHY 423 * to quiesce to an accessible state before returning control 424 * to the calling function. If the PHY does not quiesce, then 425 * return E1000E_BLK_PHY_RESET, as this is the condition that 426 * the PHY is in. 427 */ 428 ret_val = hw->phy.ops.check_reset_block(hw); 429 if (ret_val) 430 ERROR_REPORT("ME blocked access to PHY after reset\n"); 431 } 432 433 out: 434 /* Ungate automatic PHY configuration on non-managed 82579 */ 435 if ((hw->mac.type == e1000_pch2lan) && 436 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 437 msec_delay(10); 438 e1000_gate_hw_phy_config_ich8lan(hw, FALSE); 439 } 440 441 return ret_val; 442 } 443 444 /** 445 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 446 * @hw: pointer to the HW structure 447 * 448 * Initialize family-specific PHY parameters and function pointers. 449 **/ 450 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 451 { 452 struct e1000_phy_info *phy = &hw->phy; 453 s32 ret_val; 454 455 DEBUGFUNC("e1000_init_phy_params_pchlan"); 456 457 phy->addr = 1; 458 phy->reset_delay_us = 100; 459 460 phy->ops.acquire = e1000_acquire_swflag_ich8lan; 461 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 462 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 463 phy->ops.set_page = e1000_set_page_igp; 464 phy->ops.read_reg = e1000_read_phy_reg_hv; 465 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 466 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 467 phy->ops.release = e1000_release_swflag_ich8lan; 468 phy->ops.reset = e1000_phy_hw_reset_ich8lan; 469 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 470 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 471 phy->ops.write_reg = e1000_write_phy_reg_hv; 472 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 473 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 474 phy->ops.power_up = e1000_power_up_phy_copper; 475 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 476 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 477 478 phy->id = e1000_phy_unknown; 479 480 ret_val = e1000_init_phy_workarounds_pchlan(hw); 481 if (ret_val) 482 return ret_val; 483 484 if (phy->id == e1000_phy_unknown) 485 switch (hw->mac.type) { 486 default: 487 ret_val = e1000_get_phy_id(hw); 488 if (ret_val) 489 return ret_val; 490 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 491 break; 492 /* fall-through */ 493 case e1000_pch2lan: 494 case e1000_pch_lpt: 495 case e1000_pch_spt: 496 case e1000_pch_cnp: 497 /* In case the PHY needs to be in mdio slow mode, 498 * set slow mode and try to get the PHY id again. 499 */ 500 ret_val = e1000_set_mdio_slow_mode_hv(hw); 501 if (ret_val) 502 return ret_val; 503 ret_val = e1000_get_phy_id(hw); 504 if (ret_val) 505 return ret_val; 506 break; 507 } 508 phy->type = e1000_get_phy_type_from_id(phy->id); 509 510 switch (phy->type) { 511 case e1000_phy_82577: 512 case e1000_phy_82579: 513 case e1000_phy_i217: 514 phy->ops.check_polarity = e1000_check_polarity_82577; 515 phy->ops.force_speed_duplex = 516 e1000_phy_force_speed_duplex_82577; 517 phy->ops.get_cable_length = e1000_get_cable_length_82577; 518 phy->ops.get_info = e1000_get_phy_info_82577; 519 phy->ops.commit = e1000_phy_sw_reset_generic; 520 break; 521 case e1000_phy_82578: 522 phy->ops.check_polarity = e1000_check_polarity_m88; 523 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 524 phy->ops.get_cable_length = e1000_get_cable_length_m88; 525 phy->ops.get_info = e1000_get_phy_info_m88; 526 break; 527 default: 528 ret_val = -E1000_ERR_PHY; 529 break; 530 } 531 532 return ret_val; 533 } 534 535 /** 536 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 537 * @hw: pointer to the HW structure 538 * 539 * Initialize family-specific PHY parameters and function pointers. 540 **/ 541 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 542 { 543 struct e1000_phy_info *phy = &hw->phy; 544 s32 ret_val; 545 u16 i = 0; 546 547 DEBUGFUNC("e1000_init_phy_params_ich8lan"); 548 549 phy->addr = 1; 550 phy->reset_delay_us = 100; 551 552 phy->ops.acquire = e1000_acquire_swflag_ich8lan; 553 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 554 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 555 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 556 phy->ops.read_reg = e1000_read_phy_reg_igp; 557 phy->ops.release = e1000_release_swflag_ich8lan; 558 phy->ops.reset = e1000_phy_hw_reset_ich8lan; 559 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; 560 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; 561 phy->ops.write_reg = e1000_write_phy_reg_igp; 562 phy->ops.power_up = e1000_power_up_phy_copper; 563 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 564 565 /* We may need to do this twice - once for IGP and if that fails, 566 * we'll set BM func pointers and try again 567 */ 568 ret_val = e1000_determine_phy_address(hw); 569 if (ret_val) { 570 phy->ops.write_reg = e1000_write_phy_reg_bm; 571 phy->ops.read_reg = e1000_read_phy_reg_bm; 572 ret_val = e1000_determine_phy_address(hw); 573 if (ret_val) { 574 DEBUGOUT("Cannot determine PHY addr. Erroring out\n"); 575 return ret_val; 576 } 577 } 578 579 phy->id = 0; 580 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && 581 (i++ < 100)) { 582 msec_delay(1); 583 ret_val = e1000_get_phy_id(hw); 584 if (ret_val) 585 return ret_val; 586 } 587 588 /* Verify phy id */ 589 switch (phy->id) { 590 case IGP03E1000_E_PHY_ID: 591 phy->type = e1000_phy_igp_3; 592 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 593 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked; 594 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked; 595 phy->ops.get_info = e1000_get_phy_info_igp; 596 phy->ops.check_polarity = e1000_check_polarity_igp; 597 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 598 break; 599 case IFE_E_PHY_ID: 600 case IFE_PLUS_E_PHY_ID: 601 case IFE_C_E_PHY_ID: 602 phy->type = e1000_phy_ife; 603 phy->autoneg_mask = E1000_ALL_NOT_GIG; 604 phy->ops.get_info = e1000_get_phy_info_ife; 605 phy->ops.check_polarity = e1000_check_polarity_ife; 606 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 607 break; 608 case BME1000_E_PHY_ID: 609 phy->type = e1000_phy_bm; 610 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 611 phy->ops.read_reg = e1000_read_phy_reg_bm; 612 phy->ops.write_reg = e1000_write_phy_reg_bm; 613 phy->ops.commit = e1000_phy_sw_reset_generic; 614 phy->ops.get_info = e1000_get_phy_info_m88; 615 phy->ops.check_polarity = e1000_check_polarity_m88; 616 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 617 break; 618 default: 619 return -E1000_ERR_PHY; 620 break; 621 } 622 623 return E1000_SUCCESS; 624 } 625 626 /** 627 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 628 * @hw: pointer to the HW structure 629 * 630 * Initialize family-specific NVM parameters and function 631 * pointers. 632 **/ 633 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 634 { 635 struct e1000_nvm_info *nvm = &hw->nvm; 636 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 637 u32 gfpreg, sector_base_addr, sector_end_addr; 638 u16 i; 639 u32 nvm_size; 640 641 DEBUGFUNC("e1000_init_nvm_params_ich8lan"); 642 643 nvm->type = e1000_nvm_flash_sw; 644 645 if (hw->mac.type >= e1000_pch_spt) { 646 /* in SPT, gfpreg doesn't exist. NVM size is taken from the 647 * STRAP register. This is because in SPT the GbE Flash region 648 * is no longer accessed through the flash registers. Instead, 649 * the mechanism has changed, and the Flash region access 650 * registers are now implemented in GbE memory space. 651 */ 652 nvm->flash_base_addr = 0; 653 nvm_size = 654 (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1) 655 * NVM_SIZE_MULTIPLIER; 656 nvm->flash_bank_size = nvm_size / 2; 657 /* Adjust to word count */ 658 nvm->flash_bank_size /= sizeof(u16); 659 /* Set the base address for flash register access */ 660 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; 661 } else { 662 /* Can't read flash registers if register set isn't mapped. */ 663 if (!hw->flash_address) { 664 DEBUGOUT("ERROR: Flash registers not mapped\n"); 665 return -E1000_ERR_CONFIG; 666 } 667 668 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); 669 670 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 671 * Add 1 to sector_end_addr since this sector is included in 672 * the overall size. 673 */ 674 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 675 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 676 677 /* flash_base_addr is byte-aligned */ 678 nvm->flash_base_addr = sector_base_addr 679 << FLASH_SECTOR_ADDR_SHIFT; 680 681 /* find total size of the NVM, then cut in half since the total 682 * size represents two separate NVM banks. 683 */ 684 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 685 << FLASH_SECTOR_ADDR_SHIFT); 686 nvm->flash_bank_size /= 2; 687 /* Adjust to word count */ 688 nvm->flash_bank_size /= sizeof(u16); 689 } 690 691 nvm->word_size = E1000_SHADOW_RAM_WORDS; 692 693 /* Clear shadow ram */ 694 for (i = 0; i < nvm->word_size; i++) { 695 dev_spec->shadow_ram[i].modified = FALSE; 696 dev_spec->shadow_ram[i].value = 0xFFFF; 697 } 698 699 E1000_MUTEX_INIT(&dev_spec->nvm_mutex); 700 E1000_MUTEX_INIT(&dev_spec->swflag_mutex); 701 702 /* Function Pointers */ 703 nvm->ops.acquire = e1000_acquire_nvm_ich8lan; 704 nvm->ops.release = e1000_release_nvm_ich8lan; 705 if (hw->mac.type >= e1000_pch_spt) { 706 nvm->ops.read = e1000_read_nvm_spt; 707 nvm->ops.update = e1000_update_nvm_checksum_spt; 708 } else { 709 nvm->ops.read = e1000_read_nvm_ich8lan; 710 nvm->ops.update = e1000_update_nvm_checksum_ich8lan; 711 } 712 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan; 713 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan; 714 nvm->ops.write = e1000_write_nvm_ich8lan; 715 716 return E1000_SUCCESS; 717 } 718 719 /** 720 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 721 * @hw: pointer to the HW structure 722 * 723 * Initialize family-specific MAC parameters and function 724 * pointers. 725 **/ 726 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 727 { 728 struct e1000_mac_info *mac = &hw->mac; 729 730 DEBUGFUNC("e1000_init_mac_params_ich8lan"); 731 732 /* Set media type function pointer */ 733 hw->phy.media_type = e1000_media_type_copper; 734 735 /* Set mta register count */ 736 mac->mta_reg_count = 32; 737 /* Set rar entry count */ 738 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 739 if (mac->type == e1000_ich8lan) 740 mac->rar_entry_count--; 741 /* Set if part includes ASF firmware */ 742 mac->asf_firmware_present = TRUE; 743 /* FWSM register */ 744 mac->has_fwsm = TRUE; 745 /* ARC subsystem not supported */ 746 mac->arc_subsystem_valid = FALSE; 747 /* Adaptive IFS supported */ 748 mac->adaptive_ifs = TRUE; 749 750 /* Function pointers */ 751 752 /* bus type/speed/width */ 753 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan; 754 /* function id */ 755 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 756 /* reset */ 757 mac->ops.reset_hw = e1000_reset_hw_ich8lan; 758 /* hw initialization */ 759 mac->ops.init_hw = e1000_init_hw_ich8lan; 760 /* link setup */ 761 mac->ops.setup_link = e1000_setup_link_ich8lan; 762 /* physical interface setup */ 763 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan; 764 /* check for link */ 765 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan; 766 /* link info */ 767 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan; 768 /* multicast address update */ 769 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 770 /* clear hardware counters */ 771 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; 772 773 /* LED and other operations */ 774 switch (mac->type) { 775 case e1000_ich8lan: 776 case e1000_ich9lan: 777 case e1000_ich10lan: 778 /* check management mode */ 779 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 780 /* ID LED init */ 781 mac->ops.id_led_init = e1000_id_led_init_generic; 782 /* blink LED */ 783 mac->ops.blink_led = e1000_blink_led_generic; 784 /* setup LED */ 785 mac->ops.setup_led = e1000_setup_led_generic; 786 /* cleanup LED */ 787 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 788 /* turn on/off LED */ 789 mac->ops.led_on = e1000_led_on_ich8lan; 790 mac->ops.led_off = e1000_led_off_ich8lan; 791 break; 792 case e1000_pch2lan: 793 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 794 mac->ops.rar_set = e1000_rar_set_pch2lan; 795 /* fall-through */ 796 case e1000_pch_lpt: 797 case e1000_pch_spt: 798 case e1000_pch_cnp: 799 /* multicast address update for pch2 */ 800 mac->ops.update_mc_addr_list = 801 e1000_update_mc_addr_list_pch2lan; 802 /* fall-through */ 803 case e1000_pchlan: 804 /* check management mode */ 805 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 806 /* ID LED init */ 807 mac->ops.id_led_init = e1000_id_led_init_pchlan; 808 /* setup LED */ 809 mac->ops.setup_led = e1000_setup_led_pchlan; 810 /* cleanup LED */ 811 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 812 /* turn on/off LED */ 813 mac->ops.led_on = e1000_led_on_pchlan; 814 mac->ops.led_off = e1000_led_off_pchlan; 815 break; 816 default: 817 break; 818 } 819 820 if (mac->type >= e1000_pch_lpt) { 821 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 822 mac->ops.rar_set = e1000_rar_set_pch_lpt; 823 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt; 824 mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt; 825 } 826 827 /* Enable PCS Lock-loss workaround for ICH8 */ 828 if (mac->type == e1000_ich8lan) 829 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); 830 831 return E1000_SUCCESS; 832 } 833 834 /** 835 * __e1000_access_emi_reg_locked - Read/write EMI register 836 * @hw: pointer to the HW structure 837 * @addr: EMI address to program 838 * @data: pointer to value to read/write from/to the EMI address 839 * @read: boolean flag to indicate read or write 840 * 841 * This helper function assumes the SW/FW/HW Semaphore is already acquired. 842 **/ 843 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 844 u16 *data, bool read) 845 { 846 s32 ret_val; 847 848 DEBUGFUNC("__e1000_access_emi_reg_locked"); 849 850 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address); 851 if (ret_val) 852 return ret_val; 853 854 if (read) 855 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA, 856 data); 857 else 858 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 859 *data); 860 861 return ret_val; 862 } 863 864 /** 865 * e1000_read_emi_reg_locked - Read Extended Management Interface register 866 * @hw: pointer to the HW structure 867 * @addr: EMI address to program 868 * @data: value to be read from the EMI address 869 * 870 * Assumes the SW/FW/HW Semaphore is already acquired. 871 **/ 872 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 873 { 874 DEBUGFUNC("e1000_read_emi_reg_locked"); 875 876 return __e1000_access_emi_reg_locked(hw, addr, data, TRUE); 877 } 878 879 /** 880 * e1000_write_emi_reg_locked - Write Extended Management Interface register 881 * @hw: pointer to the HW structure 882 * @addr: EMI address to program 883 * @data: value to be written to the EMI address 884 * 885 * Assumes the SW/FW/HW Semaphore is already acquired. 886 **/ 887 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 888 { 889 DEBUGFUNC("e1000_read_emi_reg_locked"); 890 891 return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE); 892 } 893 894 /** 895 * e1000_set_eee_pchlan - Enable/disable EEE support 896 * @hw: pointer to the HW structure 897 * 898 * Enable/disable EEE based on setting in dev_spec structure, the duplex of 899 * the link and the EEE capabilities of the link partner. The LPI Control 900 * register bits will remain set only if/when link is up. 901 * 902 * EEE LPI must not be asserted earlier than one second after link is up. 903 * On 82579, EEE LPI should not be enabled until such time otherwise there 904 * can be link issues with some switches. Other devices can have EEE LPI 905 * enabled immediately upon link up since they have a timer in hardware which 906 * prevents LPI from being asserted too early. 907 **/ 908 s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 909 { 910 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 911 s32 ret_val; 912 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; 913 914 DEBUGFUNC("e1000_set_eee_pchlan"); 915 916 switch (hw->phy.type) { 917 case e1000_phy_82579: 918 lpa = I82579_EEE_LP_ABILITY; 919 pcs_status = I82579_EEE_PCS_STATUS; 920 adv_addr = I82579_EEE_ADVERTISEMENT; 921 break; 922 case e1000_phy_i217: 923 lpa = I217_EEE_LP_ABILITY; 924 pcs_status = I217_EEE_PCS_STATUS; 925 adv_addr = I217_EEE_ADVERTISEMENT; 926 break; 927 default: 928 return E1000_SUCCESS; 929 } 930 931 ret_val = hw->phy.ops.acquire(hw); 932 if (ret_val) 933 return ret_val; 934 935 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 936 if (ret_val) 937 goto release; 938 939 /* Clear bits that enable EEE in various speeds */ 940 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 941 942 /* Enable EEE if not disabled by user */ 943 if (!dev_spec->eee_disable) { 944 /* Save off link partner's EEE ability */ 945 ret_val = e1000_read_emi_reg_locked(hw, lpa, 946 &dev_spec->eee_lp_ability); 947 if (ret_val) 948 goto release; 949 950 /* Read EEE advertisement */ 951 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); 952 if (ret_val) 953 goto release; 954 955 /* Enable EEE only for speeds in which the link partner is 956 * EEE capable and for which we advertise EEE. 957 */ 958 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 959 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 960 961 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 962 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data); 963 if (data & NWAY_LPAR_100TX_FD_CAPS) 964 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 965 else 966 /* EEE is not supported in 100Half, so ignore 967 * partner's EEE in 100 ability if full-duplex 968 * is not advertised. 969 */ 970 dev_spec->eee_lp_ability &= 971 ~I82579_EEE_100_SUPPORTED; 972 } 973 } 974 975 if (hw->phy.type == e1000_phy_82579) { 976 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 977 &data); 978 if (ret_val) 979 goto release; 980 981 data &= ~I82579_LPI_100_PLL_SHUT; 982 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 983 data); 984 } 985 986 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 987 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 988 if (ret_val) 989 goto release; 990 991 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 992 release: 993 hw->phy.ops.release(hw); 994 995 return ret_val; 996 } 997 998 /** 999 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 1000 * @hw: pointer to the HW structure 1001 * @link: link up bool flag 1002 * 1003 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 1004 * preventing further DMA write requests. Workaround the issue by disabling 1005 * the de-assertion of the clock request when in 1Gpbs mode. 1006 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 1007 * speeds in order to avoid Tx hangs. 1008 **/ 1009 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 1010 { 1011 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); 1012 u32 status = E1000_READ_REG(hw, E1000_STATUS); 1013 s32 ret_val = E1000_SUCCESS; 1014 u16 reg; 1015 1016 if (link && (status & E1000_STATUS_SPEED_1000)) { 1017 ret_val = hw->phy.ops.acquire(hw); 1018 if (ret_val) 1019 return ret_val; 1020 1021 ret_val = 1022 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 1023 ®); 1024 if (ret_val) 1025 goto release; 1026 1027 ret_val = 1028 e1000_write_kmrn_reg_locked(hw, 1029 E1000_KMRNCTRLSTA_K1_CONFIG, 1030 reg & 1031 ~E1000_KMRNCTRLSTA_K1_ENABLE); 1032 if (ret_val) 1033 goto release; 1034 1035 usec_delay(10); 1036 1037 E1000_WRITE_REG(hw, E1000_FEXTNVM6, 1038 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 1039 1040 ret_val = 1041 e1000_write_kmrn_reg_locked(hw, 1042 E1000_KMRNCTRLSTA_K1_CONFIG, 1043 reg); 1044 release: 1045 hw->phy.ops.release(hw); 1046 } else { 1047 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 1048 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 1049 1050 if ((hw->phy.revision > 5) || !link || 1051 ((status & E1000_STATUS_SPEED_100) && 1052 (status & E1000_STATUS_FD))) 1053 goto update_fextnvm6; 1054 1055 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®); 1056 if (ret_val) 1057 return ret_val; 1058 1059 /* Clear link status transmit timeout */ 1060 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 1061 1062 if (status & E1000_STATUS_SPEED_100) { 1063 /* Set inband Tx timeout to 5x10us for 100Half */ 1064 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 1065 1066 /* Do not extend the K1 entry latency for 100Half */ 1067 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 1068 } else { 1069 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 1070 reg |= 50 << 1071 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 1072 1073 /* Extend the K1 entry latency for 10 Mbps */ 1074 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 1075 } 1076 1077 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg); 1078 if (ret_val) 1079 return ret_val; 1080 1081 update_fextnvm6: 1082 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6); 1083 } 1084 1085 return ret_val; 1086 } 1087 1088 static u64 e1000_ltr2ns(u16 ltr) 1089 { 1090 u32 value, scale; 1091 1092 /* Determine the latency in nsec based on the LTR value & scale */ 1093 value = ltr & E1000_LTRV_VALUE_MASK; 1094 scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT; 1095 1096 return value * (1 << (scale * E1000_LTRV_SCALE_FACTOR)); 1097 } 1098 1099 /** 1100 * e1000_platform_pm_pch_lpt - Set platform power management values 1101 * @hw: pointer to the HW structure 1102 * @link: bool indicating link status 1103 * 1104 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 1105 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 1106 * when link is up (which must not exceed the maximum latency supported 1107 * by the platform), otherwise specify there is no LTR requirement. 1108 * Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop 1109 * latencies in the LTR Extended Capability Structure in the PCIe Extended 1110 * Capability register set, on this device LTR is set by writing the 1111 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 1112 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 1113 * message to the PMC. 1114 * 1115 * Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF) 1116 * high-water mark. 1117 **/ 1118 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 1119 { 1120 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 1121 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 1122 u16 lat_enc = 0; /* latency encoded */ 1123 s32 obff_hwm = 0; 1124 1125 DEBUGFUNC("e1000_platform_pm_pch_lpt"); 1126 1127 if (link) { 1128 u16 speed, duplex, scale = 0; 1129 u16 max_snoop, max_nosnoop; 1130 u16 max_ltr_enc; /* max LTR latency encoded */ 1131 s64 lat_ns; 1132 s64 value; 1133 u32 rxa; 1134 1135 if (!hw->mac.max_frame_size) { 1136 DEBUGOUT("max_frame_size not set.\n"); 1137 return -E1000_ERR_CONFIG; 1138 } 1139 1140 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 1141 if (!speed) { 1142 DEBUGOUT("Speed not set.\n"); 1143 return -E1000_ERR_CONFIG; 1144 } 1145 1146 /* Rx Packet Buffer Allocation size (KB) */ 1147 rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK; 1148 1149 /* Determine the maximum latency tolerated by the device. 1150 * 1151 * Per the PCIe spec, the tolerated latencies are encoded as 1152 * a 3-bit encoded scale (only 0-5 are valid) multiplied by 1153 * a 10-bit value (0-1023) to provide a range from 1 ns to 1154 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 1155 * 1=2^5ns, 2=2^10ns,...5=2^25ns. 1156 */ 1157 lat_ns = ((s64)rxa * 1024 - 1158 (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000; 1159 if (lat_ns < 0) 1160 lat_ns = 0; 1161 else 1162 lat_ns /= speed; 1163 value = lat_ns; 1164 1165 while (value > E1000_LTRV_VALUE_MASK) { 1166 scale++; 1167 value = E1000_DIVIDE_ROUND_UP(value, (1 << 5)); 1168 } 1169 if (scale > E1000_LTRV_SCALE_MAX) { 1170 DEBUGOUT1("Invalid LTR latency scale %d\n", scale); 1171 return -E1000_ERR_CONFIG; 1172 } 1173 lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value); 1174 1175 /* Determine the maximum latency tolerated by the platform */ 1176 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop); 1177 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 1178 max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop); 1179 1180 if (lat_enc > max_ltr_enc) { 1181 lat_enc = max_ltr_enc; 1182 lat_ns = e1000_ltr2ns(max_ltr_enc); 1183 } 1184 1185 if (lat_ns) { 1186 lat_ns *= speed * 1000; 1187 lat_ns /= 8; 1188 lat_ns /= 1000000000; 1189 obff_hwm = (s32)(rxa - lat_ns); 1190 } 1191 if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) { 1192 DEBUGOUT1("Invalid high water mark %d\n", obff_hwm); 1193 return -E1000_ERR_CONFIG; 1194 } 1195 } 1196 1197 /* Set Snoop and No-Snoop latencies the same */ 1198 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 1199 E1000_WRITE_REG(hw, E1000_LTRV, reg); 1200 1201 /* Set OBFF high water mark */ 1202 reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK; 1203 reg |= obff_hwm; 1204 E1000_WRITE_REG(hw, E1000_SVT, reg); 1205 1206 /* Enable OBFF */ 1207 reg = E1000_READ_REG(hw, E1000_SVCR); 1208 reg |= E1000_SVCR_OFF_EN; 1209 /* Always unblock interrupts to the CPU even when the system is 1210 * in OBFF mode. This ensures that small round-robin traffic 1211 * (like ping) does not get dropped or experience long latency. 1212 */ 1213 reg |= E1000_SVCR_OFF_MASKINT; 1214 E1000_WRITE_REG(hw, E1000_SVCR, reg); 1215 1216 return E1000_SUCCESS; 1217 } 1218 1219 /** 1220 * e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer 1221 * @hw: pointer to the HW structure 1222 * @itr: interrupt throttling rate 1223 * 1224 * Configure OBFF with the updated interrupt rate. 1225 **/ 1226 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr) 1227 { 1228 u32 svcr; 1229 s32 timer; 1230 1231 DEBUGFUNC("e1000_set_obff_timer_pch_lpt"); 1232 1233 /* Convert ITR value into microseconds for OBFF timer */ 1234 timer = itr & E1000_ITR_MASK; 1235 timer = (timer * E1000_ITR_MULT) / 1000; 1236 1237 if ((timer < 0) || (timer > E1000_ITR_MASK)) { 1238 DEBUGOUT1("Invalid OBFF timer %d\n", timer); 1239 return -E1000_ERR_CONFIG; 1240 } 1241 1242 svcr = E1000_READ_REG(hw, E1000_SVCR); 1243 svcr &= ~E1000_SVCR_OFF_TIMER_MASK; 1244 svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT; 1245 E1000_WRITE_REG(hw, E1000_SVCR, svcr); 1246 1247 return E1000_SUCCESS; 1248 } 1249 1250 /** 1251 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP 1252 * @hw: pointer to the HW structure 1253 * @to_sx: boolean indicating a system power state transition to Sx 1254 * 1255 * When link is down, configure ULP mode to significantly reduce the power 1256 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the 1257 * ME firmware to start the ULP configuration. If not on an ME enabled 1258 * system, configure the ULP mode by software. 1259 */ 1260 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) 1261 { 1262 u32 mac_reg; 1263 s32 ret_val = E1000_SUCCESS; 1264 u16 phy_reg; 1265 u16 oem_reg = 0; 1266 1267 if ((hw->mac.type < e1000_pch_lpt) || 1268 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || 1269 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || 1270 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || 1271 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) || 1272 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) 1273 return 0; 1274 1275 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) { 1276 /* Request ME configure ULP mode in the PHY */ 1277 mac_reg = E1000_READ_REG(hw, E1000_H2ME); 1278 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; 1279 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); 1280 1281 goto out; 1282 } 1283 1284 if (!to_sx) { 1285 int i = 0; 1286 1287 /* Poll up to 5 seconds for Cable Disconnected indication */ 1288 while (!(E1000_READ_REG(hw, E1000_FEXT) & 1289 E1000_FEXT_PHY_CABLE_DISCONNECTED)) { 1290 /* Bail if link is re-acquired */ 1291 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) 1292 return -E1000_ERR_PHY; 1293 1294 if (i++ == 100) 1295 break; 1296 1297 msec_delay(50); 1298 } 1299 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n", 1300 (E1000_READ_REG(hw, E1000_FEXT) & 1301 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", 1302 i * 50); 1303 } 1304 1305 ret_val = hw->phy.ops.acquire(hw); 1306 if (ret_val) 1307 goto out; 1308 1309 /* Force SMBus mode in PHY */ 1310 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1311 if (ret_val) 1312 goto release; 1313 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS; 1314 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1315 1316 /* Force SMBus mode in MAC */ 1317 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1318 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1319 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 1320 1321 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable 1322 * LPLU and disable Gig speed when entering ULP 1323 */ 1324 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { 1325 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, 1326 &oem_reg); 1327 if (ret_val) 1328 goto release; 1329 1330 phy_reg = oem_reg; 1331 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS; 1332 1333 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1334 phy_reg); 1335 1336 if (ret_val) 1337 goto release; 1338 } 1339 1340 /* Set Inband ULP Exit, Reset to SMBus mode and 1341 * Disable SMBus Release on PERST# in PHY 1342 */ 1343 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1344 if (ret_val) 1345 goto release; 1346 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | 1347 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1348 if (to_sx) { 1349 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC) 1350 phy_reg |= I218_ULP_CONFIG1_WOL_HOST; 1351 else 1352 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1353 1354 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; 1355 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT; 1356 } else { 1357 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; 1358 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP; 1359 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1360 } 1361 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1362 1363 /* Set Disable SMBus Release on PERST# in MAC */ 1364 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7); 1365 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; 1366 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg); 1367 1368 /* Commit ULP changes in PHY by starting auto ULP configuration */ 1369 phy_reg |= I218_ULP_CONFIG1_START; 1370 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1371 1372 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && 1373 to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 1374 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1375 oem_reg); 1376 if (ret_val) 1377 goto release; 1378 } 1379 1380 release: 1381 hw->phy.ops.release(hw); 1382 out: 1383 if (ret_val) 1384 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val); 1385 else 1386 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; 1387 1388 return ret_val; 1389 } 1390 1391 /** 1392 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1393 * @hw: pointer to the HW structure 1394 * @force: boolean indicating whether or not to force disabling ULP 1395 * 1396 * Un-configure ULP mode when link is up, the system is transitioned from 1397 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1398 * system, poll for an indication from ME that ULP has been un-configured. 1399 * If not on an ME enabled system, un-configure the ULP mode by software. 1400 * 1401 * During nominal operation, this function is called when link is acquired 1402 * to disable ULP mode (force=FALSE); otherwise, for example when unloading 1403 * the driver or during Sx->S0 transitions, this is called with force=TRUE 1404 * to forcibly disable ULP. 1405 */ 1406 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) 1407 { 1408 s32 ret_val = E1000_SUCCESS; 1409 u32 mac_reg; 1410 u16 phy_reg; 1411 int i = 0; 1412 1413 if ((hw->mac.type < e1000_pch_lpt) || 1414 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || 1415 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || 1416 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || 1417 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) || 1418 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) 1419 return 0; 1420 1421 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) { 1422 if (force) { 1423 /* Request ME un-configure ULP mode in the PHY */ 1424 mac_reg = E1000_READ_REG(hw, E1000_H2ME); 1425 mac_reg &= ~E1000_H2ME_ULP; 1426 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1427 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); 1428 } 1429 1430 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */ 1431 while (E1000_READ_REG(hw, E1000_FWSM) & 1432 E1000_FWSM_ULP_CFG_DONE) { 1433 if (i++ == 30) { 1434 ret_val = -E1000_ERR_PHY; 1435 goto out; 1436 } 1437 1438 msec_delay(10); 1439 } 1440 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10); 1441 1442 if (force) { 1443 mac_reg = E1000_READ_REG(hw, E1000_H2ME); 1444 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1445 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); 1446 } else { 1447 /* Clear H2ME.ULP after ME ULP configuration */ 1448 mac_reg = E1000_READ_REG(hw, E1000_H2ME); 1449 mac_reg &= ~E1000_H2ME_ULP; 1450 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); 1451 } 1452 1453 goto out; 1454 } 1455 1456 ret_val = hw->phy.ops.acquire(hw); 1457 if (ret_val) 1458 goto out; 1459 1460 if (force) 1461 /* Toggle LANPHYPC Value bit */ 1462 e1000_toggle_lanphypc_pch_lpt(hw); 1463 1464 /* Unforce SMBus mode in PHY */ 1465 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1466 if (ret_val) { 1467 /* The MAC might be in PCIe mode, so temporarily force to 1468 * SMBus mode in order to access the PHY. 1469 */ 1470 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1471 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1472 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 1473 1474 msec_delay(50); 1475 1476 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, 1477 &phy_reg); 1478 if (ret_val) 1479 goto release; 1480 } 1481 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1482 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1483 1484 /* Unforce SMBus mode in MAC */ 1485 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1486 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1487 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 1488 1489 /* When ULP mode was previously entered, K1 was disabled by the 1490 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1491 */ 1492 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); 1493 if (ret_val) 1494 goto release; 1495 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1496 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); 1497 1498 /* Clear ULP enabled configuration */ 1499 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1500 if (ret_val) 1501 goto release; 1502 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1503 I218_ULP_CONFIG1_STICKY_ULP | 1504 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1505 I218_ULP_CONFIG1_WOL_HOST | 1506 I218_ULP_CONFIG1_INBAND_EXIT | 1507 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1508 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1509 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1510 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1511 1512 /* Commit ULP changes by starting auto ULP configuration */ 1513 phy_reg |= I218_ULP_CONFIG1_START; 1514 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1515 1516 /* Clear Disable SMBus Release on PERST# in MAC */ 1517 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7); 1518 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1519 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg); 1520 1521 release: 1522 hw->phy.ops.release(hw); 1523 if (force) { 1524 hw->phy.ops.reset(hw); 1525 msec_delay(50); 1526 } 1527 out: 1528 if (ret_val) 1529 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val); 1530 else 1531 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; 1532 1533 return ret_val; 1534 } 1535 1536 /** 1537 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 1538 * @hw: pointer to the HW structure 1539 * 1540 * Checks to see of the link status of the hardware has changed. If a 1541 * change in link status has been detected, then we read the PHY registers 1542 * to get the current speed/duplex if link exists. 1543 **/ 1544 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1545 { 1546 struct e1000_mac_info *mac = &hw->mac; 1547 s32 ret_val, tipg_reg = 0; 1548 u16 emi_addr, emi_val = 0; 1549 bool link; 1550 u16 phy_reg; 1551 1552 DEBUGFUNC("e1000_check_for_copper_link_ich8lan"); 1553 1554 /* We only want to go out to the PHY registers to see if Auto-Neg 1555 * has completed and/or if our link status has changed. The 1556 * get_link_status flag is set upon receiving a Link Status 1557 * Change or Rx Sequence Error interrupt. 1558 */ 1559 if (!mac->get_link_status) 1560 return E1000_SUCCESS; 1561 1562 /* First we want to see if the MII Status Register reports 1563 * link. If so, then we want to get the current speed/duplex 1564 * of the PHY. 1565 */ 1566 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1567 if (ret_val) 1568 return ret_val; 1569 1570 if (hw->mac.type == e1000_pchlan) { 1571 ret_val = e1000_k1_gig_workaround_hv(hw, link); 1572 if (ret_val) 1573 return ret_val; 1574 } 1575 1576 /* When connected at 10Mbps half-duplex, some parts are excessively 1577 * aggressive resulting in many collisions. To avoid this, increase 1578 * the IPG and reduce Rx latency in the PHY. 1579 */ 1580 if ((hw->mac.type >= e1000_pch2lan) && link) { 1581 u16 speed, duplex; 1582 1583 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex); 1584 tipg_reg = E1000_READ_REG(hw, E1000_TIPG); 1585 tipg_reg &= ~E1000_TIPG_IPGT_MASK; 1586 1587 if (duplex == HALF_DUPLEX && speed == SPEED_10) { 1588 tipg_reg |= 0xFF; 1589 /* Reduce Rx latency in analog PHY */ 1590 emi_val = 0; 1591 } else if (hw->mac.type >= e1000_pch_spt && 1592 duplex == FULL_DUPLEX && speed != SPEED_1000) { 1593 tipg_reg |= 0xC; 1594 emi_val = 1; 1595 } else { 1596 /* Roll back the default values */ 1597 tipg_reg |= 0x08; 1598 emi_val = 1; 1599 } 1600 1601 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg); 1602 1603 ret_val = hw->phy.ops.acquire(hw); 1604 if (ret_val) 1605 return ret_val; 1606 1607 if (hw->mac.type == e1000_pch2lan) 1608 emi_addr = I82579_RX_CONFIG; 1609 else 1610 emi_addr = I217_RX_CONFIG; 1611 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); 1612 1613 if (hw->mac.type >= e1000_pch_lpt) { 1614 u16 phy_reg; 1615 1616 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG, 1617 &phy_reg); 1618 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK; 1619 if (speed == SPEED_100 || speed == SPEED_10) 1620 phy_reg |= 0x3E8; 1621 else 1622 phy_reg |= 0xFA; 1623 hw->phy.ops.write_reg_locked(hw, 1624 I217_PLL_CLOCK_GATE_REG, 1625 phy_reg); 1626 1627 if (speed == SPEED_1000) { 1628 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, 1629 &phy_reg); 1630 1631 phy_reg |= HV_PM_CTRL_K1_CLK_REQ; 1632 1633 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, 1634 phy_reg); 1635 } 1636 } 1637 hw->phy.ops.release(hw); 1638 1639 if (ret_val) 1640 return ret_val; 1641 1642 if (hw->mac.type >= e1000_pch_spt) { 1643 u16 data; 1644 u16 ptr_gap; 1645 1646 if (speed == SPEED_1000) { 1647 ret_val = hw->phy.ops.acquire(hw); 1648 if (ret_val) 1649 return ret_val; 1650 1651 ret_val = hw->phy.ops.read_reg_locked(hw, 1652 PHY_REG(776, 20), 1653 &data); 1654 if (ret_val) { 1655 hw->phy.ops.release(hw); 1656 return ret_val; 1657 } 1658 1659 ptr_gap = (data & (0x3FF << 2)) >> 2; 1660 if (ptr_gap < 0x18) { 1661 data &= ~(0x3FF << 2); 1662 data |= (0x18 << 2); 1663 ret_val = 1664 hw->phy.ops.write_reg_locked(hw, 1665 PHY_REG(776, 20), data); 1666 } 1667 hw->phy.ops.release(hw); 1668 if (ret_val) 1669 return ret_val; 1670 } else { 1671 ret_val = hw->phy.ops.acquire(hw); 1672 if (ret_val) 1673 return ret_val; 1674 1675 ret_val = hw->phy.ops.write_reg_locked(hw, 1676 PHY_REG(776, 20), 1677 0xC023); 1678 hw->phy.ops.release(hw); 1679 if (ret_val) 1680 return ret_val; 1681 1682 } 1683 } 1684 } 1685 1686 /* I217 Packet Loss issue: 1687 * ensure that FEXTNVM4 Beacon Duration is set correctly 1688 * on power up. 1689 * Set the Beacon Duration for I217 to 8 usec 1690 */ 1691 if (hw->mac.type >= e1000_pch_lpt) { 1692 u32 mac_reg; 1693 1694 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4); 1695 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1696 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1697 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg); 1698 } 1699 1700 /* Work-around I218 hang issue */ 1701 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1702 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 1703 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) || 1704 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) { 1705 ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1706 if (ret_val) 1707 return ret_val; 1708 } 1709 if (hw->mac.type >= e1000_pch_lpt) { 1710 /* Set platform power management values for 1711 * Latency Tolerance Reporting (LTR) 1712 * Optimized Buffer Flush/Fill (OBFF) 1713 */ 1714 ret_val = e1000_platform_pm_pch_lpt(hw, link); 1715 if (ret_val) 1716 return ret_val; 1717 } 1718 1719 /* Clear link partner's EEE ability */ 1720 hw->dev_spec.ich8lan.eee_lp_ability = 0; 1721 1722 /* FEXTNVM6 K1-off workaround - for SPT only */ 1723 if (hw->mac.type == e1000_pch_spt) { 1724 u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG); 1725 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); 1726 1727 if ((pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) && 1728 (hw->dev_spec.ich8lan.disable_k1_off == FALSE)) 1729 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE; 1730 else 1731 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; 1732 1733 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6); 1734 } 1735 1736 if (!link) 1737 return E1000_SUCCESS; /* No link detected */ 1738 1739 mac->get_link_status = FALSE; 1740 1741 switch (hw->mac.type) { 1742 case e1000_pch2lan: 1743 ret_val = e1000_k1_workaround_lv(hw); 1744 if (ret_val) 1745 return ret_val; 1746 /* fall-thru */ 1747 case e1000_pchlan: 1748 if (hw->phy.type == e1000_phy_82578) { 1749 ret_val = e1000_link_stall_workaround_hv(hw); 1750 if (ret_val) 1751 return ret_val; 1752 } 1753 1754 /* Workaround for PCHx parts in half-duplex: 1755 * Set the number of preambles removed from the packet 1756 * when it is passed from the PHY to the MAC to prevent 1757 * the MAC from misinterpreting the packet type. 1758 */ 1759 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1760 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1761 1762 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) != 1763 E1000_STATUS_FD) 1764 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1765 1766 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1767 break; 1768 default: 1769 break; 1770 } 1771 1772 /* Check if there was DownShift, must be checked 1773 * immediately after link-up 1774 */ 1775 e1000_check_downshift_generic(hw); 1776 1777 /* Enable/Disable EEE after link up */ 1778 if (hw->phy.type > e1000_phy_82579) { 1779 ret_val = e1000_set_eee_pchlan(hw); 1780 if (ret_val) 1781 return ret_val; 1782 } 1783 1784 /* If we are forcing speed/duplex, then we simply return since 1785 * we have already determined whether we have link or not. 1786 */ 1787 if (!mac->autoneg) 1788 return -E1000_ERR_CONFIG; 1789 1790 /* Auto-Neg is enabled. Auto Speed Detection takes care 1791 * of MAC speed/duplex configuration. So we only need to 1792 * configure Collision Distance in the MAC. 1793 */ 1794 mac->ops.config_collision_dist(hw); 1795 1796 /* Configure Flow Control now that Auto-Neg has completed. 1797 * First, we need to restore the desired flow control 1798 * settings because we may have had to re-autoneg with a 1799 * different link partner. 1800 */ 1801 ret_val = e1000_config_fc_after_link_up_generic(hw); 1802 if (ret_val) 1803 DEBUGOUT("Error configuring flow control\n"); 1804 1805 return ret_val; 1806 } 1807 1808 /** 1809 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers 1810 * @hw: pointer to the HW structure 1811 * 1812 * Initialize family-specific function pointers for PHY, MAC, and NVM. 1813 **/ 1814 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) 1815 { 1816 DEBUGFUNC("e1000_init_function_pointers_ich8lan"); 1817 1818 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; 1819 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; 1820 switch (hw->mac.type) { 1821 case e1000_ich8lan: 1822 case e1000_ich9lan: 1823 case e1000_ich10lan: 1824 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; 1825 break; 1826 case e1000_pchlan: 1827 case e1000_pch2lan: 1828 case e1000_pch_lpt: 1829 case e1000_pch_spt: 1830 case e1000_pch_cnp: 1831 hw->phy.ops.init_params = e1000_init_phy_params_pchlan; 1832 break; 1833 default: 1834 break; 1835 } 1836 } 1837 1838 /** 1839 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1840 * @hw: pointer to the HW structure 1841 * 1842 * Acquires the mutex for performing NVM operations. 1843 **/ 1844 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw) 1845 { 1846 DEBUGFUNC("e1000_acquire_nvm_ich8lan"); 1847 1848 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex); 1849 1850 return E1000_SUCCESS; 1851 } 1852 1853 /** 1854 * e1000_release_nvm_ich8lan - Release NVM mutex 1855 * @hw: pointer to the HW structure 1856 * 1857 * Releases the mutex used while performing NVM operations. 1858 **/ 1859 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw) 1860 { 1861 DEBUGFUNC("e1000_release_nvm_ich8lan"); 1862 1863 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex); 1864 1865 return; 1866 } 1867 1868 /** 1869 * e1000_acquire_swflag_ich8lan - Acquire software control flag 1870 * @hw: pointer to the HW structure 1871 * 1872 * Acquires the software control flag for performing PHY and select 1873 * MAC CSR accesses. 1874 **/ 1875 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1876 { 1877 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1878 s32 ret_val = E1000_SUCCESS; 1879 1880 DEBUGFUNC("e1000_acquire_swflag_ich8lan"); 1881 1882 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex); 1883 1884 while (timeout) { 1885 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1886 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1887 break; 1888 1889 msec_delay_irq(1); 1890 timeout--; 1891 } 1892 1893 if (!timeout) { 1894 DEBUGOUT("SW has already locked the resource.\n"); 1895 ret_val = -E1000_ERR_CONFIG; 1896 goto out; 1897 } 1898 1899 timeout = SW_FLAG_TIMEOUT; 1900 1901 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1902 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 1903 1904 while (timeout) { 1905 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1906 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1907 break; 1908 1909 msec_delay_irq(1); 1910 timeout--; 1911 } 1912 1913 if (!timeout) { 1914 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1915 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl); 1916 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1917 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 1918 ret_val = -E1000_ERR_CONFIG; 1919 goto out; 1920 } 1921 1922 out: 1923 if (ret_val) 1924 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 1925 1926 return ret_val; 1927 } 1928 1929 /** 1930 * e1000_release_swflag_ich8lan - Release software control flag 1931 * @hw: pointer to the HW structure 1932 * 1933 * Releases the software control flag for performing PHY and select 1934 * MAC CSR accesses. 1935 **/ 1936 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1937 { 1938 u32 extcnf_ctrl; 1939 1940 DEBUGFUNC("e1000_release_swflag_ich8lan"); 1941 1942 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1943 1944 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1945 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1946 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 1947 } else { 1948 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n"); 1949 } 1950 1951 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 1952 1953 return; 1954 } 1955 1956 /** 1957 * e1000_check_mng_mode_ich8lan - Checks management mode 1958 * @hw: pointer to the HW structure 1959 * 1960 * This checks if the adapter has any manageability enabled. 1961 * This is a function pointer entry point only called by read/write 1962 * routines for the PHY and NVM parts. 1963 **/ 1964 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1965 { 1966 u32 fwsm; 1967 1968 DEBUGFUNC("e1000_check_mng_mode_ich8lan"); 1969 1970 fwsm = E1000_READ_REG(hw, E1000_FWSM); 1971 1972 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1973 ((fwsm & E1000_FWSM_MODE_MASK) == 1974 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1975 } 1976 1977 /** 1978 * e1000_check_mng_mode_pchlan - Checks management mode 1979 * @hw: pointer to the HW structure 1980 * 1981 * This checks if the adapter has iAMT enabled. 1982 * This is a function pointer entry point only called by read/write 1983 * routines for the PHY and NVM parts. 1984 **/ 1985 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 1986 { 1987 u32 fwsm; 1988 1989 DEBUGFUNC("e1000_check_mng_mode_pchlan"); 1990 1991 fwsm = E1000_READ_REG(hw, E1000_FWSM); 1992 1993 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1994 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1995 } 1996 1997 /** 1998 * e1000_rar_set_pch2lan - Set receive address register 1999 * @hw: pointer to the HW structure 2000 * @addr: pointer to the receive address 2001 * @index: receive address array register 2002 * 2003 * Sets the receive address array register at index to the address passed 2004 * in by addr. For 82579, RAR[0] is the base address register that is to 2005 * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 2006 * Use SHRA[0-3] in place of those reserved for ME. 2007 **/ 2008 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 2009 { 2010 u32 rar_low, rar_high; 2011 2012 DEBUGFUNC("e1000_rar_set_pch2lan"); 2013 2014 /* HW expects these in little endian so we reverse the byte order 2015 * from network order (big endian) to little endian 2016 */ 2017 rar_low = ((u32) addr[0] | 2018 ((u32) addr[1] << 8) | 2019 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 2020 2021 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 2022 2023 /* If MAC address zero, no need to set the AV bit */ 2024 if (rar_low || rar_high) 2025 rar_high |= E1000_RAH_AV; 2026 2027 if (index == 0) { 2028 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 2029 E1000_WRITE_FLUSH(hw); 2030 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 2031 E1000_WRITE_FLUSH(hw); 2032 return E1000_SUCCESS; 2033 } 2034 2035 /* RAR[1-6] are owned by manageability. Skip those and program the 2036 * next address into the SHRA register array. 2037 */ 2038 if (index < (u32) (hw->mac.rar_entry_count)) { 2039 s32 ret_val; 2040 2041 ret_val = e1000_acquire_swflag_ich8lan(hw); 2042 if (ret_val) 2043 goto out; 2044 2045 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low); 2046 E1000_WRITE_FLUSH(hw); 2047 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high); 2048 E1000_WRITE_FLUSH(hw); 2049 2050 e1000_release_swflag_ich8lan(hw); 2051 2052 /* verify the register updates */ 2053 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) && 2054 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high)) 2055 return E1000_SUCCESS; 2056 2057 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 2058 (index - 1), E1000_READ_REG(hw, E1000_FWSM)); 2059 } 2060 2061 out: 2062 DEBUGOUT1("Failed to write receive address at index %d\n", index); 2063 return -E1000_ERR_CONFIG; 2064 } 2065 2066 /** 2067 * e1000_rar_set_pch_lpt - Set receive address registers 2068 * @hw: pointer to the HW structure 2069 * @addr: pointer to the receive address 2070 * @index: receive address array register 2071 * 2072 * Sets the receive address register array at index to the address passed 2073 * in by addr. For LPT, RAR[0] is the base address register that is to 2074 * contain the MAC address. SHRA[0-10] are the shared receive address 2075 * registers that are shared between the Host and manageability engine (ME). 2076 **/ 2077 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 2078 { 2079 u32 rar_low, rar_high; 2080 u32 wlock_mac; 2081 2082 DEBUGFUNC("e1000_rar_set_pch_lpt"); 2083 2084 /* HW expects these in little endian so we reverse the byte order 2085 * from network order (big endian) to little endian 2086 */ 2087 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 2088 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 2089 2090 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 2091 2092 /* If MAC address zero, no need to set the AV bit */ 2093 if (rar_low || rar_high) 2094 rar_high |= E1000_RAH_AV; 2095 2096 if (index == 0) { 2097 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 2098 E1000_WRITE_FLUSH(hw); 2099 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 2100 E1000_WRITE_FLUSH(hw); 2101 return E1000_SUCCESS; 2102 } 2103 2104 /* The manageability engine (ME) can lock certain SHRAR registers that 2105 * it is using - those registers are unavailable for use. 2106 */ 2107 if (index < hw->mac.rar_entry_count) { 2108 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) & 2109 E1000_FWSM_WLOCK_MAC_MASK; 2110 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 2111 2112 /* Check if all SHRAR registers are locked */ 2113 if (wlock_mac == 1) 2114 goto out; 2115 2116 if ((wlock_mac == 0) || (index <= wlock_mac)) { 2117 s32 ret_val; 2118 2119 ret_val = e1000_acquire_swflag_ich8lan(hw); 2120 2121 if (ret_val) 2122 goto out; 2123 2124 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1), 2125 rar_low); 2126 E1000_WRITE_FLUSH(hw); 2127 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1), 2128 rar_high); 2129 E1000_WRITE_FLUSH(hw); 2130 2131 e1000_release_swflag_ich8lan(hw); 2132 2133 /* verify the register updates */ 2134 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) && 2135 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high)) 2136 return E1000_SUCCESS; 2137 } 2138 } 2139 2140 out: 2141 DEBUGOUT1("Failed to write receive address at index %d\n", index); 2142 return -E1000_ERR_CONFIG; 2143 } 2144 2145 /** 2146 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses 2147 * @hw: pointer to the HW structure 2148 * @mc_addr_list: array of multicast addresses to program 2149 * @mc_addr_count: number of multicast addresses to program 2150 * 2151 * Updates entire Multicast Table Array of the PCH2 MAC and PHY. 2152 * The caller must have a packed mc_addr_list of multicast addresses. 2153 **/ 2154 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, 2155 u8 *mc_addr_list, 2156 u32 mc_addr_count) 2157 { 2158 u16 phy_reg = 0; 2159 int i; 2160 s32 ret_val; 2161 2162 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan"); 2163 2164 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count); 2165 2166 ret_val = hw->phy.ops.acquire(hw); 2167 if (ret_val) 2168 return; 2169 2170 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2171 if (ret_val) 2172 goto release; 2173 2174 for (i = 0; i < hw->mac.mta_reg_count; i++) { 2175 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 2176 (u16)(hw->mac.mta_shadow[i] & 2177 0xFFFF)); 2178 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1), 2179 (u16)((hw->mac.mta_shadow[i] >> 16) & 2180 0xFFFF)); 2181 } 2182 2183 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2184 2185 release: 2186 hw->phy.ops.release(hw); 2187 } 2188 2189 /** 2190 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 2191 * @hw: pointer to the HW structure 2192 * 2193 * Checks if firmware is blocking the reset of the PHY. 2194 * This is a function pointer entry point only called by 2195 * reset routines. 2196 **/ 2197 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 2198 { 2199 u32 fwsm; 2200 bool blocked = FALSE; 2201 int i = 0; 2202 2203 DEBUGFUNC("e1000_check_reset_block_ich8lan"); 2204 2205 do { 2206 fwsm = E1000_READ_REG(hw, E1000_FWSM); 2207 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) { 2208 blocked = TRUE; 2209 msec_delay(10); 2210 continue; 2211 } 2212 blocked = FALSE; 2213 } while (blocked && (i++ < 30)); 2214 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS; 2215 } 2216 2217 /** 2218 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 2219 * @hw: pointer to the HW structure 2220 * 2221 * Assumes semaphore already acquired. 2222 * 2223 **/ 2224 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 2225 { 2226 u16 phy_data; 2227 u32 strap = E1000_READ_REG(hw, E1000_STRAP); 2228 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> 2229 E1000_STRAP_SMT_FREQ_SHIFT; 2230 s32 ret_val; 2231 2232 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 2233 2234 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 2235 if (ret_val) 2236 return ret_val; 2237 2238 phy_data &= ~HV_SMB_ADDR_MASK; 2239 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 2240 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 2241 2242 if (hw->phy.type == e1000_phy_i217) { 2243 /* Restore SMBus frequency */ 2244 if (freq--) { 2245 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 2246 phy_data |= (freq & (1 << 0)) << 2247 HV_SMB_ADDR_FREQ_LOW_SHIFT; 2248 phy_data |= (freq & (1 << 1)) << 2249 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 2250 } else { 2251 DEBUGOUT("Unsupported SMB frequency in PHY\n"); 2252 } 2253 } 2254 2255 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 2256 } 2257 2258 /** 2259 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 2260 * @hw: pointer to the HW structure 2261 * 2262 * SW should configure the LCD from the NVM extended configuration region 2263 * as a workaround for certain parts. 2264 **/ 2265 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 2266 { 2267 struct e1000_phy_info *phy = &hw->phy; 2268 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 2269 s32 ret_val = E1000_SUCCESS; 2270 u16 word_addr, reg_data, reg_addr, phy_page = 0; 2271 2272 DEBUGFUNC("e1000_sw_lcd_config_ich8lan"); 2273 2274 /* Initialize the PHY from the NVM on ICH platforms. This 2275 * is needed due to an issue where the NVM configuration is 2276 * not properly autoloaded after power transitions. 2277 * Therefore, after each PHY reset, we will load the 2278 * configuration data out of the NVM manually. 2279 */ 2280 switch (hw->mac.type) { 2281 case e1000_ich8lan: 2282 if (phy->type != e1000_phy_igp_3) 2283 return ret_val; 2284 2285 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) || 2286 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) { 2287 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 2288 break; 2289 } 2290 /* Fall-thru */ 2291 case e1000_pchlan: 2292 case e1000_pch2lan: 2293 case e1000_pch_lpt: 2294 case e1000_pch_spt: 2295 case e1000_pch_cnp: 2296 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 2297 break; 2298 default: 2299 return ret_val; 2300 } 2301 2302 ret_val = hw->phy.ops.acquire(hw); 2303 if (ret_val) 2304 return ret_val; 2305 2306 data = E1000_READ_REG(hw, E1000_FEXTNVM); 2307 if (!(data & sw_cfg_mask)) 2308 goto release; 2309 2310 /* Make sure HW does not configure LCD from PHY 2311 * extended configuration before SW configuration 2312 */ 2313 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 2314 if ((hw->mac.type < e1000_pch2lan) && 2315 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 2316 goto release; 2317 2318 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); 2319 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 2320 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 2321 if (!cnf_size) 2322 goto release; 2323 2324 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 2325 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 2326 2327 if (((hw->mac.type == e1000_pchlan) && 2328 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 2329 (hw->mac.type > e1000_pchlan)) { 2330 /* HW configures the SMBus address and LEDs when the 2331 * OEM and LCD Write Enable bits are set in the NVM. 2332 * When both NVM bits are cleared, SW will configure 2333 * them instead. 2334 */ 2335 ret_val = e1000_write_smbus_addr(hw); 2336 if (ret_val) 2337 goto release; 2338 2339 data = E1000_READ_REG(hw, E1000_LEDCTL); 2340 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 2341 (u16)data); 2342 if (ret_val) 2343 goto release; 2344 } 2345 2346 /* Configure LCD from extended configuration region. */ 2347 2348 /* cnf_base_addr is in DWORD */ 2349 word_addr = (u16)(cnf_base_addr << 1); 2350 2351 for (i = 0; i < cnf_size; i++) { 2352 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1, 2353 ®_data); 2354 if (ret_val) 2355 goto release; 2356 2357 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1), 2358 1, ®_addr); 2359 if (ret_val) 2360 goto release; 2361 2362 /* Save off the PHY page for future writes. */ 2363 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 2364 phy_page = reg_data; 2365 continue; 2366 } 2367 2368 reg_addr &= PHY_REG_MASK; 2369 reg_addr |= phy_page; 2370 2371 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr, 2372 reg_data); 2373 if (ret_val) 2374 goto release; 2375 } 2376 2377 release: 2378 hw->phy.ops.release(hw); 2379 return ret_val; 2380 } 2381 2382 /** 2383 * e1000_k1_gig_workaround_hv - K1 Si workaround 2384 * @hw: pointer to the HW structure 2385 * @link: link up bool flag 2386 * 2387 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 2388 * from a lower speed. This workaround disables K1 whenever link is at 1Gig 2389 * If link is down, the function will restore the default K1 setting located 2390 * in the NVM. 2391 **/ 2392 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 2393 { 2394 s32 ret_val = E1000_SUCCESS; 2395 u16 status_reg = 0; 2396 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 2397 2398 DEBUGFUNC("e1000_k1_gig_workaround_hv"); 2399 2400 if (hw->mac.type != e1000_pchlan) 2401 return E1000_SUCCESS; 2402 2403 /* Wrap the whole flow with the sw flag */ 2404 ret_val = hw->phy.ops.acquire(hw); 2405 if (ret_val) 2406 return ret_val; 2407 2408 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 2409 if (link) { 2410 if (hw->phy.type == e1000_phy_82578) { 2411 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS, 2412 &status_reg); 2413 if (ret_val) 2414 goto release; 2415 2416 status_reg &= (BM_CS_STATUS_LINK_UP | 2417 BM_CS_STATUS_RESOLVED | 2418 BM_CS_STATUS_SPEED_MASK); 2419 2420 if (status_reg == (BM_CS_STATUS_LINK_UP | 2421 BM_CS_STATUS_RESOLVED | 2422 BM_CS_STATUS_SPEED_1000)) 2423 k1_enable = FALSE; 2424 } 2425 2426 if (hw->phy.type == e1000_phy_82577) { 2427 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS, 2428 &status_reg); 2429 if (ret_val) 2430 goto release; 2431 2432 status_reg &= (HV_M_STATUS_LINK_UP | 2433 HV_M_STATUS_AUTONEG_COMPLETE | 2434 HV_M_STATUS_SPEED_MASK); 2435 2436 if (status_reg == (HV_M_STATUS_LINK_UP | 2437 HV_M_STATUS_AUTONEG_COMPLETE | 2438 HV_M_STATUS_SPEED_1000)) 2439 k1_enable = FALSE; 2440 } 2441 2442 /* Link stall fix for link up */ 2443 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 2444 0x0100); 2445 if (ret_val) 2446 goto release; 2447 2448 } else { 2449 /* Link stall fix for link down */ 2450 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 2451 0x4100); 2452 if (ret_val) 2453 goto release; 2454 } 2455 2456 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 2457 2458 release: 2459 hw->phy.ops.release(hw); 2460 2461 return ret_val; 2462 } 2463 2464 /** 2465 * e1000_configure_k1_ich8lan - Configure K1 power state 2466 * @hw: pointer to the HW structure 2467 * @enable: K1 state to configure 2468 * 2469 * Configure the K1 power state based on the provided parameter. 2470 * Assumes semaphore already acquired. 2471 * 2472 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2473 **/ 2474 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 2475 { 2476 s32 ret_val; 2477 u32 ctrl_reg = 0; 2478 u32 ctrl_ext = 0; 2479 u32 reg = 0; 2480 u16 kmrn_reg = 0; 2481 2482 DEBUGFUNC("e1000_configure_k1_ich8lan"); 2483 2484 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2485 &kmrn_reg); 2486 if (ret_val) 2487 return ret_val; 2488 2489 if (k1_enable) 2490 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 2491 else 2492 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 2493 2494 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2495 kmrn_reg); 2496 if (ret_val) 2497 return ret_val; 2498 2499 usec_delay(20); 2500 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2501 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 2502 2503 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2504 reg |= E1000_CTRL_FRCSPD; 2505 E1000_WRITE_REG(hw, E1000_CTRL, reg); 2506 2507 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 2508 E1000_WRITE_FLUSH(hw); 2509 usec_delay(20); 2510 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 2511 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2512 E1000_WRITE_FLUSH(hw); 2513 usec_delay(20); 2514 2515 return E1000_SUCCESS; 2516 } 2517 2518 /** 2519 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 2520 * @hw: pointer to the HW structure 2521 * @d0_state: boolean if entering d0 or d3 device state 2522 * 2523 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 2524 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 2525 * in NVM determines whether HW should configure LPLU and Gbe Disable. 2526 **/ 2527 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 2528 { 2529 s32 ret_val = 0; 2530 u32 mac_reg; 2531 u16 oem_reg; 2532 2533 DEBUGFUNC("e1000_oem_bits_config_ich8lan"); 2534 2535 if (hw->mac.type < e1000_pchlan) 2536 return ret_val; 2537 2538 ret_val = hw->phy.ops.acquire(hw); 2539 if (ret_val) 2540 return ret_val; 2541 2542 if (hw->mac.type == e1000_pchlan) { 2543 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 2544 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 2545 goto release; 2546 } 2547 2548 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM); 2549 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 2550 goto release; 2551 2552 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 2553 2554 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg); 2555 if (ret_val) 2556 goto release; 2557 2558 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 2559 2560 if (d0_state) { 2561 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 2562 oem_reg |= HV_OEM_BITS_GBE_DIS; 2563 2564 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 2565 oem_reg |= HV_OEM_BITS_LPLU; 2566 } else { 2567 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 2568 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 2569 oem_reg |= HV_OEM_BITS_GBE_DIS; 2570 2571 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 2572 E1000_PHY_CTRL_NOND0A_LPLU)) 2573 oem_reg |= HV_OEM_BITS_LPLU; 2574 } 2575 2576 /* Set Restart auto-neg to activate the bits */ 2577 if ((d0_state || (hw->mac.type != e1000_pchlan)) && 2578 !hw->phy.ops.check_reset_block(hw)) 2579 oem_reg |= HV_OEM_BITS_RESTART_AN; 2580 2581 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg); 2582 2583 release: 2584 hw->phy.ops.release(hw); 2585 2586 return ret_val; 2587 } 2588 2589 2590 /** 2591 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 2592 * @hw: pointer to the HW structure 2593 **/ 2594 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 2595 { 2596 s32 ret_val; 2597 u16 data; 2598 2599 DEBUGFUNC("e1000_set_mdio_slow_mode_hv"); 2600 2601 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data); 2602 if (ret_val) 2603 return ret_val; 2604 2605 data |= HV_KMRN_MDIO_SLOW; 2606 2607 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data); 2608 2609 return ret_val; 2610 } 2611 2612 /** 2613 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2614 * done after every PHY reset. 2615 **/ 2616 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2617 { 2618 s32 ret_val = E1000_SUCCESS; 2619 u16 phy_data; 2620 2621 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan"); 2622 2623 if (hw->mac.type != e1000_pchlan) 2624 return E1000_SUCCESS; 2625 2626 /* Set MDIO slow mode before any other MDIO access */ 2627 if (hw->phy.type == e1000_phy_82577) { 2628 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2629 if (ret_val) 2630 return ret_val; 2631 } 2632 2633 if (((hw->phy.type == e1000_phy_82577) && 2634 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 2635 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 2636 /* Disable generation of early preamble */ 2637 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); 2638 if (ret_val) 2639 return ret_val; 2640 2641 /* Preamble tuning for SSC */ 2642 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, 2643 0xA204); 2644 if (ret_val) 2645 return ret_val; 2646 } 2647 2648 if (hw->phy.type == e1000_phy_82578) { 2649 /* Return registers to default by doing a soft reset then 2650 * writing 0x3140 to the control register. 2651 */ 2652 if (hw->phy.revision < 2) { 2653 e1000_phy_sw_reset_generic(hw); 2654 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, 2655 0x3140); 2656 } 2657 } 2658 2659 /* Select page 0 */ 2660 ret_val = hw->phy.ops.acquire(hw); 2661 if (ret_val) 2662 return ret_val; 2663 2664 hw->phy.addr = 1; 2665 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 2666 hw->phy.ops.release(hw); 2667 if (ret_val) 2668 return ret_val; 2669 2670 /* Configure the K1 Si workaround during phy reset assuming there is 2671 * link so that it disables K1 if link is in 1Gbps. 2672 */ 2673 ret_val = e1000_k1_gig_workaround_hv(hw, TRUE); 2674 if (ret_val) 2675 return ret_val; 2676 2677 /* Workaround for link disconnects on a busy hub in half duplex */ 2678 ret_val = hw->phy.ops.acquire(hw); 2679 if (ret_val) 2680 return ret_val; 2681 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data); 2682 if (ret_val) 2683 goto release; 2684 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG, 2685 phy_data & 0x00FF); 2686 if (ret_val) 2687 goto release; 2688 2689 /* set MSE higher to enable link to stay up when noise is high */ 2690 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 2691 release: 2692 hw->phy.ops.release(hw); 2693 2694 return ret_val; 2695 } 2696 2697 /** 2698 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 2699 * @hw: pointer to the HW structure 2700 **/ 2701 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 2702 { 2703 u32 mac_reg; 2704 u16 i, phy_reg = 0; 2705 s32 ret_val; 2706 2707 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan"); 2708 2709 ret_val = hw->phy.ops.acquire(hw); 2710 if (ret_val) 2711 return; 2712 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2713 if (ret_val) 2714 goto release; 2715 2716 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */ 2717 for (i = 0; i < (hw->mac.rar_entry_count); i++) { 2718 mac_reg = E1000_READ_REG(hw, E1000_RAL(i)); 2719 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 2720 (u16)(mac_reg & 0xFFFF)); 2721 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 2722 (u16)((mac_reg >> 16) & 0xFFFF)); 2723 2724 mac_reg = E1000_READ_REG(hw, E1000_RAH(i)); 2725 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 2726 (u16)(mac_reg & 0xFFFF)); 2727 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 2728 (u16)((mac_reg & E1000_RAH_AV) 2729 >> 16)); 2730 } 2731 2732 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2733 2734 release: 2735 hw->phy.ops.release(hw); 2736 } 2737 2738 static u32 e1000_calc_rx_da_crc(u8 mac[]) 2739 { 2740 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */ 2741 u32 i, j, mask, crc; 2742 2743 DEBUGFUNC("e1000_calc_rx_da_crc"); 2744 2745 crc = 0xffffffff; 2746 for (i = 0; i < 6; i++) { 2747 crc = crc ^ mac[i]; 2748 for (j = 8; j > 0; j--) { 2749 mask = (crc & 1) * (-1); 2750 crc = (crc >> 1) ^ (poly & mask); 2751 } 2752 } 2753 return ~crc; 2754 } 2755 2756 /** 2757 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 2758 * with 82579 PHY 2759 * @hw: pointer to the HW structure 2760 * @enable: flag to enable/disable workaround when enabling/disabling jumbos 2761 **/ 2762 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 2763 { 2764 s32 ret_val = E1000_SUCCESS; 2765 u16 phy_reg, data; 2766 u32 mac_reg; 2767 u16 i; 2768 2769 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan"); 2770 2771 if (hw->mac.type < e1000_pch2lan) 2772 return E1000_SUCCESS; 2773 2774 /* disable Rx path while enabling/disabling workaround */ 2775 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg); 2776 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), 2777 phy_reg | (1 << 14)); 2778 if (ret_val) 2779 return ret_val; 2780 2781 if (enable) { 2782 /* Write Rx addresses (rar_entry_count for RAL/H, and 2783 * SHRAL/H) and initial CRC values to the MAC 2784 */ 2785 for (i = 0; i < hw->mac.rar_entry_count; i++) { 2786 u8 mac_addr[ETH_ADDR_LEN] = {0}; 2787 u32 addr_high, addr_low; 2788 2789 addr_high = E1000_READ_REG(hw, E1000_RAH(i)); 2790 if (!(addr_high & E1000_RAH_AV)) 2791 continue; 2792 addr_low = E1000_READ_REG(hw, E1000_RAL(i)); 2793 mac_addr[0] = (addr_low & 0xFF); 2794 mac_addr[1] = ((addr_low >> 8) & 0xFF); 2795 mac_addr[2] = ((addr_low >> 16) & 0xFF); 2796 mac_addr[3] = ((addr_low >> 24) & 0xFF); 2797 mac_addr[4] = (addr_high & 0xFF); 2798 mac_addr[5] = ((addr_high >> 8) & 0xFF); 2799 2800 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i), 2801 e1000_calc_rx_da_crc(mac_addr)); 2802 } 2803 2804 /* Write Rx addresses to the PHY */ 2805 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 2806 2807 /* Enable jumbo frame workaround in the MAC */ 2808 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); 2809 mac_reg &= ~(1 << 14); 2810 mac_reg |= (7 << 15); 2811 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg); 2812 2813 mac_reg = E1000_READ_REG(hw, E1000_RCTL); 2814 mac_reg |= E1000_RCTL_SECRC; 2815 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg); 2816 2817 ret_val = e1000_read_kmrn_reg_generic(hw, 2818 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2819 &data); 2820 if (ret_val) 2821 return ret_val; 2822 ret_val = e1000_write_kmrn_reg_generic(hw, 2823 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2824 data | (1 << 0)); 2825 if (ret_val) 2826 return ret_val; 2827 ret_val = e1000_read_kmrn_reg_generic(hw, 2828 E1000_KMRNCTRLSTA_HD_CTRL, 2829 &data); 2830 if (ret_val) 2831 return ret_val; 2832 data &= ~(0xF << 8); 2833 data |= (0xB << 8); 2834 ret_val = e1000_write_kmrn_reg_generic(hw, 2835 E1000_KMRNCTRLSTA_HD_CTRL, 2836 data); 2837 if (ret_val) 2838 return ret_val; 2839 2840 /* Enable jumbo frame workaround in the PHY */ 2841 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); 2842 data &= ~(0x7F << 5); 2843 data |= (0x37 << 5); 2844 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); 2845 if (ret_val) 2846 return ret_val; 2847 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); 2848 data &= ~(1 << 13); 2849 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); 2850 if (ret_val) 2851 return ret_val; 2852 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); 2853 data &= ~(0x3FF << 2); 2854 data |= (E1000_TX_PTR_GAP << 2); 2855 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); 2856 if (ret_val) 2857 return ret_val; 2858 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100); 2859 if (ret_val) 2860 return ret_val; 2861 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); 2862 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data | 2863 (1 << 10)); 2864 if (ret_val) 2865 return ret_val; 2866 } else { 2867 /* Write MAC register values back to h/w defaults */ 2868 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); 2869 mac_reg &= ~(0xF << 14); 2870 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg); 2871 2872 mac_reg = E1000_READ_REG(hw, E1000_RCTL); 2873 mac_reg &= ~E1000_RCTL_SECRC; 2874 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg); 2875 2876 ret_val = e1000_read_kmrn_reg_generic(hw, 2877 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2878 &data); 2879 if (ret_val) 2880 return ret_val; 2881 ret_val = e1000_write_kmrn_reg_generic(hw, 2882 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2883 data & ~(1 << 0)); 2884 if (ret_val) 2885 return ret_val; 2886 ret_val = e1000_read_kmrn_reg_generic(hw, 2887 E1000_KMRNCTRLSTA_HD_CTRL, 2888 &data); 2889 if (ret_val) 2890 return ret_val; 2891 data &= ~(0xF << 8); 2892 data |= (0xB << 8); 2893 ret_val = e1000_write_kmrn_reg_generic(hw, 2894 E1000_KMRNCTRLSTA_HD_CTRL, 2895 data); 2896 if (ret_val) 2897 return ret_val; 2898 2899 /* Write PHY register values back to h/w defaults */ 2900 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); 2901 data &= ~(0x7F << 5); 2902 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); 2903 if (ret_val) 2904 return ret_val; 2905 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); 2906 data |= (1 << 13); 2907 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); 2908 if (ret_val) 2909 return ret_val; 2910 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); 2911 data &= ~(0x3FF << 2); 2912 data |= (0x8 << 2); 2913 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); 2914 if (ret_val) 2915 return ret_val; 2916 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00); 2917 if (ret_val) 2918 return ret_val; 2919 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); 2920 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data & 2921 ~(1 << 10)); 2922 if (ret_val) 2923 return ret_val; 2924 } 2925 2926 /* re-enable Rx path after enabling/disabling workaround */ 2927 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg & 2928 ~(1 << 14)); 2929 } 2930 2931 /** 2932 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2933 * done after every PHY reset. 2934 **/ 2935 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2936 { 2937 s32 ret_val = E1000_SUCCESS; 2938 2939 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan"); 2940 2941 if (hw->mac.type != e1000_pch2lan) 2942 return E1000_SUCCESS; 2943 2944 /* Set MDIO slow mode before any other MDIO access */ 2945 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2946 if (ret_val) 2947 return ret_val; 2948 2949 ret_val = hw->phy.ops.acquire(hw); 2950 if (ret_val) 2951 return ret_val; 2952 /* set MSE higher to enable link to stay up when noise is high */ 2953 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 2954 if (ret_val) 2955 goto release; 2956 /* drop link after 5 times MSE threshold was reached */ 2957 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 2958 release: 2959 hw->phy.ops.release(hw); 2960 2961 return ret_val; 2962 } 2963 2964 /** 2965 * e1000_k1_gig_workaround_lv - K1 Si workaround 2966 * @hw: pointer to the HW structure 2967 * 2968 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps 2969 * Disable K1 for 1000 and 100 speeds 2970 **/ 2971 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 2972 { 2973 s32 ret_val = E1000_SUCCESS; 2974 u16 status_reg = 0; 2975 2976 DEBUGFUNC("e1000_k1_workaround_lv"); 2977 2978 if (hw->mac.type != e1000_pch2lan) 2979 return E1000_SUCCESS; 2980 2981 /* Set K1 beacon duration based on 10Mbs speed */ 2982 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg); 2983 if (ret_val) 2984 return ret_val; 2985 2986 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 2987 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 2988 if (status_reg & 2989 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) { 2990 u16 pm_phy_reg; 2991 2992 /* LV 1G/100 Packet drop issue wa */ 2993 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL, 2994 &pm_phy_reg); 2995 if (ret_val) 2996 return ret_val; 2997 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE; 2998 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, 2999 pm_phy_reg); 3000 if (ret_val) 3001 return ret_val; 3002 } else { 3003 u32 mac_reg; 3004 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4); 3005 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 3006 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 3007 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg); 3008 } 3009 } 3010 3011 return ret_val; 3012 } 3013 3014 /** 3015 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 3016 * @hw: pointer to the HW structure 3017 * @gate: boolean set to TRUE to gate, FALSE to ungate 3018 * 3019 * Gate/ungate the automatic PHY configuration via hardware; perform 3020 * the configuration via software instead. 3021 **/ 3022 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 3023 { 3024 u32 extcnf_ctrl; 3025 3026 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan"); 3027 3028 if (hw->mac.type < e1000_pch2lan) 3029 return; 3030 3031 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 3032 3033 if (gate) 3034 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 3035 else 3036 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 3037 3038 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 3039 } 3040 3041 /** 3042 * e1000_lan_init_done_ich8lan - Check for PHY config completion 3043 * @hw: pointer to the HW structure 3044 * 3045 * Check the appropriate indication the MAC has finished configuring the 3046 * PHY after a software reset. 3047 **/ 3048 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 3049 { 3050 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 3051 3052 DEBUGFUNC("e1000_lan_init_done_ich8lan"); 3053 3054 /* Wait for basic configuration completes before proceeding */ 3055 do { 3056 data = E1000_READ_REG(hw, E1000_STATUS); 3057 data &= E1000_STATUS_LAN_INIT_DONE; 3058 usec_delay(100); 3059 } while ((!data) && --loop); 3060 3061 /* If basic configuration is incomplete before the above loop 3062 * count reaches 0, loading the configuration from NVM will 3063 * leave the PHY in a bad state possibly resulting in no link. 3064 */ 3065 if (loop == 0) 3066 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n"); 3067 3068 /* Clear the Init Done bit for the next init event */ 3069 data = E1000_READ_REG(hw, E1000_STATUS); 3070 data &= ~E1000_STATUS_LAN_INIT_DONE; 3071 E1000_WRITE_REG(hw, E1000_STATUS, data); 3072 } 3073 3074 /** 3075 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 3076 * @hw: pointer to the HW structure 3077 **/ 3078 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 3079 { 3080 s32 ret_val = E1000_SUCCESS; 3081 u16 reg; 3082 3083 DEBUGFUNC("e1000_post_phy_reset_ich8lan"); 3084 3085 if (hw->phy.ops.check_reset_block(hw)) 3086 return E1000_SUCCESS; 3087 3088 /* Allow time for h/w to get to quiescent state after reset */ 3089 msec_delay(10); 3090 3091 /* Perform any necessary post-reset workarounds */ 3092 switch (hw->mac.type) { 3093 case e1000_pchlan: 3094 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 3095 if (ret_val) 3096 return ret_val; 3097 break; 3098 case e1000_pch2lan: 3099 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 3100 if (ret_val) 3101 return ret_val; 3102 break; 3103 default: 3104 break; 3105 } 3106 3107 /* Clear the host wakeup bit after lcd reset */ 3108 if (hw->mac.type >= e1000_pchlan) { 3109 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®); 3110 reg &= ~BM_WUC_HOST_WU_BIT; 3111 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg); 3112 } 3113 3114 /* Configure the LCD with the extended configuration region in NVM */ 3115 ret_val = e1000_sw_lcd_config_ich8lan(hw); 3116 if (ret_val) 3117 return ret_val; 3118 3119 /* Configure the LCD with the OEM bits in NVM */ 3120 ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE); 3121 3122 if (hw->mac.type == e1000_pch2lan) { 3123 /* Ungate automatic PHY configuration on non-managed 82579 */ 3124 if (!(E1000_READ_REG(hw, E1000_FWSM) & 3125 E1000_ICH_FWSM_FW_VALID)) { 3126 msec_delay(10); 3127 e1000_gate_hw_phy_config_ich8lan(hw, FALSE); 3128 } 3129 3130 /* Set EEE LPI Update Timer to 200usec */ 3131 ret_val = hw->phy.ops.acquire(hw); 3132 if (ret_val) 3133 return ret_val; 3134 ret_val = e1000_write_emi_reg_locked(hw, 3135 I82579_LPI_UPDATE_TIMER, 3136 0x1387); 3137 hw->phy.ops.release(hw); 3138 } 3139 3140 return ret_val; 3141 } 3142 3143 /** 3144 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 3145 * @hw: pointer to the HW structure 3146 * 3147 * Resets the PHY 3148 * This is a function pointer entry point called by drivers 3149 * or other shared routines. 3150 **/ 3151 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 3152 { 3153 s32 ret_val = E1000_SUCCESS; 3154 3155 DEBUGFUNC("e1000_phy_hw_reset_ich8lan"); 3156 3157 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 3158 if ((hw->mac.type == e1000_pch2lan) && 3159 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) 3160 e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 3161 3162 ret_val = e1000_phy_hw_reset_generic(hw); 3163 if (ret_val) 3164 return ret_val; 3165 3166 return e1000_post_phy_reset_ich8lan(hw); 3167 } 3168 3169 /** 3170 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 3171 * @hw: pointer to the HW structure 3172 * @active: TRUE to enable LPLU, FALSE to disable 3173 * 3174 * Sets the LPLU state according to the active flag. For PCH, if OEM write 3175 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 3176 * the phy speed. This function will manually set the LPLU bit and restart 3177 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 3178 * since it configures the same bit. 3179 **/ 3180 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 3181 { 3182 s32 ret_val; 3183 u16 oem_reg; 3184 3185 DEBUGFUNC("e1000_set_lplu_state_pchlan"); 3186 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg); 3187 if (ret_val) 3188 return ret_val; 3189 3190 if (active) 3191 oem_reg |= HV_OEM_BITS_LPLU; 3192 else 3193 oem_reg &= ~HV_OEM_BITS_LPLU; 3194 3195 if (!hw->phy.ops.check_reset_block(hw)) 3196 oem_reg |= HV_OEM_BITS_RESTART_AN; 3197 3198 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg); 3199 } 3200 3201 /** 3202 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 3203 * @hw: pointer to the HW structure 3204 * @active: TRUE to enable LPLU, FALSE to disable 3205 * 3206 * Sets the LPLU D0 state according to the active flag. When 3207 * activating LPLU this function also disables smart speed 3208 * and vice versa. LPLU will not be activated unless the 3209 * device autonegotiation advertisement meets standards of 3210 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3211 * This is a function pointer entry point only called by 3212 * PHY setup routines. 3213 **/ 3214 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3215 { 3216 struct e1000_phy_info *phy = &hw->phy; 3217 u32 phy_ctrl; 3218 s32 ret_val = E1000_SUCCESS; 3219 u16 data; 3220 3221 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); 3222 3223 if (phy->type == e1000_phy_ife) 3224 return E1000_SUCCESS; 3225 3226 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 3227 3228 if (active) { 3229 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 3230 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3231 3232 if (phy->type != e1000_phy_igp_3) 3233 return E1000_SUCCESS; 3234 3235 /* Call gig speed drop workaround on LPLU before accessing 3236 * any PHY registers 3237 */ 3238 if (hw->mac.type == e1000_ich8lan) 3239 e1000_gig_downshift_workaround_ich8lan(hw); 3240 3241 /* When LPLU is enabled, we should disable SmartSpeed */ 3242 ret_val = phy->ops.read_reg(hw, 3243 IGP01E1000_PHY_PORT_CONFIG, 3244 &data); 3245 if (ret_val) 3246 return ret_val; 3247 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3248 ret_val = phy->ops.write_reg(hw, 3249 IGP01E1000_PHY_PORT_CONFIG, 3250 data); 3251 if (ret_val) 3252 return ret_val; 3253 } else { 3254 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 3255 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3256 3257 if (phy->type != e1000_phy_igp_3) 3258 return E1000_SUCCESS; 3259 3260 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3261 * during Dx states where the power conservation is most 3262 * important. During driver activity we should enable 3263 * SmartSpeed, so performance is maintained. 3264 */ 3265 if (phy->smart_speed == e1000_smart_speed_on) { 3266 ret_val = phy->ops.read_reg(hw, 3267 IGP01E1000_PHY_PORT_CONFIG, 3268 &data); 3269 if (ret_val) 3270 return ret_val; 3271 3272 data |= IGP01E1000_PSCFR_SMART_SPEED; 3273 ret_val = phy->ops.write_reg(hw, 3274 IGP01E1000_PHY_PORT_CONFIG, 3275 data); 3276 if (ret_val) 3277 return ret_val; 3278 } else if (phy->smart_speed == e1000_smart_speed_off) { 3279 ret_val = phy->ops.read_reg(hw, 3280 IGP01E1000_PHY_PORT_CONFIG, 3281 &data); 3282 if (ret_val) 3283 return ret_val; 3284 3285 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3286 ret_val = phy->ops.write_reg(hw, 3287 IGP01E1000_PHY_PORT_CONFIG, 3288 data); 3289 if (ret_val) 3290 return ret_val; 3291 } 3292 } 3293 3294 return E1000_SUCCESS; 3295 } 3296 3297 /** 3298 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 3299 * @hw: pointer to the HW structure 3300 * @active: TRUE to enable LPLU, FALSE to disable 3301 * 3302 * Sets the LPLU D3 state according to the active flag. When 3303 * activating LPLU this function also disables smart speed 3304 * and vice versa. LPLU will not be activated unless the 3305 * device autonegotiation advertisement meets standards of 3306 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3307 * This is a function pointer entry point only called by 3308 * PHY setup routines. 3309 **/ 3310 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3311 { 3312 struct e1000_phy_info *phy = &hw->phy; 3313 u32 phy_ctrl; 3314 s32 ret_val = E1000_SUCCESS; 3315 u16 data; 3316 3317 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan"); 3318 3319 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 3320 3321 if (!active) { 3322 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 3323 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3324 3325 if (phy->type != e1000_phy_igp_3) 3326 return E1000_SUCCESS; 3327 3328 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3329 * during Dx states where the power conservation is most 3330 * important. During driver activity we should enable 3331 * SmartSpeed, so performance is maintained. 3332 */ 3333 if (phy->smart_speed == e1000_smart_speed_on) { 3334 ret_val = phy->ops.read_reg(hw, 3335 IGP01E1000_PHY_PORT_CONFIG, 3336 &data); 3337 if (ret_val) 3338 return ret_val; 3339 3340 data |= IGP01E1000_PSCFR_SMART_SPEED; 3341 ret_val = phy->ops.write_reg(hw, 3342 IGP01E1000_PHY_PORT_CONFIG, 3343 data); 3344 if (ret_val) 3345 return ret_val; 3346 } else if (phy->smart_speed == e1000_smart_speed_off) { 3347 ret_val = phy->ops.read_reg(hw, 3348 IGP01E1000_PHY_PORT_CONFIG, 3349 &data); 3350 if (ret_val) 3351 return ret_val; 3352 3353 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3354 ret_val = phy->ops.write_reg(hw, 3355 IGP01E1000_PHY_PORT_CONFIG, 3356 data); 3357 if (ret_val) 3358 return ret_val; 3359 } 3360 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 3361 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 3362 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 3363 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 3364 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3365 3366 if (phy->type != e1000_phy_igp_3) 3367 return E1000_SUCCESS; 3368 3369 /* Call gig speed drop workaround on LPLU before accessing 3370 * any PHY registers 3371 */ 3372 if (hw->mac.type == e1000_ich8lan) 3373 e1000_gig_downshift_workaround_ich8lan(hw); 3374 3375 /* When LPLU is enabled, we should disable SmartSpeed */ 3376 ret_val = phy->ops.read_reg(hw, 3377 IGP01E1000_PHY_PORT_CONFIG, 3378 &data); 3379 if (ret_val) 3380 return ret_val; 3381 3382 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3383 ret_val = phy->ops.write_reg(hw, 3384 IGP01E1000_PHY_PORT_CONFIG, 3385 data); 3386 } 3387 3388 return ret_val; 3389 } 3390 3391 /** 3392 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 3393 * @hw: pointer to the HW structure 3394 * @bank: pointer to the variable that returns the active bank 3395 * 3396 * Reads signature byte from the NVM using the flash access registers. 3397 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 3398 **/ 3399 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 3400 { 3401 u32 eecd; 3402 struct e1000_nvm_info *nvm = &hw->nvm; 3403 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 3404 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 3405 u32 nvm_dword = 0; 3406 u8 sig_byte = 0; 3407 s32 ret_val; 3408 3409 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan"); 3410 3411 switch (hw->mac.type) { 3412 case e1000_pch_spt: 3413 case e1000_pch_cnp: 3414 bank1_offset = nvm->flash_bank_size; 3415 act_offset = E1000_ICH_NVM_SIG_WORD; 3416 3417 /* set bank to 0 in case flash read fails */ 3418 *bank = 0; 3419 3420 /* Check bank 0 */ 3421 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, 3422 &nvm_dword); 3423 if (ret_val) 3424 return ret_val; 3425 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3426 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3427 E1000_ICH_NVM_SIG_VALUE) { 3428 *bank = 0; 3429 return E1000_SUCCESS; 3430 } 3431 3432 /* Check bank 1 */ 3433 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + 3434 bank1_offset, 3435 &nvm_dword); 3436 if (ret_val) 3437 return ret_val; 3438 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3439 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3440 E1000_ICH_NVM_SIG_VALUE) { 3441 *bank = 1; 3442 return E1000_SUCCESS; 3443 } 3444 3445 DEBUGOUT("ERROR: No valid NVM bank present\n"); 3446 return -E1000_ERR_NVM; 3447 case e1000_ich8lan: 3448 case e1000_ich9lan: 3449 eecd = E1000_READ_REG(hw, E1000_EECD); 3450 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 3451 E1000_EECD_SEC1VAL_VALID_MASK) { 3452 if (eecd & E1000_EECD_SEC1VAL) 3453 *bank = 1; 3454 else 3455 *bank = 0; 3456 3457 return E1000_SUCCESS; 3458 } 3459 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 3460 /* fall-thru */ 3461 default: 3462 /* set bank to 0 in case flash read fails */ 3463 *bank = 0; 3464 3465 /* Check bank 0 */ 3466 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 3467 &sig_byte); 3468 if (ret_val) 3469 return ret_val; 3470 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3471 E1000_ICH_NVM_SIG_VALUE) { 3472 *bank = 0; 3473 return E1000_SUCCESS; 3474 } 3475 3476 /* Check bank 1 */ 3477 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 3478 bank1_offset, 3479 &sig_byte); 3480 if (ret_val) 3481 return ret_val; 3482 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3483 E1000_ICH_NVM_SIG_VALUE) { 3484 *bank = 1; 3485 return E1000_SUCCESS; 3486 } 3487 3488 DEBUGOUT("ERROR: No valid NVM bank present\n"); 3489 return -E1000_ERR_NVM; 3490 } 3491 } 3492 3493 /** 3494 * e1000_read_nvm_spt - NVM access for SPT 3495 * @hw: pointer to the HW structure 3496 * @offset: The offset (in bytes) of the word(s) to read. 3497 * @words: Size of data to read in words. 3498 * @data: pointer to the word(s) to read at offset. 3499 * 3500 * Reads a word(s) from the NVM 3501 **/ 3502 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 3503 u16 *data) 3504 { 3505 struct e1000_nvm_info *nvm = &hw->nvm; 3506 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3507 u32 act_offset; 3508 s32 ret_val = E1000_SUCCESS; 3509 u32 bank = 0; 3510 u32 dword = 0; 3511 u16 offset_to_read; 3512 u16 i; 3513 3514 DEBUGFUNC("e1000_read_nvm_spt"); 3515 3516 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3517 (words == 0)) { 3518 DEBUGOUT("nvm parameter(s) out of bounds\n"); 3519 ret_val = -E1000_ERR_NVM; 3520 goto out; 3521 } 3522 3523 nvm->ops.acquire(hw); 3524 3525 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3526 if (ret_val != E1000_SUCCESS) { 3527 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 3528 bank = 0; 3529 } 3530 3531 act_offset = (bank) ? nvm->flash_bank_size : 0; 3532 act_offset += offset; 3533 3534 ret_val = E1000_SUCCESS; 3535 3536 for (i = 0; i < words; i += 2) { 3537 if (words - i == 1) { 3538 if (dev_spec->shadow_ram[offset+i].modified) { 3539 data[i] = dev_spec->shadow_ram[offset+i].value; 3540 } else { 3541 offset_to_read = act_offset + i - 3542 ((act_offset + i) % 2); 3543 ret_val = 3544 e1000_read_flash_dword_ich8lan(hw, 3545 offset_to_read, 3546 &dword); 3547 if (ret_val) 3548 break; 3549 if ((act_offset + i) % 2 == 0) 3550 data[i] = (u16)(dword & 0xFFFF); 3551 else 3552 data[i] = (u16)((dword >> 16) & 0xFFFF); 3553 } 3554 } else { 3555 offset_to_read = act_offset + i; 3556 if (!(dev_spec->shadow_ram[offset+i].modified) || 3557 !(dev_spec->shadow_ram[offset+i+1].modified)) { 3558 ret_val = 3559 e1000_read_flash_dword_ich8lan(hw, 3560 offset_to_read, 3561 &dword); 3562 if (ret_val) 3563 break; 3564 } 3565 if (dev_spec->shadow_ram[offset+i].modified) 3566 data[i] = dev_spec->shadow_ram[offset+i].value; 3567 else 3568 data[i] = (u16) (dword & 0xFFFF); 3569 if (dev_spec->shadow_ram[offset+i].modified) 3570 data[i+1] = 3571 dev_spec->shadow_ram[offset+i+1].value; 3572 else 3573 data[i+1] = (u16) (dword >> 16 & 0xFFFF); 3574 } 3575 } 3576 3577 nvm->ops.release(hw); 3578 3579 out: 3580 if (ret_val) 3581 DEBUGOUT1("NVM read error: %d\n", ret_val); 3582 3583 return ret_val; 3584 } 3585 3586 /** 3587 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 3588 * @hw: pointer to the HW structure 3589 * @offset: The offset (in bytes) of the word(s) to read. 3590 * @words: Size of data to read in words 3591 * @data: Pointer to the word(s) to read at offset. 3592 * 3593 * Reads a word(s) from the NVM using the flash access registers. 3594 **/ 3595 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3596 u16 *data) 3597 { 3598 struct e1000_nvm_info *nvm = &hw->nvm; 3599 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3600 u32 act_offset; 3601 s32 ret_val = E1000_SUCCESS; 3602 u32 bank = 0; 3603 u16 i, word; 3604 3605 DEBUGFUNC("e1000_read_nvm_ich8lan"); 3606 3607 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3608 (words == 0)) { 3609 DEBUGOUT("nvm parameter(s) out of bounds\n"); 3610 ret_val = -E1000_ERR_NVM; 3611 goto out; 3612 } 3613 3614 nvm->ops.acquire(hw); 3615 3616 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3617 if (ret_val != E1000_SUCCESS) { 3618 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 3619 bank = 0; 3620 } 3621 3622 act_offset = (bank) ? nvm->flash_bank_size : 0; 3623 act_offset += offset; 3624 3625 ret_val = E1000_SUCCESS; 3626 for (i = 0; i < words; i++) { 3627 if (dev_spec->shadow_ram[offset+i].modified) { 3628 data[i] = dev_spec->shadow_ram[offset+i].value; 3629 } else { 3630 ret_val = e1000_read_flash_word_ich8lan(hw, 3631 act_offset + i, 3632 &word); 3633 if (ret_val) 3634 break; 3635 data[i] = word; 3636 } 3637 } 3638 3639 nvm->ops.release(hw); 3640 3641 out: 3642 if (ret_val) 3643 DEBUGOUT1("NVM read error: %d\n", ret_val); 3644 3645 return ret_val; 3646 } 3647 3648 /** 3649 * e1000_flash_cycle_init_ich8lan - Initialize flash 3650 * @hw: pointer to the HW structure 3651 * 3652 * This function does initial flash setup so that a new read/write/erase cycle 3653 * can be started. 3654 **/ 3655 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 3656 { 3657 union ich8_hws_flash_status hsfsts; 3658 s32 ret_val = -E1000_ERR_NVM; 3659 3660 DEBUGFUNC("e1000_flash_cycle_init_ich8lan"); 3661 3662 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 3663 3664 /* Check if the flash descriptor is valid */ 3665 if (!hsfsts.hsf_status.fldesvalid) { 3666 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n"); 3667 return -E1000_ERR_NVM; 3668 } 3669 3670 /* Clear FCERR and DAEL in hw status by writing 1 */ 3671 hsfsts.hsf_status.flcerr = 1; 3672 hsfsts.hsf_status.dael = 1; 3673 if (hw->mac.type >= e1000_pch_spt) 3674 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3675 hsfsts.regval & 0xFFFF); 3676 else 3677 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 3678 3679 /* Either we should have a hardware SPI cycle in progress 3680 * bit to check against, in order to start a new cycle or 3681 * FDONE bit should be changed in the hardware so that it 3682 * is 1 after hardware reset, which can then be used as an 3683 * indication whether a cycle is in progress or has been 3684 * completed. 3685 */ 3686 3687 if (!hsfsts.hsf_status.flcinprog) { 3688 /* There is no cycle running at present, 3689 * so we can start a cycle. 3690 * Begin by setting Flash Cycle Done. 3691 */ 3692 hsfsts.hsf_status.flcdone = 1; 3693 if (hw->mac.type >= e1000_pch_spt) 3694 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3695 hsfsts.regval & 0xFFFF); 3696 else 3697 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 3698 hsfsts.regval); 3699 ret_val = E1000_SUCCESS; 3700 } else { 3701 s32 i; 3702 3703 /* Otherwise poll for sometime so the current 3704 * cycle has a chance to end before giving up. 3705 */ 3706 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 3707 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 3708 ICH_FLASH_HSFSTS); 3709 if (!hsfsts.hsf_status.flcinprog) { 3710 ret_val = E1000_SUCCESS; 3711 break; 3712 } 3713 usec_delay(1); 3714 } 3715 if (ret_val == E1000_SUCCESS) { 3716 /* Successful in waiting for previous cycle to timeout, 3717 * now set the Flash Cycle Done. 3718 */ 3719 hsfsts.hsf_status.flcdone = 1; 3720 if (hw->mac.type >= e1000_pch_spt) 3721 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3722 hsfsts.regval & 0xFFFF); 3723 else 3724 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 3725 hsfsts.regval); 3726 } else { 3727 DEBUGOUT("Flash controller busy, cannot get access\n"); 3728 } 3729 } 3730 3731 return ret_val; 3732 } 3733 3734 /** 3735 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 3736 * @hw: pointer to the HW structure 3737 * @timeout: maximum time to wait for completion 3738 * 3739 * This function starts a flash cycle and waits for its completion. 3740 **/ 3741 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 3742 { 3743 union ich8_hws_flash_ctrl hsflctl; 3744 union ich8_hws_flash_status hsfsts; 3745 u32 i = 0; 3746 3747 DEBUGFUNC("e1000_flash_cycle_ich8lan"); 3748 3749 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 3750 if (hw->mac.type >= e1000_pch_spt) 3751 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16; 3752 else 3753 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 3754 hsflctl.hsf_ctrl.flcgo = 1; 3755 3756 if (hw->mac.type >= e1000_pch_spt) 3757 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3758 hsflctl.regval << 16); 3759 else 3760 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 3761 3762 /* wait till FDONE bit is set to 1 */ 3763 do { 3764 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 3765 if (hsfsts.hsf_status.flcdone) 3766 break; 3767 usec_delay(1); 3768 } while (i++ < timeout); 3769 3770 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 3771 return E1000_SUCCESS; 3772 3773 return -E1000_ERR_NVM; 3774 } 3775 3776 /** 3777 * e1000_read_flash_dword_ich8lan - Read dword from flash 3778 * @hw: pointer to the HW structure 3779 * @offset: offset to data location 3780 * @data: pointer to the location for storing the data 3781 * 3782 * Reads the flash dword at offset into data. Offset is converted 3783 * to bytes before read. 3784 **/ 3785 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, 3786 u32 *data) 3787 { 3788 DEBUGFUNC("e1000_read_flash_dword_ich8lan"); 3789 3790 if (!data) 3791 return -E1000_ERR_NVM; 3792 3793 /* Must convert word offset into bytes. */ 3794 offset <<= 1; 3795 3796 return e1000_read_flash_data32_ich8lan(hw, offset, data); 3797 } 3798 3799 /** 3800 * e1000_read_flash_word_ich8lan - Read word from flash 3801 * @hw: pointer to the HW structure 3802 * @offset: offset to data location 3803 * @data: pointer to the location for storing the data 3804 * 3805 * Reads the flash word at offset into data. Offset is converted 3806 * to bytes before read. 3807 **/ 3808 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 3809 u16 *data) 3810 { 3811 DEBUGFUNC("e1000_read_flash_word_ich8lan"); 3812 3813 if (!data) 3814 return -E1000_ERR_NVM; 3815 3816 /* Must convert offset into bytes. */ 3817 offset <<= 1; 3818 3819 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 3820 } 3821 3822 /** 3823 * e1000_read_flash_byte_ich8lan - Read byte from flash 3824 * @hw: pointer to the HW structure 3825 * @offset: The offset of the byte to read. 3826 * @data: Pointer to a byte to store the value read. 3827 * 3828 * Reads a single byte from the NVM using the flash access registers. 3829 **/ 3830 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3831 u8 *data) 3832 { 3833 s32 ret_val; 3834 u16 word = 0; 3835 3836 /* In SPT, only 32 bits access is supported, 3837 * so this function should not be called. 3838 */ 3839 if (hw->mac.type >= e1000_pch_spt) 3840 return -E1000_ERR_NVM; 3841 else 3842 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 3843 3844 if (ret_val) 3845 return ret_val; 3846 3847 *data = (u8)word; 3848 3849 return E1000_SUCCESS; 3850 } 3851 3852 /** 3853 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 3854 * @hw: pointer to the HW structure 3855 * @offset: The offset (in bytes) of the byte or word to read. 3856 * @size: Size of data to read, 1=byte 2=word 3857 * @data: Pointer to the word to store the value read. 3858 * 3859 * Reads a byte or word from the NVM using the flash access registers. 3860 **/ 3861 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3862 u8 size, u16 *data) 3863 { 3864 union ich8_hws_flash_status hsfsts; 3865 union ich8_hws_flash_ctrl hsflctl; 3866 u32 flash_linear_addr; 3867 u32 flash_data = 0; 3868 s32 ret_val = -E1000_ERR_NVM; 3869 u8 count = 0; 3870 3871 DEBUGFUNC("e1000_read_flash_data_ich8lan"); 3872 3873 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 3874 return -E1000_ERR_NVM; 3875 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3876 hw->nvm.flash_base_addr); 3877 3878 do { 3879 usec_delay(1); 3880 /* Steps */ 3881 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3882 if (ret_val != E1000_SUCCESS) 3883 break; 3884 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 3885 3886 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3887 hsflctl.hsf_ctrl.fldbcount = size - 1; 3888 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3889 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 3890 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 3891 3892 ret_val = e1000_flash_cycle_ich8lan(hw, 3893 ICH_FLASH_READ_COMMAND_TIMEOUT); 3894 3895 /* Check if FCERR is set to 1, if set to 1, clear it 3896 * and try the whole sequence a few more times, else 3897 * read in (shift in) the Flash Data0, the order is 3898 * least significant byte first msb to lsb 3899 */ 3900 if (ret_val == E1000_SUCCESS) { 3901 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 3902 if (size == 1) 3903 *data = (u8)(flash_data & 0x000000FF); 3904 else if (size == 2) 3905 *data = (u16)(flash_data & 0x0000FFFF); 3906 break; 3907 } else { 3908 /* If we've gotten here, then things are probably 3909 * completely hosed, but if the error condition is 3910 * detected, it won't hurt to give it another try... 3911 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3912 */ 3913 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 3914 ICH_FLASH_HSFSTS); 3915 if (hsfsts.hsf_status.flcerr) { 3916 /* Repeat for some time before giving up. */ 3917 continue; 3918 } else if (!hsfsts.hsf_status.flcdone) { 3919 DEBUGOUT("Timeout error - flash cycle did not complete.\n"); 3920 break; 3921 } 3922 } 3923 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3924 3925 return ret_val; 3926 } 3927 3928 /** 3929 * e1000_read_flash_data32_ich8lan - Read dword from NVM 3930 * @hw: pointer to the HW structure 3931 * @offset: The offset (in bytes) of the dword to read. 3932 * @data: Pointer to the dword to store the value read. 3933 * 3934 * Reads a byte or word from the NVM using the flash access registers. 3935 **/ 3936 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 3937 u32 *data) 3938 { 3939 union ich8_hws_flash_status hsfsts; 3940 union ich8_hws_flash_ctrl hsflctl; 3941 u32 flash_linear_addr; 3942 s32 ret_val = -E1000_ERR_NVM; 3943 u8 count = 0; 3944 3945 DEBUGFUNC("e1000_read_flash_data_ich8lan"); 3946 3947 if (offset > ICH_FLASH_LINEAR_ADDR_MASK && hw->mac.type < e1000_pch_spt) 3948 return -E1000_ERR_NVM; 3949 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3950 hw->nvm.flash_base_addr); 3951 3952 do { 3953 usec_delay(1); 3954 /* Steps */ 3955 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3956 if (ret_val != E1000_SUCCESS) 3957 break; 3958 /* In SPT, This register is in Lan memory space, not flash. 3959 * Therefore, only 32 bit access is supported 3960 */ 3961 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16; 3962 3963 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3964 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 3965 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3966 /* In SPT, This register is in Lan memory space, not flash. 3967 * Therefore, only 32 bit access is supported 3968 */ 3969 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3970 (u32)hsflctl.regval << 16); 3971 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 3972 3973 ret_val = e1000_flash_cycle_ich8lan(hw, 3974 ICH_FLASH_READ_COMMAND_TIMEOUT); 3975 3976 /* Check if FCERR is set to 1, if set to 1, clear it 3977 * and try the whole sequence a few more times, else 3978 * read in (shift in) the Flash Data0, the order is 3979 * least significant byte first msb to lsb 3980 */ 3981 if (ret_val == E1000_SUCCESS) { 3982 *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 3983 break; 3984 } else { 3985 /* If we've gotten here, then things are probably 3986 * completely hosed, but if the error condition is 3987 * detected, it won't hurt to give it another try... 3988 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3989 */ 3990 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 3991 ICH_FLASH_HSFSTS); 3992 if (hsfsts.hsf_status.flcerr) { 3993 /* Repeat for some time before giving up. */ 3994 continue; 3995 } else if (!hsfsts.hsf_status.flcdone) { 3996 DEBUGOUT("Timeout error - flash cycle did not complete.\n"); 3997 break; 3998 } 3999 } 4000 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4001 4002 return ret_val; 4003 } 4004 4005 /** 4006 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 4007 * @hw: pointer to the HW structure 4008 * @offset: The offset (in bytes) of the word(s) to write. 4009 * @words: Size of data to write in words 4010 * @data: Pointer to the word(s) to write at offset. 4011 * 4012 * Writes a byte or word to the NVM using the flash access registers. 4013 **/ 4014 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 4015 u16 *data) 4016 { 4017 struct e1000_nvm_info *nvm = &hw->nvm; 4018 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4019 u16 i; 4020 4021 DEBUGFUNC("e1000_write_nvm_ich8lan"); 4022 4023 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 4024 (words == 0)) { 4025 DEBUGOUT("nvm parameter(s) out of bounds\n"); 4026 return -E1000_ERR_NVM; 4027 } 4028 4029 nvm->ops.acquire(hw); 4030 4031 for (i = 0; i < words; i++) { 4032 dev_spec->shadow_ram[offset+i].modified = TRUE; 4033 dev_spec->shadow_ram[offset+i].value = data[i]; 4034 } 4035 4036 nvm->ops.release(hw); 4037 4038 return E1000_SUCCESS; 4039 } 4040 4041 /** 4042 * e1000_update_nvm_checksum_spt - Update the checksum for NVM 4043 * @hw: pointer to the HW structure 4044 * 4045 * The NVM checksum is updated by calling the generic update_nvm_checksum, 4046 * which writes the checksum to the shadow ram. The changes in the shadow 4047 * ram are then committed to the EEPROM by processing each bank at a time 4048 * checking for the modified bit and writing only the pending changes. 4049 * After a successful commit, the shadow ram is cleared and is ready for 4050 * future writes. 4051 **/ 4052 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) 4053 { 4054 struct e1000_nvm_info *nvm = &hw->nvm; 4055 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4056 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 4057 s32 ret_val; 4058 u32 dword = 0; 4059 4060 DEBUGFUNC("e1000_update_nvm_checksum_spt"); 4061 4062 ret_val = e1000_update_nvm_checksum_generic(hw); 4063 if (ret_val) 4064 goto out; 4065 4066 if (nvm->type != e1000_nvm_flash_sw) 4067 goto out; 4068 4069 nvm->ops.acquire(hw); 4070 4071 /* We're writing to the opposite bank so if we're on bank 1, 4072 * write to bank 0 etc. We also need to erase the segment that 4073 * is going to be written 4074 */ 4075 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 4076 if (ret_val != E1000_SUCCESS) { 4077 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 4078 bank = 0; 4079 } 4080 4081 if (bank == 0) { 4082 new_bank_offset = nvm->flash_bank_size; 4083 old_bank_offset = 0; 4084 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 4085 if (ret_val) 4086 goto release; 4087 } else { 4088 old_bank_offset = nvm->flash_bank_size; 4089 new_bank_offset = 0; 4090 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 4091 if (ret_val) 4092 goto release; 4093 } 4094 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) { 4095 /* Determine whether to write the value stored 4096 * in the other NVM bank or a modified value stored 4097 * in the shadow RAM 4098 */ 4099 ret_val = e1000_read_flash_dword_ich8lan(hw, 4100 i + old_bank_offset, 4101 &dword); 4102 4103 if (dev_spec->shadow_ram[i].modified) { 4104 dword &= 0xffff0000; 4105 dword |= (dev_spec->shadow_ram[i].value & 0xffff); 4106 } 4107 if (dev_spec->shadow_ram[i + 1].modified) { 4108 dword &= 0x0000ffff; 4109 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) 4110 << 16); 4111 } 4112 if (ret_val) 4113 break; 4114 4115 /* If the word is 0x13, then make sure the signature bits 4116 * (15:14) are 11b until the commit has completed. 4117 * This will allow us to write 10b which indicates the 4118 * signature is valid. We want to do this after the write 4119 * has completed so that we don't mark the segment valid 4120 * while the write is still in progress 4121 */ 4122 if (i == E1000_ICH_NVM_SIG_WORD - 1) 4123 dword |= E1000_ICH_NVM_SIG_MASK << 16; 4124 4125 /* Convert offset to bytes. */ 4126 act_offset = (i + new_bank_offset) << 1; 4127 4128 usec_delay(100); 4129 4130 /* Write the data to the new bank. Offset in words*/ 4131 act_offset = i + new_bank_offset; 4132 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, 4133 dword); 4134 if (ret_val) 4135 break; 4136 } 4137 4138 /* Don't bother writing the segment valid bits if sector 4139 * programming failed. 4140 */ 4141 if (ret_val) { 4142 DEBUGOUT("Flash commit failed.\n"); 4143 goto release; 4144 } 4145 4146 /* Finally validate the new segment by setting bit 15:14 4147 * to 10b in word 0x13 , this can be done without an 4148 * erase as well since these bits are 11 to start with 4149 * and we need to change bit 14 to 0b 4150 */ 4151 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4152 4153 /*offset in words but we read dword*/ 4154 --act_offset; 4155 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 4156 4157 if (ret_val) 4158 goto release; 4159 4160 dword &= 0xBFFFFFFF; 4161 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 4162 4163 if (ret_val) 4164 goto release; 4165 4166 /* And invalidate the previously valid segment by setting 4167 * its signature word (0x13) high_byte to 0b. This can be 4168 * done without an erase because flash erase sets all bits 4169 * to 1's. We can write 1's to 0's without an erase 4170 */ 4171 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4172 4173 /* offset in words but we read dword*/ 4174 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; 4175 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 4176 4177 if (ret_val) 4178 goto release; 4179 4180 dword &= 0x00FFFFFF; 4181 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 4182 4183 if (ret_val) 4184 goto release; 4185 4186 /* Great! Everything worked, we can now clear the cached entries. */ 4187 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 4188 dev_spec->shadow_ram[i].modified = FALSE; 4189 dev_spec->shadow_ram[i].value = 0xFFFF; 4190 } 4191 4192 release: 4193 nvm->ops.release(hw); 4194 4195 /* Reload the EEPROM, or else modifications will not appear 4196 * until after the next adapter reset. 4197 */ 4198 if (!ret_val) { 4199 nvm->ops.reload(hw); 4200 msec_delay(10); 4201 } 4202 4203 out: 4204 if (ret_val) 4205 DEBUGOUT1("NVM update error: %d\n", ret_val); 4206 4207 return ret_val; 4208 } 4209 4210 /** 4211 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 4212 * @hw: pointer to the HW structure 4213 * 4214 * The NVM checksum is updated by calling the generic update_nvm_checksum, 4215 * which writes the checksum to the shadow ram. The changes in the shadow 4216 * ram are then committed to the EEPROM by processing each bank at a time 4217 * checking for the modified bit and writing only the pending changes. 4218 * After a successful commit, the shadow ram is cleared and is ready for 4219 * future writes. 4220 **/ 4221 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 4222 { 4223 struct e1000_nvm_info *nvm = &hw->nvm; 4224 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4225 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 4226 s32 ret_val; 4227 u16 data = 0; 4228 4229 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan"); 4230 4231 ret_val = e1000_update_nvm_checksum_generic(hw); 4232 if (ret_val) 4233 goto out; 4234 4235 if (nvm->type != e1000_nvm_flash_sw) 4236 goto out; 4237 4238 nvm->ops.acquire(hw); 4239 4240 /* We're writing to the opposite bank so if we're on bank 1, 4241 * write to bank 0 etc. We also need to erase the segment that 4242 * is going to be written 4243 */ 4244 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 4245 if (ret_val != E1000_SUCCESS) { 4246 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 4247 bank = 0; 4248 } 4249 4250 if (bank == 0) { 4251 new_bank_offset = nvm->flash_bank_size; 4252 old_bank_offset = 0; 4253 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 4254 if (ret_val) 4255 goto release; 4256 } else { 4257 old_bank_offset = nvm->flash_bank_size; 4258 new_bank_offset = 0; 4259 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 4260 if (ret_val) 4261 goto release; 4262 } 4263 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 4264 if (dev_spec->shadow_ram[i].modified) { 4265 data = dev_spec->shadow_ram[i].value; 4266 } else { 4267 ret_val = e1000_read_flash_word_ich8lan(hw, i + 4268 old_bank_offset, 4269 &data); 4270 if (ret_val) 4271 break; 4272 } 4273 /* If the word is 0x13, then make sure the signature bits 4274 * (15:14) are 11b until the commit has completed. 4275 * This will allow us to write 10b which indicates the 4276 * signature is valid. We want to do this after the write 4277 * has completed so that we don't mark the segment valid 4278 * while the write is still in progress 4279 */ 4280 if (i == E1000_ICH_NVM_SIG_WORD) 4281 data |= E1000_ICH_NVM_SIG_MASK; 4282 4283 /* Convert offset to bytes. */ 4284 act_offset = (i + new_bank_offset) << 1; 4285 4286 usec_delay(100); 4287 4288 /* Write the bytes to the new bank. */ 4289 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4290 act_offset, 4291 (u8)data); 4292 if (ret_val) 4293 break; 4294 4295 usec_delay(100); 4296 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4297 act_offset + 1, 4298 (u8)(data >> 8)); 4299 if (ret_val) 4300 break; 4301 } 4302 4303 /* Don't bother writing the segment valid bits if sector 4304 * programming failed. 4305 */ 4306 if (ret_val) { 4307 DEBUGOUT("Flash commit failed.\n"); 4308 goto release; 4309 } 4310 4311 /* Finally validate the new segment by setting bit 15:14 4312 * to 10b in word 0x13 , this can be done without an 4313 * erase as well since these bits are 11 to start with 4314 * and we need to change bit 14 to 0b 4315 */ 4316 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4317 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 4318 if (ret_val) 4319 goto release; 4320 4321 data &= 0xBFFF; 4322 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1, 4323 (u8)(data >> 8)); 4324 if (ret_val) 4325 goto release; 4326 4327 /* And invalidate the previously valid segment by setting 4328 * its signature word (0x13) high_byte to 0b. This can be 4329 * done without an erase because flash erase sets all bits 4330 * to 1's. We can write 1's to 0's without an erase 4331 */ 4332 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4333 4334 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 4335 4336 if (ret_val) 4337 goto release; 4338 4339 /* Great! Everything worked, we can now clear the cached entries. */ 4340 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 4341 dev_spec->shadow_ram[i].modified = FALSE; 4342 dev_spec->shadow_ram[i].value = 0xFFFF; 4343 } 4344 4345 release: 4346 nvm->ops.release(hw); 4347 4348 /* Reload the EEPROM, or else modifications will not appear 4349 * until after the next adapter reset. 4350 */ 4351 if (!ret_val) { 4352 nvm->ops.reload(hw); 4353 msec_delay(10); 4354 } 4355 4356 out: 4357 if (ret_val) 4358 DEBUGOUT1("NVM update error: %d\n", ret_val); 4359 4360 return ret_val; 4361 } 4362 4363 /** 4364 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 4365 * @hw: pointer to the HW structure 4366 * 4367 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 4368 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 4369 * calculated, in which case we need to calculate the checksum and set bit 6. 4370 **/ 4371 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 4372 { 4373 s32 ret_val; 4374 u16 data; 4375 u16 word; 4376 u16 valid_csum_mask; 4377 4378 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); 4379 4380 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 4381 * the checksum needs to be fixed. This bit is an indication that 4382 * the NVM was prepared by OEM software and did not calculate 4383 * the checksum...a likely scenario. 4384 */ 4385 switch (hw->mac.type) { 4386 case e1000_pch_lpt: 4387 case e1000_pch_spt: 4388 case e1000_pch_cnp: 4389 word = NVM_COMPAT; 4390 valid_csum_mask = NVM_COMPAT_VALID_CSUM; 4391 break; 4392 default: 4393 word = NVM_FUTURE_INIT_WORD1; 4394 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 4395 break; 4396 } 4397 4398 ret_val = hw->nvm.ops.read(hw, word, 1, &data); 4399 if (ret_val) 4400 return ret_val; 4401 4402 if (!(data & valid_csum_mask)) { 4403 data |= valid_csum_mask; 4404 ret_val = hw->nvm.ops.write(hw, word, 1, &data); 4405 if (ret_val) 4406 return ret_val; 4407 ret_val = hw->nvm.ops.update(hw); 4408 if (ret_val) 4409 return ret_val; 4410 } 4411 4412 return e1000_validate_nvm_checksum_generic(hw); 4413 } 4414 4415 /** 4416 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 4417 * @hw: pointer to the HW structure 4418 * @offset: The offset (in bytes) of the byte/word to read. 4419 * @size: Size of data to read, 1=byte 2=word 4420 * @data: The byte(s) to write to the NVM. 4421 * 4422 * Writes one/two bytes to the NVM using the flash access registers. 4423 **/ 4424 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 4425 u8 size, u16 data) 4426 { 4427 union ich8_hws_flash_status hsfsts; 4428 union ich8_hws_flash_ctrl hsflctl; 4429 u32 flash_linear_addr; 4430 u32 flash_data = 0; 4431 s32 ret_val; 4432 u8 count = 0; 4433 4434 DEBUGFUNC("e1000_write_ich8_data"); 4435 4436 if (hw->mac.type >= e1000_pch_spt) { 4437 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4438 return -E1000_ERR_NVM; 4439 } else { 4440 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4441 return -E1000_ERR_NVM; 4442 } 4443 4444 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4445 hw->nvm.flash_base_addr); 4446 4447 do { 4448 usec_delay(1); 4449 /* Steps */ 4450 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4451 if (ret_val != E1000_SUCCESS) 4452 break; 4453 /* In SPT, This register is in Lan memory space, not 4454 * flash. Therefore, only 32 bit access is supported 4455 */ 4456 if (hw->mac.type >= e1000_pch_spt) 4457 hsflctl.regval = 4458 E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS) >> 16; 4459 else 4460 hsflctl.regval = 4461 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 4462 4463 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 4464 hsflctl.hsf_ctrl.fldbcount = size - 1; 4465 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4466 /* In SPT, This register is in Lan memory space, 4467 * not flash. Therefore, only 32 bit access is 4468 * supported 4469 */ 4470 if (hw->mac.type >= e1000_pch_spt) 4471 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 4472 hsflctl.regval << 16); 4473 else 4474 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 4475 hsflctl.regval); 4476 4477 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 4478 4479 if (size == 1) 4480 flash_data = (u32)data & 0x00FF; 4481 else 4482 flash_data = (u32)data; 4483 4484 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 4485 4486 /* check if FCERR is set to 1 , if set to 1, clear it 4487 * and try the whole sequence a few more times else done 4488 */ 4489 ret_val = 4490 e1000_flash_cycle_ich8lan(hw, 4491 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4492 if (ret_val == E1000_SUCCESS) 4493 break; 4494 4495 /* If we're here, then things are most likely 4496 * completely hosed, but if the error condition 4497 * is detected, it won't hurt to give it another 4498 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4499 */ 4500 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 4501 if (hsfsts.hsf_status.flcerr) 4502 /* Repeat for some time before giving up. */ 4503 continue; 4504 if (!hsfsts.hsf_status.flcdone) { 4505 DEBUGOUT("Timeout error - flash cycle did not complete.\n"); 4506 break; 4507 } 4508 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4509 4510 return ret_val; 4511 } 4512 4513 /** 4514 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM 4515 * @hw: pointer to the HW structure 4516 * @offset: The offset (in bytes) of the dwords to read. 4517 * @data: The 4 bytes to write to the NVM. 4518 * 4519 * Writes one/two/four bytes to the NVM using the flash access registers. 4520 **/ 4521 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 4522 u32 data) 4523 { 4524 union ich8_hws_flash_status hsfsts; 4525 union ich8_hws_flash_ctrl hsflctl; 4526 u32 flash_linear_addr; 4527 s32 ret_val; 4528 u8 count = 0; 4529 4530 DEBUGFUNC("e1000_write_flash_data32_ich8lan"); 4531 4532 if (hw->mac.type >= e1000_pch_spt) { 4533 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 4534 return -E1000_ERR_NVM; 4535 } 4536 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4537 hw->nvm.flash_base_addr); 4538 do { 4539 usec_delay(1); 4540 /* Steps */ 4541 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4542 if (ret_val != E1000_SUCCESS) 4543 break; 4544 4545 /* In SPT, This register is in Lan memory space, not 4546 * flash. Therefore, only 32 bit access is supported 4547 */ 4548 if (hw->mac.type >= e1000_pch_spt) 4549 hsflctl.regval = E1000_READ_FLASH_REG(hw, 4550 ICH_FLASH_HSFSTS) 4551 >> 16; 4552 else 4553 hsflctl.regval = E1000_READ_FLASH_REG16(hw, 4554 ICH_FLASH_HSFCTL); 4555 4556 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 4557 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4558 4559 /* In SPT, This register is in Lan memory space, 4560 * not flash. Therefore, only 32 bit access is 4561 * supported 4562 */ 4563 if (hw->mac.type >= e1000_pch_spt) 4564 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 4565 hsflctl.regval << 16); 4566 else 4567 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 4568 hsflctl.regval); 4569 4570 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 4571 4572 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data); 4573 4574 /* check if FCERR is set to 1 , if set to 1, clear it 4575 * and try the whole sequence a few more times else done 4576 */ 4577 ret_val = e1000_flash_cycle_ich8lan(hw, 4578 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4579 4580 if (ret_val == E1000_SUCCESS) 4581 break; 4582 4583 /* If we're here, then things are most likely 4584 * completely hosed, but if the error condition 4585 * is detected, it won't hurt to give it another 4586 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4587 */ 4588 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 4589 4590 if (hsfsts.hsf_status.flcerr) 4591 /* Repeat for some time before giving up. */ 4592 continue; 4593 if (!hsfsts.hsf_status.flcdone) { 4594 DEBUGOUT("Timeout error - flash cycle did not complete.\n"); 4595 break; 4596 } 4597 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4598 4599 return ret_val; 4600 } 4601 4602 /** 4603 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 4604 * @hw: pointer to the HW structure 4605 * @offset: The index of the byte to read. 4606 * @data: The byte to write to the NVM. 4607 * 4608 * Writes a single byte to the NVM using the flash access registers. 4609 **/ 4610 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 4611 u8 data) 4612 { 4613 u16 word = (u16)data; 4614 4615 DEBUGFUNC("e1000_write_flash_byte_ich8lan"); 4616 4617 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 4618 } 4619 4620 /** 4621 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM 4622 * @hw: pointer to the HW structure 4623 * @offset: The offset of the word to write. 4624 * @dword: The dword to write to the NVM. 4625 * 4626 * Writes a single dword to the NVM using the flash access registers. 4627 * Goes through a retry algorithm before giving up. 4628 **/ 4629 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 4630 u32 offset, u32 dword) 4631 { 4632 s32 ret_val; 4633 u16 program_retries; 4634 4635 DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan"); 4636 4637 /* Must convert word offset into bytes. */ 4638 offset <<= 1; 4639 4640 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4641 4642 if (!ret_val) 4643 return ret_val; 4644 for (program_retries = 0; program_retries < 100; program_retries++) { 4645 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset); 4646 usec_delay(100); 4647 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4648 if (ret_val == E1000_SUCCESS) 4649 break; 4650 } 4651 if (program_retries == 100) 4652 return -E1000_ERR_NVM; 4653 4654 return E1000_SUCCESS; 4655 } 4656 4657 /** 4658 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 4659 * @hw: pointer to the HW structure 4660 * @offset: The offset of the byte to write. 4661 * @byte: The byte to write to the NVM. 4662 * 4663 * Writes a single byte to the NVM using the flash access registers. 4664 * Goes through a retry algorithm before giving up. 4665 **/ 4666 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 4667 u32 offset, u8 byte) 4668 { 4669 s32 ret_val; 4670 u16 program_retries; 4671 4672 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); 4673 4674 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4675 if (!ret_val) 4676 return ret_val; 4677 4678 for (program_retries = 0; program_retries < 100; program_retries++) { 4679 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); 4680 usec_delay(100); 4681 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4682 if (ret_val == E1000_SUCCESS) 4683 break; 4684 } 4685 if (program_retries == 100) 4686 return -E1000_ERR_NVM; 4687 4688 return E1000_SUCCESS; 4689 } 4690 4691 /** 4692 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 4693 * @hw: pointer to the HW structure 4694 * @bank: 0 for first bank, 1 for second bank, etc. 4695 * 4696 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 4697 * bank N is 4096 * N + flash_reg_addr. 4698 **/ 4699 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 4700 { 4701 struct e1000_nvm_info *nvm = &hw->nvm; 4702 union ich8_hws_flash_status hsfsts; 4703 union ich8_hws_flash_ctrl hsflctl; 4704 u32 flash_linear_addr; 4705 /* bank size is in 16bit words - adjust to bytes */ 4706 u32 flash_bank_size = nvm->flash_bank_size * 2; 4707 s32 ret_val; 4708 s32 count = 0; 4709 s32 j, iteration, sector_size; 4710 4711 DEBUGFUNC("e1000_erase_flash_bank_ich8lan"); 4712 4713 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 4714 4715 /* Determine HW Sector size: Read BERASE bits of hw flash status 4716 * register 4717 * 00: The Hw sector is 256 bytes, hence we need to erase 16 4718 * consecutive sectors. The start index for the nth Hw sector 4719 * can be calculated as = bank * 4096 + n * 256 4720 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 4721 * The start index for the nth Hw sector can be calculated 4722 * as = bank * 4096 4723 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 4724 * (ich9 only, otherwise error condition) 4725 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 4726 */ 4727 switch (hsfsts.hsf_status.berasesz) { 4728 case 0: 4729 /* Hw sector size 256 */ 4730 sector_size = ICH_FLASH_SEG_SIZE_256; 4731 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 4732 break; 4733 case 1: 4734 sector_size = ICH_FLASH_SEG_SIZE_4K; 4735 iteration = 1; 4736 break; 4737 case 2: 4738 sector_size = ICH_FLASH_SEG_SIZE_8K; 4739 iteration = 1; 4740 break; 4741 case 3: 4742 sector_size = ICH_FLASH_SEG_SIZE_64K; 4743 iteration = 1; 4744 break; 4745 default: 4746 return -E1000_ERR_NVM; 4747 } 4748 4749 /* Start with the base address, then add the sector offset. */ 4750 flash_linear_addr = hw->nvm.flash_base_addr; 4751 flash_linear_addr += (bank) ? flash_bank_size : 0; 4752 4753 for (j = 0; j < iteration; j++) { 4754 do { 4755 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; 4756 4757 /* Steps */ 4758 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4759 if (ret_val) 4760 return ret_val; 4761 4762 /* Write a value 11 (block Erase) in Flash 4763 * Cycle field in hw flash control 4764 */ 4765 if (hw->mac.type >= e1000_pch_spt) 4766 hsflctl.regval = 4767 E1000_READ_FLASH_REG(hw, 4768 ICH_FLASH_HSFSTS)>>16; 4769 else 4770 hsflctl.regval = 4771 E1000_READ_FLASH_REG16(hw, 4772 ICH_FLASH_HSFCTL); 4773 4774 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 4775 if (hw->mac.type >= e1000_pch_spt) 4776 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 4777 hsflctl.regval << 16); 4778 else 4779 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 4780 hsflctl.regval); 4781 4782 /* Write the last 24 bits of an index within the 4783 * block into Flash Linear address field in Flash 4784 * Address. 4785 */ 4786 flash_linear_addr += (j * sector_size); 4787 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, 4788 flash_linear_addr); 4789 4790 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); 4791 if (ret_val == E1000_SUCCESS) 4792 break; 4793 4794 /* Check if FCERR is set to 1. If 1, 4795 * clear it and try the whole sequence 4796 * a few more times else Done 4797 */ 4798 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 4799 ICH_FLASH_HSFSTS); 4800 if (hsfsts.hsf_status.flcerr) 4801 /* repeat for some time before giving up */ 4802 continue; 4803 else if (!hsfsts.hsf_status.flcdone) 4804 return ret_val; 4805 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 4806 } 4807 4808 return E1000_SUCCESS; 4809 } 4810 4811 /** 4812 * e1000_valid_led_default_ich8lan - Set the default LED settings 4813 * @hw: pointer to the HW structure 4814 * @data: Pointer to the LED settings 4815 * 4816 * Reads the LED default settings from the NVM to data. If the NVM LED 4817 * settings is all 0's or F's, set the LED default to a valid LED default 4818 * setting. 4819 **/ 4820 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 4821 { 4822 s32 ret_val; 4823 4824 DEBUGFUNC("e1000_valid_led_default_ich8lan"); 4825 4826 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 4827 if (ret_val) { 4828 DEBUGOUT("NVM Read Error\n"); 4829 return ret_val; 4830 } 4831 4832 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 4833 *data = ID_LED_DEFAULT_ICH8LAN; 4834 4835 return E1000_SUCCESS; 4836 } 4837 4838 /** 4839 * e1000_id_led_init_pchlan - store LED configurations 4840 * @hw: pointer to the HW structure 4841 * 4842 * PCH does not control LEDs via the LEDCTL register, rather it uses 4843 * the PHY LED configuration register. 4844 * 4845 * PCH also does not have an "always on" or "always off" mode which 4846 * complicates the ID feature. Instead of using the "on" mode to indicate 4847 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()), 4848 * use "link_up" mode. The LEDs will still ID on request if there is no 4849 * link based on logic in e1000_led_[on|off]_pchlan(). 4850 **/ 4851 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 4852 { 4853 struct e1000_mac_info *mac = &hw->mac; 4854 s32 ret_val; 4855 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 4856 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 4857 u16 data, i, temp, shift; 4858 4859 DEBUGFUNC("e1000_id_led_init_pchlan"); 4860 4861 /* Get default ID LED modes */ 4862 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 4863 if (ret_val) 4864 return ret_val; 4865 4866 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 4867 mac->ledctl_mode1 = mac->ledctl_default; 4868 mac->ledctl_mode2 = mac->ledctl_default; 4869 4870 for (i = 0; i < 4; i++) { 4871 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 4872 shift = (i * 5); 4873 switch (temp) { 4874 case ID_LED_ON1_DEF2: 4875 case ID_LED_ON1_ON2: 4876 case ID_LED_ON1_OFF2: 4877 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4878 mac->ledctl_mode1 |= (ledctl_on << shift); 4879 break; 4880 case ID_LED_OFF1_DEF2: 4881 case ID_LED_OFF1_ON2: 4882 case ID_LED_OFF1_OFF2: 4883 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4884 mac->ledctl_mode1 |= (ledctl_off << shift); 4885 break; 4886 default: 4887 /* Do nothing */ 4888 break; 4889 } 4890 switch (temp) { 4891 case ID_LED_DEF1_ON2: 4892 case ID_LED_ON1_ON2: 4893 case ID_LED_OFF1_ON2: 4894 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4895 mac->ledctl_mode2 |= (ledctl_on << shift); 4896 break; 4897 case ID_LED_DEF1_OFF2: 4898 case ID_LED_ON1_OFF2: 4899 case ID_LED_OFF1_OFF2: 4900 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4901 mac->ledctl_mode2 |= (ledctl_off << shift); 4902 break; 4903 default: 4904 /* Do nothing */ 4905 break; 4906 } 4907 } 4908 4909 return E1000_SUCCESS; 4910 } 4911 4912 /** 4913 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 4914 * @hw: pointer to the HW structure 4915 * 4916 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 4917 * register, so the bus width is hard coded. 4918 **/ 4919 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 4920 { 4921 struct e1000_bus_info *bus = &hw->bus; 4922 s32 ret_val; 4923 4924 DEBUGFUNC("e1000_get_bus_info_ich8lan"); 4925 4926 ret_val = e1000_get_bus_info_pcie_generic(hw); 4927 4928 /* ICH devices are "PCI Express"-ish. They have 4929 * a configuration space, but do not contain 4930 * PCI Express Capability registers, so bus width 4931 * must be hardcoded. 4932 */ 4933 if (bus->width == e1000_bus_width_unknown) 4934 bus->width = e1000_bus_width_pcie_x1; 4935 4936 return ret_val; 4937 } 4938 4939 /** 4940 * e1000_reset_hw_ich8lan - Reset the hardware 4941 * @hw: pointer to the HW structure 4942 * 4943 * Does a full reset of the hardware which includes a reset of the PHY and 4944 * MAC. 4945 **/ 4946 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 4947 { 4948 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4949 u16 kum_cfg; 4950 u32 ctrl, reg; 4951 s32 ret_val; 4952 4953 DEBUGFUNC("e1000_reset_hw_ich8lan"); 4954 4955 /* Prevent the PCI-E bus from sticking if there is no TLP connection 4956 * on the last TLP read/write transaction when MAC is reset. 4957 */ 4958 ret_val = e1000_disable_pcie_master_generic(hw); 4959 if (ret_val) 4960 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 4961 4962 DEBUGOUT("Masking off all interrupts\n"); 4963 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4964 4965 /* Disable the Transmit and Receive units. Then delay to allow 4966 * any pending transactions to complete before we hit the MAC 4967 * with the global reset. 4968 */ 4969 E1000_WRITE_REG(hw, E1000_RCTL, 0); 4970 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 4971 E1000_WRITE_FLUSH(hw); 4972 4973 msec_delay(10); 4974 4975 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 4976 if (hw->mac.type == e1000_ich8lan) { 4977 /* Set Tx and Rx buffer allocation to 8k apiece. */ 4978 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); 4979 /* Set Packet Buffer Size to 16k. */ 4980 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); 4981 } 4982 4983 if (hw->mac.type == e1000_pchlan) { 4984 /* Save the NVM K1 bit setting*/ 4985 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 4986 if (ret_val) 4987 return ret_val; 4988 4989 if (kum_cfg & E1000_NVM_K1_ENABLE) 4990 dev_spec->nvm_k1_enabled = TRUE; 4991 else 4992 dev_spec->nvm_k1_enabled = FALSE; 4993 } 4994 4995 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4996 4997 if (!hw->phy.ops.check_reset_block(hw)) { 4998 /* Full-chip reset requires MAC and PHY reset at the same 4999 * time to make sure the interface between MAC and the 5000 * external PHY is reset. 5001 */ 5002 ctrl |= E1000_CTRL_PHY_RST; 5003 5004 /* Gate automatic PHY configuration by hardware on 5005 * non-managed 82579 5006 */ 5007 if ((hw->mac.type == e1000_pch2lan) && 5008 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) 5009 e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 5010 } 5011 ret_val = e1000_acquire_swflag_ich8lan(hw); 5012 DEBUGOUT("Issuing a global reset to ich8lan\n"); 5013 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); 5014 /* cannot issue a flush here because it hangs the hardware */ 5015 msec_delay(20); 5016 5017 /* Set Phy Config Counter to 50msec */ 5018 if (hw->mac.type == e1000_pch2lan) { 5019 reg = E1000_READ_REG(hw, E1000_FEXTNVM3); 5020 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 5021 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 5022 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg); 5023 } 5024 5025 if (!ret_val) 5026 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 5027 5028 if (ctrl & E1000_CTRL_PHY_RST) { 5029 ret_val = hw->phy.ops.get_cfg_done(hw); 5030 if (ret_val) 5031 return ret_val; 5032 5033 ret_val = e1000_post_phy_reset_ich8lan(hw); 5034 if (ret_val) 5035 return ret_val; 5036 } 5037 5038 /* For PCH, this write will make sure that any noise 5039 * will be detected as a CRC error and be dropped rather than show up 5040 * as a bad packet to the DMA engine. 5041 */ 5042 if (hw->mac.type == e1000_pchlan) 5043 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565); 5044 5045 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 5046 E1000_READ_REG(hw, E1000_ICR); 5047 5048 reg = E1000_READ_REG(hw, E1000_KABGTXD); 5049 reg |= E1000_KABGTXD_BGSQLBIAS; 5050 E1000_WRITE_REG(hw, E1000_KABGTXD, reg); 5051 5052 return E1000_SUCCESS; 5053 } 5054 5055 /** 5056 * e1000_init_hw_ich8lan - Initialize the hardware 5057 * @hw: pointer to the HW structure 5058 * 5059 * Prepares the hardware for transmit and receive by doing the following: 5060 * - initialize hardware bits 5061 * - initialize LED identification 5062 * - setup receive address registers 5063 * - setup flow control 5064 * - setup transmit descriptors 5065 * - clear statistics 5066 **/ 5067 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 5068 { 5069 struct e1000_mac_info *mac = &hw->mac; 5070 u32 ctrl_ext, txdctl, snoop; 5071 s32 ret_val; 5072 u16 i; 5073 5074 DEBUGFUNC("e1000_init_hw_ich8lan"); 5075 5076 e1000_initialize_hw_bits_ich8lan(hw); 5077 5078 /* Initialize identification LED */ 5079 ret_val = mac->ops.id_led_init(hw); 5080 /* An error is not fatal and we should not stop init due to this */ 5081 if (ret_val) 5082 DEBUGOUT("Error initializing identification LED\n"); 5083 5084 /* Setup the receive address. */ 5085 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 5086 5087 /* Zero out the Multicast HASH table */ 5088 DEBUGOUT("Zeroing the MTA\n"); 5089 for (i = 0; i < mac->mta_reg_count; i++) 5090 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 5091 5092 /* The 82578 Rx buffer will stall if wakeup is enabled in host and 5093 * the ME. Disable wakeup by clearing the host wakeup bit. 5094 * Reset the phy after disabling host wakeup to reset the Rx buffer. 5095 */ 5096 if (hw->phy.type == e1000_phy_82578) { 5097 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i); 5098 i &= ~BM_WUC_HOST_WU_BIT; 5099 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i); 5100 ret_val = e1000_phy_hw_reset_ich8lan(hw); 5101 if (ret_val) 5102 return ret_val; 5103 } 5104 5105 /* Setup link and flow control */ 5106 ret_val = mac->ops.setup_link(hw); 5107 5108 /* Set the transmit descriptor write-back policy for both queues */ 5109 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 5110 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 5111 E1000_TXDCTL_FULL_TX_DESC_WB); 5112 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 5113 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 5114 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 5115 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1)); 5116 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 5117 E1000_TXDCTL_FULL_TX_DESC_WB); 5118 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 5119 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 5120 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); 5121 5122 /* ICH8 has opposite polarity of no_snoop bits. 5123 * By default, we should use snoop behavior. 5124 */ 5125 if (mac->type == e1000_ich8lan) 5126 snoop = PCIE_ICH8_SNOOP_ALL; 5127 else 5128 snoop = (u32) ~(PCIE_NO_SNOOP_ALL); 5129 e1000_set_pcie_no_snoop_generic(hw, snoop); 5130 5131 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5132 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 5133 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5134 5135 /* Clear all of the statistics registers (clear on read). It is 5136 * important that we do this after we have tried to establish link 5137 * because the symbol error count will increment wildly if there 5138 * is no link. 5139 */ 5140 e1000_clear_hw_cntrs_ich8lan(hw); 5141 5142 return ret_val; 5143 } 5144 5145 /** 5146 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 5147 * @hw: pointer to the HW structure 5148 * 5149 * Sets/Clears required hardware bits necessary for correctly setting up the 5150 * hardware for transmit and receive. 5151 **/ 5152 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 5153 { 5154 u32 reg; 5155 5156 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan"); 5157 5158 /* Extended Device Control */ 5159 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 5160 reg |= (1 << 22); 5161 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 5162 if (hw->mac.type >= e1000_pchlan) 5163 reg |= E1000_CTRL_EXT_PHYPDEN; 5164 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 5165 5166 /* Transmit Descriptor Control 0 */ 5167 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 5168 reg |= (1 << 22); 5169 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 5170 5171 /* Transmit Descriptor Control 1 */ 5172 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 5173 reg |= (1 << 22); 5174 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 5175 5176 /* Transmit Arbitration Control 0 */ 5177 reg = E1000_READ_REG(hw, E1000_TARC(0)); 5178 if (hw->mac.type == e1000_ich8lan) 5179 reg |= (1 << 28) | (1 << 29); 5180 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 5181 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 5182 5183 /* Transmit Arbitration Control 1 */ 5184 reg = E1000_READ_REG(hw, E1000_TARC(1)); 5185 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 5186 reg &= ~(1 << 28); 5187 else 5188 reg |= (1 << 28); 5189 reg |= (1 << 24) | (1 << 26) | (1 << 30); 5190 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 5191 5192 /* Device Status */ 5193 if (hw->mac.type == e1000_ich8lan) { 5194 reg = E1000_READ_REG(hw, E1000_STATUS); 5195 reg &= ~(1UL << 31); 5196 E1000_WRITE_REG(hw, E1000_STATUS, reg); 5197 } 5198 5199 /* work-around descriptor data corruption issue during nfs v2 udp 5200 * traffic, just disable the nfs filtering capability 5201 */ 5202 reg = E1000_READ_REG(hw, E1000_RFCTL); 5203 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 5204 5205 /* Disable IPv6 extension header parsing because some malformed 5206 * IPv6 headers can hang the Rx. 5207 */ 5208 if (hw->mac.type == e1000_ich8lan) 5209 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 5210 E1000_WRITE_REG(hw, E1000_RFCTL, reg); 5211 5212 /* Enable ECC on Lynxpoint */ 5213 if (hw->mac.type >= e1000_pch_lpt) { 5214 reg = E1000_READ_REG(hw, E1000_PBECCSTS); 5215 reg |= E1000_PBECCSTS_ECC_ENABLE; 5216 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg); 5217 5218 reg = E1000_READ_REG(hw, E1000_CTRL); 5219 reg |= E1000_CTRL_MEHE; 5220 E1000_WRITE_REG(hw, E1000_CTRL, reg); 5221 } 5222 5223 return; 5224 } 5225 5226 /** 5227 * e1000_setup_link_ich8lan - Setup flow control and link settings 5228 * @hw: pointer to the HW structure 5229 * 5230 * Determines which flow control settings to use, then configures flow 5231 * control. Calls the appropriate media-specific link configuration 5232 * function. Assuming the adapter has a valid link partner, a valid link 5233 * should be established. Assumes the hardware has previously been reset 5234 * and the transmitter and receiver are not enabled. 5235 **/ 5236 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 5237 { 5238 s32 ret_val; 5239 5240 DEBUGFUNC("e1000_setup_link_ich8lan"); 5241 5242 if (hw->phy.ops.check_reset_block(hw)) 5243 return E1000_SUCCESS; 5244 5245 /* ICH parts do not have a word in the NVM to determine 5246 * the default flow control setting, so we explicitly 5247 * set it to full. 5248 */ 5249 if (hw->fc.requested_mode == e1000_fc_default) 5250 hw->fc.requested_mode = e1000_fc_full; 5251 5252 /* Save off the requested flow control mode for use later. Depending 5253 * on the link partner's capabilities, we may or may not use this mode. 5254 */ 5255 hw->fc.current_mode = hw->fc.requested_mode; 5256 5257 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 5258 hw->fc.current_mode); 5259 5260 /* Continue to configure the copper link. */ 5261 ret_val = hw->mac.ops.setup_physical_interface(hw); 5262 if (ret_val) 5263 return ret_val; 5264 5265 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 5266 if ((hw->phy.type == e1000_phy_82578) || 5267 (hw->phy.type == e1000_phy_82579) || 5268 (hw->phy.type == e1000_phy_i217) || 5269 (hw->phy.type == e1000_phy_82577)) { 5270 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time); 5271 5272 ret_val = hw->phy.ops.write_reg(hw, 5273 PHY_REG(BM_PORT_CTRL_PAGE, 27), 5274 hw->fc.pause_time); 5275 if (ret_val) 5276 return ret_val; 5277 } 5278 5279 return e1000_set_fc_watermarks_generic(hw); 5280 } 5281 5282 /** 5283 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 5284 * @hw: pointer to the HW structure 5285 * 5286 * Configures the kumeran interface to the PHY to wait the appropriate time 5287 * when polling the PHY, then call the generic setup_copper_link to finish 5288 * configuring the copper link. 5289 **/ 5290 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 5291 { 5292 u32 ctrl; 5293 s32 ret_val; 5294 u16 reg_data; 5295 5296 DEBUGFUNC("e1000_setup_copper_link_ich8lan"); 5297 5298 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5299 ctrl |= E1000_CTRL_SLU; 5300 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5301 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5302 5303 /* Set the mac to wait the maximum time between each iteration 5304 * and increase the max iterations when polling the phy; 5305 * this fixes erroneous timeouts at 10Mbps. 5306 */ 5307 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 5308 0xFFFF); 5309 if (ret_val) 5310 return ret_val; 5311 ret_val = e1000_read_kmrn_reg_generic(hw, 5312 E1000_KMRNCTRLSTA_INBAND_PARAM, 5313 ®_data); 5314 if (ret_val) 5315 return ret_val; 5316 reg_data |= 0x3F; 5317 ret_val = e1000_write_kmrn_reg_generic(hw, 5318 E1000_KMRNCTRLSTA_INBAND_PARAM, 5319 reg_data); 5320 if (ret_val) 5321 return ret_val; 5322 5323 switch (hw->phy.type) { 5324 case e1000_phy_igp_3: 5325 ret_val = e1000_copper_link_setup_igp(hw); 5326 if (ret_val) 5327 return ret_val; 5328 break; 5329 case e1000_phy_bm: 5330 case e1000_phy_82578: 5331 ret_val = e1000_copper_link_setup_m88(hw); 5332 if (ret_val) 5333 return ret_val; 5334 break; 5335 case e1000_phy_82577: 5336 case e1000_phy_82579: 5337 ret_val = e1000_copper_link_setup_82577(hw); 5338 if (ret_val) 5339 return ret_val; 5340 break; 5341 case e1000_phy_ife: 5342 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, 5343 ®_data); 5344 if (ret_val) 5345 return ret_val; 5346 5347 reg_data &= ~IFE_PMC_AUTO_MDIX; 5348 5349 switch (hw->phy.mdix) { 5350 case 1: 5351 reg_data &= ~IFE_PMC_FORCE_MDIX; 5352 break; 5353 case 2: 5354 reg_data |= IFE_PMC_FORCE_MDIX; 5355 break; 5356 case 0: 5357 default: 5358 reg_data |= IFE_PMC_AUTO_MDIX; 5359 break; 5360 } 5361 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, 5362 reg_data); 5363 if (ret_val) 5364 return ret_val; 5365 break; 5366 default: 5367 break; 5368 } 5369 5370 return e1000_setup_copper_link_generic(hw); 5371 } 5372 5373 /** 5374 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface 5375 * @hw: pointer to the HW structure 5376 * 5377 * Calls the PHY specific link setup function and then calls the 5378 * generic setup_copper_link to finish configuring the link for 5379 * Lynxpoint PCH devices 5380 **/ 5381 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) 5382 { 5383 u32 ctrl; 5384 s32 ret_val; 5385 5386 DEBUGFUNC("e1000_setup_copper_link_pch_lpt"); 5387 5388 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5389 ctrl |= E1000_CTRL_SLU; 5390 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5391 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5392 5393 ret_val = e1000_copper_link_setup_82577(hw); 5394 if (ret_val) 5395 return ret_val; 5396 5397 return e1000_setup_copper_link_generic(hw); 5398 } 5399 5400 /** 5401 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 5402 * @hw: pointer to the HW structure 5403 * @speed: pointer to store current link speed 5404 * @duplex: pointer to store the current link duplex 5405 * 5406 * Calls the generic get_speed_and_duplex to retrieve the current link 5407 * information and then calls the Kumeran lock loss workaround for links at 5408 * gigabit speeds. 5409 **/ 5410 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 5411 u16 *duplex) 5412 { 5413 s32 ret_val; 5414 5415 DEBUGFUNC("e1000_get_link_up_info_ich8lan"); 5416 5417 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 5418 if (ret_val) 5419 return ret_val; 5420 5421 if ((hw->mac.type == e1000_ich8lan) && 5422 (hw->phy.type == e1000_phy_igp_3) && 5423 (*speed == SPEED_1000)) { 5424 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 5425 } 5426 5427 return ret_val; 5428 } 5429 5430 /** 5431 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 5432 * @hw: pointer to the HW structure 5433 * 5434 * Work-around for 82566 Kumeran PCS lock loss: 5435 * On link status change (i.e. PCI reset, speed change) and link is up and 5436 * speed is gigabit- 5437 * 0) if workaround is optionally disabled do nothing 5438 * 1) wait 1ms for Kumeran link to come up 5439 * 2) check Kumeran Diagnostic register PCS lock loss bit 5440 * 3) if not set the link is locked (all is good), otherwise... 5441 * 4) reset the PHY 5442 * 5) repeat up to 10 times 5443 * Note: this is only called for IGP3 copper when speed is 1gb. 5444 **/ 5445 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 5446 { 5447 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5448 u32 phy_ctrl; 5449 s32 ret_val; 5450 u16 i, data; 5451 bool link; 5452 5453 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); 5454 5455 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 5456 return E1000_SUCCESS; 5457 5458 /* Make sure link is up before proceeding. If not just return. 5459 * Attempting this while link is negotiating fouled up link 5460 * stability 5461 */ 5462 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 5463 if (!link) 5464 return E1000_SUCCESS; 5465 5466 for (i = 0; i < 10; i++) { 5467 /* read once to clear */ 5468 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 5469 if (ret_val) 5470 return ret_val; 5471 /* and again to get new status */ 5472 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 5473 if (ret_val) 5474 return ret_val; 5475 5476 /* check for PCS lock */ 5477 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5478 return E1000_SUCCESS; 5479 5480 /* Issue PHY reset */ 5481 hw->phy.ops.reset(hw); 5482 msec_delay_irq(5); 5483 } 5484 /* Disable GigE link negotiation */ 5485 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 5486 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 5487 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5488 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 5489 5490 /* Call gig speed drop workaround on Gig disable before accessing 5491 * any PHY registers 5492 */ 5493 e1000_gig_downshift_workaround_ich8lan(hw); 5494 5495 /* unable to acquire PCS lock */ 5496 return -E1000_ERR_PHY; 5497 } 5498 5499 /** 5500 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 5501 * @hw: pointer to the HW structure 5502 * @state: boolean value used to set the current Kumeran workaround state 5503 * 5504 * If ICH8, set the current Kumeran workaround state (enabled - TRUE 5505 * /disabled - FALSE). 5506 **/ 5507 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 5508 bool state) 5509 { 5510 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5511 5512 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan"); 5513 5514 if (hw->mac.type != e1000_ich8lan) { 5515 DEBUGOUT("Workaround applies to ICH8 only.\n"); 5516 return; 5517 } 5518 5519 dev_spec->kmrn_lock_loss_workaround_enabled = state; 5520 5521 return; 5522 } 5523 5524 /** 5525 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 5526 * @hw: pointer to the HW structure 5527 * 5528 * Workaround for 82566 power-down on D3 entry: 5529 * 1) disable gigabit link 5530 * 2) write VR power-down enable 5531 * 3) read it back 5532 * Continue if successful, else issue LCD reset and repeat 5533 **/ 5534 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 5535 { 5536 u32 reg; 5537 u16 data; 5538 u8 retry = 0; 5539 5540 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); 5541 5542 if (hw->phy.type != e1000_phy_igp_3) 5543 return; 5544 5545 /* Try the workaround twice (if needed) */ 5546 do { 5547 /* Disable link */ 5548 reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 5549 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 5550 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5551 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); 5552 5553 /* Call gig speed drop workaround on Gig disable before 5554 * accessing any PHY registers 5555 */ 5556 if (hw->mac.type == e1000_ich8lan) 5557 e1000_gig_downshift_workaround_ich8lan(hw); 5558 5559 /* Write VR power-down enable */ 5560 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 5561 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5562 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL, 5563 data | IGP3_VR_CTRL_MODE_SHUTDOWN); 5564 5565 /* Read it back and test */ 5566 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 5567 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5568 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 5569 break; 5570 5571 /* Issue PHY reset and repeat at most one more time */ 5572 reg = E1000_READ_REG(hw, E1000_CTRL); 5573 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); 5574 retry++; 5575 } while (retry); 5576 } 5577 5578 /** 5579 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working 5580 * @hw: pointer to the HW structure 5581 * 5582 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 5583 * LPLU, Gig disable, MDIC PHY reset): 5584 * 1) Set Kumeran Near-end loopback 5585 * 2) Clear Kumeran Near-end loopback 5586 * Should only be called for ICH8[m] devices with any 1G Phy. 5587 **/ 5588 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 5589 { 5590 s32 ret_val; 5591 u16 reg_data; 5592 5593 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); 5594 5595 if ((hw->mac.type != e1000_ich8lan) || 5596 (hw->phy.type == e1000_phy_ife)) 5597 return; 5598 5599 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5600 ®_data); 5601 if (ret_val) 5602 return; 5603 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 5604 ret_val = e1000_write_kmrn_reg_generic(hw, 5605 E1000_KMRNCTRLSTA_DIAG_OFFSET, 5606 reg_data); 5607 if (ret_val) 5608 return; 5609 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 5610 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5611 reg_data); 5612 } 5613 5614 /** 5615 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 5616 * @hw: pointer to the HW structure 5617 * 5618 * During S0 to Sx transition, it is possible the link remains at gig 5619 * instead of negotiating to a lower speed. Before going to Sx, set 5620 * 'Gig Disable' to force link speed negotiation to a lower speed based on 5621 * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 5622 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 5623 * needs to be written. 5624 * Parts that support (and are linked to a partner which support) EEE in 5625 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 5626 * than 10Mbps w/o EEE. 5627 **/ 5628 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 5629 { 5630 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5631 u32 phy_ctrl; 5632 s32 ret_val; 5633 5634 DEBUGFUNC("e1000_suspend_workarounds_ich8lan"); 5635 5636 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 5637 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 5638 5639 if (hw->phy.type == e1000_phy_i217) { 5640 u16 phy_reg, device_id = hw->device_id; 5641 5642 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 5643 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 5644 (device_id == E1000_DEV_ID_PCH_I218_LM3) || 5645 (device_id == E1000_DEV_ID_PCH_I218_V3) || 5646 (hw->mac.type >= e1000_pch_spt)) { 5647 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); 5648 5649 E1000_WRITE_REG(hw, E1000_FEXTNVM6, 5650 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 5651 } 5652 5653 ret_val = hw->phy.ops.acquire(hw); 5654 if (ret_val) 5655 goto out; 5656 5657 if (!dev_spec->eee_disable) { 5658 u16 eee_advert; 5659 5660 ret_val = 5661 e1000_read_emi_reg_locked(hw, 5662 I217_EEE_ADVERTISEMENT, 5663 &eee_advert); 5664 if (ret_val) 5665 goto release; 5666 5667 /* Disable LPLU if both link partners support 100BaseT 5668 * EEE and 100Full is advertised on both ends of the 5669 * link, and enable Auto Enable LPI since there will 5670 * be no driver to enable LPI while in Sx. 5671 */ 5672 if ((eee_advert & I82579_EEE_100_SUPPORTED) && 5673 (dev_spec->eee_lp_ability & 5674 I82579_EEE_100_SUPPORTED) && 5675 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { 5676 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 5677 E1000_PHY_CTRL_NOND0A_LPLU); 5678 5679 /* Set Auto Enable LPI after link up */ 5680 hw->phy.ops.read_reg_locked(hw, 5681 I217_LPI_GPIO_CTRL, 5682 &phy_reg); 5683 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5684 hw->phy.ops.write_reg_locked(hw, 5685 I217_LPI_GPIO_CTRL, 5686 phy_reg); 5687 } 5688 } 5689 5690 /* For i217 Intel Rapid Start Technology support, 5691 * when the system is going into Sx and no manageability engine 5692 * is present, the driver must configure proxy to reset only on 5693 * power good. LPI (Low Power Idle) state must also reset only 5694 * on power good, as well as the MTA (Multicast table array). 5695 * The SMBus release must also be disabled on LCD reset. 5696 */ 5697 if (!(E1000_READ_REG(hw, E1000_FWSM) & 5698 E1000_ICH_FWSM_FW_VALID)) { 5699 /* Enable proxy to reset only on power good. */ 5700 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL, 5701 &phy_reg); 5702 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 5703 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 5704 phy_reg); 5705 5706 /* Set bit enable LPI (EEE) to reset only on 5707 * power good. 5708 */ 5709 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg); 5710 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 5711 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg); 5712 5713 /* Disable the SMB release on LCD reset. */ 5714 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg); 5715 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 5716 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); 5717 } 5718 5719 /* Enable MTA to reset for Intel Rapid Start Technology 5720 * Support 5721 */ 5722 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg); 5723 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 5724 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); 5725 5726 release: 5727 hw->phy.ops.release(hw); 5728 } 5729 out: 5730 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 5731 5732 if (hw->mac.type == e1000_ich8lan) 5733 e1000_gig_downshift_workaround_ich8lan(hw); 5734 5735 if (hw->mac.type >= e1000_pchlan) { 5736 e1000_oem_bits_config_ich8lan(hw, FALSE); 5737 5738 /* Reset PHY to activate OEM bits on 82577/8 */ 5739 if (hw->mac.type == e1000_pchlan) 5740 e1000_phy_hw_reset_generic(hw); 5741 5742 ret_val = hw->phy.ops.acquire(hw); 5743 if (ret_val) 5744 return; 5745 e1000_write_smbus_addr(hw); 5746 hw->phy.ops.release(hw); 5747 } 5748 5749 return; 5750 } 5751 5752 /** 5753 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 5754 * @hw: pointer to the HW structure 5755 * 5756 * During Sx to S0 transitions on non-managed devices or managed devices 5757 * on which PHY resets are not blocked, if the PHY registers cannot be 5758 * accessed properly by the s/w toggle the LANPHYPC value to power cycle 5759 * the PHY. 5760 * On i217, setup Intel Rapid Start Technology. 5761 **/ 5762 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 5763 { 5764 s32 ret_val; 5765 5766 DEBUGFUNC("e1000_resume_workarounds_pchlan"); 5767 if (hw->mac.type < e1000_pch2lan) 5768 return E1000_SUCCESS; 5769 5770 ret_val = e1000_init_phy_workarounds_pchlan(hw); 5771 if (ret_val) { 5772 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val); 5773 return ret_val; 5774 } 5775 5776 /* For i217 Intel Rapid Start Technology support when the system 5777 * is transitioning from Sx and no manageability engine is present 5778 * configure SMBus to restore on reset, disable proxy, and enable 5779 * the reset on MTA (Multicast table array). 5780 */ 5781 if (hw->phy.type == e1000_phy_i217) { 5782 u16 phy_reg; 5783 5784 ret_val = hw->phy.ops.acquire(hw); 5785 if (ret_val) { 5786 DEBUGOUT("Failed to setup iRST\n"); 5787 return ret_val; 5788 } 5789 5790 /* Clear Auto Enable LPI after link up */ 5791 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); 5792 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5793 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); 5794 5795 if (!(E1000_READ_REG(hw, E1000_FWSM) & 5796 E1000_ICH_FWSM_FW_VALID)) { 5797 /* Restore clear on SMB if no manageability engine 5798 * is present 5799 */ 5800 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, 5801 &phy_reg); 5802 if (ret_val) 5803 goto release; 5804 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 5805 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); 5806 5807 /* Disable Proxy */ 5808 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0); 5809 } 5810 /* Enable reset on MTA */ 5811 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG, 5812 &phy_reg); 5813 if (ret_val) 5814 goto release; 5815 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 5816 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); 5817 release: 5818 if (ret_val) 5819 DEBUGOUT1("Error %d in resume workarounds\n", ret_val); 5820 hw->phy.ops.release(hw); 5821 return ret_val; 5822 } 5823 return E1000_SUCCESS; 5824 } 5825 5826 /** 5827 * e1000_cleanup_led_ich8lan - Restore the default LED operation 5828 * @hw: pointer to the HW structure 5829 * 5830 * Return the LED back to the default configuration. 5831 **/ 5832 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 5833 { 5834 DEBUGFUNC("e1000_cleanup_led_ich8lan"); 5835 5836 if (hw->phy.type == e1000_phy_ife) 5837 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5838 0); 5839 5840 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 5841 return E1000_SUCCESS; 5842 } 5843 5844 /** 5845 * e1000_led_on_ich8lan - Turn LEDs on 5846 * @hw: pointer to the HW structure 5847 * 5848 * Turn on the LEDs. 5849 **/ 5850 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 5851 { 5852 DEBUGFUNC("e1000_led_on_ich8lan"); 5853 5854 if (hw->phy.type == e1000_phy_ife) 5855 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5856 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 5857 5858 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 5859 return E1000_SUCCESS; 5860 } 5861 5862 /** 5863 * e1000_led_off_ich8lan - Turn LEDs off 5864 * @hw: pointer to the HW structure 5865 * 5866 * Turn off the LEDs. 5867 **/ 5868 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 5869 { 5870 DEBUGFUNC("e1000_led_off_ich8lan"); 5871 5872 if (hw->phy.type == e1000_phy_ife) 5873 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5874 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 5875 5876 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 5877 return E1000_SUCCESS; 5878 } 5879 5880 /** 5881 * e1000_setup_led_pchlan - Configures SW controllable LED 5882 * @hw: pointer to the HW structure 5883 * 5884 * This prepares the SW controllable LED for use. 5885 **/ 5886 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 5887 { 5888 DEBUGFUNC("e1000_setup_led_pchlan"); 5889 5890 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 5891 (u16)hw->mac.ledctl_mode1); 5892 } 5893 5894 /** 5895 * e1000_cleanup_led_pchlan - Restore the default LED operation 5896 * @hw: pointer to the HW structure 5897 * 5898 * Return the LED back to the default configuration. 5899 **/ 5900 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 5901 { 5902 DEBUGFUNC("e1000_cleanup_led_pchlan"); 5903 5904 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 5905 (u16)hw->mac.ledctl_default); 5906 } 5907 5908 /** 5909 * e1000_led_on_pchlan - Turn LEDs on 5910 * @hw: pointer to the HW structure 5911 * 5912 * Turn on the LEDs. 5913 **/ 5914 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 5915 { 5916 u16 data = (u16)hw->mac.ledctl_mode2; 5917 u32 i, led; 5918 5919 DEBUGFUNC("e1000_led_on_pchlan"); 5920 5921 /* If no link, then turn LED on by setting the invert bit 5922 * for each LED that's mode is "link_up" in ledctl_mode2. 5923 */ 5924 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 5925 for (i = 0; i < 3; i++) { 5926 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5927 if ((led & E1000_PHY_LED0_MODE_MASK) != 5928 E1000_LEDCTL_MODE_LINK_UP) 5929 continue; 5930 if (led & E1000_PHY_LED0_IVRT) 5931 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5932 else 5933 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5934 } 5935 } 5936 5937 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 5938 } 5939 5940 /** 5941 * e1000_led_off_pchlan - Turn LEDs off 5942 * @hw: pointer to the HW structure 5943 * 5944 * Turn off the LEDs. 5945 **/ 5946 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 5947 { 5948 u16 data = (u16)hw->mac.ledctl_mode1; 5949 u32 i, led; 5950 5951 DEBUGFUNC("e1000_led_off_pchlan"); 5952 5953 /* If no link, then turn LED off by clearing the invert bit 5954 * for each LED that's mode is "link_up" in ledctl_mode1. 5955 */ 5956 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 5957 for (i = 0; i < 3; i++) { 5958 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5959 if ((led & E1000_PHY_LED0_MODE_MASK) != 5960 E1000_LEDCTL_MODE_LINK_UP) 5961 continue; 5962 if (led & E1000_PHY_LED0_IVRT) 5963 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5964 else 5965 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5966 } 5967 } 5968 5969 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 5970 } 5971 5972 /** 5973 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 5974 * @hw: pointer to the HW structure 5975 * 5976 * Read appropriate register for the config done bit for completion status 5977 * and configure the PHY through s/w for EEPROM-less parts. 5978 * 5979 * NOTE: some silicon which is EEPROM-less will fail trying to read the 5980 * config done bit, so only an error is logged and continues. If we were 5981 * to return with error, EEPROM-less silicon would not be able to be reset 5982 * or change link. 5983 **/ 5984 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 5985 { 5986 s32 ret_val = E1000_SUCCESS; 5987 u32 bank = 0; 5988 u32 status; 5989 5990 DEBUGFUNC("e1000_get_cfg_done_ich8lan"); 5991 5992 e1000_get_cfg_done_generic(hw); 5993 5994 /* Wait for indication from h/w that it has completed basic config */ 5995 if (hw->mac.type >= e1000_ich10lan) { 5996 e1000_lan_init_done_ich8lan(hw); 5997 } else { 5998 ret_val = e1000_get_auto_rd_done_generic(hw); 5999 if (ret_val) { 6000 /* When auto config read does not complete, do not 6001 * return with an error. This can happen in situations 6002 * where there is no eeprom and prevents getting link. 6003 */ 6004 DEBUGOUT("Auto Read Done did not complete\n"); 6005 ret_val = E1000_SUCCESS; 6006 } 6007 } 6008 6009 /* Clear PHY Reset Asserted bit */ 6010 status = E1000_READ_REG(hw, E1000_STATUS); 6011 if (status & E1000_STATUS_PHYRA) 6012 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA); 6013 else 6014 DEBUGOUT("PHY Reset Asserted not set - needs delay\n"); 6015 6016 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 6017 if (hw->mac.type <= e1000_ich9lan) { 6018 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && 6019 (hw->phy.type == e1000_phy_igp_3)) { 6020 e1000_phy_init_script_igp3(hw); 6021 } 6022 } else { 6023 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 6024 /* Maybe we should do a basic PHY config */ 6025 DEBUGOUT("EEPROM not present\n"); 6026 ret_val = -E1000_ERR_CONFIG; 6027 } 6028 } 6029 6030 return ret_val; 6031 } 6032 6033 /** 6034 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 6035 * @hw: pointer to the HW structure 6036 * 6037 * In the case of a PHY power down to save power, or to turn off link during a 6038 * driver unload, or wake on lan is not enabled, remove the link. 6039 **/ 6040 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 6041 { 6042 /* If the management interface is not enabled, then power down */ 6043 if (!(hw->mac.ops.check_mng_mode(hw) || 6044 hw->phy.ops.check_reset_block(hw))) 6045 e1000_power_down_phy_copper(hw); 6046 6047 return; 6048 } 6049 6050 /** 6051 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 6052 * @hw: pointer to the HW structure 6053 * 6054 * Clears hardware counters specific to the silicon family and calls 6055 * clear_hw_cntrs_generic to clear all general purpose counters. 6056 **/ 6057 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 6058 { 6059 u16 phy_data; 6060 s32 ret_val; 6061 6062 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan"); 6063 6064 e1000_clear_hw_cntrs_base_generic(hw); 6065 6066 E1000_READ_REG(hw, E1000_ALGNERRC); 6067 E1000_READ_REG(hw, E1000_RXERRC); 6068 E1000_READ_REG(hw, E1000_TNCRS); 6069 E1000_READ_REG(hw, E1000_CEXTERR); 6070 E1000_READ_REG(hw, E1000_TSCTC); 6071 E1000_READ_REG(hw, E1000_TSCTFC); 6072 6073 E1000_READ_REG(hw, E1000_MGTPRC); 6074 E1000_READ_REG(hw, E1000_MGTPDC); 6075 E1000_READ_REG(hw, E1000_MGTPTC); 6076 6077 E1000_READ_REG(hw, E1000_IAC); 6078 E1000_READ_REG(hw, E1000_ICRXOC); 6079 6080 /* Clear PHY statistics registers */ 6081 if ((hw->phy.type == e1000_phy_82578) || 6082 (hw->phy.type == e1000_phy_82579) || 6083 (hw->phy.type == e1000_phy_i217) || 6084 (hw->phy.type == e1000_phy_82577)) { 6085 ret_val = hw->phy.ops.acquire(hw); 6086 if (ret_val) 6087 return; 6088 ret_val = hw->phy.ops.set_page(hw, 6089 HV_STATS_PAGE << IGP_PAGE_SHIFT); 6090 if (ret_val) 6091 goto release; 6092 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 6093 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 6094 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 6095 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 6096 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 6097 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 6098 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 6099 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 6100 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 6101 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 6102 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 6103 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 6104 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 6105 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 6106 release: 6107 hw->phy.ops.release(hw); 6108 } 6109 } 6110 6111