1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4 support code. 14 * 15 * Copyright (C) 2011-2013 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23 #ifndef __T4NEX_H 24 #define __T4NEX_H 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 #define T4_IOCTL ((('t' << 16) | '4') << 8) 31 #define T4_IOCTL_PCIGET32 (T4_IOCTL + 1) 32 #define T4_IOCTL_PCIPUT32 (T4_IOCTL + 2) 33 #define T4_IOCTL_GET32 (T4_IOCTL + 3) 34 #define T4_IOCTL_PUT32 (T4_IOCTL + 4) 35 #define T4_IOCTL_REGDUMP (T4_IOCTL + 5) 36 #define T4_IOCTL_SGE_CONTEXT (T4_IOCTL + 6) 37 #define T4_IOCTL_DEVLOG (T4_IOCTL + 7) 38 #define T4_IOCTL_GET_MEM (T4_IOCTL + 8) 39 #define T4_IOCTL_GET_TID_TAB (T4_IOCTL + 9) 40 #define T4_IOCTL_GET_MBOX (T4_IOCTL + 10) 41 #define T4_IOCTL_GET_CIM_LA (T4_IOCTL + 11) 42 #define T4_IOCTL_GET_CIM_QCFG (T4_IOCTL + 12) 43 #define T4_IOCTL_GET_CIM_IBQ (T4_IOCTL + 13) 44 #define T4_IOCTL_GET_EDC (T4_IOCTL + 14) 45 #define T4_IOCTL_LOAD_FW (T4_IOCTL + 15) 46 #define T4_IOCTL_GET_CUDBG (T4_IOCTL + 16) 47 48 enum { 49 T4_CTXT_EGRESS, 50 T4_CTXT_INGRESS, 51 T4_CTXT_FLM 52 }; 53 54 struct t4_reg32_cmd { 55 uint32_t reg; 56 uint32_t value; 57 }; 58 59 #define T4_REGDUMP_SIZE (160 * 1024) 60 #define T6_REGDUMP_SIZE (332 * 1024) 61 #define T5_REGDUMP_SIZE (332 * 1024) 62 63 struct t4_regdump { 64 uint32_t version; 65 uint32_t len; 66 uint32_t *data; 67 }; 68 69 struct t4_sge_context { 70 uint32_t version; 71 uint32_t mem_id; 72 uint32_t addr; 73 uint32_t len; 74 uint8_t *data; 75 }; 76 77 struct t4_mem_range { 78 uint32_t addr; 79 uint32_t len; 80 uint32_t *data; 81 }; 82 83 struct t4_tid_info { 84 uint32_t len; 85 uint32_t *data; 86 }; 87 88 struct t4_mbox { 89 uint32_t len; 90 uint32_t *data; 91 }; 92 93 struct t4_cim_la { 94 uint32_t len; 95 uint32_t *data; 96 }; 97 98 struct t4_ibq { 99 uint32_t len; 100 uint32_t *data; 101 }; 102 103 struct t4_edc { 104 uint32_t len; 105 uint32_t mem; 106 uint32_t pos; 107 char *data; 108 }; 109 110 struct t4_cim_qcfg { 111 uint16_t base[14]; 112 uint16_t size[14]; 113 uint16_t thres[6]; 114 uint32_t stat[4 * (6 + 8)]; 115 uint32_t obq_wr[2 * (8)]; 116 uint32_t num_obq; 117 }; 118 119 #define T4_DEVLOG_SIZE 32768 120 struct t4_devlog { 121 uint32_t len; 122 uint32_t data[0]; 123 }; 124 125 struct t4_ldfw { 126 uint32_t len; 127 uint32_t data[0]; 128 }; 129 130 struct t4_cudbg_dump { 131 uint8_t wr_flash; 132 uint8_t bitmap[16]; 133 uint32_t len; 134 uint32_t data[0]; 135 }; 136 137 #ifdef __cplusplus 138 } 139 #endif 140 141 #endif /* __T4NEX_H */ 142