1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4 support code. 14 * 15 * Copyright (C) 2010-2013 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23 #include <sys/ddi.h> 24 #include <sys/sunddi.h> 25 #include <sys/sunndi.h> 26 #include <sys/atomic.h> 27 #include <sys/dlpi.h> 28 #include <sys/pattr.h> 29 #include <sys/strsubr.h> 30 #include <sys/stream.h> 31 #include <sys/strsun.h> 32 #include <inet/ip.h> 33 #include <inet/tcp.h> 34 35 #include "version.h" 36 #include "common/common.h" 37 #include "common/t4_msg.h" 38 #include "common/t4_regs.h" 39 #include "common/t4_regs_values.h" 40 41 /* TODO: Tune. */ 42 int rx_buf_size = 8192; 43 int tx_copy_threshold = 256; 44 uint16_t rx_copy_threshold = 256; 45 46 /* Used to track coalesced tx work request */ 47 struct txpkts { 48 mblk_t *tail; /* head is in the software descriptor */ 49 uint64_t *flitp; /* ptr to flit where next pkt should start */ 50 uint8_t npkt; /* # of packets in this work request */ 51 uint8_t nflits; /* # of flits used by this work request */ 52 uint16_t plen; /* total payload (sum of all packets) */ 53 }; 54 55 /* All information needed to tx a frame */ 56 struct txinfo { 57 uint32_t len; /* Total length of frame */ 58 uint32_t flags; /* Checksum and LSO flags */ 59 uint32_t mss; /* MSS for LSO */ 60 uint8_t nsegs; /* # of segments in the SGL, 0 means imm. tx */ 61 uint8_t nflits; /* # of flits needed for the SGL */ 62 uint8_t hdls_used; /* # of DMA handles used */ 63 uint32_t txb_used; /* txb_space used */ 64 struct ulptx_sgl sgl __attribute__((aligned(8))); 65 struct ulptx_sge_pair reserved[TX_SGL_SEGS / 2]; 66 }; 67 68 static int service_iq(struct sge_iq *iq, int budget); 69 static inline void init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, 70 int8_t pktc_idx, int qsize, uint8_t esize); 71 static inline void init_fl(struct sge_fl *fl, uint16_t qsize); 72 static inline void init_eq(struct adapter *sc, struct sge_eq *eq, 73 uint16_t eqtype, uint16_t qsize,uint8_t tx_chan, uint16_t iqid); 74 static int alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, 75 struct sge_fl *fl, int intr_idx, int cong); 76 static int free_iq_fl(struct port_info *pi, struct sge_iq *iq, 77 struct sge_fl *fl); 78 static int alloc_fwq(struct adapter *sc); 79 static int free_fwq(struct adapter *sc); 80 #ifdef TCP_OFFLOAD_ENABLE 81 static int alloc_mgmtq(struct adapter *sc); 82 #endif 83 static int alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, 84 int i); 85 static int free_rxq(struct port_info *pi, struct sge_rxq *rxq); 86 #ifdef TCP_OFFLOAD_ENABLE 87 static int alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq, 88 int intr_idx); 89 static int free_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq); 90 #endif 91 static int ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq); 92 static int eth_eq_alloc(struct adapter *sc, struct port_info *pi, 93 struct sge_eq *eq); 94 #ifdef TCP_OFFLOAD_ENABLE 95 static int ofld_eq_alloc(struct adapter *sc, struct port_info *pi, 96 struct sge_eq *eq); 97 #endif 98 static int alloc_eq(struct adapter *sc, struct port_info *pi, 99 struct sge_eq *eq); 100 static int free_eq(struct adapter *sc, struct sge_eq *eq); 101 #ifdef TCP_OFFLOAD_ENABLE 102 static int alloc_wrq(struct adapter *sc, struct port_info *pi, 103 struct sge_wrq *wrq, int idx); 104 static int free_wrq(struct adapter *sc, struct sge_wrq *wrq); 105 #endif 106 static int alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx); 107 static int free_txq(struct port_info *pi, struct sge_txq *txq); 108 static int alloc_dma_memory(struct adapter *sc, size_t len, int flags, 109 ddi_device_acc_attr_t *acc_attr, ddi_dma_attr_t *dma_attr, 110 ddi_dma_handle_t *dma_hdl, ddi_acc_handle_t *acc_hdl, uint64_t *pba, 111 caddr_t *pva); 112 static int free_dma_memory(ddi_dma_handle_t *dhdl, ddi_acc_handle_t *ahdl); 113 static int alloc_desc_ring(struct adapter *sc, size_t len, int rw, 114 ddi_dma_handle_t *dma_hdl, ddi_acc_handle_t *acc_hdl, uint64_t *pba, 115 caddr_t *pva); 116 static int free_desc_ring(ddi_dma_handle_t *dhdl, ddi_acc_handle_t *ahdl); 117 static int alloc_tx_copybuffer(struct adapter *sc, size_t len, 118 ddi_dma_handle_t *dma_hdl, ddi_acc_handle_t *acc_hdl, uint64_t *pba, 119 caddr_t *pva); 120 static inline bool is_new_response(const struct sge_iq *iq, 121 struct rsp_ctrl **ctrl); 122 static inline void iq_next(struct sge_iq *iq); 123 static int refill_fl(struct adapter *sc, struct sge_fl *fl, int nbufs); 124 static void refill_sfl(void *arg); 125 static void add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl); 126 static void free_fl_bufs(struct sge_fl *fl); 127 static mblk_t *get_fl_payload(struct adapter *sc, struct sge_fl *fl, 128 uint32_t len_newbuf, int *fl_bufs_used); 129 static int get_frame_txinfo(struct sge_txq *txq, mblk_t **fp, 130 struct txinfo *txinfo, int sgl_only); 131 static inline int fits_in_txb(struct sge_txq *txq, int len, int *waste); 132 static inline int copy_into_txb(struct sge_txq *txq, mblk_t *m, int len, 133 struct txinfo *txinfo); 134 static inline void add_seg(struct txinfo *txinfo, uint64_t ba, uint32_t len); 135 static inline int add_mblk(struct sge_txq *txq, struct txinfo *txinfo, 136 mblk_t *m, int len); 137 static void free_txinfo_resources(struct sge_txq *txq, struct txinfo *txinfo); 138 static int add_to_txpkts(struct sge_txq *txq, struct txpkts *txpkts, mblk_t *m, 139 struct txinfo *txinfo); 140 static void write_txpkts_wr(struct sge_txq *txq, struct txpkts *txpkts); 141 static int write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, mblk_t *m, 142 struct txinfo *txinfo); 143 static inline void write_ulp_cpl_sgl(struct port_info *pi, struct sge_txq *txq, 144 struct txpkts *txpkts, struct txinfo *txinfo); 145 static inline void copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, 146 int len); 147 static inline void ring_tx_db(struct adapter *sc, struct sge_eq *eq); 148 static int reclaim_tx_descs(struct sge_txq *txq, int howmany); 149 static void write_txqflush_wr(struct sge_txq *txq); 150 static int t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, 151 mblk_t *m); 152 static inline void ring_fl_db(struct adapter *sc, struct sge_fl *fl); 153 static kstat_t *setup_port_config_kstats(struct port_info *pi); 154 static kstat_t *setup_port_info_kstats(struct port_info *pi); 155 static kstat_t *setup_rxq_kstats(struct port_info *pi, struct sge_rxq *rxq, 156 int idx); 157 static int update_rxq_kstats(kstat_t *ksp, int rw); 158 static int update_port_info_kstats(kstat_t *ksp, int rw); 159 static kstat_t *setup_txq_kstats(struct port_info *pi, struct sge_txq *txq, 160 int idx); 161 static int update_txq_kstats(kstat_t *ksp, int rw); 162 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 163 mblk_t *); 164 static int handle_fw_rpl(struct sge_iq *iq, const struct rss_header *rss, 165 mblk_t *m); 166 167 static inline int 168 reclaimable(struct sge_eq *eq) 169 { 170 unsigned int cidx; 171 172 cidx = eq->spg->cidx; /* stable snapshot */ 173 cidx = be16_to_cpu(cidx); 174 175 if (cidx >= eq->cidx) 176 return (cidx - eq->cidx); 177 else 178 return (cidx + eq->cap - eq->cidx); 179 } 180 181 void 182 t4_sge_init(struct adapter *sc) 183 { 184 struct driver_properties *p = &sc->props; 185 ddi_dma_attr_t *dma_attr; 186 ddi_device_acc_attr_t *acc_attr; 187 uint32_t sge_control, sge_conm_ctrl; 188 int egress_threshold; 189 190 /* 191 * Device access and DMA attributes for descriptor rings 192 */ 193 acc_attr = &sc->sge.acc_attr_desc; 194 acc_attr->devacc_attr_version = DDI_DEVICE_ATTR_V0; 195 acc_attr->devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 196 acc_attr->devacc_attr_dataorder = DDI_STRICTORDER_ACC; 197 198 dma_attr = &sc->sge.dma_attr_desc; 199 dma_attr->dma_attr_version = DMA_ATTR_V0; 200 dma_attr->dma_attr_addr_lo = 0; 201 dma_attr->dma_attr_addr_hi = UINT64_MAX; 202 dma_attr->dma_attr_count_max = UINT64_MAX; 203 dma_attr->dma_attr_align = 512; 204 dma_attr->dma_attr_burstsizes = 0xfff; 205 dma_attr->dma_attr_minxfer = 1; 206 dma_attr->dma_attr_maxxfer = UINT64_MAX; 207 dma_attr->dma_attr_seg = UINT64_MAX; 208 dma_attr->dma_attr_sgllen = 1; 209 dma_attr->dma_attr_granular = 1; 210 dma_attr->dma_attr_flags = 0; 211 212 /* 213 * Device access and DMA attributes for tx buffers 214 */ 215 acc_attr = &sc->sge.acc_attr_tx; 216 acc_attr->devacc_attr_version = DDI_DEVICE_ATTR_V0; 217 acc_attr->devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 218 219 dma_attr = &sc->sge.dma_attr_tx; 220 dma_attr->dma_attr_version = DMA_ATTR_V0; 221 dma_attr->dma_attr_addr_lo = 0; 222 dma_attr->dma_attr_addr_hi = UINT64_MAX; 223 dma_attr->dma_attr_count_max = UINT64_MAX; 224 dma_attr->dma_attr_align = 1; 225 dma_attr->dma_attr_burstsizes = 0xfff; 226 dma_attr->dma_attr_minxfer = 1; 227 dma_attr->dma_attr_maxxfer = UINT64_MAX; 228 dma_attr->dma_attr_seg = UINT64_MAX; 229 dma_attr->dma_attr_sgllen = TX_SGL_SEGS; 230 dma_attr->dma_attr_granular = 1; 231 dma_attr->dma_attr_flags = 0; 232 233 /* 234 * Ingress Padding Boundary and Egress Status Page Size are set up by 235 * t4_fixup_host_params(). 236 */ 237 sge_control = t4_read_reg(sc, A_SGE_CONTROL); 238 sc->sge.pktshift = G_PKTSHIFT(sge_control); 239 sc->sge.stat_len = (sge_control & F_EGRSTATUSPAGESIZE) ? 128 : 64; 240 241 /* t4_nex uses FLM packed mode */ 242 sc->sge.fl_align = t4_fl_pkt_align(sc, true); 243 244 /* 245 * Device access and DMA attributes for rx buffers 246 */ 247 sc->sge.rxb_params.dip = sc->dip; 248 sc->sge.rxb_params.buf_size = rx_buf_size; 249 250 acc_attr = &sc->sge.rxb_params.acc_attr_rx; 251 acc_attr->devacc_attr_version = DDI_DEVICE_ATTR_V0; 252 acc_attr->devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 253 254 dma_attr = &sc->sge.rxb_params.dma_attr_rx; 255 dma_attr->dma_attr_version = DMA_ATTR_V0; 256 dma_attr->dma_attr_addr_lo = 0; 257 dma_attr->dma_attr_addr_hi = UINT64_MAX; 258 dma_attr->dma_attr_count_max = UINT64_MAX; 259 /* 260 * Low 4 bits of an rx buffer address have a special meaning to the SGE 261 * and an rx buf cannot have an address with any of these bits set. 262 * FL_ALIGN is >= 32 so we're sure things are ok. 263 */ 264 dma_attr->dma_attr_align = sc->sge.fl_align; 265 dma_attr->dma_attr_burstsizes = 0xfff; 266 dma_attr->dma_attr_minxfer = 1; 267 dma_attr->dma_attr_maxxfer = UINT64_MAX; 268 dma_attr->dma_attr_seg = UINT64_MAX; 269 dma_attr->dma_attr_sgllen = 1; 270 dma_attr->dma_attr_granular = 1; 271 dma_attr->dma_attr_flags = 0; 272 273 sc->sge.rxbuf_cache = rxbuf_cache_create(&sc->sge.rxb_params); 274 275 /* 276 * A FL with <= fl_starve_thres buffers is starving and a periodic 277 * timer will attempt to refill it. This needs to be larger than the 278 * SGE's Egress Congestion Threshold. If it isn't, then we can get 279 * stuck waiting for new packets while the SGE is waiting for us to 280 * give it more Free List entries. (Note that the SGE's Egress 281 * Congestion Threshold is in units of 2 Free List pointers.) For T4, 282 * there was only a single field to control this. For T5 there's the 283 * original field which now only applies to Unpacked Mode Free List 284 * buffers and a new field which only applies to Packed Mode Free List 285 * buffers. 286 */ 287 288 sge_conm_ctrl = t4_read_reg(sc, A_SGE_CONM_CTRL); 289 switch (CHELSIO_CHIP_VERSION(sc->params.chip)) { 290 case CHELSIO_T4: 291 egress_threshold = G_EGRTHRESHOLD(sge_conm_ctrl); 292 break; 293 case CHELSIO_T5: 294 egress_threshold = G_EGRTHRESHOLDPACKING(sge_conm_ctrl); 295 break; 296 case CHELSIO_T6: 297 default: 298 egress_threshold = G_T6_EGRTHRESHOLDPACKING(sge_conm_ctrl); 299 } 300 sc->sge.fl_starve_threshold = 2*egress_threshold + 1; 301 302 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, rx_buf_size); 303 304 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, 305 V_THRESHOLD_0(p->counter_val[0]) | 306 V_THRESHOLD_1(p->counter_val[1]) | 307 V_THRESHOLD_2(p->counter_val[2]) | 308 V_THRESHOLD_3(p->counter_val[3])); 309 310 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, 311 V_TIMERVALUE0(us_to_core_ticks(sc, p->timer_val[0])) | 312 V_TIMERVALUE1(us_to_core_ticks(sc, p->timer_val[1]))); 313 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, 314 V_TIMERVALUE2(us_to_core_ticks(sc, p->timer_val[2])) | 315 V_TIMERVALUE3(us_to_core_ticks(sc, p->timer_val[3]))); 316 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, 317 V_TIMERVALUE4(us_to_core_ticks(sc, p->timer_val[4])) | 318 V_TIMERVALUE5(us_to_core_ticks(sc, p->timer_val[5]))); 319 320 (void) t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_rpl); 321 (void) t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_rpl); 322 (void) t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 323 (void) t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx); 324 (void) t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, 325 t4_handle_fw_rpl); 326 } 327 328 /* 329 * Allocate and initialize the firmware event queue and the forwarded interrupt 330 * queues, if any. The adapter owns all these queues as they are not associated 331 * with any particular port. 332 * 333 * Returns errno on failure. Resources allocated up to that point may still be 334 * allocated. Caller is responsible for cleanup in case this function fails. 335 */ 336 int 337 t4_setup_adapter_queues(struct adapter *sc) 338 { 339 int rc; 340 341 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 342 343 /* 344 * Firmware event queue 345 */ 346 rc = alloc_fwq(sc); 347 if (rc != 0) 348 return (rc); 349 350 #ifdef TCP_OFFLOAD_ENABLE 351 /* 352 * Management queue. This is just a control queue that uses the fwq as 353 * its associated iq. 354 */ 355 rc = alloc_mgmtq(sc); 356 #endif 357 358 return (rc); 359 } 360 361 /* 362 * Idempotent 363 */ 364 int 365 t4_teardown_adapter_queues(struct adapter *sc) 366 { 367 368 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 369 370 (void) free_fwq(sc); 371 372 return (0); 373 } 374 375 static inline int 376 first_vector(struct port_info *pi) 377 { 378 struct adapter *sc = pi->adapter; 379 int rc = T4_EXTRA_INTR, i; 380 381 if (sc->intr_count == 1) 382 return (0); 383 384 for_each_port(sc, i) { 385 struct port_info *p = sc->port[i]; 386 387 if (i == pi->port_id) 388 break; 389 390 #ifdef TCP_OFFLOAD_ENABLE 391 if (!(sc->flags & INTR_FWD)) 392 rc += p->nrxq + p->nofldrxq; 393 else 394 rc += max(p->nrxq, p->nofldrxq); 395 #else 396 /* 397 * Not compiled with offload support and intr_count > 1. Only 398 * NIC queues exist and they'd better be taking direct 399 * interrupts. 400 */ 401 ASSERT(!(sc->flags & INTR_FWD)); 402 rc += p->nrxq; 403 #endif 404 } 405 return (rc); 406 } 407 408 /* 409 * Given an arbitrary "index," come up with an iq that can be used by other 410 * queues (of this port) for interrupt forwarding, SGE egress updates, etc. 411 * The iq returned is guaranteed to be something that takes direct interrupts. 412 */ 413 static struct sge_iq * 414 port_intr_iq(struct port_info *pi, int idx) 415 { 416 struct adapter *sc = pi->adapter; 417 struct sge *s = &sc->sge; 418 struct sge_iq *iq = NULL; 419 420 if (sc->intr_count == 1) 421 return (&sc->sge.fwq); 422 423 #ifdef TCP_OFFLOAD_ENABLE 424 if (!(sc->flags & INTR_FWD)) { 425 idx %= pi->nrxq + pi->nofldrxq; 426 427 if (idx >= pi->nrxq) { 428 idx -= pi->nrxq; 429 iq = &s->ofld_rxq[pi->first_ofld_rxq + idx].iq; 430 } else 431 iq = &s->rxq[pi->first_rxq + idx].iq; 432 433 } else { 434 idx %= max(pi->nrxq, pi->nofldrxq); 435 436 if (pi->nrxq >= pi->nofldrxq) 437 iq = &s->rxq[pi->first_rxq + idx].iq; 438 else 439 iq = &s->ofld_rxq[pi->first_ofld_rxq + idx].iq; 440 } 441 #else 442 /* 443 * Not compiled with offload support and intr_count > 1. Only NIC 444 * queues exist and they'd better be taking direct interrupts. 445 */ 446 ASSERT(!(sc->flags & INTR_FWD)); 447 448 idx %= pi->nrxq; 449 iq = &s->rxq[pi->first_rxq + idx].iq; 450 #endif 451 452 return (iq); 453 } 454 455 int 456 t4_setup_port_queues(struct port_info *pi) 457 { 458 int rc = 0, i, intr_idx, j; 459 struct sge_rxq *rxq; 460 struct sge_txq *txq; 461 #ifdef TCP_OFFLOAD_ENABLE 462 int iqid; 463 struct sge_wrq *ctrlq; 464 struct sge_ofld_rxq *ofld_rxq; 465 struct sge_wrq *ofld_txq; 466 #endif 467 struct adapter *sc = pi->adapter; 468 struct driver_properties *p = &sc->props; 469 470 pi->ksp_config = setup_port_config_kstats(pi); 471 pi->ksp_info = setup_port_info_kstats(pi); 472 473 /* Interrupt vector to start from (when using multiple vectors) */ 474 intr_idx = first_vector(pi); 475 476 /* 477 * First pass over all rx queues (NIC and TOE): 478 * a) initialize iq and fl 479 * b) allocate queue iff it will take direct interrupts. 480 */ 481 482 for_each_rxq(pi, i, rxq) { 483 484 init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, p->qsize_rxq, 485 RX_IQ_ESIZE); 486 487 init_fl(&rxq->fl, p->qsize_rxq / 8); /* 8 bufs in each entry */ 488 489 if ((!(sc->flags & INTR_FWD)) 490 #ifdef TCP_OFFLOAD_ENABLE 491 || (sc->intr_count > 1 && pi->nrxq >= pi->nofldrxq) 492 #else 493 || (sc->intr_count > 1 && pi->nrxq) 494 #endif 495 ) { 496 rxq->iq.flags |= IQ_INTR; 497 rc = alloc_rxq(pi, rxq, intr_idx, i); 498 if (rc != 0) 499 goto done; 500 intr_idx++; 501 } 502 503 } 504 505 #ifdef TCP_OFFLOAD_ENABLE 506 for_each_ofld_rxq(pi, i, ofld_rxq) { 507 508 init_iq(&ofld_rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, 509 p->qsize_rxq, RX_IQ_ESIZE); 510 511 init_fl(&ofld_rxq->fl, p->qsize_rxq / 8); 512 513 if (!(sc->flags & INTR_FWD) || 514 (sc->intr_count > 1 && pi->nofldrxq > pi->nrxq)) { 515 ofld_rxq->iq.flags = IQ_INTR; 516 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx); 517 if (rc != 0) 518 goto done; 519 520 intr_idx++; 521 } 522 } 523 #endif 524 525 /* 526 * Second pass over all rx queues (NIC and TOE). The queues forwarding 527 * their interrupts are allocated now. 528 */ 529 j = 0; 530 for_each_rxq(pi, i, rxq) { 531 if (rxq->iq.flags & IQ_INTR) 532 continue; 533 534 intr_idx = port_intr_iq(pi, j)->abs_id; 535 536 rc = alloc_rxq(pi, rxq, intr_idx, i); 537 if (rc != 0) 538 goto done; 539 j++; 540 } 541 542 #ifdef TCP_OFFLOAD_ENABLE 543 for_each_ofld_rxq(pi, i, ofld_rxq) { 544 if (ofld_rxq->iq.flags & IQ_INTR) 545 continue; 546 547 intr_idx = port_intr_iq(pi, j)->abs_id; 548 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx); 549 if (rc != 0) 550 goto done; 551 j++; 552 } 553 #endif 554 /* 555 * Now the tx queues. Only one pass needed. 556 */ 557 j = 0; 558 for_each_txq(pi, i, txq) { 559 uint16_t iqid; 560 561 iqid = port_intr_iq(pi, j)->cntxt_id; 562 init_eq(sc, &txq->eq, EQ_ETH, p->qsize_txq, pi->tx_chan, iqid); 563 rc = alloc_txq(pi, txq, i); 564 if (rc != 0) 565 goto done; 566 } 567 568 #ifdef TCP_OFFLOAD_ENABLE 569 for_each_ofld_txq(pi, i, ofld_txq) { 570 uint16_t iqid; 571 572 iqid = port_intr_iq(pi, j)->cntxt_id; 573 init_eq(sc, &ofld_txq->eq, EQ_OFLD, p->qsize_txq, pi->tx_chan, 574 iqid); 575 rc = alloc_wrq(sc, pi, ofld_txq, i); 576 if (rc != 0) 577 goto done; 578 } 579 580 /* 581 * Finally, the control queue. 582 */ 583 ctrlq = &sc->sge.ctrlq[pi->port_id]; 584 iqid = port_intr_iq(pi, 0)->cntxt_id; 585 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid); 586 rc = alloc_wrq(sc, pi, ctrlq, 0); 587 #endif 588 589 done: 590 if (rc != 0) 591 (void) t4_teardown_port_queues(pi); 592 593 return (rc); 594 } 595 596 /* 597 * Idempotent 598 */ 599 int 600 t4_teardown_port_queues(struct port_info *pi) 601 { 602 int i; 603 struct sge_rxq *rxq; 604 struct sge_txq *txq; 605 #ifdef TCP_OFFLOAD_ENABLE 606 struct adapter *sc = pi->adapter; 607 struct sge_ofld_rxq *ofld_rxq; 608 struct sge_wrq *ofld_txq; 609 #endif 610 611 if (pi->ksp_config != NULL) { 612 kstat_delete(pi->ksp_config); 613 pi->ksp_config = NULL; 614 } 615 if (pi->ksp_info != NULL) { 616 kstat_delete(pi->ksp_info); 617 pi->ksp_info = NULL; 618 } 619 620 #ifdef TCP_OFFLOAD_ENABLE 621 (void) free_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 622 #endif 623 624 for_each_txq(pi, i, txq) { 625 (void) free_txq(pi, txq); 626 } 627 628 #ifdef TCP_OFFLOAD_ENABLE 629 for_each_ofld_txq(pi, i, ofld_txq) { 630 (void) free_wrq(sc, ofld_txq); 631 } 632 633 for_each_ofld_rxq(pi, i, ofld_rxq) { 634 if ((ofld_rxq->iq.flags & IQ_INTR) == 0) 635 (void) free_ofld_rxq(pi, ofld_rxq); 636 } 637 #endif 638 639 for_each_rxq(pi, i, rxq) { 640 if ((rxq->iq.flags & IQ_INTR) == 0) 641 (void) free_rxq(pi, rxq); 642 } 643 644 /* 645 * Then take down the rx queues that take direct interrupts. 646 */ 647 648 for_each_rxq(pi, i, rxq) { 649 if (rxq->iq.flags & IQ_INTR) 650 (void) free_rxq(pi, rxq); 651 } 652 653 #ifdef TCP_OFFLOAD_ENABLE 654 for_each_ofld_rxq(pi, i, ofld_rxq) { 655 if (ofld_rxq->iq.flags & IQ_INTR) 656 (void) free_ofld_rxq(pi, ofld_rxq); 657 } 658 #endif 659 660 return (0); 661 } 662 663 /* Deals with errors and forwarded interrupts */ 664 uint_t 665 t4_intr_all(caddr_t arg1, caddr_t arg2) 666 { 667 668 (void) t4_intr_err(arg1, arg2); 669 (void) t4_intr(arg1, arg2); 670 671 return (DDI_INTR_CLAIMED); 672 } 673 674 static void 675 t4_intr_rx_work(struct sge_iq *iq) 676 { 677 mblk_t *mp = NULL; 678 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */ 679 RXQ_LOCK(rxq); 680 if (!iq->polling) { 681 mp = t4_ring_rx(rxq, iq->qsize/8); 682 t4_write_reg(iq->adapter, MYPF_REG(A_SGE_PF_GTS), 683 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_next)); 684 } 685 RXQ_UNLOCK(rxq); 686 if (mp != NULL) 687 mac_rx_ring(rxq->port->mh, rxq->ring_handle, mp, 688 rxq->ring_gen_num); 689 } 690 691 /* Deals with interrupts on the given ingress queue */ 692 /* ARGSUSED */ 693 uint_t 694 t4_intr(caddr_t arg1, caddr_t arg2) 695 { 696 /* LINTED: E_BAD_PTR_CAST_ALIGN */ 697 struct sge_iq *iq = (struct sge_iq *)arg2; 698 int state; 699 700 /* Right now receive polling is only enabled for MSI-X and 701 * when we have enough msi-x vectors i.e no interrupt forwarding. 702 */ 703 if (iq->adapter->props.multi_rings) { 704 t4_intr_rx_work(iq); 705 } else { 706 state = atomic_cas_uint(&iq->state, IQS_IDLE, IQS_BUSY); 707 if (state == IQS_IDLE) { 708 (void) service_iq(iq, 0); 709 (void) atomic_cas_uint(&iq->state, IQS_BUSY, IQS_IDLE); 710 } 711 } 712 return (DDI_INTR_CLAIMED); 713 } 714 715 /* Deals with error interrupts */ 716 /* ARGSUSED */ 717 uint_t 718 t4_intr_err(caddr_t arg1, caddr_t arg2) 719 { 720 /* LINTED: E_BAD_PTR_CAST_ALIGN */ 721 struct adapter *sc = (struct adapter *)arg1; 722 723 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 724 (void) t4_slow_intr_handler(sc); 725 726 return (DDI_INTR_CLAIMED); 727 } 728 729 /* 730 * t4_ring_rx - Process responses from an SGE response queue. 731 * 732 * This function processes responses from an SGE response queue up to the supplied budget. 733 * Responses include received packets as well as control messages from FW 734 * or HW. 735 * It returns a chain of mblks containing the received data, to be 736 * passed up to mac_ring_rx(). 737 */ 738 mblk_t * 739 t4_ring_rx(struct sge_rxq *rxq, int budget) 740 { 741 struct sge_iq *iq = &rxq->iq; 742 struct sge_fl *fl = &rxq->fl; /* Use iff IQ_HAS_FL */ 743 struct adapter *sc = iq->adapter; 744 struct rsp_ctrl *ctrl; 745 const struct rss_header *rss; 746 int ndescs = 0, fl_bufs_used = 0; 747 int rsp_type; 748 uint32_t lq; 749 mblk_t *mblk_head = NULL, **mblk_tail, *m; 750 struct cpl_rx_pkt *cpl; 751 uint32_t received_bytes = 0, pkt_len = 0; 752 bool csum_ok; 753 uint16_t err_vec; 754 755 mblk_tail = &mblk_head; 756 757 while (is_new_response(iq, &ctrl)) { 758 759 membar_consumer(); 760 761 m = NULL; 762 rsp_type = G_RSPD_TYPE(ctrl->u.type_gen); 763 lq = be32_to_cpu(ctrl->pldbuflen_qid); 764 rss = (const void *)iq->cdesc; 765 766 switch (rsp_type) { 767 case X_RSPD_TYPE_FLBUF: 768 769 ASSERT(iq->flags & IQ_HAS_FL); 770 771 if (CPL_RX_PKT == rss->opcode) { 772 cpl = (void *)(rss + 1); 773 pkt_len = be16_to_cpu(cpl->len); 774 775 if (iq->polling && ((received_bytes + pkt_len) > budget)) 776 goto done; 777 778 m = get_fl_payload(sc, fl, lq, &fl_bufs_used); 779 if (m == NULL) { 780 panic("%s: line %d.", __func__, 781 __LINE__); 782 } 783 784 iq->intr_next = iq->intr_params; 785 m->b_rptr += sc->sge.pktshift; 786 if (sc->params.tp.rx_pkt_encap) 787 /* It is enabled only in T6 config file */ 788 err_vec = G_T6_COMPR_RXERR_VEC(ntohs(cpl->err_vec)); 789 else 790 err_vec = ntohs(cpl->err_vec); 791 792 csum_ok = cpl->csum_calc && !err_vec; 793 794 /* TODO: what about cpl->ip_frag? */ 795 if (csum_ok && !cpl->ip_frag) { 796 mac_hcksum_set(m, 0, 0, 0, 0xffff, 797 HCK_FULLCKSUM_OK | HCK_FULLCKSUM | 798 HCK_IPV4_HDRCKSUM_OK); 799 rxq->rxcsum++; 800 } 801 rxq->rxpkts++; 802 rxq->rxbytes += pkt_len; 803 received_bytes += pkt_len; 804 805 *mblk_tail = m; 806 mblk_tail = &m->b_next; 807 808 break; 809 } 810 811 m = get_fl_payload(sc, fl, lq, &fl_bufs_used); 812 if (m == NULL) { 813 panic("%s: line %d.", __func__, 814 __LINE__); 815 } 816 817 case X_RSPD_TYPE_CPL: 818 ASSERT(rss->opcode < NUM_CPL_CMDS); 819 sc->cpl_handler[rss->opcode](iq, rss, m); 820 break; 821 822 default: 823 break; 824 } 825 iq_next(iq); 826 ++ndescs; 827 if (!iq->polling && (ndescs == budget)) 828 break; 829 } 830 831 done: 832 833 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), 834 V_CIDXINC(ndescs) | V_INGRESSQID(iq->cntxt_id) | 835 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 836 837 if ((fl_bufs_used > 0) || (iq->flags & IQ_HAS_FL)) { 838 int starved; 839 FL_LOCK(fl); 840 fl->needed += fl_bufs_used; 841 starved = refill_fl(sc, fl, fl->cap / 8); 842 FL_UNLOCK(fl); 843 if (starved) 844 add_fl_to_sfl(sc, fl); 845 } 846 return (mblk_head); 847 } 848 849 /* 850 * Deals with anything and everything on the given ingress queue. 851 */ 852 static int 853 service_iq(struct sge_iq *iq, int budget) 854 { 855 struct sge_iq *q; 856 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */ 857 struct sge_fl *fl = &rxq->fl; /* Use iff IQ_HAS_FL */ 858 struct adapter *sc = iq->adapter; 859 struct rsp_ctrl *ctrl; 860 const struct rss_header *rss; 861 int ndescs = 0, limit, fl_bufs_used = 0; 862 int rsp_type; 863 uint32_t lq; 864 mblk_t *m; 865 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 866 867 limit = budget ? budget : iq->qsize / 8; 868 869 /* 870 * We always come back and check the descriptor ring for new indirect 871 * interrupts and other responses after running a single handler. 872 */ 873 for (;;) { 874 while (is_new_response(iq, &ctrl)) { 875 876 membar_consumer(); 877 878 m = NULL; 879 rsp_type = G_RSPD_TYPE(ctrl->u.type_gen); 880 lq = be32_to_cpu(ctrl->pldbuflen_qid); 881 rss = (const void *)iq->cdesc; 882 883 switch (rsp_type) { 884 case X_RSPD_TYPE_FLBUF: 885 886 ASSERT(iq->flags & IQ_HAS_FL); 887 888 m = get_fl_payload(sc, fl, lq, &fl_bufs_used); 889 if (m == NULL) { 890 panic("%s: line %d.", __func__, 891 __LINE__); 892 } 893 894 /* FALLTHRU */ 895 case X_RSPD_TYPE_CPL: 896 897 ASSERT(rss->opcode < NUM_CPL_CMDS); 898 sc->cpl_handler[rss->opcode](iq, rss, m); 899 break; 900 901 case X_RSPD_TYPE_INTR: 902 903 /* 904 * Interrupts should be forwarded only to queues 905 * that are not forwarding their interrupts. 906 * This means service_iq can recurse but only 1 907 * level deep. 908 */ 909 ASSERT(budget == 0); 910 911 q = sc->sge.iqmap[lq - sc->sge.iq_start]; 912 if (atomic_cas_uint(&q->state, IQS_IDLE, 913 IQS_BUSY) == IQS_IDLE) { 914 if (service_iq(q, q->qsize / 8) == 0) { 915 (void) atomic_cas_uint( 916 &q->state, IQS_BUSY, 917 IQS_IDLE); 918 } else { 919 STAILQ_INSERT_TAIL(&iql, q, 920 link); 921 } 922 } 923 break; 924 925 default: 926 break; 927 } 928 929 iq_next(iq); 930 if (++ndescs == limit) { 931 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), 932 V_CIDXINC(ndescs) | 933 V_INGRESSQID(iq->cntxt_id) | 934 V_SEINTARM(V_QINTR_TIMER_IDX( 935 X_TIMERREG_UPDATE_CIDX))); 936 ndescs = 0; 937 938 if (fl_bufs_used > 0) { 939 ASSERT(iq->flags & IQ_HAS_FL); 940 FL_LOCK(fl); 941 fl->needed += fl_bufs_used; 942 (void) refill_fl(sc, fl, fl->cap / 8); 943 FL_UNLOCK(fl); 944 fl_bufs_used = 0; 945 } 946 947 if (budget != 0) 948 return (EINPROGRESS); 949 } 950 } 951 952 if (STAILQ_EMPTY(&iql) != 0) 953 break; 954 955 /* 956 * Process the head only, and send it to the back of the list if 957 * it's still not done. 958 */ 959 q = STAILQ_FIRST(&iql); 960 STAILQ_REMOVE_HEAD(&iql, link); 961 if (service_iq(q, q->qsize / 8) == 0) 962 (void) atomic_cas_uint(&q->state, IQS_BUSY, IQS_IDLE); 963 else 964 STAILQ_INSERT_TAIL(&iql, q, link); 965 } 966 967 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) | 968 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_next)); 969 970 if (iq->flags & IQ_HAS_FL) { 971 int starved; 972 973 FL_LOCK(fl); 974 fl->needed += fl_bufs_used; 975 starved = refill_fl(sc, fl, fl->cap / 4); 976 FL_UNLOCK(fl); 977 if (starved != 0) 978 add_fl_to_sfl(sc, fl); 979 } 980 981 return (0); 982 } 983 984 #ifdef TCP_OFFLOAD_ENABLE 985 int 986 t4_mgmt_tx(struct adapter *sc, mblk_t *m) 987 { 988 return (t4_wrq_tx(sc, &sc->sge.mgmtq, m)); 989 } 990 991 /* 992 * Doesn't fail. Holds on to work requests it can't send right away. 993 */ 994 int 995 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m0) 996 { 997 struct sge_eq *eq = &wrq->eq; 998 struct mblk_pair *wr_list = &wrq->wr_list; 999 int can_reclaim; 1000 caddr_t dst; 1001 mblk_t *wr, *next; 1002 1003 TXQ_LOCK_ASSERT_OWNED(wrq); 1004 #ifdef TCP_OFFLOAD_ENABLE 1005 ASSERT((eq->flags & EQ_TYPEMASK) == EQ_OFLD || 1006 (eq->flags & EQ_TYPEMASK) == EQ_CTRL); 1007 #else 1008 ASSERT((eq->flags & EQ_TYPEMASK) == EQ_CTRL); 1009 #endif 1010 1011 if (m0 != NULL) { 1012 if (wr_list->head != NULL) 1013 wr_list->tail->b_next = m0; 1014 else 1015 wr_list->head = m0; 1016 while (m0->b_next) 1017 m0 = m0->b_next; 1018 wr_list->tail = m0; 1019 } 1020 1021 can_reclaim = reclaimable(eq); 1022 eq->cidx += can_reclaim; 1023 eq->avail += can_reclaim; 1024 if (eq->cidx >= eq->cap) 1025 eq->cidx -= eq->cap; 1026 1027 for (wr = wr_list->head; wr; wr = next) { 1028 int ndesc, len = 0; 1029 mblk_t *m; 1030 1031 next = wr->b_next; 1032 wr->b_next = NULL; 1033 1034 for (m = wr; m; m = m->b_cont) 1035 len += MBLKL(m); 1036 1037 ASSERT(len > 0 && (len & 0x7) == 0); 1038 ASSERT(len <= SGE_MAX_WR_LEN); 1039 1040 ndesc = howmany(len, EQ_ESIZE); 1041 if (eq->avail < ndesc) { 1042 wr->b_next = next; 1043 wrq->no_desc++; 1044 break; 1045 } 1046 1047 dst = (void *)&eq->desc[eq->pidx]; 1048 for (m = wr; m; m = m->b_cont) 1049 copy_to_txd(eq, (void *)m->b_rptr, &dst, MBLKL(m)); 1050 1051 eq->pidx += ndesc; 1052 eq->avail -= ndesc; 1053 if (eq->pidx >= eq->cap) 1054 eq->pidx -= eq->cap; 1055 1056 eq->pending += ndesc; 1057 if (eq->pending > 16) 1058 ring_tx_db(sc, eq); 1059 1060 wrq->tx_wrs++; 1061 freemsg(wr); 1062 1063 if (eq->avail < 8) { 1064 can_reclaim = reclaimable(eq); 1065 eq->cidx += can_reclaim; 1066 eq->avail += can_reclaim; 1067 if (eq->cidx >= eq->cap) 1068 eq->cidx -= eq->cap; 1069 } 1070 } 1071 1072 if (eq->pending != 0) 1073 ring_tx_db(sc, eq); 1074 1075 if (wr == NULL) 1076 wr_list->head = wr_list->tail = NULL; 1077 else { 1078 wr_list->head = wr; 1079 1080 ASSERT(wr_list->tail->b_next == NULL); 1081 } 1082 1083 return (0); 1084 } 1085 #endif 1086 1087 /* Per-packet header in a coalesced tx WR, before the SGL starts (in flits) */ 1088 #define TXPKTS_PKT_HDR ((\ 1089 sizeof (struct ulp_txpkt) + \ 1090 sizeof (struct ulptx_idata) + \ 1091 sizeof (struct cpl_tx_pkt_core)) / 8) 1092 1093 /* Header of a coalesced tx WR, before SGL of first packet (in flits) */ 1094 #define TXPKTS_WR_HDR (\ 1095 sizeof (struct fw_eth_tx_pkts_wr) / 8 + \ 1096 TXPKTS_PKT_HDR) 1097 1098 /* Header of a tx WR, before SGL of first packet (in flits) */ 1099 #define TXPKT_WR_HDR ((\ 1100 sizeof (struct fw_eth_tx_pkt_wr) + \ 1101 sizeof (struct cpl_tx_pkt_core)) / 8) 1102 1103 /* Header of a tx LSO WR, before SGL of first packet (in flits) */ 1104 #define TXPKT_LSO_WR_HDR ((\ 1105 sizeof (struct fw_eth_tx_pkt_wr) + \ 1106 sizeof(struct cpl_tx_pkt_lso_core) + \ 1107 sizeof (struct cpl_tx_pkt_core)) / 8) 1108 1109 mblk_t * 1110 t4_eth_tx(void *arg, mblk_t *frame) 1111 { 1112 struct sge_txq *txq = (struct sge_txq *) arg; 1113 struct port_info *pi = txq->port; 1114 struct adapter *sc = pi->adapter; 1115 struct sge_eq *eq = &txq->eq; 1116 mblk_t *next_frame; 1117 int rc, coalescing; 1118 struct txpkts txpkts; 1119 struct txinfo txinfo; 1120 1121 txpkts.npkt = 0; /* indicates there's nothing in txpkts */ 1122 coalescing = 0; 1123 1124 TXQ_LOCK(txq); 1125 if (eq->avail < 8) 1126 (void) reclaim_tx_descs(txq, 8); 1127 for (; frame; frame = next_frame) { 1128 1129 if (eq->avail < 8) 1130 break; 1131 1132 next_frame = frame->b_next; 1133 frame->b_next = NULL; 1134 1135 if (next_frame != NULL) 1136 coalescing = 1; 1137 1138 rc = get_frame_txinfo(txq, &frame, &txinfo, coalescing); 1139 if (rc != 0) { 1140 if (rc == ENOMEM) { 1141 1142 /* Short of resources, suspend tx */ 1143 1144 frame->b_next = next_frame; 1145 break; 1146 } 1147 1148 /* 1149 * Unrecoverable error for this frame, throw it 1150 * away and move on to the next. 1151 */ 1152 1153 freemsg(frame); 1154 continue; 1155 } 1156 1157 if (coalescing != 0 && 1158 add_to_txpkts(txq, &txpkts, frame, &txinfo) == 0) { 1159 1160 /* Successfully absorbed into txpkts */ 1161 1162 write_ulp_cpl_sgl(pi, txq, &txpkts, &txinfo); 1163 goto doorbell; 1164 } 1165 1166 /* 1167 * We weren't coalescing to begin with, or current frame could 1168 * not be coalesced (add_to_txpkts flushes txpkts if a frame 1169 * given to it can't be coalesced). Either way there should be 1170 * nothing in txpkts. 1171 */ 1172 ASSERT(txpkts.npkt == 0); 1173 1174 /* We're sending out individual frames now */ 1175 coalescing = 0; 1176 1177 if (eq->avail < 8) 1178 (void) reclaim_tx_descs(txq, 8); 1179 rc = write_txpkt_wr(pi, txq, frame, &txinfo); 1180 if (rc != 0) { 1181 1182 /* Short of hardware descriptors, suspend tx */ 1183 1184 /* 1185 * This is an unlikely but expensive failure. We've 1186 * done all the hard work (DMA bindings etc.) and now we 1187 * can't send out the frame. What's worse, we have to 1188 * spend even more time freeing up everything in txinfo. 1189 */ 1190 txq->qfull++; 1191 free_txinfo_resources(txq, &txinfo); 1192 1193 frame->b_next = next_frame; 1194 break; 1195 } 1196 1197 doorbell: 1198 /* Fewer and fewer doorbells as the queue fills up */ 1199 if (eq->pending >= (1 << (fls(eq->qsize - eq->avail) / 2))) { 1200 txq->txbytes += txinfo.len; 1201 txq->txpkts++; 1202 ring_tx_db(sc, eq); 1203 } 1204 (void) reclaim_tx_descs(txq, 32); 1205 } 1206 1207 if (txpkts.npkt > 0) 1208 write_txpkts_wr(txq, &txpkts); 1209 1210 /* 1211 * frame not NULL means there was an error but we haven't thrown it 1212 * away. This can happen when we're short of tx descriptors (qfull) or 1213 * maybe even DMA handles (dma_hdl_failed). Either way, a credit flush 1214 * and reclaim will get things going again. 1215 * 1216 * If eq->avail is already 0 we know a credit flush was requested in the 1217 * WR that reduced it to 0 so we don't need another flush (we don't have 1218 * any descriptor for a flush WR anyway, duh). 1219 */ 1220 if (frame && eq->avail > 0) 1221 write_txqflush_wr(txq); 1222 1223 if (eq->pending != 0) 1224 ring_tx_db(sc, eq); 1225 1226 (void) reclaim_tx_descs(txq, eq->qsize); 1227 TXQ_UNLOCK(txq); 1228 1229 return (frame); 1230 } 1231 1232 static inline void 1233 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int8_t pktc_idx, 1234 int qsize, uint8_t esize) 1235 { 1236 ASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS); 1237 ASSERT(pktc_idx < SGE_NCOUNTERS); /* -ve is ok, means don't use */ 1238 1239 iq->flags = 0; 1240 iq->adapter = sc; 1241 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 1242 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 1243 if (pktc_idx >= 0) { 1244 iq->intr_params |= F_QINTR_CNT_EN; 1245 iq->intr_pktc_idx = pktc_idx; 1246 } 1247 iq->qsize = roundup(qsize, 16); /* See FW_IQ_CMD/iqsize */ 1248 iq->esize = max(esize, 16); /* See FW_IQ_CMD/iqesize */ 1249 } 1250 1251 static inline void 1252 init_fl(struct sge_fl *fl, uint16_t qsize) 1253 { 1254 1255 fl->qsize = qsize; 1256 } 1257 1258 static inline void 1259 init_eq(struct adapter *sc, struct sge_eq *eq, uint16_t eqtype, uint16_t qsize, 1260 uint8_t tx_chan, uint16_t iqid) 1261 { 1262 struct sge *s = &sc->sge; 1263 uint32_t r; 1264 1265 ASSERT(tx_chan < NCHAN); 1266 ASSERT(eqtype <= EQ_TYPEMASK); 1267 1268 if (is_t5(sc->params.chip)) { 1269 r = t4_read_reg(sc, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 1270 r >>= S_QUEUESPERPAGEPF0 + 1271 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf; 1272 s->s_qpp = r & M_QUEUESPERPAGEPF0; 1273 } 1274 1275 eq->flags = eqtype & EQ_TYPEMASK; 1276 eq->tx_chan = tx_chan; 1277 eq->iqid = iqid; 1278 eq->qsize = qsize; 1279 } 1280 1281 /* 1282 * Allocates the ring for an ingress queue and an optional freelist. If the 1283 * freelist is specified it will be allocated and then associated with the 1284 * ingress queue. 1285 * 1286 * Returns errno on failure. Resources allocated up to that point may still be 1287 * allocated. Caller is responsible for cleanup in case this function fails. 1288 * 1289 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then 1290 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies 1291 * the index of the queue to which its interrupts will be forwarded. 1292 */ 1293 static int 1294 alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl, 1295 int intr_idx, int cong) 1296 { 1297 int rc, i, cntxt_id; 1298 size_t len; 1299 struct fw_iq_cmd c; 1300 struct adapter *sc = iq->adapter; 1301 uint32_t v = 0; 1302 1303 len = iq->qsize * iq->esize; 1304 rc = alloc_desc_ring(sc, len, DDI_DMA_READ, &iq->dhdl, &iq->ahdl, 1305 &iq->ba, (caddr_t *)&iq->desc); 1306 if (rc != 0) 1307 return (rc); 1308 1309 bzero(&c, sizeof (c)); 1310 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 1311 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 1312 V_FW_IQ_CMD_VFN(0)); 1313 1314 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 1315 FW_LEN16(c)); 1316 1317 /* Special handling for firmware event queue */ 1318 if (iq == &sc->sge.fwq) 1319 v |= F_FW_IQ_CMD_IQASYNCH; 1320 1321 if (iq->flags & IQ_INTR) 1322 ASSERT(intr_idx < sc->intr_count); 1323 else 1324 v |= F_FW_IQ_CMD_IQANDST; 1325 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 1326 1327 c.type_to_iqandstindex = cpu_to_be32(v | 1328 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 1329 V_FW_IQ_CMD_VIID(pi->viid) | 1330 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 1331 c.iqdroprss_to_iqesize = cpu_to_be16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 1332 F_FW_IQ_CMD_IQGTSMODE | 1333 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 1334 V_FW_IQ_CMD_IQESIZE(ilog2(iq->esize) - 4)); 1335 c.iqsize = cpu_to_be16(iq->qsize); 1336 c.iqaddr = cpu_to_be64(iq->ba); 1337 if (cong >= 0) 1338 c.iqns_to_fl0congen = BE_32(F_FW_IQ_CMD_IQFLINTCONGEN); 1339 1340 if (fl != NULL) { 1341 unsigned int chip_ver = CHELSIO_CHIP_VERSION(sc->params.chip); 1342 1343 mutex_init(&fl->lock, NULL, MUTEX_DRIVER, 1344 DDI_INTR_PRI(sc->intr_pri)); 1345 fl->flags |= FL_MTX; 1346 1347 len = fl->qsize * RX_FL_ESIZE; 1348 rc = alloc_desc_ring(sc, len, DDI_DMA_WRITE, &fl->dhdl, 1349 &fl->ahdl, &fl->ba, (caddr_t *)&fl->desc); 1350 if (rc != 0) 1351 return (rc); 1352 1353 /* Allocate space for one software descriptor per buffer. */ 1354 fl->cap = (fl->qsize - sc->sge.stat_len / RX_FL_ESIZE) * 8; 1355 fl->sdesc = kmem_zalloc(sizeof (struct fl_sdesc) * fl->cap, 1356 KM_SLEEP); 1357 fl->needed = fl->cap; 1358 fl->lowat = roundup(sc->sge.fl_starve_threshold, 8); 1359 1360 c.iqns_to_fl0congen |= 1361 cpu_to_be32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 1362 F_FW_IQ_CMD_FL0PACKEN | F_FW_IQ_CMD_FL0PADEN); 1363 if (cong >= 0) { 1364 c.iqns_to_fl0congen |= 1365 BE_32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 1366 F_FW_IQ_CMD_FL0CONGCIF | 1367 F_FW_IQ_CMD_FL0CONGEN); 1368 } 1369 1370 /* In T6, for egress queue type FL there is internal overhead 1371 * of 16B for header going into FLM module. Hence the maximum 1372 * allowed burst size is 448 bytes. For T4/T5, the hardware 1373 * doesn't coalesce fetch requests if more than 64 bytes of 1374 * Free List pointers are provided, so we use a 128-byte Fetch 1375 * Burst Minimum there (T6 implements coalescing so we can use 1376 * the smaller 64-byte value there). 1377 */ 1378 1379 c.fl0dcaen_to_fl0cidxfthresh = 1380 cpu_to_be16(V_FW_IQ_CMD_FL0FBMIN(chip_ver <= CHELSIO_T5 1381 ? X_FETCHBURSTMIN_128B 1382 : X_FETCHBURSTMIN_64B) | 1383 V_FW_IQ_CMD_FL0FBMAX(chip_ver <= CHELSIO_T5 1384 ? X_FETCHBURSTMAX_512B 1385 : X_FETCHBURSTMAX_256B)); 1386 c.fl0size = cpu_to_be16(fl->qsize); 1387 c.fl0addr = cpu_to_be64(fl->ba); 1388 } 1389 1390 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof (c), &c); 1391 if (rc != 0) { 1392 cxgb_printf(sc->dip, CE_WARN, 1393 "failed to create ingress queue: %d", rc); 1394 return (rc); 1395 } 1396 1397 iq->cdesc = iq->desc; 1398 iq->cidx = 0; 1399 iq->gen = 1; 1400 iq->intr_next = iq->intr_params; 1401 iq->adapter = sc; 1402 iq->cntxt_id = be16_to_cpu(c.iqid); 1403 iq->abs_id = be16_to_cpu(c.physiqid); 1404 iq->flags |= IQ_ALLOCATED; 1405 mutex_init(&iq->lock, NULL, 1406 MUTEX_DRIVER, DDI_INTR_PRI(DDI_INTR_PRI(sc->intr_pri))); 1407 iq->polling = 0; 1408 1409 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 1410 if (cntxt_id >= sc->sge.niq) { 1411 panic("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 1412 cntxt_id, sc->sge.niq - 1); 1413 } 1414 sc->sge.iqmap[cntxt_id] = iq; 1415 1416 if (fl != NULL) { 1417 fl->cntxt_id = be16_to_cpu(c.fl0id); 1418 fl->pidx = fl->cidx = 0; 1419 fl->copy_threshold = rx_copy_threshold; 1420 1421 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 1422 if (cntxt_id >= sc->sge.neq) { 1423 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 1424 __func__, cntxt_id, sc->sge.neq - 1); 1425 } 1426 sc->sge.eqmap[cntxt_id] = (void *)fl; 1427 1428 FL_LOCK(fl); 1429 (void) refill_fl(sc, fl, fl->lowat); 1430 FL_UNLOCK(fl); 1431 1432 iq->flags |= IQ_HAS_FL; 1433 } 1434 1435 if (is_t5(sc->params.chip) && cong >= 0) { 1436 uint32_t param, val; 1437 1438 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 1439 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 1440 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 1441 if (cong == 0) 1442 val = 1 << 19; 1443 else { 1444 val = 2 << 19; 1445 for (i = 0; i < 4; i++) { 1446 if (cong & (1 << i)) 1447 val |= 1 << (i << 2); 1448 } 1449 } 1450 1451 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 1452 if (rc != 0) { 1453 /* report error but carry on */ 1454 cxgb_printf(sc->dip, CE_WARN, 1455 "failed to set congestion manager context for " 1456 "ingress queue %d: %d", iq->cntxt_id, rc); 1457 } 1458 } 1459 1460 /* Enable IQ interrupts */ 1461 iq->state = IQS_IDLE; 1462 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) | 1463 V_INGRESSQID(iq->cntxt_id)); 1464 1465 return (0); 1466 } 1467 1468 static int 1469 free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl) 1470 { 1471 int rc; 1472 struct adapter *sc = iq->adapter; 1473 dev_info_t *dip; 1474 1475 dip = pi ? pi->dip : sc->dip; 1476 1477 if (iq != NULL) { 1478 if (iq->flags & IQ_ALLOCATED) { 1479 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 1480 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 1481 fl ? fl->cntxt_id : 0xffff, 0xffff); 1482 if (rc != 0) { 1483 cxgb_printf(dip, CE_WARN, 1484 "failed to free queue %p: %d", iq, rc); 1485 return (rc); 1486 } 1487 mutex_destroy(&iq->lock); 1488 iq->flags &= ~IQ_ALLOCATED; 1489 } 1490 1491 if (iq->desc != NULL) { 1492 (void) free_desc_ring(&iq->dhdl, &iq->ahdl); 1493 iq->desc = NULL; 1494 } 1495 1496 bzero(iq, sizeof (*iq)); 1497 } 1498 1499 if (fl != NULL) { 1500 if (fl->sdesc != NULL) { 1501 FL_LOCK(fl); 1502 free_fl_bufs(fl); 1503 FL_UNLOCK(fl); 1504 1505 kmem_free(fl->sdesc, sizeof (struct fl_sdesc) * 1506 fl->cap); 1507 fl->sdesc = NULL; 1508 } 1509 1510 if (fl->desc != NULL) { 1511 (void) free_desc_ring(&fl->dhdl, &fl->ahdl); 1512 fl->desc = NULL; 1513 } 1514 1515 if (fl->flags & FL_MTX) { 1516 mutex_destroy(&fl->lock); 1517 fl->flags &= ~FL_MTX; 1518 } 1519 1520 bzero(fl, sizeof (struct sge_fl)); 1521 } 1522 1523 return (0); 1524 } 1525 1526 static int 1527 alloc_fwq(struct adapter *sc) 1528 { 1529 int rc, intr_idx; 1530 struct sge_iq *fwq = &sc->sge.fwq; 1531 1532 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, FW_IQ_ESIZE); 1533 fwq->flags |= IQ_INTR; /* always */ 1534 intr_idx = sc->intr_count > 1 ? 1 : 0; 1535 rc = alloc_iq_fl(sc->port[0], fwq, NULL, intr_idx, -1); 1536 if (rc != 0) { 1537 cxgb_printf(sc->dip, CE_WARN, 1538 "failed to create firmware event queue: %d.", rc); 1539 return (rc); 1540 } 1541 1542 return (0); 1543 } 1544 1545 static int 1546 free_fwq(struct adapter *sc) 1547 { 1548 1549 return (free_iq_fl(NULL, &sc->sge.fwq, NULL)); 1550 } 1551 1552 #ifdef TCP_OFFLOAD_ENABLE 1553 static int 1554 alloc_mgmtq(struct adapter *sc) 1555 { 1556 int rc; 1557 struct sge_wrq *mgmtq = &sc->sge.mgmtq; 1558 1559 init_eq(sc, &mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan, 1560 sc->sge.fwq.cntxt_id); 1561 rc = alloc_wrq(sc, NULL, mgmtq, 0); 1562 if (rc != 0) { 1563 cxgb_printf(sc->dip, CE_WARN, 1564 "failed to create management queue: %d\n", rc); 1565 return (rc); 1566 } 1567 1568 return (0); 1569 } 1570 #endif 1571 1572 static int 1573 alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int i) 1574 { 1575 int rc; 1576 1577 rxq->port = pi; 1578 rc = alloc_iq_fl(pi, &rxq->iq, &rxq->fl, intr_idx, 1 << pi->tx_chan); 1579 if (rc != 0) 1580 return (rc); 1581 1582 rxq->ksp = setup_rxq_kstats(pi, rxq, i); 1583 1584 return (rc); 1585 } 1586 1587 static int 1588 free_rxq(struct port_info *pi, struct sge_rxq *rxq) 1589 { 1590 int rc; 1591 1592 if (rxq->ksp != NULL) { 1593 kstat_delete(rxq->ksp); 1594 rxq->ksp = NULL; 1595 } 1596 1597 rc = free_iq_fl(pi, &rxq->iq, &rxq->fl); 1598 if (rc == 0) 1599 bzero(&rxq->fl, sizeof (*rxq) - offsetof(struct sge_rxq, fl)); 1600 1601 return (rc); 1602 } 1603 1604 #ifdef TCP_OFFLOAD_ENABLE 1605 static int 1606 alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq, 1607 int intr_idx) 1608 { 1609 int rc; 1610 1611 rc = alloc_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 1612 1 << pi->tx_chan); 1613 if (rc != 0) 1614 return (rc); 1615 1616 return (rc); 1617 } 1618 1619 static int 1620 free_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq) 1621 { 1622 int rc; 1623 1624 rc = free_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl); 1625 if (rc == 0) 1626 bzero(&ofld_rxq->fl, sizeof (*ofld_rxq) - 1627 offsetof(struct sge_ofld_rxq, fl)); 1628 1629 return (rc); 1630 } 1631 #endif 1632 1633 static int 1634 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 1635 { 1636 int rc, cntxt_id; 1637 struct fw_eq_ctrl_cmd c; 1638 1639 bzero(&c, sizeof (c)); 1640 1641 c.op_to_vfn = BE_32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 1642 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 1643 V_FW_EQ_CTRL_CMD_VFN(0)); 1644 c.alloc_to_len16 = BE_32(F_FW_EQ_CTRL_CMD_ALLOC | 1645 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 1646 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); /* TODO */ 1647 c.physeqid_pkd = BE_32(0); 1648 c.fetchszm_to_iqid = 1649 BE_32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 1650 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 1651 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 1652 c.dcaen_to_eqsize = 1653 BE_32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 1654 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 1655 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 1656 V_FW_EQ_CTRL_CMD_EQSIZE(eq->qsize)); 1657 c.eqaddr = BE_64(eq->ba); 1658 1659 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof (c), &c); 1660 if (rc != 0) { 1661 cxgb_printf(sc->dip, CE_WARN, 1662 "failed to create control queue %d: %d", eq->tx_chan, rc); 1663 return (rc); 1664 } 1665 eq->flags |= EQ_ALLOCATED; 1666 1667 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(BE_32(c.cmpliqid_eqid)); 1668 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 1669 if (cntxt_id >= sc->sge.neq) 1670 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 1671 cntxt_id, sc->sge.neq - 1); 1672 sc->sge.eqmap[cntxt_id] = eq; 1673 1674 return (rc); 1675 } 1676 1677 static int 1678 eth_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 1679 { 1680 int rc, cntxt_id; 1681 struct fw_eq_eth_cmd c; 1682 1683 bzero(&c, sizeof (c)); 1684 1685 c.op_to_vfn = BE_32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 1686 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 1687 V_FW_EQ_ETH_CMD_VFN(0)); 1688 c.alloc_to_len16 = BE_32(F_FW_EQ_ETH_CMD_ALLOC | 1689 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 1690 c.autoequiqe_to_viid = BE_32(V_FW_EQ_ETH_CMD_VIID(pi->viid)); 1691 c.fetchszm_to_iqid = 1692 BE_32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 1693 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 1694 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 1695 c.dcaen_to_eqsize = BE_32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 1696 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 1697 V_FW_EQ_ETH_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 1698 V_FW_EQ_ETH_CMD_EQSIZE(eq->qsize)); 1699 c.eqaddr = BE_64(eq->ba); 1700 1701 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof (c), &c); 1702 if (rc != 0) { 1703 cxgb_printf(pi->dip, CE_WARN, 1704 "failed to create Ethernet egress queue: %d", rc); 1705 return (rc); 1706 } 1707 eq->flags |= EQ_ALLOCATED; 1708 1709 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(BE_32(c.eqid_pkd)); 1710 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 1711 if (cntxt_id >= sc->sge.neq) 1712 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 1713 cntxt_id, sc->sge.neq - 1); 1714 sc->sge.eqmap[cntxt_id] = eq; 1715 1716 return (rc); 1717 } 1718 1719 #ifdef TCP_OFFLOAD_ENABLE 1720 static int 1721 ofld_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 1722 { 1723 int rc, cntxt_id; 1724 struct fw_eq_ofld_cmd c; 1725 1726 bzero(&c, sizeof (c)); 1727 1728 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 1729 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 1730 V_FW_EQ_OFLD_CMD_VFN(0)); 1731 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 1732 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 1733 c.fetchszm_to_iqid = 1734 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 1735 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 1736 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 1737 c.dcaen_to_eqsize = 1738 BE_32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 1739 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 1740 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 1741 V_FW_EQ_OFLD_CMD_EQSIZE(eq->qsize)); 1742 c.eqaddr = BE_64(eq->ba); 1743 1744 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof (c), &c); 1745 if (rc != 0) { 1746 cxgb_printf(pi->dip, CE_WARN, 1747 "failed to create egress queue for TCP offload: %d", rc); 1748 return (rc); 1749 } 1750 eq->flags |= EQ_ALLOCATED; 1751 1752 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(BE_32(c.eqid_pkd)); 1753 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 1754 if (cntxt_id >= sc->sge.neq) 1755 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 1756 cntxt_id, sc->sge.neq - 1); 1757 sc->sge.eqmap[cntxt_id] = eq; 1758 1759 return (rc); 1760 } 1761 #endif 1762 1763 static int 1764 alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 1765 { 1766 int rc; 1767 size_t len; 1768 1769 mutex_init(&eq->lock, NULL, MUTEX_DRIVER, DDI_INTR_PRI(sc->intr_pri)); 1770 eq->flags |= EQ_MTX; 1771 1772 len = eq->qsize * EQ_ESIZE; 1773 rc = alloc_desc_ring(sc, len, DDI_DMA_WRITE, &eq->desc_dhdl, 1774 &eq->desc_ahdl, &eq->ba, (caddr_t *)&eq->desc); 1775 if (rc != 0) 1776 return (rc); 1777 1778 eq->cap = eq->qsize - sc->sge.stat_len / EQ_ESIZE; 1779 eq->spg = (void *)&eq->desc[eq->cap]; 1780 eq->avail = eq->cap - 1; /* one less to avoid cidx = pidx */ 1781 eq->pidx = eq->cidx = 0; 1782 eq->doorbells = sc->doorbells; 1783 1784 switch (eq->flags & EQ_TYPEMASK) { 1785 case EQ_CTRL: 1786 rc = ctrl_eq_alloc(sc, eq); 1787 break; 1788 1789 case EQ_ETH: 1790 rc = eth_eq_alloc(sc, pi, eq); 1791 break; 1792 1793 #ifdef TCP_OFFLOAD_ENABLE 1794 case EQ_OFLD: 1795 rc = ofld_eq_alloc(sc, pi, eq); 1796 break; 1797 #endif 1798 1799 default: 1800 panic("%s: invalid eq type %d.", __func__, 1801 eq->flags & EQ_TYPEMASK); 1802 } 1803 1804 if (eq->doorbells & 1805 (DOORBELL_UDB | DOORBELL_UDBWC | DOORBELL_WCWR)) { 1806 uint32_t s_qpp = sc->sge.s_qpp; 1807 uint32_t mask = (1 << s_qpp) - 1; 1808 volatile uint8_t *udb; 1809 1810 udb = (volatile uint8_t *)sc->reg1p + UDBS_DB_OFFSET; 1811 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 1812 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 1813 if (eq->udb_qid > PAGE_SIZE / UDBS_SEG_SIZE) 1814 eq->doorbells &= ~DOORBELL_WCWR; 1815 else { 1816 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 1817 eq->udb_qid = 0; 1818 } 1819 eq->udb = (volatile void *)udb; 1820 } 1821 1822 if (rc != 0) { 1823 cxgb_printf(sc->dip, CE_WARN, 1824 "failed to allocate egress queue(%d): %d", 1825 eq->flags & EQ_TYPEMASK, rc); 1826 } 1827 1828 return (rc); 1829 } 1830 1831 static int 1832 free_eq(struct adapter *sc, struct sge_eq *eq) 1833 { 1834 int rc; 1835 1836 if (eq->flags & EQ_ALLOCATED) { 1837 switch (eq->flags & EQ_TYPEMASK) { 1838 case EQ_CTRL: 1839 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 1840 eq->cntxt_id); 1841 break; 1842 1843 case EQ_ETH: 1844 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 1845 eq->cntxt_id); 1846 break; 1847 1848 #ifdef TCP_OFFLOAD_ENABLE 1849 case EQ_OFLD: 1850 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 1851 eq->cntxt_id); 1852 break; 1853 #endif 1854 1855 default: 1856 panic("%s: invalid eq type %d.", __func__, 1857 eq->flags & EQ_TYPEMASK); 1858 } 1859 if (rc != 0) { 1860 cxgb_printf(sc->dip, CE_WARN, 1861 "failed to free egress queue (%d): %d", 1862 eq->flags & EQ_TYPEMASK, rc); 1863 return (rc); 1864 } 1865 eq->flags &= ~EQ_ALLOCATED; 1866 } 1867 1868 if (eq->desc != NULL) { 1869 (void) free_desc_ring(&eq->desc_dhdl, &eq->desc_ahdl); 1870 eq->desc = NULL; 1871 } 1872 1873 if (eq->flags & EQ_MTX) 1874 mutex_destroy(&eq->lock); 1875 1876 bzero(eq, sizeof (*eq)); 1877 return (0); 1878 } 1879 1880 #ifdef TCP_OFFLOAD_ENABLE 1881 /* ARGSUSED */ 1882 static int 1883 alloc_wrq(struct adapter *sc, struct port_info *pi, struct sge_wrq *wrq, 1884 int idx) 1885 { 1886 int rc; 1887 1888 rc = alloc_eq(sc, pi, &wrq->eq); 1889 if (rc != 0) 1890 return (rc); 1891 1892 wrq->adapter = sc; 1893 wrq->wr_list.head = NULL; 1894 wrq->wr_list.tail = NULL; 1895 1896 /* 1897 * TODO: use idx to figure out what kind of wrq this is and install 1898 * useful kstats for it. 1899 */ 1900 1901 return (rc); 1902 } 1903 1904 static int 1905 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 1906 { 1907 int rc; 1908 1909 rc = free_eq(sc, &wrq->eq); 1910 if (rc != 0) 1911 return (rc); 1912 1913 bzero(wrq, sizeof (*wrq)); 1914 return (0); 1915 } 1916 #endif 1917 1918 static int 1919 alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx) 1920 { 1921 int rc, i; 1922 struct adapter *sc = pi->adapter; 1923 struct sge_eq *eq = &txq->eq; 1924 1925 rc = alloc_eq(sc, pi, eq); 1926 if (rc != 0) 1927 return (rc); 1928 1929 txq->port = pi; 1930 txq->sdesc = kmem_zalloc(sizeof (struct tx_sdesc) * eq->cap, KM_SLEEP); 1931 txq->txb_size = eq->qsize * tx_copy_threshold; 1932 rc = alloc_tx_copybuffer(sc, txq->txb_size, &txq->txb_dhdl, 1933 &txq->txb_ahdl, &txq->txb_ba, &txq->txb_va); 1934 if (rc == 0) 1935 txq->txb_avail = txq->txb_size; 1936 else 1937 txq->txb_avail = txq->txb_size = 0; 1938 1939 /* 1940 * TODO: is this too low? Worst case would need around 4 times qsize 1941 * (all tx descriptors filled to the brim with SGLs, with each entry in 1942 * the SGL coming from a distinct DMA handle). Increase tx_dhdl_total 1943 * if you see too many dma_hdl_failed. 1944 */ 1945 txq->tx_dhdl_total = eq->qsize * 2; 1946 txq->tx_dhdl = kmem_zalloc(sizeof (ddi_dma_handle_t) * 1947 txq->tx_dhdl_total, KM_SLEEP); 1948 for (i = 0; i < txq->tx_dhdl_total; i++) { 1949 rc = ddi_dma_alloc_handle(sc->dip, &sc->sge.dma_attr_tx, 1950 DDI_DMA_SLEEP, 0, &txq->tx_dhdl[i]); 1951 if (rc != DDI_SUCCESS) { 1952 cxgb_printf(sc->dip, CE_WARN, 1953 "%s: failed to allocate DMA handle (%d)", 1954 __func__, rc); 1955 return (rc == DDI_DMA_NORESOURCES ? ENOMEM : EINVAL); 1956 } 1957 txq->tx_dhdl_avail++; 1958 } 1959 1960 txq->ksp = setup_txq_kstats(pi, txq, idx); 1961 1962 return (rc); 1963 } 1964 1965 static int 1966 free_txq(struct port_info *pi, struct sge_txq *txq) 1967 { 1968 int i; 1969 struct adapter *sc = pi->adapter; 1970 struct sge_eq *eq = &txq->eq; 1971 1972 if (txq->ksp != NULL) { 1973 kstat_delete(txq->ksp); 1974 txq->ksp = NULL; 1975 } 1976 1977 if (txq->txb_va != NULL) { 1978 (void) free_desc_ring(&txq->txb_dhdl, &txq->txb_ahdl); 1979 txq->txb_va = NULL; 1980 } 1981 1982 if (txq->sdesc != NULL) { 1983 struct tx_sdesc *sd; 1984 ddi_dma_handle_t hdl; 1985 1986 TXQ_LOCK(txq); 1987 while (eq->cidx != eq->pidx) { 1988 sd = &txq->sdesc[eq->cidx]; 1989 1990 for (i = sd->hdls_used; i; i--) { 1991 hdl = txq->tx_dhdl[txq->tx_dhdl_cidx]; 1992 (void) ddi_dma_unbind_handle(hdl); 1993 if (++txq->tx_dhdl_cidx == txq->tx_dhdl_total) 1994 txq->tx_dhdl_cidx = 0; 1995 } 1996 1997 ASSERT(sd->m); 1998 freemsgchain(sd->m); 1999 2000 eq->cidx += sd->desc_used; 2001 if (eq->cidx >= eq->cap) 2002 eq->cidx -= eq->cap; 2003 2004 txq->txb_avail += txq->txb_used; 2005 } 2006 ASSERT(txq->tx_dhdl_cidx == txq->tx_dhdl_pidx); 2007 ASSERT(txq->txb_avail == txq->txb_size); 2008 TXQ_UNLOCK(txq); 2009 2010 kmem_free(txq->sdesc, sizeof (struct tx_sdesc) * eq->cap); 2011 txq->sdesc = NULL; 2012 } 2013 2014 if (txq->tx_dhdl != NULL) { 2015 for (i = 0; i < txq->tx_dhdl_total; i++) { 2016 if (txq->tx_dhdl[i] != NULL) 2017 ddi_dma_free_handle(&txq->tx_dhdl[i]); 2018 } 2019 } 2020 2021 (void) free_eq(sc, &txq->eq); 2022 2023 bzero(txq, sizeof (*txq)); 2024 return (0); 2025 } 2026 2027 /* 2028 * Allocates a block of contiguous memory for DMA. Can be used to allocate 2029 * memory for descriptor rings or for tx/rx copy buffers. 2030 * 2031 * Caller does not have to clean up anything if this function fails, it cleans 2032 * up after itself. 2033 * 2034 * Caller provides the following: 2035 * len length of the block of memory to allocate. 2036 * flags DDI_DMA_* flags to use (CONSISTENT/STREAMING, READ/WRITE/RDWR) 2037 * acc_attr device access attributes for the allocation. 2038 * dma_attr DMA attributes for the allocation 2039 * 2040 * If the function is successful it fills up this information: 2041 * dma_hdl DMA handle for the allocated memory 2042 * acc_hdl access handle for the allocated memory 2043 * ba bus address of the allocated memory 2044 * va KVA of the allocated memory. 2045 */ 2046 static int 2047 alloc_dma_memory(struct adapter *sc, size_t len, int flags, 2048 ddi_device_acc_attr_t *acc_attr, ddi_dma_attr_t *dma_attr, 2049 ddi_dma_handle_t *dma_hdl, ddi_acc_handle_t *acc_hdl, 2050 uint64_t *pba, caddr_t *pva) 2051 { 2052 int rc; 2053 ddi_dma_handle_t dhdl; 2054 ddi_acc_handle_t ahdl; 2055 ddi_dma_cookie_t cookie; 2056 uint_t ccount; 2057 caddr_t va; 2058 size_t real_len; 2059 2060 *pva = NULL; 2061 2062 /* 2063 * DMA handle. 2064 */ 2065 rc = ddi_dma_alloc_handle(sc->dip, dma_attr, DDI_DMA_SLEEP, 0, &dhdl); 2066 if (rc != DDI_SUCCESS) { 2067 cxgb_printf(sc->dip, CE_WARN, 2068 "failed to allocate DMA handle: %d", rc); 2069 2070 return (rc == DDI_DMA_NORESOURCES ? ENOMEM : EINVAL); 2071 } 2072 2073 /* 2074 * Memory suitable for DMA. 2075 */ 2076 rc = ddi_dma_mem_alloc(dhdl, len, acc_attr, 2077 flags & DDI_DMA_CONSISTENT ? DDI_DMA_CONSISTENT : DDI_DMA_STREAMING, 2078 DDI_DMA_SLEEP, 0, &va, &real_len, &ahdl); 2079 if (rc != DDI_SUCCESS) { 2080 cxgb_printf(sc->dip, CE_WARN, 2081 "failed to allocate DMA memory: %d", rc); 2082 2083 ddi_dma_free_handle(&dhdl); 2084 return (ENOMEM); 2085 } 2086 2087 if (len != real_len) { 2088 cxgb_printf(sc->dip, CE_WARN, 2089 "%s: len (%u) != real_len (%u)\n", len, real_len); 2090 } 2091 2092 /* 2093 * DMA bindings. 2094 */ 2095 rc = ddi_dma_addr_bind_handle(dhdl, NULL, va, real_len, flags, NULL, 2096 NULL, &cookie, &ccount); 2097 if (rc != DDI_DMA_MAPPED) { 2098 cxgb_printf(sc->dip, CE_WARN, 2099 "failed to map DMA memory: %d", rc); 2100 2101 ddi_dma_mem_free(&ahdl); 2102 ddi_dma_free_handle(&dhdl); 2103 return (ENOMEM); 2104 } 2105 if (ccount != 1) { 2106 cxgb_printf(sc->dip, CE_WARN, 2107 "unusable DMA mapping (%d segments)", ccount); 2108 (void) free_desc_ring(&dhdl, &ahdl); 2109 } 2110 2111 bzero(va, real_len); 2112 *dma_hdl = dhdl; 2113 *acc_hdl = ahdl; 2114 *pba = cookie.dmac_laddress; 2115 *pva = va; 2116 2117 return (0); 2118 } 2119 2120 static int 2121 free_dma_memory(ddi_dma_handle_t *dhdl, ddi_acc_handle_t *ahdl) 2122 { 2123 (void) ddi_dma_unbind_handle(*dhdl); 2124 ddi_dma_mem_free(ahdl); 2125 ddi_dma_free_handle(dhdl); 2126 2127 return (0); 2128 } 2129 2130 static int 2131 alloc_desc_ring(struct adapter *sc, size_t len, int rw, 2132 ddi_dma_handle_t *dma_hdl, ddi_acc_handle_t *acc_hdl, 2133 uint64_t *pba, caddr_t *pva) 2134 { 2135 ddi_device_acc_attr_t *acc_attr = &sc->sge.acc_attr_desc; 2136 ddi_dma_attr_t *dma_attr = &sc->sge.dma_attr_desc; 2137 2138 return (alloc_dma_memory(sc, len, DDI_DMA_CONSISTENT | rw, acc_attr, 2139 dma_attr, dma_hdl, acc_hdl, pba, pva)); 2140 } 2141 2142 static int 2143 free_desc_ring(ddi_dma_handle_t *dhdl, ddi_acc_handle_t *ahdl) 2144 { 2145 return (free_dma_memory(dhdl, ahdl)); 2146 } 2147 2148 static int 2149 alloc_tx_copybuffer(struct adapter *sc, size_t len, 2150 ddi_dma_handle_t *dma_hdl, ddi_acc_handle_t *acc_hdl, 2151 uint64_t *pba, caddr_t *pva) 2152 { 2153 ddi_device_acc_attr_t *acc_attr = &sc->sge.acc_attr_tx; 2154 ddi_dma_attr_t *dma_attr = &sc->sge.dma_attr_desc; /* NOT dma_attr_tx */ 2155 2156 return (alloc_dma_memory(sc, len, DDI_DMA_STREAMING | DDI_DMA_WRITE, 2157 acc_attr, dma_attr, dma_hdl, acc_hdl, pba, pva)); 2158 } 2159 2160 static inline bool 2161 is_new_response(const struct sge_iq *iq, struct rsp_ctrl **ctrl) 2162 { 2163 (void) ddi_dma_sync(iq->dhdl, (uintptr_t)iq->cdesc - 2164 (uintptr_t)iq->desc, iq->esize, DDI_DMA_SYNC_FORKERNEL); 2165 2166 *ctrl = (void *)((uintptr_t)iq->cdesc + 2167 (iq->esize - sizeof (struct rsp_ctrl))); 2168 2169 return ((((*ctrl)->u.type_gen >> S_RSPD_GEN) == iq->gen)); 2170 } 2171 2172 static inline void 2173 iq_next(struct sge_iq *iq) 2174 { 2175 iq->cdesc = (void *) ((uintptr_t)iq->cdesc + iq->esize); 2176 if (++iq->cidx == iq->qsize - 1) { 2177 iq->cidx = 0; 2178 iq->gen ^= 1; 2179 iq->cdesc = iq->desc; 2180 } 2181 } 2182 2183 /* 2184 * Fill up the freelist by upto nbufs and maybe ring its doorbell. 2185 * 2186 * Returns non-zero to indicate that it should be added to the list of starving 2187 * freelists. 2188 */ 2189 static int 2190 refill_fl(struct adapter *sc, struct sge_fl *fl, int nbufs) 2191 { 2192 uint64_t *d = &fl->desc[fl->pidx]; 2193 struct fl_sdesc *sd = &fl->sdesc[fl->pidx]; 2194 2195 FL_LOCK_ASSERT_OWNED(fl); 2196 ASSERT(nbufs >= 0); 2197 2198 if (nbufs > fl->needed) 2199 nbufs = fl->needed; 2200 2201 while (nbufs--) { 2202 if (sd->rxb != NULL) { 2203 if (sd->rxb->ref_cnt == 1) { 2204 /* 2205 * Buffer is available for recycling. Two ways 2206 * this can happen: 2207 * 2208 * a) All the packets DMA'd into it last time 2209 * around were within the rx_copy_threshold 2210 * and no part of the buffer was ever passed 2211 * up (ref_cnt never went over 1). 2212 * 2213 * b) Packets DMA'd into the buffer were passed 2214 * up but have all been freed by the upper 2215 * layers by now (ref_cnt went over 1 but is 2216 * now back to 1). 2217 * 2218 * Either way the bus address in the descriptor 2219 * ring is already valid. 2220 */ 2221 ASSERT(*d == cpu_to_be64(sd->rxb->ba)); 2222 d++; 2223 goto recycled; 2224 } else { 2225 /* 2226 * Buffer still in use and we need a 2227 * replacement. But first release our reference 2228 * on the existing buffer. 2229 */ 2230 rxbuf_free(sd->rxb); 2231 } 2232 } 2233 2234 sd->rxb = rxbuf_alloc(sc->sge.rxbuf_cache, KM_NOSLEEP, 1); 2235 if (sd->rxb == NULL) 2236 break; 2237 *d++ = cpu_to_be64(sd->rxb->ba); 2238 2239 recycled: fl->pending++; 2240 sd++; 2241 fl->needed--; 2242 if (++fl->pidx == fl->cap) { 2243 fl->pidx = 0; 2244 sd = fl->sdesc; 2245 d = fl->desc; 2246 } 2247 } 2248 2249 if (fl->pending >= 8) 2250 ring_fl_db(sc, fl); 2251 2252 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 2253 } 2254 2255 #ifndef TAILQ_FOREACH_SAFE 2256 #define TAILQ_FOREACH_SAFE(var, head, field, tvar) \ 2257 for ((var) = TAILQ_FIRST((head)); \ 2258 (var) && ((tvar) = TAILQ_NEXT((var), field), 1); \ 2259 (var) = (tvar)) 2260 #endif 2261 2262 /* 2263 * Attempt to refill all starving freelists. 2264 */ 2265 static void 2266 refill_sfl(void *arg) 2267 { 2268 struct adapter *sc = arg; 2269 struct sge_fl *fl, *fl_temp; 2270 2271 mutex_enter(&sc->sfl_lock); 2272 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 2273 FL_LOCK(fl); 2274 (void) refill_fl(sc, fl, 64); 2275 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 2276 TAILQ_REMOVE(&sc->sfl, fl, link); 2277 fl->flags &= ~FL_STARVING; 2278 } 2279 FL_UNLOCK(fl); 2280 } 2281 2282 if (!TAILQ_EMPTY(&sc->sfl) != 0) 2283 sc->sfl_timer = timeout(refill_sfl, sc, drv_usectohz(100000)); 2284 mutex_exit(&sc->sfl_lock); 2285 } 2286 2287 static void 2288 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 2289 { 2290 mutex_enter(&sc->sfl_lock); 2291 FL_LOCK(fl); 2292 if ((fl->flags & FL_DOOMED) == 0) { 2293 if (TAILQ_EMPTY(&sc->sfl) != 0) { 2294 sc->sfl_timer = timeout(refill_sfl, sc, 2295 drv_usectohz(100000)); 2296 } 2297 fl->flags |= FL_STARVING; 2298 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 2299 } 2300 FL_UNLOCK(fl); 2301 mutex_exit(&sc->sfl_lock); 2302 } 2303 2304 static void 2305 free_fl_bufs(struct sge_fl *fl) 2306 { 2307 struct fl_sdesc *sd; 2308 unsigned int i; 2309 2310 FL_LOCK_ASSERT_OWNED(fl); 2311 2312 for (i = 0; i < fl->cap; i++) { 2313 sd = &fl->sdesc[i]; 2314 2315 if (sd->rxb != NULL) { 2316 rxbuf_free(sd->rxb); 2317 sd->rxb = NULL; 2318 } 2319 } 2320 } 2321 2322 /* 2323 * Note that fl->cidx and fl->offset are left unchanged in case of failure. 2324 */ 2325 static mblk_t * 2326 get_fl_payload(struct adapter *sc, struct sge_fl *fl, 2327 uint32_t len_newbuf, int *fl_bufs_used) 2328 { 2329 struct mblk_pair frame = {0}; 2330 struct rxbuf *rxb; 2331 mblk_t *m = NULL; 2332 uint_t nbuf = 0, len, copy, n; 2333 uint32_t cidx, offset; 2334 2335 /* 2336 * The SGE won't pack a new frame into the current buffer if the entire 2337 * payload doesn't fit in the remaining space. Move on to the next buf 2338 * in that case. 2339 */ 2340 if (fl->offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 2341 fl->offset = 0; 2342 if (++fl->cidx == fl->cap) 2343 fl->cidx = 0; 2344 nbuf++; 2345 } 2346 cidx = fl->cidx; 2347 offset = fl->offset; 2348 2349 len = G_RSPD_LEN(len_newbuf); /* pktshift + payload length */ 2350 copy = (len <= fl->copy_threshold); 2351 if (copy != 0) { 2352 frame.head = m = allocb(len, BPRI_HI); 2353 if (m == NULL) 2354 return (NULL); 2355 } 2356 2357 while (len) { 2358 rxb = fl->sdesc[cidx].rxb; 2359 n = min(len, rxb->buf_size - offset); 2360 2361 (void) ddi_dma_sync(rxb->dhdl, offset, n, 2362 DDI_DMA_SYNC_FORKERNEL); 2363 2364 if (copy != 0) 2365 bcopy(rxb->va + offset, m->b_wptr, n); 2366 else { 2367 m = desballoc((unsigned char *)rxb->va + offset, n, 2368 BPRI_HI, &rxb->freefunc); 2369 if (m == NULL) { 2370 freemsg(frame.head); 2371 return (NULL); 2372 } 2373 atomic_inc_uint(&rxb->ref_cnt); 2374 if (frame.head != NULL) 2375 frame.tail->b_cont = m; 2376 else 2377 frame.head = m; 2378 frame.tail = m; 2379 } 2380 m->b_wptr += n; 2381 len -= n; 2382 offset += roundup(n, sc->sge.fl_align); 2383 ASSERT(offset <= rxb->buf_size); 2384 if (offset == rxb->buf_size) { 2385 offset = 0; 2386 if (++cidx == fl->cap) 2387 cidx = 0; 2388 nbuf++; 2389 } 2390 } 2391 2392 fl->cidx = cidx; 2393 fl->offset = offset; 2394 (*fl_bufs_used) += nbuf; 2395 2396 ASSERT(frame.head != NULL); 2397 return (frame.head); 2398 } 2399 2400 /* 2401 * We'll do immediate data tx for non-LSO, but only when not coalescing. We're 2402 * willing to use upto 2 hardware descriptors which means a maximum of 96 bytes 2403 * of immediate data. 2404 */ 2405 #define IMM_LEN ( \ 2406 2 * EQ_ESIZE \ 2407 - sizeof (struct fw_eth_tx_pkt_wr) \ 2408 - sizeof (struct cpl_tx_pkt_core)) 2409 2410 /* 2411 * Returns non-zero on failure, no need to cleanup anything in that case. 2412 * 2413 * Note 1: We always try to pull up the mblk if required and return E2BIG only 2414 * if this fails. 2415 * 2416 * Note 2: We'll also pullup incoming mblk if HW_LSO is set and the first mblk 2417 * does not have the TCP header in it. 2418 */ 2419 static int 2420 get_frame_txinfo(struct sge_txq *txq, mblk_t **fp, struct txinfo *txinfo, 2421 int sgl_only) 2422 { 2423 uint32_t flags = 0, len, n; 2424 mblk_t *m = *fp; 2425 int rc; 2426 2427 TXQ_LOCK_ASSERT_OWNED(txq); /* will manipulate txb and dma_hdls */ 2428 2429 mac_hcksum_get(m, NULL, NULL, NULL, NULL, &flags); 2430 txinfo->flags = flags; 2431 2432 mac_lso_get(m, &txinfo->mss, &flags); 2433 txinfo->flags |= flags; 2434 2435 if (flags & HW_LSO) 2436 sgl_only = 1; /* Do not allow immediate data with LSO */ 2437 2438 start: txinfo->nsegs = 0; 2439 txinfo->hdls_used = 0; 2440 txinfo->txb_used = 0; 2441 txinfo->len = 0; 2442 2443 /* total length and a rough estimate of # of segments */ 2444 n = 0; 2445 for (; m; m = m->b_cont) { 2446 len = MBLKL(m); 2447 n += (len / PAGE_SIZE) + 1; 2448 txinfo->len += len; 2449 } 2450 m = *fp; 2451 2452 if (n >= TX_SGL_SEGS || (flags & HW_LSO && MBLKL(m) < 50)) { 2453 txq->pullup_early++; 2454 m = msgpullup(*fp, -1); 2455 if (m == NULL) { 2456 txq->pullup_failed++; 2457 return (E2BIG); /* (*fp) left as it was */ 2458 } 2459 freemsg(*fp); 2460 *fp = m; 2461 mac_hcksum_set(m, NULL, NULL, NULL, NULL, txinfo->flags); 2462 } 2463 2464 if (txinfo->len <= IMM_LEN && !sgl_only) 2465 return (0); /* nsegs = 0 tells caller to use imm. tx */ 2466 2467 if (txinfo->len <= txq->copy_threshold && 2468 copy_into_txb(txq, m, txinfo->len, txinfo) == 0) 2469 goto done; 2470 2471 for (; m; m = m->b_cont) { 2472 2473 len = MBLKL(m); 2474 2475 /* Use tx copy buffer if this mblk is small enough */ 2476 if (len <= txq->copy_threshold && 2477 copy_into_txb(txq, m, len, txinfo) == 0) 2478 continue; 2479 2480 /* Add DMA bindings for this mblk to the SGL */ 2481 rc = add_mblk(txq, txinfo, m, len); 2482 2483 if (rc == E2BIG || 2484 (txinfo->nsegs == TX_SGL_SEGS && m->b_cont)) { 2485 2486 txq->pullup_late++; 2487 m = msgpullup(*fp, -1); 2488 if (m != NULL) { 2489 free_txinfo_resources(txq, txinfo); 2490 freemsg(*fp); 2491 *fp = m; 2492 mac_hcksum_set(m, NULL, NULL, NULL, NULL, 2493 txinfo->flags); 2494 goto start; 2495 } 2496 2497 txq->pullup_failed++; 2498 rc = E2BIG; 2499 } 2500 2501 if (rc != 0) { 2502 free_txinfo_resources(txq, txinfo); 2503 return (rc); 2504 } 2505 } 2506 2507 ASSERT(txinfo->nsegs > 0 && txinfo->nsegs <= TX_SGL_SEGS); 2508 2509 done: 2510 2511 /* 2512 * Store the # of flits required to hold this frame's SGL in nflits. An 2513 * SGL has a (ULPTX header + len0, addr0) tuple optionally followed by 2514 * multiple (len0 + len1, addr0, addr1) tuples. If addr1 is not used 2515 * then len1 must be set to 0. 2516 */ 2517 n = txinfo->nsegs - 1; 2518 txinfo->nflits = (3 * n) / 2 + (n & 1) + 2; 2519 if (n & 1) 2520 txinfo->sgl.sge[n / 2].len[1] = cpu_to_be32(0); 2521 2522 txinfo->sgl.cmd_nsge = cpu_to_be32(V_ULPTX_CMD((u32)ULP_TX_SC_DSGL) | 2523 V_ULPTX_NSGE(txinfo->nsegs)); 2524 2525 return (0); 2526 } 2527 2528 static inline int 2529 fits_in_txb(struct sge_txq *txq, int len, int *waste) 2530 { 2531 if (txq->txb_avail < len) 2532 return (0); 2533 2534 if (txq->txb_next + len <= txq->txb_size) { 2535 *waste = 0; 2536 return (1); 2537 } 2538 2539 *waste = txq->txb_size - txq->txb_next; 2540 2541 return (txq->txb_avail - *waste < len ? 0 : 1); 2542 } 2543 2544 #define TXB_CHUNK 64 2545 2546 /* 2547 * Copies the specified # of bytes into txq's tx copy buffer and updates txinfo 2548 * and txq to indicate resources used. Caller has to make sure that those many 2549 * bytes are available in the mblk chain (b_cont linked). 2550 */ 2551 static inline int 2552 copy_into_txb(struct sge_txq *txq, mblk_t *m, int len, struct txinfo *txinfo) 2553 { 2554 int waste, n; 2555 2556 TXQ_LOCK_ASSERT_OWNED(txq); /* will manipulate txb */ 2557 2558 if (!fits_in_txb(txq, len, &waste)) { 2559 txq->txb_full++; 2560 return (ENOMEM); 2561 } 2562 2563 if (waste != 0) { 2564 ASSERT((waste & (TXB_CHUNK - 1)) == 0); 2565 txinfo->txb_used += waste; 2566 txq->txb_avail -= waste; 2567 txq->txb_next = 0; 2568 } 2569 2570 for (n = 0; n < len; m = m->b_cont) { 2571 bcopy(m->b_rptr, txq->txb_va + txq->txb_next + n, MBLKL(m)); 2572 n += MBLKL(m); 2573 } 2574 2575 add_seg(txinfo, txq->txb_ba + txq->txb_next, len); 2576 2577 n = roundup(len, TXB_CHUNK); 2578 txinfo->txb_used += n; 2579 txq->txb_avail -= n; 2580 txq->txb_next += n; 2581 ASSERT(txq->txb_next <= txq->txb_size); 2582 if (txq->txb_next == txq->txb_size) 2583 txq->txb_next = 0; 2584 2585 return (0); 2586 } 2587 2588 static inline void 2589 add_seg(struct txinfo *txinfo, uint64_t ba, uint32_t len) 2590 { 2591 ASSERT(txinfo->nsegs < TX_SGL_SEGS); /* must have room */ 2592 2593 if (txinfo->nsegs != 0) { 2594 int idx = txinfo->nsegs - 1; 2595 txinfo->sgl.sge[idx / 2].len[idx & 1] = cpu_to_be32(len); 2596 txinfo->sgl.sge[idx / 2].addr[idx & 1] = cpu_to_be64(ba); 2597 } else { 2598 txinfo->sgl.len0 = cpu_to_be32(len); 2599 txinfo->sgl.addr0 = cpu_to_be64(ba); 2600 } 2601 txinfo->nsegs++; 2602 } 2603 2604 /* 2605 * This function cleans up any partially allocated resources when it fails so 2606 * there's nothing for the caller to clean up in that case. 2607 * 2608 * EIO indicates permanent failure. Caller should drop the frame containing 2609 * this mblk and continue. 2610 * 2611 * E2BIG indicates that the SGL length for this mblk exceeds the hardware 2612 * limit. Caller should pull up the frame before trying to send it out. 2613 * (This error means our pullup_early heuristic did not work for this frame) 2614 * 2615 * ENOMEM indicates a temporary shortage of resources (DMA handles, other DMA 2616 * resources, etc.). Caller should suspend the tx queue and wait for reclaim to 2617 * free up resources. 2618 */ 2619 static inline int 2620 add_mblk(struct sge_txq *txq, struct txinfo *txinfo, mblk_t *m, int len) 2621 { 2622 ddi_dma_handle_t dhdl; 2623 ddi_dma_cookie_t cookie; 2624 uint_t ccount = 0; 2625 int rc; 2626 2627 TXQ_LOCK_ASSERT_OWNED(txq); /* will manipulate dhdls */ 2628 2629 if (txq->tx_dhdl_avail == 0) { 2630 txq->dma_hdl_failed++; 2631 return (ENOMEM); 2632 } 2633 2634 dhdl = txq->tx_dhdl[txq->tx_dhdl_pidx]; 2635 rc = ddi_dma_addr_bind_handle(dhdl, NULL, (caddr_t)m->b_rptr, len, 2636 DDI_DMA_WRITE | DDI_DMA_STREAMING, DDI_DMA_DONTWAIT, NULL, &cookie, 2637 &ccount); 2638 if (rc != DDI_DMA_MAPPED) { 2639 txq->dma_map_failed++; 2640 2641 ASSERT(rc != DDI_DMA_INUSE && rc != DDI_DMA_PARTIAL_MAP); 2642 2643 return (rc == DDI_DMA_NORESOURCES ? ENOMEM : EIO); 2644 } 2645 2646 if (ccount + txinfo->nsegs > TX_SGL_SEGS) { 2647 (void) ddi_dma_unbind_handle(dhdl); 2648 return (E2BIG); 2649 } 2650 2651 add_seg(txinfo, cookie.dmac_laddress, cookie.dmac_size); 2652 while (--ccount) { 2653 ddi_dma_nextcookie(dhdl, &cookie); 2654 add_seg(txinfo, cookie.dmac_laddress, cookie.dmac_size); 2655 } 2656 2657 if (++txq->tx_dhdl_pidx == txq->tx_dhdl_total) 2658 txq->tx_dhdl_pidx = 0; 2659 txq->tx_dhdl_avail--; 2660 txinfo->hdls_used++; 2661 2662 return (0); 2663 } 2664 2665 /* 2666 * Releases all the txq resources used up in the specified txinfo. 2667 */ 2668 static void 2669 free_txinfo_resources(struct sge_txq *txq, struct txinfo *txinfo) 2670 { 2671 int n; 2672 2673 TXQ_LOCK_ASSERT_OWNED(txq); /* dhdls, txb */ 2674 2675 n = txinfo->txb_used; 2676 if (n > 0) { 2677 txq->txb_avail += n; 2678 if (n <= txq->txb_next) 2679 txq->txb_next -= n; 2680 else { 2681 n -= txq->txb_next; 2682 txq->txb_next = txq->txb_size - n; 2683 } 2684 } 2685 2686 for (n = txinfo->hdls_used; n > 0; n--) { 2687 if (txq->tx_dhdl_pidx > 0) 2688 txq->tx_dhdl_pidx--; 2689 else 2690 txq->tx_dhdl_pidx = txq->tx_dhdl_total - 1; 2691 txq->tx_dhdl_avail++; 2692 (void) ddi_dma_unbind_handle(txq->tx_dhdl[txq->tx_dhdl_pidx]); 2693 } 2694 } 2695 2696 /* 2697 * Returns 0 to indicate that m has been accepted into a coalesced tx work 2698 * request. It has either been folded into txpkts or txpkts was flushed and m 2699 * has started a new coalesced work request (as the first frame in a fresh 2700 * txpkts). 2701 * 2702 * Returns non-zero to indicate a failure - caller is responsible for 2703 * transmitting m, if there was anything in txpkts it has been flushed. 2704 */ 2705 static int 2706 add_to_txpkts(struct sge_txq *txq, struct txpkts *txpkts, mblk_t *m, 2707 struct txinfo *txinfo) 2708 { 2709 struct sge_eq *eq = &txq->eq; 2710 int can_coalesce; 2711 struct tx_sdesc *txsd; 2712 uint8_t flits; 2713 2714 TXQ_LOCK_ASSERT_OWNED(txq); 2715 2716 if (txpkts->npkt > 0) { 2717 flits = TXPKTS_PKT_HDR + txinfo->nflits; 2718 can_coalesce = (txinfo->flags & HW_LSO) == 0 && 2719 txpkts->nflits + flits <= TX_WR_FLITS && 2720 txpkts->nflits + flits <= eq->avail * 8 && 2721 txpkts->plen + txinfo->len < 65536; 2722 2723 if (can_coalesce != 0) { 2724 txpkts->tail->b_next = m; 2725 txpkts->tail = m; 2726 txpkts->npkt++; 2727 txpkts->nflits += flits; 2728 txpkts->plen += txinfo->len; 2729 2730 txsd = &txq->sdesc[eq->pidx]; 2731 txsd->txb_used += txinfo->txb_used; 2732 txsd->hdls_used += txinfo->hdls_used; 2733 2734 return (0); 2735 } 2736 2737 /* 2738 * Couldn't coalesce m into txpkts. The first order of business 2739 * is to send txpkts on its way. Then we'll revisit m. 2740 */ 2741 write_txpkts_wr(txq, txpkts); 2742 } 2743 2744 /* 2745 * Check if we can start a new coalesced tx work request with m as 2746 * the first packet in it. 2747 */ 2748 2749 ASSERT(txpkts->npkt == 0); 2750 ASSERT(txinfo->len < 65536); 2751 2752 flits = TXPKTS_WR_HDR + txinfo->nflits; 2753 can_coalesce = (txinfo->flags & HW_LSO) == 0 && 2754 flits <= eq->avail * 8 && flits <= TX_WR_FLITS; 2755 2756 if (can_coalesce == 0) 2757 return (EINVAL); 2758 2759 /* 2760 * Start a fresh coalesced tx WR with m as the first frame in it. 2761 */ 2762 txpkts->tail = m; 2763 txpkts->npkt = 1; 2764 txpkts->nflits = flits; 2765 txpkts->flitp = &eq->desc[eq->pidx].flit[2]; 2766 txpkts->plen = txinfo->len; 2767 2768 txsd = &txq->sdesc[eq->pidx]; 2769 txsd->m = m; 2770 txsd->txb_used = txinfo->txb_used; 2771 txsd->hdls_used = txinfo->hdls_used; 2772 2773 return (0); 2774 } 2775 2776 /* 2777 * Note that write_txpkts_wr can never run out of hardware descriptors (but 2778 * write_txpkt_wr can). add_to_txpkts ensures that a frame is accepted for 2779 * coalescing only if sufficient hardware descriptors are available. 2780 */ 2781 static void 2782 write_txpkts_wr(struct sge_txq *txq, struct txpkts *txpkts) 2783 { 2784 struct sge_eq *eq = &txq->eq; 2785 struct fw_eth_tx_pkts_wr *wr; 2786 struct tx_sdesc *txsd; 2787 uint32_t ctrl; 2788 uint16_t ndesc; 2789 2790 TXQ_LOCK_ASSERT_OWNED(txq); /* pidx, avail */ 2791 2792 ndesc = howmany(txpkts->nflits, 8); 2793 2794 wr = (void *)&eq->desc[eq->pidx]; 2795 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR) | 2796 V_FW_WR_IMMDLEN(0)); /* immdlen does not matter in this WR */ 2797 ctrl = V_FW_WR_LEN16(howmany(txpkts->nflits, 2)); 2798 if (eq->avail == ndesc) 2799 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; 2800 wr->equiq_to_len16 = cpu_to_be32(ctrl); 2801 wr->plen = cpu_to_be16(txpkts->plen); 2802 wr->npkt = txpkts->npkt; 2803 wr->r3 = wr->type = 0; 2804 2805 /* Everything else already written */ 2806 2807 txsd = &txq->sdesc[eq->pidx]; 2808 txsd->desc_used = ndesc; 2809 2810 txq->txb_used += txsd->txb_used / TXB_CHUNK; 2811 txq->hdl_used += txsd->hdls_used; 2812 2813 ASSERT(eq->avail >= ndesc); 2814 2815 eq->pending += ndesc; 2816 eq->avail -= ndesc; 2817 eq->pidx += ndesc; 2818 if (eq->pidx >= eq->cap) 2819 eq->pidx -= eq->cap; 2820 2821 txq->txpkts_pkts += txpkts->npkt; 2822 txq->txpkts_wrs++; 2823 txpkts->npkt = 0; /* emptied */ 2824 } 2825 2826 static int 2827 write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, mblk_t *m, 2828 struct txinfo *txinfo) 2829 { 2830 struct sge_eq *eq = &txq->eq; 2831 struct fw_eth_tx_pkt_wr *wr; 2832 struct cpl_tx_pkt_core *cpl; 2833 uint32_t ctrl; /* used in many unrelated places */ 2834 uint64_t ctrl1; 2835 int nflits, ndesc; 2836 struct tx_sdesc *txsd; 2837 caddr_t dst; 2838 2839 TXQ_LOCK_ASSERT_OWNED(txq); /* pidx, avail */ 2840 2841 /* 2842 * Do we have enough flits to send this frame out? 2843 */ 2844 ctrl = sizeof (struct cpl_tx_pkt_core); 2845 if (txinfo->flags & HW_LSO) { 2846 nflits = TXPKT_LSO_WR_HDR; 2847 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 2848 } else 2849 nflits = TXPKT_WR_HDR; 2850 if (txinfo->nsegs > 0) 2851 nflits += txinfo->nflits; 2852 else { 2853 nflits += howmany(txinfo->len, 8); 2854 ctrl += txinfo->len; 2855 } 2856 ndesc = howmany(nflits, 8); 2857 if (ndesc > eq->avail) 2858 return (ENOMEM); 2859 2860 /* Firmware work request header */ 2861 wr = (void *)&eq->desc[eq->pidx]; 2862 wr->op_immdlen = cpu_to_be32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 2863 V_FW_WR_IMMDLEN(ctrl)); 2864 ctrl = V_FW_WR_LEN16(howmany(nflits, 2)); 2865 if (eq->avail == ndesc) 2866 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; 2867 wr->equiq_to_len16 = cpu_to_be32(ctrl); 2868 wr->r3 = 0; 2869 2870 if (txinfo->flags & HW_LSO) { 2871 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 2872 char *p = (void *)m->b_rptr; 2873 ctrl = V_LSO_OPCODE((u32)CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 2874 F_LSO_LAST_SLICE; 2875 2876 /* LINTED: E_BAD_PTR_CAST_ALIGN */ 2877 if (((struct ether_header *)p)->ether_type == 2878 htons(ETHERTYPE_VLAN)) { 2879 ctrl |= V_LSO_ETHHDR_LEN(1); 2880 p += sizeof (struct ether_vlan_header); 2881 } else 2882 p += sizeof (struct ether_header); 2883 2884 /* LINTED: E_BAD_PTR_CAST_ALIGN for IPH_HDR_LENGTH() */ 2885 ctrl |= V_LSO_IPHDR_LEN(IPH_HDR_LENGTH(p) / 4); 2886 /* LINTED: E_BAD_PTR_CAST_ALIGN for IPH_HDR_LENGTH() */ 2887 p += IPH_HDR_LENGTH(p); 2888 ctrl |= V_LSO_TCPHDR_LEN(TCP_HDR_LENGTH((tcph_t *)p) / 4); 2889 2890 lso->lso_ctrl = cpu_to_be32(ctrl); 2891 lso->ipid_ofst = cpu_to_be16(0); 2892 lso->mss = cpu_to_be16(txinfo->mss); 2893 lso->seqno_offset = cpu_to_be32(0); 2894 if (is_t4(pi->adapter->params.chip)) 2895 lso->len = cpu_to_be32(txinfo->len); 2896 else 2897 lso->len = cpu_to_be32(V_LSO_T5_XFER_SIZE(txinfo->len)); 2898 2899 cpl = (void *)(lso + 1); 2900 2901 txq->tso_wrs++; 2902 } else 2903 cpl = (void *)(wr + 1); 2904 2905 /* Checksum offload */ 2906 ctrl1 = 0; 2907 if (!(txinfo->flags & HCK_IPV4_HDRCKSUM)) 2908 ctrl1 |= F_TXPKT_IPCSUM_DIS; 2909 if (!(txinfo->flags & HCK_FULLCKSUM)) 2910 ctrl1 |= F_TXPKT_L4CSUM_DIS; 2911 if (ctrl1 == 0) 2912 txq->txcsum++; /* some hardware assistance provided */ 2913 2914 /* CPL header */ 2915 cpl->ctrl0 = cpu_to_be32(V_TXPKT_OPCODE(CPL_TX_PKT) | 2916 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); 2917 cpl->pack = 0; 2918 cpl->len = cpu_to_be16(txinfo->len); 2919 cpl->ctrl1 = cpu_to_be64(ctrl1); 2920 2921 /* Software descriptor */ 2922 txsd = &txq->sdesc[eq->pidx]; 2923 txsd->m = m; 2924 txsd->txb_used = txinfo->txb_used; 2925 txsd->hdls_used = txinfo->hdls_used; 2926 /* LINTED: E_ASSIGN_NARROW_CONV */ 2927 txsd->desc_used = ndesc; 2928 2929 txq->txb_used += txinfo->txb_used / TXB_CHUNK; 2930 txq->hdl_used += txinfo->hdls_used; 2931 2932 eq->pending += ndesc; 2933 eq->avail -= ndesc; 2934 eq->pidx += ndesc; 2935 if (eq->pidx >= eq->cap) 2936 eq->pidx -= eq->cap; 2937 2938 /* SGL */ 2939 dst = (void *)(cpl + 1); 2940 if (txinfo->nsegs > 0) { 2941 txq->sgl_wrs++; 2942 copy_to_txd(eq, (void *)&txinfo->sgl, &dst, txinfo->nflits * 8); 2943 2944 /* Need to zero-pad to a 16 byte boundary if not on one */ 2945 if ((uintptr_t)dst & 0xf) 2946 /* LINTED: E_BAD_PTR_CAST_ALIGN */ 2947 *(uint64_t *)dst = 0; 2948 2949 } else { 2950 txq->imm_wrs++; 2951 #ifdef DEBUG 2952 ctrl = txinfo->len; 2953 #endif 2954 for (; m; m = m->b_cont) { 2955 copy_to_txd(eq, (void *)m->b_rptr, &dst, MBLKL(m)); 2956 #ifdef DEBUG 2957 ctrl -= MBLKL(m); 2958 #endif 2959 } 2960 ASSERT(ctrl == 0); 2961 } 2962 2963 txq->txpkt_wrs++; 2964 return (0); 2965 } 2966 2967 static inline void 2968 write_ulp_cpl_sgl(struct port_info *pi, struct sge_txq *txq, 2969 struct txpkts *txpkts, struct txinfo *txinfo) 2970 { 2971 struct ulp_txpkt *ulpmc; 2972 struct ulptx_idata *ulpsc; 2973 struct cpl_tx_pkt_core *cpl; 2974 uintptr_t flitp, start, end; 2975 uint64_t ctrl; 2976 caddr_t dst; 2977 2978 ASSERT(txpkts->npkt > 0); 2979 2980 start = (uintptr_t)txq->eq.desc; 2981 end = (uintptr_t)txq->eq.spg; 2982 2983 /* Checksum offload */ 2984 ctrl = 0; 2985 if (!(txinfo->flags & HCK_IPV4_HDRCKSUM)) 2986 ctrl |= F_TXPKT_IPCSUM_DIS; 2987 if (!(txinfo->flags & HCK_FULLCKSUM)) 2988 ctrl |= F_TXPKT_L4CSUM_DIS; 2989 if (ctrl == 0) 2990 txq->txcsum++; /* some hardware assistance provided */ 2991 2992 /* 2993 * The previous packet's SGL must have ended at a 16 byte boundary (this 2994 * is required by the firmware/hardware). It follows that flitp cannot 2995 * wrap around between the ULPTX master command and ULPTX subcommand (8 2996 * bytes each), and that it can not wrap around in the middle of the 2997 * cpl_tx_pkt_core either. 2998 */ 2999 flitp = (uintptr_t)txpkts->flitp; 3000 ASSERT((flitp & 0xf) == 0); 3001 3002 /* ULP master command */ 3003 ulpmc = (void *)flitp; 3004 ulpmc->cmd_dest = htonl(V_ULPTX_CMD(ULP_TX_PKT) | V_ULP_TXPKT_DEST(0)); 3005 ulpmc->len = htonl(howmany(sizeof (*ulpmc) + sizeof (*ulpsc) + 3006 sizeof (*cpl) + 8 * txinfo->nflits, 16)); 3007 3008 /* ULP subcommand */ 3009 ulpsc = (void *)(ulpmc + 1); 3010 ulpsc->cmd_more = cpu_to_be32(V_ULPTX_CMD((u32)ULP_TX_SC_IMM) | 3011 F_ULP_TX_SC_MORE); 3012 ulpsc->len = cpu_to_be32(sizeof (struct cpl_tx_pkt_core)); 3013 3014 flitp += sizeof (*ulpmc) + sizeof (*ulpsc); 3015 if (flitp == end) 3016 flitp = start; 3017 3018 /* CPL_TX_PKT */ 3019 cpl = (void *)flitp; 3020 cpl->ctrl0 = cpu_to_be32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3021 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); 3022 cpl->pack = 0; 3023 cpl->len = cpu_to_be16(txinfo->len); 3024 cpl->ctrl1 = cpu_to_be64(ctrl); 3025 3026 flitp += sizeof (*cpl); 3027 if (flitp == end) 3028 flitp = start; 3029 3030 /* SGL for this frame */ 3031 dst = (caddr_t)flitp; 3032 copy_to_txd(&txq->eq, (void *)&txinfo->sgl, &dst, txinfo->nflits * 8); 3033 flitp = (uintptr_t)dst; 3034 3035 /* Zero pad and advance to a 16 byte boundary if not already at one. */ 3036 if (flitp & 0xf) { 3037 3038 /* no matter what, flitp should be on an 8 byte boundary */ 3039 ASSERT((flitp & 0x7) == 0); 3040 3041 *(uint64_t *)flitp = 0; 3042 flitp += sizeof (uint64_t); 3043 txpkts->nflits++; 3044 } 3045 3046 if (flitp == end) 3047 flitp = start; 3048 3049 txpkts->flitp = (void *)flitp; 3050 } 3051 3052 static inline void 3053 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 3054 { 3055 if ((uintptr_t)(*to) + len <= (uintptr_t)eq->spg) { 3056 bcopy(from, *to, len); 3057 (*to) += len; 3058 } else { 3059 int portion = (uintptr_t)eq->spg - (uintptr_t)(*to); 3060 3061 bcopy(from, *to, portion); 3062 from += portion; 3063 portion = len - portion; /* remaining */ 3064 bcopy(from, (void *)eq->desc, portion); 3065 (*to) = (caddr_t)eq->desc + portion; 3066 } 3067 } 3068 3069 static inline void 3070 ring_tx_db(struct adapter *sc, struct sge_eq *eq) 3071 { 3072 int val, db_mode; 3073 u_int db = eq->doorbells; 3074 3075 if (eq->pending > 1) 3076 db &= ~DOORBELL_WCWR; 3077 3078 if (eq->pending > eq->pidx) { 3079 int offset = eq->cap - (eq->pending - eq->pidx); 3080 3081 /* pidx has wrapped around since last doorbell */ 3082 3083 (void) ddi_dma_sync(eq->desc_dhdl, 3084 offset * sizeof (struct tx_desc), 0, 3085 DDI_DMA_SYNC_FORDEV); 3086 (void) ddi_dma_sync(eq->desc_dhdl, 3087 0, eq->pidx * sizeof (struct tx_desc), 3088 DDI_DMA_SYNC_FORDEV); 3089 } else if (eq->pending > 0) { 3090 (void) ddi_dma_sync(eq->desc_dhdl, 3091 (eq->pidx - eq->pending) * sizeof (struct tx_desc), 3092 eq->pending * sizeof (struct tx_desc), 3093 DDI_DMA_SYNC_FORDEV); 3094 } 3095 3096 membar_producer(); 3097 3098 if (is_t4(sc->params.chip)) 3099 val = V_PIDX(eq->pending); 3100 else 3101 val = V_PIDX_T5(eq->pending); 3102 3103 db_mode = (1 << (ffs(db) - 1)); 3104 switch (db_mode) { 3105 case DOORBELL_UDB: 3106 *eq->udb = LE_32(V_QID(eq->udb_qid) | val); 3107 break; 3108 3109 case DOORBELL_WCWR: 3110 { 3111 volatile uint64_t *dst, *src; 3112 int i; 3113 /* 3114 * Queues whose 128B doorbell segment fits in 3115 * the page do not use relative qid 3116 * (udb_qid is always 0). Only queues with 3117 * doorbell segments can do WCWR. 3118 */ 3119 ASSERT(eq->udb_qid == 0 && eq->pending == 1); 3120 3121 dst = (volatile void *)((uintptr_t)eq->udb + 3122 UDBS_WR_OFFSET - UDBS_DB_OFFSET); 3123 i = eq->pidx ? eq->pidx - 1 : eq->cap - 1; 3124 src = (void *)&eq->desc[i]; 3125 while (src != (void *)&eq->desc[i + 1]) 3126 *dst++ = *src++; 3127 membar_producer(); 3128 break; 3129 } 3130 3131 case DOORBELL_UDBWC: 3132 *eq->udb = LE_32(V_QID(eq->udb_qid) | val); 3133 membar_producer(); 3134 break; 3135 3136 case DOORBELL_KDB: 3137 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), 3138 V_QID(eq->cntxt_id) | val); 3139 break; 3140 } 3141 3142 eq->pending = 0; 3143 } 3144 3145 static int 3146 reclaim_tx_descs(struct sge_txq *txq, int howmany) 3147 { 3148 struct tx_sdesc *txsd; 3149 uint_t cidx, can_reclaim, reclaimed, txb_freed, hdls_freed; 3150 struct sge_eq *eq = &txq->eq; 3151 3152 EQ_LOCK_ASSERT_OWNED(eq); 3153 3154 cidx = eq->spg->cidx; /* stable snapshot */ 3155 cidx = be16_to_cpu(cidx); 3156 3157 if (cidx >= eq->cidx) 3158 can_reclaim = cidx - eq->cidx; 3159 else 3160 can_reclaim = cidx + eq->cap - eq->cidx; 3161 3162 if (can_reclaim == 0) 3163 return (0); 3164 3165 txb_freed = hdls_freed = reclaimed = 0; 3166 do { 3167 int ndesc; 3168 3169 txsd = &txq->sdesc[eq->cidx]; 3170 ndesc = txsd->desc_used; 3171 3172 /* Firmware doesn't return "partial" credits. */ 3173 ASSERT(can_reclaim >= ndesc); 3174 3175 /* 3176 * We always keep mblk around, even for immediate data. If mblk 3177 * is NULL, this has to be the software descriptor for a credit 3178 * flush work request. 3179 */ 3180 if (txsd->m != NULL) 3181 freemsgchain(txsd->m); 3182 #ifdef DEBUG 3183 else { 3184 ASSERT(txsd->txb_used == 0); 3185 ASSERT(txsd->hdls_used == 0); 3186 ASSERT(ndesc == 1); 3187 } 3188 #endif 3189 3190 txb_freed += txsd->txb_used; 3191 hdls_freed += txsd->hdls_used; 3192 reclaimed += ndesc; 3193 3194 eq->cidx += ndesc; 3195 if (eq->cidx >= eq->cap) 3196 eq->cidx -= eq->cap; 3197 3198 can_reclaim -= ndesc; 3199 3200 } while (can_reclaim && reclaimed < howmany); 3201 3202 eq->avail += reclaimed; 3203 ASSERT(eq->avail < eq->cap); /* avail tops out at (cap - 1) */ 3204 3205 txq->txb_avail += txb_freed; 3206 3207 txq->tx_dhdl_avail += hdls_freed; 3208 ASSERT(txq->tx_dhdl_avail <= txq->tx_dhdl_total); 3209 for (; hdls_freed; hdls_freed--) { 3210 (void) ddi_dma_unbind_handle(txq->tx_dhdl[txq->tx_dhdl_cidx]); 3211 if (++txq->tx_dhdl_cidx == txq->tx_dhdl_total) 3212 txq->tx_dhdl_cidx = 0; 3213 } 3214 3215 return (reclaimed); 3216 } 3217 3218 static void 3219 write_txqflush_wr(struct sge_txq *txq) 3220 { 3221 struct sge_eq *eq = &txq->eq; 3222 struct fw_eq_flush_wr *wr; 3223 struct tx_sdesc *txsd; 3224 3225 EQ_LOCK_ASSERT_OWNED(eq); 3226 ASSERT(eq->avail > 0); 3227 3228 wr = (void *)&eq->desc[eq->pidx]; 3229 bzero(wr, sizeof (*wr)); 3230 wr->opcode = FW_EQ_FLUSH_WR; 3231 wr->equiq_to_len16 = cpu_to_be32(V_FW_WR_LEN16(sizeof (*wr) / 16) | 3232 F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 3233 3234 txsd = &txq->sdesc[eq->pidx]; 3235 txsd->m = NULL; 3236 txsd->txb_used = 0; 3237 txsd->hdls_used = 0; 3238 txsd->desc_used = 1; 3239 3240 eq->pending++; 3241 eq->avail--; 3242 if (++eq->pidx == eq->cap) 3243 eq->pidx = 0; 3244 } 3245 3246 static int 3247 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, mblk_t *m) 3248 { 3249 bool csum_ok; 3250 uint16_t err_vec; 3251 struct sge_rxq *rxq = (void *)iq; 3252 struct mblk_pair chain = {0}; 3253 struct adapter *sc = iq->adapter; 3254 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 3255 3256 iq->intr_next = iq->intr_params; 3257 3258 m->b_rptr += sc->sge.pktshift; 3259 3260 /* Compressed error vector is enabled for T6 only */ 3261 if (sc->params.tp.rx_pkt_encap) 3262 /* It is enabled only in T6 config file */ 3263 err_vec = G_T6_COMPR_RXERR_VEC(ntohs(cpl->err_vec)); 3264 else 3265 err_vec = ntohs(cpl->err_vec); 3266 3267 csum_ok = cpl->csum_calc && !err_vec; 3268 /* TODO: what about cpl->ip_frag? */ 3269 if (csum_ok && !cpl->ip_frag) { 3270 mac_hcksum_set(m, 0, 0, 0, 0xffff, 3271 HCK_FULLCKSUM_OK | HCK_FULLCKSUM | 3272 HCK_IPV4_HDRCKSUM_OK); 3273 rxq->rxcsum++; 3274 } 3275 3276 /* Add to the chain that we'll send up */ 3277 if (chain.head != NULL) 3278 chain.tail->b_next = m; 3279 else 3280 chain.head = m; 3281 chain.tail = m; 3282 3283 t4_mac_rx(rxq->port, rxq, chain.head); 3284 3285 rxq->rxpkts++; 3286 rxq->rxbytes += be16_to_cpu(cpl->len); 3287 return (0); 3288 } 3289 3290 #define FL_HW_IDX(idx) ((idx) >> 3) 3291 3292 static inline void 3293 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 3294 { 3295 int desc_start, desc_last, ndesc; 3296 uint32_t v = sc->params.arch.sge_fl_db ; 3297 3298 ndesc = FL_HW_IDX(fl->pending); 3299 3300 /* Hold back one credit if pidx = cidx */ 3301 if (FL_HW_IDX(fl->pidx) == FL_HW_IDX(fl->cidx)) 3302 ndesc--; 3303 3304 /* 3305 * There are chances of ndesc modified above (to avoid pidx = cidx). 3306 * If there is nothing to post, return. 3307 */ 3308 if (ndesc <= 0) 3309 return; 3310 3311 desc_last = FL_HW_IDX(fl->pidx); 3312 3313 if (fl->pidx < fl->pending) { 3314 /* There was a wrap */ 3315 desc_start = FL_HW_IDX(fl->pidx + fl->cap - fl->pending); 3316 3317 /* From desc_start to the end of list */ 3318 (void) ddi_dma_sync(fl->dhdl, desc_start * RX_FL_ESIZE, 0, 3319 DDI_DMA_SYNC_FORDEV); 3320 3321 /* From start of list to the desc_last */ 3322 if (desc_last != 0) 3323 (void) ddi_dma_sync(fl->dhdl, 0, desc_last * 3324 RX_FL_ESIZE, DDI_DMA_SYNC_FORDEV); 3325 } else { 3326 /* There was no wrap, sync from start_desc to last_desc */ 3327 desc_start = FL_HW_IDX(fl->pidx - fl->pending); 3328 (void) ddi_dma_sync(fl->dhdl, desc_start * RX_FL_ESIZE, 3329 ndesc * RX_FL_ESIZE, DDI_DMA_SYNC_FORDEV); 3330 } 3331 3332 if (is_t4(sc->params.chip)) 3333 v |= V_PIDX(ndesc); 3334 else 3335 v |= V_PIDX_T5(ndesc); 3336 v |= V_QID(fl->cntxt_id) | V_PIDX(ndesc); 3337 3338 membar_producer(); 3339 3340 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v); 3341 3342 /* 3343 * Update pending count: 3344 * Deduct the number of descriptors posted 3345 */ 3346 fl->pending -= ndesc * 8; 3347 } 3348 3349 /* ARGSUSED */ 3350 static int 3351 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 3352 mblk_t *m) 3353 { 3354 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 3355 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 3356 struct adapter *sc = iq->adapter; 3357 struct sge *s = &sc->sge; 3358 struct sge_txq *txq; 3359 3360 txq = (void *)s->eqmap[qid - s->eq_start]; 3361 txq->qflush++; 3362 t4_mac_tx_update(txq->port, txq); 3363 3364 return (0); 3365 } 3366 3367 static int 3368 handle_fw_rpl(struct sge_iq *iq, const struct rss_header *rss, mblk_t *m) 3369 { 3370 struct adapter *sc = iq->adapter; 3371 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 3372 3373 ASSERT(m == NULL); 3374 3375 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 3376 const struct rss_header *rss2; 3377 3378 rss2 = (const struct rss_header *)&cpl->data[0]; 3379 return (sc->cpl_handler[rss2->opcode](iq, rss2, m)); 3380 } 3381 return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0])); 3382 } 3383 3384 int 3385 t4_alloc_tx_maps(struct adapter *sc, struct tx_maps *txmaps, int count, 3386 int flags) 3387 { 3388 int i, rc; 3389 3390 txmaps->map_total = count; 3391 txmaps->map_avail = txmaps->map_cidx = txmaps->map_pidx = 0; 3392 3393 txmaps->map = kmem_zalloc(sizeof (ddi_dma_handle_t) * 3394 txmaps->map_total, flags); 3395 3396 for (i = 0; i < count; i++) { 3397 rc = ddi_dma_alloc_handle(sc->dip, &sc->sge.dma_attr_tx, 3398 DDI_DMA_SLEEP, 0, &txmaps->map[i]); 3399 if (rc != DDI_SUCCESS) { 3400 cxgb_printf(sc->dip, CE_WARN, 3401 "%s: failed to allocate DMA handle (%d)", 3402 __func__, rc); 3403 return (rc == DDI_DMA_NORESOURCES ? ENOMEM : EINVAL); 3404 } 3405 txmaps->map_avail++; 3406 } 3407 3408 return (0); 3409 } 3410 3411 #define KS_UINIT(x) kstat_named_init(&kstatp->x, #x, KSTAT_DATA_ULONG) 3412 #define KS_CINIT(x) kstat_named_init(&kstatp->x, #x, KSTAT_DATA_CHAR) 3413 #define KS_U_SET(x, y) kstatp->x.value.ul = (y) 3414 #define KS_U_FROM(x, y) kstatp->x.value.ul = (y)->x 3415 #define KS_C_SET(x, ...) \ 3416 (void) snprintf(kstatp->x.value.c, 16, __VA_ARGS__) 3417 3418 /* 3419 * cxgbe:X:config 3420 */ 3421 struct cxgbe_port_config_kstats { 3422 kstat_named_t idx; 3423 kstat_named_t nrxq; 3424 kstat_named_t ntxq; 3425 kstat_named_t first_rxq; 3426 kstat_named_t first_txq; 3427 kstat_named_t controller; 3428 kstat_named_t factory_mac_address; 3429 }; 3430 3431 /* 3432 * cxgbe:X:info 3433 */ 3434 struct cxgbe_port_info_kstats { 3435 kstat_named_t transceiver; 3436 kstat_named_t rx_ovflow0; 3437 kstat_named_t rx_ovflow1; 3438 kstat_named_t rx_ovflow2; 3439 kstat_named_t rx_ovflow3; 3440 kstat_named_t rx_trunc0; 3441 kstat_named_t rx_trunc1; 3442 kstat_named_t rx_trunc2; 3443 kstat_named_t rx_trunc3; 3444 kstat_named_t tx_pause; 3445 kstat_named_t rx_pause; 3446 }; 3447 3448 static kstat_t * 3449 setup_port_config_kstats(struct port_info *pi) 3450 { 3451 kstat_t *ksp; 3452 struct cxgbe_port_config_kstats *kstatp; 3453 int ndata; 3454 dev_info_t *pdip = ddi_get_parent(pi->dip); 3455 uint8_t *ma = &pi->hw_addr[0]; 3456 3457 ndata = sizeof (struct cxgbe_port_config_kstats) / 3458 sizeof (kstat_named_t); 3459 3460 ksp = kstat_create(T4_PORT_NAME, ddi_get_instance(pi->dip), "config", 3461 "net", KSTAT_TYPE_NAMED, ndata, 0); 3462 if (ksp == NULL) { 3463 cxgb_printf(pi->dip, CE_WARN, "failed to initialize kstats."); 3464 return (NULL); 3465 } 3466 3467 kstatp = (struct cxgbe_port_config_kstats *)ksp->ks_data; 3468 3469 KS_UINIT(idx); 3470 KS_UINIT(nrxq); 3471 KS_UINIT(ntxq); 3472 KS_UINIT(first_rxq); 3473 KS_UINIT(first_txq); 3474 KS_CINIT(controller); 3475 KS_CINIT(factory_mac_address); 3476 3477 KS_U_SET(idx, pi->port_id); 3478 KS_U_SET(nrxq, pi->nrxq); 3479 KS_U_SET(ntxq, pi->ntxq); 3480 KS_U_SET(first_rxq, pi->first_rxq); 3481 KS_U_SET(first_txq, pi->first_txq); 3482 KS_C_SET(controller, "%s%d", ddi_driver_name(pdip), 3483 ddi_get_instance(pdip)); 3484 KS_C_SET(factory_mac_address, "%02X%02X%02X%02X%02X%02X", 3485 ma[0], ma[1], ma[2], ma[3], ma[4], ma[5]); 3486 3487 /* Do NOT set ksp->ks_update. These kstats do not change. */ 3488 3489 /* Install the kstat */ 3490 ksp->ks_private = (void *)pi; 3491 kstat_install(ksp); 3492 3493 return (ksp); 3494 } 3495 3496 static kstat_t * 3497 setup_port_info_kstats(struct port_info *pi) 3498 { 3499 kstat_t *ksp; 3500 struct cxgbe_port_info_kstats *kstatp; 3501 int ndata; 3502 3503 ndata = sizeof (struct cxgbe_port_info_kstats) / sizeof (kstat_named_t); 3504 3505 ksp = kstat_create(T4_PORT_NAME, ddi_get_instance(pi->dip), "info", 3506 "net", KSTAT_TYPE_NAMED, ndata, 0); 3507 if (ksp == NULL) { 3508 cxgb_printf(pi->dip, CE_WARN, "failed to initialize kstats."); 3509 return (NULL); 3510 } 3511 3512 kstatp = (struct cxgbe_port_info_kstats *)ksp->ks_data; 3513 3514 KS_CINIT(transceiver); 3515 KS_UINIT(rx_ovflow0); 3516 KS_UINIT(rx_ovflow1); 3517 KS_UINIT(rx_ovflow2); 3518 KS_UINIT(rx_ovflow3); 3519 KS_UINIT(rx_trunc0); 3520 KS_UINIT(rx_trunc1); 3521 KS_UINIT(rx_trunc2); 3522 KS_UINIT(rx_trunc3); 3523 KS_UINIT(tx_pause); 3524 KS_UINIT(rx_pause); 3525 3526 /* Install the kstat */ 3527 ksp->ks_update = update_port_info_kstats; 3528 ksp->ks_private = (void *)pi; 3529 kstat_install(ksp); 3530 3531 return (ksp); 3532 } 3533 3534 static int 3535 update_port_info_kstats(kstat_t *ksp, int rw) 3536 { 3537 struct cxgbe_port_info_kstats *kstatp = 3538 (struct cxgbe_port_info_kstats *)ksp->ks_data; 3539 struct port_info *pi = ksp->ks_private; 3540 static const char *mod_str[] = { NULL, "LR", "SR", "ER", "TWINAX", 3541 "active TWINAX", "LRM" }; 3542 uint32_t bgmap; 3543 3544 if (rw == KSTAT_WRITE) 3545 return (0); 3546 3547 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 3548 KS_C_SET(transceiver, "unplugged"); 3549 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 3550 KS_C_SET(transceiver, "unknown"); 3551 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 3552 KS_C_SET(transceiver, "unsupported"); 3553 else if (pi->mod_type > 0 && pi->mod_type < ARRAY_SIZE(mod_str)) 3554 KS_C_SET(transceiver, "%s", mod_str[pi->mod_type]); 3555 else 3556 KS_C_SET(transceiver, "type %d", pi->mod_type); 3557 3558 #define GET_STAT(name) t4_read_reg64(pi->adapter, \ 3559 PORT_REG(pi->port_id, A_MPS_PORT_STAT_##name##_L)) 3560 #define GET_STAT_COM(name) t4_read_reg64(pi->adapter, \ 3561 A_MPS_STAT_##name##_L) 3562 3563 bgmap = G_NUMPORTS(t4_read_reg(pi->adapter, A_MPS_CMN_CTL)); 3564 if (bgmap == 0) 3565 bgmap = (pi->port_id == 0) ? 0xf : 0; 3566 else if (bgmap == 1) 3567 bgmap = (pi->port_id < 2) ? (3 << (2 * pi->port_id)) : 0; 3568 else 3569 bgmap = 1; 3570 3571 KS_U_SET(rx_ovflow0, (bgmap & 1) ? 3572 GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0); 3573 KS_U_SET(rx_ovflow1, (bgmap & 2) ? 3574 GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0); 3575 KS_U_SET(rx_ovflow2, (bgmap & 4) ? 3576 GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0); 3577 KS_U_SET(rx_ovflow3, (bgmap & 8) ? 3578 GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0); 3579 KS_U_SET(rx_trunc0, (bgmap & 1) ? 3580 GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0); 3581 KS_U_SET(rx_trunc1, (bgmap & 2) ? 3582 GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0); 3583 KS_U_SET(rx_trunc2, (bgmap & 4) ? 3584 GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0); 3585 KS_U_SET(rx_trunc3, (bgmap & 8) ? 3586 GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0); 3587 3588 KS_U_SET(tx_pause, GET_STAT(TX_PORT_PAUSE)); 3589 KS_U_SET(rx_pause, GET_STAT(RX_PORT_PAUSE)); 3590 3591 return (0); 3592 3593 } 3594 3595 /* 3596 * cxgbe:X:rxqY 3597 */ 3598 struct rxq_kstats { 3599 kstat_named_t rxcsum; 3600 kstat_named_t rxpkts; 3601 kstat_named_t rxbytes; 3602 kstat_named_t nomem; 3603 }; 3604 3605 static kstat_t * 3606 setup_rxq_kstats(struct port_info *pi, struct sge_rxq *rxq, int idx) 3607 { 3608 struct kstat *ksp; 3609 struct rxq_kstats *kstatp; 3610 int ndata; 3611 char str[16]; 3612 3613 ndata = sizeof (struct rxq_kstats) / sizeof (kstat_named_t); 3614 (void) snprintf(str, sizeof (str), "rxq%u", idx); 3615 3616 ksp = kstat_create(T4_PORT_NAME, ddi_get_instance(pi->dip), str, "rxq", 3617 KSTAT_TYPE_NAMED, ndata, 0); 3618 if (ksp == NULL) { 3619 cxgb_printf(pi->dip, CE_WARN, 3620 "%s: failed to initialize rxq kstats for queue %d.", 3621 __func__, idx); 3622 return (NULL); 3623 } 3624 3625 kstatp = (struct rxq_kstats *)ksp->ks_data; 3626 3627 KS_UINIT(rxcsum); 3628 KS_UINIT(rxpkts); 3629 KS_UINIT(rxbytes); 3630 KS_UINIT(nomem); 3631 3632 ksp->ks_update = update_rxq_kstats; 3633 ksp->ks_private = (void *)rxq; 3634 kstat_install(ksp); 3635 3636 return (ksp); 3637 } 3638 3639 static int 3640 update_rxq_kstats(kstat_t *ksp, int rw) 3641 { 3642 struct rxq_kstats *kstatp = (struct rxq_kstats *)ksp->ks_data; 3643 struct sge_rxq *rxq = ksp->ks_private; 3644 3645 if (rw == KSTAT_WRITE) 3646 return (0); 3647 3648 KS_U_FROM(rxcsum, rxq); 3649 KS_U_FROM(rxpkts, rxq); 3650 KS_U_FROM(rxbytes, rxq); 3651 KS_U_FROM(nomem, rxq); 3652 3653 return (0); 3654 } 3655 3656 /* 3657 * cxgbe:X:txqY 3658 */ 3659 struct txq_kstats { 3660 kstat_named_t txcsum; 3661 kstat_named_t tso_wrs; 3662 kstat_named_t imm_wrs; 3663 kstat_named_t sgl_wrs; 3664 kstat_named_t txpkt_wrs; 3665 kstat_named_t txpkts_wrs; 3666 kstat_named_t txpkts_pkts; 3667 kstat_named_t txb_used; 3668 kstat_named_t hdl_used; 3669 kstat_named_t txb_full; 3670 kstat_named_t dma_hdl_failed; 3671 kstat_named_t dma_map_failed; 3672 kstat_named_t qfull; 3673 kstat_named_t qflush; 3674 kstat_named_t pullup_early; 3675 kstat_named_t pullup_late; 3676 kstat_named_t pullup_failed; 3677 }; 3678 3679 static kstat_t * 3680 setup_txq_kstats(struct port_info *pi, struct sge_txq *txq, int idx) 3681 { 3682 struct kstat *ksp; 3683 struct txq_kstats *kstatp; 3684 int ndata; 3685 char str[16]; 3686 3687 ndata = sizeof (struct txq_kstats) / sizeof (kstat_named_t); 3688 (void) snprintf(str, sizeof (str), "txq%u", idx); 3689 3690 ksp = kstat_create(T4_PORT_NAME, ddi_get_instance(pi->dip), str, "txq", 3691 KSTAT_TYPE_NAMED, ndata, 0); 3692 if (ksp == NULL) { 3693 cxgb_printf(pi->dip, CE_WARN, 3694 "%s: failed to initialize txq kstats for queue %d.", 3695 __func__, idx); 3696 return (NULL); 3697 } 3698 3699 kstatp = (struct txq_kstats *)ksp->ks_data; 3700 3701 KS_UINIT(txcsum); 3702 KS_UINIT(tso_wrs); 3703 KS_UINIT(imm_wrs); 3704 KS_UINIT(sgl_wrs); 3705 KS_UINIT(txpkt_wrs); 3706 KS_UINIT(txpkts_wrs); 3707 KS_UINIT(txpkts_pkts); 3708 KS_UINIT(txb_used); 3709 KS_UINIT(hdl_used); 3710 KS_UINIT(txb_full); 3711 KS_UINIT(dma_hdl_failed); 3712 KS_UINIT(dma_map_failed); 3713 KS_UINIT(qfull); 3714 KS_UINIT(qflush); 3715 KS_UINIT(pullup_early); 3716 KS_UINIT(pullup_late); 3717 KS_UINIT(pullup_failed); 3718 3719 ksp->ks_update = update_txq_kstats; 3720 ksp->ks_private = (void *)txq; 3721 kstat_install(ksp); 3722 3723 return (ksp); 3724 } 3725 3726 static int 3727 update_txq_kstats(kstat_t *ksp, int rw) 3728 { 3729 struct txq_kstats *kstatp = (struct txq_kstats *)ksp->ks_data; 3730 struct sge_txq *txq = ksp->ks_private; 3731 3732 if (rw == KSTAT_WRITE) 3733 return (0); 3734 3735 KS_U_FROM(txcsum, txq); 3736 KS_U_FROM(tso_wrs, txq); 3737 KS_U_FROM(imm_wrs, txq); 3738 KS_U_FROM(sgl_wrs, txq); 3739 KS_U_FROM(txpkt_wrs, txq); 3740 KS_U_FROM(txpkts_wrs, txq); 3741 KS_U_FROM(txpkts_pkts, txq); 3742 KS_U_FROM(txb_used, txq); 3743 KS_U_FROM(hdl_used, txq); 3744 KS_U_FROM(txb_full, txq); 3745 KS_U_FROM(dma_hdl_failed, txq); 3746 KS_U_FROM(dma_map_failed, txq); 3747 KS_U_FROM(qfull, txq); 3748 KS_U_FROM(qflush, txq); 3749 KS_U_FROM(pullup_early, txq); 3750 KS_U_FROM(pullup_late, txq); 3751 KS_U_FROM(pullup_failed, txq); 3752 3753 return (0); 3754 } 3755