1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4 support code. 14 * 15 * Copyright (C) 2010-2013 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23 /* 24 * Copyright 2024 Oxide Computer Company 25 */ 26 27 #include <sys/ddi.h> 28 #include <sys/sunddi.h> 29 #include <sys/sunndi.h> 30 #include <sys/modctl.h> 31 #include <sys/conf.h> 32 #include <sys/devops.h> 33 #include <sys/pci.h> 34 #include <sys/atomic.h> 35 #include <sys/types.h> 36 #include <sys/file.h> 37 #include <sys/errno.h> 38 #include <sys/open.h> 39 #include <sys/cred.h> 40 #include <sys/stat.h> 41 #include <sys/mkdev.h> 42 #include <sys/queue.h> 43 #include <sys/containerof.h> 44 #include <sys/sensors.h> 45 #include <sys/firmload.h> 46 #include <sys/mac_provider.h> 47 #include <sys/mac_ether.h> 48 #include <sys/vlan.h> 49 50 #include "common/common.h" 51 #include "common/t4_msg.h" 52 #include "common/t4_regs.h" 53 #include "common/t4_extra_regs.h" 54 55 static int t4_cb_open(dev_t *devp, int flag, int otyp, cred_t *credp); 56 static int t4_cb_close(dev_t dev, int flag, int otyp, cred_t *credp); 57 static int t4_cb_ioctl(dev_t dev, int cmd, intptr_t d, int mode, cred_t *credp, 58 int *rp); 59 struct cb_ops t4_cb_ops = { 60 .cb_open = t4_cb_open, 61 .cb_close = t4_cb_close, 62 .cb_strategy = nodev, 63 .cb_print = nodev, 64 .cb_dump = nodev, 65 .cb_read = nodev, 66 .cb_write = nodev, 67 .cb_ioctl = t4_cb_ioctl, 68 .cb_devmap = nodev, 69 .cb_mmap = nodev, 70 .cb_segmap = nodev, 71 .cb_chpoll = nochpoll, 72 .cb_prop_op = ddi_prop_op, 73 .cb_flag = D_MP, 74 .cb_rev = CB_REV, 75 .cb_aread = nodev, 76 .cb_awrite = nodev 77 }; 78 79 static int t4_bus_ctl(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t op, 80 void *arg, void *result); 81 static int t4_bus_config(dev_info_t *dip, uint_t flags, ddi_bus_config_op_t op, 82 void *arg, dev_info_t **cdipp); 83 static int t4_bus_unconfig(dev_info_t *dip, uint_t flags, 84 ddi_bus_config_op_t op, void *arg); 85 struct bus_ops t4_bus_ops = { 86 .busops_rev = BUSO_REV, 87 .bus_ctl = t4_bus_ctl, 88 .bus_prop_op = ddi_bus_prop_op, 89 .bus_config = t4_bus_config, 90 .bus_unconfig = t4_bus_unconfig, 91 }; 92 93 static int t4_devo_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, 94 void **rp); 95 static int t4_devo_probe(dev_info_t *dip); 96 static int t4_devo_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 97 static int t4_devo_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 98 static int t4_devo_quiesce(dev_info_t *dip); 99 static struct dev_ops t4_dev_ops = { 100 .devo_rev = DEVO_REV, 101 .devo_getinfo = t4_devo_getinfo, 102 .devo_identify = nulldev, 103 .devo_probe = t4_devo_probe, 104 .devo_attach = t4_devo_attach, 105 .devo_detach = t4_devo_detach, 106 .devo_reset = nodev, 107 .devo_cb_ops = &t4_cb_ops, 108 .devo_bus_ops = &t4_bus_ops, 109 .devo_quiesce = &t4_devo_quiesce, 110 }; 111 112 static struct modldrv t4nex_modldrv = { 113 .drv_modops = &mod_driverops, 114 .drv_linkinfo = "Chelsio T4-T6 nexus " DRV_VERSION, 115 .drv_dev_ops = &t4_dev_ops 116 }; 117 118 static struct modlinkage t4nex_modlinkage = { 119 .ml_rev = MODREV_1, 120 .ml_linkage = {&t4nex_modldrv, NULL}, 121 }; 122 123 void *t4_list; 124 125 struct intrs_and_queues { 126 int intr_type; /* DDI_INTR_TYPE_* */ 127 int nirq; /* Number of vectors */ 128 int intr_fwd; /* Interrupts forwarded */ 129 int ntxq10g; /* # of NIC txq's for each 10G port */ 130 int nrxq10g; /* # of NIC rxq's for each 10G port */ 131 int ntxq1g; /* # of NIC txq's for each 1G port */ 132 int nrxq1g; /* # of NIC rxq's for each 1G port */ 133 }; 134 135 static unsigned int getpf(struct adapter *sc); 136 static int prep_firmware(struct adapter *sc); 137 static int upload_config_file(struct adapter *sc, uint32_t *mt, uint32_t *ma); 138 static int partition_resources(struct adapter *sc); 139 static int adap__pre_init_tweaks(struct adapter *sc); 140 static int get_params__pre_init(struct adapter *sc); 141 static int get_params__post_init(struct adapter *sc); 142 static int set_params__post_init(struct adapter *); 143 static void setup_memwin(struct adapter *sc); 144 static int validate_mt_off_len(struct adapter *, int, uint32_t, int, 145 uint32_t *); 146 void memwin_info(struct adapter *, int, uint32_t *, uint32_t *); 147 uint32_t position_memwin(struct adapter *, int, uint32_t); 148 static int prop_lookup_int_array(struct adapter *sc, char *name, int *data, 149 uint_t count); 150 static int prop_lookup_int_array(struct adapter *sc, char *name, int *data, 151 uint_t count); 152 static int init_driver_props(struct adapter *sc, struct driver_properties *p); 153 static int remove_extra_props(struct adapter *sc, int n10g, int n1g); 154 static int cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, 155 struct intrs_and_queues *iaq); 156 static int add_child_node(struct adapter *sc, int idx); 157 static int remove_child_node(struct adapter *sc, int idx); 158 static kstat_t *setup_kstats(struct adapter *sc); 159 static kstat_t *setup_wc_kstats(struct adapter *); 160 static int update_wc_kstats(kstat_t *, int); 161 static kmutex_t t4_adapter_list_lock; 162 static SLIST_HEAD(, adapter) t4_adapter_list; 163 164 static int t4_temperature_read(void *, sensor_ioctl_scalar_t *); 165 static int t4_voltage_read(void *, sensor_ioctl_scalar_t *); 166 static const ksensor_ops_t t4_temp_ops = { 167 .kso_kind = ksensor_kind_temperature, 168 .kso_scalar = t4_temperature_read 169 }; 170 171 static const ksensor_ops_t t4_volt_ops = { 172 .kso_kind = ksensor_kind_voltage, 173 .kso_scalar = t4_voltage_read 174 }; 175 176 static int t4_ufm_getcaps(ddi_ufm_handle_t *, void *, ddi_ufm_cap_t *); 177 static int t4_ufm_fill_image(ddi_ufm_handle_t *, void *, uint_t, 178 ddi_ufm_image_t *); 179 static int t4_ufm_fill_slot(ddi_ufm_handle_t *, void *, uint_t, uint_t, 180 ddi_ufm_slot_t *); 181 static ddi_ufm_ops_t t4_ufm_ops = { 182 .ddi_ufm_op_fill_image = t4_ufm_fill_image, 183 .ddi_ufm_op_fill_slot = t4_ufm_fill_slot, 184 .ddi_ufm_op_getcaps = t4_ufm_getcaps 185 }; 186 187 int 188 _init(void) 189 { 190 int rc; 191 192 rc = ddi_soft_state_init(&t4_list, sizeof (struct adapter), 0); 193 if (rc != 0) 194 return (rc); 195 196 rc = mod_install(&t4nex_modlinkage); 197 if (rc != 0) 198 ddi_soft_state_fini(&t4_list); 199 200 mutex_init(&t4_adapter_list_lock, NULL, MUTEX_DRIVER, NULL); 201 SLIST_INIT(&t4_adapter_list); 202 t4_debug_init(); 203 204 return (0); 205 } 206 207 int 208 _fini(void) 209 { 210 int rc; 211 212 rc = mod_remove(&t4nex_modlinkage); 213 if (rc != 0) 214 return (rc); 215 216 ddi_soft_state_fini(&t4_list); 217 t4_debug_fini(); 218 219 return (0); 220 } 221 222 int 223 _info(struct modinfo *mi) 224 { 225 return (mod_info(&t4nex_modlinkage, mi)); 226 } 227 228 /* ARGSUSED */ 229 static int 230 t4_devo_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **rp) 231 { 232 struct adapter *sc; 233 minor_t minor; 234 235 minor = getminor((dev_t)arg); /* same as instance# in our case */ 236 237 if (cmd == DDI_INFO_DEVT2DEVINFO) { 238 sc = ddi_get_soft_state(t4_list, minor); 239 if (sc == NULL) 240 return (DDI_FAILURE); 241 242 ASSERT(sc->dev == (dev_t)arg); 243 *rp = (void *)sc->dip; 244 } else if (cmd == DDI_INFO_DEVT2INSTANCE) 245 *rp = (void *) (unsigned long) minor; 246 else 247 ASSERT(0); 248 249 return (DDI_SUCCESS); 250 } 251 252 static int 253 t4_devo_probe(dev_info_t *dip) 254 { 255 int rc, id, *reg; 256 uint_t n, pf; 257 258 id = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 259 "device-id", 0xffff); 260 if (id == 0xffff) 261 return (DDI_PROBE_DONTCARE); 262 263 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 264 "reg", ®, &n); 265 if (rc != DDI_SUCCESS) 266 return (DDI_PROBE_DONTCARE); 267 268 pf = PCI_REG_FUNC_G(reg[0]); 269 ddi_prop_free(reg); 270 271 /* Prevent driver attachment on any PF except 0 on the FPGA */ 272 if (id == 0xa000 && pf != 0) 273 return (DDI_PROBE_FAILURE); 274 275 return (DDI_PROBE_DONTCARE); 276 } 277 278 static int 279 t4_devo_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 280 { 281 struct adapter *sc = NULL; 282 struct sge *s; 283 int i, instance, rc = DDI_SUCCESS, rqidx, tqidx, q; 284 int irq = 0, nxg = 0, n1g = 0; 285 char name[16]; 286 struct driver_properties *prp; 287 struct intrs_and_queues iaq; 288 ddi_device_acc_attr_t da = { 289 .devacc_attr_version = DDI_DEVICE_ATTR_V0, 290 .devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC, 291 .devacc_attr_dataorder = DDI_STRICTORDER_ACC 292 }; 293 ddi_device_acc_attr_t da1 = { 294 .devacc_attr_version = DDI_DEVICE_ATTR_V0, 295 .devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC, 296 .devacc_attr_dataorder = DDI_STRICTORDER_ACC 297 }; 298 299 if (cmd != DDI_ATTACH) 300 return (DDI_FAILURE); 301 302 /* 303 * Allocate space for soft state. 304 */ 305 instance = ddi_get_instance(dip); 306 rc = ddi_soft_state_zalloc(t4_list, instance); 307 if (rc != DDI_SUCCESS) { 308 cxgb_printf(dip, CE_WARN, 309 "failed to allocate soft state: %d", rc); 310 return (DDI_FAILURE); 311 } 312 313 sc = ddi_get_soft_state(t4_list, instance); 314 sc->dip = dip; 315 sc->dev = makedevice(ddi_driver_major(dip), instance); 316 mutex_init(&sc->lock, NULL, MUTEX_DRIVER, NULL); 317 cv_init(&sc->cv, NULL, CV_DRIVER, NULL); 318 mutex_init(&sc->sfl_lock, NULL, MUTEX_DRIVER, NULL); 319 TAILQ_INIT(&sc->sfl); 320 mutex_init(&sc->mbox_lock, NULL, MUTEX_DRIVER, NULL); 321 STAILQ_INIT(&sc->mbox_list); 322 323 mutex_enter(&t4_adapter_list_lock); 324 SLIST_INSERT_HEAD(&t4_adapter_list, sc, link); 325 mutex_exit(&t4_adapter_list_lock); 326 327 sc->pf = getpf(sc); 328 if (sc->pf > 8) { 329 rc = EINVAL; 330 cxgb_printf(dip, CE_WARN, 331 "failed to determine PCI PF# of device"); 332 goto done; 333 } 334 sc->mbox = sc->pf; 335 336 /* Initialize the driver properties */ 337 prp = &sc->props; 338 (void) init_driver_props(sc, prp); 339 340 /* 341 * Enable access to the PCI config space. 342 */ 343 rc = pci_config_setup(dip, &sc->pci_regh); 344 if (rc != DDI_SUCCESS) { 345 cxgb_printf(dip, CE_WARN, 346 "failed to enable PCI config space access: %d", rc); 347 goto done; 348 } 349 350 /* TODO: Set max read request to 4K */ 351 352 /* 353 * Enable MMIO access. 354 */ 355 rc = ddi_regs_map_setup(dip, 1, &sc->regp, 0, 0, &da, &sc->regh); 356 if (rc != DDI_SUCCESS) { 357 cxgb_printf(dip, CE_WARN, 358 "failed to map device registers: %d", rc); 359 goto done; 360 } 361 362 (void) memset(sc->chan_map, 0xff, sizeof (sc->chan_map)); 363 364 for (i = 0; i < NCHAN; i++) { 365 (void) snprintf(name, sizeof (name), "%s-%d", "reclaim", i); 366 sc->tq[i] = ddi_taskq_create(sc->dip, name, 1, 367 TASKQ_DEFAULTPRI, 0); 368 369 if (sc->tq[i] == NULL) { 370 cxgb_printf(dip, CE_WARN, "failed to create taskqs"); 371 rc = DDI_FAILURE; 372 goto done; 373 } 374 } 375 376 /* 377 * Prepare the adapter for operation. 378 */ 379 rc = -t4_prep_adapter(sc, false); 380 if (rc != 0) { 381 cxgb_printf(dip, CE_WARN, "failed to prepare adapter: %d", rc); 382 goto done; 383 } 384 385 /* 386 * Enable BAR1 access. 387 */ 388 sc->doorbells |= DOORBELL_KDB; 389 rc = ddi_regs_map_setup(dip, 2, &sc->reg1p, 0, 0, &da1, &sc->reg1h); 390 if (rc != DDI_SUCCESS) { 391 cxgb_printf(dip, CE_WARN, 392 "failed to map BAR1 device registers: %d", rc); 393 goto done; 394 } else { 395 if (is_t5(sc->params.chip)) { 396 sc->doorbells |= DOORBELL_UDB; 397 if (prp->wc) { 398 /* 399 * Enable write combining on BAR2. This is the 400 * userspace doorbell BAR and is split into 128B 401 * (UDBS_SEG_SIZE) doorbell regions, each 402 * associated with an egress queue. The first 403 * 64B has the doorbell and the second 64B can 404 * be used to submit a tx work request with an 405 * implicit doorbell. 406 */ 407 sc->doorbells &= ~DOORBELL_UDB; 408 sc->doorbells |= (DOORBELL_WCWR | 409 DOORBELL_UDBWC); 410 t4_write_reg(sc, A_SGE_STAT_CFG, 411 V_STATSOURCE_T5(7) | V_STATMODE(0)); 412 } 413 } 414 } 415 416 /* 417 * Do this really early. Note that minor number = instance. 418 */ 419 (void) snprintf(name, sizeof (name), "%s,%d", T4_NEXUS_NAME, instance); 420 rc = ddi_create_minor_node(dip, name, S_IFCHR, instance, 421 DDI_NT_NEXUS, 0); 422 if (rc != DDI_SUCCESS) { 423 cxgb_printf(dip, CE_WARN, 424 "failed to create device node: %d", rc); 425 rc = DDI_SUCCESS; /* carry on */ 426 } 427 428 /* Do this early. Memory window is required for loading config file. */ 429 setup_memwin(sc); 430 431 /* Prepare the firmware for operation */ 432 rc = prep_firmware(sc); 433 if (rc != 0) 434 goto done; /* error message displayed already */ 435 436 rc = adap__pre_init_tweaks(sc); 437 if (rc != 0) 438 goto done; 439 440 rc = get_params__pre_init(sc); 441 if (rc != 0) 442 goto done; /* error message displayed already */ 443 444 t4_sge_init(sc); 445 446 if (sc->flags & TAF_MASTER_PF) { 447 /* get basic stuff going */ 448 rc = -t4_fw_initialize(sc, sc->mbox); 449 if (rc != 0) { 450 cxgb_printf(sc->dip, CE_WARN, 451 "early init failed: %d.\n", rc); 452 goto done; 453 } 454 } 455 456 rc = get_params__post_init(sc); 457 if (rc != 0) 458 goto done; /* error message displayed already */ 459 460 rc = set_params__post_init(sc); 461 if (rc != 0) 462 goto done; /* error message displayed already */ 463 464 /* 465 * TODO: This is the place to call t4_set_filter_mode() 466 */ 467 468 /* tweak some settings */ 469 t4_write_reg(sc, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) | V_RXTSHIFTMAXR1(4) | 470 V_RXTSHIFTMAXR2(15) | V_PERSHIFTBACKOFFMAX(8) | V_PERSHIFTMAX(8) | 471 V_KEEPALIVEMAXR1(4) | V_KEEPALIVEMAXR2(9)); 472 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); 473 474 /* 475 * Work-around for bug 2619 476 * Set DisableVlan field in TP_RSS_CONFIG_VRT register so that the 477 * VLAN tag extraction is disabled. 478 */ 479 t4_set_reg_field(sc, A_TP_RSS_CONFIG_VRT, F_DISABLEVLAN, F_DISABLEVLAN); 480 481 /* Store filter mode */ 482 t4_read_indirect(sc, A_TP_PIO_ADDR, A_TP_PIO_DATA, &sc->filter_mode, 1, 483 A_TP_VLAN_PRI_MAP); 484 485 /* 486 * First pass over all the ports - allocate VIs and initialize some 487 * basic parameters like mac address, port type, etc. We also figure 488 * out whether a port is 10G or 1G and use that information when 489 * calculating how many interrupts to attempt to allocate. 490 */ 491 for_each_port(sc, i) { 492 struct port_info *pi; 493 494 pi = kmem_zalloc(sizeof (*pi), KM_SLEEP); 495 sc->port[i] = pi; 496 497 /* These must be set before t4_port_init */ 498 pi->adapter = sc; 499 /* LINTED: E_ASSIGN_NARROW_CONV */ 500 pi->port_id = i; 501 } 502 503 /* Allocate the vi and initialize parameters like mac addr */ 504 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0); 505 if (rc) { 506 cxgb_printf(dip, CE_WARN, "unable to initialize port: %d", rc); 507 goto done; 508 } 509 510 for_each_port(sc, i) { 511 struct port_info *pi = sc->port[i]; 512 513 mutex_init(&pi->lock, NULL, MUTEX_DRIVER, NULL); 514 pi->mtu = ETHERMTU; 515 516 if (is_10XG_port(pi)) { 517 nxg++; 518 pi->tmr_idx = prp->tmr_idx_10g; 519 pi->pktc_idx = prp->pktc_idx_10g; 520 } else { 521 n1g++; 522 pi->tmr_idx = prp->tmr_idx_1g; 523 pi->pktc_idx = prp->pktc_idx_1g; 524 } 525 526 pi->xact_addr_filt = -1; 527 t4_mc_init(pi); 528 529 setbit(&sc->registered_device_map, i); 530 } 531 532 (void) remove_extra_props(sc, nxg, n1g); 533 534 if (sc->registered_device_map == 0) { 535 cxgb_printf(dip, CE_WARN, "no usable ports"); 536 rc = DDI_FAILURE; 537 goto done; 538 } 539 540 rc = cfg_itype_and_nqueues(sc, nxg, n1g, &iaq); 541 if (rc != 0) 542 goto done; /* error message displayed already */ 543 544 sc->intr_type = iaq.intr_type; 545 sc->intr_count = iaq.nirq; 546 547 if (sc->props.multi_rings && (sc->intr_type != DDI_INTR_TYPE_MSIX)) { 548 sc->props.multi_rings = 0; 549 cxgb_printf(dip, CE_WARN, 550 "Multiple rings disabled as interrupt type is not MSI-X"); 551 } 552 553 if (sc->props.multi_rings && iaq.intr_fwd) { 554 sc->props.multi_rings = 0; 555 cxgb_printf(dip, CE_WARN, 556 "Multiple rings disabled as interrupts are forwarded"); 557 } 558 559 if (!sc->props.multi_rings) { 560 iaq.ntxq10g = 1; 561 iaq.ntxq1g = 1; 562 } 563 s = &sc->sge; 564 s->nrxq = nxg * iaq.nrxq10g + n1g * iaq.nrxq1g; 565 s->ntxq = nxg * iaq.ntxq10g + n1g * iaq.ntxq1g; 566 s->neq = s->ntxq + s->nrxq; /* the fl in an rxq is an eq */ 567 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 568 if (iaq.intr_fwd != 0) 569 sc->flags |= TAF_INTR_FWD; 570 s->rxq = kmem_zalloc(s->nrxq * sizeof (struct sge_rxq), KM_SLEEP); 571 s->txq = kmem_zalloc(s->ntxq * sizeof (struct sge_txq), KM_SLEEP); 572 s->iqmap = 573 kmem_zalloc(s->iqmap_sz * sizeof (struct sge_iq *), KM_SLEEP); 574 s->eqmap = 575 kmem_zalloc(s->eqmap_sz * sizeof (struct sge_eq *), KM_SLEEP); 576 577 sc->intr_handle = 578 kmem_zalloc(sc->intr_count * sizeof (ddi_intr_handle_t), KM_SLEEP); 579 580 /* 581 * Second pass over the ports. This time we know the number of rx and 582 * tx queues that each port should get. 583 */ 584 rqidx = tqidx = 0; 585 for_each_port(sc, i) { 586 struct port_info *pi = sc->port[i]; 587 588 if (pi == NULL) 589 continue; 590 591 t4_mc_cb_init(pi); 592 /* LINTED: E_ASSIGN_NARROW_CONV */ 593 pi->first_rxq = rqidx; 594 /* LINTED: E_ASSIGN_NARROW_CONV */ 595 pi->nrxq = (is_10XG_port(pi)) ? iaq.nrxq10g 596 : iaq.nrxq1g; 597 /* LINTED: E_ASSIGN_NARROW_CONV */ 598 pi->first_txq = tqidx; 599 /* LINTED: E_ASSIGN_NARROW_CONV */ 600 pi->ntxq = (is_10XG_port(pi)) ? iaq.ntxq10g 601 : iaq.ntxq1g; 602 603 rqidx += pi->nrxq; 604 tqidx += pi->ntxq; 605 606 /* 607 * Enable hw checksumming and LSO for all ports by default. 608 * They can be disabled using ndd (hw_csum and hw_lso). 609 */ 610 pi->features |= (CXGBE_HW_CSUM | CXGBE_HW_LSO); 611 } 612 613 /* 614 * Setup Interrupts. 615 */ 616 617 i = 0; 618 rc = ddi_intr_alloc(dip, sc->intr_handle, sc->intr_type, 0, 619 sc->intr_count, &i, DDI_INTR_ALLOC_STRICT); 620 if (rc != DDI_SUCCESS) { 621 cxgb_printf(dip, CE_WARN, 622 "failed to allocate %d interrupt(s) of type %d: %d, %d", 623 sc->intr_count, sc->intr_type, rc, i); 624 goto done; 625 } 626 ASSERT(sc->intr_count == i); /* allocation was STRICT */ 627 (void) ddi_intr_get_cap(sc->intr_handle[0], &sc->intr_cap); 628 (void) ddi_intr_get_pri(sc->intr_handle[0], &sc->intr_pri); 629 if (sc->intr_count == 1) { 630 ASSERT(sc->flags & TAF_INTR_FWD); 631 (void) ddi_intr_add_handler(sc->intr_handle[0], t4_intr_all, sc, 632 &s->fwq); 633 } else { 634 /* Multiple interrupts. The first one is always error intr */ 635 (void) ddi_intr_add_handler(sc->intr_handle[0], t4_intr_err, sc, 636 NULL); 637 irq++; 638 639 /* The second one is always the firmware event queue */ 640 (void) ddi_intr_add_handler(sc->intr_handle[1], t4_intr, sc, 641 &s->fwq); 642 irq++; 643 /* 644 * Note that if TAF_INTR_FWD is set then either the NIC rx 645 * queues or (exclusive or) the TOE rx queueus will be taking 646 * direct interrupts. 647 * 648 * There is no need to check for is_offload(sc) as nofldrxq 649 * will be 0 if offload is disabled. 650 */ 651 for_each_port(sc, i) { 652 struct port_info *pi = sc->port[i]; 653 struct sge_rxq *rxq; 654 rxq = &s->rxq[pi->first_rxq]; 655 for (q = 0; q < pi->nrxq; q++, rxq++) { 656 (void) ddi_intr_add_handler( 657 sc->intr_handle[irq], t4_intr, sc, 658 &rxq->iq); 659 irq++; 660 } 661 } 662 663 } 664 sc->flags |= TAF_INTR_ALLOC; 665 666 if ((rc = ksensor_create_scalar_pcidev(dip, SENSOR_KIND_TEMPERATURE, 667 &t4_temp_ops, sc, "temp", &sc->temp_sensor)) != 0) { 668 cxgb_printf(dip, CE_WARN, "failed to create temperature " 669 "sensor: %d", rc); 670 rc = DDI_FAILURE; 671 goto done; 672 } 673 674 if ((rc = ksensor_create_scalar_pcidev(dip, SENSOR_KIND_VOLTAGE, 675 &t4_volt_ops, sc, "vdd", &sc->volt_sensor)) != 0) { 676 cxgb_printf(dip, CE_WARN, "failed to create voltage " 677 "sensor: %d", rc); 678 rc = DDI_FAILURE; 679 goto done; 680 } 681 682 683 if ((rc = ddi_ufm_init(dip, DDI_UFM_CURRENT_VERSION, &t4_ufm_ops, 684 &sc->ufm_hdl, sc)) != 0) { 685 cxgb_printf(dip, CE_WARN, "failed to enable UFM ops: %d", rc); 686 rc = DDI_FAILURE; 687 goto done; 688 } 689 ddi_ufm_update(sc->ufm_hdl); 690 ddi_report_dev(dip); 691 692 /* 693 * Hardware/Firmware/etc. Version/Revision IDs. 694 */ 695 t4_dump_version_info(sc); 696 697 cxgb_printf(dip, CE_NOTE, "(%d rxq, %d txq total) %d %s.", 698 rqidx, tqidx, sc->intr_count, 699 sc->intr_type == DDI_INTR_TYPE_MSIX ? "MSI-X interrupts" : 700 sc->intr_type == DDI_INTR_TYPE_MSI ? "MSI interrupts" : 701 "fixed interrupt"); 702 703 sc->ksp = setup_kstats(sc); 704 sc->ksp_stat = setup_wc_kstats(sc); 705 sc->params.drv_memwin = MEMWIN_NIC; 706 707 done: 708 if (rc != DDI_SUCCESS) { 709 (void) t4_devo_detach(dip, DDI_DETACH); 710 711 /* rc may have errno style errors or DDI errors */ 712 rc = DDI_FAILURE; 713 } 714 715 return (rc); 716 } 717 718 static int 719 t4_devo_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 720 { 721 int instance, i; 722 struct adapter *sc; 723 struct port_info *pi; 724 struct sge *s; 725 726 if (cmd != DDI_DETACH) 727 return (DDI_FAILURE); 728 729 instance = ddi_get_instance(dip); 730 sc = ddi_get_soft_state(t4_list, instance); 731 if (sc == NULL) 732 return (DDI_SUCCESS); 733 734 if (sc->flags & TAF_INIT_DONE) { 735 t4_intr_disable(sc); 736 for_each_port(sc, i) { 737 pi = sc->port[i]; 738 if (pi && pi->flags & TPF_INIT_DONE) 739 (void) port_full_uninit(pi); 740 } 741 (void) adapter_full_uninit(sc); 742 } 743 744 /* Safe to call no matter what */ 745 if (sc->ufm_hdl != NULL) { 746 ddi_ufm_fini(sc->ufm_hdl); 747 sc->ufm_hdl = NULL; 748 } 749 (void) ksensor_remove(dip, KSENSOR_ALL_IDS); 750 ddi_prop_remove_all(dip); 751 ddi_remove_minor_node(dip, NULL); 752 753 for (i = 0; i < NCHAN; i++) { 754 if (sc->tq[i]) { 755 ddi_taskq_wait(sc->tq[i]); 756 ddi_taskq_destroy(sc->tq[i]); 757 } 758 } 759 760 if (sc->ksp != NULL) 761 kstat_delete(sc->ksp); 762 if (sc->ksp_stat != NULL) 763 kstat_delete(sc->ksp_stat); 764 765 s = &sc->sge; 766 if (s->rxq != NULL) 767 kmem_free(s->rxq, s->nrxq * sizeof (struct sge_rxq)); 768 if (s->txq != NULL) 769 kmem_free(s->txq, s->ntxq * sizeof (struct sge_txq)); 770 if (s->iqmap != NULL) 771 kmem_free(s->iqmap, s->iqmap_sz * sizeof (struct sge_iq *)); 772 if (s->eqmap != NULL) 773 kmem_free(s->eqmap, s->eqmap_sz * sizeof (struct sge_eq *)); 774 775 if (s->rxbuf_cache != NULL) 776 kmem_cache_destroy(s->rxbuf_cache); 777 778 if (sc->flags & TAF_INTR_ALLOC) { 779 for (i = 0; i < sc->intr_count; i++) { 780 (void) ddi_intr_remove_handler(sc->intr_handle[i]); 781 (void) ddi_intr_free(sc->intr_handle[i]); 782 } 783 sc->flags &= ~TAF_INTR_ALLOC; 784 } 785 786 if (sc->intr_handle != NULL) { 787 kmem_free(sc->intr_handle, 788 sc->intr_count * sizeof (*sc->intr_handle)); 789 } 790 791 for_each_port(sc, i) { 792 pi = sc->port[i]; 793 if (pi != NULL) { 794 mutex_destroy(&pi->lock); 795 kmem_free(pi, sizeof (*pi)); 796 clrbit(&sc->registered_device_map, i); 797 } 798 } 799 800 if (sc->flags & FW_OK) 801 (void) t4_fw_bye(sc, sc->mbox); 802 803 if (sc->reg1h != NULL) 804 ddi_regs_map_free(&sc->reg1h); 805 806 if (sc->regh != NULL) 807 ddi_regs_map_free(&sc->regh); 808 809 if (sc->pci_regh != NULL) 810 pci_config_teardown(&sc->pci_regh); 811 812 mutex_enter(&t4_adapter_list_lock); 813 SLIST_REMOVE(&t4_adapter_list, sc, adapter, link); 814 mutex_exit(&t4_adapter_list_lock); 815 816 mutex_destroy(&sc->mbox_lock); 817 mutex_destroy(&sc->lock); 818 cv_destroy(&sc->cv); 819 mutex_destroy(&sc->sfl_lock); 820 821 #ifdef DEBUG 822 bzero(sc, sizeof (*sc)); 823 #endif 824 ddi_soft_state_free(t4_list, instance); 825 826 return (DDI_SUCCESS); 827 } 828 829 static int 830 t4_devo_quiesce(dev_info_t *dip) 831 { 832 int instance; 833 struct adapter *sc; 834 835 instance = ddi_get_instance(dip); 836 sc = ddi_get_soft_state(t4_list, instance); 837 if (sc == NULL) 838 return (DDI_SUCCESS); 839 840 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 841 t4_intr_disable(sc); 842 t4_write_reg(sc, A_PL_RST, F_PIORSTMODE | F_PIORST); 843 844 return (DDI_SUCCESS); 845 } 846 847 static int 848 t4_bus_ctl(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t op, void *arg, 849 void *result) 850 { 851 char s[4]; 852 struct port_info *pi; 853 dev_info_t *child = (dev_info_t *)arg; 854 855 switch (op) { 856 case DDI_CTLOPS_REPORTDEV: 857 pi = ddi_get_parent_data(rdip); 858 pi->instance = ddi_get_instance(dip); 859 pi->child_inst = ddi_get_instance(rdip); 860 return (DDI_SUCCESS); 861 862 case DDI_CTLOPS_INITCHILD: 863 pi = ddi_get_parent_data(child); 864 if (pi == NULL) 865 return (DDI_NOT_WELL_FORMED); 866 (void) snprintf(s, sizeof (s), "%d", pi->port_id); 867 ddi_set_name_addr(child, s); 868 return (DDI_SUCCESS); 869 870 case DDI_CTLOPS_UNINITCHILD: 871 ddi_set_name_addr(child, NULL); 872 return (DDI_SUCCESS); 873 874 case DDI_CTLOPS_ATTACH: 875 case DDI_CTLOPS_DETACH: 876 return (DDI_SUCCESS); 877 878 default: 879 return (ddi_ctlops(dip, rdip, op, arg, result)); 880 } 881 } 882 883 static int 884 t4_bus_config(dev_info_t *dip, uint_t flags, ddi_bus_config_op_t op, void *arg, 885 dev_info_t **cdipp) 886 { 887 int instance, i; 888 struct adapter *sc; 889 890 instance = ddi_get_instance(dip); 891 sc = ddi_get_soft_state(t4_list, instance); 892 893 if (op == BUS_CONFIG_ONE) { 894 char *c; 895 896 /* 897 * arg is something like "cxgb@0" where 0 is the port_id hanging 898 * off this nexus. 899 */ 900 901 c = arg; 902 while (*(c + 1)) 903 c++; 904 905 /* There should be exactly 1 digit after '@' */ 906 if (*(c - 1) != '@') 907 return (NDI_FAILURE); 908 909 i = *c - '0'; 910 911 if (add_child_node(sc, i) != 0) 912 return (NDI_FAILURE); 913 914 flags |= NDI_ONLINE_ATTACH; 915 916 } else if (op == BUS_CONFIG_ALL || op == BUS_CONFIG_DRIVER) { 917 /* Allocate and bind all child device nodes */ 918 for_each_port(sc, i) 919 (void) add_child_node(sc, i); 920 flags |= NDI_ONLINE_ATTACH; 921 } 922 923 return (ndi_busop_bus_config(dip, flags, op, arg, cdipp, 0)); 924 } 925 926 static int 927 t4_bus_unconfig(dev_info_t *dip, uint_t flags, ddi_bus_config_op_t op, 928 void *arg) 929 { 930 int instance, i, rc; 931 struct adapter *sc; 932 933 instance = ddi_get_instance(dip); 934 sc = ddi_get_soft_state(t4_list, instance); 935 936 if (op == BUS_CONFIG_ONE || op == BUS_UNCONFIG_ALL || 937 op == BUS_UNCONFIG_DRIVER) 938 flags |= NDI_UNCONFIG; 939 940 rc = ndi_busop_bus_unconfig(dip, flags, op, arg); 941 if (rc != 0) 942 return (rc); 943 944 if (op == BUS_UNCONFIG_ONE) { 945 char *c; 946 947 c = arg; 948 while (*(c + 1)) 949 c++; 950 951 if (*(c - 1) != '@') 952 return (NDI_SUCCESS); 953 954 i = *c - '0'; 955 956 rc = remove_child_node(sc, i); 957 958 } else if (op == BUS_UNCONFIG_ALL || op == BUS_UNCONFIG_DRIVER) { 959 960 for_each_port(sc, i) 961 (void) remove_child_node(sc, i); 962 } 963 964 return (rc); 965 } 966 967 /* ARGSUSED */ 968 static int 969 t4_cb_open(dev_t *devp, int flag, int otyp, cred_t *credp) 970 { 971 struct adapter *sc; 972 973 if (otyp != OTYP_CHR) 974 return (EINVAL); 975 976 sc = ddi_get_soft_state(t4_list, getminor(*devp)); 977 if (sc == NULL) 978 return (ENXIO); 979 980 return (atomic_cas_uint(&sc->open, 0, EBUSY)); 981 } 982 983 /* ARGSUSED */ 984 static int 985 t4_cb_close(dev_t dev, int flag, int otyp, cred_t *credp) 986 { 987 struct adapter *sc; 988 989 sc = ddi_get_soft_state(t4_list, getminor(dev)); 990 if (sc == NULL) 991 return (EINVAL); 992 993 (void) atomic_swap_uint(&sc->open, 0); 994 return (0); 995 } 996 997 /* ARGSUSED */ 998 static int 999 t4_cb_ioctl(dev_t dev, int cmd, intptr_t d, int mode, cred_t *credp, int *rp) 1000 { 1001 int instance; 1002 struct adapter *sc; 1003 void *data = (void *)d; 1004 1005 if (crgetuid(credp) != 0) 1006 return (EPERM); 1007 1008 instance = getminor(dev); 1009 sc = ddi_get_soft_state(t4_list, instance); 1010 if (sc == NULL) 1011 return (EINVAL); 1012 1013 return (t4_ioctl(sc, cmd, data, mode)); 1014 } 1015 1016 static unsigned int 1017 getpf(struct adapter *sc) 1018 { 1019 int rc, *data; 1020 uint_t n, pf; 1021 1022 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, sc->dip, 1023 DDI_PROP_DONTPASS, "reg", &data, &n); 1024 if (rc != DDI_SUCCESS) { 1025 cxgb_printf(sc->dip, CE_WARN, 1026 "failed to lookup \"reg\" property: %d", rc); 1027 return (0xff); 1028 } 1029 1030 pf = PCI_REG_FUNC_G(data[0]); 1031 ddi_prop_free(data); 1032 1033 return (pf); 1034 } 1035 1036 /* 1037 * Install a compatible firmware (if required), establish contact with it, 1038 * become the master, and reset the device. 1039 */ 1040 static int 1041 prep_firmware(struct adapter *sc) 1042 { 1043 int rc; 1044 size_t fw_size; 1045 int reset = 1; 1046 enum dev_state state; 1047 unsigned char *fw_data; 1048 struct fw_hdr *card_fw, *hdr; 1049 const char *fw_file = NULL; 1050 firmware_handle_t fw_hdl; 1051 struct fw_info fi, *fw_info = &fi; 1052 1053 struct driver_properties *p = &sc->props; 1054 1055 /* Contact firmware, request master */ 1056 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MUST, &state); 1057 if (rc < 0) { 1058 rc = -rc; 1059 cxgb_printf(sc->dip, CE_WARN, 1060 "failed to connect to the firmware: %d.", rc); 1061 return (rc); 1062 } 1063 1064 if (rc == sc->mbox) 1065 sc->flags |= TAF_MASTER_PF; 1066 1067 /* We may need FW version info for later reporting */ 1068 t4_get_version_info(sc); 1069 1070 switch (CHELSIO_CHIP_VERSION(sc->params.chip)) { 1071 case CHELSIO_T4: 1072 fw_file = "t4fw.bin"; 1073 break; 1074 case CHELSIO_T5: 1075 fw_file = "t5fw.bin"; 1076 break; 1077 case CHELSIO_T6: 1078 fw_file = "t6fw.bin"; 1079 break; 1080 default: 1081 cxgb_printf(sc->dip, CE_WARN, "Adapter type not supported\n"); 1082 return (EINVAL); 1083 } 1084 1085 if (firmware_open(T4_PORT_NAME, fw_file, &fw_hdl) != 0) { 1086 cxgb_printf(sc->dip, CE_WARN, "Could not open %s\n", fw_file); 1087 return (EINVAL); 1088 } 1089 1090 fw_size = firmware_get_size(fw_hdl); 1091 1092 if (fw_size < sizeof (struct fw_hdr)) { 1093 cxgb_printf(sc->dip, CE_WARN, "%s is too small (%ld bytes)\n", 1094 fw_file, fw_size); 1095 firmware_close(fw_hdl); 1096 return (EINVAL); 1097 } 1098 1099 if (fw_size > FLASH_FW_MAX_SIZE) { 1100 cxgb_printf(sc->dip, CE_WARN, 1101 "%s is too large (%ld bytes, max allowed is %ld)\n", 1102 fw_file, fw_size, FLASH_FW_MAX_SIZE); 1103 firmware_close(fw_hdl); 1104 return (EFBIG); 1105 } 1106 1107 fw_data = kmem_zalloc(fw_size, KM_SLEEP); 1108 if (firmware_read(fw_hdl, 0, fw_data, fw_size) != 0) { 1109 cxgb_printf(sc->dip, CE_WARN, "Failed to read from %s\n", 1110 fw_file); 1111 firmware_close(fw_hdl); 1112 kmem_free(fw_data, fw_size); 1113 return (EINVAL); 1114 } 1115 firmware_close(fw_hdl); 1116 1117 bzero(fw_info, sizeof (*fw_info)); 1118 fw_info->chip = CHELSIO_CHIP_VERSION(sc->params.chip); 1119 1120 hdr = (struct fw_hdr *)fw_data; 1121 fw_info->fw_hdr.fw_ver = hdr->fw_ver; 1122 fw_info->fw_hdr.chip = hdr->chip; 1123 fw_info->fw_hdr.intfver_nic = hdr->intfver_nic; 1124 fw_info->fw_hdr.intfver_vnic = hdr->intfver_vnic; 1125 fw_info->fw_hdr.intfver_ofld = hdr->intfver_ofld; 1126 fw_info->fw_hdr.intfver_ri = hdr->intfver_ri; 1127 fw_info->fw_hdr.intfver_iscsipdu = hdr->intfver_iscsipdu; 1128 fw_info->fw_hdr.intfver_iscsi = hdr->intfver_iscsi; 1129 fw_info->fw_hdr.intfver_fcoepdu = hdr->intfver_fcoepdu; 1130 fw_info->fw_hdr.intfver_fcoe = hdr->intfver_fcoe; 1131 1132 /* allocate memory to read the header of the firmware on the card */ 1133 card_fw = kmem_zalloc(sizeof (*card_fw), KM_SLEEP); 1134 1135 rc = -t4_prep_fw(sc, fw_info, fw_data, fw_size, card_fw, 1136 p->t4_fw_install, state, &reset); 1137 1138 kmem_free(card_fw, sizeof (*card_fw)); 1139 kmem_free(fw_data, fw_size); 1140 1141 if (rc != 0) { 1142 cxgb_printf(sc->dip, CE_WARN, 1143 "failed to install firmware: %d", rc); 1144 return (rc); 1145 } else { 1146 /* refresh */ 1147 (void) t4_check_fw_version(sc); 1148 } 1149 1150 /* Reset device */ 1151 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 1152 if (rc != 0) { 1153 cxgb_printf(sc->dip, CE_WARN, 1154 "firmware reset failed: %d.", rc); 1155 if (rc != ETIMEDOUT && rc != EIO) 1156 (void) t4_fw_bye(sc, sc->mbox); 1157 return (rc); 1158 } 1159 1160 /* Partition adapter resources as specified in the config file. */ 1161 if (sc->flags & TAF_MASTER_PF) { 1162 /* Handle default vs special T4 config file */ 1163 1164 rc = partition_resources(sc); 1165 if (rc != 0) 1166 goto err; /* error message displayed already */ 1167 } 1168 1169 sc->flags |= FW_OK; 1170 return (0); 1171 err: 1172 return (rc); 1173 1174 } 1175 1176 static const struct memwin t4_memwin[] = { 1177 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 1178 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 1179 { MEMWIN2_BASE, MEMWIN2_APERTURE } 1180 }; 1181 1182 static const struct memwin t5_memwin[] = { 1183 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 1184 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 1185 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 1186 }; 1187 1188 #define FW_PARAM_DEV(param) \ 1189 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 1190 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 1191 #define FW_PARAM_PFVF(param) \ 1192 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 1193 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 1194 1195 /* 1196 * Verify that the memory range specified by the memtype/offset/len pair is 1197 * valid and lies entirely within the memtype specified. The global address of 1198 * the start of the range is returned in addr. 1199 */ 1200 int 1201 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len, 1202 uint32_t *addr) 1203 { 1204 uint32_t em, addr_len, maddr, mlen; 1205 1206 /* Memory can only be accessed in naturally aligned 4 byte units */ 1207 if (off & 3 || len & 3 || len == 0) 1208 return (EINVAL); 1209 1210 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 1211 switch (mtype) { 1212 case MEM_EDC0: 1213 if (!(em & F_EDRAM0_ENABLE)) 1214 return (EINVAL); 1215 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 1216 maddr = G_EDRAM0_BASE(addr_len) << 20; 1217 mlen = G_EDRAM0_SIZE(addr_len) << 20; 1218 break; 1219 case MEM_EDC1: 1220 if (!(em & F_EDRAM1_ENABLE)) 1221 return (EINVAL); 1222 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 1223 maddr = G_EDRAM1_BASE(addr_len) << 20; 1224 mlen = G_EDRAM1_SIZE(addr_len) << 20; 1225 break; 1226 case MEM_MC: 1227 if (!(em & F_EXT_MEM_ENABLE)) 1228 return (EINVAL); 1229 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 1230 maddr = G_EXT_MEM_BASE(addr_len) << 20; 1231 mlen = G_EXT_MEM_SIZE(addr_len) << 20; 1232 break; 1233 case MEM_MC1: 1234 if (is_t4(sc->params.chip) || !(em & F_EXT_MEM1_ENABLE)) 1235 return (EINVAL); 1236 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 1237 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 1238 mlen = G_EXT_MEM1_SIZE(addr_len) << 20; 1239 break; 1240 default: 1241 return (EINVAL); 1242 } 1243 1244 if (mlen > 0 && off < mlen && off + len <= mlen) { 1245 *addr = maddr + off; /* global address */ 1246 return (0); 1247 } 1248 1249 return (EFAULT); 1250 } 1251 1252 void 1253 memwin_info(struct adapter *sc, int win, uint32_t *base, uint32_t *aperture) 1254 { 1255 const struct memwin *mw; 1256 1257 if (is_t4(sc->params.chip)) { 1258 mw = &t4_memwin[win]; 1259 } else { 1260 mw = &t5_memwin[win]; 1261 } 1262 1263 if (base != NULL) 1264 *base = mw->base; 1265 if (aperture != NULL) 1266 *aperture = mw->aperture; 1267 } 1268 1269 /* 1270 * Upload configuration file to card's memory. 1271 */ 1272 static int 1273 upload_config_file(struct adapter *sc, uint32_t *mt, uint32_t *ma) 1274 { 1275 int rc = 0; 1276 size_t cflen, cfbaselen; 1277 uint_t i, n; 1278 uint32_t param, val, addr, mtype, maddr; 1279 uint32_t off, mw_base, mw_aperture; 1280 uint32_t *cfdata, *cfbase; 1281 firmware_handle_t fw_hdl; 1282 const char *cfg_file = NULL; 1283 1284 /* Figure out where the firmware wants us to upload it. */ 1285 param = FW_PARAM_DEV(CF); 1286 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 1287 if (rc != 0) { 1288 /* Firmwares without config file support will fail this way */ 1289 cxgb_printf(sc->dip, CE_WARN, 1290 "failed to query config file location: %d.\n", rc); 1291 return (rc); 1292 } 1293 *mt = mtype = G_FW_PARAMS_PARAM_Y(val); 1294 *ma = maddr = G_FW_PARAMS_PARAM_Z(val) << 16; 1295 1296 switch (CHELSIO_CHIP_VERSION(sc->params.chip)) { 1297 case CHELSIO_T4: 1298 cfg_file = "t4fw_cfg.txt"; 1299 break; 1300 case CHELSIO_T5: 1301 cfg_file = "t5fw_cfg.txt"; 1302 break; 1303 case CHELSIO_T6: 1304 cfg_file = "t6fw_cfg.txt"; 1305 break; 1306 default: 1307 cxgb_printf(sc->dip, CE_WARN, "Invalid Adapter detected\n"); 1308 return (EINVAL); 1309 } 1310 1311 if (firmware_open(T4_PORT_NAME, cfg_file, &fw_hdl) != 0) { 1312 cxgb_printf(sc->dip, CE_WARN, "Could not open %s\n", cfg_file); 1313 return (EINVAL); 1314 } 1315 1316 cflen = firmware_get_size(fw_hdl); 1317 /* 1318 * Truncate the length to a multiple of uint32_ts. The configuration 1319 * text files have trailing comments (and hopefully always will) so 1320 * nothing important is lost. 1321 */ 1322 cflen &= ~3; 1323 1324 if (cflen > FLASH_CFG_MAX_SIZE) { 1325 cxgb_printf(sc->dip, CE_WARN, 1326 "config file too long (%d, max allowed is %d). ", 1327 cflen, FLASH_CFG_MAX_SIZE); 1328 firmware_close(fw_hdl); 1329 return (EFBIG); 1330 } 1331 1332 rc = validate_mt_off_len(sc, mtype, maddr, cflen, &addr); 1333 if (rc != 0) { 1334 cxgb_printf(sc->dip, CE_WARN, 1335 "%s: addr (%d/0x%x) or len %d is not valid: %d. " 1336 "Will try to use the config on the card, if any.\n", 1337 __func__, mtype, maddr, cflen, rc); 1338 firmware_close(fw_hdl); 1339 return (EFAULT); 1340 } 1341 1342 cfbaselen = cflen; 1343 cfbase = cfdata = kmem_zalloc(cflen, KM_SLEEP); 1344 if (firmware_read(fw_hdl, 0, cfdata, cflen) != 0) { 1345 cxgb_printf(sc->dip, CE_WARN, "Failed to read from %s\n", 1346 cfg_file); 1347 firmware_close(fw_hdl); 1348 kmem_free(cfbase, cfbaselen); 1349 return (EINVAL); 1350 } 1351 firmware_close(fw_hdl); 1352 1353 memwin_info(sc, 2, &mw_base, &mw_aperture); 1354 while (cflen) { 1355 off = position_memwin(sc, 2, addr); 1356 n = min(cflen, mw_aperture - off); 1357 for (i = 0; i < n; i += 4) 1358 t4_write_reg(sc, mw_base + off + i, *cfdata++); 1359 cflen -= n; 1360 addr += n; 1361 } 1362 1363 kmem_free(cfbase, cfbaselen); 1364 1365 return (rc); 1366 } 1367 1368 /* 1369 * Partition chip resources for use between various PFs, VFs, etc. This is done 1370 * by uploading the firmware configuration file to the adapter and instructing 1371 * the firmware to process it. 1372 */ 1373 static int 1374 partition_resources(struct adapter *sc) 1375 { 1376 int rc; 1377 struct fw_caps_config_cmd caps; 1378 uint32_t mtype, maddr, finicsum, cfcsum; 1379 1380 rc = upload_config_file(sc, &mtype, &maddr); 1381 if (rc != 0) { 1382 mtype = FW_MEMTYPE_CF_FLASH; 1383 maddr = t4_flash_cfg_addr(sc); 1384 } 1385 1386 bzero(&caps, sizeof (caps)); 1387 caps.op_to_write = BE_32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1388 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1389 caps.cfvalid_to_len16 = BE_32(F_FW_CAPS_CONFIG_CMD_CFVALID | 1390 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 1391 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) | FW_LEN16(caps)); 1392 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof (caps), &caps); 1393 if (rc != 0) { 1394 cxgb_printf(sc->dip, CE_WARN, 1395 "failed to pre-process config file: %d.\n", rc); 1396 return (rc); 1397 } 1398 1399 finicsum = ntohl(caps.finicsum); 1400 cfcsum = ntohl(caps.cfcsum); 1401 if (finicsum != cfcsum) { 1402 cxgb_printf(sc->dip, CE_WARN, 1403 "WARNING: config file checksum mismatch: %08x %08x\n", 1404 finicsum, cfcsum); 1405 } 1406 sc->cfcsum = cfcsum; 1407 1408 /* TODO: Need to configure this correctly */ 1409 caps.toecaps = htons(FW_CAPS_CONFIG_TOE); 1410 caps.iscsicaps = 0; 1411 caps.rdmacaps = 0; 1412 caps.fcoecaps = 0; 1413 /* TODO: Disable VNIC cap for now */ 1414 caps.niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM); 1415 1416 caps.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1417 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 1418 caps.cfvalid_to_len16 = htonl(FW_LEN16(caps)); 1419 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof (caps), NULL); 1420 if (rc != 0) { 1421 cxgb_printf(sc->dip, CE_WARN, 1422 "failed to process config file: %d.\n", rc); 1423 return (rc); 1424 } 1425 1426 return (0); 1427 } 1428 1429 /* 1430 * Tweak configuration based on module parameters, etc. Most of these have 1431 * defaults assigned to them by Firmware Configuration Files (if we're using 1432 * them) but need to be explicitly set if we're using hard-coded 1433 * initialization. But even in the case of using Firmware Configuration 1434 * Files, we'd like to expose the ability to change these via module 1435 * parameters so these are essentially common tweaks/settings for 1436 * Configuration Files and hard-coded initialization ... 1437 */ 1438 static int 1439 adap__pre_init_tweaks(struct adapter *sc) 1440 { 1441 int rx_dma_offset = 2; /* Offset of RX packets into DMA buffers */ 1442 1443 /* 1444 * Fix up various Host-Dependent Parameters like Page Size, Cache 1445 * Line Size, etc. The firmware default is for a 4KB Page Size and 1446 * 64B Cache Line Size ... 1447 */ 1448 (void) t4_fixup_host_params_compat(sc, PAGE_SIZE, _CACHE_LINE_SIZE, 1449 T5_LAST_REV); 1450 1451 t4_set_reg_field(sc, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT), 1452 V_PKTSHIFT(rx_dma_offset)); 1453 1454 return (0); 1455 } 1456 /* 1457 * Retrieve parameters that are needed (or nice to have) prior to calling 1458 * t4_sge_init and t4_fw_initialize. 1459 */ 1460 static int 1461 get_params__pre_init(struct adapter *sc) 1462 { 1463 int rc; 1464 uint32_t param[2], val[2]; 1465 struct fw_devlog_cmd cmd; 1466 struct devlog_params *dlog = &sc->params.devlog; 1467 1468 /* 1469 * Grab the raw VPD parameters. 1470 */ 1471 rc = -t4_get_raw_vpd_params(sc, &sc->params.vpd); 1472 if (rc != 0) { 1473 cxgb_printf(sc->dip, CE_WARN, 1474 "failed to query VPD parameters (pre_init): %d.\n", rc); 1475 return (rc); 1476 } 1477 1478 param[0] = FW_PARAM_DEV(PORTVEC); 1479 param[1] = FW_PARAM_DEV(CCLK); 1480 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 1481 if (rc != 0) { 1482 cxgb_printf(sc->dip, CE_WARN, 1483 "failed to query parameters (pre_init): %d.\n", rc); 1484 return (rc); 1485 } 1486 1487 sc->params.portvec = val[0]; 1488 sc->params.nports = 0; 1489 while (val[0]) { 1490 sc->params.nports++; 1491 val[0] &= val[0] - 1; 1492 } 1493 1494 sc->params.vpd.cclk = val[1]; 1495 1496 /* Read device log parameters. */ 1497 bzero(&cmd, sizeof (cmd)); 1498 cmd.op_to_write = htonl(V_FW_CMD_OP(FW_DEVLOG_CMD) | 1499 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1500 cmd.retval_len16 = htonl(FW_LEN16(cmd)); 1501 rc = -t4_wr_mbox(sc, sc->mbox, &cmd, sizeof (cmd), &cmd); 1502 if (rc != 0) { 1503 cxgb_printf(sc->dip, CE_WARN, 1504 "failed to get devlog parameters: %d.\n", rc); 1505 bzero(dlog, sizeof (*dlog)); 1506 rc = 0; /* devlog isn't critical for device operation */ 1507 } else { 1508 val[0] = ntohl(cmd.memtype_devlog_memaddr16_devlog); 1509 dlog->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(val[0]); 1510 dlog->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(val[0]) << 4; 1511 dlog->size = ntohl(cmd.memsize_devlog); 1512 } 1513 1514 return (rc); 1515 } 1516 1517 /* 1518 * Retrieve various parameters that are of interest to the driver. The device 1519 * has been initialized by the firmware at this point. 1520 */ 1521 static int 1522 get_params__post_init(struct adapter *sc) 1523 { 1524 int rc; 1525 uint32_t param[7], val[7]; 1526 struct fw_caps_config_cmd caps; 1527 1528 param[0] = FW_PARAM_PFVF(IQFLINT_START); 1529 param[1] = FW_PARAM_PFVF(EQ_START); 1530 param[2] = FW_PARAM_PFVF(IQFLINT_END); 1531 param[3] = FW_PARAM_PFVF(EQ_END); 1532 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 1533 if (rc != 0) { 1534 cxgb_printf(sc->dip, CE_WARN, 1535 "failed to query parameters (post_init): %d.\n", rc); 1536 return (rc); 1537 } 1538 1539 sc->sge.iq_start = val[0]; 1540 sc->sge.eq_start = val[1]; 1541 sc->sge.iqmap_sz = val[2] - sc->sge.iq_start + 1; 1542 sc->sge.eqmap_sz = val[3] - sc->sge.eq_start + 1; 1543 1544 /* get capabilites */ 1545 bzero(&caps, sizeof (caps)); 1546 caps.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1547 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1548 caps.cfvalid_to_len16 = htonl(FW_LEN16(caps)); 1549 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof (caps), &caps); 1550 if (rc != 0) { 1551 cxgb_printf(sc->dip, CE_WARN, 1552 "failed to get card capabilities: %d.\n", rc); 1553 return (rc); 1554 } 1555 1556 rc = -t4_get_pfres(sc); 1557 if (rc != 0) { 1558 cxgb_printf(sc->dip, CE_WARN, 1559 "failed to query PF resource params: %d.\n", rc); 1560 return (rc); 1561 } 1562 1563 /* These are finalized by FW initialization, load their values now */ 1564 val[0] = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 1565 sc->params.tp.tre = G_TIMERRESOLUTION(val[0]); 1566 sc->params.tp.dack_re = G_DELAYEDACKRESOLUTION(val[0]); 1567 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 1568 1569 return (rc); 1570 } 1571 1572 static int 1573 set_params__post_init(struct adapter *sc) 1574 { 1575 uint32_t param, val; 1576 1577 /* ask for encapsulated CPLs */ 1578 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 1579 val = 1; 1580 (void) t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 1581 1582 return (0); 1583 } 1584 1585 /* TODO: verify */ 1586 static void 1587 setup_memwin(struct adapter *sc) 1588 { 1589 pci_regspec_t *data; 1590 int rc; 1591 uint_t n; 1592 uintptr_t bar0; 1593 uintptr_t mem_win0_base, mem_win1_base, mem_win2_base; 1594 uintptr_t mem_win2_aperture; 1595 1596 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, sc->dip, 1597 DDI_PROP_DONTPASS, "assigned-addresses", (int **)&data, &n); 1598 if (rc != DDI_SUCCESS) { 1599 cxgb_printf(sc->dip, CE_WARN, 1600 "failed to lookup \"assigned-addresses\" property: %d", rc); 1601 return; 1602 } 1603 n /= sizeof (*data); 1604 1605 bar0 = ((uint64_t)data[0].pci_phys_mid << 32) | data[0].pci_phys_low; 1606 ddi_prop_free(data); 1607 1608 if (is_t4(sc->params.chip)) { 1609 mem_win0_base = bar0 + MEMWIN0_BASE; 1610 mem_win1_base = bar0 + MEMWIN1_BASE; 1611 mem_win2_base = bar0 + MEMWIN2_BASE; 1612 mem_win2_aperture = MEMWIN2_APERTURE; 1613 } else { 1614 /* For T5, only relative offset inside the PCIe BAR is passed */ 1615 mem_win0_base = MEMWIN0_BASE; 1616 mem_win1_base = MEMWIN1_BASE; 1617 mem_win2_base = MEMWIN2_BASE_T5; 1618 mem_win2_aperture = MEMWIN2_APERTURE_T5; 1619 } 1620 1621 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 0), 1622 mem_win0_base | V_BIR(0) | 1623 V_WINDOW(ilog2(MEMWIN0_APERTURE) - 10)); 1624 1625 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 1), 1626 mem_win1_base | V_BIR(0) | 1627 V_WINDOW(ilog2(MEMWIN1_APERTURE) - 10)); 1628 1629 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2), 1630 mem_win2_base | V_BIR(0) | 1631 V_WINDOW(ilog2(mem_win2_aperture) - 10)); 1632 1633 /* flush */ 1634 (void) t4_read_reg(sc, 1635 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 1636 } 1637 1638 /* 1639 * Positions the memory window such that it can be used to access the specified 1640 * address in the chip's address space. The return value is the offset of addr 1641 * from the start of the window. 1642 */ 1643 uint32_t 1644 position_memwin(struct adapter *sc, int n, uint32_t addr) 1645 { 1646 uint32_t start, pf; 1647 uint32_t reg; 1648 1649 if (addr & 3) { 1650 cxgb_printf(sc->dip, CE_WARN, 1651 "addr (0x%x) is not at a 4B boundary.\n", addr); 1652 return (EFAULT); 1653 } 1654 1655 if (is_t4(sc->params.chip)) { 1656 pf = 0; 1657 start = addr & ~0xf; /* start must be 16B aligned */ 1658 } else { 1659 pf = V_PFNUM(sc->pf); 1660 start = addr & ~0x7f; /* start must be 128B aligned */ 1661 } 1662 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, n); 1663 1664 t4_write_reg(sc, reg, start | pf); 1665 (void) t4_read_reg(sc, reg); 1666 1667 return (addr - start); 1668 } 1669 1670 1671 /* 1672 * Reads the named property and fills up the "data" array (which has at least 1673 * "count" elements). We first try and lookup the property for our dev_t and 1674 * then retry with DDI_DEV_T_ANY if it's not found. 1675 * 1676 * Returns non-zero if the property was found and "data" has been updated. 1677 */ 1678 static int 1679 prop_lookup_int_array(struct adapter *sc, char *name, int *data, uint_t count) 1680 { 1681 dev_info_t *dip = sc->dip; 1682 dev_t dev = sc->dev; 1683 int rc, *d; 1684 uint_t i, n; 1685 1686 rc = ddi_prop_lookup_int_array(dev, dip, DDI_PROP_DONTPASS, 1687 name, &d, &n); 1688 if (rc == DDI_PROP_SUCCESS) 1689 goto found; 1690 1691 if (rc != DDI_PROP_NOT_FOUND) { 1692 cxgb_printf(dip, CE_WARN, 1693 "failed to lookup property %s for minor %d: %d.", 1694 name, getminor(dev), rc); 1695 return (0); 1696 } 1697 1698 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1699 name, &d, &n); 1700 if (rc == DDI_PROP_SUCCESS) 1701 goto found; 1702 1703 if (rc != DDI_PROP_NOT_FOUND) { 1704 cxgb_printf(dip, CE_WARN, 1705 "failed to lookup property %s: %d.", name, rc); 1706 return (0); 1707 } 1708 1709 return (0); 1710 1711 found: 1712 if (n > count) { 1713 cxgb_printf(dip, CE_NOTE, 1714 "property %s has too many elements (%d), ignoring extras", 1715 name, n); 1716 } 1717 1718 for (i = 0; i < n && i < count; i++) 1719 data[i] = d[i]; 1720 ddi_prop_free(d); 1721 1722 return (1); 1723 } 1724 1725 static int 1726 prop_lookup_int(struct adapter *sc, char *name, int defval) 1727 { 1728 int rc; 1729 1730 rc = ddi_prop_get_int(sc->dev, sc->dip, DDI_PROP_DONTPASS, name, -1); 1731 if (rc != -1) 1732 return (rc); 1733 1734 return (ddi_prop_get_int(DDI_DEV_T_ANY, sc->dip, DDI_PROP_DONTPASS, 1735 name, defval)); 1736 } 1737 1738 static int 1739 init_driver_props(struct adapter *sc, struct driver_properties *p) 1740 { 1741 dev_t dev = sc->dev; 1742 dev_info_t *dip = sc->dip; 1743 int i, *data; 1744 uint_t tmr[SGE_NTIMERS] = {5, 10, 20, 50, 100, 200}; 1745 uint_t cnt[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 1746 1747 /* 1748 * Holdoff timer 1749 */ 1750 data = &p->timer_val[0]; 1751 for (i = 0; i < SGE_NTIMERS; i++) 1752 data[i] = tmr[i]; 1753 (void) prop_lookup_int_array(sc, "holdoff-timer-values", data, 1754 SGE_NTIMERS); 1755 for (i = 0; i < SGE_NTIMERS; i++) { 1756 int limit = 200U; 1757 if (data[i] > limit) { 1758 cxgb_printf(dip, CE_WARN, 1759 "holdoff timer %d is too high (%d), lowered to %d.", 1760 i, data[i], limit); 1761 data[i] = limit; 1762 } 1763 } 1764 (void) ddi_prop_update_int_array(dev, dip, "holdoff-timer-values", 1765 data, SGE_NTIMERS); 1766 1767 /* 1768 * Holdoff packet counter 1769 */ 1770 data = &p->counter_val[0]; 1771 for (i = 0; i < SGE_NCOUNTERS; i++) 1772 data[i] = cnt[i]; 1773 (void) prop_lookup_int_array(sc, "holdoff-pkt-counter-values", data, 1774 SGE_NCOUNTERS); 1775 for (i = 0; i < SGE_NCOUNTERS; i++) { 1776 int limit = M_THRESHOLD_0; 1777 if (data[i] > limit) { 1778 cxgb_printf(dip, CE_WARN, 1779 "holdoff pkt-counter %d is too high (%d), " 1780 "lowered to %d.", i, data[i], limit); 1781 data[i] = limit; 1782 } 1783 } 1784 (void) ddi_prop_update_int_array(dev, dip, "holdoff-pkt-counter-values", 1785 data, SGE_NCOUNTERS); 1786 1787 /* 1788 * Maximum # of tx and rx queues to use for each 1789 * 100G, 40G, 25G, 10G and 1G port. 1790 */ 1791 p->max_ntxq_10g = prop_lookup_int(sc, "max-ntxq-10G-port", 8); 1792 (void) ddi_prop_update_int(dev, dip, "max-ntxq-10G-port", 1793 p->max_ntxq_10g); 1794 1795 p->max_nrxq_10g = prop_lookup_int(sc, "max-nrxq-10G-port", 8); 1796 (void) ddi_prop_update_int(dev, dip, "max-nrxq-10G-port", 1797 p->max_nrxq_10g); 1798 1799 p->max_ntxq_1g = prop_lookup_int(sc, "max-ntxq-1G-port", 2); 1800 (void) ddi_prop_update_int(dev, dip, "max-ntxq-1G-port", 1801 p->max_ntxq_1g); 1802 1803 p->max_nrxq_1g = prop_lookup_int(sc, "max-nrxq-1G-port", 2); 1804 (void) ddi_prop_update_int(dev, dip, "max-nrxq-1G-port", 1805 p->max_nrxq_1g); 1806 1807 /* 1808 * Holdoff parameters for 10G and 1G ports. 1809 */ 1810 p->tmr_idx_10g = prop_lookup_int(sc, "holdoff-timer-idx-10G", 0); 1811 (void) ddi_prop_update_int(dev, dip, "holdoff-timer-idx-10G", 1812 p->tmr_idx_10g); 1813 1814 p->pktc_idx_10g = prop_lookup_int(sc, "holdoff-pktc-idx-10G", 2); 1815 (void) ddi_prop_update_int(dev, dip, "holdoff-pktc-idx-10G", 1816 p->pktc_idx_10g); 1817 1818 p->tmr_idx_1g = prop_lookup_int(sc, "holdoff-timer-idx-1G", 0); 1819 (void) ddi_prop_update_int(dev, dip, "holdoff-timer-idx-1G", 1820 p->tmr_idx_1g); 1821 1822 p->pktc_idx_1g = prop_lookup_int(sc, "holdoff-pktc-idx-1G", 2); 1823 (void) ddi_prop_update_int(dev, dip, "holdoff-pktc-idx-1G", 1824 p->pktc_idx_1g); 1825 1826 /* 1827 * Size (number of entries) of each tx and rx queue. 1828 */ 1829 i = prop_lookup_int(sc, "qsize-txq", TX_EQ_QSIZE); 1830 p->qsize_txq = max(i, 128); 1831 if (p->qsize_txq != i) { 1832 cxgb_printf(dip, CE_WARN, 1833 "using %d instead of %d as the tx queue size", 1834 p->qsize_txq, i); 1835 } 1836 (void) ddi_prop_update_int(dev, dip, "qsize-txq", p->qsize_txq); 1837 1838 i = prop_lookup_int(sc, "qsize-rxq", RX_IQ_QSIZE); 1839 p->qsize_rxq = max(i, 128); 1840 while (p->qsize_rxq & 7) 1841 p->qsize_rxq--; 1842 if (p->qsize_rxq != i) { 1843 cxgb_printf(dip, CE_WARN, 1844 "using %d instead of %d as the rx queue size", 1845 p->qsize_rxq, i); 1846 } 1847 (void) ddi_prop_update_int(dev, dip, "qsize-rxq", p->qsize_rxq); 1848 1849 /* 1850 * Interrupt types allowed. 1851 * Bits 0, 1, 2 = INTx, MSI, MSI-X respectively. See sys/ddi_intr.h 1852 */ 1853 p->intr_types = prop_lookup_int(sc, "interrupt-types", 1854 DDI_INTR_TYPE_MSIX | DDI_INTR_TYPE_MSI | DDI_INTR_TYPE_FIXED); 1855 (void) ddi_prop_update_int(dev, dip, "interrupt-types", p->intr_types); 1856 1857 /* 1858 * Write combining 1859 * 0 to disable, 1 to enable 1860 */ 1861 p->wc = prop_lookup_int(sc, "write-combine", 1); 1862 cxgb_printf(dip, CE_WARN, "write-combine: using of %d", p->wc); 1863 if (p->wc != 0 && p->wc != 1) { 1864 cxgb_printf(dip, CE_WARN, 1865 "write-combine: using 1 instead of %d", p->wc); 1866 p->wc = 1; 1867 } 1868 (void) ddi_prop_update_int(dev, dip, "write-combine", p->wc); 1869 1870 p->t4_fw_install = prop_lookup_int(sc, "t4_fw_install", 1); 1871 if (p->t4_fw_install != 0 && p->t4_fw_install != 2) 1872 p->t4_fw_install = 1; 1873 (void) ddi_prop_update_int(dev, dip, "t4_fw_install", p->t4_fw_install); 1874 1875 /* Multiple Rings */ 1876 p->multi_rings = prop_lookup_int(sc, "multi-rings", 1); 1877 if (p->multi_rings != 0 && p->multi_rings != 1) { 1878 cxgb_printf(dip, CE_NOTE, 1879 "multi-rings: using value 1 instead of %d", p->multi_rings); 1880 p->multi_rings = 1; 1881 } 1882 1883 (void) ddi_prop_update_int(dev, dip, "multi-rings", p->multi_rings); 1884 1885 return (0); 1886 } 1887 1888 static int 1889 remove_extra_props(struct adapter *sc, int n10g, int n1g) 1890 { 1891 if (n10g == 0) { 1892 (void) ddi_prop_remove(sc->dev, sc->dip, "max-ntxq-10G-port"); 1893 (void) ddi_prop_remove(sc->dev, sc->dip, "max-nrxq-10G-port"); 1894 (void) ddi_prop_remove(sc->dev, sc->dip, 1895 "holdoff-timer-idx-10G"); 1896 (void) ddi_prop_remove(sc->dev, sc->dip, 1897 "holdoff-pktc-idx-10G"); 1898 } 1899 1900 if (n1g == 0) { 1901 (void) ddi_prop_remove(sc->dev, sc->dip, "max-ntxq-1G-port"); 1902 (void) ddi_prop_remove(sc->dev, sc->dip, "max-nrxq-1G-port"); 1903 (void) ddi_prop_remove(sc->dev, sc->dip, 1904 "holdoff-timer-idx-1G"); 1905 (void) ddi_prop_remove(sc->dev, sc->dip, "holdoff-pktc-idx-1G"); 1906 } 1907 1908 return (0); 1909 } 1910 1911 static int 1912 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, 1913 struct intrs_and_queues *iaq) 1914 { 1915 struct driver_properties *p = &sc->props; 1916 int rc, itype, itypes, navail, nc, n; 1917 int pfres_rxq, pfres_txq, pfresq; 1918 1919 bzero(iaq, sizeof (*iaq)); 1920 nc = ncpus; /* our snapshot of the number of CPUs */ 1921 iaq->ntxq10g = min(nc, p->max_ntxq_10g); 1922 iaq->ntxq1g = min(nc, p->max_ntxq_1g); 1923 iaq->nrxq10g = min(nc, p->max_nrxq_10g); 1924 iaq->nrxq1g = min(nc, p->max_nrxq_1g); 1925 1926 pfres_rxq = iaq->nrxq10g * n10g + iaq->nrxq1g * n1g; 1927 pfres_txq = iaq->ntxq10g * n10g + iaq->ntxq1g * n1g; 1928 1929 /* 1930 * If current configuration of max number of Rxqs and Txqs exceed 1931 * the max available for all the ports under this PF, then shrink 1932 * the queues to max available. Reduce them in a way that each 1933 * port under this PF has equally distributed number of queues. 1934 * Must guarantee at least 1 queue for each port for both NIC 1935 * and Offload queues. 1936 * 1937 * neq - fixed max number of Egress queues on Tx path and Free List 1938 * queues that hold Rx payload data on Rx path. Half are reserved 1939 * for Egress queues and the other half for Free List queues. 1940 * Hence, the division by 2. 1941 * 1942 * niqflint - max number of Ingress queues with interrupts on Rx 1943 * path to receive completions that indicate Rx payload has been 1944 * posted in its associated Free List queue. Also handles Tx 1945 * completions for packets successfully transmitted on Tx path. 1946 * 1947 * nethctrl - max number of Egress queues only for Tx path. This 1948 * number is usually half of neq. However, if it became less than 1949 * neq due to lack of resources based on firmware configuration, 1950 * then take the lower value. 1951 */ 1952 const uint_t max_rxq = 1953 MIN(sc->params.pfres.neq / 2, sc->params.pfres.niqflint); 1954 while (pfres_rxq > max_rxq) { 1955 pfresq = pfres_rxq; 1956 1957 if (iaq->nrxq10g > 1) { 1958 iaq->nrxq10g--; 1959 pfres_rxq -= n10g; 1960 } 1961 1962 if (iaq->nrxq1g > 1) { 1963 iaq->nrxq1g--; 1964 pfres_rxq -= n1g; 1965 } 1966 1967 /* Break if nothing changed */ 1968 if (pfresq == pfres_rxq) 1969 break; 1970 } 1971 1972 const uint_t max_txq = 1973 MIN(sc->params.pfres.neq / 2, sc->params.pfres.nethctrl); 1974 while (pfres_txq > max_txq) { 1975 pfresq = pfres_txq; 1976 1977 if (iaq->ntxq10g > 1) { 1978 iaq->ntxq10g--; 1979 pfres_txq -= n10g; 1980 } 1981 1982 if (iaq->ntxq1g > 1) { 1983 iaq->ntxq1g--; 1984 pfres_txq -= n1g; 1985 } 1986 1987 /* Break if nothing changed */ 1988 if (pfresq == pfres_txq) 1989 break; 1990 } 1991 1992 rc = ddi_intr_get_supported_types(sc->dip, &itypes); 1993 if (rc != DDI_SUCCESS) { 1994 cxgb_printf(sc->dip, CE_WARN, 1995 "failed to determine supported interrupt types: %d", rc); 1996 return (rc); 1997 } 1998 1999 for (itype = DDI_INTR_TYPE_MSIX; itype; itype >>= 1) { 2000 ASSERT(itype == DDI_INTR_TYPE_MSIX || 2001 itype == DDI_INTR_TYPE_MSI || 2002 itype == DDI_INTR_TYPE_FIXED); 2003 2004 if ((itype & itypes & p->intr_types) == 0) 2005 continue; /* not supported or not allowed */ 2006 2007 navail = 0; 2008 rc = ddi_intr_get_navail(sc->dip, itype, &navail); 2009 if (rc != DDI_SUCCESS || navail == 0) { 2010 cxgb_printf(sc->dip, CE_WARN, 2011 "failed to get # of interrupts for type %d: %d", 2012 itype, rc); 2013 continue; /* carry on */ 2014 } 2015 2016 iaq->intr_type = itype; 2017 if (navail == 0) 2018 continue; 2019 2020 /* 2021 * Best option: an interrupt vector for errors, one for the 2022 * firmware event queue, and one each for each rxq (NIC as well 2023 * as offload). 2024 */ 2025 iaq->nirq = T4_EXTRA_INTR; 2026 iaq->nirq += n10g * iaq->nrxq10g; 2027 iaq->nirq += n1g * iaq->nrxq1g; 2028 2029 if (iaq->nirq <= navail && 2030 (itype != DDI_INTR_TYPE_MSI || ISP2(iaq->nirq))) { 2031 iaq->intr_fwd = 0; 2032 goto allocate; 2033 } 2034 2035 /* 2036 * Second best option: an interrupt vector for errors, one for 2037 * the firmware event queue, and one each for either NIC or 2038 * offload rxq's. 2039 */ 2040 iaq->nirq = T4_EXTRA_INTR; 2041 iaq->nirq += n10g * iaq->nrxq10g; 2042 iaq->nirq += n1g * iaq->nrxq1g; 2043 if (iaq->nirq <= navail && 2044 (itype != DDI_INTR_TYPE_MSI || ISP2(iaq->nirq))) { 2045 iaq->intr_fwd = 1; 2046 goto allocate; 2047 } 2048 2049 /* 2050 * Next best option: an interrupt vector for errors, one for the 2051 * firmware event queue, and at least one per port. At this 2052 * point we know we'll have to downsize nrxq or nofldrxq to fit 2053 * what's available to us. 2054 */ 2055 iaq->nirq = T4_EXTRA_INTR; 2056 iaq->nirq += n10g + n1g; 2057 if (iaq->nirq <= navail) { 2058 int leftover = navail - iaq->nirq; 2059 2060 if (n10g > 0) { 2061 int target = iaq->nrxq10g; 2062 2063 n = 1; 2064 while (n < target && leftover >= n10g) { 2065 leftover -= n10g; 2066 iaq->nirq += n10g; 2067 n++; 2068 } 2069 iaq->nrxq10g = min(n, iaq->nrxq10g); 2070 } 2071 2072 if (n1g > 0) { 2073 int target = iaq->nrxq1g; 2074 2075 n = 1; 2076 while (n < target && leftover >= n1g) { 2077 leftover -= n1g; 2078 iaq->nirq += n1g; 2079 n++; 2080 } 2081 iaq->nrxq1g = min(n, iaq->nrxq1g); 2082 } 2083 2084 /* 2085 * We have arrived at a minimum value required to enable 2086 * per queue irq(either NIC or offload). Thus for non- 2087 * offload case, we will get a vector per queue, while 2088 * offload case, we will get a vector per offload/NIC q. 2089 * Hence enable Interrupt forwarding only for offload 2090 * case. 2091 */ 2092 if (itype != DDI_INTR_TYPE_MSI) { 2093 goto allocate; 2094 } 2095 } 2096 2097 /* 2098 * Least desirable option: one interrupt vector for everything. 2099 */ 2100 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1; 2101 iaq->intr_fwd = 1; 2102 2103 allocate: 2104 return (0); 2105 } 2106 2107 cxgb_printf(sc->dip, CE_WARN, 2108 "failed to find a usable interrupt type. supported=%d, allowed=%d", 2109 itypes, p->intr_types); 2110 return (DDI_FAILURE); 2111 } 2112 2113 static int 2114 add_child_node(struct adapter *sc, int idx) 2115 { 2116 int rc; 2117 struct port_info *pi; 2118 2119 if (idx < 0 || idx >= sc->params.nports) 2120 return (EINVAL); 2121 2122 pi = sc->port[idx]; 2123 if (pi == NULL) 2124 return (ENODEV); /* t4_port_init failed earlier */ 2125 2126 PORT_LOCK(pi); 2127 if (pi->dip != NULL) { 2128 rc = 0; /* EEXIST really, but then bus_config fails */ 2129 goto done; 2130 } 2131 2132 rc = ndi_devi_alloc(sc->dip, T4_PORT_NAME, DEVI_SID_NODEID, &pi->dip); 2133 if (rc != DDI_SUCCESS || pi->dip == NULL) { 2134 rc = ENOMEM; 2135 goto done; 2136 } 2137 2138 (void) ddi_set_parent_data(pi->dip, pi); 2139 (void) ndi_devi_bind_driver(pi->dip, 0); 2140 rc = 0; 2141 done: 2142 PORT_UNLOCK(pi); 2143 return (rc); 2144 } 2145 2146 static int 2147 remove_child_node(struct adapter *sc, int idx) 2148 { 2149 int rc; 2150 struct port_info *pi; 2151 2152 if (idx < 0 || idx >= sc->params.nports) 2153 return (EINVAL); 2154 2155 pi = sc->port[idx]; 2156 if (pi == NULL) 2157 return (ENODEV); 2158 2159 PORT_LOCK(pi); 2160 if (pi->dip == NULL) { 2161 rc = ENODEV; 2162 goto done; 2163 } 2164 2165 rc = ndi_devi_free(pi->dip); 2166 if (rc == 0) 2167 pi->dip = NULL; 2168 done: 2169 PORT_UNLOCK(pi); 2170 return (rc); 2171 } 2172 2173 static char * 2174 print_port_speed(const struct port_info *pi) 2175 { 2176 if (!pi) 2177 return ("-"); 2178 2179 if (is_100G_port(pi)) 2180 return ("100G"); 2181 else if (is_50G_port(pi)) 2182 return ("50G"); 2183 else if (is_40G_port(pi)) 2184 return ("40G"); 2185 else if (is_25G_port(pi)) 2186 return ("25G"); 2187 else if (is_10G_port(pi)) 2188 return ("10G"); 2189 else 2190 return ("1G"); 2191 } 2192 2193 #define KS_UINIT(x) kstat_named_init(&kstatp->x, #x, KSTAT_DATA_ULONG) 2194 #define KS_CINIT(x) kstat_named_init(&kstatp->x, #x, KSTAT_DATA_CHAR) 2195 #define KS_U64INIT(x) kstat_named_init(&kstatp->x, #x, KSTAT_DATA_UINT64) 2196 #define KS_U_SET(x, y) kstatp->x.value.ul = (y) 2197 #define KS_C_SET(x, ...) \ 2198 (void) snprintf(kstatp->x.value.c, 16, __VA_ARGS__) 2199 2200 /* 2201 * t4nex:X:config 2202 */ 2203 struct t4_kstats { 2204 kstat_named_t chip_ver; 2205 kstat_named_t fw_vers; 2206 kstat_named_t tp_vers; 2207 kstat_named_t driver_version; 2208 kstat_named_t serial_number; 2209 kstat_named_t ec_level; 2210 kstat_named_t id; 2211 kstat_named_t bus_type; 2212 kstat_named_t bus_width; 2213 kstat_named_t bus_speed; 2214 kstat_named_t core_clock; 2215 kstat_named_t port_cnt; 2216 kstat_named_t port_type; 2217 kstat_named_t pci_vendor_id; 2218 kstat_named_t pci_device_id; 2219 }; 2220 static kstat_t * 2221 setup_kstats(struct adapter *sc) 2222 { 2223 kstat_t *ksp; 2224 struct t4_kstats *kstatp; 2225 int ndata; 2226 struct pci_params *p = &sc->params.pci; 2227 struct vpd_params *v = &sc->params.vpd; 2228 uint16_t pci_vendor, pci_device; 2229 2230 ndata = sizeof (struct t4_kstats) / sizeof (kstat_named_t); 2231 2232 ksp = kstat_create(T4_NEXUS_NAME, ddi_get_instance(sc->dip), "config", 2233 "nexus", KSTAT_TYPE_NAMED, ndata, 0); 2234 if (ksp == NULL) { 2235 cxgb_printf(sc->dip, CE_WARN, "failed to initialize kstats."); 2236 return (NULL); 2237 } 2238 2239 kstatp = (struct t4_kstats *)ksp->ks_data; 2240 2241 KS_UINIT(chip_ver); 2242 KS_CINIT(fw_vers); 2243 KS_CINIT(tp_vers); 2244 KS_CINIT(driver_version); 2245 KS_CINIT(serial_number); 2246 KS_CINIT(ec_level); 2247 KS_CINIT(id); 2248 KS_CINIT(bus_type); 2249 KS_CINIT(bus_width); 2250 KS_CINIT(bus_speed); 2251 KS_UINIT(core_clock); 2252 KS_UINIT(port_cnt); 2253 KS_CINIT(port_type); 2254 KS_CINIT(pci_vendor_id); 2255 KS_CINIT(pci_device_id); 2256 2257 KS_U_SET(chip_ver, sc->params.chip); 2258 KS_C_SET(fw_vers, "%d.%d.%d.%d", 2259 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 2260 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 2261 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 2262 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 2263 KS_C_SET(tp_vers, "%d.%d.%d.%d", 2264 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 2265 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 2266 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 2267 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 2268 KS_C_SET(driver_version, DRV_VERSION); 2269 KS_C_SET(serial_number, "%s", v->sn); 2270 KS_C_SET(ec_level, "%s", v->ec); 2271 KS_C_SET(id, "%s", v->id); 2272 KS_C_SET(bus_type, "pci-express"); 2273 KS_C_SET(bus_width, "x%d lanes", p->width); 2274 KS_C_SET(bus_speed, "%d", p->speed); 2275 KS_U_SET(core_clock, v->cclk); 2276 KS_U_SET(port_cnt, sc->params.nports); 2277 2278 t4_os_pci_read_cfg2(sc, PCI_CONF_VENID, &pci_vendor); 2279 KS_C_SET(pci_vendor_id, "0x%x", pci_vendor); 2280 2281 t4_os_pci_read_cfg2(sc, PCI_CONF_DEVID, &pci_device); 2282 KS_C_SET(pci_device_id, "0x%x", pci_device); 2283 2284 KS_C_SET(port_type, "%s/%s/%s/%s", 2285 print_port_speed(sc->port[0]), 2286 print_port_speed(sc->port[1]), 2287 print_port_speed(sc->port[2]), 2288 print_port_speed(sc->port[3])); 2289 2290 /* Do NOT set ksp->ks_update. These kstats do not change. */ 2291 2292 /* Install the kstat */ 2293 ksp->ks_private = (void *)sc; 2294 kstat_install(ksp); 2295 2296 return (ksp); 2297 } 2298 2299 /* 2300 * t4nex:X:stat 2301 */ 2302 struct t4_wc_kstats { 2303 kstat_named_t write_coal_success; 2304 kstat_named_t write_coal_failure; 2305 }; 2306 static kstat_t * 2307 setup_wc_kstats(struct adapter *sc) 2308 { 2309 kstat_t *ksp; 2310 struct t4_wc_kstats *kstatp; 2311 2312 const uint_t ndata = 2313 sizeof (struct t4_wc_kstats) / sizeof (kstat_named_t); 2314 ksp = kstat_create(T4_NEXUS_NAME, ddi_get_instance(sc->dip), "stats", 2315 "nexus", KSTAT_TYPE_NAMED, ndata, 0); 2316 if (ksp == NULL) { 2317 cxgb_printf(sc->dip, CE_WARN, "failed to initialize kstats."); 2318 return (NULL); 2319 } 2320 2321 kstatp = (struct t4_wc_kstats *)ksp->ks_data; 2322 2323 KS_UINIT(write_coal_success); 2324 KS_UINIT(write_coal_failure); 2325 2326 ksp->ks_update = update_wc_kstats; 2327 /* Install the kstat */ 2328 ksp->ks_private = (void *)sc; 2329 kstat_install(ksp); 2330 2331 return (ksp); 2332 } 2333 2334 static int 2335 update_wc_kstats(kstat_t *ksp, int rw) 2336 { 2337 struct t4_wc_kstats *kstatp = (struct t4_wc_kstats *)ksp->ks_data; 2338 struct adapter *sc = ksp->ks_private; 2339 uint32_t wc_total, wc_success, wc_failure; 2340 2341 if (rw == KSTAT_WRITE) 2342 return (0); 2343 2344 if (is_t5(sc->params.chip)) { 2345 wc_total = t4_read_reg(sc, A_SGE_STAT_TOTAL); 2346 wc_failure = t4_read_reg(sc, A_SGE_STAT_MATCH); 2347 wc_success = wc_total - wc_failure; 2348 } else { 2349 wc_success = 0; 2350 wc_failure = 0; 2351 } 2352 2353 KS_U_SET(write_coal_success, wc_success); 2354 KS_U_SET(write_coal_failure, wc_failure); 2355 2356 return (0); 2357 } 2358 2359 /* 2360 * cxgbe:X:fec 2361 * 2362 * This provides visibility into the errors that have been found by the 2363 * different FEC subsystems. While it's tempting to combine the two different 2364 * FEC types logically, the data that the errors tell us are pretty different 2365 * between the two. Firecode is strictly per-lane, but RS has parts that are 2366 * related to symbol distribution to lanes and also to the overall channel. 2367 */ 2368 struct cxgbe_port_fec_kstats { 2369 kstat_named_t rs_corr; 2370 kstat_named_t rs_uncorr; 2371 kstat_named_t rs_sym0_corr; 2372 kstat_named_t rs_sym1_corr; 2373 kstat_named_t rs_sym2_corr; 2374 kstat_named_t rs_sym3_corr; 2375 kstat_named_t fc_lane0_corr; 2376 kstat_named_t fc_lane0_uncorr; 2377 kstat_named_t fc_lane1_corr; 2378 kstat_named_t fc_lane1_uncorr; 2379 kstat_named_t fc_lane2_corr; 2380 kstat_named_t fc_lane2_uncorr; 2381 kstat_named_t fc_lane3_corr; 2382 kstat_named_t fc_lane3_uncorr; 2383 }; 2384 2385 static uint32_t 2386 read_fec_pair(struct port_info *pi, uint32_t lo_reg, uint32_t high_reg) 2387 { 2388 struct adapter *sc = pi->adapter; 2389 uint8_t port = pi->tx_chan; 2390 uint32_t low, high, ret; 2391 2392 low = t4_read_reg32(sc, T5_PORT_REG(port, lo_reg)); 2393 high = t4_read_reg32(sc, T5_PORT_REG(port, high_reg)); 2394 ret = low & 0xffff; 2395 ret |= (high & 0xffff) << 16; 2396 return (ret); 2397 } 2398 2399 static int 2400 update_port_fec_kstats(kstat_t *ksp, int rw) 2401 { 2402 struct cxgbe_port_fec_kstats *fec = ksp->ks_data; 2403 struct port_info *pi = ksp->ks_private; 2404 2405 if (rw == KSTAT_WRITE) { 2406 return (EACCES); 2407 } 2408 2409 /* 2410 * First go ahead and gather RS related stats. 2411 */ 2412 fec->rs_corr.value.ui64 += read_fec_pair(pi, T6_RS_FEC_CCW_LO, 2413 T6_RS_FEC_CCW_HI); 2414 fec->rs_uncorr.value.ui64 += read_fec_pair(pi, T6_RS_FEC_NCCW_LO, 2415 T6_RS_FEC_NCCW_HI); 2416 fec->rs_sym0_corr.value.ui64 += read_fec_pair(pi, T6_RS_FEC_SYMERR0_LO, 2417 T6_RS_FEC_SYMERR0_HI); 2418 fec->rs_sym1_corr.value.ui64 += read_fec_pair(pi, T6_RS_FEC_SYMERR1_LO, 2419 T6_RS_FEC_SYMERR1_HI); 2420 fec->rs_sym2_corr.value.ui64 += read_fec_pair(pi, T6_RS_FEC_SYMERR2_LO, 2421 T6_RS_FEC_SYMERR2_HI); 2422 fec->rs_sym3_corr.value.ui64 += read_fec_pair(pi, T6_RS_FEC_SYMERR3_LO, 2423 T6_RS_FEC_SYMERR3_HI); 2424 2425 /* 2426 * Now go through and try to grab Firecode/BASE-R stats. 2427 */ 2428 fec->fc_lane0_corr.value.ui64 += read_fec_pair(pi, T6_FC_FEC_L0_CERR_LO, 2429 T6_FC_FEC_L0_CERR_HI); 2430 fec->fc_lane0_uncorr.value.ui64 += read_fec_pair(pi, 2431 T6_FC_FEC_L0_NCERR_LO, T6_FC_FEC_L0_NCERR_HI); 2432 fec->fc_lane1_corr.value.ui64 += read_fec_pair(pi, T6_FC_FEC_L1_CERR_LO, 2433 T6_FC_FEC_L1_CERR_HI); 2434 fec->fc_lane1_uncorr.value.ui64 += read_fec_pair(pi, 2435 T6_FC_FEC_L1_NCERR_LO, T6_FC_FEC_L1_NCERR_HI); 2436 fec->fc_lane2_corr.value.ui64 += read_fec_pair(pi, T6_FC_FEC_L2_CERR_LO, 2437 T6_FC_FEC_L2_CERR_HI); 2438 fec->fc_lane2_uncorr.value.ui64 += read_fec_pair(pi, 2439 T6_FC_FEC_L2_NCERR_LO, T6_FC_FEC_L2_NCERR_HI); 2440 fec->fc_lane3_corr.value.ui64 += read_fec_pair(pi, T6_FC_FEC_L3_CERR_LO, 2441 T6_FC_FEC_L3_CERR_HI); 2442 fec->fc_lane3_uncorr.value.ui64 += read_fec_pair(pi, 2443 T6_FC_FEC_L3_NCERR_LO, T6_FC_FEC_L3_NCERR_HI); 2444 2445 return (0); 2446 } 2447 2448 static kstat_t * 2449 setup_port_fec_kstats(struct port_info *pi) 2450 { 2451 kstat_t *ksp; 2452 struct cxgbe_port_fec_kstats *kstatp; 2453 2454 if (!is_t6(pi->adapter->params.chip)) { 2455 return (NULL); 2456 } 2457 2458 ksp = kstat_create(T4_PORT_NAME, ddi_get_instance(pi->dip), "fec", 2459 "net", KSTAT_TYPE_NAMED, sizeof (struct cxgbe_port_fec_kstats) / 2460 sizeof (kstat_named_t), 0); 2461 if (ksp == NULL) { 2462 cxgb_printf(pi->dip, CE_WARN, "failed to initialize fec " 2463 "kstats."); 2464 return (NULL); 2465 } 2466 2467 kstatp = ksp->ks_data; 2468 KS_U64INIT(rs_corr); 2469 KS_U64INIT(rs_uncorr); 2470 KS_U64INIT(rs_sym0_corr); 2471 KS_U64INIT(rs_sym1_corr); 2472 KS_U64INIT(rs_sym2_corr); 2473 KS_U64INIT(rs_sym3_corr); 2474 KS_U64INIT(fc_lane0_corr); 2475 KS_U64INIT(fc_lane0_uncorr); 2476 KS_U64INIT(fc_lane1_corr); 2477 KS_U64INIT(fc_lane1_uncorr); 2478 KS_U64INIT(fc_lane2_corr); 2479 KS_U64INIT(fc_lane2_uncorr); 2480 KS_U64INIT(fc_lane3_corr); 2481 KS_U64INIT(fc_lane3_uncorr); 2482 2483 ksp->ks_update = update_port_fec_kstats; 2484 ksp->ks_private = pi; 2485 kstat_install(ksp); 2486 2487 return (ksp); 2488 } 2489 2490 int 2491 adapter_full_init(struct adapter *sc) 2492 { 2493 int i, rc = 0; 2494 2495 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 2496 2497 rc = t4_setup_adapter_queues(sc); 2498 if (rc != 0) 2499 goto done; 2500 2501 if (sc->intr_cap & DDI_INTR_FLAG_BLOCK) 2502 (void) ddi_intr_block_enable(sc->intr_handle, sc->intr_count); 2503 else { 2504 for (i = 0; i < sc->intr_count; i++) 2505 (void) ddi_intr_enable(sc->intr_handle[i]); 2506 } 2507 t4_intr_enable(sc); 2508 sc->flags |= TAF_INIT_DONE; 2509 2510 done: 2511 if (rc != 0) 2512 (void) adapter_full_uninit(sc); 2513 2514 return (rc); 2515 } 2516 2517 int 2518 adapter_full_uninit(struct adapter *sc) 2519 { 2520 int i, rc = 0; 2521 2522 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 2523 2524 if (sc->intr_cap & DDI_INTR_FLAG_BLOCK) 2525 (void) ddi_intr_block_disable(sc->intr_handle, sc->intr_count); 2526 else { 2527 for (i = 0; i < sc->intr_count; i++) 2528 (void) ddi_intr_disable(sc->intr_handle[i]); 2529 } 2530 2531 rc = t4_teardown_adapter_queues(sc); 2532 if (rc != 0) 2533 return (rc); 2534 2535 sc->flags &= ~TAF_INIT_DONE; 2536 2537 return (0); 2538 } 2539 2540 int 2541 port_full_init(struct port_info *pi) 2542 { 2543 struct adapter *sc = pi->adapter; 2544 uint16_t *rss; 2545 struct sge_rxq *rxq; 2546 int rc, i; 2547 2548 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 2549 ASSERT((pi->flags & TPF_INIT_DONE) == 0); 2550 2551 /* 2552 * Allocate tx/rx/fl queues for this port. 2553 */ 2554 rc = t4_setup_port_queues(pi); 2555 if (rc != 0) 2556 goto done; /* error message displayed already */ 2557 2558 /* 2559 * Setup RSS for this port. 2560 */ 2561 rss = kmem_zalloc(pi->nrxq * sizeof (*rss), KM_SLEEP); 2562 for_each_rxq(pi, i, rxq) { 2563 rss[i] = rxq->iq.abs_id; 2564 } 2565 rc = -t4_config_rss_range(sc, sc->mbox, pi->viid, 0, 2566 pi->rss_size, rss, pi->nrxq); 2567 kmem_free(rss, pi->nrxq * sizeof (*rss)); 2568 if (rc != 0) { 2569 cxgb_printf(pi->dip, CE_WARN, "rss_config failed: %d", rc); 2570 goto done; 2571 } 2572 2573 /* 2574 * Initialize our per-port FEC kstats. 2575 */ 2576 pi->ksp_fec = setup_port_fec_kstats(pi); 2577 2578 pi->flags |= TPF_INIT_DONE; 2579 done: 2580 if (rc != 0) 2581 (void) port_full_uninit(pi); 2582 2583 return (rc); 2584 } 2585 2586 /* 2587 * Idempotent. 2588 */ 2589 int 2590 port_full_uninit(struct port_info *pi) 2591 { 2592 2593 ASSERT(pi->flags & TPF_INIT_DONE); 2594 2595 if (pi->ksp_fec != NULL) { 2596 kstat_delete(pi->ksp_fec); 2597 pi->ksp_fec = NULL; 2598 } 2599 (void) t4_teardown_port_queues(pi); 2600 pi->flags &= ~TPF_INIT_DONE; 2601 2602 return (0); 2603 } 2604 2605 void 2606 enable_port_queues(struct port_info *pi) 2607 { 2608 struct adapter *sc = pi->adapter; 2609 int i; 2610 struct sge_iq *iq; 2611 struct sge_rxq *rxq; 2612 2613 ASSERT(pi->flags & TPF_INIT_DONE); 2614 2615 /* 2616 * TODO: whatever was queued up after we set iq->state to IQS_DISABLED 2617 * back in disable_port_queues will be processed now, after an unbounded 2618 * delay. This can't be good. 2619 */ 2620 2621 for_each_rxq(pi, i, rxq) { 2622 iq = &rxq->iq; 2623 if (atomic_cas_uint(&iq->state, IQS_DISABLED, IQS_IDLE) != 2624 IQS_DISABLED) 2625 panic("%s: iq %p wasn't disabled", __func__, 2626 (void *) iq); 2627 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), 2628 V_SEINTARM(iq->intr_params) | V_INGRESSQID(iq->cntxt_id)); 2629 } 2630 } 2631 2632 void 2633 disable_port_queues(struct port_info *pi) 2634 { 2635 int i; 2636 struct adapter *sc = pi->adapter; 2637 struct sge_rxq *rxq; 2638 2639 ASSERT(pi->flags & TPF_INIT_DONE); 2640 2641 /* 2642 * TODO: need proper implementation for all tx queues (ctrl, eth, ofld). 2643 */ 2644 2645 for_each_rxq(pi, i, rxq) { 2646 while (atomic_cas_uint(&rxq->iq.state, IQS_IDLE, 2647 IQS_DISABLED) != IQS_IDLE) 2648 msleep(1); 2649 } 2650 2651 mutex_enter(&sc->sfl_lock); 2652 for_each_rxq(pi, i, rxq) 2653 rxq->fl.flags |= FL_DOOMED; 2654 mutex_exit(&sc->sfl_lock); 2655 /* TODO: need to wait for all fl's to be removed from sc->sfl */ 2656 } 2657 2658 void 2659 t4_fatal_err(struct adapter *sc) 2660 { 2661 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 2662 t4_intr_disable(sc); 2663 cxgb_printf(sc->dip, CE_WARN, 2664 "encountered fatal error, adapter stopped."); 2665 } 2666 2667 int 2668 t4_os_find_pci_capability(struct adapter *sc, int cap) 2669 { 2670 uint16_t stat; 2671 uint8_t cap_ptr, cap_id; 2672 2673 t4_os_pci_read_cfg2(sc, PCI_CONF_STAT, &stat); 2674 if ((stat & PCI_STAT_CAP) == 0) 2675 return (0); /* does not implement capabilities */ 2676 2677 t4_os_pci_read_cfg1(sc, PCI_CONF_CAP_PTR, &cap_ptr); 2678 while (cap_ptr) { 2679 t4_os_pci_read_cfg1(sc, cap_ptr + PCI_CAP_ID, &cap_id); 2680 if (cap_id == cap) 2681 return (cap_ptr); /* found */ 2682 t4_os_pci_read_cfg1(sc, cap_ptr + PCI_CAP_NEXT_PTR, &cap_ptr); 2683 } 2684 2685 return (0); /* not found */ 2686 } 2687 2688 void 2689 t4_os_portmod_changed(struct adapter *sc, int idx) 2690 { 2691 static const char *mod_str[] = { 2692 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 2693 }; 2694 struct port_info *pi = sc->port[idx]; 2695 2696 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 2697 cxgb_printf(pi->dip, CE_NOTE, "transceiver unplugged."); 2698 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 2699 cxgb_printf(pi->dip, CE_NOTE, 2700 "unknown transceiver inserted.\n"); 2701 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 2702 cxgb_printf(pi->dip, CE_NOTE, 2703 "unsupported transceiver inserted.\n"); 2704 else if (pi->mod_type > 0 && pi->mod_type < ARRAY_SIZE(mod_str)) 2705 cxgb_printf(pi->dip, CE_NOTE, "%s transceiver inserted.\n", 2706 mod_str[pi->mod_type]); 2707 else 2708 cxgb_printf(pi->dip, CE_NOTE, "transceiver (type %d) inserted.", 2709 pi->mod_type); 2710 2711 if ((isset(&sc->open_device_map, pi->port_id) != 0) && 2712 pi->link_cfg.new_module) 2713 pi->link_cfg.redo_l1cfg = true; 2714 } 2715 2716 static int 2717 t4_sensor_read(struct adapter *sc, uint32_t diag, uint32_t *valp) 2718 { 2719 int rc; 2720 struct port_info *pi = sc->port[0]; 2721 uint32_t param, val; 2722 2723 rc = begin_synchronized_op(pi, 1, 1); 2724 if (rc != 0) { 2725 return (rc); 2726 } 2727 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2728 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 2729 V_FW_PARAMS_PARAM_Y(diag); 2730 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2731 end_synchronized_op(pi, 1); 2732 2733 if (rc != 0) { 2734 return (rc); 2735 } 2736 2737 if (val == 0) { 2738 return (EIO); 2739 } 2740 2741 *valp = val; 2742 return (0); 2743 } 2744 2745 static int 2746 t4_temperature_read(void *arg, sensor_ioctl_scalar_t *scalar) 2747 { 2748 int ret; 2749 struct adapter *sc = arg; 2750 uint32_t val; 2751 2752 ret = t4_sensor_read(sc, FW_PARAM_DEV_DIAG_TMP, &val); 2753 if (ret != 0) { 2754 return (ret); 2755 } 2756 2757 /* 2758 * The device measures temperature in units of 1 degree Celsius. We 2759 * don't know its precision. 2760 */ 2761 scalar->sis_unit = SENSOR_UNIT_CELSIUS; 2762 scalar->sis_gran = 1; 2763 scalar->sis_prec = 0; 2764 scalar->sis_value = val; 2765 2766 return (0); 2767 } 2768 2769 static int 2770 t4_voltage_read(void *arg, sensor_ioctl_scalar_t *scalar) 2771 { 2772 int ret; 2773 struct adapter *sc = arg; 2774 uint32_t val; 2775 2776 ret = t4_sensor_read(sc, FW_PARAM_DEV_DIAG_VDD, &val); 2777 if (ret != 0) { 2778 return (ret); 2779 } 2780 2781 scalar->sis_unit = SENSOR_UNIT_VOLTS; 2782 scalar->sis_gran = 1000; 2783 scalar->sis_prec = 0; 2784 scalar->sis_value = val; 2785 2786 return (0); 2787 } 2788 2789 /* 2790 * While the hardware supports the ability to read and write the flash image, 2791 * this is not currently wired up. 2792 */ 2793 static int 2794 t4_ufm_getcaps(ddi_ufm_handle_t *ufmh, void *arg, ddi_ufm_cap_t *caps) 2795 { 2796 *caps = DDI_UFM_CAP_REPORT; 2797 return (0); 2798 } 2799 2800 static int 2801 t4_ufm_fill_image(ddi_ufm_handle_t *ufmh, void *arg, uint_t imgno, 2802 ddi_ufm_image_t *imgp) 2803 { 2804 if (imgno != 0) { 2805 return (EINVAL); 2806 } 2807 2808 ddi_ufm_image_set_desc(imgp, "Firmware"); 2809 ddi_ufm_image_set_nslots(imgp, 1); 2810 2811 return (0); 2812 } 2813 2814 static int 2815 t4_ufm_fill_slot_version(nvlist_t *nvl, const char *key, uint32_t vers) 2816 { 2817 char buf[128]; 2818 2819 if (vers == 0) { 2820 return (0); 2821 } 2822 2823 if (snprintf(buf, sizeof (buf), "%u.%u.%u.%u", 2824 G_FW_HDR_FW_VER_MAJOR(vers), G_FW_HDR_FW_VER_MINOR(vers), 2825 G_FW_HDR_FW_VER_MICRO(vers), G_FW_HDR_FW_VER_BUILD(vers)) >= 2826 sizeof (buf)) { 2827 return (EOVERFLOW); 2828 } 2829 2830 return (nvlist_add_string(nvl, key, buf)); 2831 } 2832 2833 static int 2834 t4_ufm_fill_slot(ddi_ufm_handle_t *ufmh, void *arg, uint_t imgno, uint_t slotno, 2835 ddi_ufm_slot_t *slotp) 2836 { 2837 int ret; 2838 struct adapter *sc = arg; 2839 nvlist_t *misc = NULL; 2840 char buf[128]; 2841 2842 if (imgno != 0 || slotno != 0) { 2843 return (EINVAL); 2844 } 2845 2846 if (snprintf(buf, sizeof (buf), "%u.%u.%u.%u", 2847 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 2848 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 2849 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 2850 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)) >= sizeof (buf)) { 2851 return (EOVERFLOW); 2852 } 2853 2854 ddi_ufm_slot_set_version(slotp, buf); 2855 2856 (void) nvlist_alloc(&misc, NV_UNIQUE_NAME, KM_SLEEP); 2857 if ((ret = t4_ufm_fill_slot_version(misc, "TP Microcode", 2858 sc->params.tp_vers)) != 0) { 2859 goto err; 2860 } 2861 2862 if ((ret = t4_ufm_fill_slot_version(misc, "Bootstrap", 2863 sc->params.bs_vers)) != 0) { 2864 goto err; 2865 } 2866 2867 if ((ret = t4_ufm_fill_slot_version(misc, "Expansion ROM", 2868 sc->params.er_vers)) != 0) { 2869 goto err; 2870 } 2871 2872 if ((ret = nvlist_add_uint32(misc, "Serial Configuration", 2873 sc->params.scfg_vers)) != 0) { 2874 goto err; 2875 } 2876 2877 if ((ret = nvlist_add_uint32(misc, "VPD Version", 2878 sc->params.vpd_vers)) != 0) { 2879 goto err; 2880 } 2881 2882 ddi_ufm_slot_set_misc(slotp, misc); 2883 ddi_ufm_slot_set_attrs(slotp, DDI_UFM_ATTR_ACTIVE | 2884 DDI_UFM_ATTR_WRITEABLE | DDI_UFM_ATTR_READABLE); 2885 return (0); 2886 2887 err: 2888 nvlist_free(misc); 2889 return (ret); 2890 2891 } 2892 2893 2894 int 2895 t4_cxgbe_attach(struct port_info *pi, dev_info_t *dip) 2896 { 2897 ASSERT(pi != NULL); 2898 2899 mac_register_t *mac = mac_alloc(MAC_VERSION); 2900 if (mac == NULL) { 2901 return (DDI_FAILURE); 2902 } 2903 2904 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 2905 mac->m_driver = pi; 2906 mac->m_dip = dip; 2907 mac->m_src_addr = pi->hw_addr; 2908 mac->m_callbacks = pi->mc; 2909 mac->m_max_sdu = pi->mtu; 2910 mac->m_priv_props = pi->props; 2911 mac->m_margin = VLAN_TAGSZ; 2912 2913 if (!mac->m_callbacks->mc_unicst) { 2914 /* Multiple rings enabled */ 2915 mac->m_v12n = MAC_VIRT_LEVEL1; 2916 } 2917 2918 mac_handle_t mh = NULL; 2919 const int rc = mac_register(mac, &mh); 2920 mac_free(mac); 2921 if (rc != 0) { 2922 return (DDI_FAILURE); 2923 } 2924 2925 pi->mh = mh; 2926 2927 /* 2928 * Link state from this point onwards to the time interface is plumbed, 2929 * should be set to LINK_STATE_UNKNOWN. The mac should be updated about 2930 * the link state as either LINK_STATE_UP or LINK_STATE_DOWN based on 2931 * the actual link state detection after interface plumb. 2932 */ 2933 mac_link_update(mh, LINK_STATE_UNKNOWN); 2934 2935 return (DDI_SUCCESS); 2936 } 2937 2938 int 2939 t4_cxgbe_detach(struct port_info *pi) 2940 { 2941 ASSERT(pi != NULL); 2942 ASSERT(pi->mh != NULL); 2943 2944 if (mac_unregister(pi->mh) == 0) { 2945 pi->mh = NULL; 2946 return (DDI_SUCCESS); 2947 } 2948 2949 return (DDI_FAILURE); 2950 } 2951