1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4 support code. 14 * 15 * Copyright (C) 2010-2013 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23 /* 24 * Copyright 2023 Oxide Computer Company 25 */ 26 27 #include <sys/ddi.h> 28 #include <sys/sunddi.h> 29 #include <sys/sunndi.h> 30 #include <sys/modctl.h> 31 #include <sys/conf.h> 32 #include <sys/devops.h> 33 #include <sys/pci.h> 34 #include <sys/atomic.h> 35 #include <sys/types.h> 36 #include <sys/file.h> 37 #include <sys/errno.h> 38 #include <sys/open.h> 39 #include <sys/cred.h> 40 #include <sys/stat.h> 41 #include <sys/mkdev.h> 42 #include <sys/queue.h> 43 #include <sys/containerof.h> 44 #include <sys/sensors.h> 45 #include <sys/firmload.h> 46 47 #include "version.h" 48 #include "common/common.h" 49 #include "common/t4_msg.h" 50 #include "common/t4_regs.h" 51 #include "common/t4_extra_regs.h" 52 #include "t4_l2t.h" 53 54 static int t4_cb_open(dev_t *devp, int flag, int otyp, cred_t *credp); 55 static int t4_cb_close(dev_t dev, int flag, int otyp, cred_t *credp); 56 static int t4_cb_ioctl(dev_t dev, int cmd, intptr_t d, int mode, cred_t *credp, 57 int *rp); 58 struct cb_ops t4_cb_ops = { 59 .cb_open = t4_cb_open, 60 .cb_close = t4_cb_close, 61 .cb_strategy = nodev, 62 .cb_print = nodev, 63 .cb_dump = nodev, 64 .cb_read = nodev, 65 .cb_write = nodev, 66 .cb_ioctl = t4_cb_ioctl, 67 .cb_devmap = nodev, 68 .cb_mmap = nodev, 69 .cb_segmap = nodev, 70 .cb_chpoll = nochpoll, 71 .cb_prop_op = ddi_prop_op, 72 .cb_flag = D_MP, 73 .cb_rev = CB_REV, 74 .cb_aread = nodev, 75 .cb_awrite = nodev 76 }; 77 78 static int t4_bus_ctl(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t op, 79 void *arg, void *result); 80 static int t4_bus_config(dev_info_t *dip, uint_t flags, ddi_bus_config_op_t op, 81 void *arg, dev_info_t **cdipp); 82 static int t4_bus_unconfig(dev_info_t *dip, uint_t flags, 83 ddi_bus_config_op_t op, void *arg); 84 struct bus_ops t4_bus_ops = { 85 .busops_rev = BUSO_REV, 86 .bus_ctl = t4_bus_ctl, 87 .bus_prop_op = ddi_bus_prop_op, 88 .bus_config = t4_bus_config, 89 .bus_unconfig = t4_bus_unconfig, 90 }; 91 92 static int t4_devo_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, 93 void **rp); 94 static int t4_devo_probe(dev_info_t *dip); 95 static int t4_devo_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 96 static int t4_devo_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 97 static int t4_devo_quiesce(dev_info_t *dip); 98 struct dev_ops t4_dev_ops = { 99 .devo_rev = DEVO_REV, 100 .devo_getinfo = t4_devo_getinfo, 101 .devo_identify = nulldev, 102 .devo_probe = t4_devo_probe, 103 .devo_attach = t4_devo_attach, 104 .devo_detach = t4_devo_detach, 105 .devo_reset = nodev, 106 .devo_cb_ops = &t4_cb_ops, 107 .devo_bus_ops = &t4_bus_ops, 108 .devo_quiesce = &t4_devo_quiesce, 109 }; 110 111 static struct modldrv modldrv = { 112 .drv_modops = &mod_driverops, 113 .drv_linkinfo = "Chelsio T4 nexus " DRV_VERSION, 114 .drv_dev_ops = &t4_dev_ops 115 }; 116 117 static struct modlinkage modlinkage = { 118 .ml_rev = MODREV_1, 119 .ml_linkage = {&modldrv, NULL}, 120 }; 121 122 void *t4_list; 123 124 struct intrs_and_queues { 125 int intr_type; /* DDI_INTR_TYPE_* */ 126 int nirq; /* Number of vectors */ 127 int intr_fwd; /* Interrupts forwarded */ 128 int ntxq10g; /* # of NIC txq's for each 10G port */ 129 int nrxq10g; /* # of NIC rxq's for each 10G port */ 130 int ntxq1g; /* # of NIC txq's for each 1G port */ 131 int nrxq1g; /* # of NIC rxq's for each 1G port */ 132 }; 133 134 static int cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, 135 mblk_t *m); 136 static int fw_msg_not_handled(struct adapter *, const __be64 *); 137 int t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h); 138 static unsigned int getpf(struct adapter *sc); 139 static int prep_firmware(struct adapter *sc); 140 static int upload_config_file(struct adapter *sc, uint32_t *mt, uint32_t *ma); 141 static int partition_resources(struct adapter *sc); 142 static int adap__pre_init_tweaks(struct adapter *sc); 143 static int get_params__pre_init(struct adapter *sc); 144 static int get_params__post_init(struct adapter *sc); 145 static int set_params__post_init(struct adapter *); 146 static void setup_memwin(struct adapter *sc); 147 static int validate_mt_off_len(struct adapter *, int, uint32_t, int, 148 uint32_t *); 149 void memwin_info(struct adapter *, int, uint32_t *, uint32_t *); 150 uint32_t position_memwin(struct adapter *, int, uint32_t); 151 static int prop_lookup_int_array(struct adapter *sc, char *name, int *data, 152 uint_t count); 153 static int prop_lookup_int_array(struct adapter *sc, char *name, int *data, 154 uint_t count); 155 static int init_driver_props(struct adapter *sc, struct driver_properties *p); 156 static int remove_extra_props(struct adapter *sc, int n10g, int n1g); 157 static int cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, 158 struct intrs_and_queues *iaq); 159 static int add_child_node(struct adapter *sc, int idx); 160 static int remove_child_node(struct adapter *sc, int idx); 161 static kstat_t *setup_kstats(struct adapter *sc); 162 static kstat_t *setup_wc_kstats(struct adapter *); 163 static int update_wc_kstats(kstat_t *, int); 164 static kmutex_t t4_adapter_list_lock; 165 static SLIST_HEAD(, adapter) t4_adapter_list; 166 167 static int t4_temperature_read(void *, sensor_ioctl_scalar_t *); 168 static int t4_voltage_read(void *, sensor_ioctl_scalar_t *); 169 static const ksensor_ops_t t4_temp_ops = { 170 .kso_kind = ksensor_kind_temperature, 171 .kso_scalar = t4_temperature_read 172 }; 173 174 static const ksensor_ops_t t4_volt_ops = { 175 .kso_kind = ksensor_kind_voltage, 176 .kso_scalar = t4_voltage_read 177 }; 178 179 static int t4_ufm_getcaps(ddi_ufm_handle_t *, void *, ddi_ufm_cap_t *); 180 static int t4_ufm_fill_image(ddi_ufm_handle_t *, void *, uint_t, 181 ddi_ufm_image_t *); 182 static int t4_ufm_fill_slot(ddi_ufm_handle_t *, void *, uint_t, uint_t, 183 ddi_ufm_slot_t *); 184 static ddi_ufm_ops_t t4_ufm_ops = { 185 .ddi_ufm_op_fill_image = t4_ufm_fill_image, 186 .ddi_ufm_op_fill_slot = t4_ufm_fill_slot, 187 .ddi_ufm_op_getcaps = t4_ufm_getcaps 188 }; 189 190 int 191 _init(void) 192 { 193 int rc; 194 195 rc = ddi_soft_state_init(&t4_list, sizeof (struct adapter), 0); 196 if (rc != 0) 197 return (rc); 198 199 rc = mod_install(&modlinkage); 200 if (rc != 0) 201 ddi_soft_state_fini(&t4_list); 202 203 mutex_init(&t4_adapter_list_lock, NULL, MUTEX_DRIVER, NULL); 204 SLIST_INIT(&t4_adapter_list); 205 206 return (rc); 207 } 208 209 int 210 _fini(void) 211 { 212 int rc; 213 214 rc = mod_remove(&modlinkage); 215 if (rc != 0) 216 return (rc); 217 218 ddi_soft_state_fini(&t4_list); 219 return (0); 220 } 221 222 int 223 _info(struct modinfo *mi) 224 { 225 return (mod_info(&modlinkage, mi)); 226 } 227 228 /* ARGSUSED */ 229 static int 230 t4_devo_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **rp) 231 { 232 struct adapter *sc; 233 minor_t minor; 234 235 minor = getminor((dev_t)arg); /* same as instance# in our case */ 236 237 if (cmd == DDI_INFO_DEVT2DEVINFO) { 238 sc = ddi_get_soft_state(t4_list, minor); 239 if (sc == NULL) 240 return (DDI_FAILURE); 241 242 ASSERT(sc->dev == (dev_t)arg); 243 *rp = (void *)sc->dip; 244 } else if (cmd == DDI_INFO_DEVT2INSTANCE) 245 *rp = (void *) (unsigned long) minor; 246 else 247 ASSERT(0); 248 249 return (DDI_SUCCESS); 250 } 251 252 static int 253 t4_devo_probe(dev_info_t *dip) 254 { 255 int rc, id, *reg; 256 uint_t n, pf; 257 258 id = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 259 "device-id", 0xffff); 260 if (id == 0xffff) 261 return (DDI_PROBE_DONTCARE); 262 263 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 264 "reg", ®, &n); 265 if (rc != DDI_SUCCESS) 266 return (DDI_PROBE_DONTCARE); 267 268 pf = PCI_REG_FUNC_G(reg[0]); 269 ddi_prop_free(reg); 270 271 /* Prevent driver attachment on any PF except 0 on the FPGA */ 272 if (id == 0xa000 && pf != 0) 273 return (DDI_PROBE_FAILURE); 274 275 return (DDI_PROBE_DONTCARE); 276 } 277 278 static int 279 t4_devo_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 280 { 281 struct adapter *sc = NULL; 282 struct sge *s; 283 int i, instance, rc = DDI_SUCCESS, rqidx, tqidx, q; 284 int irq = 0, nxg = 0, n1g = 0; 285 char name[16]; 286 struct driver_properties *prp; 287 struct intrs_and_queues iaq; 288 ddi_device_acc_attr_t da = { 289 .devacc_attr_version = DDI_DEVICE_ATTR_V0, 290 .devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC, 291 .devacc_attr_dataorder = DDI_STRICTORDER_ACC 292 }; 293 ddi_device_acc_attr_t da1 = { 294 .devacc_attr_version = DDI_DEVICE_ATTR_V0, 295 .devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC, 296 .devacc_attr_dataorder = DDI_STRICTORDER_ACC 297 }; 298 299 if (cmd != DDI_ATTACH) 300 return (DDI_FAILURE); 301 302 /* 303 * Allocate space for soft state. 304 */ 305 instance = ddi_get_instance(dip); 306 rc = ddi_soft_state_zalloc(t4_list, instance); 307 if (rc != DDI_SUCCESS) { 308 cxgb_printf(dip, CE_WARN, 309 "failed to allocate soft state: %d", rc); 310 return (DDI_FAILURE); 311 } 312 313 sc = ddi_get_soft_state(t4_list, instance); 314 sc->dip = dip; 315 sc->dev = makedevice(ddi_driver_major(dip), instance); 316 mutex_init(&sc->lock, NULL, MUTEX_DRIVER, NULL); 317 cv_init(&sc->cv, NULL, CV_DRIVER, NULL); 318 mutex_init(&sc->sfl_lock, NULL, MUTEX_DRIVER, NULL); 319 TAILQ_INIT(&sc->sfl); 320 mutex_init(&sc->mbox_lock, NULL, MUTEX_DRIVER, NULL); 321 STAILQ_INIT(&sc->mbox_list); 322 323 mutex_enter(&t4_adapter_list_lock); 324 SLIST_INSERT_HEAD(&t4_adapter_list, sc, link); 325 mutex_exit(&t4_adapter_list_lock); 326 327 sc->pf = getpf(sc); 328 if (sc->pf > 8) { 329 rc = EINVAL; 330 cxgb_printf(dip, CE_WARN, 331 "failed to determine PCI PF# of device"); 332 goto done; 333 } 334 sc->mbox = sc->pf; 335 336 /* Initialize the driver properties */ 337 prp = &sc->props; 338 (void)init_driver_props(sc, prp); 339 340 /* 341 * Enable access to the PCI config space. 342 */ 343 rc = pci_config_setup(dip, &sc->pci_regh); 344 if (rc != DDI_SUCCESS) { 345 cxgb_printf(dip, CE_WARN, 346 "failed to enable PCI config space access: %d", rc); 347 goto done; 348 } 349 350 /* TODO: Set max read request to 4K */ 351 352 /* 353 * Enable MMIO access. 354 */ 355 rc = ddi_regs_map_setup(dip, 1, &sc->regp, 0, 0, &da, &sc->regh); 356 if (rc != DDI_SUCCESS) { 357 cxgb_printf(dip, CE_WARN, 358 "failed to map device registers: %d", rc); 359 goto done; 360 } 361 362 (void) memset(sc->chan_map, 0xff, sizeof (sc->chan_map)); 363 364 /* 365 * Initialize cpl handler. 366 */ 367 for (i = 0; i < ARRAY_SIZE(sc->cpl_handler); i++) { 368 sc->cpl_handler[i] = cpl_not_handled; 369 } 370 371 for (i = 0; i < ARRAY_SIZE(sc->fw_msg_handler); i++) { 372 sc->fw_msg_handler[i] = fw_msg_not_handled; 373 } 374 375 for (i = 0; i < NCHAN; i++) { 376 (void) snprintf(name, sizeof (name), "%s-%d", 377 "reclaim", i); 378 sc->tq[i] = ddi_taskq_create(sc->dip, 379 name, 1, TASKQ_DEFAULTPRI, 0); 380 381 if (sc->tq[i] == NULL) { 382 cxgb_printf(dip, CE_WARN, 383 "failed to create task queues"); 384 rc = DDI_FAILURE; 385 goto done; 386 } 387 } 388 389 /* 390 * Prepare the adapter for operation. 391 */ 392 rc = -t4_prep_adapter(sc, false); 393 if (rc != 0) { 394 cxgb_printf(dip, CE_WARN, "failed to prepare adapter: %d", rc); 395 goto done; 396 } 397 398 /* 399 * Enable BAR1 access. 400 */ 401 sc->doorbells |= DOORBELL_KDB; 402 rc = ddi_regs_map_setup(dip, 2, &sc->reg1p, 0, 0, &da1, &sc->reg1h); 403 if (rc != DDI_SUCCESS) { 404 cxgb_printf(dip, CE_WARN, 405 "failed to map BAR1 device registers: %d", rc); 406 goto done; 407 } else { 408 if (is_t5(sc->params.chip)) { 409 sc->doorbells |= DOORBELL_UDB; 410 if (prp->wc) { 411 /* 412 * Enable write combining on BAR2. This is the 413 * userspace doorbell BAR and is split into 128B 414 * (UDBS_SEG_SIZE) doorbell regions, each associated 415 * with an egress queue. The first 64B has the doorbell 416 * and the second 64B can be used to submit a tx work 417 * request with an implicit doorbell. 418 */ 419 sc->doorbells &= ~DOORBELL_UDB; 420 sc->doorbells |= (DOORBELL_WCWR | 421 DOORBELL_UDBWC); 422 t4_write_reg(sc, A_SGE_STAT_CFG, 423 V_STATSOURCE_T5(7) | V_STATMODE(0)); 424 } 425 } 426 } 427 428 /* 429 * Do this really early. Note that minor number = instance. 430 */ 431 (void) snprintf(name, sizeof (name), "%s,%d", T4_NEXUS_NAME, instance); 432 rc = ddi_create_minor_node(dip, name, S_IFCHR, instance, 433 DDI_NT_NEXUS, 0); 434 if (rc != DDI_SUCCESS) { 435 cxgb_printf(dip, CE_WARN, 436 "failed to create device node: %d", rc); 437 rc = DDI_SUCCESS; /* carry on */ 438 } 439 440 /* Do this early. Memory window is required for loading config file. */ 441 setup_memwin(sc); 442 443 /* Prepare the firmware for operation */ 444 rc = prep_firmware(sc); 445 if (rc != 0) 446 goto done; /* error message displayed already */ 447 448 rc = adap__pre_init_tweaks(sc); 449 if (rc != 0) 450 goto done; 451 452 rc = get_params__pre_init(sc); 453 if (rc != 0) 454 goto done; /* error message displayed already */ 455 456 t4_sge_init(sc); 457 458 if (sc->flags & MASTER_PF) { 459 /* get basic stuff going */ 460 rc = -t4_fw_initialize(sc, sc->mbox); 461 if (rc != 0) { 462 cxgb_printf(sc->dip, CE_WARN, 463 "early init failed: %d.\n", rc); 464 goto done; 465 } 466 } 467 468 rc = get_params__post_init(sc); 469 if (rc != 0) 470 goto done; /* error message displayed already */ 471 472 rc = set_params__post_init(sc); 473 if (rc != 0) 474 goto done; /* error message displayed already */ 475 476 /* 477 * TODO: This is the place to call t4_set_filter_mode() 478 */ 479 480 /* tweak some settings */ 481 t4_write_reg(sc, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) | V_RXTSHIFTMAXR1(4) | 482 V_RXTSHIFTMAXR2(15) | V_PERSHIFTBACKOFFMAX(8) | V_PERSHIFTMAX(8) | 483 V_KEEPALIVEMAXR1(4) | V_KEEPALIVEMAXR2(9)); 484 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); 485 486 /* 487 * Work-around for bug 2619 488 * Set DisableVlan field in TP_RSS_CONFIG_VRT register so that the 489 * VLAN tag extraction is disabled. 490 */ 491 t4_set_reg_field(sc, A_TP_RSS_CONFIG_VRT, F_DISABLEVLAN, F_DISABLEVLAN); 492 493 /* Store filter mode */ 494 t4_read_indirect(sc, A_TP_PIO_ADDR, A_TP_PIO_DATA, &sc->filter_mode, 1, 495 A_TP_VLAN_PRI_MAP); 496 497 /* 498 * First pass over all the ports - allocate VIs and initialize some 499 * basic parameters like mac address, port type, etc. We also figure 500 * out whether a port is 10G or 1G and use that information when 501 * calculating how many interrupts to attempt to allocate. 502 */ 503 for_each_port(sc, i) { 504 struct port_info *pi; 505 506 pi = kmem_zalloc(sizeof (*pi), KM_SLEEP); 507 sc->port[i] = pi; 508 509 /* These must be set before t4_port_init */ 510 pi->adapter = sc; 511 /* LINTED: E_ASSIGN_NARROW_CONV */ 512 pi->port_id = i; 513 } 514 515 /* Allocate the vi and initialize parameters like mac addr */ 516 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0); 517 if (rc) { 518 cxgb_printf(dip, CE_WARN, 519 "unable to initialize port: %d", rc); 520 goto done; 521 } 522 523 for_each_port(sc, i) { 524 struct port_info *pi = sc->port[i]; 525 526 mutex_init(&pi->lock, NULL, MUTEX_DRIVER, NULL); 527 pi->mtu = ETHERMTU; 528 529 if (is_10XG_port(pi)) { 530 nxg++; 531 pi->tmr_idx = prp->tmr_idx_10g; 532 pi->pktc_idx = prp->pktc_idx_10g; 533 } else { 534 n1g++; 535 pi->tmr_idx = prp->tmr_idx_1g; 536 pi->pktc_idx = prp->pktc_idx_1g; 537 } 538 539 pi->xact_addr_filt = -1; 540 t4_mc_init(pi); 541 542 setbit(&sc->registered_device_map, i); 543 } 544 545 (void) remove_extra_props(sc, nxg, n1g); 546 547 if (sc->registered_device_map == 0) { 548 cxgb_printf(dip, CE_WARN, "no usable ports"); 549 rc = DDI_FAILURE; 550 goto done; 551 } 552 553 rc = cfg_itype_and_nqueues(sc, nxg, n1g, &iaq); 554 if (rc != 0) 555 goto done; /* error message displayed already */ 556 557 sc->intr_type = iaq.intr_type; 558 sc->intr_count = iaq.nirq; 559 560 if (sc->props.multi_rings && (sc->intr_type != DDI_INTR_TYPE_MSIX)) { 561 sc->props.multi_rings = 0; 562 cxgb_printf(dip, CE_WARN, 563 "Multiple rings disabled as interrupt type is not MSI-X"); 564 } 565 566 if (sc->props.multi_rings && iaq.intr_fwd) { 567 sc->props.multi_rings = 0; 568 cxgb_printf(dip, CE_WARN, 569 "Multiple rings disabled as interrupts are forwarded"); 570 } 571 572 if (!sc->props.multi_rings) { 573 iaq.ntxq10g = 1; 574 iaq.ntxq1g = 1; 575 } 576 s = &sc->sge; 577 s->nrxq = nxg * iaq.nrxq10g + n1g * iaq.nrxq1g; 578 s->ntxq = nxg * iaq.ntxq10g + n1g * iaq.ntxq1g; 579 s->neq = s->ntxq + s->nrxq; /* the fl in an rxq is an eq */ 580 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 581 if (iaq.intr_fwd != 0) 582 sc->flags |= INTR_FWD; 583 s->rxq = kmem_zalloc(s->nrxq * sizeof (struct sge_rxq), KM_SLEEP); 584 s->txq = kmem_zalloc(s->ntxq * sizeof (struct sge_txq), KM_SLEEP); 585 s->iqmap = kmem_zalloc(s->iqmap_sz * sizeof (struct sge_iq *), KM_SLEEP); 586 s->eqmap = kmem_zalloc(s->eqmap_sz * sizeof (struct sge_eq *), KM_SLEEP); 587 588 sc->intr_handle = kmem_zalloc(sc->intr_count * 589 sizeof (ddi_intr_handle_t), KM_SLEEP); 590 591 /* 592 * Second pass over the ports. This time we know the number of rx and 593 * tx queues that each port should get. 594 */ 595 rqidx = tqidx = 0; 596 for_each_port(sc, i) { 597 struct port_info *pi = sc->port[i]; 598 599 if (pi == NULL) 600 continue; 601 602 t4_mc_cb_init(pi); 603 /* LINTED: E_ASSIGN_NARROW_CONV */ 604 pi->first_rxq = rqidx; 605 /* LINTED: E_ASSIGN_NARROW_CONV */ 606 pi->nrxq = (is_10XG_port(pi)) ? iaq.nrxq10g 607 : iaq.nrxq1g; 608 /* LINTED: E_ASSIGN_NARROW_CONV */ 609 pi->first_txq = tqidx; 610 /* LINTED: E_ASSIGN_NARROW_CONV */ 611 pi->ntxq = (is_10XG_port(pi)) ? iaq.ntxq10g 612 : iaq.ntxq1g; 613 614 rqidx += pi->nrxq; 615 tqidx += pi->ntxq; 616 617 /* 618 * Enable hw checksumming and LSO for all ports by default. 619 * They can be disabled using ndd (hw_csum and hw_lso). 620 */ 621 pi->features |= (CXGBE_HW_CSUM | CXGBE_HW_LSO); 622 } 623 624 /* 625 * Setup Interrupts. 626 */ 627 628 i = 0; 629 rc = ddi_intr_alloc(dip, sc->intr_handle, sc->intr_type, 0, 630 sc->intr_count, &i, DDI_INTR_ALLOC_STRICT); 631 if (rc != DDI_SUCCESS) { 632 cxgb_printf(dip, CE_WARN, 633 "failed to allocate %d interrupt(s) of type %d: %d, %d", 634 sc->intr_count, sc->intr_type, rc, i); 635 goto done; 636 } 637 ASSERT(sc->intr_count == i); /* allocation was STRICT */ 638 (void) ddi_intr_get_cap(sc->intr_handle[0], &sc->intr_cap); 639 (void) ddi_intr_get_pri(sc->intr_handle[0], &sc->intr_pri); 640 if (sc->intr_count == 1) { 641 ASSERT(sc->flags & INTR_FWD); 642 (void) ddi_intr_add_handler(sc->intr_handle[0], t4_intr_all, sc, 643 &s->fwq); 644 } else { 645 /* Multiple interrupts. The first one is always error intr */ 646 (void) ddi_intr_add_handler(sc->intr_handle[0], t4_intr_err, sc, 647 NULL); 648 irq++; 649 650 /* The second one is always the firmware event queue */ 651 (void) ddi_intr_add_handler(sc->intr_handle[1], t4_intr, sc, 652 &s->fwq); 653 irq++; 654 /* 655 * Note that if INTR_FWD is set then either the NIC rx 656 * queues or (exclusive or) the TOE rx queueus will be taking 657 * direct interrupts. 658 * 659 * There is no need to check for is_offload(sc) as nofldrxq 660 * will be 0 if offload is disabled. 661 */ 662 for_each_port(sc, i) { 663 struct port_info *pi = sc->port[i]; 664 struct sge_rxq *rxq; 665 rxq = &s->rxq[pi->first_rxq]; 666 for (q = 0; q < pi->nrxq; q++, rxq++) { 667 (void) ddi_intr_add_handler( 668 sc->intr_handle[irq], t4_intr, sc, 669 &rxq->iq); 670 irq++; 671 } 672 } 673 674 } 675 sc->flags |= INTR_ALLOCATED; 676 677 if ((rc = ksensor_create_scalar_pcidev(dip, SENSOR_KIND_TEMPERATURE, 678 &t4_temp_ops, sc, "temp", &sc->temp_sensor)) != 0) { 679 cxgb_printf(dip, CE_WARN, "failed to create temperature " 680 "sensor: %d", rc); 681 rc = DDI_FAILURE; 682 goto done; 683 } 684 685 if ((rc = ksensor_create_scalar_pcidev(dip, SENSOR_KIND_VOLTAGE, 686 &t4_volt_ops, sc, "vdd", &sc->volt_sensor)) != 0) { 687 cxgb_printf(dip, CE_WARN, "failed to create voltage " 688 "sensor: %d", rc); 689 rc = DDI_FAILURE; 690 goto done; 691 } 692 693 694 if ((rc = ddi_ufm_init(dip, DDI_UFM_CURRENT_VERSION, &t4_ufm_ops, 695 &sc->ufm_hdl, sc)) != 0) { 696 cxgb_printf(dip, CE_WARN, "failed to enable UFM ops: %d", rc); 697 rc = DDI_FAILURE; 698 goto done; 699 } 700 ddi_ufm_update(sc->ufm_hdl); 701 ddi_report_dev(dip); 702 703 /* 704 * Hardware/Firmware/etc. Version/Revision IDs. 705 */ 706 t4_dump_version_info(sc); 707 708 cxgb_printf(dip, CE_NOTE, 709 "(%d rxq, %d txq total) %d %s.", 710 rqidx, tqidx, sc->intr_count, 711 sc->intr_type == DDI_INTR_TYPE_MSIX ? "MSI-X interrupts" : 712 sc->intr_type == DDI_INTR_TYPE_MSI ? "MSI interrupts" : 713 "fixed interrupt"); 714 715 sc->ksp = setup_kstats(sc); 716 sc->ksp_stat = setup_wc_kstats(sc); 717 sc->params.drv_memwin = MEMWIN_NIC; 718 719 done: 720 if (rc != DDI_SUCCESS) { 721 (void) t4_devo_detach(dip, DDI_DETACH); 722 723 /* rc may have errno style errors or DDI errors */ 724 rc = DDI_FAILURE; 725 } 726 727 return (rc); 728 } 729 730 static int 731 t4_devo_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 732 { 733 int instance, i; 734 struct adapter *sc; 735 struct port_info *pi; 736 struct sge *s; 737 738 if (cmd != DDI_DETACH) 739 return (DDI_FAILURE); 740 741 instance = ddi_get_instance(dip); 742 sc = ddi_get_soft_state(t4_list, instance); 743 if (sc == NULL) 744 return (DDI_SUCCESS); 745 746 if (sc->flags & FULL_INIT_DONE) { 747 t4_intr_disable(sc); 748 for_each_port(sc, i) { 749 pi = sc->port[i]; 750 if (pi && pi->flags & PORT_INIT_DONE) 751 (void) port_full_uninit(pi); 752 } 753 (void) adapter_full_uninit(sc); 754 } 755 756 /* Safe to call no matter what */ 757 if (sc->ufm_hdl != NULL) { 758 ddi_ufm_fini(sc->ufm_hdl); 759 sc->ufm_hdl = NULL; 760 } 761 (void) ksensor_remove(dip, KSENSOR_ALL_IDS); 762 ddi_prop_remove_all(dip); 763 ddi_remove_minor_node(dip, NULL); 764 765 for (i = 0; i < NCHAN; i++) { 766 if (sc->tq[i]) { 767 ddi_taskq_wait(sc->tq[i]); 768 ddi_taskq_destroy(sc->tq[i]); 769 } 770 } 771 772 if (sc->ksp != NULL) 773 kstat_delete(sc->ksp); 774 if (sc->ksp_stat != NULL) 775 kstat_delete(sc->ksp_stat); 776 777 s = &sc->sge; 778 if (s->rxq != NULL) 779 kmem_free(s->rxq, s->nrxq * sizeof (struct sge_rxq)); 780 if (s->txq != NULL) 781 kmem_free(s->txq, s->ntxq * sizeof (struct sge_txq)); 782 if (s->iqmap != NULL) 783 kmem_free(s->iqmap, s->iqmap_sz * sizeof (struct sge_iq *)); 784 if (s->eqmap != NULL) 785 kmem_free(s->eqmap, s->eqmap_sz * sizeof (struct sge_eq *)); 786 787 if (s->rxbuf_cache != NULL) 788 rxbuf_cache_destroy(s->rxbuf_cache); 789 790 if (sc->flags & INTR_ALLOCATED) { 791 for (i = 0; i < sc->intr_count; i++) { 792 (void) ddi_intr_remove_handler(sc->intr_handle[i]); 793 (void) ddi_intr_free(sc->intr_handle[i]); 794 } 795 sc->flags &= ~INTR_ALLOCATED; 796 } 797 798 if (sc->intr_handle != NULL) { 799 kmem_free(sc->intr_handle, 800 sc->intr_count * sizeof (*sc->intr_handle)); 801 } 802 803 for_each_port(sc, i) { 804 pi = sc->port[i]; 805 if (pi != NULL) { 806 mutex_destroy(&pi->lock); 807 kmem_free(pi, sizeof (*pi)); 808 clrbit(&sc->registered_device_map, i); 809 } 810 } 811 812 if (sc->flags & FW_OK) 813 (void) t4_fw_bye(sc, sc->mbox); 814 815 if (sc->reg1h != NULL) 816 ddi_regs_map_free(&sc->reg1h); 817 818 if (sc->regh != NULL) 819 ddi_regs_map_free(&sc->regh); 820 821 if (sc->pci_regh != NULL) 822 pci_config_teardown(&sc->pci_regh); 823 824 mutex_enter(&t4_adapter_list_lock); 825 SLIST_REMOVE(&t4_adapter_list, sc, adapter, link); 826 mutex_exit(&t4_adapter_list_lock); 827 828 mutex_destroy(&sc->mbox_lock); 829 mutex_destroy(&sc->lock); 830 cv_destroy(&sc->cv); 831 mutex_destroy(&sc->sfl_lock); 832 833 #ifdef DEBUG 834 bzero(sc, sizeof (*sc)); 835 #endif 836 ddi_soft_state_free(t4_list, instance); 837 838 return (DDI_SUCCESS); 839 } 840 841 static int 842 t4_devo_quiesce(dev_info_t *dip) 843 { 844 int instance; 845 struct adapter *sc; 846 847 instance = ddi_get_instance(dip); 848 sc = ddi_get_soft_state(t4_list, instance); 849 if (sc == NULL) 850 return (DDI_SUCCESS); 851 852 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 853 t4_intr_disable(sc); 854 t4_write_reg(sc, A_PL_RST, F_PIORSTMODE | F_PIORST); 855 856 return (DDI_SUCCESS); 857 } 858 859 static int 860 t4_bus_ctl(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t op, void *arg, 861 void *result) 862 { 863 char s[4]; 864 struct port_info *pi; 865 dev_info_t *child = (dev_info_t *)arg; 866 867 switch (op) { 868 case DDI_CTLOPS_REPORTDEV: 869 pi = ddi_get_parent_data(rdip); 870 pi->instance = ddi_get_instance(dip); 871 pi->child_inst = ddi_get_instance(rdip); 872 cmn_err(CE_CONT, "?%s%d is port %s on %s%d\n", 873 ddi_node_name(rdip), ddi_get_instance(rdip), 874 ddi_get_name_addr(rdip), ddi_driver_name(dip), 875 ddi_get_instance(dip)); 876 return (DDI_SUCCESS); 877 878 case DDI_CTLOPS_INITCHILD: 879 pi = ddi_get_parent_data(child); 880 if (pi == NULL) 881 return (DDI_NOT_WELL_FORMED); 882 (void) snprintf(s, sizeof (s), "%d", pi->port_id); 883 ddi_set_name_addr(child, s); 884 return (DDI_SUCCESS); 885 886 case DDI_CTLOPS_UNINITCHILD: 887 ddi_set_name_addr(child, NULL); 888 return (DDI_SUCCESS); 889 890 case DDI_CTLOPS_ATTACH: 891 case DDI_CTLOPS_DETACH: 892 return (DDI_SUCCESS); 893 894 default: 895 return (ddi_ctlops(dip, rdip, op, arg, result)); 896 } 897 } 898 899 static int 900 t4_bus_config(dev_info_t *dip, uint_t flags, ddi_bus_config_op_t op, void *arg, 901 dev_info_t **cdipp) 902 { 903 int instance, i; 904 struct adapter *sc; 905 906 instance = ddi_get_instance(dip); 907 sc = ddi_get_soft_state(t4_list, instance); 908 909 if (op == BUS_CONFIG_ONE) { 910 char *c; 911 912 /* 913 * arg is something like "cxgb@0" where 0 is the port_id hanging 914 * off this nexus. 915 */ 916 917 c = arg; 918 while (*(c + 1)) 919 c++; 920 921 /* There should be exactly 1 digit after '@' */ 922 if (*(c - 1) != '@') 923 return (NDI_FAILURE); 924 925 i = *c - '0'; 926 927 if (add_child_node(sc, i) != 0) 928 return (NDI_FAILURE); 929 930 flags |= NDI_ONLINE_ATTACH; 931 932 } else if (op == BUS_CONFIG_ALL || op == BUS_CONFIG_DRIVER) { 933 /* Allocate and bind all child device nodes */ 934 for_each_port(sc, i) 935 (void) add_child_node(sc, i); 936 flags |= NDI_ONLINE_ATTACH; 937 } 938 939 return (ndi_busop_bus_config(dip, flags, op, arg, cdipp, 0)); 940 } 941 942 static int 943 t4_bus_unconfig(dev_info_t *dip, uint_t flags, ddi_bus_config_op_t op, 944 void *arg) 945 { 946 int instance, i, rc; 947 struct adapter *sc; 948 949 instance = ddi_get_instance(dip); 950 sc = ddi_get_soft_state(t4_list, instance); 951 952 if (op == BUS_CONFIG_ONE || op == BUS_UNCONFIG_ALL || 953 op == BUS_UNCONFIG_DRIVER) 954 flags |= NDI_UNCONFIG; 955 956 rc = ndi_busop_bus_unconfig(dip, flags, op, arg); 957 if (rc != 0) 958 return (rc); 959 960 if (op == BUS_UNCONFIG_ONE) { 961 char *c; 962 963 c = arg; 964 while (*(c + 1)) 965 c++; 966 967 if (*(c - 1) != '@') 968 return (NDI_SUCCESS); 969 970 i = *c - '0'; 971 972 rc = remove_child_node(sc, i); 973 974 } else if (op == BUS_UNCONFIG_ALL || op == BUS_UNCONFIG_DRIVER) { 975 976 for_each_port(sc, i) 977 (void) remove_child_node(sc, i); 978 } 979 980 return (rc); 981 } 982 983 /* ARGSUSED */ 984 static int 985 t4_cb_open(dev_t *devp, int flag, int otyp, cred_t *credp) 986 { 987 struct adapter *sc; 988 989 if (otyp != OTYP_CHR) 990 return (EINVAL); 991 992 sc = ddi_get_soft_state(t4_list, getminor(*devp)); 993 if (sc == NULL) 994 return (ENXIO); 995 996 return (atomic_cas_uint(&sc->open, 0, EBUSY)); 997 } 998 999 /* ARGSUSED */ 1000 static int 1001 t4_cb_close(dev_t dev, int flag, int otyp, cred_t *credp) 1002 { 1003 struct adapter *sc; 1004 1005 sc = ddi_get_soft_state(t4_list, getminor(dev)); 1006 if (sc == NULL) 1007 return (EINVAL); 1008 1009 (void) atomic_swap_uint(&sc->open, 0); 1010 return (0); 1011 } 1012 1013 /* ARGSUSED */ 1014 static int 1015 t4_cb_ioctl(dev_t dev, int cmd, intptr_t d, int mode, cred_t *credp, int *rp) 1016 { 1017 int instance; 1018 struct adapter *sc; 1019 void *data = (void *)d; 1020 1021 if (crgetuid(credp) != 0) 1022 return (EPERM); 1023 1024 instance = getminor(dev); 1025 sc = ddi_get_soft_state(t4_list, instance); 1026 if (sc == NULL) 1027 return (EINVAL); 1028 1029 return (t4_ioctl(sc, cmd, data, mode)); 1030 } 1031 1032 static unsigned int 1033 getpf(struct adapter *sc) 1034 { 1035 int rc, *data; 1036 uint_t n, pf; 1037 1038 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, sc->dip, 1039 DDI_PROP_DONTPASS, "reg", &data, &n); 1040 if (rc != DDI_SUCCESS) { 1041 cxgb_printf(sc->dip, CE_WARN, 1042 "failed to lookup \"reg\" property: %d", rc); 1043 return (0xff); 1044 } 1045 1046 pf = PCI_REG_FUNC_G(data[0]); 1047 ddi_prop_free(data); 1048 1049 return (pf); 1050 } 1051 1052 /* 1053 * Install a compatible firmware (if required), establish contact with it, 1054 * become the master, and reset the device. 1055 */ 1056 static int 1057 prep_firmware(struct adapter *sc) 1058 { 1059 int rc; 1060 size_t fw_size; 1061 int reset = 1; 1062 enum dev_state state; 1063 unsigned char *fw_data; 1064 struct fw_hdr *card_fw, *hdr; 1065 const char *fw_file = NULL; 1066 firmware_handle_t fw_hdl; 1067 struct fw_info fi, *fw_info = &fi; 1068 1069 struct driver_properties *p = &sc->props; 1070 1071 /* Contact firmware, request master */ 1072 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MUST, &state); 1073 if (rc < 0) { 1074 rc = -rc; 1075 cxgb_printf(sc->dip, CE_WARN, 1076 "failed to connect to the firmware: %d.", rc); 1077 return (rc); 1078 } 1079 1080 if (rc == sc->mbox) 1081 sc->flags |= MASTER_PF; 1082 1083 /* We may need FW version info for later reporting */ 1084 t4_get_version_info(sc); 1085 1086 switch(CHELSIO_CHIP_VERSION(sc->params.chip)) { 1087 case CHELSIO_T4: 1088 fw_file = "t4fw.bin"; 1089 break; 1090 case CHELSIO_T5: 1091 fw_file = "t5fw.bin"; 1092 break; 1093 case CHELSIO_T6: 1094 fw_file = "t6fw.bin"; 1095 break; 1096 default: 1097 cxgb_printf(sc->dip, CE_WARN, "Adapter type not supported\n"); 1098 return (EINVAL); 1099 } 1100 1101 if (firmware_open(T4_PORT_NAME, fw_file, &fw_hdl) != 0) { 1102 cxgb_printf(sc->dip, CE_WARN, "Could not open %s\n", fw_file); 1103 return (EINVAL); 1104 } 1105 1106 fw_size = firmware_get_size(fw_hdl); 1107 1108 if (fw_size < sizeof (struct fw_hdr)) { 1109 cxgb_printf(sc->dip, CE_WARN, "%s is too small (%ld bytes)\n", 1110 fw_file, fw_size); 1111 firmware_close(fw_hdl); 1112 return (EINVAL); 1113 } 1114 1115 if (fw_size > FLASH_FW_MAX_SIZE) { 1116 cxgb_printf(sc->dip, CE_WARN, 1117 "%s is too large (%ld bytes, max allowed is %ld)\n", 1118 fw_file, fw_size, FLASH_FW_MAX_SIZE); 1119 firmware_close(fw_hdl); 1120 return (EFBIG); 1121 } 1122 1123 fw_data = kmem_zalloc(fw_size, KM_SLEEP); 1124 if (firmware_read(fw_hdl, 0, fw_data, fw_size) != 0) { 1125 cxgb_printf(sc->dip, CE_WARN, "Failed to read from %s\n", 1126 fw_file); 1127 firmware_close(fw_hdl); 1128 kmem_free(fw_data, fw_size); 1129 return (EINVAL); 1130 } 1131 firmware_close(fw_hdl); 1132 1133 bzero(fw_info, sizeof (*fw_info)); 1134 fw_info->chip = CHELSIO_CHIP_VERSION(sc->params.chip); 1135 1136 hdr = (struct fw_hdr *)fw_data; 1137 fw_info->fw_hdr.fw_ver = hdr->fw_ver; 1138 fw_info->fw_hdr.chip = hdr->chip; 1139 fw_info->fw_hdr.intfver_nic = hdr->intfver_nic; 1140 fw_info->fw_hdr.intfver_vnic = hdr->intfver_vnic; 1141 fw_info->fw_hdr.intfver_ofld = hdr->intfver_ofld; 1142 fw_info->fw_hdr.intfver_ri = hdr->intfver_ri; 1143 fw_info->fw_hdr.intfver_iscsipdu = hdr->intfver_iscsipdu; 1144 fw_info->fw_hdr.intfver_iscsi = hdr->intfver_iscsi; 1145 fw_info->fw_hdr.intfver_fcoepdu = hdr->intfver_fcoepdu; 1146 fw_info->fw_hdr.intfver_fcoe = hdr->intfver_fcoe; 1147 1148 /* allocate memory to read the header of the firmware on the card */ 1149 card_fw = kmem_zalloc(sizeof (*card_fw), KM_SLEEP); 1150 1151 rc = -t4_prep_fw(sc, fw_info, fw_data, fw_size, card_fw, 1152 p->t4_fw_install, state, &reset); 1153 1154 kmem_free(card_fw, sizeof (*card_fw)); 1155 kmem_free(fw_data, fw_size); 1156 1157 if (rc != 0) { 1158 cxgb_printf(sc->dip, CE_WARN, 1159 "failed to install firmware: %d", rc); 1160 return (rc); 1161 } else { 1162 /* refresh */ 1163 (void) t4_check_fw_version(sc); 1164 } 1165 1166 /* Reset device */ 1167 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 1168 if (rc != 0) { 1169 cxgb_printf(sc->dip, CE_WARN, 1170 "firmware reset failed: %d.", rc); 1171 if (rc != ETIMEDOUT && rc != EIO) 1172 (void) t4_fw_bye(sc, sc->mbox); 1173 return (rc); 1174 } 1175 1176 /* Partition adapter resources as specified in the config file. */ 1177 if (sc->flags & MASTER_PF) { 1178 /* Handle default vs special T4 config file */ 1179 1180 rc = partition_resources(sc); 1181 if (rc != 0) 1182 goto err; /* error message displayed already */ 1183 } 1184 1185 sc->flags |= FW_OK; 1186 return (0); 1187 err: 1188 return (rc); 1189 1190 } 1191 1192 static const struct memwin t4_memwin[] = { 1193 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 1194 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 1195 { MEMWIN2_BASE, MEMWIN2_APERTURE } 1196 }; 1197 1198 static const struct memwin t5_memwin[] = { 1199 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 1200 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 1201 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 1202 }; 1203 1204 #define FW_PARAM_DEV(param) \ 1205 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 1206 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 1207 #define FW_PARAM_PFVF(param) \ 1208 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 1209 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 1210 1211 /* 1212 * Verify that the memory range specified by the memtype/offset/len pair is 1213 * valid and lies entirely within the memtype specified. The global address of 1214 * the start of the range is returned in addr. 1215 */ 1216 int 1217 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len, 1218 uint32_t *addr) 1219 { 1220 uint32_t em, addr_len, maddr, mlen; 1221 1222 /* Memory can only be accessed in naturally aligned 4 byte units */ 1223 if (off & 3 || len & 3 || len == 0) 1224 return (EINVAL); 1225 1226 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 1227 switch (mtype) { 1228 case MEM_EDC0: 1229 if (!(em & F_EDRAM0_ENABLE)) 1230 return (EINVAL); 1231 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 1232 maddr = G_EDRAM0_BASE(addr_len) << 20; 1233 mlen = G_EDRAM0_SIZE(addr_len) << 20; 1234 break; 1235 case MEM_EDC1: 1236 if (!(em & F_EDRAM1_ENABLE)) 1237 return (EINVAL); 1238 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 1239 maddr = G_EDRAM1_BASE(addr_len) << 20; 1240 mlen = G_EDRAM1_SIZE(addr_len) << 20; 1241 break; 1242 case MEM_MC: 1243 if (!(em & F_EXT_MEM_ENABLE)) 1244 return (EINVAL); 1245 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 1246 maddr = G_EXT_MEM_BASE(addr_len) << 20; 1247 mlen = G_EXT_MEM_SIZE(addr_len) << 20; 1248 break; 1249 case MEM_MC1: 1250 if (is_t4(sc->params.chip) || !(em & F_EXT_MEM1_ENABLE)) 1251 return (EINVAL); 1252 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 1253 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 1254 mlen = G_EXT_MEM1_SIZE(addr_len) << 20; 1255 break; 1256 default: 1257 return (EINVAL); 1258 } 1259 1260 if (mlen > 0 && off < mlen && off + len <= mlen) { 1261 *addr = maddr + off; /* global address */ 1262 return (0); 1263 } 1264 1265 return (EFAULT); 1266 } 1267 1268 void 1269 memwin_info(struct adapter *sc, int win, uint32_t *base, uint32_t *aperture) 1270 { 1271 const struct memwin *mw; 1272 1273 if (is_t4(sc->params.chip)) { 1274 mw = &t4_memwin[win]; 1275 } else { 1276 mw = &t5_memwin[win]; 1277 } 1278 1279 if (base != NULL) 1280 *base = mw->base; 1281 if (aperture != NULL) 1282 *aperture = mw->aperture; 1283 } 1284 1285 /* 1286 * Upload configuration file to card's memory. 1287 */ 1288 static int 1289 upload_config_file(struct adapter *sc, uint32_t *mt, uint32_t *ma) 1290 { 1291 int rc = 0; 1292 size_t cflen, cfbaselen; 1293 u_int i, n; 1294 uint32_t param, val, addr, mtype, maddr; 1295 uint32_t off, mw_base, mw_aperture; 1296 uint32_t *cfdata, *cfbase; 1297 firmware_handle_t fw_hdl; 1298 const char *cfg_file = NULL; 1299 1300 /* Figure out where the firmware wants us to upload it. */ 1301 param = FW_PARAM_DEV(CF); 1302 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 1303 if (rc != 0) { 1304 /* Firmwares without config file support will fail this way */ 1305 cxgb_printf(sc->dip, CE_WARN, 1306 "failed to query config file location: %d.\n", rc); 1307 return (rc); 1308 } 1309 *mt = mtype = G_FW_PARAMS_PARAM_Y(val); 1310 *ma = maddr = G_FW_PARAMS_PARAM_Z(val) << 16; 1311 1312 switch (CHELSIO_CHIP_VERSION(sc->params.chip)) { 1313 case CHELSIO_T4: 1314 cfg_file = "t4fw_cfg.txt"; 1315 break; 1316 case CHELSIO_T5: 1317 cfg_file = "t5fw_cfg.txt"; 1318 break; 1319 case CHELSIO_T6: 1320 cfg_file = "t6fw_cfg.txt"; 1321 break; 1322 default: 1323 cxgb_printf(sc->dip, CE_WARN, "Invalid Adapter detected\n"); 1324 return EINVAL; 1325 } 1326 1327 if (firmware_open(T4_PORT_NAME, cfg_file, &fw_hdl) != 0) { 1328 cxgb_printf(sc->dip, CE_WARN, "Could not open %s\n", cfg_file); 1329 return EINVAL; 1330 } 1331 1332 cflen = firmware_get_size(fw_hdl); 1333 /* 1334 * Truncate the length to a multiple of uint32_ts. The configuration 1335 * text files have trailing comments (and hopefully always will) so 1336 * nothing important is lost. 1337 */ 1338 cflen &= ~3; 1339 1340 if (cflen > FLASH_CFG_MAX_SIZE) { 1341 cxgb_printf(sc->dip, CE_WARN, 1342 "config file too long (%d, max allowed is %d). ", 1343 cflen, FLASH_CFG_MAX_SIZE); 1344 firmware_close(fw_hdl); 1345 return (EFBIG); 1346 } 1347 1348 rc = validate_mt_off_len(sc, mtype, maddr, cflen, &addr); 1349 if (rc != 0) { 1350 cxgb_printf(sc->dip, CE_WARN, 1351 "%s: addr (%d/0x%x) or len %d is not valid: %d. " 1352 "Will try to use the config on the card, if any.\n", 1353 __func__, mtype, maddr, cflen, rc); 1354 firmware_close(fw_hdl); 1355 return (EFAULT); 1356 } 1357 1358 cfbaselen = cflen; 1359 cfbase = cfdata = kmem_zalloc(cflen, KM_SLEEP); 1360 if (firmware_read(fw_hdl, 0, cfdata, cflen) != 0) { 1361 cxgb_printf(sc->dip, CE_WARN, "Failed to read from %s\n", 1362 cfg_file); 1363 firmware_close(fw_hdl); 1364 kmem_free(cfbase, cfbaselen); 1365 return EINVAL; 1366 } 1367 firmware_close(fw_hdl); 1368 1369 memwin_info(sc, 2, &mw_base, &mw_aperture); 1370 while (cflen) { 1371 off = position_memwin(sc, 2, addr); 1372 n = min(cflen, mw_aperture - off); 1373 for (i = 0; i < n; i += 4) 1374 t4_write_reg(sc, mw_base + off + i, *cfdata++); 1375 cflen -= n; 1376 addr += n; 1377 } 1378 1379 kmem_free(cfbase, cfbaselen); 1380 1381 return (rc); 1382 } 1383 1384 /* 1385 * Partition chip resources for use between various PFs, VFs, etc. This is done 1386 * by uploading the firmware configuration file to the adapter and instructing 1387 * the firmware to process it. 1388 */ 1389 static int 1390 partition_resources(struct adapter *sc) 1391 { 1392 int rc; 1393 struct fw_caps_config_cmd caps; 1394 uint32_t mtype, maddr, finicsum, cfcsum; 1395 1396 rc = upload_config_file(sc, &mtype, &maddr); 1397 if (rc != 0) { 1398 mtype = FW_MEMTYPE_CF_FLASH; 1399 maddr = t4_flash_cfg_addr(sc); 1400 } 1401 1402 bzero(&caps, sizeof (caps)); 1403 caps.op_to_write = BE_32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1404 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1405 caps.cfvalid_to_len16 = BE_32(F_FW_CAPS_CONFIG_CMD_CFVALID | 1406 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 1407 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) | FW_LEN16(caps)); 1408 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof (caps), &caps); 1409 if (rc != 0) { 1410 cxgb_printf(sc->dip, CE_WARN, 1411 "failed to pre-process config file: %d.\n", rc); 1412 return (rc); 1413 } 1414 1415 finicsum = ntohl(caps.finicsum); 1416 cfcsum = ntohl(caps.cfcsum); 1417 if (finicsum != cfcsum) { 1418 cxgb_printf(sc->dip, CE_WARN, 1419 "WARNING: config file checksum mismatch: %08x %08x\n", 1420 finicsum, cfcsum); 1421 } 1422 sc->cfcsum = cfcsum; 1423 1424 /* TODO: Need to configure this correctly */ 1425 caps.toecaps = htons(FW_CAPS_CONFIG_TOE); 1426 caps.iscsicaps = 0; 1427 caps.rdmacaps = 0; 1428 caps.fcoecaps = 0; 1429 /* TODO: Disable VNIC cap for now */ 1430 caps.niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM); 1431 1432 caps.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1433 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 1434 caps.cfvalid_to_len16 = htonl(FW_LEN16(caps)); 1435 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof (caps), NULL); 1436 if (rc != 0) { 1437 cxgb_printf(sc->dip, CE_WARN, 1438 "failed to process config file: %d.\n", rc); 1439 return (rc); 1440 } 1441 1442 return (0); 1443 } 1444 1445 /* 1446 * Tweak configuration based on module parameters, etc. Most of these have 1447 * defaults assigned to them by Firmware Configuration Files (if we're using 1448 * them) but need to be explicitly set if we're using hard-coded 1449 * initialization. But even in the case of using Firmware Configuration 1450 * Files, we'd like to expose the ability to change these via module 1451 * parameters so these are essentially common tweaks/settings for 1452 * Configuration Files and hard-coded initialization ... 1453 */ 1454 static int 1455 adap__pre_init_tweaks(struct adapter *sc) 1456 { 1457 int rx_dma_offset = 2; /* Offset of RX packets into DMA buffers */ 1458 1459 /* 1460 * Fix up various Host-Dependent Parameters like Page Size, Cache 1461 * Line Size, etc. The firmware default is for a 4KB Page Size and 1462 * 64B Cache Line Size ... 1463 */ 1464 (void) t4_fixup_host_params_compat(sc, PAGE_SIZE, CACHE_LINE, T5_LAST_REV); 1465 1466 t4_set_reg_field(sc, A_SGE_CONTROL, 1467 V_PKTSHIFT(M_PKTSHIFT), V_PKTSHIFT(rx_dma_offset)); 1468 1469 return 0; 1470 } 1471 /* 1472 * Retrieve parameters that are needed (or nice to have) prior to calling 1473 * t4_sge_init and t4_fw_initialize. 1474 */ 1475 static int 1476 get_params__pre_init(struct adapter *sc) 1477 { 1478 int rc; 1479 uint32_t param[2], val[2]; 1480 struct fw_devlog_cmd cmd; 1481 struct devlog_params *dlog = &sc->params.devlog; 1482 1483 /* 1484 * Grab the raw VPD parameters. 1485 */ 1486 rc = -t4_get_raw_vpd_params(sc, &sc->params.vpd); 1487 if (rc != 0) { 1488 cxgb_printf(sc->dip, CE_WARN, 1489 "failed to query VPD parameters (pre_init): %d.\n", rc); 1490 return (rc); 1491 } 1492 1493 param[0] = FW_PARAM_DEV(PORTVEC); 1494 param[1] = FW_PARAM_DEV(CCLK); 1495 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 1496 if (rc != 0) { 1497 cxgb_printf(sc->dip, CE_WARN, 1498 "failed to query parameters (pre_init): %d.\n", rc); 1499 return (rc); 1500 } 1501 1502 sc->params.portvec = val[0]; 1503 sc->params.nports = 0; 1504 while (val[0]) { 1505 sc->params.nports++; 1506 val[0] &= val[0] - 1; 1507 } 1508 1509 sc->params.vpd.cclk = val[1]; 1510 1511 /* Read device log parameters. */ 1512 bzero(&cmd, sizeof (cmd)); 1513 cmd.op_to_write = htonl(V_FW_CMD_OP(FW_DEVLOG_CMD) | 1514 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1515 cmd.retval_len16 = htonl(FW_LEN16(cmd)); 1516 rc = -t4_wr_mbox(sc, sc->mbox, &cmd, sizeof (cmd), &cmd); 1517 if (rc != 0) { 1518 cxgb_printf(sc->dip, CE_WARN, 1519 "failed to get devlog parameters: %d.\n", rc); 1520 bzero(dlog, sizeof (*dlog)); 1521 rc = 0; /* devlog isn't critical for device operation */ 1522 } else { 1523 val[0] = ntohl(cmd.memtype_devlog_memaddr16_devlog); 1524 dlog->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(val[0]); 1525 dlog->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(val[0]) << 4; 1526 dlog->size = ntohl(cmd.memsize_devlog); 1527 } 1528 1529 return (rc); 1530 } 1531 1532 /* 1533 * Retrieve various parameters that are of interest to the driver. The device 1534 * has been initialized by the firmware at this point. 1535 */ 1536 static int 1537 get_params__post_init(struct adapter *sc) 1538 { 1539 int rc; 1540 uint32_t param[7], val[7]; 1541 struct fw_caps_config_cmd caps; 1542 1543 param[0] = FW_PARAM_PFVF(IQFLINT_START); 1544 param[1] = FW_PARAM_PFVF(EQ_START); 1545 param[2] = FW_PARAM_PFVF(FILTER_START); 1546 param[3] = FW_PARAM_PFVF(FILTER_END); 1547 param[4] = FW_PARAM_PFVF(L2T_START); 1548 param[5] = FW_PARAM_PFVF(L2T_END); 1549 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 1550 if (rc != 0) { 1551 cxgb_printf(sc->dip, CE_WARN, 1552 "failed to query parameters (post_init): %d.\n", rc); 1553 return (rc); 1554 } 1555 1556 /* LINTED: E_ASSIGN_NARROW_CONV */ 1557 sc->sge.iq_start = val[0]; 1558 sc->sge.eq_start = val[1]; 1559 sc->tids.ftid_base = val[2]; 1560 sc->tids.nftids = val[3] - val[2] + 1; 1561 sc->vres.l2t.start = val[4]; 1562 sc->vres.l2t.size = val[5] - val[4] + 1; 1563 1564 param[0] = FW_PARAM_PFVF(IQFLINT_END); 1565 param[1] = FW_PARAM_PFVF(EQ_END); 1566 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 1567 if (rc != 0) { 1568 cxgb_printf(sc->dip, CE_WARN, 1569 "failed to query eq/iq map size parameters (post_init): %d.\n", 1570 rc); 1571 return (rc); 1572 } 1573 1574 sc->sge.iqmap_sz = val[0] - sc->sge.iq_start + 1; 1575 sc->sge.eqmap_sz = val[1] - sc->sge.eq_start + 1; 1576 1577 /* get capabilites */ 1578 bzero(&caps, sizeof (caps)); 1579 caps.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1580 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1581 caps.cfvalid_to_len16 = htonl(FW_LEN16(caps)); 1582 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof (caps), &caps); 1583 if (rc != 0) { 1584 cxgb_printf(sc->dip, CE_WARN, 1585 "failed to get card capabilities: %d.\n", rc); 1586 return (rc); 1587 } 1588 1589 if (caps.toecaps != 0) { 1590 /* query offload-related parameters */ 1591 param[0] = FW_PARAM_DEV(NTID); 1592 param[1] = FW_PARAM_PFVF(SERVER_START); 1593 param[2] = FW_PARAM_PFVF(SERVER_END); 1594 param[3] = FW_PARAM_PFVF(TDDP_START); 1595 param[4] = FW_PARAM_PFVF(TDDP_END); 1596 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 1597 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 1598 if (rc != 0) { 1599 cxgb_printf(sc->dip, CE_WARN, 1600 "failed to query TOE parameters: %d.\n", rc); 1601 return (rc); 1602 } 1603 sc->tids.ntids = val[0]; 1604 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 1605 sc->tids.stid_base = val[1]; 1606 sc->tids.nstids = val[2] - val[1] + 1; 1607 sc->vres.ddp.start = val[3]; 1608 sc->vres.ddp.size = val[4] - val[3] + 1; 1609 sc->params.ofldq_wr_cred = val[5]; 1610 sc->params.offload = 1; 1611 } 1612 1613 rc = -t4_get_pfres(sc); 1614 if (rc != 0) { 1615 cxgb_printf(sc->dip, CE_WARN, 1616 "failed to query PF resource params: %d.\n", rc); 1617 return (rc); 1618 } 1619 1620 /* These are finalized by FW initialization, load their values now */ 1621 val[0] = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 1622 sc->params.tp.tre = G_TIMERRESOLUTION(val[0]); 1623 sc->params.tp.dack_re = G_DELAYEDACKRESOLUTION(val[0]); 1624 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 1625 1626 return (rc); 1627 } 1628 1629 static int 1630 set_params__post_init(struct adapter *sc) 1631 { 1632 uint32_t param, val; 1633 1634 /* ask for encapsulated CPLs */ 1635 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 1636 val = 1; 1637 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 1638 1639 return (0); 1640 } 1641 1642 /* TODO: verify */ 1643 static void 1644 setup_memwin(struct adapter *sc) 1645 { 1646 pci_regspec_t *data; 1647 int rc; 1648 uint_t n; 1649 uintptr_t bar0; 1650 uintptr_t mem_win0_base, mem_win1_base, mem_win2_base; 1651 uintptr_t mem_win2_aperture; 1652 1653 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, sc->dip, 1654 DDI_PROP_DONTPASS, "assigned-addresses", (int **)&data, &n); 1655 if (rc != DDI_SUCCESS) { 1656 cxgb_printf(sc->dip, CE_WARN, 1657 "failed to lookup \"assigned-addresses\" property: %d", rc); 1658 return; 1659 } 1660 n /= sizeof (*data); 1661 1662 bar0 = ((uint64_t)data[0].pci_phys_mid << 32) | data[0].pci_phys_low; 1663 ddi_prop_free(data); 1664 1665 if (is_t4(sc->params.chip)) { 1666 mem_win0_base = bar0 + MEMWIN0_BASE; 1667 mem_win1_base = bar0 + MEMWIN1_BASE; 1668 mem_win2_base = bar0 + MEMWIN2_BASE; 1669 mem_win2_aperture = MEMWIN2_APERTURE; 1670 } else { 1671 /* For T5, only relative offset inside the PCIe BAR is passed */ 1672 mem_win0_base = MEMWIN0_BASE; 1673 mem_win1_base = MEMWIN1_BASE; 1674 mem_win2_base = MEMWIN2_BASE_T5; 1675 mem_win2_aperture = MEMWIN2_APERTURE_T5; 1676 } 1677 1678 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 0), 1679 mem_win0_base | V_BIR(0) | 1680 V_WINDOW(ilog2(MEMWIN0_APERTURE) - 10)); 1681 1682 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 1), 1683 mem_win1_base | V_BIR(0) | 1684 V_WINDOW(ilog2(MEMWIN1_APERTURE) - 10)); 1685 1686 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2), 1687 mem_win2_base | V_BIR(0) | 1688 V_WINDOW(ilog2(mem_win2_aperture) - 10)); 1689 1690 /* flush */ 1691 (void)t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 1692 } 1693 1694 /* 1695 * Positions the memory window such that it can be used to access the specified 1696 * address in the chip's address space. The return value is the offset of addr 1697 * from the start of the window. 1698 */ 1699 uint32_t 1700 position_memwin(struct adapter *sc, int n, uint32_t addr) 1701 { 1702 uint32_t start, pf; 1703 uint32_t reg; 1704 1705 if (addr & 3) { 1706 cxgb_printf(sc->dip, CE_WARN, 1707 "addr (0x%x) is not at a 4B boundary.\n", addr); 1708 return (EFAULT); 1709 } 1710 1711 if (is_t4(sc->params.chip)) { 1712 pf = 0; 1713 start = addr & ~0xf; /* start must be 16B aligned */ 1714 } else { 1715 pf = V_PFNUM(sc->pf); 1716 start = addr & ~0x7f; /* start must be 128B aligned */ 1717 } 1718 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, n); 1719 1720 t4_write_reg(sc, reg, start | pf); 1721 (void) t4_read_reg(sc, reg); 1722 1723 return (addr - start); 1724 } 1725 1726 1727 /* 1728 * Reads the named property and fills up the "data" array (which has at least 1729 * "count" elements). We first try and lookup the property for our dev_t and 1730 * then retry with DDI_DEV_T_ANY if it's not found. 1731 * 1732 * Returns non-zero if the property was found and "data" has been updated. 1733 */ 1734 static int 1735 prop_lookup_int_array(struct adapter *sc, char *name, int *data, uint_t count) 1736 { 1737 dev_info_t *dip = sc->dip; 1738 dev_t dev = sc->dev; 1739 int rc, *d; 1740 uint_t i, n; 1741 1742 rc = ddi_prop_lookup_int_array(dev, dip, DDI_PROP_DONTPASS, 1743 name, &d, &n); 1744 if (rc == DDI_PROP_SUCCESS) 1745 goto found; 1746 1747 if (rc != DDI_PROP_NOT_FOUND) { 1748 cxgb_printf(dip, CE_WARN, 1749 "failed to lookup property %s for minor %d: %d.", 1750 name, getminor(dev), rc); 1751 return (0); 1752 } 1753 1754 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1755 name, &d, &n); 1756 if (rc == DDI_PROP_SUCCESS) 1757 goto found; 1758 1759 if (rc != DDI_PROP_NOT_FOUND) { 1760 cxgb_printf(dip, CE_WARN, 1761 "failed to lookup property %s: %d.", name, rc); 1762 return (0); 1763 } 1764 1765 return (0); 1766 1767 found: 1768 if (n > count) { 1769 cxgb_printf(dip, CE_NOTE, 1770 "property %s has too many elements (%d), ignoring extras", 1771 name, n); 1772 } 1773 1774 for (i = 0; i < n && i < count; i++) 1775 data[i] = d[i]; 1776 ddi_prop_free(d); 1777 1778 return (1); 1779 } 1780 1781 static int 1782 prop_lookup_int(struct adapter *sc, char *name, int defval) 1783 { 1784 int rc; 1785 1786 rc = ddi_prop_get_int(sc->dev, sc->dip, DDI_PROP_DONTPASS, name, -1); 1787 if (rc != -1) 1788 return (rc); 1789 1790 return (ddi_prop_get_int(DDI_DEV_T_ANY, sc->dip, DDI_PROP_DONTPASS, 1791 name, defval)); 1792 } 1793 1794 static int 1795 init_driver_props(struct adapter *sc, struct driver_properties *p) 1796 { 1797 dev_t dev = sc->dev; 1798 dev_info_t *dip = sc->dip; 1799 int i, *data; 1800 uint_t tmr[SGE_NTIMERS] = {5, 10, 20, 50, 100, 200}; 1801 uint_t cnt[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 1802 1803 /* 1804 * Holdoff timer 1805 */ 1806 data = &p->timer_val[0]; 1807 for (i = 0; i < SGE_NTIMERS; i++) 1808 data[i] = tmr[i]; 1809 (void) prop_lookup_int_array(sc, "holdoff-timer-values", data, 1810 SGE_NTIMERS); 1811 for (i = 0; i < SGE_NTIMERS; i++) { 1812 int limit = 200U; 1813 if (data[i] > limit) { 1814 cxgb_printf(dip, CE_WARN, 1815 "holdoff timer %d is too high (%d), lowered to %d.", 1816 i, data[i], limit); 1817 data[i] = limit; 1818 } 1819 } 1820 (void) ddi_prop_update_int_array(dev, dip, "holdoff-timer-values", 1821 data, SGE_NTIMERS); 1822 1823 /* 1824 * Holdoff packet counter 1825 */ 1826 data = &p->counter_val[0]; 1827 for (i = 0; i < SGE_NCOUNTERS; i++) 1828 data[i] = cnt[i]; 1829 (void) prop_lookup_int_array(sc, "holdoff-pkt-counter-values", data, 1830 SGE_NCOUNTERS); 1831 for (i = 0; i < SGE_NCOUNTERS; i++) { 1832 int limit = M_THRESHOLD_0; 1833 if (data[i] > limit) { 1834 cxgb_printf(dip, CE_WARN, 1835 "holdoff pkt-counter %d is too high (%d), " 1836 "lowered to %d.", i, data[i], limit); 1837 data[i] = limit; 1838 } 1839 } 1840 (void) ddi_prop_update_int_array(dev, dip, "holdoff-pkt-counter-values", 1841 data, SGE_NCOUNTERS); 1842 1843 /* 1844 * Maximum # of tx and rx queues to use for each 1845 * 100G, 40G, 25G, 10G and 1G port. 1846 */ 1847 p->max_ntxq_10g = prop_lookup_int(sc, "max-ntxq-10G-port", 8); 1848 (void) ddi_prop_update_int(dev, dip, "max-ntxq-10G-port", 1849 p->max_ntxq_10g); 1850 1851 p->max_nrxq_10g = prop_lookup_int(sc, "max-nrxq-10G-port", 8); 1852 (void) ddi_prop_update_int(dev, dip, "max-nrxq-10G-port", 1853 p->max_nrxq_10g); 1854 1855 p->max_ntxq_1g = prop_lookup_int(sc, "max-ntxq-1G-port", 2); 1856 (void) ddi_prop_update_int(dev, dip, "max-ntxq-1G-port", 1857 p->max_ntxq_1g); 1858 1859 p->max_nrxq_1g = prop_lookup_int(sc, "max-nrxq-1G-port", 2); 1860 (void) ddi_prop_update_int(dev, dip, "max-nrxq-1G-port", 1861 p->max_nrxq_1g); 1862 1863 /* 1864 * Holdoff parameters for 10G and 1G ports. 1865 */ 1866 p->tmr_idx_10g = prop_lookup_int(sc, "holdoff-timer-idx-10G", 0); 1867 (void) ddi_prop_update_int(dev, dip, "holdoff-timer-idx-10G", 1868 p->tmr_idx_10g); 1869 1870 p->pktc_idx_10g = prop_lookup_int(sc, "holdoff-pktc-idx-10G", 2); 1871 (void) ddi_prop_update_int(dev, dip, "holdoff-pktc-idx-10G", 1872 p->pktc_idx_10g); 1873 1874 p->tmr_idx_1g = prop_lookup_int(sc, "holdoff-timer-idx-1G", 0); 1875 (void) ddi_prop_update_int(dev, dip, "holdoff-timer-idx-1G", 1876 p->tmr_idx_1g); 1877 1878 p->pktc_idx_1g = prop_lookup_int(sc, "holdoff-pktc-idx-1G", 2); 1879 (void) ddi_prop_update_int(dev, dip, "holdoff-pktc-idx-1G", 1880 p->pktc_idx_1g); 1881 1882 /* 1883 * Size (number of entries) of each tx and rx queue. 1884 */ 1885 i = prop_lookup_int(sc, "qsize-txq", TX_EQ_QSIZE); 1886 p->qsize_txq = max(i, 128); 1887 if (p->qsize_txq != i) { 1888 cxgb_printf(dip, CE_WARN, 1889 "using %d instead of %d as the tx queue size", 1890 p->qsize_txq, i); 1891 } 1892 (void) ddi_prop_update_int(dev, dip, "qsize-txq", p->qsize_txq); 1893 1894 i = prop_lookup_int(sc, "qsize-rxq", RX_IQ_QSIZE); 1895 p->qsize_rxq = max(i, 128); 1896 while (p->qsize_rxq & 7) 1897 p->qsize_rxq--; 1898 if (p->qsize_rxq != i) { 1899 cxgb_printf(dip, CE_WARN, 1900 "using %d instead of %d as the rx queue size", 1901 p->qsize_rxq, i); 1902 } 1903 (void) ddi_prop_update_int(dev, dip, "qsize-rxq", p->qsize_rxq); 1904 1905 /* 1906 * Interrupt types allowed. 1907 * Bits 0, 1, 2 = INTx, MSI, MSI-X respectively. See sys/ddi_intr.h 1908 */ 1909 p->intr_types = prop_lookup_int(sc, "interrupt-types", 1910 DDI_INTR_TYPE_MSIX | DDI_INTR_TYPE_MSI | DDI_INTR_TYPE_FIXED); 1911 (void) ddi_prop_update_int(dev, dip, "interrupt-types", p->intr_types); 1912 1913 /* 1914 * Forwarded interrupt queues. Create this property to force the driver 1915 * to use forwarded interrupt queues. 1916 */ 1917 if (ddi_prop_exists(dev, dip, DDI_PROP_DONTPASS, 1918 "interrupt-forwarding") != 0 || 1919 ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1920 "interrupt-forwarding") != 0) { 1921 UNIMPLEMENTED(); 1922 (void) ddi_prop_create(dev, dip, DDI_PROP_CANSLEEP, 1923 "interrupt-forwarding", NULL, 0); 1924 } 1925 1926 /* 1927 * Write combining 1928 * 0 to disable, 1 to enable 1929 */ 1930 p->wc = prop_lookup_int(sc, "write-combine", 1); 1931 cxgb_printf(dip, CE_WARN, "write-combine: using of %d", p->wc); 1932 if (p->wc != 0 && p->wc != 1) { 1933 cxgb_printf(dip, CE_WARN, 1934 "write-combine: using 1 instead of %d", p->wc); 1935 p->wc = 1; 1936 } 1937 (void) ddi_prop_update_int(dev, dip, "write-combine", p->wc); 1938 1939 p->t4_fw_install = prop_lookup_int(sc, "t4_fw_install", 1); 1940 if (p->t4_fw_install != 0 && p->t4_fw_install != 2) 1941 p->t4_fw_install = 1; 1942 (void) ddi_prop_update_int(dev, dip, "t4_fw_install", p->t4_fw_install); 1943 1944 /* Multiple Rings */ 1945 p->multi_rings = prop_lookup_int(sc, "multi-rings", 1); 1946 if (p->multi_rings != 0 && p->multi_rings != 1) { 1947 cxgb_printf(dip, CE_NOTE, 1948 "multi-rings: using value 1 instead of %d", p->multi_rings); 1949 p->multi_rings = 1; 1950 } 1951 1952 (void) ddi_prop_update_int(dev, dip, "multi-rings", p->multi_rings); 1953 1954 return (0); 1955 } 1956 1957 static int 1958 remove_extra_props(struct adapter *sc, int n10g, int n1g) 1959 { 1960 if (n10g == 0) { 1961 (void) ddi_prop_remove(sc->dev, sc->dip, "max-ntxq-10G-port"); 1962 (void) ddi_prop_remove(sc->dev, sc->dip, "max-nrxq-10G-port"); 1963 (void) ddi_prop_remove(sc->dev, sc->dip, 1964 "holdoff-timer-idx-10G"); 1965 (void) ddi_prop_remove(sc->dev, sc->dip, 1966 "holdoff-pktc-idx-10G"); 1967 } 1968 1969 if (n1g == 0) { 1970 (void) ddi_prop_remove(sc->dev, sc->dip, "max-ntxq-1G-port"); 1971 (void) ddi_prop_remove(sc->dev, sc->dip, "max-nrxq-1G-port"); 1972 (void) ddi_prop_remove(sc->dev, sc->dip, 1973 "holdoff-timer-idx-1G"); 1974 (void) ddi_prop_remove(sc->dev, sc->dip, "holdoff-pktc-idx-1G"); 1975 } 1976 1977 return (0); 1978 } 1979 1980 static int 1981 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, 1982 struct intrs_and_queues *iaq) 1983 { 1984 struct driver_properties *p = &sc->props; 1985 int rc, itype, itypes, navail, nc, n; 1986 int pfres_rxq, pfres_txq, pfresq; 1987 1988 bzero(iaq, sizeof (*iaq)); 1989 nc = ncpus; /* our snapshot of the number of CPUs */ 1990 iaq->ntxq10g = min(nc, p->max_ntxq_10g); 1991 iaq->ntxq1g = min(nc, p->max_ntxq_1g); 1992 iaq->nrxq10g = min(nc, p->max_nrxq_10g); 1993 iaq->nrxq1g = min(nc, p->max_nrxq_1g); 1994 1995 pfres_rxq = iaq->nrxq10g * n10g + iaq->nrxq1g * n1g; 1996 pfres_txq = iaq->ntxq10g * n10g + iaq->ntxq1g * n1g; 1997 1998 /* If current configuration of max number of Rxqs and Txqs exceed 1999 * the max available for all the ports under this PF, then shrink 2000 * the queues to max available. Reduce them in a way that each 2001 * port under this PF has equally distributed number of queues. 2002 * Must guarantee at least 1 queue for each port for both NIC 2003 * and Offload queues. 2004 * 2005 * neq - fixed max number of Egress queues on Tx path and Free List 2006 * queues that hold Rx payload data on Rx path. Half are reserved 2007 * for Egress queues and the other half for Free List queues. 2008 * Hence, the division by 2. 2009 * 2010 * niqflint - max number of Ingress queues with interrupts on Rx 2011 * path to receive completions that indicate Rx payload has been 2012 * posted in its associated Free List queue. Also handles Tx 2013 * completions for packets successfully transmitted on Tx path. 2014 * 2015 * nethctrl - max number of Egress queues only for Tx path. This 2016 * number is usually half of neq. However, if it became less than 2017 * neq due to lack of resources based on firmware configuration, 2018 * then take the lower value. 2019 */ 2020 while (pfres_rxq > 2021 min(sc->params.pfres.neq / 2, sc->params.pfres.niqflint)) { 2022 pfresq = pfres_rxq; 2023 2024 if (iaq->nrxq10g > 1) { 2025 iaq->nrxq10g--; 2026 pfres_rxq -= n10g; 2027 } 2028 2029 if (iaq->nrxq1g > 1) { 2030 iaq->nrxq1g--; 2031 pfres_rxq -= n1g; 2032 } 2033 2034 /* Break if nothing changed */ 2035 if (pfresq == pfres_rxq) 2036 break; 2037 } 2038 2039 while (pfres_txq > 2040 min(sc->params.pfres.neq / 2, sc->params.pfres.nethctrl)) { 2041 pfresq = pfres_txq; 2042 2043 if (iaq->ntxq10g > 1) { 2044 iaq->ntxq10g--; 2045 pfres_txq -= n10g; 2046 } 2047 2048 if (iaq->ntxq1g > 1) { 2049 iaq->ntxq1g--; 2050 pfres_txq -= n1g; 2051 } 2052 2053 /* Break if nothing changed */ 2054 if (pfresq == pfres_txq) 2055 break; 2056 } 2057 2058 rc = ddi_intr_get_supported_types(sc->dip, &itypes); 2059 if (rc != DDI_SUCCESS) { 2060 cxgb_printf(sc->dip, CE_WARN, 2061 "failed to determine supported interrupt types: %d", rc); 2062 return (rc); 2063 } 2064 2065 for (itype = DDI_INTR_TYPE_MSIX; itype; itype >>= 1) { 2066 ASSERT(itype == DDI_INTR_TYPE_MSIX || 2067 itype == DDI_INTR_TYPE_MSI || 2068 itype == DDI_INTR_TYPE_FIXED); 2069 2070 if ((itype & itypes & p->intr_types) == 0) 2071 continue; /* not supported or not allowed */ 2072 2073 navail = 0; 2074 rc = ddi_intr_get_navail(sc->dip, itype, &navail); 2075 if (rc != DDI_SUCCESS || navail == 0) { 2076 cxgb_printf(sc->dip, CE_WARN, 2077 "failed to get # of interrupts for type %d: %d", 2078 itype, rc); 2079 continue; /* carry on */ 2080 } 2081 2082 iaq->intr_type = itype; 2083 if (navail == 0) 2084 continue; 2085 2086 /* 2087 * Best option: an interrupt vector for errors, one for the 2088 * firmware event queue, and one each for each rxq (NIC as well 2089 * as offload). 2090 */ 2091 iaq->nirq = T4_EXTRA_INTR; 2092 iaq->nirq += n10g * iaq->nrxq10g; 2093 iaq->nirq += n1g * iaq->nrxq1g; 2094 2095 if (iaq->nirq <= navail && 2096 (itype != DDI_INTR_TYPE_MSI || ISP2(iaq->nirq))) { 2097 iaq->intr_fwd = 0; 2098 goto allocate; 2099 } 2100 2101 /* 2102 * Second best option: an interrupt vector for errors, one for 2103 * the firmware event queue, and one each for either NIC or 2104 * offload rxq's. 2105 */ 2106 iaq->nirq = T4_EXTRA_INTR; 2107 iaq->nirq += n10g * iaq->nrxq10g; 2108 iaq->nirq += n1g * iaq->nrxq1g; 2109 if (iaq->nirq <= navail && 2110 (itype != DDI_INTR_TYPE_MSI || ISP2(iaq->nirq))) { 2111 iaq->intr_fwd = 1; 2112 goto allocate; 2113 } 2114 2115 /* 2116 * Next best option: an interrupt vector for errors, one for the 2117 * firmware event queue, and at least one per port. At this 2118 * point we know we'll have to downsize nrxq or nofldrxq to fit 2119 * what's available to us. 2120 */ 2121 iaq->nirq = T4_EXTRA_INTR; 2122 iaq->nirq += n10g + n1g; 2123 if (iaq->nirq <= navail) { 2124 int leftover = navail - iaq->nirq; 2125 2126 if (n10g > 0) { 2127 int target = iaq->nrxq10g; 2128 2129 n = 1; 2130 while (n < target && leftover >= n10g) { 2131 leftover -= n10g; 2132 iaq->nirq += n10g; 2133 n++; 2134 } 2135 iaq->nrxq10g = min(n, iaq->nrxq10g); 2136 } 2137 2138 if (n1g > 0) { 2139 int target = iaq->nrxq1g; 2140 2141 n = 1; 2142 while (n < target && leftover >= n1g) { 2143 leftover -= n1g; 2144 iaq->nirq += n1g; 2145 n++; 2146 } 2147 iaq->nrxq1g = min(n, iaq->nrxq1g); 2148 } 2149 2150 /* We have arrived at a minimum value required to enable 2151 * per queue irq(either NIC or offload). Thus for non- 2152 * offload case, we will get a vector per queue, while 2153 * offload case, we will get a vector per offload/NIC q. 2154 * Hence enable Interrupt forwarding only for offload 2155 * case. 2156 */ 2157 if (itype != DDI_INTR_TYPE_MSI) { 2158 goto allocate; 2159 } 2160 } 2161 2162 /* 2163 * Least desirable option: one interrupt vector for everything. 2164 */ 2165 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1; 2166 iaq->intr_fwd = 1; 2167 2168 allocate: 2169 return (0); 2170 } 2171 2172 cxgb_printf(sc->dip, CE_WARN, 2173 "failed to find a usable interrupt type. supported=%d, allowed=%d", 2174 itypes, p->intr_types); 2175 return (DDI_FAILURE); 2176 } 2177 2178 static int 2179 add_child_node(struct adapter *sc, int idx) 2180 { 2181 int rc; 2182 struct port_info *pi; 2183 2184 if (idx < 0 || idx >= sc->params.nports) 2185 return (EINVAL); 2186 2187 pi = sc->port[idx]; 2188 if (pi == NULL) 2189 return (ENODEV); /* t4_port_init failed earlier */ 2190 2191 PORT_LOCK(pi); 2192 if (pi->dip != NULL) { 2193 rc = 0; /* EEXIST really, but then bus_config fails */ 2194 goto done; 2195 } 2196 2197 rc = ndi_devi_alloc(sc->dip, T4_PORT_NAME, DEVI_SID_NODEID, &pi->dip); 2198 if (rc != DDI_SUCCESS || pi->dip == NULL) { 2199 rc = ENOMEM; 2200 goto done; 2201 } 2202 2203 (void) ddi_set_parent_data(pi->dip, pi); 2204 (void) ndi_devi_bind_driver(pi->dip, 0); 2205 rc = 0; 2206 done: 2207 PORT_UNLOCK(pi); 2208 return (rc); 2209 } 2210 2211 static int 2212 remove_child_node(struct adapter *sc, int idx) 2213 { 2214 int rc; 2215 struct port_info *pi; 2216 2217 if (idx < 0 || idx >= sc->params.nports) 2218 return (EINVAL); 2219 2220 pi = sc->port[idx]; 2221 if (pi == NULL) 2222 return (ENODEV); 2223 2224 PORT_LOCK(pi); 2225 if (pi->dip == NULL) { 2226 rc = ENODEV; 2227 goto done; 2228 } 2229 2230 rc = ndi_devi_free(pi->dip); 2231 if (rc == 0) 2232 pi->dip = NULL; 2233 done: 2234 PORT_UNLOCK(pi); 2235 return (rc); 2236 } 2237 2238 static char * 2239 print_port_speed(const struct port_info *pi) 2240 { 2241 if (!pi) 2242 return "-"; 2243 2244 if (is_100G_port(pi)) 2245 return "100G"; 2246 else if (is_50G_port(pi)) 2247 return "50G"; 2248 else if (is_40G_port(pi)) 2249 return "40G"; 2250 else if (is_25G_port(pi)) 2251 return "25G"; 2252 else if (is_10G_port(pi)) 2253 return "10G"; 2254 else 2255 return "1G"; 2256 } 2257 2258 #define KS_UINIT(x) kstat_named_init(&kstatp->x, #x, KSTAT_DATA_ULONG) 2259 #define KS_CINIT(x) kstat_named_init(&kstatp->x, #x, KSTAT_DATA_CHAR) 2260 #define KS_U64INIT(x) kstat_named_init(&kstatp->x, #x, KSTAT_DATA_UINT64) 2261 #define KS_U_SET(x, y) kstatp->x.value.ul = (y) 2262 #define KS_C_SET(x, ...) \ 2263 (void) snprintf(kstatp->x.value.c, 16, __VA_ARGS__) 2264 2265 /* 2266 * t4nex:X:config 2267 */ 2268 struct t4_kstats { 2269 kstat_named_t chip_ver; 2270 kstat_named_t fw_vers; 2271 kstat_named_t tp_vers; 2272 kstat_named_t driver_version; 2273 kstat_named_t serial_number; 2274 kstat_named_t ec_level; 2275 kstat_named_t id; 2276 kstat_named_t bus_type; 2277 kstat_named_t bus_width; 2278 kstat_named_t bus_speed; 2279 kstat_named_t core_clock; 2280 kstat_named_t port_cnt; 2281 kstat_named_t port_type; 2282 kstat_named_t pci_vendor_id; 2283 kstat_named_t pci_device_id; 2284 }; 2285 static kstat_t * 2286 setup_kstats(struct adapter *sc) 2287 { 2288 kstat_t *ksp; 2289 struct t4_kstats *kstatp; 2290 int ndata; 2291 struct pci_params *p = &sc->params.pci; 2292 struct vpd_params *v = &sc->params.vpd; 2293 uint16_t pci_vendor, pci_device; 2294 2295 ndata = sizeof (struct t4_kstats) / sizeof (kstat_named_t); 2296 2297 ksp = kstat_create(T4_NEXUS_NAME, ddi_get_instance(sc->dip), "config", 2298 "nexus", KSTAT_TYPE_NAMED, ndata, 0); 2299 if (ksp == NULL) { 2300 cxgb_printf(sc->dip, CE_WARN, "failed to initialize kstats."); 2301 return (NULL); 2302 } 2303 2304 kstatp = (struct t4_kstats *)ksp->ks_data; 2305 2306 KS_UINIT(chip_ver); 2307 KS_CINIT(fw_vers); 2308 KS_CINIT(tp_vers); 2309 KS_CINIT(driver_version); 2310 KS_CINIT(serial_number); 2311 KS_CINIT(ec_level); 2312 KS_CINIT(id); 2313 KS_CINIT(bus_type); 2314 KS_CINIT(bus_width); 2315 KS_CINIT(bus_speed); 2316 KS_UINIT(core_clock); 2317 KS_UINIT(port_cnt); 2318 KS_CINIT(port_type); 2319 KS_CINIT(pci_vendor_id); 2320 KS_CINIT(pci_device_id); 2321 2322 KS_U_SET(chip_ver, sc->params.chip); 2323 KS_C_SET(fw_vers, "%d.%d.%d.%d", 2324 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 2325 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 2326 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 2327 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 2328 KS_C_SET(tp_vers, "%d.%d.%d.%d", 2329 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 2330 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 2331 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 2332 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 2333 KS_C_SET(driver_version, DRV_VERSION); 2334 KS_C_SET(serial_number, "%s", v->sn); 2335 KS_C_SET(ec_level, "%s", v->ec); 2336 KS_C_SET(id, "%s", v->id); 2337 KS_C_SET(bus_type, "pci-express"); 2338 KS_C_SET(bus_width, "x%d lanes", p->width); 2339 KS_C_SET(bus_speed, "%d", p->speed); 2340 KS_U_SET(core_clock, v->cclk); 2341 KS_U_SET(port_cnt, sc->params.nports); 2342 2343 t4_os_pci_read_cfg2(sc, PCI_CONF_VENID, &pci_vendor); 2344 KS_C_SET(pci_vendor_id, "0x%x", pci_vendor); 2345 2346 t4_os_pci_read_cfg2(sc, PCI_CONF_DEVID, &pci_device); 2347 KS_C_SET(pci_device_id, "0x%x", pci_device); 2348 2349 KS_C_SET(port_type, "%s/%s/%s/%s", 2350 print_port_speed(sc->port[0]), 2351 print_port_speed(sc->port[1]), 2352 print_port_speed(sc->port[2]), 2353 print_port_speed(sc->port[3])); 2354 2355 /* Do NOT set ksp->ks_update. These kstats do not change. */ 2356 2357 /* Install the kstat */ 2358 ksp->ks_private = (void *)sc; 2359 kstat_install(ksp); 2360 2361 return (ksp); 2362 } 2363 2364 /* 2365 * t4nex:X:stat 2366 */ 2367 struct t4_wc_kstats { 2368 kstat_named_t write_coal_success; 2369 kstat_named_t write_coal_failure; 2370 }; 2371 static kstat_t * 2372 setup_wc_kstats(struct adapter *sc) 2373 { 2374 kstat_t *ksp; 2375 struct t4_wc_kstats *kstatp; 2376 int ndata; 2377 2378 ndata = sizeof(struct t4_wc_kstats) / sizeof(kstat_named_t); 2379 ksp = kstat_create(T4_NEXUS_NAME, ddi_get_instance(sc->dip), "stats", 2380 "nexus", KSTAT_TYPE_NAMED, ndata, 0); 2381 if (ksp == NULL) { 2382 cxgb_printf(sc->dip, CE_WARN, "failed to initialize kstats."); 2383 return (NULL); 2384 } 2385 2386 kstatp = (struct t4_wc_kstats *)ksp->ks_data; 2387 2388 KS_UINIT(write_coal_success); 2389 KS_UINIT(write_coal_failure); 2390 2391 ksp->ks_update = update_wc_kstats; 2392 /* Install the kstat */ 2393 ksp->ks_private = (void *)sc; 2394 kstat_install(ksp); 2395 2396 return (ksp); 2397 } 2398 2399 static int 2400 update_wc_kstats(kstat_t *ksp, int rw) 2401 { 2402 struct t4_wc_kstats *kstatp = (struct t4_wc_kstats *)ksp->ks_data; 2403 struct adapter *sc = ksp->ks_private; 2404 uint32_t wc_total, wc_success, wc_failure; 2405 2406 if (rw == KSTAT_WRITE) 2407 return (0); 2408 2409 if (is_t5(sc->params.chip)) { 2410 wc_total = t4_read_reg(sc, A_SGE_STAT_TOTAL); 2411 wc_failure = t4_read_reg(sc, A_SGE_STAT_MATCH); 2412 wc_success = wc_total - wc_failure; 2413 } else { 2414 wc_success = 0; 2415 wc_failure = 0; 2416 } 2417 2418 KS_U_SET(write_coal_success, wc_success); 2419 KS_U_SET(write_coal_failure, wc_failure); 2420 2421 return (0); 2422 } 2423 2424 /* 2425 * cxgbe:X:fec 2426 * 2427 * This provides visibility into the errors that have been found by the 2428 * different FEC subsystems. While it's tempting to combine the two different 2429 * FEC types logically, the data that the errors tell us are pretty different 2430 * between the two. Firecode is strictly per-lane, but RS has parts that are 2431 * related to symbol distribution to lanes and also to the overall channel. 2432 */ 2433 struct cxgbe_port_fec_kstats { 2434 kstat_named_t rs_corr; 2435 kstat_named_t rs_uncorr; 2436 kstat_named_t rs_sym0_corr; 2437 kstat_named_t rs_sym1_corr; 2438 kstat_named_t rs_sym2_corr; 2439 kstat_named_t rs_sym3_corr; 2440 kstat_named_t fc_lane0_corr; 2441 kstat_named_t fc_lane0_uncorr; 2442 kstat_named_t fc_lane1_corr; 2443 kstat_named_t fc_lane1_uncorr; 2444 kstat_named_t fc_lane2_corr; 2445 kstat_named_t fc_lane2_uncorr; 2446 kstat_named_t fc_lane3_corr; 2447 kstat_named_t fc_lane3_uncorr; 2448 }; 2449 2450 static uint32_t 2451 read_fec_pair(struct port_info *pi, uint32_t lo_reg, uint32_t high_reg) 2452 { 2453 struct adapter *sc = pi->adapter; 2454 uint8_t port = pi->tx_chan; 2455 uint32_t low, high, ret; 2456 2457 low = t4_read_reg32(sc, T5_PORT_REG(port, lo_reg)); 2458 high = t4_read_reg32(sc, T5_PORT_REG(port, high_reg)); 2459 ret = low & 0xffff; 2460 ret |= (high & 0xffff) << 16; 2461 return (ret); 2462 } 2463 2464 static int 2465 update_port_fec_kstats(kstat_t *ksp, int rw) 2466 { 2467 struct cxgbe_port_fec_kstats *fec = ksp->ks_data; 2468 struct port_info *pi = ksp->ks_private; 2469 2470 if (rw == KSTAT_WRITE) { 2471 return (EACCES); 2472 } 2473 2474 /* 2475 * First go ahead and gather RS related stats. 2476 */ 2477 fec->rs_corr.value.ui64 += read_fec_pair(pi, T6_RS_FEC_CCW_LO, 2478 T6_RS_FEC_CCW_HI); 2479 fec->rs_uncorr.value.ui64 += read_fec_pair(pi, T6_RS_FEC_NCCW_LO, 2480 T6_RS_FEC_NCCW_HI); 2481 fec->rs_sym0_corr.value.ui64 += read_fec_pair(pi, T6_RS_FEC_SYMERR0_LO, 2482 T6_RS_FEC_SYMERR0_HI); 2483 fec->rs_sym1_corr.value.ui64 += read_fec_pair(pi, T6_RS_FEC_SYMERR1_LO, 2484 T6_RS_FEC_SYMERR1_HI); 2485 fec->rs_sym2_corr.value.ui64 += read_fec_pair(pi, T6_RS_FEC_SYMERR2_LO, 2486 T6_RS_FEC_SYMERR2_HI); 2487 fec->rs_sym3_corr.value.ui64 += read_fec_pair(pi, T6_RS_FEC_SYMERR3_LO, 2488 T6_RS_FEC_SYMERR3_HI); 2489 2490 /* 2491 * Now go through and try to grab Firecode/BASE-R stats. 2492 */ 2493 fec->fc_lane0_corr.value.ui64 += read_fec_pair(pi, T6_FC_FEC_L0_CERR_LO, 2494 T6_FC_FEC_L0_CERR_HI); 2495 fec->fc_lane0_uncorr.value.ui64 += read_fec_pair(pi, 2496 T6_FC_FEC_L0_NCERR_LO, T6_FC_FEC_L0_NCERR_HI); 2497 fec->fc_lane1_corr.value.ui64 += read_fec_pair(pi, T6_FC_FEC_L1_CERR_LO, 2498 T6_FC_FEC_L1_CERR_HI); 2499 fec->fc_lane1_uncorr.value.ui64 += read_fec_pair(pi, 2500 T6_FC_FEC_L1_NCERR_LO, T6_FC_FEC_L1_NCERR_HI); 2501 fec->fc_lane2_corr.value.ui64 += read_fec_pair(pi, T6_FC_FEC_L2_CERR_LO, 2502 T6_FC_FEC_L2_CERR_HI); 2503 fec->fc_lane2_uncorr.value.ui64 += read_fec_pair(pi, 2504 T6_FC_FEC_L2_NCERR_LO, T6_FC_FEC_L2_NCERR_HI); 2505 fec->fc_lane3_corr.value.ui64 += read_fec_pair(pi, T6_FC_FEC_L3_CERR_LO, 2506 T6_FC_FEC_L3_CERR_HI); 2507 fec->fc_lane3_uncorr.value.ui64 += read_fec_pair(pi, 2508 T6_FC_FEC_L3_NCERR_LO, T6_FC_FEC_L3_NCERR_HI); 2509 2510 return (0); 2511 } 2512 2513 static kstat_t * 2514 setup_port_fec_kstats(struct port_info *pi) 2515 { 2516 kstat_t *ksp; 2517 struct cxgbe_port_fec_kstats *kstatp; 2518 2519 if (!is_t6(pi->adapter->params.chip)) { 2520 return (NULL); 2521 } 2522 2523 ksp = kstat_create(T4_PORT_NAME, ddi_get_instance(pi->dip), "fec", 2524 "net", KSTAT_TYPE_NAMED, sizeof (struct cxgbe_port_fec_kstats) / 2525 sizeof (kstat_named_t), 0); 2526 if (ksp == NULL) { 2527 cxgb_printf(pi->dip, CE_WARN, "failed to initialize fec " 2528 "kstats."); 2529 return (NULL); 2530 } 2531 2532 kstatp = ksp->ks_data; 2533 KS_U64INIT(rs_corr); 2534 KS_U64INIT(rs_uncorr); 2535 KS_U64INIT(rs_sym0_corr); 2536 KS_U64INIT(rs_sym1_corr); 2537 KS_U64INIT(rs_sym2_corr); 2538 KS_U64INIT(rs_sym3_corr); 2539 KS_U64INIT(fc_lane0_corr); 2540 KS_U64INIT(fc_lane0_uncorr); 2541 KS_U64INIT(fc_lane1_corr); 2542 KS_U64INIT(fc_lane1_uncorr); 2543 KS_U64INIT(fc_lane2_corr); 2544 KS_U64INIT(fc_lane2_uncorr); 2545 KS_U64INIT(fc_lane3_corr); 2546 KS_U64INIT(fc_lane3_uncorr); 2547 2548 ksp->ks_update = update_port_fec_kstats; 2549 ksp->ks_private = pi; 2550 kstat_install(ksp); 2551 2552 return (ksp); 2553 } 2554 2555 int 2556 adapter_full_init(struct adapter *sc) 2557 { 2558 int i, rc = 0; 2559 2560 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 2561 2562 rc = t4_setup_adapter_queues(sc); 2563 if (rc != 0) 2564 goto done; 2565 2566 if (sc->intr_cap & DDI_INTR_FLAG_BLOCK) 2567 (void) ddi_intr_block_enable(sc->intr_handle, sc->intr_count); 2568 else { 2569 for (i = 0; i < sc->intr_count; i++) 2570 (void) ddi_intr_enable(sc->intr_handle[i]); 2571 } 2572 t4_intr_enable(sc); 2573 sc->flags |= FULL_INIT_DONE; 2574 2575 done: 2576 if (rc != 0) 2577 (void) adapter_full_uninit(sc); 2578 2579 return (rc); 2580 } 2581 2582 int 2583 adapter_full_uninit(struct adapter *sc) 2584 { 2585 int i, rc = 0; 2586 2587 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 2588 2589 if (sc->intr_cap & DDI_INTR_FLAG_BLOCK) 2590 (void) ddi_intr_block_disable(sc->intr_handle, sc->intr_count); 2591 else { 2592 for (i = 0; i < sc->intr_count; i++) 2593 (void) ddi_intr_disable(sc->intr_handle[i]); 2594 } 2595 2596 rc = t4_teardown_adapter_queues(sc); 2597 if (rc != 0) 2598 return (rc); 2599 2600 sc->flags &= ~FULL_INIT_DONE; 2601 2602 return (0); 2603 } 2604 2605 int 2606 port_full_init(struct port_info *pi) 2607 { 2608 struct adapter *sc = pi->adapter; 2609 uint16_t *rss; 2610 struct sge_rxq *rxq; 2611 int rc, i; 2612 2613 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 2614 ASSERT((pi->flags & PORT_INIT_DONE) == 0); 2615 2616 /* 2617 * Allocate tx/rx/fl queues for this port. 2618 */ 2619 rc = t4_setup_port_queues(pi); 2620 if (rc != 0) 2621 goto done; /* error message displayed already */ 2622 2623 /* 2624 * Setup RSS for this port. 2625 */ 2626 rss = kmem_zalloc(pi->nrxq * sizeof (*rss), KM_SLEEP); 2627 for_each_rxq(pi, i, rxq) { 2628 rss[i] = rxq->iq.abs_id; 2629 } 2630 rc = -t4_config_rss_range(sc, sc->mbox, pi->viid, 0, 2631 pi->rss_size, rss, pi->nrxq); 2632 kmem_free(rss, pi->nrxq * sizeof (*rss)); 2633 if (rc != 0) { 2634 cxgb_printf(pi->dip, CE_WARN, "rss_config failed: %d", rc); 2635 goto done; 2636 } 2637 2638 /* 2639 * Initialize our per-port FEC kstats. 2640 */ 2641 pi->ksp_fec = setup_port_fec_kstats(pi); 2642 2643 pi->flags |= PORT_INIT_DONE; 2644 done: 2645 if (rc != 0) 2646 (void) port_full_uninit(pi); 2647 2648 return (rc); 2649 } 2650 2651 /* 2652 * Idempotent. 2653 */ 2654 int 2655 port_full_uninit(struct port_info *pi) 2656 { 2657 2658 ASSERT(pi->flags & PORT_INIT_DONE); 2659 2660 if (pi->ksp_fec != NULL) { 2661 kstat_delete(pi->ksp_fec); 2662 pi->ksp_fec = NULL; 2663 } 2664 (void) t4_teardown_port_queues(pi); 2665 pi->flags &= ~PORT_INIT_DONE; 2666 2667 return (0); 2668 } 2669 2670 void 2671 enable_port_queues(struct port_info *pi) 2672 { 2673 struct adapter *sc = pi->adapter; 2674 int i; 2675 struct sge_iq *iq; 2676 struct sge_rxq *rxq; 2677 2678 ASSERT(pi->flags & PORT_INIT_DONE); 2679 2680 /* 2681 * TODO: whatever was queued up after we set iq->state to IQS_DISABLED 2682 * back in disable_port_queues will be processed now, after an unbounded 2683 * delay. This can't be good. 2684 */ 2685 2686 for_each_rxq(pi, i, rxq) { 2687 iq = &rxq->iq; 2688 if (atomic_cas_uint(&iq->state, IQS_DISABLED, IQS_IDLE) != 2689 IQS_DISABLED) 2690 panic("%s: iq %p wasn't disabled", __func__, 2691 (void *) iq); 2692 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), 2693 V_SEINTARM(iq->intr_params) | V_INGRESSQID(iq->cntxt_id)); 2694 } 2695 } 2696 2697 void 2698 disable_port_queues(struct port_info *pi) 2699 { 2700 int i; 2701 struct adapter *sc = pi->adapter; 2702 struct sge_rxq *rxq; 2703 2704 ASSERT(pi->flags & PORT_INIT_DONE); 2705 2706 /* 2707 * TODO: need proper implementation for all tx queues (ctrl, eth, ofld). 2708 */ 2709 2710 for_each_rxq(pi, i, rxq) { 2711 while (atomic_cas_uint(&rxq->iq.state, IQS_IDLE, 2712 IQS_DISABLED) != IQS_IDLE) 2713 msleep(1); 2714 } 2715 2716 mutex_enter(&sc->sfl_lock); 2717 for_each_rxq(pi, i, rxq) 2718 rxq->fl.flags |= FL_DOOMED; 2719 mutex_exit(&sc->sfl_lock); 2720 /* TODO: need to wait for all fl's to be removed from sc->sfl */ 2721 } 2722 2723 void 2724 t4_fatal_err(struct adapter *sc) 2725 { 2726 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 2727 t4_intr_disable(sc); 2728 cxgb_printf(sc->dip, CE_WARN, 2729 "encountered fatal error, adapter stopped."); 2730 } 2731 2732 int 2733 t4_os_find_pci_capability(struct adapter *sc, int cap) 2734 { 2735 uint16_t stat; 2736 uint8_t cap_ptr, cap_id; 2737 2738 t4_os_pci_read_cfg2(sc, PCI_CONF_STAT, &stat); 2739 if ((stat & PCI_STAT_CAP) == 0) 2740 return (0); /* does not implement capabilities */ 2741 2742 t4_os_pci_read_cfg1(sc, PCI_CONF_CAP_PTR, &cap_ptr); 2743 while (cap_ptr) { 2744 t4_os_pci_read_cfg1(sc, cap_ptr + PCI_CAP_ID, &cap_id); 2745 if (cap_id == cap) 2746 return (cap_ptr); /* found */ 2747 t4_os_pci_read_cfg1(sc, cap_ptr + PCI_CAP_NEXT_PTR, &cap_ptr); 2748 } 2749 2750 return (0); /* not found */ 2751 } 2752 2753 void 2754 t4_os_portmod_changed(struct adapter *sc, int idx) 2755 { 2756 static const char *mod_str[] = { 2757 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 2758 }; 2759 struct port_info *pi = sc->port[idx]; 2760 2761 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 2762 cxgb_printf(pi->dip, CE_NOTE, "transceiver unplugged."); 2763 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 2764 cxgb_printf(pi->dip, CE_NOTE, 2765 "unknown transceiver inserted.\n"); 2766 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 2767 cxgb_printf(pi->dip, CE_NOTE, 2768 "unsupported transceiver inserted.\n"); 2769 else if (pi->mod_type > 0 && pi->mod_type < ARRAY_SIZE(mod_str)) 2770 cxgb_printf(pi->dip, CE_NOTE, "%s transceiver inserted.\n", 2771 mod_str[pi->mod_type]); 2772 else 2773 cxgb_printf(pi->dip, CE_NOTE, "transceiver (type %d) inserted.", 2774 pi->mod_type); 2775 2776 if ((isset(&sc->open_device_map, pi->port_id) != 0) && 2777 pi->link_cfg.new_module) 2778 pi->link_cfg.redo_l1cfg = true; 2779 } 2780 2781 /* ARGSUSED */ 2782 static int 2783 cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, mblk_t *m) 2784 { 2785 if (m != NULL) 2786 freemsg(m); 2787 return (0); 2788 } 2789 2790 int 2791 t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h) 2792 { 2793 uint_t *loc, new; 2794 2795 if (opcode >= ARRAY_SIZE(sc->cpl_handler)) 2796 return (EINVAL); 2797 2798 new = (uint_t)(unsigned long) (h ? h : cpl_not_handled); 2799 loc = (uint_t *)&sc->cpl_handler[opcode]; 2800 (void) atomic_swap_uint(loc, new); 2801 2802 return (0); 2803 } 2804 2805 static int 2806 fw_msg_not_handled(struct adapter *sc, const __be64 *data) 2807 { 2808 struct cpl_fw6_msg *cpl; 2809 2810 cpl = __containerof((void *)data, struct cpl_fw6_msg, data); 2811 2812 cxgb_printf(sc->dip, CE_WARN, "%s fw_msg type %d", __func__, cpl->type); 2813 return (0); 2814 } 2815 2816 int 2817 t4_register_fw_msg_handler(struct adapter *sc, int type, fw_msg_handler_t h) 2818 { 2819 fw_msg_handler_t *loc, new; 2820 2821 if (type >= ARRAY_SIZE(sc->fw_msg_handler)) 2822 return (EINVAL); 2823 2824 /* 2825 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 2826 * handler dispatch table. Reject any attempt to install a handler for 2827 * this subtype. 2828 */ 2829 if (type == FW_TYPE_RSSCPL || type == FW6_TYPE_RSSCPL) 2830 return (EINVAL); 2831 2832 new = h ? h : fw_msg_not_handled; 2833 loc = &sc->fw_msg_handler[type]; 2834 (void)atomic_swap_ptr(loc, (void *)new); 2835 2836 return (0); 2837 } 2838 2839 static int 2840 t4_sensor_read(struct adapter *sc, uint32_t diag, uint32_t *valp) 2841 { 2842 int rc; 2843 struct port_info *pi = sc->port[0]; 2844 uint32_t param, val; 2845 2846 rc = begin_synchronized_op(pi, 1, 1); 2847 if (rc != 0) { 2848 return (rc); 2849 } 2850 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2851 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 2852 V_FW_PARAMS_PARAM_Y(diag); 2853 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2854 end_synchronized_op(pi, 1); 2855 2856 if (rc != 0) { 2857 return (rc); 2858 } 2859 2860 if (val == 0) { 2861 return (EIO); 2862 } 2863 2864 *valp = val; 2865 return (0); 2866 } 2867 2868 static int 2869 t4_temperature_read(void *arg, sensor_ioctl_scalar_t *scalar) 2870 { 2871 int ret; 2872 struct adapter *sc = arg; 2873 uint32_t val; 2874 2875 ret = t4_sensor_read(sc, FW_PARAM_DEV_DIAG_TMP, &val); 2876 if (ret != 0) { 2877 return (ret); 2878 } 2879 2880 /* 2881 * The device measures temperature in units of 1 degree Celsius. We 2882 * don't know its precision. 2883 */ 2884 scalar->sis_unit = SENSOR_UNIT_CELSIUS; 2885 scalar->sis_gran = 1; 2886 scalar->sis_prec = 0; 2887 scalar->sis_value = val; 2888 2889 return (0); 2890 } 2891 2892 static int 2893 t4_voltage_read(void *arg, sensor_ioctl_scalar_t *scalar) 2894 { 2895 int ret; 2896 struct adapter *sc = arg; 2897 uint32_t val; 2898 2899 ret = t4_sensor_read(sc, FW_PARAM_DEV_DIAG_VDD, &val); 2900 if (ret != 0) { 2901 return (ret); 2902 } 2903 2904 scalar->sis_unit = SENSOR_UNIT_VOLTS; 2905 scalar->sis_gran = 1000; 2906 scalar->sis_prec = 0; 2907 scalar->sis_value = val; 2908 2909 return (0); 2910 } 2911 2912 /* 2913 * While the hardware supports the ability to read and write the flash image, 2914 * this is not currently wired up. 2915 */ 2916 static int 2917 t4_ufm_getcaps(ddi_ufm_handle_t *ufmh, void *arg, ddi_ufm_cap_t *caps) 2918 { 2919 *caps = DDI_UFM_CAP_REPORT; 2920 return (0); 2921 } 2922 2923 static int 2924 t4_ufm_fill_image(ddi_ufm_handle_t *ufmh, void *arg, uint_t imgno, 2925 ddi_ufm_image_t *imgp) 2926 { 2927 if (imgno != 0) { 2928 return (EINVAL); 2929 } 2930 2931 ddi_ufm_image_set_desc(imgp, "Firmware"); 2932 ddi_ufm_image_set_nslots(imgp, 1); 2933 2934 return (0); 2935 } 2936 2937 static int 2938 t4_ufm_fill_slot_version(nvlist_t *nvl, const char *key, uint32_t vers) 2939 { 2940 char buf[128]; 2941 2942 if (vers == 0) { 2943 return (0); 2944 } 2945 2946 if (snprintf(buf, sizeof (buf), "%u.%u.%u.%u", 2947 G_FW_HDR_FW_VER_MAJOR(vers), G_FW_HDR_FW_VER_MINOR(vers), 2948 G_FW_HDR_FW_VER_MICRO(vers), G_FW_HDR_FW_VER_BUILD(vers)) >= 2949 sizeof (buf)) { 2950 return (EOVERFLOW); 2951 } 2952 2953 return (nvlist_add_string(nvl, key, buf)); 2954 } 2955 2956 static int 2957 t4_ufm_fill_slot(ddi_ufm_handle_t *ufmh, void *arg, uint_t imgno, uint_t slotno, 2958 ddi_ufm_slot_t *slotp) 2959 { 2960 int ret; 2961 struct adapter *sc = arg; 2962 nvlist_t *misc = NULL; 2963 char buf[128]; 2964 2965 if (imgno != 0 || slotno != 0) { 2966 return (EINVAL); 2967 } 2968 2969 if (snprintf(buf, sizeof (buf), "%u.%u.%u.%u", 2970 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 2971 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 2972 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 2973 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)) >= sizeof (buf)) { 2974 return (EOVERFLOW); 2975 } 2976 2977 ddi_ufm_slot_set_version(slotp, buf); 2978 2979 (void) nvlist_alloc(&misc, NV_UNIQUE_NAME, KM_SLEEP); 2980 if ((ret = t4_ufm_fill_slot_version(misc, "TP Microcode", 2981 sc->params.tp_vers)) != 0) { 2982 goto err; 2983 } 2984 2985 if ((ret = t4_ufm_fill_slot_version(misc, "Bootstrap", 2986 sc->params.bs_vers)) != 0) { 2987 goto err; 2988 } 2989 2990 if ((ret = t4_ufm_fill_slot_version(misc, "Expansion ROM", 2991 sc->params.er_vers)) != 0) { 2992 goto err; 2993 } 2994 2995 if ((ret = nvlist_add_uint32(misc, "Serial Configuration", 2996 sc->params.scfg_vers)) != 0) { 2997 goto err; 2998 } 2999 3000 if ((ret = nvlist_add_uint32(misc, "VPD Version", 3001 sc->params.vpd_vers)) != 0) { 3002 goto err; 3003 } 3004 3005 ddi_ufm_slot_set_misc(slotp, misc); 3006 ddi_ufm_slot_set_attrs(slotp, DDI_UFM_ATTR_ACTIVE | 3007 DDI_UFM_ATTR_WRITEABLE | DDI_UFM_ATTR_READABLE); 3008 return (0); 3009 3010 err: 3011 nvlist_free(misc); 3012 return (ret); 3013 3014 } 3015