1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4 support code. 14 * 15 * Copyright (C) 2011-2013 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23 /* 24 * Copyright 2024 Oxide Computer Company 25 */ 26 27 #ifndef __CXGBE_ADAPTER_H 28 #define __CXGBE_ADAPTER_H 29 30 #include <sys/ddi.h> 31 #include <sys/mac_provider.h> 32 #include <sys/ethernet.h> 33 #include <sys/queue.h> 34 #include <sys/containerof.h> 35 #include <sys/ddi_ufm.h> 36 37 #include "firmware/t4fw_interface.h" 38 #include "shared.h" 39 40 struct adapter; 41 typedef struct adapter adapter_t; 42 43 #define FW_IQ_QSIZE 256 44 #define FW_IQ_ESIZE 64 /* At least 64 mandated by the firmware spec */ 45 46 #define RX_IQ_QSIZE 1024 47 #define RX_IQ_ESIZE 64 /* At least 64 so CPL_RX_PKT will fit */ 48 49 #define EQ_ESIZE 64 /* All egress queues use this entry size */ 50 51 #define RX_FL_ESIZE 64 /* 8 64bit addresses */ 52 53 #define FL_BUF_SIZES 4 54 55 #define CTRL_EQ_QSIZE 128 56 57 #define TX_EQ_QSIZE 1024 58 #define TX_SGL_SEGS 36 59 #define TX_WR_FLITS (SGE_MAX_WR_LEN / 8) 60 61 #define UDBS_SEG_SHIFT 7 /* log2(UDBS_SEG_SIZE) */ 62 #define UDBS_DB_OFFSET 8 /* offset of the 4B doorbell in a segment */ 63 #define UDBS_WR_OFFSET 64 /* offset of the work request in a segment */ 64 65 typedef enum t4_port_flags { 66 TPF_INIT_DONE = (1 << 0), 67 } t4_port_flags_t; 68 69 typedef enum t4_port_feat { 70 CXGBE_HW_LSO = (1 << 0), 71 CXGBE_HW_CSUM = (1 << 1), 72 } t4_port_feat_t; 73 74 struct port_info { 75 dev_info_t *dip; 76 mac_handle_t mh; 77 mac_callbacks_t *mc; 78 void *props; 79 int mtu; 80 uint8_t hw_addr[ETHERADDRL]; 81 82 kmutex_t lock; 83 struct adapter *adapter; 84 85 t4_port_flags_t flags; 86 87 uint16_t viid; 88 int16_t xact_addr_filt; /* index of exact MAC address filter */ 89 uint16_t rss_size; /* size of VI's RSS table slice */ 90 uint16_t ntxq; /* # of tx queues */ 91 uint16_t first_txq; /* index of first tx queue */ 92 uint16_t nrxq; /* # of rx queues */ 93 uint16_t first_rxq; /* index of first rx queue */ 94 uint8_t lport; /* associated offload logical port */ 95 int8_t mdio_addr; 96 uint8_t port_type; 97 uint8_t mod_type; 98 uint8_t port_id; 99 uint8_t tx_chan; 100 uint8_t rx_chan; 101 uint8_t rx_cchan; 102 uint8_t instance; /* Associated adapter instance */ 103 uint8_t child_inst; /* Associated child instance */ 104 uint8_t tmr_idx; 105 int8_t pktc_idx; 106 struct link_config link_cfg; 107 struct port_stats stats; 108 t4_port_feat_t features; 109 uint8_t macaddr_cnt; 110 u8 rss_mode; 111 u16 viid_mirror; 112 kstat_t *ksp_config; 113 kstat_t *ksp_info; 114 kstat_t *ksp_fec; 115 116 u8 vivld; 117 u8 vin; 118 u8 smt_idx; 119 120 u8 vivld_mirror; 121 u8 vin_mirror; 122 u8 smt_idx_mirror; 123 }; 124 125 struct fl_sdesc { 126 struct rxbuf *rxb; 127 }; 128 129 struct tx_desc { 130 __be64 flit[8]; 131 }; 132 133 /* DMA maps used for tx */ 134 struct tx_maps { 135 ddi_dma_handle_t *map; 136 uint32_t map_total; /* # of DMA maps */ 137 uint32_t map_pidx; /* next map to be used */ 138 uint32_t map_cidx; /* reclaimed up to this index */ 139 uint32_t map_avail; /* # of available maps */ 140 }; 141 142 struct tx_sdesc { 143 mblk_t *m; 144 uint32_t txb_used; /* # of bytes of tx copy buffer used */ 145 uint16_t hdls_used; /* # of dma handles used */ 146 uint16_t desc_used; /* # of hardware descriptors used */ 147 }; 148 149 typedef enum t4_iq_flags { 150 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 151 IQ_INTR = (1 << 1), /* iq takes direct interrupt */ 152 IQ_HAS_FL = (1 << 2), /* iq has fl */ 153 } t4_iq_flags_t; 154 155 typedef enum t4_iq_state { 156 IQS_DISABLED = 0, 157 IQS_BUSY = 1, 158 IQS_IDLE = 2, 159 } t4_iq_state_t; 160 161 struct rxbuf_cache_params { 162 dev_info_t *dip; 163 ddi_dma_attr_t dma_attr_rx; 164 ddi_device_acc_attr_t acc_attr_rx; 165 size_t buf_size; 166 }; 167 168 /* 169 * Ingress Queue: T4 is producer, driver is consumer. 170 */ 171 struct sge_iq { 172 t4_iq_state_t state; 173 t4_iq_flags_t flags; 174 175 ddi_dma_handle_t dhdl; 176 ddi_acc_handle_t ahdl; 177 178 __be64 *desc; /* KVA of descriptor ring */ 179 uint64_t ba; /* bus address of descriptor ring */ 180 const __be64 *cdesc; /* current descriptor */ 181 struct adapter *adapter; /* associated adapter */ 182 uint8_t gen; /* generation bit */ 183 uint8_t intr_params; /* interrupt holdoff parameters */ 184 int8_t intr_pktc_idx; /* packet count threshold index */ 185 uint8_t intr_next; /* holdoff for next interrupt */ 186 uint8_t esize; /* size (bytes) of each entry in the queue */ 187 uint16_t qsize; /* size (# of entries) of the queue */ 188 uint16_t cidx; /* consumer index */ 189 uint16_t pending; /* # of descs processed since last doorbell */ 190 uint16_t cntxt_id; /* SGE context id for the iq */ 191 uint16_t abs_id; /* absolute SGE id for the iq */ 192 kmutex_t lock; /* Rx access lock */ 193 uint8_t polling; 194 195 STAILQ_ENTRY(sge_iq) link; 196 }; 197 198 typedef enum t4_eq_flags { 199 EQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 200 EQ_MTX = (1 << 1), /* mutex has been initialized */ 201 } t4_eq_flags_t; 202 203 /* Listed in order of preference. */ 204 typedef enum t4_doorbells { 205 DOORBELL_UDB = (1 << 0), 206 DOORBELL_WCWR = (1 << 1), 207 DOORBELL_UDBWC = (1 << 2), 208 DOORBELL_KDB = (1 << 3), 209 } t4_doorbells_t; 210 211 /* 212 * Egress Queue: driver is producer, T4 is consumer. 213 * 214 * Note: A free list is an egress queue (driver produces the buffers and T4 215 * consumes them) but it's special enough to have its own struct (see sge_fl). 216 */ 217 struct sge_eq { 218 ddi_dma_handle_t desc_dhdl; 219 ddi_acc_handle_t desc_ahdl; 220 t4_eq_flags_t flags; 221 kmutex_t lock; 222 223 struct tx_desc *desc; /* KVA of descriptor ring */ 224 uint64_t ba; /* bus address of descriptor ring */ 225 struct sge_qstat *spg; /* status page, for convenience */ 226 t4_doorbells_t doorbells; 227 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 228 uint_t udb_qid; /* relative qid within the doorbell page */ 229 uint16_t cap; /* max # of desc, for convenience */ 230 uint16_t avail; /* available descriptors, for convenience */ 231 uint16_t qsize; /* size (# of entries) of the queue */ 232 uint16_t cidx; /* consumer idx (desc idx) */ 233 uint16_t pidx; /* producer idx (desc idx) */ 234 uint16_t pending; /* # of descriptors used since last doorbell */ 235 uint16_t iqid; /* iq that gets egr_update for the eq */ 236 uint8_t tx_chan; /* tx channel used by the eq */ 237 uint32_t cntxt_id; /* SGE context id for the eq */ 238 }; 239 240 typedef enum t4_fl_flags { 241 FL_MTX = (1 << 0), /* mutex has been initialized */ 242 FL_STARVING = (1 << 1), /* on the list of starving fl's */ 243 FL_DOOMED = (1 << 2), /* about to be destroyed */ 244 } t4_fl_flags_t; 245 246 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 247 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 248 249 struct sge_fl { 250 t4_fl_flags_t flags; 251 kmutex_t lock; 252 ddi_dma_handle_t dhdl; 253 ddi_acc_handle_t ahdl; 254 255 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 256 uint64_t ba; /* bus address of descriptor ring */ 257 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 258 uint32_t cap; /* max # of buffers, for convenience */ 259 uint16_t qsize; /* size (# of entries) of the queue */ 260 uint16_t cntxt_id; /* SGE context id for the freelist */ 261 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 262 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 263 uint32_t needed; /* # of buffers needed to fill up fl. */ 264 uint32_t lowat; /* # of buffers <= this means fl needs help */ 265 uint32_t pending; /* # of bufs allocated since last doorbell */ 266 uint32_t offset; /* current packet within the larger buffer */ 267 uint16_t copy_threshold; /* anything this size or less is copied up */ 268 269 uint64_t copied_up; /* # of frames copied into mblk and handed up */ 270 uint64_t passed_up; /* # of frames wrapped in mblk and handed up */ 271 uint64_t allocb_fail; /* # of mblk allocation failures */ 272 273 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 274 }; 275 276 /* txq: SGE egress queue + miscellaneous items */ 277 struct sge_txq { 278 struct sge_eq eq; /* MUST be first */ 279 280 struct port_info *port; /* the port this txq belongs to */ 281 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 282 mac_ring_handle_t ring_handle; 283 284 /* DMA handles used for tx */ 285 ddi_dma_handle_t *tx_dhdl; 286 uint32_t tx_dhdl_total; /* Total # of handles */ 287 uint32_t tx_dhdl_pidx; /* next handle to be used */ 288 uint32_t tx_dhdl_cidx; /* reclaimed up to this index */ 289 uint32_t tx_dhdl_avail; /* # of available handles */ 290 291 /* Copy buffers for tx */ 292 ddi_dma_handle_t txb_dhdl; 293 ddi_acc_handle_t txb_ahdl; 294 caddr_t txb_va; /* KVA of copy buffers area */ 295 uint64_t txb_ba; /* bus address of copy buffers area */ 296 uint32_t txb_size; /* total size */ 297 uint32_t txb_next; /* offset of next useable area in the buffer */ 298 uint32_t txb_avail; /* # of bytes available */ 299 uint16_t copy_threshold; /* anything this size or less is copied up */ 300 301 uint64_t txpkts; /* # of ethernet packets */ 302 uint64_t txbytes; /* # of ethernet bytes */ 303 kstat_t *ksp; 304 305 /* stats for common events first */ 306 307 uint64_t txcsum; /* # of times hardware assisted with checksum */ 308 uint64_t tso_wrs; /* # of IPv4 TSO work requests */ 309 uint64_t imm_wrs; /* # of work requests with immediate data */ 310 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 311 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 312 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 313 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 314 uint64_t txb_used; /* # of tx copy buffers used (64 byte each) */ 315 uint64_t hdl_used; /* # of DMA handles used */ 316 317 /* stats for not-that-common events */ 318 319 uint32_t txb_full; /* txb ran out of space */ 320 uint32_t dma_hdl_failed; /* couldn't obtain DMA handle */ 321 uint32_t dma_map_failed; /* couldn't obtain DMA mapping */ 322 uint32_t qfull; /* out of hardware descriptors */ 323 uint32_t qflush; /* # of SGE_EGR_UPDATE notifications for txq */ 324 uint32_t pullup_early; /* # of pullups before starting frame's SGL */ 325 uint32_t pullup_late; /* # of pullups while building frame's SGL */ 326 uint32_t pullup_failed; /* # of failed pullups */ 327 uint32_t csum_failed; /* # of csum reqs we failed to fulfill */ 328 }; 329 330 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 331 struct sge_rxq { 332 struct sge_iq iq; /* MUST be first */ 333 struct sge_fl fl; 334 335 struct port_info *port; /* the port this rxq belongs to */ 336 kstat_t *ksp; 337 338 mac_ring_handle_t ring_handle; 339 uint64_t ring_gen_num; 340 341 /* stats for common events first */ 342 343 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 344 uint64_t rxpkts; /* # of ethernet packets */ 345 uint64_t rxbytes; /* # of ethernet bytes */ 346 347 /* stats for not-that-common events */ 348 349 uint32_t nomem; /* mblk allocation during rx failed */ 350 }; 351 352 struct sge { 353 int fl_starve_threshold; 354 int s_qpp; 355 356 int nrxq; /* total rx queues (all ports and the rest) */ 357 int ntxq; /* total tx queues (all ports and the rest) */ 358 int niq; /* total ingress queues */ 359 int neq; /* total egress queues */ 360 int stat_len; /* length of status page at ring end */ 361 int pktshift; /* padding between CPL & packet data */ 362 int fl_align; /* response queue message alignment */ 363 364 struct sge_iq fwq; /* Firmware event queue */ 365 struct sge_txq *txq; /* NIC tx queues */ 366 struct sge_rxq *rxq; /* NIC rx queues */ 367 368 int iq_start; /* iq context id map start index */ 369 int eq_start; /* eq context id map start index */ 370 int iqmap_sz; /* size of iq context id map */ 371 int eqmap_sz; /* size of eq context id map */ 372 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 373 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 374 375 /* Device access and DMA attributes for all the descriptor rings */ 376 ddi_device_acc_attr_t acc_attr_desc; 377 ddi_dma_attr_t dma_attr_desc; 378 379 /* Device access and DMA attributes for tx buffers */ 380 ddi_device_acc_attr_t acc_attr_tx; 381 ddi_dma_attr_t dma_attr_tx; 382 383 /* Device access and DMA attributes for rx buffers are in rxb_params */ 384 kmem_cache_t *rxbuf_cache; 385 struct rxbuf_cache_params rxb_params; 386 }; 387 388 struct driver_properties { 389 /* There is a driver.conf variable for each of these */ 390 int max_ntxq_10g; 391 int max_nrxq_10g; 392 int max_ntxq_1g; 393 int max_nrxq_1g; 394 int intr_types; 395 int tmr_idx_10g; 396 int pktc_idx_10g; 397 int tmr_idx_1g; 398 int pktc_idx_1g; 399 int qsize_txq; 400 int qsize_rxq; 401 402 int timer_val[SGE_NTIMERS]; 403 int counter_val[SGE_NCOUNTERS]; 404 405 int wc; 406 407 int multi_rings; 408 int t4_fw_install; 409 }; 410 411 struct t4_mbox_list { 412 STAILQ_ENTRY(t4_mbox_list) link; 413 }; 414 415 typedef enum t4_adapter_flags { 416 TAF_INIT_DONE = (1 << 0), 417 TAF_FW_OK = (1 << 1), 418 TAF_INTR_FWD = (1 << 2), 419 TAF_INTR_ALLOC = (1 << 3), 420 TAF_MASTER_PF = (1 << 4), 421 422 TAF_BUSY = (1 << 9), 423 } t4_adapter_flags_t; 424 425 struct adapter { 426 SLIST_ENTRY(adapter) link; 427 dev_info_t *dip; 428 dev_t dev; 429 430 unsigned int pf; 431 unsigned int mbox; 432 433 unsigned int vpd_busy; 434 unsigned int vpd_flag; 435 436 u32 t4_bar0; 437 438 uint_t open; /* character device is open */ 439 440 /* PCI config space access handle */ 441 ddi_acc_handle_t pci_regh; 442 443 /* MMIO register access handle */ 444 ddi_acc_handle_t regh; 445 caddr_t regp; 446 /* BAR1 register access handle */ 447 ddi_acc_handle_t reg1h; 448 caddr_t reg1p; 449 450 /* Interrupt information */ 451 int intr_type; 452 int intr_count; 453 int intr_cap; 454 uint_t intr_pri; 455 ddi_intr_handle_t *intr_handle; 456 457 struct driver_properties props; 458 kstat_t *ksp; 459 kstat_t *ksp_stat; 460 461 struct sge sge; 462 463 struct port_info *port[MAX_NPORTS]; 464 ddi_taskq_t *tq[NCHAN]; 465 uint8_t chan_map[NCHAN]; 466 uint32_t filter_mode; 467 468 t4_adapter_flags_t flags; 469 t4_doorbells_t doorbells; 470 int registered_device_map; 471 int open_device_map; 472 473 unsigned int cfcsum; 474 struct adapter_params params; 475 476 uint16_t linkcaps; 477 uint16_t niccaps; 478 uint16_t toecaps; 479 uint16_t rdmacaps; 480 uint16_t iscsicaps; 481 uint16_t fcoecaps; 482 483 kmutex_t lock; 484 kcondvar_t cv; 485 486 /* Starving free lists */ 487 kmutex_t sfl_lock; /* same cache-line as sc_lock? but that's ok */ 488 TAILQ_HEAD(, sge_fl) sfl; 489 timeout_id_t sfl_timer; 490 491 /* Sensors */ 492 id_t temp_sensor; 493 id_t volt_sensor; 494 495 ddi_ufm_handle_t *ufm_hdl; 496 497 /* support for single-threading access to adapter mailbox registers */ 498 kmutex_t mbox_lock; 499 STAILQ_HEAD(, t4_mbox_list) mbox_list; 500 }; 501 502 struct memwin { 503 uint32_t base; 504 uint32_t aperture; 505 }; 506 507 #define ADAPTER_LOCK(sc) mutex_enter(&(sc)->lock) 508 #define ADAPTER_UNLOCK(sc) mutex_exit(&(sc)->lock) 509 #define ADAPTER_LOCK_ASSERT_OWNED(sc) ASSERT(mutex_owned(&(sc)->lock)) 510 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) ASSERT(!mutex_owned(&(sc)->lock)) 511 512 #define PORT_LOCK(pi) mutex_enter(&(pi)->lock) 513 #define PORT_UNLOCK(pi) mutex_exit(&(pi)->lock) 514 #define PORT_LOCK_ASSERT_OWNED(pi) ASSERT(mutex_owned(&(pi)->lock)) 515 #define PORT_LOCK_ASSERT_NOTOWNED(pi) ASSERT(!mutex_owned(&(pi)->lock)) 516 517 #define IQ_LOCK(iq) mutex_enter(&(iq)->lock) 518 #define IQ_UNLOCK(iq) mutex_exit(&(iq)->lock) 519 #define IQ_LOCK_ASSERT_OWNED(iq) ASSERT(mutex_owned(&(iq)->lock)) 520 #define IQ_LOCK_ASSERT_NOTOWNED(iq) ASSERT(!mutex_owned(&(iq)->lock)) 521 522 #define FL_LOCK(fl) mutex_enter(&(fl)->lock) 523 #define FL_UNLOCK(fl) mutex_exit(&(fl)->lock) 524 #define FL_LOCK_ASSERT_OWNED(fl) ASSERT(mutex_owned(&(fl)->lock)) 525 #define FL_LOCK_ASSERT_NOTOWNED(fl) ASSERT(!mutex_owned(&(fl)->lock)) 526 527 #define RXQ_LOCK(rxq) IQ_LOCK(&(rxq)->iq) 528 #define RXQ_UNLOCK(rxq) IQ_UNLOCK(&(rxq)->iq) 529 #define RXQ_LOCK_ASSERT_OWNED(rxq) IQ_LOCK_ASSERT_OWNED(&(rxq)->iq) 530 #define RXQ_LOCK_ASSERT_NOTOWNED(rxq) IQ_LOCK_ASSERT_NOTOWNED(&(rxq)->iq) 531 532 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 533 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 534 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 535 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 536 537 #define EQ_LOCK(eq) mutex_enter(&(eq)->lock) 538 #define EQ_UNLOCK(eq) mutex_exit(&(eq)->lock) 539 #define EQ_LOCK_ASSERT_OWNED(eq) ASSERT(mutex_owned(&(eq)->lock)) 540 #define EQ_LOCK_ASSERT_NOTOWNED(eq) ASSERT(!mutex_owned(&(eq)->lock)) 541 542 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 543 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 544 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 545 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 546 547 #define for_each_txq(pi, iter, txq) \ 548 txq = &pi->adapter->sge.txq[pi->first_txq]; \ 549 for (iter = 0; iter < pi->ntxq; ++iter, ++txq) 550 #define for_each_rxq(pi, iter, rxq) \ 551 rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \ 552 for (iter = 0; iter < pi->nrxq; ++iter, ++rxq) 553 554 #define NFIQ(sc) ((sc)->intr_count > 1 ? (sc)->intr_count - 1 : 1) 555 556 /* One for errors, one for firmware events */ 557 #define T4_EXTRA_INTR 2 558 559 static inline void t4_mbox_list_add(struct adapter *adap, 560 struct t4_mbox_list *entry) 561 { 562 mutex_enter(&adap->mbox_lock); 563 STAILQ_INSERT_TAIL(&adap->mbox_list, entry, link); 564 mutex_exit(&adap->mbox_lock); 565 } 566 567 static inline void t4_mbox_list_del(struct adapter *adap, 568 struct t4_mbox_list *entry) 569 { 570 mutex_enter(&adap->mbox_lock); 571 STAILQ_REMOVE(&adap->mbox_list, entry, t4_mbox_list, link); 572 mutex_exit(&adap->mbox_lock); 573 } 574 575 static inline struct t4_mbox_list * 576 t4_mbox_list_first_entry(struct adapter *adap) 577 { 578 return (STAILQ_FIRST(&adap->mbox_list)); 579 } 580 581 static inline uint32_t 582 t4_read_reg(struct adapter *sc, uint32_t reg) 583 { 584 /* LINTED: E_BAD_PTR_CAST_ALIGN */ 585 return (ddi_get32(sc->regh, (uint32_t *)(sc->regp + reg))); 586 } 587 588 static inline void 589 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 590 { 591 /* LINTED: E_BAD_PTR_CAST_ALIGN */ 592 ddi_put32(sc->regh, (uint32_t *)(sc->regp + reg), val); 593 } 594 595 static inline void 596 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 597 { 598 *val = pci_config_get8(sc->pci_regh, reg); 599 } 600 601 static inline void 602 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 603 { 604 pci_config_put8(sc->pci_regh, reg, val); 605 } 606 607 static inline void 608 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 609 { 610 *val = pci_config_get16(sc->pci_regh, reg); 611 } 612 613 static inline void 614 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 615 { 616 pci_config_put16(sc->pci_regh, reg, val); 617 } 618 619 static inline void 620 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 621 { 622 *val = pci_config_get32(sc->pci_regh, reg); 623 } 624 625 static inline void 626 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 627 { 628 pci_config_put32(sc->pci_regh, reg, val); 629 } 630 631 static inline uint32_t 632 t4_read_reg32(struct adapter *sc, uint32_t reg) 633 { 634 return (ddi_get32(sc->regh, (uint32_t *)(sc->regp + reg))); 635 } 636 637 static inline uint64_t 638 t4_read_reg64(struct adapter *sc, uint32_t reg) 639 { 640 return (ddi_get64(sc->regh, (uint64_t *)(sc->regp + reg))); 641 } 642 643 static inline void 644 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 645 { 646 ddi_put64(sc->regh, (uint64_t *)(sc->regp + reg), val); 647 } 648 649 static inline struct port_info * 650 adap2pinfo(struct adapter *sc, int idx) 651 { 652 return (sc->port[idx]); 653 } 654 655 static inline void 656 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 657 { 658 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHERADDRL); 659 } 660 661 static inline bool 662 is_10G_port(const struct port_info *pi) 663 { 664 return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G) != 0); 665 } 666 667 static inline struct sge_rxq * 668 iq_to_rxq(struct sge_iq *iq) 669 { 670 return (__containerof(iq, struct sge_rxq, iq)); 671 } 672 673 static inline bool 674 is_25G_port(const struct port_info *pi) 675 { 676 return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G) != 0); 677 } 678 679 static inline bool 680 is_40G_port(const struct port_info *pi) 681 { 682 return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G) != 0); 683 } 684 685 static inline bool 686 is_50G_port(const struct port_info *pi) 687 { 688 return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G) != 0); 689 } 690 691 static inline bool 692 is_100G_port(const struct port_info *pi) 693 { 694 return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G) != 0); 695 } 696 697 static inline bool 698 is_10XG_port(const struct port_info *pi) 699 { 700 return (is_10G_port(pi) || is_40G_port(pi) || 701 is_25G_port(pi) || is_50G_port(pi) || 702 is_100G_port(pi)); 703 } 704 705 /* 706 * t4_os_pci_read_seeprom - read four bytes of SEEPROM/VPD contents 707 * @adapter: the adapter 708 * @addr: SEEPROM/VPD Address to read 709 * @valp: where to store the value read 710 * 711 * Read a 32-bit value from the given address in the SEEPROM/VPD. The address 712 * must be four-byte aligned. Returns 0 on success, a negative erro number 713 * on failure. 714 */ 715 static inline int t4_os_pci_read_seeprom(adapter_t *adapter, int addr, 716 u32 *valp) 717 { 718 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 719 int ret; 720 721 ret = t4_seeprom_read(adapter, addr, valp); 722 723 return (ret >= 0 ? 0 : ret); 724 } 725 726 /* 727 * t4_os_pci_write_seeprom - write four bytes of SEEPROM/VPD contents 728 * @adapter: the adapter 729 * @addr: SEEPROM/VPD Address to write 730 * @val: the value write 731 * 732 * Write a 32-bit value to the given address in the SEEPROM/VPD. The address 733 * must be four-byte aligned. Returns 0 on success, a negative erro number 734 * on failure. 735 */ 736 static inline int t4_os_pci_write_seeprom(adapter_t *adapter, int addr, u32 val) 737 { 738 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 739 int ret; 740 741 ret = t4_seeprom_write(adapter, addr, val); 742 743 return (ret >= 0 ? 0 : ret); 744 } 745 746 static inline int t4_os_pci_set_vpd_size(struct adapter *adapter, size_t len) 747 { 748 return (0); 749 } 750 751 static inline unsigned int t4_use_ldst(struct adapter *adap) 752 { 753 return (adap->flags & FW_OK); 754 } 755 756 static inline void t4_db_full(struct adapter *adap) {} 757 static inline void t4_db_dropped(struct adapter *adap) {} 758 759 /* t4_nexus.c */ 760 int t4_os_find_pci_capability(struct adapter *sc, int cap); 761 void t4_os_portmod_changed(struct adapter *sc, int idx); 762 int adapter_full_init(struct adapter *sc); 763 int adapter_full_uninit(struct adapter *sc); 764 int port_full_init(struct port_info *pi); 765 int port_full_uninit(struct port_info *pi); 766 void enable_port_queues(struct port_info *pi); 767 void disable_port_queues(struct port_info *pi); 768 void t4_iterate(void (*func)(int, void *), void *arg); 769 770 /* t4_debug.c */ 771 void t4_debug_init(void); 772 void t4_debug_fini(void); 773 774 /* t4_sge.c */ 775 void t4_sge_init(struct adapter *sc); 776 int t4_setup_adapter_queues(struct adapter *sc); 777 int t4_teardown_adapter_queues(struct adapter *sc); 778 int t4_setup_port_queues(struct port_info *pi); 779 int t4_teardown_port_queues(struct port_info *pi); 780 uint_t t4_intr_all(caddr_t arg1, caddr_t arg2); 781 uint_t t4_intr(caddr_t arg1, caddr_t arg2); 782 uint_t t4_intr_err(caddr_t arg1, caddr_t arg2); 783 int t4_mgmt_tx(struct adapter *sc, mblk_t *m); 784 void memwin_info(struct adapter *, int, uint32_t *, uint32_t *); 785 uint32_t position_memwin(struct adapter *, int, uint32_t); 786 787 mblk_t *t4_eth_tx(void *, mblk_t *); 788 mblk_t *t4_mc_tx(void *arg, mblk_t *m); 789 mblk_t *t4_ring_rx(struct sge_rxq *rxq, int poll_bytes); 790 int t4_alloc_tx_maps(struct adapter *sc, struct tx_maps *txmaps, int count, 791 int flags); 792 793 /* t4_mac.c */ 794 void t4_mc_init(struct port_info *pi); 795 void t4_mc_cb_init(struct port_info *); 796 void t4_os_link_changed(struct adapter *sc, int idx, int link_stat); 797 void t4_mac_rx(struct port_info *pi, struct sge_rxq *rxq, mblk_t *m); 798 void t4_mac_tx_update(struct port_info *pi, struct sge_txq *txq); 799 int t4_addmac(void *arg, const uint8_t *ucaddr); 800 801 /* t4_ioctl.c */ 802 int t4_ioctl(struct adapter *sc, int cmd, void *data, int mode); 803 804 int begin_synchronized_op(struct port_info *pi, int hold, int waitok); 805 void end_synchronized_op(struct port_info *pi, int held); 806 807 #define setbit(a, i) ((a)[(i)/NBBY] |= 1<<((i)%NBBY)) 808 #define clrbit(a, i) ((a)[(i)/NBBY] &= ~(1<<((i)%NBBY))) 809 #define isset(a, i) ((a)[(i)/NBBY] & (1<<((i)%NBBY))) 810 811 #endif /* __CXGBE_ADAPTER_H */ 812