1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4 support code. 14 * 15 * Copyright (C) 2011-2013 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23 /* 24 * Copyright 2025 Oxide Computer Company 25 */ 26 27 #ifndef __CXGBE_ADAPTER_H 28 #define __CXGBE_ADAPTER_H 29 30 #include <sys/ddi.h> 31 #include <sys/mac_provider.h> 32 #include <sys/ethernet.h> 33 #include <sys/queue.h> 34 #include <sys/containerof.h> 35 #include <sys/ddi_ufm.h> 36 37 #include "firmware/t4fw_interface.h" 38 #include "shared.h" 39 40 struct adapter; 41 typedef struct adapter adapter_t; 42 43 #define FW_IQ_QSIZE 256 44 #define FW_IQ_ESIZE 64 /* At least 64 mandated by the firmware spec */ 45 46 #define RX_IQ_QSIZE 1024 47 #define RX_IQ_ESIZE 64 /* At least 64 so CPL_RX_PKT will fit */ 48 49 #define EQ_ESIZE 64 /* All egress queues use this entry size */ 50 51 #define RX_FL_ESIZE 64 /* 8 64bit addresses */ 52 53 #define FL_BUF_SIZES 4 54 55 #define CTRL_EQ_QSIZE 128 56 57 #define TX_EQ_QSIZE 1024 58 #define TX_SGL_SEGS 36 59 #define TX_WR_FLITS (SGE_MAX_WR_LEN / 8) 60 61 #define UDBS_SEG_SHIFT 7 /* log2(UDBS_SEG_SIZE) */ 62 #define UDBS_DB_OFFSET 8 /* offset of the 4B doorbell in a segment */ 63 #define UDBS_WR_OFFSET 64 /* offset of the work request in a segment */ 64 65 typedef enum t4_port_flags { 66 TPF_INIT_DONE = (1 << 0), 67 TPF_OPEN = (1 << 1), 68 } t4_port_flags_t; 69 70 typedef enum t4_port_feat { 71 CXGBE_HW_LSO = (1 << 0), 72 CXGBE_HW_CSUM = (1 << 1), 73 } t4_port_feat_t; 74 75 struct port_info { 76 dev_info_t *dip; 77 mac_handle_t mh; 78 mac_callbacks_t *mc; 79 int mtu; 80 uint8_t hw_addr[ETHERADDRL]; 81 82 kmutex_t lock; 83 struct adapter *adapter; 84 85 t4_port_flags_t flags; 86 87 uint16_t viid; 88 int16_t xact_addr_filt; /* index of exact MAC address filter */ 89 uint16_t rss_size; /* size of VI's RSS table slice */ 90 uint16_t ntxq; /* # of tx queues */ 91 uint16_t first_txq; /* index of first tx queue */ 92 uint16_t nrxq; /* # of rx queues */ 93 uint16_t first_rxq; /* index of first rx queue */ 94 uint8_t lport; /* associated offload logical port */ 95 int8_t mdio_addr; 96 uint8_t port_type; 97 uint8_t mod_type; 98 uint8_t port_id; 99 uint8_t tx_chan; 100 uint8_t rx_chan; 101 uint8_t rx_cchan; 102 uint8_t instance; /* Associated adapter instance */ 103 uint8_t child_inst; /* Associated child instance */ 104 105 uint8_t tmr_idx; 106 int8_t pktc_idx; 107 uint8_t dbq_timer_idx; 108 109 struct link_config link_cfg; 110 struct port_stats stats; 111 t4_port_feat_t features; 112 uint8_t macaddr_cnt; 113 u8 rss_mode; 114 u16 viid_mirror; 115 kstat_t *ksp_config; 116 kstat_t *ksp_info; 117 kstat_t *ksp_fec; 118 119 u8 vivld; 120 u8 vin; 121 u8 smt_idx; 122 123 u8 vivld_mirror; 124 u8 vin_mirror; 125 u8 smt_idx_mirror; 126 }; 127 128 struct fl_sdesc { 129 struct rxbuf *rxb; 130 }; 131 132 struct tx_desc { 133 __be64 flit[8]; 134 }; 135 136 struct tx_sdesc { 137 mblk_t *mp_head; 138 mblk_t *mp_tail; 139 uint32_t txb_used; /* # of bytes of tx copy buffer used */ 140 uint16_t hdls_used; /* # of dma handles used */ 141 uint16_t desc_used; /* # of hardware descriptors used */ 142 uint64_t _pad; 143 }; 144 145 typedef enum t4_iq_flags { 146 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 147 IQ_INTR = (1 << 1), /* iq takes direct interrupt */ 148 IQ_HAS_FL = (1 << 2), /* iq has fl */ 149 } t4_iq_flags_t; 150 151 typedef enum t4_iq_state { 152 IQS_DISABLED = 0, 153 IQS_BUSY = 1, 154 IQS_IDLE = 2, 155 } t4_iq_state_t; 156 157 struct rxbuf_cache_params { 158 dev_info_t *dip; 159 ddi_dma_attr_t dma_attr_rx; 160 ddi_device_acc_attr_t acc_attr_rx; 161 size_t buf_size; 162 }; 163 164 struct sge_iq_stats { 165 uint64_t sis_overflow; 166 uint64_t sis_processed; 167 }; 168 169 /* 170 * These values are designed to match up with what is posted to GTS registers 171 * when processing an ingress queue. 172 * 173 * See: t4_iq_update_intr_cfg() and t4_iq_gts_update(). 174 */ 175 typedef enum t4_intr_config { 176 TIC_SE_INTR_ARM = 1, 177 TIC_TIMER0 = (0 << 1), 178 TIC_TIMER1 = (1 << 1), 179 TIC_TIMER2 = (2 << 1), 180 TIC_TIMER3 = (3 << 1), 181 TIC_TIMER4 = (4 << 1), 182 TIC_TIMER5 = (5 << 1), 183 TIC_START_COUNTER = (6 << 1), 184 } t4_intr_config_t; 185 186 /* 187 * Ingress Queue: T4 is producer, driver is consumer. 188 */ 189 struct sge_iq { 190 t4_iq_state_t state; 191 t4_iq_flags_t flags; 192 t4_intr_config_t intr_params; 193 194 ddi_dma_handle_t dhdl; 195 ddi_acc_handle_t ahdl; 196 197 __be64 *desc; /* KVA of descriptor ring */ 198 uint64_t ba; /* bus address of descriptor ring */ 199 const __be64 *cdesc; /* current descriptor */ 200 struct adapter *adapter; /* associated adapter */ 201 uint8_t gen; /* generation bit */ 202 int8_t intr_pktc_idx; /* packet count threshold index */ 203 uint8_t esize; /* size (bytes) of each entry in the queue */ 204 uint16_t qsize; /* size (# of entries) of the queue */ 205 uint16_t cidx; /* consumer index */ 206 uint16_t pending; /* # of descs processed since last doorbell */ 207 uint16_t cntxt_id; /* SGE context id for the iq */ 208 uint16_t abs_id; /* absolute SGE id for the iq */ 209 kmutex_t lock; /* Rx access lock */ 210 uint8_t polling; 211 212 struct sge_iq_stats stats; 213 214 STAILQ_ENTRY(sge_iq) link; 215 }; 216 217 typedef enum t4_eq_flags { 218 /* Initialization state flags: */ 219 EQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 220 EQ_MTX = (1 << 1), /* mutex has been initialized */ 221 222 /* Runtime state flags: */ 223 224 /* 225 * Short on resources (memory and/or descriptors) while attempting to 226 * enqueue work in EQ 227 */ 228 EQ_CORKED = (1 << 2), 229 } t4_eq_flags_t; 230 231 /* Listed in order of preference. */ 232 typedef enum t4_doorbells { 233 DOORBELL_UDB = (1 << 0), 234 DOORBELL_WCWR = (1 << 1), 235 DOORBELL_UDBWC = (1 << 2), 236 DOORBELL_KDB = (1 << 3), 237 } t4_doorbells_t; 238 239 /* 240 * Egress Queue: driver is producer, T4 is consumer. 241 * 242 * Note: A free list is an egress queue (driver produces the buffers and T4 243 * consumes them) but it's special enough to have its own struct (see sge_fl). 244 */ 245 struct sge_eq { 246 ddi_dma_handle_t desc_dhdl; 247 ddi_acc_handle_t desc_ahdl; 248 t4_eq_flags_t flags; 249 kmutex_t lock; 250 251 struct tx_desc *desc; /* KVA of descriptor ring */ 252 uint64_t ba; /* bus address of descriptor ring */ 253 struct sge_qstat *spg; /* status page, for convenience */ 254 t4_doorbells_t doorbells; 255 caddr_t udb; /* KVA of doorbell (lies within BAR2) */ 256 uint_t udb_qid; /* relative qid within the doorbell page */ 257 uint16_t cap; /* max # of desc, for convenience */ 258 uint16_t avail; /* available descriptors, for convenience */ 259 uint16_t qsize; /* size (# of entries) of the queue */ 260 uint16_t cidx; /* consumer idx (desc idx) */ 261 uint16_t pidx; /* producer idx (desc idx) */ 262 uint16_t pending; /* # of descriptors used since last doorbell */ 263 uint16_t iqid; /* iq that gets egr_update for the eq */ 264 uint8_t tx_chan; /* tx channel used by the eq */ 265 uint32_t cntxt_id; /* SGE context id for the eq */ 266 }; 267 268 typedef enum t4_fl_flags { 269 FL_MTX = (1 << 0), /* mutex has been initialized */ 270 FL_STARVING = (1 << 1), /* on the list of starving fl's */ 271 FL_DOOMED = (1 << 2), /* about to be destroyed */ 272 } t4_fl_flags_t; 273 274 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 275 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 276 277 struct sge_fl { 278 t4_fl_flags_t flags; 279 kmutex_t lock; 280 ddi_dma_handle_t dhdl; 281 ddi_acc_handle_t ahdl; 282 283 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 284 uint64_t ba; /* bus address of descriptor ring */ 285 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 286 uint32_t cap; /* max # of buffers, for convenience */ 287 uint16_t qsize; /* size (# of entries) of the queue */ 288 uint16_t cntxt_id; /* SGE context id for the freelist */ 289 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 290 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 291 uint32_t needed; /* # of buffers needed to fill up fl. */ 292 uint32_t lowat; /* # of buffers <= this means fl needs help */ 293 uint32_t pending; /* # of bufs allocated since last doorbell */ 294 uint32_t offset; /* current packet within the larger buffer */ 295 uint16_t copy_threshold; /* anything this size or less is copied up */ 296 297 uint64_t copied_up; /* # of frames copied into mblk and handed up */ 298 uint64_t passed_up; /* # of frames wrapped in mblk and handed up */ 299 uint64_t allocb_fail; /* # of mblk allocation failures */ 300 301 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 302 }; 303 304 /* txq: SGE egress queue + miscellaneous items */ 305 struct sge_txq { 306 struct sge_eq eq; /* MUST be first */ 307 308 struct port_info *port; /* the port this txq belongs to */ 309 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 310 mac_ring_handle_t ring_handle; 311 312 /* DMA handles used for tx */ 313 ddi_dma_handle_t *tx_dhdl; 314 uint32_t tx_dhdl_total; /* Total # of handles */ 315 uint32_t tx_dhdl_pidx; /* next handle to be used */ 316 uint32_t tx_dhdl_cidx; /* reclaimed up to this index */ 317 uint32_t tx_dhdl_avail; /* # of available handles */ 318 319 /* Copy buffers for tx */ 320 ddi_dma_handle_t txb_dhdl; 321 ddi_acc_handle_t txb_ahdl; 322 caddr_t txb_va; /* KVA of copy buffers area */ 323 uint64_t txb_ba; /* bus address of copy buffers area */ 324 uint32_t txb_size; /* total size */ 325 uint32_t txb_next; /* offset of next useable area in the buffer */ 326 uint32_t txb_avail; /* # of bytes available */ 327 uint16_t copy_threshold; /* anything this size or less is copied up */ 328 329 uint64_t txpkts; /* # of ethernet packets */ 330 uint64_t txbytes; /* # of ethernet bytes */ 331 kstat_t *ksp; 332 333 /* stats for common events first */ 334 335 uint64_t txcsum; /* # of times hardware assisted with checksum */ 336 uint64_t tso_wrs; /* # of IPv4 TSO work requests */ 337 uint64_t imm_wrs; /* # of work requests with immediate data */ 338 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 339 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 340 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 341 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 342 uint64_t txb_used; /* # of tx copy buffers used (64 byte each) */ 343 uint64_t hdl_used; /* # of DMA handles used */ 344 345 /* stats for not-that-common events */ 346 347 uint32_t txb_full; /* txb ran out of space */ 348 uint32_t dma_hdl_failed; /* couldn't obtain DMA handle */ 349 uint32_t dma_map_failed; /* couldn't obtain DMA mapping */ 350 uint32_t qfull; /* out of hardware descriptors */ 351 uint32_t pullup_early; /* # of pullups before starting frame's SGL */ 352 uint32_t pullup_late; /* # of pullups while building frame's SGL */ 353 uint32_t pullup_failed; /* # of failed pullups */ 354 uint32_t csum_failed; /* # of csum reqs we failed to fulfill */ 355 }; 356 357 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 358 struct sge_rxq { 359 struct sge_iq iq; /* MUST be first */ 360 struct sge_fl fl; 361 362 struct port_info *port; /* the port this rxq belongs to */ 363 kstat_t *ksp; 364 365 mac_ring_handle_t ring_handle; 366 uint64_t ring_gen_num; 367 368 /* stats for common events first */ 369 370 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 371 uint64_t rxpkts; /* # of ethernet packets */ 372 uint64_t rxbytes; /* # of ethernet bytes */ 373 374 /* stats for not-that-common events */ 375 376 uint32_t nomem; /* mblk allocation during rx failed */ 377 }; 378 379 struct sge { 380 int fl_starve_threshold; 381 int s_qpp; 382 uint64_t dbq_timer_tick; 383 uint16_t dbq_timers[SGE_NDBQTIMERS]; 384 385 int nrxq; /* total rx queues (all ports and the rest) */ 386 int ntxq; /* total tx queues (all ports and the rest) */ 387 int niq; /* total ingress queues */ 388 int neq; /* total egress queues */ 389 int stat_len; /* length of status page at ring end */ 390 int pktshift; /* padding between CPL & packet data */ 391 int fl_align; /* response queue message alignment */ 392 uint8_t fwq_tmr_idx; /* Intr. coalesce timer for FWQ */ 393 int8_t fwq_pktc_idx; /* Intr. coalesce count for FWQ */ 394 395 struct sge_iq fwq; /* Firmware event queue */ 396 struct sge_txq *txq; /* NIC tx queues */ 397 struct sge_rxq *rxq; /* NIC rx queues */ 398 399 uint_t iq_start; /* iq context id map start index */ 400 uint_t eq_start; /* eq context id map start index */ 401 uint_t iqmap_sz; /* size of iq context id map */ 402 uint_t eqmap_sz; /* size of eq context id map */ 403 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 404 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 405 406 /* Device access and DMA attributes for all the descriptor rings */ 407 ddi_device_acc_attr_t acc_attr_desc; 408 ddi_dma_attr_t dma_attr_desc; 409 410 /* Device access and DMA attributes for tx buffers */ 411 ddi_device_acc_attr_t acc_attr_tx; 412 ddi_dma_attr_t dma_attr_tx; 413 414 /* Device access and DMA attributes for rx buffers are in rxb_params */ 415 kmem_cache_t *rxbuf_cache; 416 struct rxbuf_cache_params rxb_params; 417 }; 418 419 struct driver_properties { 420 int max_ntxq_10g; 421 int max_nrxq_10g; 422 int max_ntxq_1g; 423 int max_nrxq_1g; 424 int intr_types; 425 int tmr_idx_10g; 426 int pktc_idx_10g; 427 int tmr_idx_1g; 428 int pktc_idx_1g; 429 uint8_t dbq_timer_idx; 430 uint8_t fwq_tmr_idx; 431 int8_t fwq_pktc_idx; 432 int qsize_txq; 433 int qsize_rxq; 434 435 uint_t holdoff_timer_us[SGE_NTIMERS]; 436 uint_t holdoff_pktcnt[SGE_NCOUNTERS]; 437 438 int wc; 439 440 int multi_rings; 441 int t4_fw_install; 442 }; 443 444 struct t4_mbox_list { 445 STAILQ_ENTRY(t4_mbox_list) link; 446 }; 447 448 typedef enum t4_adapter_flags { 449 /* Initialization progress status bits */ 450 TAF_INIT_DONE = (1 << 0), 451 TAF_FW_OK = (1 << 1), 452 TAF_INTR_FWD = (1 << 2), 453 TAF_INTR_ALLOC = (1 << 3), 454 455 /* State & capability bits */ 456 TAF_MASTER_PF = (1 << 4), 457 TAF_DBQ_TIMER = (1 << 5), 458 } t4_adapter_flags_t; 459 460 struct adapter { 461 list_node_t node; 462 dev_info_t *dip; 463 dev_t dev; 464 465 unsigned int pf; 466 unsigned int mbox; 467 468 unsigned int vpd_busy; 469 unsigned int vpd_flag; 470 471 u32 t4_bar0; 472 473 uint_t open; /* character device is open */ 474 475 /* PCI config space access handle */ 476 ddi_acc_handle_t pci_regh; 477 478 /* MMIO register access handle */ 479 ddi_acc_handle_t regh; 480 caddr_t regp; 481 /* BAR2 register access handle */ 482 ddi_acc_handle_t bar2_hdl; 483 caddr_t bar2_ptr; 484 485 /* Interrupt information */ 486 int intr_type; 487 int intr_count; 488 int intr_cap; 489 uint_t intr_pri; 490 ddi_intr_handle_t *intr_handle; 491 492 struct driver_properties props; 493 kstat_t *ksp; 494 kstat_t *ksp_stat; 495 496 struct sge sge; 497 498 struct port_info *port[MAX_NPORTS]; 499 uint8_t chan_map[NCHAN]; 500 uint32_t filter_mode; 501 502 t4_adapter_flags_t flags; 503 t4_doorbells_t doorbells; 504 505 unsigned int cfcsum; 506 struct adapter_params params; 507 508 kmutex_t lock; 509 kcondvar_t cv; 510 511 /* Starving free lists */ 512 kmutex_t sfl_lock; /* same cache-line as sc_lock? but that's ok */ 513 TAILQ_HEAD(, sge_fl) sfl; 514 timeout_id_t sfl_timer; 515 516 /* Sensors */ 517 id_t temp_sensor; 518 id_t volt_sensor; 519 520 ddi_ufm_handle_t *ufm_hdl; 521 522 /* support for single-threading access to adapter mailbox registers */ 523 kmutex_t mbox_lock; 524 STAILQ_HEAD(, t4_mbox_list) mbox_list; 525 }; 526 527 struct memwin { 528 uint32_t base; 529 uint32_t aperture; 530 }; 531 532 #define ADAPTER_LOCK(sc) mutex_enter(&(sc)->lock) 533 #define ADAPTER_UNLOCK(sc) mutex_exit(&(sc)->lock) 534 #define ADAPTER_LOCK_ASSERT_OWNED(sc) ASSERT(mutex_owned(&(sc)->lock)) 535 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) ASSERT(!mutex_owned(&(sc)->lock)) 536 537 #define PORT_LOCK(pi) mutex_enter(&(pi)->lock) 538 #define PORT_UNLOCK(pi) mutex_exit(&(pi)->lock) 539 #define PORT_LOCK_ASSERT_OWNED(pi) ASSERT(mutex_owned(&(pi)->lock)) 540 #define PORT_LOCK_ASSERT_NOTOWNED(pi) ASSERT(!mutex_owned(&(pi)->lock)) 541 542 #define IQ_LOCK(iq) mutex_enter(&(iq)->lock) 543 #define IQ_UNLOCK(iq) mutex_exit(&(iq)->lock) 544 #define IQ_LOCK_ASSERT_OWNED(iq) ASSERT(mutex_owned(&(iq)->lock)) 545 #define IQ_LOCK_ASSERT_NOTOWNED(iq) ASSERT(!mutex_owned(&(iq)->lock)) 546 547 #define FL_LOCK(fl) mutex_enter(&(fl)->lock) 548 #define FL_UNLOCK(fl) mutex_exit(&(fl)->lock) 549 #define FL_LOCK_ASSERT_OWNED(fl) ASSERT(mutex_owned(&(fl)->lock)) 550 #define FL_LOCK_ASSERT_NOTOWNED(fl) ASSERT(!mutex_owned(&(fl)->lock)) 551 552 #define RXQ_LOCK(rxq) IQ_LOCK(&(rxq)->iq) 553 #define RXQ_UNLOCK(rxq) IQ_UNLOCK(&(rxq)->iq) 554 #define RXQ_LOCK_ASSERT_OWNED(rxq) IQ_LOCK_ASSERT_OWNED(&(rxq)->iq) 555 #define RXQ_LOCK_ASSERT_NOTOWNED(rxq) IQ_LOCK_ASSERT_NOTOWNED(&(rxq)->iq) 556 557 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 558 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 559 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 560 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 561 562 #define EQ_LOCK(eq) mutex_enter(&(eq)->lock) 563 #define EQ_UNLOCK(eq) mutex_exit(&(eq)->lock) 564 #define EQ_LOCK_ASSERT_OWNED(eq) ASSERT(mutex_owned(&(eq)->lock)) 565 #define EQ_LOCK_ASSERT_NOTOWNED(eq) ASSERT(!mutex_owned(&(eq)->lock)) 566 567 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 568 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 569 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 570 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 571 572 #define for_each_txq(pi, iter, txq) \ 573 txq = &pi->adapter->sge.txq[pi->first_txq]; \ 574 for (iter = 0; iter < pi->ntxq; ++iter, ++txq) 575 #define for_each_rxq(pi, iter, rxq) \ 576 rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \ 577 for (iter = 0; iter < pi->nrxq; ++iter, ++rxq) 578 579 #define NFIQ(sc) ((sc)->intr_count > 1 ? (sc)->intr_count - 1 : 1) 580 581 /* One for errors, one for firmware events */ 582 #define T4_EXTRA_INTR 2 583 584 static inline void t4_mbox_list_add(struct adapter *adap, 585 struct t4_mbox_list *entry) 586 { 587 mutex_enter(&adap->mbox_lock); 588 STAILQ_INSERT_TAIL(&adap->mbox_list, entry, link); 589 mutex_exit(&adap->mbox_lock); 590 } 591 592 static inline void t4_mbox_list_del(struct adapter *adap, 593 struct t4_mbox_list *entry) 594 { 595 mutex_enter(&adap->mbox_lock); 596 STAILQ_REMOVE(&adap->mbox_list, entry, t4_mbox_list, link); 597 mutex_exit(&adap->mbox_lock); 598 } 599 600 static inline struct t4_mbox_list * 601 t4_mbox_list_first_entry(struct adapter *adap) 602 { 603 return (STAILQ_FIRST(&adap->mbox_list)); 604 } 605 606 static inline struct port_info * 607 adap2pinfo(struct adapter *sc, int idx) 608 { 609 return (sc->port[idx]); 610 } 611 612 static inline struct sge_rxq * 613 iq_to_rxq(struct sge_iq *iq) 614 { 615 return (__containerof(iq, struct sge_rxq, iq)); 616 } 617 618 static inline bool 619 t4_port_is_10xg(const struct port_info *pi) 620 { 621 return (pi->link_cfg.pcaps & 622 (FW_PORT_CAP32_SPEED_400G | 623 FW_PORT_CAP32_SPEED_200G | 624 FW_PORT_CAP32_SPEED_100G | 625 FW_PORT_CAP32_SPEED_50G | 626 FW_PORT_CAP32_SPEED_40G | 627 FW_PORT_CAP32_SPEED_25G | 628 FW_PORT_CAP32_SPEED_10G)); 629 } 630 631 static inline unsigned int t4_use_ldst(struct adapter *adap) 632 { 633 return (adap->flags & FW_OK); 634 } 635 636 static inline void t4_db_full(struct adapter *adap) {} 637 static inline void t4_db_dropped(struct adapter *adap) {} 638 639 /* Is chip version equal to specified value? */ 640 static inline bool 641 t4_cver_eq(const adapter_t *adap, uint8_t ver) 642 { 643 return (CHELSIO_CHIP_VERSION(adap->params.chip) == ver); 644 } 645 646 /* Is chip version greater than or equal to specified value? */ 647 static inline bool 648 t4_cver_ge(const adapter_t *adap, uint8_t ver) 649 { 650 return (CHELSIO_CHIP_VERSION(adap->params.chip) >= ver); 651 } 652 653 /* t4_nexus.c */ 654 int t4_port_full_init(struct port_info *); 655 void t4_port_queues_enable(struct port_info *pi); 656 void t4_port_queues_disable(struct port_info *pi); 657 658 uint32_t t4_read_reg(struct adapter *, uint32_t); 659 void t4_write_reg(struct adapter *, uint32_t, uint32_t); 660 uint64_t t4_read_reg64(struct adapter *, uint32_t); 661 void t4_write_reg64(struct adapter *, uint32_t, uint64_t); 662 663 /* t4_debug.c */ 664 void t4_debug_init(void); 665 void t4_debug_fini(void); 666 667 /* t4_sge.c */ 668 void t4_sge_init(struct adapter *sc); 669 int t4_alloc_fwq(struct adapter *); 670 int t4_free_fwq(struct adapter *); 671 int t4_setup_port_queues(struct port_info *pi); 672 int t4_teardown_port_queues(struct port_info *pi); 673 uint_t t4_intr_all(caddr_t arg1, caddr_t arg2); 674 uint_t t4_intr(caddr_t arg1, caddr_t arg2); 675 uint_t t4_intr_err(caddr_t arg1, caddr_t arg2); 676 void t4_iq_gts_update(struct sge_iq *, t4_intr_config_t, uint16_t); 677 void t4_iq_update_intr_cfg(struct sge_iq *, uint8_t, int8_t); 678 void t4_eq_update_dbq_timer(struct sge_eq *, struct port_info *); 679 int t4_mgmt_tx(struct adapter *sc, mblk_t *m); 680 681 mblk_t *t4_eth_tx(void *, mblk_t *); 682 mblk_t *t4_mc_tx(void *arg, mblk_t *m); 683 mblk_t *t4_ring_rx(struct sge_rxq *rxq, int poll_bytes); 684 685 /* t4_mac.c */ 686 void t4_mc_cb_init(struct port_info *); 687 void t4_os_link_changed(struct adapter *sc, int idx, int link_stat); 688 void t4_mac_rx(struct port_info *pi, struct sge_rxq *rxq, mblk_t *m); 689 void t4_mac_tx_update(struct port_info *pi, struct sge_txq *txq); 690 int t4_addmac(void *arg, const uint8_t *ucaddr); 691 const char **t4_get_priv_props(struct port_info *, size_t *); 692 uint8_t t4_choose_holdoff_timer(struct adapter *, uint_t); 693 int8_t t4_choose_holdoff_pktcnt(struct adapter *, int); 694 uint_t t4_choose_dbq_timer(struct adapter *, uint_t); 695 696 /* t4_ioctl.c */ 697 int t4_ioctl(struct adapter *sc, int cmd, void *data, int mode); 698 699 #endif /* __CXGBE_ADAPTER_H */ 700