1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4 support code. 14 * 15 * Copyright (C) 2011-2013 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23 #ifndef __CXGBE_ADAPTER_H 24 #define __CXGBE_ADAPTER_H 25 26 #include <sys/ddi.h> 27 #include <sys/mac_provider.h> 28 #include <sys/ethernet.h> 29 #include <sys/queue.h> 30 #include <sys/containerof.h> 31 32 #include "offload.h" 33 #include "firmware/t4fw_interface.h" 34 #include "shared.h" 35 36 struct adapter; 37 typedef struct adapter adapter_t; 38 39 enum { 40 FW_IQ_QSIZE = 256, 41 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 42 43 RX_IQ_QSIZE = 1024, 44 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 45 46 EQ_ESIZE = 64, /* All egres queues use this entry size */ 47 48 RX_FL_ESIZE = 64, /* 8 64bit addresses */ 49 50 FL_BUF_SIZES = 4, 51 52 CTRL_EQ_QSIZE = 128, 53 54 TX_EQ_QSIZE = 1024, 55 TX_SGL_SEGS = 36, 56 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 57 }; 58 59 enum { 60 /* adapter flags */ 61 FULL_INIT_DONE = (1 << 0), 62 FW_OK = (1 << 1), 63 INTR_FWD = (1 << 2), 64 INTR_ALLOCATED = (1 << 3), 65 MASTER_PF = (1 << 4), 66 67 CXGBE_BUSY = (1 << 9), 68 69 /* port flags */ 70 DOOMED = (1 << 0), 71 PORT_INIT_DONE = (1 << 1), 72 }; 73 74 enum { 75 /* Features */ 76 CXGBE_HW_LSO = (1 << 0), 77 CXGBE_HW_CSUM = (1 << 1), 78 }; 79 80 enum { 81 UDBS_SEG_SHIFT = 7, /* log2(UDBS_SEG_SIZE) */ 82 UDBS_DB_OFFSET = 8, /* offset of the 4B doorbell in a segment */ 83 UDBS_WR_OFFSET = 64, /* offset of the work request in a segment */ 84 }; 85 86 #define IS_DOOMED(pi) (pi->flags & DOOMED) 87 #define SET_DOOMED(pi) do { pi->flags |= DOOMED; } while (0) 88 #define IS_BUSY(sc) (sc->flags & CXGBE_BUSY) 89 #define SET_BUSY(sc) do { sc->flags |= CXGBE_BUSY; } while (0) 90 #define CLR_BUSY(sc) do { sc->flags &= ~CXGBE_BUSY; } while (0) 91 92 struct port_info { 93 PORT_INFO_HDR; 94 95 kmutex_t lock; 96 struct adapter *adapter; 97 98 #ifdef TCP_OFFLOAD_ENABLE 99 void *tdev; 100 #endif 101 102 unsigned int flags; 103 104 uint16_t viid; 105 int16_t xact_addr_filt; /* index of exact MAC address filter */ 106 uint16_t rss_size; /* size of VI's RSS table slice */ 107 uint16_t ntxq; /* # of tx queues */ 108 uint16_t first_txq; /* index of first tx queue */ 109 uint16_t nrxq; /* # of rx queues */ 110 uint16_t first_rxq; /* index of first rx queue */ 111 #ifdef TCP_OFFLOAD_ENABLE 112 uint16_t nofldtxq; /* # of offload tx queues */ 113 uint16_t first_ofld_txq; /* index of first offload tx queue */ 114 uint16_t nofldrxq; /* # of offload rx queues */ 115 uint16_t first_ofld_rxq; /* index of first offload rx queue */ 116 #endif 117 uint8_t lport; /* associated offload logical port */ 118 int8_t mdio_addr; 119 uint8_t port_type; 120 uint8_t mod_type; 121 uint8_t port_id; 122 uint8_t tx_chan; 123 uint8_t rx_chan; 124 uint8_t rx_cchan; 125 uint8_t instance; /* Associated adapter instance */ 126 uint8_t child_inst; /* Associated child instance */ 127 uint8_t tmr_idx; 128 int8_t pktc_idx; 129 struct link_config link_cfg; 130 struct port_stats stats; 131 uint32_t features; 132 uint8_t macaddr_cnt; 133 u8 rss_mode; 134 u16 viid_mirror; 135 kstat_t *ksp_config; 136 kstat_t *ksp_info; 137 138 u8 vivld; 139 u8 vin; 140 u8 smt_idx; 141 142 u8 vivld_mirror; 143 u8 vin_mirror; 144 u8 smt_idx_mirror; 145 }; 146 147 struct fl_sdesc { 148 struct rxbuf *rxb; 149 }; 150 151 struct tx_desc { 152 __be64 flit[8]; 153 }; 154 155 /* DMA maps used for tx */ 156 struct tx_maps { 157 ddi_dma_handle_t *map; 158 uint32_t map_total; /* # of DMA maps */ 159 uint32_t map_pidx; /* next map to be used */ 160 uint32_t map_cidx; /* reclaimed up to this index */ 161 uint32_t map_avail; /* # of available maps */ 162 }; 163 164 struct tx_sdesc { 165 mblk_t *m; 166 uint32_t txb_used; /* # of bytes of tx copy buffer used */ 167 uint16_t hdls_used; /* # of dma handles used */ 168 uint16_t desc_used; /* # of hardware descriptors used */ 169 }; 170 171 enum { 172 /* iq flags */ 173 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 174 IQ_INTR = (1 << 1), /* iq takes direct interrupt */ 175 IQ_HAS_FL = (1 << 2), /* iq has fl */ 176 177 /* iq state */ 178 IQS_DISABLED = 0, 179 IQS_BUSY = 1, 180 IQS_IDLE = 2, 181 }; 182 183 /* 184 * Ingress Queue: T4 is producer, driver is consumer. 185 */ 186 struct sge_iq { 187 unsigned int flags; 188 ddi_dma_handle_t dhdl; 189 ddi_acc_handle_t ahdl; 190 191 volatile uint_t state; 192 __be64 *desc; /* KVA of descriptor ring */ 193 uint64_t ba; /* bus address of descriptor ring */ 194 const __be64 *cdesc; /* current descriptor */ 195 struct adapter *adapter; /* associated adapter */ 196 uint8_t gen; /* generation bit */ 197 uint8_t intr_params; /* interrupt holdoff parameters */ 198 int8_t intr_pktc_idx; /* packet count threshold index */ 199 uint8_t intr_next; /* holdoff for next interrupt */ 200 uint8_t esize; /* size (bytes) of each entry in the queue */ 201 uint16_t qsize; /* size (# of entries) of the queue */ 202 uint16_t cidx; /* consumer index */ 203 uint16_t pending; /* # of descs processed since last doorbell */ 204 uint16_t cntxt_id; /* SGE context id for the iq */ 205 uint16_t abs_id; /* absolute SGE id for the iq */ 206 kmutex_t lock; /* Rx access lock */ 207 uint8_t polling; 208 209 STAILQ_ENTRY(sge_iq) link; 210 }; 211 212 enum { 213 EQ_CTRL = 1, 214 EQ_ETH = 2, 215 #ifdef TCP_OFFLOAD_ENABLE 216 EQ_OFLD = 3, 217 #endif 218 219 /* eq flags */ 220 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 221 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 222 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 223 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 224 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 225 EQ_MTX = (1 << 7), /* mutex has been initialized */ 226 EQ_STARTED = (1 << 8), /* started */ 227 }; 228 229 /* Listed in order of preference. Update t4_sysctls too if you change these */ 230 enum {DOORBELL_UDB=0x1 , DOORBELL_WCWR=0x2, DOORBELL_UDBWC=0x4, DOORBELL_KDB=0x8}; 231 232 /* 233 * Egress Queue: driver is producer, T4 is consumer. 234 * 235 * Note: A free list is an egress queue (driver produces the buffers and T4 236 * consumes them) but it's special enough to have its own struct (see sge_fl). 237 */ 238 struct sge_eq { 239 ddi_dma_handle_t desc_dhdl; 240 ddi_acc_handle_t desc_ahdl; 241 unsigned int flags; 242 kmutex_t lock; 243 244 struct tx_desc *desc; /* KVA of descriptor ring */ 245 uint64_t ba; /* bus address of descriptor ring */ 246 struct sge_qstat *spg; /* status page, for convenience */ 247 int doorbells; 248 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 249 u_int udb_qid; /* relative qid within the doorbell page */ 250 uint16_t cap; /* max # of desc, for convenience */ 251 uint16_t avail; /* available descriptors, for convenience */ 252 uint16_t qsize; /* size (# of entries) of the queue */ 253 uint16_t cidx; /* consumer idx (desc idx) */ 254 uint16_t pidx; /* producer idx (desc idx) */ 255 uint16_t pending; /* # of descriptors used since last doorbell */ 256 uint16_t iqid; /* iq that gets egr_update for the eq */ 257 uint8_t tx_chan; /* tx channel used by the eq */ 258 uint32_t cntxt_id; /* SGE context id for the eq */ 259 }; 260 261 enum { 262 /* fl flags */ 263 FL_MTX = (1 << 0), /* mutex has been initialized */ 264 FL_STARVING = (1 << 1), /* on the list of starving fl's */ 265 FL_DOOMED = (1 << 2), /* about to be destroyed */ 266 }; 267 268 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 269 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 270 271 struct sge_fl { 272 unsigned int flags; 273 kmutex_t lock; 274 ddi_dma_handle_t dhdl; 275 ddi_acc_handle_t ahdl; 276 277 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 278 uint64_t ba; /* bus address of descriptor ring */ 279 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 280 uint32_t cap; /* max # of buffers, for convenience */ 281 uint16_t qsize; /* size (# of entries) of the queue */ 282 uint16_t cntxt_id; /* SGE context id for the freelist */ 283 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 284 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 285 uint32_t needed; /* # of buffers needed to fill up fl. */ 286 uint32_t lowat; /* # of buffers <= this means fl needs help */ 287 uint32_t pending; /* # of bufs allocated since last doorbell */ 288 uint32_t offset; /* current packet within the larger buffer */ 289 uint16_t copy_threshold; /* anything this size or less is copied up */ 290 291 uint64_t copied_up; /* # of frames copied into mblk and handed up */ 292 uint64_t passed_up; /* # of frames wrapped in mblk and handed up */ 293 uint64_t allocb_fail; /* # of mblk allocation failures */ 294 295 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 296 }; 297 298 /* txq: SGE egress queue + miscellaneous items */ 299 struct sge_txq { 300 struct sge_eq eq; /* MUST be first */ 301 302 struct port_info *port; /* the port this txq belongs to */ 303 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 304 mac_ring_handle_t ring_handle; 305 306 /* DMA handles used for tx */ 307 ddi_dma_handle_t *tx_dhdl; 308 uint32_t tx_dhdl_total; /* Total # of handles */ 309 uint32_t tx_dhdl_pidx; /* next handle to be used */ 310 uint32_t tx_dhdl_cidx; /* reclaimed up to this index */ 311 uint32_t tx_dhdl_avail; /* # of available handles */ 312 313 /* Copy buffers for tx */ 314 ddi_dma_handle_t txb_dhdl; 315 ddi_acc_handle_t txb_ahdl; 316 caddr_t txb_va; /* KVA of copy buffers area */ 317 uint64_t txb_ba; /* bus address of copy buffers area */ 318 uint32_t txb_size; /* total size */ 319 uint32_t txb_next; /* offset of next useable area in the buffer */ 320 uint32_t txb_avail; /* # of bytes available */ 321 uint16_t copy_threshold; /* anything this size or less is copied up */ 322 323 uint64_t txpkts; /* # of ethernet packets */ 324 uint64_t txbytes; /* # of ethernet bytes */ 325 kstat_t *ksp; 326 327 /* stats for common events first */ 328 329 uint64_t txcsum; /* # of times hardware assisted with checksum */ 330 uint64_t tso_wrs; /* # of IPv4 TSO work requests */ 331 uint64_t imm_wrs; /* # of work requests with immediate data */ 332 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 333 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 334 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 335 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 336 uint64_t txb_used; /* # of tx copy buffers used (64 byte each) */ 337 uint64_t hdl_used; /* # of DMA handles used */ 338 339 /* stats for not-that-common events */ 340 341 uint32_t txb_full; /* txb ran out of space */ 342 uint32_t dma_hdl_failed; /* couldn't obtain DMA handle */ 343 uint32_t dma_map_failed; /* couldn't obtain DMA mapping */ 344 uint32_t qfull; /* out of hardware descriptors */ 345 uint32_t qflush; /* # of SGE_EGR_UPDATE notifications for txq */ 346 uint32_t pullup_early; /* # of pullups before starting frame's SGL */ 347 uint32_t pullup_late; /* # of pullups while building frame's SGL */ 348 uint32_t pullup_failed; /* # of failed pullups */ 349 }; 350 351 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 352 struct sge_rxq { 353 struct sge_iq iq; /* MUST be first */ 354 struct sge_fl fl; 355 356 struct port_info *port; /* the port this rxq belongs to */ 357 kstat_t *ksp; 358 359 mac_ring_handle_t ring_handle; 360 uint64_t ring_gen_num; 361 362 /* stats for common events first */ 363 364 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 365 uint64_t rxpkts; /* # of ethernet packets */ 366 uint64_t rxbytes; /* # of ethernet bytes */ 367 368 /* stats for not-that-common events */ 369 370 uint32_t nomem; /* mblk allocation during rx failed */ 371 }; 372 373 #ifdef TCP_OFFLOAD_ENABLE 374 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 375 struct sge_ofld_rxq { 376 struct sge_iq iq; /* MUST be first */ 377 struct sge_fl fl; 378 }; 379 380 /* 381 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 382 * and offload tx queues are of this type. 383 */ 384 struct sge_wrq { 385 struct sge_eq eq; /* MUST be first */ 386 387 struct adapter *adapter; 388 389 /* List of WRs held up due to lack of tx descriptors */ 390 struct mblk_pair wr_list; 391 392 /* stats for common events first */ 393 394 uint64_t tx_wrs; /* # of tx work requests */ 395 396 /* stats for not-that-common events */ 397 398 uint32_t no_desc; /* out of hardware descriptors */ 399 }; 400 #endif 401 402 struct sge { 403 int fl_starve_threshold; 404 int s_qpp; 405 406 int nrxq; /* total rx queues (all ports and the rest) */ 407 int ntxq; /* total tx queues (all ports and the rest) */ 408 #ifdef TCP_OFFLOAD_ENABLE 409 int nofldrxq; /* total # of TOE rx queues */ 410 int nofldtxq; /* total # of TOE tx queues */ 411 #endif 412 int niq; /* total ingress queues */ 413 int neq; /* total egress queues */ 414 int stat_len; /* length of status page at ring end */ 415 int pktshift; /* padding between CPL & packet data */ 416 int fl_align; /* response queue message alignment */ 417 418 struct sge_iq fwq; /* Firmware event queue */ 419 #ifdef TCP_OFFLOAD_ENABLE 420 struct sge_wrq mgmtq; /* Management queue (Control queue) */ 421 #endif 422 struct sge_txq *txq; /* NIC tx queues */ 423 struct sge_rxq *rxq; /* NIC rx queues */ 424 #ifdef TCP_OFFLOAD_ENABLE 425 struct sge_wrq *ctrlq; /* Control queues */ 426 struct sge_wrq *ofld_txq; /* TOE tx queues */ 427 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 428 #endif 429 430 uint16_t iq_start; 431 int eq_start; 432 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 433 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 434 435 /* Device access and DMA attributes for all the descriptor rings */ 436 ddi_device_acc_attr_t acc_attr_desc; 437 ddi_dma_attr_t dma_attr_desc; 438 439 /* Device access and DMA attributes for tx buffers */ 440 ddi_device_acc_attr_t acc_attr_tx; 441 ddi_dma_attr_t dma_attr_tx; 442 443 /* Device access and DMA attributes for rx buffers are in rxb_params */ 444 kmem_cache_t *rxbuf_cache; 445 struct rxbuf_cache_params rxb_params; 446 }; 447 448 struct driver_properties { 449 /* There is a driver.conf variable for each of these */ 450 int max_ntxq_10g; 451 int max_nrxq_10g; 452 int max_ntxq_1g; 453 int max_nrxq_1g; 454 #ifdef TCP_OFFLOAD_ENABLE 455 int max_nofldtxq_10g; 456 int max_nofldrxq_10g; 457 int max_nofldtxq_1g; 458 int max_nofldrxq_1g; 459 #endif 460 int intr_types; 461 int tmr_idx_10g; 462 int pktc_idx_10g; 463 int tmr_idx_1g; 464 int pktc_idx_1g; 465 int qsize_txq; 466 int qsize_rxq; 467 468 int timer_val[SGE_NTIMERS]; 469 int counter_val[SGE_NCOUNTERS]; 470 471 int wc; 472 473 int multi_rings; 474 int t4_fw_install; 475 }; 476 477 struct rss_header; 478 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 479 mblk_t *); 480 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 481 482 struct adapter { 483 SLIST_ENTRY(adapter) link; 484 dev_info_t *dip; 485 dev_t dev; 486 487 unsigned int pf; 488 unsigned int mbox; 489 490 unsigned int vpd_busy; 491 unsigned int vpd_flag; 492 493 u32 t4_bar0; 494 495 uint_t open; /* character device is open */ 496 497 /* PCI config space access handle */ 498 ddi_acc_handle_t pci_regh; 499 500 /* MMIO register access handle */ 501 ddi_acc_handle_t regh; 502 caddr_t regp; 503 /* BAR1 register access handle */ 504 ddi_acc_handle_t reg1h; 505 caddr_t reg1p; 506 507 /* Interrupt information */ 508 int intr_type; 509 int intr_count; 510 int intr_cap; 511 uint_t intr_pri; 512 ddi_intr_handle_t *intr_handle; 513 514 struct driver_properties props; 515 kstat_t *ksp; 516 kstat_t *ksp_stat; 517 518 struct sge sge; 519 520 struct port_info *port[MAX_NPORTS]; 521 ddi_taskq_t *tq[NCHAN]; 522 uint8_t chan_map[NCHAN]; 523 uint32_t filter_mode; 524 525 struct l2t_data *l2t; /* L2 table */ 526 struct tid_info tids; 527 528 int doorbells; 529 int registered_device_map; 530 int open_device_map; 531 int flags; 532 533 unsigned int cfcsum; 534 struct adapter_params params; 535 struct t4_virt_res vres; 536 537 #ifdef TCP_OFFLOAD_ENABLE 538 struct uld_softc tom; 539 struct tom_tunables tt; 540 #endif 541 542 #ifdef TCP_OFFLOAD_ENABLE 543 int offload_map; 544 #endif 545 uint16_t linkcaps; 546 uint16_t niccaps; 547 uint16_t toecaps; 548 uint16_t rdmacaps; 549 uint16_t iscsicaps; 550 uint16_t fcoecaps; 551 552 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ 553 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 554 555 kmutex_t lock; 556 kcondvar_t cv; 557 558 /* Starving free lists */ 559 kmutex_t sfl_lock; /* same cache-line as sc_lock? but that's ok */ 560 TAILQ_HEAD(, sge_fl) sfl; 561 timeout_id_t sfl_timer; 562 }; 563 564 enum { 565 NIC_H = 0, 566 TOM_H, 567 IW_H, 568 ISCSI_H 569 }; 570 571 struct memwin { 572 uint32_t base; 573 uint32_t aperture; 574 }; 575 576 #define ADAPTER_LOCK(sc) mutex_enter(&(sc)->lock) 577 #define ADAPTER_UNLOCK(sc) mutex_exit(&(sc)->lock) 578 #define ADAPTER_LOCK_ASSERT_OWNED(sc) ASSERT(mutex_owned(&(sc)->lock)) 579 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) ASSERT(!mutex_owned(&(sc)->lock)) 580 581 #define PORT_LOCK(pi) mutex_enter(&(pi)->lock) 582 #define PORT_UNLOCK(pi) mutex_exit(&(pi)->lock) 583 #define PORT_LOCK_ASSERT_OWNED(pi) ASSERT(mutex_owned(&(pi)->lock)) 584 #define PORT_LOCK_ASSERT_NOTOWNED(pi) ASSERT(!mutex_owned(&(pi)->lock)) 585 586 #define IQ_LOCK(iq) mutex_enter(&(iq)->lock) 587 #define IQ_UNLOCK(iq) mutex_exit(&(iq)->lock) 588 #define IQ_LOCK_ASSERT_OWNED(iq) ASSERT(mutex_owned(&(iq)->lock)) 589 #define IQ_LOCK_ASSERT_NOTOWNED(iq) ASSERT(!mutex_owned(&(iq)->lock)) 590 591 #define FL_LOCK(fl) mutex_enter(&(fl)->lock) 592 #define FL_UNLOCK(fl) mutex_exit(&(fl)->lock) 593 #define FL_LOCK_ASSERT_OWNED(fl) ASSERT(mutex_owned(&(fl)->lock)) 594 #define FL_LOCK_ASSERT_NOTOWNED(fl) ASSERT(!mutex_owned(&(fl)->lock)) 595 596 #define RXQ_LOCK(rxq) IQ_LOCK(&(rxq)->iq) 597 #define RXQ_UNLOCK(rxq) IQ_UNLOCK(&(rxq)->iq) 598 #define RXQ_LOCK_ASSERT_OWNED(rxq) IQ_LOCK_ASSERT_OWNED(&(rxq)->iq) 599 #define RXQ_LOCK_ASSERT_NOTOWNED(rxq) IQ_LOCK_ASSERT_NOTOWNED(&(rxq)->iq) 600 601 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 602 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 603 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 604 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 605 606 #define EQ_LOCK(eq) mutex_enter(&(eq)->lock) 607 #define EQ_UNLOCK(eq) mutex_exit(&(eq)->lock) 608 #define EQ_LOCK_ASSERT_OWNED(eq) ASSERT(mutex_owned(&(eq)->lock)) 609 #define EQ_LOCK_ASSERT_NOTOWNED(eq) ASSERT(!mutex_owned(&(eq)->lock)) 610 611 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 612 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 613 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 614 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 615 616 #define for_each_txq(pi, iter, txq) \ 617 txq = &pi->adapter->sge.txq[pi->first_txq]; \ 618 for (iter = 0; iter < pi->ntxq; ++iter, ++txq) 619 #define for_each_rxq(pi, iter, rxq) \ 620 rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \ 621 for (iter = 0; iter < pi->nrxq; ++iter, ++rxq) 622 #define for_each_ofld_txq(pi, iter, ofld_txq) \ 623 ofld_txq = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq]; \ 624 for (iter = 0; iter < pi->nofldtxq; ++iter, ++ofld_txq) 625 #define for_each_ofld_rxq(pi, iter, ofld_rxq) \ 626 ofld_rxq = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq]; \ 627 for (iter = 0; iter < pi->nofldrxq; ++iter, ++ofld_rxq) 628 629 #define NFIQ(sc) ((sc)->intr_count > 1 ? (sc)->intr_count - 1 : 1) 630 631 /* One for errors, one for firmware events */ 632 #define T4_EXTRA_INTR 2 633 634 /* Presently disabling locking around mbox access 635 * We may need to reenable it later 636 */ 637 typedef int t4_os_lock_t; 638 static inline void t4_os_lock(t4_os_lock_t *lock) 639 { 640 641 } 642 static inline void t4_os_unlock(t4_os_lock_t *lock) 643 { 644 645 } 646 647 static inline uint32_t 648 t4_read_reg(struct adapter *sc, uint32_t reg) 649 { 650 /* LINTED: E_BAD_PTR_CAST_ALIGN */ 651 return (ddi_get32(sc->regh, (uint32_t *)(sc->regp + reg))); 652 } 653 654 static inline void 655 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 656 { 657 /* LINTED: E_BAD_PTR_CAST_ALIGN */ 658 ddi_put32(sc->regh, (uint32_t *)(sc->regp + reg), val); 659 } 660 661 static inline void 662 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 663 { 664 *val = pci_config_get8(sc->pci_regh, reg); 665 } 666 667 static inline void 668 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 669 { 670 pci_config_put8(sc->pci_regh, reg, val); 671 } 672 673 static inline void 674 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 675 { 676 *val = pci_config_get16(sc->pci_regh, reg); 677 } 678 679 static inline void 680 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 681 { 682 pci_config_put16(sc->pci_regh, reg, val); 683 } 684 685 static inline void 686 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 687 { 688 *val = pci_config_get32(sc->pci_regh, reg); 689 } 690 691 static inline void 692 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 693 { 694 pci_config_put32(sc->pci_regh, reg, val); 695 } 696 697 static inline uint64_t 698 t4_read_reg64(struct adapter *sc, uint32_t reg) 699 { 700 /* LINTED: E_BAD_PTR_CAST_ALIGN */ 701 return (ddi_get64(sc->regh, (uint64_t *)(sc->regp + reg))); 702 } 703 704 static inline void 705 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 706 { 707 /* LINTED: E_BAD_PTR_CAST_ALIGN */ 708 ddi_put64(sc->regh, (uint64_t *)(sc->regp + reg), val); 709 } 710 711 static inline struct port_info * 712 adap2pinfo(struct adapter *sc, int idx) 713 { 714 return (sc->port[idx]); 715 } 716 717 static inline void 718 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 719 { 720 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHERADDRL); 721 } 722 723 static inline bool 724 is_10G_port(const struct port_info *pi) 725 { 726 return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G) != 0); 727 } 728 729 static inline struct sge_rxq * 730 iq_to_rxq(struct sge_iq *iq) 731 { 732 return (__containerof(iq, struct sge_rxq, iq)); 733 } 734 735 static inline bool 736 is_25G_port(const struct port_info *pi) 737 { 738 return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G) != 0); 739 } 740 741 static inline bool 742 is_40G_port(const struct port_info *pi) 743 { 744 return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G) != 0); 745 } 746 747 static inline bool 748 is_100G_port(const struct port_info *pi) 749 { 750 return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G) != 0); 751 } 752 753 static inline bool 754 is_10XG_port(const struct port_info *pi) 755 { 756 return (is_10G_port(pi) || is_40G_port(pi) || 757 is_25G_port(pi) || is_100G_port(pi)); 758 } 759 760 static inline char * 761 print_port_speed(const struct port_info *pi) 762 { 763 if (!pi) 764 return "-"; 765 766 if (is_100G_port(pi)) 767 return "100G"; 768 else if (is_40G_port(pi)) 769 return "40G"; 770 else if (is_25G_port(pi)) 771 return "25G"; 772 else if (is_10G_port(pi)) 773 return "10G"; 774 else 775 return "1G"; 776 } 777 778 #ifdef TCP_OFFLOAD_ENABLE 779 int t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m0); 780 781 static inline int 782 t4_wrq_tx(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m) 783 { 784 int rc; 785 786 TXQ_LOCK(wrq); 787 rc = t4_wrq_tx_locked(sc, wrq, m); 788 TXQ_UNLOCK(wrq); 789 return (rc); 790 } 791 #endif 792 793 /** 794 * t4_os_pci_read_seeprom - read four bytes of SEEPROM/VPD contents 795 * @adapter: the adapter 796 * @addr: SEEPROM/VPD Address to read 797 * @valp: where to store the value read 798 * 799 * Read a 32-bit value from the given address in the SEEPROM/VPD. The address 800 * must be four-byte aligned. Returns 0 on success, a negative erro number 801 * on failure. 802 */ 803 static inline int t4_os_pci_read_seeprom(adapter_t *adapter, 804 int addr, u32 *valp) 805 { 806 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 807 int ret; 808 809 ret = t4_seeprom_read(adapter, addr, valp); 810 811 return ret >= 0 ? 0 : ret; 812 } 813 814 /** 815 * t4_os_pci_write_seeprom - write four bytes of SEEPROM/VPD contents 816 * @adapter: the adapter 817 * @addr: SEEPROM/VPD Address to write 818 * @val: the value write 819 * 820 * Write a 32-bit value to the given address in the SEEPROM/VPD. The address 821 * must be four-byte aligned. Returns 0 on success, a negative erro number 822 * on failure. 823 */ 824 static inline int t4_os_pci_write_seeprom(adapter_t *adapter, 825 int addr, u32 val) 826 { 827 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 828 int ret; 829 830 ret = t4_seeprom_write(adapter, addr, val); 831 832 return ret >= 0 ? 0 : ret; 833 } 834 835 static inline int t4_os_pci_set_vpd_size(struct adapter *adapter, size_t len) 836 { 837 return 0; 838 } 839 840 static inline unsigned int t4_use_ldst(struct adapter *adap) 841 { 842 return (adap->flags & FW_OK); 843 } 844 #define t4_os_alloc(_size) kmem_alloc(_size, KM_SLEEP) 845 846 static inline void t4_db_full(struct adapter *adap) {} 847 static inline void t4_db_dropped(struct adapter *adap) {} 848 849 /* t4_nexus.c */ 850 int t4_os_find_pci_capability(struct adapter *sc, int cap); 851 void t4_os_portmod_changed(const struct adapter *sc, int idx); 852 int adapter_full_init(struct adapter *sc); 853 int adapter_full_uninit(struct adapter *sc); 854 int port_full_init(struct port_info *pi); 855 int port_full_uninit(struct port_info *pi); 856 void enable_port_queues(struct port_info *pi); 857 void disable_port_queues(struct port_info *pi); 858 int t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h); 859 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 860 void t4_iterate(void (*func)(int, void *), void *arg); 861 862 /* t4_sge.c */ 863 void t4_sge_init(struct adapter *sc); 864 int t4_setup_adapter_queues(struct adapter *sc); 865 int t4_teardown_adapter_queues(struct adapter *sc); 866 int t4_setup_port_queues(struct port_info *pi); 867 int t4_teardown_port_queues(struct port_info *pi); 868 uint_t t4_intr_all(caddr_t arg1, caddr_t arg2); 869 uint_t t4_intr(caddr_t arg1, caddr_t arg2); 870 uint_t t4_intr_err(caddr_t arg1, caddr_t arg2); 871 int t4_mgmt_tx(struct adapter *sc, mblk_t *m); 872 void memwin_info(struct adapter *, int, uint32_t *, uint32_t *); 873 uint32_t position_memwin(struct adapter *, int, uint32_t); 874 875 mblk_t *t4_eth_tx(void *, mblk_t *); 876 mblk_t *t4_mc_tx(void *arg, mblk_t *m); 877 mblk_t *t4_ring_rx(struct sge_rxq *rxq, int poll_bytes); 878 int t4_alloc_tx_maps(struct adapter *sc, struct tx_maps *txmaps, int count, 879 int flags); 880 881 /* t4_mac.c */ 882 void t4_mc_init(struct port_info *pi); 883 void t4_mc_cb_init(struct port_info *); 884 void t4_os_link_changed(struct adapter *sc, int idx, int link_stat); 885 void t4_mac_rx(struct port_info *pi, struct sge_rxq *rxq, mblk_t *m); 886 void t4_mac_tx_update(struct port_info *pi, struct sge_txq *txq); 887 int t4_addmac(void *arg, const uint8_t *ucaddr); 888 889 /* t4_ioctl.c */ 890 int t4_ioctl(struct adapter *sc, int cmd, void *data, int mode); 891 892 struct l2t_data *t4_init_l2t(struct adapter *sc); 893 int begin_synchronized_op(struct port_info *pi, int hold, int waitok); 894 void end_synchronized_op(struct port_info *pi, int held); 895 #endif /* __CXGBE_ADAPTER_H */ 896