1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4 support code. 14 * 15 * Copyright (C) 2011-2013 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23 #ifndef __CXGBE_ADAPTER_H 24 #define __CXGBE_ADAPTER_H 25 26 #include <sys/ddi.h> 27 #include <sys/mac_provider.h> 28 #include <sys/ethernet.h> 29 #include <sys/queue.h> 30 #include <sys/containerof.h> 31 #include <sys/ddi_ufm.h> 32 33 #include "offload.h" 34 #include "firmware/t4fw_interface.h" 35 #include "shared.h" 36 37 struct adapter; 38 typedef struct adapter adapter_t; 39 40 enum { 41 FW_IQ_QSIZE = 256, 42 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 43 44 RX_IQ_QSIZE = 1024, 45 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 46 47 EQ_ESIZE = 64, /* All egres queues use this entry size */ 48 49 RX_FL_ESIZE = 64, /* 8 64bit addresses */ 50 51 FL_BUF_SIZES = 4, 52 53 CTRL_EQ_QSIZE = 128, 54 55 TX_EQ_QSIZE = 1024, 56 TX_SGL_SEGS = 36, 57 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 58 }; 59 60 enum { 61 /* adapter flags */ 62 FULL_INIT_DONE = (1 << 0), 63 FW_OK = (1 << 1), 64 INTR_FWD = (1 << 2), 65 INTR_ALLOCATED = (1 << 3), 66 MASTER_PF = (1 << 4), 67 68 CXGBE_BUSY = (1 << 9), 69 70 /* port flags */ 71 DOOMED = (1 << 0), 72 PORT_INIT_DONE = (1 << 1), 73 }; 74 75 enum { 76 /* Features */ 77 CXGBE_HW_LSO = (1 << 0), 78 CXGBE_HW_CSUM = (1 << 1), 79 }; 80 81 enum { 82 UDBS_SEG_SHIFT = 7, /* log2(UDBS_SEG_SIZE) */ 83 UDBS_DB_OFFSET = 8, /* offset of the 4B doorbell in a segment */ 84 UDBS_WR_OFFSET = 64, /* offset of the work request in a segment */ 85 }; 86 87 #define IS_DOOMED(pi) (pi->flags & DOOMED) 88 #define SET_DOOMED(pi) do { pi->flags |= DOOMED; } while (0) 89 #define IS_BUSY(sc) (sc->flags & CXGBE_BUSY) 90 #define SET_BUSY(sc) do { sc->flags |= CXGBE_BUSY; } while (0) 91 #define CLR_BUSY(sc) do { sc->flags &= ~CXGBE_BUSY; } while (0) 92 93 struct port_info { 94 PORT_INFO_HDR; 95 96 kmutex_t lock; 97 struct adapter *adapter; 98 99 unsigned int flags; 100 101 uint16_t viid; 102 int16_t xact_addr_filt; /* index of exact MAC address filter */ 103 uint16_t rss_size; /* size of VI's RSS table slice */ 104 uint16_t ntxq; /* # of tx queues */ 105 uint16_t first_txq; /* index of first tx queue */ 106 uint16_t nrxq; /* # of rx queues */ 107 uint16_t first_rxq; /* index of first rx queue */ 108 uint8_t lport; /* associated offload logical port */ 109 int8_t mdio_addr; 110 uint8_t port_type; 111 uint8_t mod_type; 112 uint8_t port_id; 113 uint8_t tx_chan; 114 uint8_t rx_chan; 115 uint8_t rx_cchan; 116 uint8_t instance; /* Associated adapter instance */ 117 uint8_t child_inst; /* Associated child instance */ 118 uint8_t tmr_idx; 119 int8_t pktc_idx; 120 struct link_config link_cfg; 121 struct port_stats stats; 122 uint32_t features; 123 uint8_t macaddr_cnt; 124 u8 rss_mode; 125 u16 viid_mirror; 126 kstat_t *ksp_config; 127 kstat_t *ksp_info; 128 kstat_t *ksp_fec; 129 130 u8 vivld; 131 u8 vin; 132 u8 smt_idx; 133 134 u8 vivld_mirror; 135 u8 vin_mirror; 136 u8 smt_idx_mirror; 137 }; 138 139 struct fl_sdesc { 140 struct rxbuf *rxb; 141 }; 142 143 struct tx_desc { 144 __be64 flit[8]; 145 }; 146 147 /* DMA maps used for tx */ 148 struct tx_maps { 149 ddi_dma_handle_t *map; 150 uint32_t map_total; /* # of DMA maps */ 151 uint32_t map_pidx; /* next map to be used */ 152 uint32_t map_cidx; /* reclaimed up to this index */ 153 uint32_t map_avail; /* # of available maps */ 154 }; 155 156 struct tx_sdesc { 157 mblk_t *m; 158 uint32_t txb_used; /* # of bytes of tx copy buffer used */ 159 uint16_t hdls_used; /* # of dma handles used */ 160 uint16_t desc_used; /* # of hardware descriptors used */ 161 }; 162 163 enum { 164 /* iq flags */ 165 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 166 IQ_INTR = (1 << 1), /* iq takes direct interrupt */ 167 IQ_HAS_FL = (1 << 2), /* iq has fl */ 168 169 /* iq state */ 170 IQS_DISABLED = 0, 171 IQS_BUSY = 1, 172 IQS_IDLE = 2, 173 }; 174 175 /* 176 * Ingress Queue: T4 is producer, driver is consumer. 177 */ 178 struct sge_iq { 179 unsigned int flags; 180 ddi_dma_handle_t dhdl; 181 ddi_acc_handle_t ahdl; 182 183 volatile uint_t state; 184 __be64 *desc; /* KVA of descriptor ring */ 185 uint64_t ba; /* bus address of descriptor ring */ 186 const __be64 *cdesc; /* current descriptor */ 187 struct adapter *adapter; /* associated adapter */ 188 uint8_t gen; /* generation bit */ 189 uint8_t intr_params; /* interrupt holdoff parameters */ 190 int8_t intr_pktc_idx; /* packet count threshold index */ 191 uint8_t intr_next; /* holdoff for next interrupt */ 192 uint8_t esize; /* size (bytes) of each entry in the queue */ 193 uint16_t qsize; /* size (# of entries) of the queue */ 194 uint16_t cidx; /* consumer index */ 195 uint16_t pending; /* # of descs processed since last doorbell */ 196 uint16_t cntxt_id; /* SGE context id for the iq */ 197 uint16_t abs_id; /* absolute SGE id for the iq */ 198 kmutex_t lock; /* Rx access lock */ 199 uint8_t polling; 200 201 STAILQ_ENTRY(sge_iq) link; 202 }; 203 204 enum { 205 EQ_CTRL = 1, 206 EQ_ETH = 2, 207 208 /* eq flags */ 209 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 210 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 211 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 212 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 213 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 214 EQ_MTX = (1 << 7), /* mutex has been initialized */ 215 EQ_STARTED = (1 << 8), /* started */ 216 }; 217 218 /* Listed in order of preference. Update t4_sysctls too if you change these */ 219 enum {DOORBELL_UDB=0x1 , DOORBELL_WCWR=0x2, DOORBELL_UDBWC=0x4, DOORBELL_KDB=0x8}; 220 221 /* 222 * Egress Queue: driver is producer, T4 is consumer. 223 * 224 * Note: A free list is an egress queue (driver produces the buffers and T4 225 * consumes them) but it's special enough to have its own struct (see sge_fl). 226 */ 227 struct sge_eq { 228 ddi_dma_handle_t desc_dhdl; 229 ddi_acc_handle_t desc_ahdl; 230 unsigned int flags; 231 kmutex_t lock; 232 233 struct tx_desc *desc; /* KVA of descriptor ring */ 234 uint64_t ba; /* bus address of descriptor ring */ 235 struct sge_qstat *spg; /* status page, for convenience */ 236 int doorbells; 237 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 238 u_int udb_qid; /* relative qid within the doorbell page */ 239 uint16_t cap; /* max # of desc, for convenience */ 240 uint16_t avail; /* available descriptors, for convenience */ 241 uint16_t qsize; /* size (# of entries) of the queue */ 242 uint16_t cidx; /* consumer idx (desc idx) */ 243 uint16_t pidx; /* producer idx (desc idx) */ 244 uint16_t pending; /* # of descriptors used since last doorbell */ 245 uint16_t iqid; /* iq that gets egr_update for the eq */ 246 uint8_t tx_chan; /* tx channel used by the eq */ 247 uint32_t cntxt_id; /* SGE context id for the eq */ 248 }; 249 250 enum { 251 /* fl flags */ 252 FL_MTX = (1 << 0), /* mutex has been initialized */ 253 FL_STARVING = (1 << 1), /* on the list of starving fl's */ 254 FL_DOOMED = (1 << 2), /* about to be destroyed */ 255 }; 256 257 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 258 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 259 260 struct sge_fl { 261 unsigned int flags; 262 kmutex_t lock; 263 ddi_dma_handle_t dhdl; 264 ddi_acc_handle_t ahdl; 265 266 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 267 uint64_t ba; /* bus address of descriptor ring */ 268 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 269 uint32_t cap; /* max # of buffers, for convenience */ 270 uint16_t qsize; /* size (# of entries) of the queue */ 271 uint16_t cntxt_id; /* SGE context id for the freelist */ 272 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 273 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 274 uint32_t needed; /* # of buffers needed to fill up fl. */ 275 uint32_t lowat; /* # of buffers <= this means fl needs help */ 276 uint32_t pending; /* # of bufs allocated since last doorbell */ 277 uint32_t offset; /* current packet within the larger buffer */ 278 uint16_t copy_threshold; /* anything this size or less is copied up */ 279 280 uint64_t copied_up; /* # of frames copied into mblk and handed up */ 281 uint64_t passed_up; /* # of frames wrapped in mblk and handed up */ 282 uint64_t allocb_fail; /* # of mblk allocation failures */ 283 284 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 285 }; 286 287 /* txq: SGE egress queue + miscellaneous items */ 288 struct sge_txq { 289 struct sge_eq eq; /* MUST be first */ 290 291 struct port_info *port; /* the port this txq belongs to */ 292 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 293 mac_ring_handle_t ring_handle; 294 295 /* DMA handles used for tx */ 296 ddi_dma_handle_t *tx_dhdl; 297 uint32_t tx_dhdl_total; /* Total # of handles */ 298 uint32_t tx_dhdl_pidx; /* next handle to be used */ 299 uint32_t tx_dhdl_cidx; /* reclaimed up to this index */ 300 uint32_t tx_dhdl_avail; /* # of available handles */ 301 302 /* Copy buffers for tx */ 303 ddi_dma_handle_t txb_dhdl; 304 ddi_acc_handle_t txb_ahdl; 305 caddr_t txb_va; /* KVA of copy buffers area */ 306 uint64_t txb_ba; /* bus address of copy buffers area */ 307 uint32_t txb_size; /* total size */ 308 uint32_t txb_next; /* offset of next useable area in the buffer */ 309 uint32_t txb_avail; /* # of bytes available */ 310 uint16_t copy_threshold; /* anything this size or less is copied up */ 311 312 uint64_t txpkts; /* # of ethernet packets */ 313 uint64_t txbytes; /* # of ethernet bytes */ 314 kstat_t *ksp; 315 316 /* stats for common events first */ 317 318 uint64_t txcsum; /* # of times hardware assisted with checksum */ 319 uint64_t tso_wrs; /* # of IPv4 TSO work requests */ 320 uint64_t imm_wrs; /* # of work requests with immediate data */ 321 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 322 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 323 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 324 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 325 uint64_t txb_used; /* # of tx copy buffers used (64 byte each) */ 326 uint64_t hdl_used; /* # of DMA handles used */ 327 328 /* stats for not-that-common events */ 329 330 uint32_t txb_full; /* txb ran out of space */ 331 uint32_t dma_hdl_failed; /* couldn't obtain DMA handle */ 332 uint32_t dma_map_failed; /* couldn't obtain DMA mapping */ 333 uint32_t qfull; /* out of hardware descriptors */ 334 uint32_t qflush; /* # of SGE_EGR_UPDATE notifications for txq */ 335 uint32_t pullup_early; /* # of pullups before starting frame's SGL */ 336 uint32_t pullup_late; /* # of pullups while building frame's SGL */ 337 uint32_t pullup_failed; /* # of failed pullups */ 338 uint32_t csum_failed; /* # of csum reqs we failed to fulfill */ 339 }; 340 341 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 342 struct sge_rxq { 343 struct sge_iq iq; /* MUST be first */ 344 struct sge_fl fl; 345 346 struct port_info *port; /* the port this rxq belongs to */ 347 kstat_t *ksp; 348 349 mac_ring_handle_t ring_handle; 350 uint64_t ring_gen_num; 351 352 /* stats for common events first */ 353 354 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 355 uint64_t rxpkts; /* # of ethernet packets */ 356 uint64_t rxbytes; /* # of ethernet bytes */ 357 358 /* stats for not-that-common events */ 359 360 uint32_t nomem; /* mblk allocation during rx failed */ 361 }; 362 363 struct sge { 364 int fl_starve_threshold; 365 int s_qpp; 366 367 int nrxq; /* total rx queues (all ports and the rest) */ 368 int ntxq; /* total tx queues (all ports and the rest) */ 369 int niq; /* total ingress queues */ 370 int neq; /* total egress queues */ 371 int stat_len; /* length of status page at ring end */ 372 int pktshift; /* padding between CPL & packet data */ 373 int fl_align; /* response queue message alignment */ 374 375 struct sge_iq fwq; /* Firmware event queue */ 376 struct sge_txq *txq; /* NIC tx queues */ 377 struct sge_rxq *rxq; /* NIC rx queues */ 378 379 int iq_start; /* iq context id map start index */ 380 int eq_start; /* eq context id map start index */ 381 int iqmap_sz; /* size of iq context id map */ 382 int eqmap_sz; /* size of eq context id map */ 383 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 384 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 385 386 /* Device access and DMA attributes for all the descriptor rings */ 387 ddi_device_acc_attr_t acc_attr_desc; 388 ddi_dma_attr_t dma_attr_desc; 389 390 /* Device access and DMA attributes for tx buffers */ 391 ddi_device_acc_attr_t acc_attr_tx; 392 ddi_dma_attr_t dma_attr_tx; 393 394 /* Device access and DMA attributes for rx buffers are in rxb_params */ 395 kmem_cache_t *rxbuf_cache; 396 struct rxbuf_cache_params rxb_params; 397 }; 398 399 struct driver_properties { 400 /* There is a driver.conf variable for each of these */ 401 int max_ntxq_10g; 402 int max_nrxq_10g; 403 int max_ntxq_1g; 404 int max_nrxq_1g; 405 int intr_types; 406 int tmr_idx_10g; 407 int pktc_idx_10g; 408 int tmr_idx_1g; 409 int pktc_idx_1g; 410 int qsize_txq; 411 int qsize_rxq; 412 413 int timer_val[SGE_NTIMERS]; 414 int counter_val[SGE_NCOUNTERS]; 415 416 int wc; 417 418 int multi_rings; 419 int t4_fw_install; 420 }; 421 422 struct rss_header; 423 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 424 mblk_t *); 425 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 426 427 struct t4_mbox_list { 428 STAILQ_ENTRY(t4_mbox_list) link; 429 }; 430 431 struct adapter { 432 SLIST_ENTRY(adapter) link; 433 dev_info_t *dip; 434 dev_t dev; 435 436 unsigned int pf; 437 unsigned int mbox; 438 439 unsigned int vpd_busy; 440 unsigned int vpd_flag; 441 442 u32 t4_bar0; 443 444 uint_t open; /* character device is open */ 445 446 /* PCI config space access handle */ 447 ddi_acc_handle_t pci_regh; 448 449 /* MMIO register access handle */ 450 ddi_acc_handle_t regh; 451 caddr_t regp; 452 /* BAR1 register access handle */ 453 ddi_acc_handle_t reg1h; 454 caddr_t reg1p; 455 456 /* Interrupt information */ 457 int intr_type; 458 int intr_count; 459 int intr_cap; 460 uint_t intr_pri; 461 ddi_intr_handle_t *intr_handle; 462 463 struct driver_properties props; 464 kstat_t *ksp; 465 kstat_t *ksp_stat; 466 467 struct sge sge; 468 469 struct port_info *port[MAX_NPORTS]; 470 ddi_taskq_t *tq[NCHAN]; 471 uint8_t chan_map[NCHAN]; 472 uint32_t filter_mode; 473 474 struct l2t_data *l2t; /* L2 table */ 475 struct tid_info tids; 476 477 int doorbells; 478 int registered_device_map; 479 int open_device_map; 480 int flags; 481 482 unsigned int cfcsum; 483 struct adapter_params params; 484 struct t4_virt_res vres; 485 486 uint16_t linkcaps; 487 uint16_t niccaps; 488 uint16_t toecaps; 489 uint16_t rdmacaps; 490 uint16_t iscsicaps; 491 uint16_t fcoecaps; 492 493 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ 494 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 495 496 kmutex_t lock; 497 kcondvar_t cv; 498 499 /* Starving free lists */ 500 kmutex_t sfl_lock; /* same cache-line as sc_lock? but that's ok */ 501 TAILQ_HEAD(, sge_fl) sfl; 502 timeout_id_t sfl_timer; 503 504 /* Sensors */ 505 id_t temp_sensor; 506 id_t volt_sensor; 507 508 ddi_ufm_handle_t *ufm_hdl; 509 510 /* support for single-threading access to adapter mailbox registers */ 511 kmutex_t mbox_lock; 512 STAILQ_HEAD(, t4_mbox_list) mbox_list; 513 }; 514 515 enum { 516 NIC_H = 0, 517 TOM_H, 518 IW_H, 519 ISCSI_H 520 }; 521 522 struct memwin { 523 uint32_t base; 524 uint32_t aperture; 525 }; 526 527 #define ADAPTER_LOCK(sc) mutex_enter(&(sc)->lock) 528 #define ADAPTER_UNLOCK(sc) mutex_exit(&(sc)->lock) 529 #define ADAPTER_LOCK_ASSERT_OWNED(sc) ASSERT(mutex_owned(&(sc)->lock)) 530 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) ASSERT(!mutex_owned(&(sc)->lock)) 531 532 #define PORT_LOCK(pi) mutex_enter(&(pi)->lock) 533 #define PORT_UNLOCK(pi) mutex_exit(&(pi)->lock) 534 #define PORT_LOCK_ASSERT_OWNED(pi) ASSERT(mutex_owned(&(pi)->lock)) 535 #define PORT_LOCK_ASSERT_NOTOWNED(pi) ASSERT(!mutex_owned(&(pi)->lock)) 536 537 #define IQ_LOCK(iq) mutex_enter(&(iq)->lock) 538 #define IQ_UNLOCK(iq) mutex_exit(&(iq)->lock) 539 #define IQ_LOCK_ASSERT_OWNED(iq) ASSERT(mutex_owned(&(iq)->lock)) 540 #define IQ_LOCK_ASSERT_NOTOWNED(iq) ASSERT(!mutex_owned(&(iq)->lock)) 541 542 #define FL_LOCK(fl) mutex_enter(&(fl)->lock) 543 #define FL_UNLOCK(fl) mutex_exit(&(fl)->lock) 544 #define FL_LOCK_ASSERT_OWNED(fl) ASSERT(mutex_owned(&(fl)->lock)) 545 #define FL_LOCK_ASSERT_NOTOWNED(fl) ASSERT(!mutex_owned(&(fl)->lock)) 546 547 #define RXQ_LOCK(rxq) IQ_LOCK(&(rxq)->iq) 548 #define RXQ_UNLOCK(rxq) IQ_UNLOCK(&(rxq)->iq) 549 #define RXQ_LOCK_ASSERT_OWNED(rxq) IQ_LOCK_ASSERT_OWNED(&(rxq)->iq) 550 #define RXQ_LOCK_ASSERT_NOTOWNED(rxq) IQ_LOCK_ASSERT_NOTOWNED(&(rxq)->iq) 551 552 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 553 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 554 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 555 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 556 557 #define EQ_LOCK(eq) mutex_enter(&(eq)->lock) 558 #define EQ_UNLOCK(eq) mutex_exit(&(eq)->lock) 559 #define EQ_LOCK_ASSERT_OWNED(eq) ASSERT(mutex_owned(&(eq)->lock)) 560 #define EQ_LOCK_ASSERT_NOTOWNED(eq) ASSERT(!mutex_owned(&(eq)->lock)) 561 562 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 563 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 564 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 565 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 566 567 #define for_each_txq(pi, iter, txq) \ 568 txq = &pi->adapter->sge.txq[pi->first_txq]; \ 569 for (iter = 0; iter < pi->ntxq; ++iter, ++txq) 570 #define for_each_rxq(pi, iter, rxq) \ 571 rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \ 572 for (iter = 0; iter < pi->nrxq; ++iter, ++rxq) 573 #define for_each_ofld_txq(pi, iter, ofld_txq) \ 574 ofld_txq = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq]; \ 575 for (iter = 0; iter < pi->nofldtxq; ++iter, ++ofld_txq) 576 #define for_each_ofld_rxq(pi, iter, ofld_rxq) \ 577 ofld_rxq = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq]; \ 578 for (iter = 0; iter < pi->nofldrxq; ++iter, ++ofld_rxq) 579 580 #define NFIQ(sc) ((sc)->intr_count > 1 ? (sc)->intr_count - 1 : 1) 581 582 /* One for errors, one for firmware events */ 583 #define T4_EXTRA_INTR 2 584 585 typedef kmutex_t t4_os_lock_t; 586 587 static inline void t4_os_lock(t4_os_lock_t *lock) 588 { 589 mutex_enter(lock); 590 } 591 592 static inline void t4_os_unlock(t4_os_lock_t *lock) 593 { 594 mutex_exit(lock); 595 } 596 597 static inline void t4_mbox_list_add(struct adapter *adap, 598 struct t4_mbox_list *entry) 599 { 600 t4_os_lock(&adap->mbox_lock); 601 STAILQ_INSERT_TAIL(&adap->mbox_list, entry, link); 602 t4_os_unlock(&adap->mbox_lock); 603 } 604 605 static inline void t4_mbox_list_del(struct adapter *adap, 606 struct t4_mbox_list *entry) 607 { 608 t4_os_lock(&adap->mbox_lock); 609 STAILQ_REMOVE(&adap->mbox_list, entry, t4_mbox_list, link); 610 t4_os_unlock(&adap->mbox_lock); 611 } 612 613 static inline struct t4_mbox_list * 614 t4_mbox_list_first_entry(struct adapter *adap) 615 { 616 return STAILQ_FIRST(&adap->mbox_list); 617 } 618 619 static inline uint32_t 620 t4_read_reg(struct adapter *sc, uint32_t reg) 621 { 622 /* LINTED: E_BAD_PTR_CAST_ALIGN */ 623 return (ddi_get32(sc->regh, (uint32_t *)(sc->regp + reg))); 624 } 625 626 static inline void 627 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 628 { 629 /* LINTED: E_BAD_PTR_CAST_ALIGN */ 630 ddi_put32(sc->regh, (uint32_t *)(sc->regp + reg), val); 631 } 632 633 static inline void 634 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 635 { 636 *val = pci_config_get8(sc->pci_regh, reg); 637 } 638 639 static inline void 640 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 641 { 642 pci_config_put8(sc->pci_regh, reg, val); 643 } 644 645 static inline void 646 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 647 { 648 *val = pci_config_get16(sc->pci_regh, reg); 649 } 650 651 static inline void 652 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 653 { 654 pci_config_put16(sc->pci_regh, reg, val); 655 } 656 657 static inline void 658 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 659 { 660 *val = pci_config_get32(sc->pci_regh, reg); 661 } 662 663 static inline void 664 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 665 { 666 pci_config_put32(sc->pci_regh, reg, val); 667 } 668 669 static inline uint32_t 670 t4_read_reg32(struct adapter *sc, uint32_t reg) 671 { 672 return (ddi_get32(sc->regh, (uint32_t *)(sc->regp + reg))); 673 } 674 675 static inline uint64_t 676 t4_read_reg64(struct adapter *sc, uint32_t reg) 677 { 678 return (ddi_get64(sc->regh, (uint64_t *)(sc->regp + reg))); 679 } 680 681 static inline void 682 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 683 { 684 ddi_put64(sc->regh, (uint64_t *)(sc->regp + reg), val); 685 } 686 687 static inline struct port_info * 688 adap2pinfo(struct adapter *sc, int idx) 689 { 690 return (sc->port[idx]); 691 } 692 693 static inline void 694 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 695 { 696 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHERADDRL); 697 } 698 699 static inline bool 700 is_10G_port(const struct port_info *pi) 701 { 702 return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G) != 0); 703 } 704 705 static inline struct sge_rxq * 706 iq_to_rxq(struct sge_iq *iq) 707 { 708 return (__containerof(iq, struct sge_rxq, iq)); 709 } 710 711 static inline bool 712 is_25G_port(const struct port_info *pi) 713 { 714 return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G) != 0); 715 } 716 717 static inline bool 718 is_40G_port(const struct port_info *pi) 719 { 720 return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G) != 0); 721 } 722 723 static inline bool 724 is_50G_port(const struct port_info *pi) 725 { 726 return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G) != 0); 727 } 728 729 static inline bool 730 is_100G_port(const struct port_info *pi) 731 { 732 return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G) != 0); 733 } 734 735 static inline bool 736 is_10XG_port(const struct port_info *pi) 737 { 738 return (is_10G_port(pi) || is_40G_port(pi) || 739 is_25G_port(pi) || is_50G_port(pi) || 740 is_100G_port(pi)); 741 } 742 743 /** 744 * t4_os_pci_read_seeprom - read four bytes of SEEPROM/VPD contents 745 * @adapter: the adapter 746 * @addr: SEEPROM/VPD Address to read 747 * @valp: where to store the value read 748 * 749 * Read a 32-bit value from the given address in the SEEPROM/VPD. The address 750 * must be four-byte aligned. Returns 0 on success, a negative erro number 751 * on failure. 752 */ 753 static inline int t4_os_pci_read_seeprom(adapter_t *adapter, 754 int addr, u32 *valp) 755 { 756 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 757 int ret; 758 759 ret = t4_seeprom_read(adapter, addr, valp); 760 761 return ret >= 0 ? 0 : ret; 762 } 763 764 /** 765 * t4_os_pci_write_seeprom - write four bytes of SEEPROM/VPD contents 766 * @adapter: the adapter 767 * @addr: SEEPROM/VPD Address to write 768 * @val: the value write 769 * 770 * Write a 32-bit value to the given address in the SEEPROM/VPD. The address 771 * must be four-byte aligned. Returns 0 on success, a negative erro number 772 * on failure. 773 */ 774 static inline int t4_os_pci_write_seeprom(adapter_t *adapter, 775 int addr, u32 val) 776 { 777 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 778 int ret; 779 780 ret = t4_seeprom_write(adapter, addr, val); 781 782 return ret >= 0 ? 0 : ret; 783 } 784 785 static inline int t4_os_pci_set_vpd_size(struct adapter *adapter, size_t len) 786 { 787 return 0; 788 } 789 790 static inline unsigned int t4_use_ldst(struct adapter *adap) 791 { 792 return (adap->flags & FW_OK); 793 } 794 #define t4_os_alloc(_size) kmem_alloc(_size, KM_SLEEP) 795 796 static inline void t4_db_full(struct adapter *adap) {} 797 static inline void t4_db_dropped(struct adapter *adap) {} 798 799 /* t4_nexus.c */ 800 int t4_os_find_pci_capability(struct adapter *sc, int cap); 801 void t4_os_portmod_changed(struct adapter *sc, int idx); 802 int adapter_full_init(struct adapter *sc); 803 int adapter_full_uninit(struct adapter *sc); 804 int port_full_init(struct port_info *pi); 805 int port_full_uninit(struct port_info *pi); 806 void enable_port_queues(struct port_info *pi); 807 void disable_port_queues(struct port_info *pi); 808 int t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h); 809 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 810 void t4_iterate(void (*func)(int, void *), void *arg); 811 812 /* t4_sge.c */ 813 void t4_sge_init(struct adapter *sc); 814 int t4_setup_adapter_queues(struct adapter *sc); 815 int t4_teardown_adapter_queues(struct adapter *sc); 816 int t4_setup_port_queues(struct port_info *pi); 817 int t4_teardown_port_queues(struct port_info *pi); 818 uint_t t4_intr_all(caddr_t arg1, caddr_t arg2); 819 uint_t t4_intr(caddr_t arg1, caddr_t arg2); 820 uint_t t4_intr_err(caddr_t arg1, caddr_t arg2); 821 int t4_mgmt_tx(struct adapter *sc, mblk_t *m); 822 void memwin_info(struct adapter *, int, uint32_t *, uint32_t *); 823 uint32_t position_memwin(struct adapter *, int, uint32_t); 824 825 mblk_t *t4_eth_tx(void *, mblk_t *); 826 mblk_t *t4_mc_tx(void *arg, mblk_t *m); 827 mblk_t *t4_ring_rx(struct sge_rxq *rxq, int poll_bytes); 828 int t4_alloc_tx_maps(struct adapter *sc, struct tx_maps *txmaps, int count, 829 int flags); 830 831 /* t4_mac.c */ 832 void t4_mc_init(struct port_info *pi); 833 void t4_mc_cb_init(struct port_info *); 834 void t4_os_link_changed(struct adapter *sc, int idx, int link_stat); 835 void t4_mac_rx(struct port_info *pi, struct sge_rxq *rxq, mblk_t *m); 836 void t4_mac_tx_update(struct port_info *pi, struct sge_txq *txq); 837 int t4_addmac(void *arg, const uint8_t *ucaddr); 838 839 /* t4_ioctl.c */ 840 int t4_ioctl(struct adapter *sc, int cmd, void *data, int mode); 841 842 struct l2t_data *t4_init_l2t(struct adapter *sc); 843 int begin_synchronized_op(struct port_info *pi, int hold, int waitok); 844 void end_synchronized_op(struct port_info *pi, int held); 845 #endif /* __CXGBE_ADAPTER_H */ 846