1 /* 2 * Chelsio Terminator 4 (T4) Firmware interface header file. 3 * 4 * Copyright (C) 2009-2014 Chelsio Communications. All rights reserved. 5 * 6 * Written by felix marti (felix@chelsio.com) 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 11 * release for licensing terms and conditions. 12 */ 13 14 /* 15 * Copyright 2020 RackTop Systems, Inc. 16 */ 17 18 #ifndef _T4FW_INTERFACE_H_ 19 #define _T4FW_INTERFACE_H_ 20 21 /****************************************************************************** 22 * R E T U R N V A L U E S 23 ********************************/ 24 25 enum fw_retval { 26 FW_SUCCESS = 0, /* completed sucessfully */ 27 FW_EPERM = 1, /* operation not permitted */ 28 FW_ENOENT = 2, /* no such file or directory */ 29 FW_EIO = 5, /* input/output error; hw bad */ 30 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 31 FW_EAGAIN = 11, /* try again */ 32 FW_ENOMEM = 12, /* out of memory */ 33 FW_EFAULT = 14, /* bad address; fw bad */ 34 FW_EBUSY = 16, /* resource busy */ 35 FW_EEXIST = 17, /* file exists */ 36 FW_ENODEV = 19, /* no such device */ 37 FW_EINVAL = 22, /* invalid argument */ 38 FW_ENOSPC = 28, /* no space left on device */ 39 FW_ENOSYS = 38, /* functionality not implemented */ 40 FW_ENODATA = 61, /* no data available */ 41 FW_EPROTO = 71, /* protocol error */ 42 FW_EADDRINUSE = 98, /* address already in use */ 43 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 44 FW_ENETDOWN = 100, /* network is down */ 45 FW_ENETUNREACH = 101, /* network is unreachable */ 46 FW_ENOBUFS = 105, /* no buffer space available */ 47 FW_ETIMEDOUT = 110, /* timeout */ 48 FW_EINPROGRESS = 115, /* fw internal */ 49 FW_SCSI_ABORT_REQUESTED = 128, /* */ 50 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 51 FW_SCSI_ABORTED = 130, /* */ 52 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 53 FW_ERR_LINK_DOWN = 132, /* */ 54 FW_RDEV_NOT_READY = 133, /* */ 55 FW_ERR_RDEV_LOST = 134, /* */ 56 FW_ERR_RDEV_LOGO = 135, /* */ 57 FW_FCOE_NO_XCHG = 136, /* */ 58 FW_SCSI_RSP_ERR = 137, /* */ 59 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 60 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 61 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 62 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 63 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 64 }; 65 66 /****************************************************************************** 67 * M E M O R Y T Y P E s 68 ******************************/ 69 70 enum fw_memtype { 71 FW_MEMTYPE_EDC0 = 0x0, 72 FW_MEMTYPE_EDC1 = 0x1, 73 FW_MEMTYPE_EXTMEM = 0x2, 74 FW_MEMTYPE_FLASH = 0x4, 75 FW_MEMTYPE_INTERNAL = 0x5, 76 FW_MEMTYPE_EXTMEM1 = 0x6, 77 FW_MEMTYPE_HMA = 0x7, 78 }; 79 80 /****************************************************************************** 81 * W O R K R E Q U E S T s 82 ********************************/ 83 84 enum fw_wr_opcodes { 85 FW_FRAG_WR = 0x1d, 86 FW_FILTER_WR = 0x02, 87 FW_ULPTX_WR = 0x04, 88 FW_TP_WR = 0x05, 89 FW_ETH_TX_PKT_WR = 0x08, 90 FW_ETH_TX_PKT2_WR = 0x44, 91 FW_ETH_TX_PKTS_WR = 0x09, 92 FW_ETH_TX_PKTS2_WR = 0x78, 93 FW_ETH_TX_EO_WR = 0x1c, 94 FW_EQ_FLUSH_WR = 0x1b, 95 FW_OFLD_CONNECTION_WR = 0x2f, 96 FW_FLOWC_WR = 0x0a, 97 FW_OFLD_TX_DATA_WR = 0x0b, 98 FW_CMD_WR = 0x10, 99 FW_ETH_TX_PKT_VM_WR = 0x11, 100 FW_ETH_TX_PKTS_VM_WR = 0x12, 101 FW_RI_RES_WR = 0x0c, 102 FW_RI_RDMA_WRITE_WR = 0x14, 103 FW_RI_SEND_WR = 0x15, 104 FW_RI_RDMA_READ_WR = 0x16, 105 FW_RI_RECV_WR = 0x17, 106 FW_RI_BIND_MW_WR = 0x18, 107 FW_RI_FR_NSMR_WR = 0x19, 108 FW_RI_FR_NSMR_TPTE_WR = 0x20, 109 FW_RI_RDMA_WRITE_CMPL_WR = 0x21, 110 FW_RI_INV_LSTAG_WR = 0x1a, 111 FW_RI_SEND_IMMEDIATE_WR = 0x15, 112 FW_RI_ATOMIC_WR = 0x16, 113 FW_RI_WR = 0x0d, 114 FW_CHNET_IFCONF_WR = 0x6b, 115 FW_RDEV_WR = 0x38, 116 FW_FOISCSI_NODE_WR = 0x60, 117 FW_FOISCSI_CTRL_WR = 0x6a, 118 FW_FOISCSI_CHAP_WR = 0x6c, 119 FW_FCOE_ELS_CT_WR = 0x30, 120 FW_SCSI_WRITE_WR = 0x31, 121 FW_SCSI_READ_WR = 0x32, 122 FW_SCSI_CMD_WR = 0x33, 123 FW_SCSI_ABRT_CLS_WR = 0x34, 124 FW_SCSI_TGT_ACC_WR = 0x35, 125 FW_SCSI_TGT_XMIT_WR = 0x36, 126 FW_SCSI_TGT_RSP_WR = 0x37, 127 FW_POFCOE_TCB_WR = 0x42, 128 FW_POFCOE_ULPTX_WR = 0x43, 129 FW_ISCSI_TX_DATA_WR = 0x45, 130 FW_PTP_TX_PKT_WR = 0x46, 131 FW_TLSTX_DATA_WR = 0x68, 132 FW_TLS_KEYCTX_TX_WR = 0x69, 133 FW_CRYPTO_LOOKASIDE_WR = 0x6d, 134 FW_COiSCSI_TGT_WR = 0x70, 135 FW_COiSCSI_TGT_CONN_WR = 0x71, 136 FW_COiSCSI_TGT_XMIT_WR = 0x72, 137 FW_ISNS_WR = 0x75, 138 FW_ISNS_XMIT_WR = 0x76, 139 FW_FILTER2_WR = 0x77, 140 FW_LASTC2E_WR = 0x80 141 }; 142 143 /* 144 * Generic work request header flit0 145 */ 146 struct fw_wr_hdr { 147 __be32 hi; 148 __be32 lo; 149 }; 150 151 /* work request opcode (hi) 152 */ 153 #define S_FW_WR_OP 24 154 #define M_FW_WR_OP 0xff 155 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 156 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 157 158 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 159 */ 160 #define S_FW_WR_ATOMIC 23 161 #define M_FW_WR_ATOMIC 0x1 162 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 163 #define G_FW_WR_ATOMIC(x) \ 164 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 165 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 166 167 /* flush flag (hi) - firmware flushes flushable work request buffered 168 * in the flow context. 169 */ 170 #define S_FW_WR_FLUSH 22 171 #define M_FW_WR_FLUSH 0x1 172 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 173 #define G_FW_WR_FLUSH(x) \ 174 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 175 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 176 177 /* completion flag (hi) - firmware generates a cpl_fw6_ack 178 */ 179 #define S_FW_WR_COMPL 21 180 #define M_FW_WR_COMPL 0x1 181 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 182 #define G_FW_WR_COMPL(x) \ 183 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 184 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 185 186 187 /* work request immediate data lengh (hi) 188 */ 189 #define S_FW_WR_IMMDLEN 0 190 #define M_FW_WR_IMMDLEN 0xff 191 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 192 #define G_FW_WR_IMMDLEN(x) \ 193 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 194 195 /* egress queue status update to associated ingress queue entry (lo) 196 */ 197 #define S_FW_WR_EQUIQ 31 198 #define M_FW_WR_EQUIQ 0x1 199 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 200 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 201 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 202 203 /* egress queue status update to egress queue status entry (lo) 204 */ 205 #define S_FW_WR_EQUEQ 30 206 #define M_FW_WR_EQUEQ 0x1 207 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 208 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 209 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 210 211 /* flow context identifier (lo) 212 */ 213 #define S_FW_WR_FLOWID 8 214 #define M_FW_WR_FLOWID 0xfffff 215 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 216 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 217 218 /* length in units of 16-bytes (lo) 219 */ 220 #define S_FW_WR_LEN16 0 221 #define M_FW_WR_LEN16 0xff 222 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 223 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 224 225 struct fw_frag_wr { 226 __be32 op_to_fragoff16; 227 __be32 flowid_len16; 228 __be64 r4; 229 }; 230 231 #define S_FW_FRAG_WR_EOF 15 232 #define M_FW_FRAG_WR_EOF 0x1 233 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 234 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 235 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 236 237 #define S_FW_FRAG_WR_FRAGOFF16 8 238 #define M_FW_FRAG_WR_FRAGOFF16 0x7f 239 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 240 #define G_FW_FRAG_WR_FRAGOFF16(x) \ 241 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 242 243 /* valid filter configurations for compressed tuple 244 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 245 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 246 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 247 * OV - Outer VLAN/VNIC_ID, 248 */ 249 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 250 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 251 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 252 #define HW_TPL_FR_MT_M_OV_P_FC 0x387 253 #define HW_TPL_FR_MT_E_PR_T 0x370 254 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 255 #define HW_TPL_FR_MT_E_T_P_FC 0X353 256 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 257 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 258 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 259 #define HW_TPL_FR_MT_T_OV_P_FC 0X317 260 #define HW_TPL_FR_M_E_PR_FC 0X2E1 261 #define HW_TPL_FR_M_E_T_FC 0X2D1 262 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 263 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 264 #define HW_TPL_FR_M_T_IV_FC 0X299 265 #define HW_TPL_FR_M_T_OV_FC 0X295 266 #define HW_TPL_FR_E_PR_T_P 0X272 267 #define HW_TPL_FR_E_PR_T_FC 0X271 268 #define HW_TPL_FR_E_IV_FC 0X249 269 #define HW_TPL_FR_E_OV_FC 0X245 270 #define HW_TPL_FR_PR_T_IV_FC 0X239 271 #define HW_TPL_FR_PR_T_OV_FC 0X235 272 #define HW_TPL_FR_IV_OV_FC 0X20D 273 #define HW_TPL_MT_M_E_PR 0X1E0 274 #define HW_TPL_MT_M_E_T 0X1D0 275 #define HW_TPL_MT_E_PR_T_FC 0X171 276 #define HW_TPL_MT_E_IV 0X148 277 #define HW_TPL_MT_E_OV 0X144 278 #define HW_TPL_MT_PR_T_IV 0X138 279 #define HW_TPL_MT_PR_T_OV 0X134 280 #define HW_TPL_M_E_PR_P 0X0E2 281 #define HW_TPL_M_E_T_P 0X0D2 282 #define HW_TPL_E_PR_T_P_FC 0X073 283 #define HW_TPL_E_IV_P 0X04A 284 #define HW_TPL_E_OV_P 0X046 285 #define HW_TPL_PR_T_IV_P 0X03A 286 #define HW_TPL_PR_T_OV_P 0X036 287 288 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 289 enum fw_filter_wr_cookie { 290 FW_FILTER_WR_SUCCESS, 291 FW_FILTER_WR_FLT_ADDED, 292 FW_FILTER_WR_FLT_DELETED, 293 FW_FILTER_WR_SMT_TBL_FULL, 294 FW_FILTER_WR_EINVAL, 295 }; 296 297 enum fw_filter_wr_nat_mode { 298 FW_FILTER_WR_NATMODE_NONE = 0, 299 FW_FILTER_WR_NATMODE_DIP , 300 FW_FILTER_WR_NATMODE_DIPDP, 301 FW_FILTER_WR_NATMODE_DIPDPSIP, 302 FW_FILTER_WR_NATMODE_DIPDPSP, 303 FW_FILTER_WR_NATMODE_SIPSP, 304 FW_FILTER_WR_NATMODE_DIPSIPSP, 305 FW_FILTER_WR_NATMODE_FOURTUPLE, 306 }; 307 308 struct fw_filter_wr { 309 __be32 op_pkd; 310 __be32 len16_pkd; 311 __be64 r3; 312 __be32 tid_to_iq; 313 __be32 del_filter_to_l2tix; 314 __be16 ethtype; 315 __be16 ethtypem; 316 __u8 frag_to_ovlan_vldm; 317 __u8 smac_sel; 318 __be16 rx_chan_rx_rpl_iq; 319 __be32 maci_to_matchtypem; 320 __u8 ptcl; 321 __u8 ptclm; 322 __u8 ttyp; 323 __u8 ttypm; 324 __be16 ivlan; 325 __be16 ivlanm; 326 __be16 ovlan; 327 __be16 ovlanm; 328 __u8 lip[16]; 329 __u8 lipm[16]; 330 __u8 fip[16]; 331 __u8 fipm[16]; 332 __be16 lp; 333 __be16 lpm; 334 __be16 fp; 335 __be16 fpm; 336 __be16 r7; 337 __u8 sma[6]; 338 }; 339 340 struct fw_filter2_wr { 341 __be32 op_pkd; 342 __be32 len16_pkd; 343 __be64 r3; 344 __be32 tid_to_iq; 345 __be32 del_filter_to_l2tix; 346 __be16 ethtype; 347 __be16 ethtypem; 348 __u8 frag_to_ovlan_vldm; 349 __u8 smac_sel; 350 __be16 rx_chan_rx_rpl_iq; 351 __be32 maci_to_matchtypem; 352 __u8 ptcl; 353 __u8 ptclm; 354 __u8 ttyp; 355 __u8 ttypm; 356 __be16 ivlan; 357 __be16 ivlanm; 358 __be16 ovlan; 359 __be16 ovlanm; 360 __u8 lip[16]; 361 __u8 lipm[16]; 362 __u8 fip[16]; 363 __u8 fipm[16]; 364 __be16 lp; 365 __be16 lpm; 366 __be16 fp; 367 __be16 fpm; 368 __be16 r7; 369 __u8 sma[6]; 370 __be16 r8; 371 __u8 filter_type_swapmac; 372 __u8 natmode_to_ulp_type; 373 __be16 newlport; 374 __be16 newfport; 375 __u8 newlip[16]; 376 __u8 newfip[16]; 377 __be32 natseqcheck; 378 __be32 r9; 379 __be64 r10; 380 __be64 r11; 381 __be64 r12; 382 __be64 r13; 383 }; 384 385 #define S_FW_FILTER_WR_TID 12 386 #define M_FW_FILTER_WR_TID 0xfffff 387 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 388 #define G_FW_FILTER_WR_TID(x) \ 389 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 390 391 #define S_FW_FILTER_WR_RQTYPE 11 392 #define M_FW_FILTER_WR_RQTYPE 0x1 393 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 394 #define G_FW_FILTER_WR_RQTYPE(x) \ 395 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 396 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 397 398 #define S_FW_FILTER_WR_NOREPLY 10 399 #define M_FW_FILTER_WR_NOREPLY 0x1 400 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 401 #define G_FW_FILTER_WR_NOREPLY(x) \ 402 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 403 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 404 405 #define S_FW_FILTER_WR_IQ 0 406 #define M_FW_FILTER_WR_IQ 0x3ff 407 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 408 #define G_FW_FILTER_WR_IQ(x) \ 409 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 410 411 #define S_FW_FILTER_WR_DEL_FILTER 31 412 #define M_FW_FILTER_WR_DEL_FILTER 0x1 413 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 414 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 415 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 416 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 417 418 #define S_FW_FILTER2_WR_DROP_ENCAP 30 419 #define M_FW_FILTER2_WR_DROP_ENCAP 0x1 420 #define V_FW_FILTER2_WR_DROP_ENCAP(x) ((x) << S_FW_FILTER2_WR_DROP_ENCAP) 421 #define G_FW_FILTER2_WR_DROP_ENCAP(x) \ 422 (((x) >> S_FW_FILTER2_WR_DROP_ENCAP) & M_FW_FILTER2_WR_DROP_ENCAP) 423 #define F_FW_FILTER2_WR_DROP_ENCAP V_FW_FILTER2_WR_DROP_ENCAP(1U) 424 425 #define S_FW_FILTER2_WR_TX_LOOP 29 426 #define M_FW_FILTER2_WR_TX_LOOP 0x1 427 #define V_FW_FILTER2_WR_TX_LOOP(x) ((x) << S_FW_FILTER2_WR_TX_LOOP) 428 #define G_FW_FILTER2_WR_TX_LOOP(x) \ 429 (((x) >> S_FW_FILTER2_WR_TX_LOOP) & M_FW_FILTER2_WR_TX_LOOP) 430 #define F_FW_FILTER2_WR_TX_LOOP V_FW_FILTER2_WR_TX_LOOP(1U) 431 432 #define S_FW_FILTER_WR_RPTTID 25 433 #define M_FW_FILTER_WR_RPTTID 0x1 434 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 435 #define G_FW_FILTER_WR_RPTTID(x) \ 436 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 437 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 438 439 #define S_FW_FILTER_WR_DROP 24 440 #define M_FW_FILTER_WR_DROP 0x1 441 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 442 #define G_FW_FILTER_WR_DROP(x) \ 443 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 444 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 445 446 #define S_FW_FILTER_WR_DIRSTEER 23 447 #define M_FW_FILTER_WR_DIRSTEER 0x1 448 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 449 #define G_FW_FILTER_WR_DIRSTEER(x) \ 450 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 451 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 452 453 #define S_FW_FILTER_WR_MASKHASH 22 454 #define M_FW_FILTER_WR_MASKHASH 0x1 455 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 456 #define G_FW_FILTER_WR_MASKHASH(x) \ 457 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 458 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 459 460 #define S_FW_FILTER_WR_DIRSTEERHASH 21 461 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 462 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 463 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 464 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 465 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 466 467 #define S_FW_FILTER_WR_LPBK 20 468 #define M_FW_FILTER_WR_LPBK 0x1 469 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 470 #define G_FW_FILTER_WR_LPBK(x) \ 471 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 472 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 473 474 #define S_FW_FILTER_WR_DMAC 19 475 #define M_FW_FILTER_WR_DMAC 0x1 476 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 477 #define G_FW_FILTER_WR_DMAC(x) \ 478 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 479 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 480 481 #define S_FW_FILTER_WR_SMAC 18 482 #define M_FW_FILTER_WR_SMAC 0x1 483 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 484 #define G_FW_FILTER_WR_SMAC(x) \ 485 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 486 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 487 488 #define S_FW_FILTER_WR_INSVLAN 17 489 #define M_FW_FILTER_WR_INSVLAN 0x1 490 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 491 #define G_FW_FILTER_WR_INSVLAN(x) \ 492 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 493 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 494 495 #define S_FW_FILTER_WR_RMVLAN 16 496 #define M_FW_FILTER_WR_RMVLAN 0x1 497 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 498 #define G_FW_FILTER_WR_RMVLAN(x) \ 499 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 500 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 501 502 #define S_FW_FILTER_WR_HITCNTS 15 503 #define M_FW_FILTER_WR_HITCNTS 0x1 504 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 505 #define G_FW_FILTER_WR_HITCNTS(x) \ 506 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 507 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 508 509 #define S_FW_FILTER_WR_TXCHAN 13 510 #define M_FW_FILTER_WR_TXCHAN 0x3 511 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 512 #define G_FW_FILTER_WR_TXCHAN(x) \ 513 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 514 515 #define S_FW_FILTER_WR_PRIO 12 516 #define M_FW_FILTER_WR_PRIO 0x1 517 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 518 #define G_FW_FILTER_WR_PRIO(x) \ 519 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 520 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 521 522 #define S_FW_FILTER_WR_L2TIX 0 523 #define M_FW_FILTER_WR_L2TIX 0xfff 524 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 525 #define G_FW_FILTER_WR_L2TIX(x) \ 526 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 527 528 #define S_FW_FILTER_WR_FRAG 7 529 #define M_FW_FILTER_WR_FRAG 0x1 530 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 531 #define G_FW_FILTER_WR_FRAG(x) \ 532 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 533 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 534 535 #define S_FW_FILTER_WR_FRAGM 6 536 #define M_FW_FILTER_WR_FRAGM 0x1 537 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 538 #define G_FW_FILTER_WR_FRAGM(x) \ 539 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 540 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 541 542 #define S_FW_FILTER_WR_IVLAN_VLD 5 543 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 544 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 545 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 546 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 547 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 548 549 #define S_FW_FILTER_WR_OVLAN_VLD 4 550 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 551 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 552 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 553 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 554 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 555 556 #define S_FW_FILTER_WR_IVLAN_VLDM 3 557 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 558 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 559 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 560 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 561 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 562 563 #define S_FW_FILTER_WR_OVLAN_VLDM 2 564 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 565 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 566 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 567 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 568 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 569 570 #define S_FW_FILTER_WR_RX_CHAN 15 571 #define M_FW_FILTER_WR_RX_CHAN 0x1 572 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 573 #define G_FW_FILTER_WR_RX_CHAN(x) \ 574 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 575 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 576 577 #define S_FW_FILTER_WR_RX_RPL_IQ 0 578 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 579 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 580 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 581 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 582 583 #define S_FW_FILTER2_WR_FILTER_TYPE 1 584 #define M_FW_FILTER2_WR_FILTER_TYPE 0x1 585 #define V_FW_FILTER2_WR_FILTER_TYPE(x) ((x) << S_FW_FILTER2_WR_FILTER_TYPE) 586 #define G_FW_FILTER2_WR_FILTER_TYPE(x) \ 587 (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE) 588 #define F_FW_FILTER2_WR_FILTER_TYPE V_FW_FILTER2_WR_FILTER_TYPE(1U) 589 590 #define S_FW_FILTER2_WR_SWAPMAC 0 591 #define M_FW_FILTER2_WR_SWAPMAC 0x1 592 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC) 593 #define G_FW_FILTER2_WR_SWAPMAC(x) \ 594 (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC) 595 #define F_FW_FILTER2_WR_SWAPMAC V_FW_FILTER2_WR_SWAPMAC(1U) 596 597 #define S_FW_FILTER2_WR_NATMODE 5 598 #define M_FW_FILTER2_WR_NATMODE 0x7 599 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE) 600 #define G_FW_FILTER2_WR_NATMODE(x) \ 601 (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE) 602 603 #define S_FW_FILTER2_WR_NATFLAGCHECK 4 604 #define M_FW_FILTER2_WR_NATFLAGCHECK 0x1 605 #define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK) 606 #define G_FW_FILTER2_WR_NATFLAGCHECK(x) \ 607 (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK) 608 #define F_FW_FILTER2_WR_NATFLAGCHECK V_FW_FILTER2_WR_NATFLAGCHECK(1U) 609 610 #define S_FW_FILTER2_WR_ULP_TYPE 0 611 #define M_FW_FILTER2_WR_ULP_TYPE 0xf 612 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE) 613 #define G_FW_FILTER2_WR_ULP_TYPE(x) \ 614 (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE) 615 616 #define S_FW_FILTER_WR_MACI 23 617 #define M_FW_FILTER_WR_MACI 0x1ff 618 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 619 #define G_FW_FILTER_WR_MACI(x) \ 620 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 621 622 #define S_FW_FILTER_WR_MACIM 14 623 #define M_FW_FILTER_WR_MACIM 0x1ff 624 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 625 #define G_FW_FILTER_WR_MACIM(x) \ 626 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 627 628 #define S_FW_FILTER_WR_FCOE 13 629 #define M_FW_FILTER_WR_FCOE 0x1 630 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 631 #define G_FW_FILTER_WR_FCOE(x) \ 632 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 633 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 634 635 #define S_FW_FILTER_WR_FCOEM 12 636 #define M_FW_FILTER_WR_FCOEM 0x1 637 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 638 #define G_FW_FILTER_WR_FCOEM(x) \ 639 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 640 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 641 642 #define S_FW_FILTER_WR_PORT 9 643 #define M_FW_FILTER_WR_PORT 0x7 644 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 645 #define G_FW_FILTER_WR_PORT(x) \ 646 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 647 648 #define S_FW_FILTER_WR_PORTM 6 649 #define M_FW_FILTER_WR_PORTM 0x7 650 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 651 #define G_FW_FILTER_WR_PORTM(x) \ 652 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 653 654 #define S_FW_FILTER_WR_MATCHTYPE 3 655 #define M_FW_FILTER_WR_MATCHTYPE 0x7 656 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 657 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 658 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 659 660 #define S_FW_FILTER_WR_MATCHTYPEM 0 661 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 662 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 663 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 664 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 665 666 struct fw_ulptx_wr { 667 __be32 op_to_compl; 668 __be32 flowid_len16; 669 __u64 cookie; 670 }; 671 672 /* flag for packet type - control packet (0), data packet (1) 673 */ 674 #define S_FW_ULPTX_WR_DATA 28 675 #define M_FW_ULPTX_WR_DATA 0x1 676 #define V_FW_ULPTX_WR_DATA(x) ((x) << S_FW_ULPTX_WR_DATA) 677 #define G_FW_ULPTX_WR_DATA(x) \ 678 (((x) >> S_FW_ULPTX_WR_DATA) & M_FW_ULPTX_WR_DATA) 679 #define F_FW_ULPTX_WR_DATA V_FW_ULPTX_WR_DATA(1U) 680 681 struct fw_tp_wr { 682 __be32 op_to_immdlen; 683 __be32 flowid_len16; 684 __u64 cookie; 685 }; 686 687 struct fw_eth_tx_pkt_wr { 688 __be32 op_immdlen; 689 __be32 equiq_to_len16; 690 __be64 r3; 691 }; 692 693 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 694 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 695 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 696 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 697 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 698 699 struct fw_eth_tx_pkt2_wr { 700 __be32 op_immdlen; 701 __be32 equiq_to_len16; 702 __be32 r3; 703 __be32 L4ChkDisable_to_IpHdrLen; 704 }; 705 706 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 707 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 708 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 709 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 710 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 711 712 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 713 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 714 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 715 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 716 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 717 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 718 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 719 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 720 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 721 722 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 723 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 724 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 725 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 726 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 727 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 728 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 729 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 730 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 731 732 #define S_FW_ETH_TX_PKT2_WR_IVLAN 28 733 #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 734 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 735 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 736 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 737 #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 738 739 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 740 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 741 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 742 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 743 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 744 745 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 746 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 747 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 748 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 749 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 750 751 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 752 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 753 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 754 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 755 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 756 757 struct fw_eth_tx_pkts_wr { 758 __be32 op_pkd; 759 __be32 equiq_to_len16; 760 __be32 r3; 761 __be16 plen; 762 __u8 npkt; 763 __u8 type; 764 }; 765 766 #define S_FW_PTP_TX_PKT_WR_IMMDLEN 0 767 #define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff 768 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) 769 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ 770 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN) 771 772 struct fw_eth_tx_pkt_ptp_wr { 773 __be32 op_immdlen; 774 __be32 equiq_to_len16; 775 __be64 r3; 776 }; 777 778 enum fw_eth_tx_eo_type { 779 FW_ETH_TX_EO_TYPE_UDPSEG, 780 FW_ETH_TX_EO_TYPE_TCPSEG, 781 FW_ETH_TX_EO_TYPE_NVGRESEG, 782 FW_ETH_TX_EO_TYPE_VXLANSEG, 783 FW_ETH_TX_EO_TYPE_GENEVESEG, 784 }; 785 786 struct fw_eth_tx_eo_wr { 787 __be32 op_immdlen; 788 __be32 equiq_to_len16; 789 __be64 r3; 790 union fw_eth_tx_eo { 791 struct fw_eth_tx_eo_udpseg { 792 __u8 type; 793 __u8 ethlen; 794 __be16 iplen; 795 __u8 udplen; 796 __u8 rtplen; 797 __be16 r4; 798 __be16 mss; 799 __be16 schedpktsize; 800 __be32 plen; 801 } udpseg; 802 struct fw_eth_tx_eo_tcpseg { 803 __u8 type; 804 __u8 ethlen; 805 __be16 iplen; 806 __u8 tcplen; 807 __u8 tsclk_tsoff; 808 __be16 r4; 809 __be16 mss; 810 __be16 r5; 811 __be32 plen; 812 } tcpseg; 813 struct fw_eth_tx_eo_nvgreseg { 814 __u8 type; 815 __u8 iphdroffout; 816 __be16 grehdroff; 817 __be16 iphdroffin; 818 __be16 tcphdroffin; 819 __be16 mss; 820 __be16 r4; 821 __be32 plen; 822 } nvgreseg; 823 struct fw_eth_tx_eo_vxlanseg { 824 __u8 type; 825 __u8 iphdroffout; 826 __be16 vxlanhdroff; 827 __be16 iphdroffin; 828 __be16 tcphdroffin; 829 __be16 mss; 830 __be16 r4; 831 __be32 plen; 832 833 } vxlanseg; 834 struct fw_eth_tx_eo_geneveseg { 835 __u8 type; 836 __u8 iphdroffout; 837 __be16 genevehdroff; 838 __be16 iphdroffin; 839 __be16 tcphdroffin; 840 __be16 mss; 841 __be16 r4; 842 __be32 plen; 843 } geneveseg; 844 } u; 845 }; 846 847 #define S_FW_ETH_TX_EO_WR_IMMDLEN 0 848 #define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff 849 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) 850 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ 851 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN) 852 853 #define S_FW_ETH_TX_EO_WR_TSCLK 6 854 #define M_FW_ETH_TX_EO_WR_TSCLK 0x3 855 #define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) 856 #define G_FW_ETH_TX_EO_WR_TSCLK(x) \ 857 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK) 858 859 #define S_FW_ETH_TX_EO_WR_TSOFF 0 860 #define M_FW_ETH_TX_EO_WR_TSOFF 0x3f 861 #define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) 862 #define G_FW_ETH_TX_EO_WR_TSOFF(x) \ 863 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF) 864 865 struct fw_eq_flush_wr { 866 __u8 opcode; 867 __u8 r1[3]; 868 __be32 equiq_to_len16; 869 __be64 r3; 870 }; 871 872 struct fw_ofld_connection_wr { 873 __be32 op_compl; 874 __be32 len16_pkd; 875 __u64 cookie; 876 __be64 r2; 877 __be64 r3; 878 struct fw_ofld_connection_le { 879 __be32 version_cpl; 880 __be32 filter; 881 __be32 r1; 882 __be16 lport; 883 __be16 pport; 884 union fw_ofld_connection_leip { 885 struct fw_ofld_connection_le_ipv4 { 886 __be32 pip; 887 __be32 lip; 888 __be64 r0; 889 __be64 r1; 890 __be64 r2; 891 } ipv4; 892 struct fw_ofld_connection_le_ipv6 { 893 __be64 pip_hi; 894 __be64 pip_lo; 895 __be64 lip_hi; 896 __be64 lip_lo; 897 } ipv6; 898 } u; 899 } le; 900 struct fw_ofld_connection_tcb { 901 __be32 t_state_to_astid; 902 __be16 cplrxdataack_cplpassacceptrpl; 903 __be16 rcv_adv; 904 __be32 rcv_nxt; 905 __be32 tx_max; 906 __be64 opt0; 907 __be32 opt2; 908 __be32 r1; 909 __be64 r2; 910 __be64 r3; 911 } tcb; 912 }; 913 914 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 915 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 916 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 917 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 918 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 919 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 920 M_FW_OFLD_CONNECTION_WR_VERSION) 921 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 922 923 #define S_FW_OFLD_CONNECTION_WR_CPL 30 924 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 925 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 926 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 927 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 928 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 929 930 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 931 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 932 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 933 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 934 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 935 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 936 M_FW_OFLD_CONNECTION_WR_T_STATE) 937 938 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 939 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 940 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 941 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 942 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 943 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 944 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 945 946 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 947 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 948 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 949 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 950 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 951 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 952 953 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 954 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 955 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 956 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 957 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 958 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 959 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 960 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 961 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 962 963 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 964 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 965 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 966 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 967 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 968 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 969 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 970 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 971 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 972 973 enum fw_flowc_mnem_tcpstate { 974 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 975 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 976 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 977 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 978 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 979 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 980 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 981 * will resend FIN - equiv ESTAB 982 */ 983 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 984 * will resend FIN but have 985 * received FIN 986 */ 987 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 988 * will resend FIN but have 989 * received FIN 990 */ 991 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 992 * waiting for FIN 993 */ 994 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 995 }; 996 997 enum fw_flowc_mnem_eostate { 998 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */ 999 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 1000 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending 1001 * outstanding payload 1002 */ 1003 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after 1004 * discarding outstanding payload 1005 */ 1006 }; 1007 1008 enum fw_flowc_mnem { 1009 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 1010 FW_FLOWC_MNEM_CH = 1, 1011 FW_FLOWC_MNEM_PORT = 2, 1012 FW_FLOWC_MNEM_IQID = 3, 1013 FW_FLOWC_MNEM_SNDNXT = 4, 1014 FW_FLOWC_MNEM_RCVNXT = 5, 1015 FW_FLOWC_MNEM_SNDBUF = 6, 1016 FW_FLOWC_MNEM_MSS = 7, 1017 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 1018 FW_FLOWC_MNEM_TCPSTATE = 9, 1019 FW_FLOWC_MNEM_EOSTATE = 10, 1020 FW_FLOWC_MNEM_SCHEDCLASS = 11, 1021 FW_FLOWC_MNEM_DCBPRIO = 12, 1022 FW_FLOWC_MNEM_SND_SCALE = 13, 1023 FW_FLOWC_MNEM_RCV_SCALE = 14, 1024 FW_FLOWC_MNEM_ULP_MODE = 15, 1025 FW_FLOWC_MNEM_MAX = 16, 1026 }; 1027 1028 struct fw_flowc_mnemval { 1029 __u8 mnemonic; 1030 __u8 r4[3]; 1031 __be32 val; 1032 }; 1033 1034 struct fw_flowc_wr { 1035 __be32 op_to_nparams; 1036 __be32 flowid_len16; 1037 #ifndef C99_NOT_SUPPORTED 1038 struct fw_flowc_mnemval mnemval[0]; 1039 #endif 1040 }; 1041 1042 #define S_FW_FLOWC_WR_NPARAMS 0 1043 #define M_FW_FLOWC_WR_NPARAMS 0xff 1044 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 1045 #define G_FW_FLOWC_WR_NPARAMS(x) \ 1046 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 1047 1048 struct fw_ofld_tx_data_wr { 1049 __be32 op_to_immdlen; 1050 __be32 flowid_len16; 1051 __be32 plen; 1052 __be32 lsodisable_to_flags; 1053 }; 1054 1055 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 1056 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 1057 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1058 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 1059 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1060 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 1061 M_FW_OFLD_TX_DATA_WR_LSODISABLE) 1062 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 1063 1064 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 1065 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 1066 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1067 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1068 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1069 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1070 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 1071 1072 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 1073 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 1074 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1075 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1076 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1077 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 1078 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1079 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 1080 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 1081 1082 #define S_FW_OFLD_TX_DATA_WR_FLAGS 0 1083 #define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff 1084 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) 1085 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ 1086 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS) 1087 1088 1089 /* Use fw_ofld_tx_data_wr structure */ 1090 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10 1091 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff 1092 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1093 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1094 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1095 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1096 1097 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9 1098 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1 1099 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1100 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1101 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1102 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \ 1103 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1104 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \ 1105 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U) 1106 1107 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8 1108 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1 1109 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1110 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1111 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1112 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \ 1113 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1114 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \ 1115 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U) 1116 1117 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7 1118 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 1119 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1120 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1121 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1122 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 1123 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1124 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \ 1125 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 1126 1127 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6 1128 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 1129 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1130 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1131 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1132 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 1133 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1134 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \ 1135 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 1136 1137 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0 1138 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f 1139 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1140 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1141 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1142 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1143 1144 struct fw_cmd_wr { 1145 __be32 op_dma; 1146 __be32 len16_pkd; 1147 __be64 cookie_daddr; 1148 }; 1149 1150 #define S_FW_CMD_WR_DMA 17 1151 #define M_FW_CMD_WR_DMA 0x1 1152 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 1153 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 1154 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 1155 1156 struct fw_eth_tx_pkt_vm_wr { 1157 __be32 op_immdlen; 1158 __be32 equiq_to_len16; 1159 __be32 r3[2]; 1160 __u8 ethmacdst[6]; 1161 __u8 ethmacsrc[6]; 1162 __be16 ethtype; 1163 __be16 vlantci; 1164 }; 1165 1166 struct fw_eth_tx_pkts_vm_wr { 1167 __be32 op_pkd; 1168 __be32 equiq_to_len16; 1169 __be32 r3; 1170 __be16 plen; 1171 __u8 npkt; 1172 __u8 r4; 1173 __u8 ethmacdst[6]; 1174 __u8 ethmacsrc[6]; 1175 __be16 ethtype; 1176 __be16 vlantci; 1177 }; 1178 1179 /****************************************************************************** 1180 * R I W O R K R E Q U E S T s 1181 **************************************/ 1182 1183 enum fw_ri_wr_opcode { 1184 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 1185 FW_RI_READ_REQ = 0x1, 1186 FW_RI_READ_RESP = 0x2, 1187 FW_RI_SEND = 0x3, 1188 FW_RI_SEND_WITH_INV = 0x4, 1189 FW_RI_SEND_WITH_SE = 0x5, 1190 FW_RI_SEND_WITH_SE_INV = 0x6, 1191 FW_RI_TERMINATE = 0x7, 1192 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 1193 FW_RI_BIND_MW = 0x9, 1194 FW_RI_FAST_REGISTER = 0xa, 1195 FW_RI_LOCAL_INV = 0xb, 1196 FW_RI_QP_MODIFY = 0xc, 1197 FW_RI_BYPASS = 0xd, 1198 FW_RI_RECEIVE = 0xe, 1199 #if 0 1200 FW_RI_SEND_IMMEDIATE = 0x8, 1201 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 1202 FW_RI_ATOMIC_REQUEST = 0xa, 1203 FW_RI_ATOMIC_RESPONSE = 0xb, 1204 1205 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 1206 FW_RI_FAST_REGISTER = 0xd, 1207 FW_RI_LOCAL_INV = 0xe, 1208 #endif 1209 FW_RI_SGE_EC_CR_RETURN = 0xf, 1210 FW_RI_WRITE_IMMEDIATE = FW_RI_RDMA_INIT, 1211 }; 1212 1213 enum fw_ri_wr_flags { 1214 FW_RI_COMPLETION_FLAG = 0x01, 1215 FW_RI_NOTIFICATION_FLAG = 0x02, 1216 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 1217 FW_RI_READ_FENCE_FLAG = 0x08, 1218 FW_RI_LOCAL_FENCE_FLAG = 0x10, 1219 FW_RI_RDMA_READ_INVALIDATE = 0x20, 1220 FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40 1221 }; 1222 1223 enum fw_ri_mpa_attrs { 1224 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 1225 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 1226 FW_RI_MPA_CRC_ENABLE = 0x04, 1227 FW_RI_MPA_IETF_ENABLE = 0x08 1228 }; 1229 1230 enum fw_ri_qp_caps { 1231 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 1232 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 1233 FW_RI_QP_BIND_ENABLE = 0x04, 1234 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 1235 FW_RI_QP_STAG0_ENABLE = 0x10, 1236 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 1237 }; 1238 1239 enum fw_ri_addr_type { 1240 FW_RI_ZERO_BASED_TO = 0x00, 1241 FW_RI_VA_BASED_TO = 0x01 1242 }; 1243 1244 enum fw_ri_mem_perms { 1245 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 1246 FW_RI_MEM_ACCESS_REM_READ = 0x02, 1247 FW_RI_MEM_ACCESS_REM = 0x03, 1248 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 1249 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 1250 FW_RI_MEM_ACCESS_LOCAL = 0x0C 1251 }; 1252 1253 enum fw_ri_stag_type { 1254 FW_RI_STAG_NSMR = 0x00, 1255 FW_RI_STAG_SMR = 0x01, 1256 FW_RI_STAG_MW = 0x02, 1257 FW_RI_STAG_MW_RELAXED = 0x03 1258 }; 1259 1260 enum fw_ri_data_op { 1261 FW_RI_DATA_IMMD = 0x81, 1262 FW_RI_DATA_DSGL = 0x82, 1263 FW_RI_DATA_ISGL = 0x83 1264 }; 1265 1266 enum fw_ri_sgl_depth { 1267 FW_RI_SGL_DEPTH_MAX_SQ = 16, 1268 FW_RI_SGL_DEPTH_MAX_RQ = 4 1269 }; 1270 1271 enum fw_ri_cqe_err { 1272 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 1273 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 1274 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 1275 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 1276 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 1277 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 1278 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 1279 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 1280 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 1281 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1282 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1283 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 1284 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 1285 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 1286 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 1287 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 1288 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 1289 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 1290 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 1291 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 1292 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 1293 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1294 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 1295 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 1296 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 1297 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1298 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 1299 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 1300 1301 }; 1302 1303 struct fw_ri_dsge_pair { 1304 __be32 len[2]; 1305 __be64 addr[2]; 1306 }; 1307 1308 struct fw_ri_dsgl { 1309 __u8 op; 1310 __u8 r1; 1311 __be16 nsge; 1312 __be32 len0; 1313 __be64 addr0; 1314 #ifndef C99_NOT_SUPPORTED 1315 struct fw_ri_dsge_pair sge[0]; 1316 #endif 1317 }; 1318 1319 struct fw_ri_sge { 1320 __be32 stag; 1321 __be32 len; 1322 __be64 to; 1323 }; 1324 1325 struct fw_ri_isgl { 1326 __u8 op; 1327 __u8 r1; 1328 __be16 nsge; 1329 __be32 r2; 1330 #ifndef C99_NOT_SUPPORTED 1331 struct fw_ri_sge sge[0]; 1332 #endif 1333 }; 1334 1335 struct fw_ri_immd { 1336 __u8 op; 1337 __u8 r1; 1338 __be16 r2; 1339 __be32 immdlen; 1340 #ifndef C99_NOT_SUPPORTED 1341 __u8 data[0]; 1342 #endif 1343 }; 1344 1345 struct fw_ri_tpte { 1346 __be32 valid_to_pdid; 1347 __be32 locread_to_qpid; 1348 __be32 nosnoop_pbladdr; 1349 __be32 len_lo; 1350 __be32 va_hi; 1351 __be32 va_lo_fbo; 1352 __be32 dca_mwbcnt_pstag; 1353 __be32 len_hi; 1354 }; 1355 1356 #define S_FW_RI_TPTE_VALID 31 1357 #define M_FW_RI_TPTE_VALID 0x1 1358 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1359 #define G_FW_RI_TPTE_VALID(x) \ 1360 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1361 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1362 1363 #define S_FW_RI_TPTE_STAGKEY 23 1364 #define M_FW_RI_TPTE_STAGKEY 0xff 1365 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1366 #define G_FW_RI_TPTE_STAGKEY(x) \ 1367 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1368 1369 #define S_FW_RI_TPTE_STAGSTATE 22 1370 #define M_FW_RI_TPTE_STAGSTATE 0x1 1371 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1372 #define G_FW_RI_TPTE_STAGSTATE(x) \ 1373 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1374 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1375 1376 #define S_FW_RI_TPTE_STAGTYPE 20 1377 #define M_FW_RI_TPTE_STAGTYPE 0x3 1378 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1379 #define G_FW_RI_TPTE_STAGTYPE(x) \ 1380 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1381 1382 #define S_FW_RI_TPTE_PDID 0 1383 #define M_FW_RI_TPTE_PDID 0xfffff 1384 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1385 #define G_FW_RI_TPTE_PDID(x) \ 1386 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1387 1388 #define S_FW_RI_TPTE_PERM 28 1389 #define M_FW_RI_TPTE_PERM 0xf 1390 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1391 #define G_FW_RI_TPTE_PERM(x) \ 1392 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1393 1394 #define S_FW_RI_TPTE_REMINVDIS 27 1395 #define M_FW_RI_TPTE_REMINVDIS 0x1 1396 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1397 #define G_FW_RI_TPTE_REMINVDIS(x) \ 1398 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1399 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1400 1401 #define S_FW_RI_TPTE_ADDRTYPE 26 1402 #define M_FW_RI_TPTE_ADDRTYPE 1 1403 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1404 #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1405 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1406 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1407 1408 #define S_FW_RI_TPTE_MWBINDEN 25 1409 #define M_FW_RI_TPTE_MWBINDEN 0x1 1410 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1411 #define G_FW_RI_TPTE_MWBINDEN(x) \ 1412 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1413 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1414 1415 #define S_FW_RI_TPTE_PS 20 1416 #define M_FW_RI_TPTE_PS 0x1f 1417 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1418 #define G_FW_RI_TPTE_PS(x) \ 1419 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1420 1421 #define S_FW_RI_TPTE_QPID 0 1422 #define M_FW_RI_TPTE_QPID 0xfffff 1423 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1424 #define G_FW_RI_TPTE_QPID(x) \ 1425 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1426 1427 #define S_FW_RI_TPTE_NOSNOOP 31 1428 #define M_FW_RI_TPTE_NOSNOOP 0x1 1429 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1430 #define G_FW_RI_TPTE_NOSNOOP(x) \ 1431 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1432 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1433 1434 #define S_FW_RI_TPTE_PBLADDR 0 1435 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1436 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1437 #define G_FW_RI_TPTE_PBLADDR(x) \ 1438 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1439 1440 #define S_FW_RI_TPTE_DCA 24 1441 #define M_FW_RI_TPTE_DCA 0x1f 1442 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1443 #define G_FW_RI_TPTE_DCA(x) \ 1444 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1445 1446 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1447 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1448 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1449 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1450 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1451 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1452 1453 enum fw_ri_cqe_rxtx { 1454 FW_RI_CQE_RXTX_RX = 0x0, 1455 FW_RI_CQE_RXTX_TX = 0x1, 1456 }; 1457 1458 struct fw_ri_cqe { 1459 union fw_ri_rxtx { 1460 struct fw_ri_scqe { 1461 __be32 qpid_n_stat_rxtx_type; 1462 __be32 plen; 1463 __be32 stag; 1464 __be32 wrid; 1465 } scqe; 1466 struct fw_ri_rcqe { 1467 __be32 qpid_n_stat_rxtx_type; 1468 __be32 plen; 1469 __be32 stag; 1470 __be32 msn; 1471 } rcqe; 1472 struct fw_ri_rcqe_imm { 1473 __be32 qpid_n_stat_rxtx_type; 1474 __be32 plen; 1475 __be32 mo; 1476 __be32 msn; 1477 __u64 imm_data; 1478 } imm_data_rcqe; 1479 } u; 1480 }; 1481 1482 #define S_FW_RI_CQE_QPID 12 1483 #define M_FW_RI_CQE_QPID 0xfffff 1484 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1485 #define G_FW_RI_CQE_QPID(x) \ 1486 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1487 1488 #define S_FW_RI_CQE_NOTIFY 10 1489 #define M_FW_RI_CQE_NOTIFY 0x1 1490 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1491 #define G_FW_RI_CQE_NOTIFY(x) \ 1492 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1493 1494 #define S_FW_RI_CQE_STATUS 5 1495 #define M_FW_RI_CQE_STATUS 0x1f 1496 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1497 #define G_FW_RI_CQE_STATUS(x) \ 1498 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1499 1500 1501 #define S_FW_RI_CQE_RXTX 4 1502 #define M_FW_RI_CQE_RXTX 0x1 1503 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1504 #define G_FW_RI_CQE_RXTX(x) \ 1505 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1506 1507 #define S_FW_RI_CQE_TYPE 0 1508 #define M_FW_RI_CQE_TYPE 0xf 1509 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1510 #define G_FW_RI_CQE_TYPE(x) \ 1511 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1512 1513 enum fw_ri_res_type { 1514 FW_RI_RES_TYPE_SQ, 1515 FW_RI_RES_TYPE_RQ, 1516 FW_RI_RES_TYPE_CQ, 1517 FW_RI_RES_TYPE_SRQ, 1518 }; 1519 1520 enum fw_ri_res_op { 1521 FW_RI_RES_OP_WRITE, 1522 FW_RI_RES_OP_RESET, 1523 }; 1524 1525 struct fw_ri_res { 1526 union fw_ri_restype { 1527 struct fw_ri_res_sqrq { 1528 __u8 restype; 1529 __u8 op; 1530 __be16 r3; 1531 __be32 eqid; 1532 __be32 r4[2]; 1533 __be32 fetchszm_to_iqid; 1534 __be32 dcaen_to_eqsize; 1535 __be64 eqaddr; 1536 } sqrq; 1537 struct fw_ri_res_cq { 1538 __u8 restype; 1539 __u8 op; 1540 __be16 r3; 1541 __be32 iqid; 1542 __be32 r4[2]; 1543 __be32 iqandst_to_iqandstindex; 1544 __be16 iqdroprss_to_iqesize; 1545 __be16 iqsize; 1546 __be64 iqaddr; 1547 __be32 iqns_iqro; 1548 __be32 r6_lo; 1549 __be64 r7; 1550 } cq; 1551 struct fw_ri_res_srq { 1552 __u8 restype; 1553 __u8 op; 1554 __be16 r3; 1555 __be32 eqid; 1556 __be32 r4[2]; 1557 __be32 fetchszm_to_iqid; 1558 __be32 dcaen_to_eqsize; 1559 __be64 eqaddr; 1560 __be32 srqid; 1561 __be32 pdid; 1562 __be32 hwsrqsize; 1563 __be32 hwsrqaddr; 1564 } srq; 1565 } u; 1566 }; 1567 1568 struct fw_ri_res_wr { 1569 __be32 op_nres; 1570 __be32 len16_pkd; 1571 __u64 cookie; 1572 #ifndef C99_NOT_SUPPORTED 1573 struct fw_ri_res res[0]; 1574 #endif 1575 }; 1576 1577 #define S_FW_RI_RES_WR_VFN 8 1578 #define M_FW_RI_RES_WR_VFN 0xff 1579 #define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN) 1580 #define G_FW_RI_RES_WR_VFN(x) \ 1581 (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN) 1582 1583 #define S_FW_RI_RES_WR_NRES 0 1584 #define M_FW_RI_RES_WR_NRES 0xff 1585 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1586 #define G_FW_RI_RES_WR_NRES(x) \ 1587 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1588 1589 #define S_FW_RI_RES_WR_FETCHSZM 26 1590 #define M_FW_RI_RES_WR_FETCHSZM 0x1 1591 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1592 #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1593 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1594 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1595 1596 #define S_FW_RI_RES_WR_STATUSPGNS 25 1597 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1598 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1599 #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1600 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1601 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1602 1603 #define S_FW_RI_RES_WR_STATUSPGRO 24 1604 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1605 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1606 #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1607 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1608 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1609 1610 #define S_FW_RI_RES_WR_FETCHNS 23 1611 #define M_FW_RI_RES_WR_FETCHNS 0x1 1612 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1613 #define G_FW_RI_RES_WR_FETCHNS(x) \ 1614 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1615 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1616 1617 #define S_FW_RI_RES_WR_FETCHRO 22 1618 #define M_FW_RI_RES_WR_FETCHRO 0x1 1619 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1620 #define G_FW_RI_RES_WR_FETCHRO(x) \ 1621 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1622 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1623 1624 #define S_FW_RI_RES_WR_HOSTFCMODE 20 1625 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1626 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1627 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1628 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1629 1630 #define S_FW_RI_RES_WR_CPRIO 19 1631 #define M_FW_RI_RES_WR_CPRIO 0x1 1632 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1633 #define G_FW_RI_RES_WR_CPRIO(x) \ 1634 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1635 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1636 1637 #define S_FW_RI_RES_WR_ONCHIP 18 1638 #define M_FW_RI_RES_WR_ONCHIP 0x1 1639 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1640 #define G_FW_RI_RES_WR_ONCHIP(x) \ 1641 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1642 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1643 1644 #define S_FW_RI_RES_WR_PCIECHN 16 1645 #define M_FW_RI_RES_WR_PCIECHN 0x3 1646 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1647 #define G_FW_RI_RES_WR_PCIECHN(x) \ 1648 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1649 1650 #define S_FW_RI_RES_WR_IQID 0 1651 #define M_FW_RI_RES_WR_IQID 0xffff 1652 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1653 #define G_FW_RI_RES_WR_IQID(x) \ 1654 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1655 1656 #define S_FW_RI_RES_WR_DCAEN 31 1657 #define M_FW_RI_RES_WR_DCAEN 0x1 1658 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1659 #define G_FW_RI_RES_WR_DCAEN(x) \ 1660 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1661 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1662 1663 #define S_FW_RI_RES_WR_DCACPU 26 1664 #define M_FW_RI_RES_WR_DCACPU 0x1f 1665 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1666 #define G_FW_RI_RES_WR_DCACPU(x) \ 1667 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1668 1669 #define S_FW_RI_RES_WR_FBMIN 23 1670 #define M_FW_RI_RES_WR_FBMIN 0x7 1671 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1672 #define G_FW_RI_RES_WR_FBMIN(x) \ 1673 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1674 1675 #define S_FW_RI_RES_WR_FBMAX 20 1676 #define M_FW_RI_RES_WR_FBMAX 0x7 1677 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1678 #define G_FW_RI_RES_WR_FBMAX(x) \ 1679 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1680 1681 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1682 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1683 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1684 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1685 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1686 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1687 1688 #define S_FW_RI_RES_WR_CIDXFTHRESH 16 1689 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1690 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1691 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1692 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1693 1694 #define S_FW_RI_RES_WR_EQSIZE 0 1695 #define M_FW_RI_RES_WR_EQSIZE 0xffff 1696 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1697 #define G_FW_RI_RES_WR_EQSIZE(x) \ 1698 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1699 1700 #define S_FW_RI_RES_WR_IQANDST 15 1701 #define M_FW_RI_RES_WR_IQANDST 0x1 1702 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1703 #define G_FW_RI_RES_WR_IQANDST(x) \ 1704 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1705 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1706 1707 #define S_FW_RI_RES_WR_IQANUS 14 1708 #define M_FW_RI_RES_WR_IQANUS 0x1 1709 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1710 #define G_FW_RI_RES_WR_IQANUS(x) \ 1711 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1712 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1713 1714 #define S_FW_RI_RES_WR_IQANUD 12 1715 #define M_FW_RI_RES_WR_IQANUD 0x3 1716 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1717 #define G_FW_RI_RES_WR_IQANUD(x) \ 1718 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1719 1720 #define S_FW_RI_RES_WR_IQANDSTINDEX 0 1721 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1722 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1723 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1724 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1725 1726 #define S_FW_RI_RES_WR_IQDROPRSS 15 1727 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 1728 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1729 #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1730 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1731 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1732 1733 #define S_FW_RI_RES_WR_IQGTSMODE 14 1734 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 1735 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1736 #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1737 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1738 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1739 1740 #define S_FW_RI_RES_WR_IQPCIECH 12 1741 #define M_FW_RI_RES_WR_IQPCIECH 0x3 1742 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1743 #define G_FW_RI_RES_WR_IQPCIECH(x) \ 1744 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1745 1746 #define S_FW_RI_RES_WR_IQDCAEN 11 1747 #define M_FW_RI_RES_WR_IQDCAEN 0x1 1748 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1749 #define G_FW_RI_RES_WR_IQDCAEN(x) \ 1750 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1751 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1752 1753 #define S_FW_RI_RES_WR_IQDCACPU 6 1754 #define M_FW_RI_RES_WR_IQDCACPU 0x1f 1755 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1756 #define G_FW_RI_RES_WR_IQDCACPU(x) \ 1757 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1758 1759 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1760 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1761 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1762 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1763 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1764 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1765 1766 #define S_FW_RI_RES_WR_IQO 3 1767 #define M_FW_RI_RES_WR_IQO 0x1 1768 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1769 #define G_FW_RI_RES_WR_IQO(x) \ 1770 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1771 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1772 1773 #define S_FW_RI_RES_WR_IQCPRIO 2 1774 #define M_FW_RI_RES_WR_IQCPRIO 0x1 1775 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1776 #define G_FW_RI_RES_WR_IQCPRIO(x) \ 1777 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1778 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1779 1780 #define S_FW_RI_RES_WR_IQESIZE 0 1781 #define M_FW_RI_RES_WR_IQESIZE 0x3 1782 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1783 #define G_FW_RI_RES_WR_IQESIZE(x) \ 1784 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1785 1786 #define S_FW_RI_RES_WR_IQNS 31 1787 #define M_FW_RI_RES_WR_IQNS 0x1 1788 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1789 #define G_FW_RI_RES_WR_IQNS(x) \ 1790 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1791 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1792 1793 #define S_FW_RI_RES_WR_IQRO 30 1794 #define M_FW_RI_RES_WR_IQRO 0x1 1795 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1796 #define G_FW_RI_RES_WR_IQRO(x) \ 1797 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1798 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1799 1800 struct fw_ri_rdma_write_wr { 1801 __u8 opcode; 1802 __u8 flags; 1803 __u16 wrid; 1804 __u8 r1[3]; 1805 __u8 len16; 1806 __u64 immd_data; 1807 __be32 plen; 1808 __be32 stag_sink; 1809 __be64 to_sink; 1810 #ifndef C99_NOT_SUPPORTED 1811 union { 1812 struct fw_ri_immd immd_src[0]; 1813 struct fw_ri_isgl isgl_src[0]; 1814 } u; 1815 #endif 1816 }; 1817 1818 struct fw_ri_send_wr { 1819 __u8 opcode; 1820 __u8 flags; 1821 __u16 wrid; 1822 __u8 r1[3]; 1823 __u8 len16; 1824 __be32 sendop_pkd; 1825 __be32 stag_inv; 1826 __be32 plen; 1827 __be32 r3; 1828 __be64 r4; 1829 #ifndef C99_NOT_SUPPORTED 1830 union { 1831 struct fw_ri_immd immd_src[0]; 1832 struct fw_ri_isgl isgl_src[0]; 1833 } u; 1834 #endif 1835 }; 1836 1837 #define S_FW_RI_SEND_WR_SENDOP 0 1838 #define M_FW_RI_SEND_WR_SENDOP 0xf 1839 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1840 #define G_FW_RI_SEND_WR_SENDOP(x) \ 1841 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1842 1843 struct fw_ri_rdma_write_cmpl_wr { 1844 __u8 opcode; 1845 __u8 flags; 1846 __u16 wrid; 1847 __u8 r1[3]; 1848 __u8 len16; 1849 __u8 r2; 1850 __u8 flags_send; 1851 __u16 wrid_send; 1852 __be32 stag_inv; 1853 __be32 plen; 1854 __be32 stag_sink; 1855 __be64 to_sink; 1856 union fw_ri_cmpl { 1857 struct fw_ri_immd_cmpl { 1858 __u8 op; 1859 __u8 r1[6]; 1860 __u8 immdlen; 1861 __u8 data[16]; 1862 } immd_src; 1863 struct fw_ri_isgl isgl_src; 1864 } u_cmpl; 1865 __be64 r3; 1866 #ifndef C99_NOT_SUPPORTED 1867 union fw_ri_write { 1868 struct fw_ri_immd immd_src[0]; 1869 struct fw_ri_isgl isgl_src[0]; 1870 } u; 1871 #endif 1872 }; 1873 1874 struct fw_ri_rdma_read_wr { 1875 __u8 opcode; 1876 __u8 flags; 1877 __u16 wrid; 1878 __u8 r1[3]; 1879 __u8 len16; 1880 __be64 r2; 1881 __be32 stag_sink; 1882 __be32 to_sink_hi; 1883 __be32 to_sink_lo; 1884 __be32 plen; 1885 __be32 stag_src; 1886 __be32 to_src_hi; 1887 __be32 to_src_lo; 1888 __be32 r5; 1889 }; 1890 1891 struct fw_ri_recv_wr { 1892 __u8 opcode; 1893 __u8 r1; 1894 __u16 wrid; 1895 __u8 r2[3]; 1896 __u8 len16; 1897 struct fw_ri_isgl isgl; 1898 }; 1899 1900 struct fw_ri_bind_mw_wr { 1901 __u8 opcode; 1902 __u8 flags; 1903 __u16 wrid; 1904 __u8 r1[3]; 1905 __u8 len16; 1906 __u8 qpbinde_to_dcacpu; 1907 __u8 pgsz_shift; 1908 __u8 addr_type; 1909 __u8 mem_perms; 1910 __be32 stag_mr; 1911 __be32 stag_mw; 1912 __be32 r3; 1913 __be64 len_mw; 1914 __be64 va_fbo; 1915 __be64 r4; 1916 }; 1917 1918 #define S_FW_RI_BIND_MW_WR_QPBINDE 6 1919 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1920 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1921 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1922 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1923 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1924 1925 #define S_FW_RI_BIND_MW_WR_NS 5 1926 #define M_FW_RI_BIND_MW_WR_NS 0x1 1927 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1928 #define G_FW_RI_BIND_MW_WR_NS(x) \ 1929 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1930 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1931 1932 #define S_FW_RI_BIND_MW_WR_DCACPU 0 1933 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1934 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1935 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1936 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1937 1938 struct fw_ri_fr_nsmr_wr { 1939 __u8 opcode; 1940 __u8 flags; 1941 __u16 wrid; 1942 __u8 r1[3]; 1943 __u8 len16; 1944 __u8 qpbinde_to_dcacpu; 1945 __u8 pgsz_shift; 1946 __u8 addr_type; 1947 __u8 mem_perms; 1948 __be32 stag; 1949 __be32 len_hi; 1950 __be32 len_lo; 1951 __be32 va_hi; 1952 __be32 va_lo_fbo; 1953 }; 1954 1955 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1956 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1957 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1958 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1959 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1960 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1961 1962 #define S_FW_RI_FR_NSMR_WR_NS 5 1963 #define M_FW_RI_FR_NSMR_WR_NS 0x1 1964 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1965 #define G_FW_RI_FR_NSMR_WR_NS(x) \ 1966 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1967 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1968 1969 #define S_FW_RI_FR_NSMR_WR_DCACPU 0 1970 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1971 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1972 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1973 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1974 1975 struct fw_ri_fr_nsmr_tpte_wr { 1976 __u8 opcode; 1977 __u8 flags; 1978 __u16 wrid; 1979 __u8 r1[3]; 1980 __u8 len16; 1981 __be32 r2; 1982 __be32 stag; 1983 struct fw_ri_tpte tpte; 1984 __be64 pbl[2]; 1985 }; 1986 1987 struct fw_ri_inv_lstag_wr { 1988 __u8 opcode; 1989 __u8 flags; 1990 __u16 wrid; 1991 __u8 r1[3]; 1992 __u8 len16; 1993 __be32 r2; 1994 __be32 stag_inv; 1995 }; 1996 1997 struct fw_ri_send_immediate_wr { 1998 __u8 opcode; 1999 __u8 flags; 2000 __u16 wrid; 2001 __u8 r1[3]; 2002 __u8 len16; 2003 __be32 sendimmop_pkd; 2004 __be32 r3; 2005 __be32 plen; 2006 __be32 r4; 2007 __be64 r5; 2008 #ifndef C99_NOT_SUPPORTED 2009 struct fw_ri_immd immd_src[0]; 2010 #endif 2011 }; 2012 2013 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 2014 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 2015 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 2016 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 2017 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 2018 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 2019 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 2020 2021 enum fw_ri_atomic_op { 2022 FW_RI_ATOMIC_OP_FETCHADD, 2023 FW_RI_ATOMIC_OP_SWAP, 2024 FW_RI_ATOMIC_OP_CMDSWAP, 2025 }; 2026 2027 struct fw_ri_atomic_wr { 2028 __u8 opcode; 2029 __u8 flags; 2030 __u16 wrid; 2031 __u8 r1[3]; 2032 __u8 len16; 2033 __be32 atomicop_pkd; 2034 __be64 r3; 2035 __be32 aopcode_pkd; 2036 __be32 reqid; 2037 __be32 stag; 2038 __be32 to_hi; 2039 __be32 to_lo; 2040 __be32 addswap_data_hi; 2041 __be32 addswap_data_lo; 2042 __be32 addswap_mask_hi; 2043 __be32 addswap_mask_lo; 2044 __be32 compare_data_hi; 2045 __be32 compare_data_lo; 2046 __be32 compare_mask_hi; 2047 __be32 compare_mask_lo; 2048 __be32 r5; 2049 }; 2050 2051 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 2052 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 2053 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 2054 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 2055 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 2056 2057 #define S_FW_RI_ATOMIC_WR_AOPCODE 0 2058 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 2059 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 2060 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 2061 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 2062 2063 enum fw_ri_type { 2064 FW_RI_TYPE_INIT, 2065 FW_RI_TYPE_FINI, 2066 FW_RI_TYPE_TERMINATE 2067 }; 2068 2069 enum fw_ri_init_p2ptype { 2070 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 2071 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 2072 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 2073 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 2074 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 2075 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 2076 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 2077 }; 2078 2079 enum fw_ri_init_rqeqid_srq { 2080 FW_RI_INIT_RQEQID_SRQ = 1U << 31, 2081 }; 2082 2083 struct fw_ri_wr { 2084 __be32 op_compl; 2085 __be32 flowid_len16; 2086 __u64 cookie; 2087 union fw_ri { 2088 struct fw_ri_init { 2089 __u8 type; 2090 __u8 mpareqbit_p2ptype; 2091 __u8 r4[2]; 2092 __u8 mpa_attrs; 2093 __u8 qp_caps; 2094 __be16 nrqe; 2095 __be32 pdid; 2096 __be32 qpid; 2097 __be32 sq_eqid; 2098 __be32 rq_eqid; 2099 __be32 scqid; 2100 __be32 rcqid; 2101 __be32 ord_max; 2102 __be32 ird_max; 2103 __be32 iss; 2104 __be32 irs; 2105 __be32 hwrqsize; 2106 __be32 hwrqaddr; 2107 __be64 r5; 2108 union fw_ri_init_p2p { 2109 struct fw_ri_rdma_write_wr write; 2110 struct fw_ri_rdma_read_wr read; 2111 struct fw_ri_send_wr send; 2112 } u; 2113 } init; 2114 struct fw_ri_fini { 2115 __u8 type; 2116 __u8 r3[7]; 2117 __be64 r4; 2118 } fini; 2119 struct fw_ri_terminate { 2120 __u8 type; 2121 __u8 r3[3]; 2122 __be32 immdlen; 2123 __u8 termmsg[40]; 2124 } terminate; 2125 } u; 2126 }; 2127 2128 #define S_FW_RI_WR_MPAREQBIT 7 2129 #define M_FW_RI_WR_MPAREQBIT 0x1 2130 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 2131 #define G_FW_RI_WR_MPAREQBIT(x) \ 2132 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 2133 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 2134 2135 #define S_FW_RI_WR_0BRRBIT 6 2136 #define M_FW_RI_WR_0BRRBIT 0x1 2137 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 2138 #define G_FW_RI_WR_0BRRBIT(x) \ 2139 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 2140 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 2141 2142 #define S_FW_RI_WR_P2PTYPE 0 2143 #define M_FW_RI_WR_P2PTYPE 0xf 2144 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 2145 #define G_FW_RI_WR_P2PTYPE(x) \ 2146 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 2147 2148 /****************************************************************************** 2149 * F O i S C S I W O R K R E Q U E S T s 2150 *********************************************/ 2151 2152 #define FW_FOISCSI_NAME_MAX_LEN 224 2153 #define FW_FOISCSI_ALIAS_MAX_LEN 224 2154 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 2155 #define FW_FOISCSI_INIT_NODE_MAX 8 2156 2157 enum fw_chnet_ifconf_wr_subop { 2158 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 2159 2160 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 2161 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 2162 2163 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 2164 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 2165 2166 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 2167 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 2168 2169 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 2170 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 2171 2172 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 2173 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 2174 2175 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 2176 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 2177 2178 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET, 2179 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET, 2180 2181 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET, 2182 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET, 2183 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED, 2184 2185 FW_CHNET_IFCONF_WR_SUBOP_MAX, 2186 }; 2187 2188 struct fw_chnet_ifconf_wr { 2189 __be32 op_compl; 2190 __be32 flowid_len16; 2191 __be64 cookie; 2192 __be32 if_flowid; 2193 __u8 idx; 2194 __u8 subop; 2195 __u8 retval; 2196 __u8 r2; 2197 __be64 r3; 2198 struct fw_chnet_ifconf_params { 2199 __be32 r0; 2200 __be16 vlanid; 2201 __be16 mtu; 2202 union fw_chnet_ifconf_addr_type { 2203 struct fw_chnet_ifconf_ipv4 { 2204 __be32 addr; 2205 __be32 mask; 2206 __be32 router; 2207 __be32 r0; 2208 __be64 r1; 2209 } ipv4; 2210 struct fw_chnet_ifconf_ipv6 { 2211 __u8 prefix_len; 2212 __u8 r0; 2213 __be16 r1; 2214 __be32 r2; 2215 __be64 addr_hi; 2216 __be64 addr_lo; 2217 __be64 router_hi; 2218 __be64 router_lo; 2219 } ipv6; 2220 } in_attr; 2221 } param; 2222 }; 2223 2224 enum fw_foiscsi_node_type { 2225 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 2226 FW_FOISCSI_NODE_TYPE_TARGET, 2227 }; 2228 2229 enum fw_foiscsi_session_type { 2230 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 2231 FW_FOISCSI_SESSION_TYPE_NORMAL, 2232 }; 2233 2234 enum fw_foiscsi_auth_policy { 2235 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 2236 FW_FOISCSI_AUTH_POLICY_MUTUAL, 2237 }; 2238 2239 enum fw_foiscsi_auth_method { 2240 FW_FOISCSI_AUTH_METHOD_NONE = 0, 2241 FW_FOISCSI_AUTH_METHOD_CHAP, 2242 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 2243 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 2244 }; 2245 2246 enum fw_foiscsi_digest_type { 2247 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 2248 FW_FOISCSI_DIGEST_TYPE_CRC32, 2249 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 2250 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 2251 }; 2252 2253 enum fw_foiscsi_wr_subop { 2254 FW_FOISCSI_WR_SUBOP_ADD = 1, 2255 FW_FOISCSI_WR_SUBOP_DEL = 2, 2256 FW_FOISCSI_WR_SUBOP_MOD = 4, 2257 }; 2258 2259 enum fw_foiscsi_ctrl_state { 2260 FW_FOISCSI_CTRL_STATE_FREE = 0, 2261 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 2262 FW_FOISCSI_CTRL_STATE_FAILED, 2263 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 2264 FW_FOISCSI_CTRL_STATE_REDIRECT, 2265 }; 2266 2267 struct fw_rdev_wr { 2268 __be32 op_to_immdlen; 2269 __be32 alloc_to_len16; 2270 __be64 cookie; 2271 __u8 protocol; 2272 __u8 event_cause; 2273 __u8 cur_state; 2274 __u8 prev_state; 2275 __be32 flags_to_assoc_flowid; 2276 union rdev_entry { 2277 struct fcoe_rdev_entry { 2278 __be32 flowid; 2279 __u8 protocol; 2280 __u8 event_cause; 2281 __u8 flags; 2282 __u8 rjt_reason; 2283 __u8 cur_login_st; 2284 __u8 prev_login_st; 2285 __be16 rcv_fr_sz; 2286 __u8 rd_xfer_rdy_to_rport_type; 2287 __u8 vft_to_qos; 2288 __u8 org_proc_assoc_to_acc_rsp_code; 2289 __u8 enh_disc_to_tgt; 2290 __u8 wwnn[8]; 2291 __u8 wwpn[8]; 2292 __be16 iqid; 2293 __u8 fc_oui[3]; 2294 __u8 r_id[3]; 2295 } fcoe_rdev; 2296 struct iscsi_rdev_entry { 2297 __be32 flowid; 2298 __u8 protocol; 2299 __u8 event_cause; 2300 __u8 flags; 2301 __u8 r3; 2302 __be16 iscsi_opts; 2303 __be16 tcp_opts; 2304 __be16 ip_opts; 2305 __be16 max_rcv_len; 2306 __be16 max_snd_len; 2307 __be16 first_brst_len; 2308 __be16 max_brst_len; 2309 __be16 r4; 2310 __be16 def_time2wait; 2311 __be16 def_time2ret; 2312 __be16 nop_out_intrvl; 2313 __be16 non_scsi_to; 2314 __be16 isid; 2315 __be16 tsid; 2316 __be16 port; 2317 __be16 tpgt; 2318 __u8 r5[6]; 2319 __be16 iqid; 2320 } iscsi_rdev; 2321 } u; 2322 }; 2323 2324 #define S_FW_RDEV_WR_IMMDLEN 0 2325 #define M_FW_RDEV_WR_IMMDLEN 0xff 2326 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 2327 #define G_FW_RDEV_WR_IMMDLEN(x) \ 2328 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 2329 2330 #define S_FW_RDEV_WR_ALLOC 31 2331 #define M_FW_RDEV_WR_ALLOC 0x1 2332 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 2333 #define G_FW_RDEV_WR_ALLOC(x) \ 2334 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 2335 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 2336 2337 #define S_FW_RDEV_WR_FREE 30 2338 #define M_FW_RDEV_WR_FREE 0x1 2339 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 2340 #define G_FW_RDEV_WR_FREE(x) \ 2341 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 2342 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 2343 2344 #define S_FW_RDEV_WR_MODIFY 29 2345 #define M_FW_RDEV_WR_MODIFY 0x1 2346 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 2347 #define G_FW_RDEV_WR_MODIFY(x) \ 2348 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 2349 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 2350 2351 #define S_FW_RDEV_WR_FLOWID 8 2352 #define M_FW_RDEV_WR_FLOWID 0xfffff 2353 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 2354 #define G_FW_RDEV_WR_FLOWID(x) \ 2355 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 2356 2357 #define S_FW_RDEV_WR_LEN16 0 2358 #define M_FW_RDEV_WR_LEN16 0xff 2359 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 2360 #define G_FW_RDEV_WR_LEN16(x) \ 2361 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 2362 2363 #define S_FW_RDEV_WR_FLAGS 24 2364 #define M_FW_RDEV_WR_FLAGS 0xff 2365 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 2366 #define G_FW_RDEV_WR_FLAGS(x) \ 2367 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 2368 2369 #define S_FW_RDEV_WR_GET_NEXT 20 2370 #define M_FW_RDEV_WR_GET_NEXT 0xf 2371 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 2372 #define G_FW_RDEV_WR_GET_NEXT(x) \ 2373 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 2374 2375 #define S_FW_RDEV_WR_ASSOC_FLOWID 0 2376 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 2377 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 2378 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 2379 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 2380 2381 #define S_FW_RDEV_WR_RJT 7 2382 #define M_FW_RDEV_WR_RJT 0x1 2383 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 2384 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 2385 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 2386 2387 #define S_FW_RDEV_WR_REASON 0 2388 #define M_FW_RDEV_WR_REASON 0x7f 2389 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 2390 #define G_FW_RDEV_WR_REASON(x) \ 2391 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 2392 2393 #define S_FW_RDEV_WR_RD_XFER_RDY 7 2394 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 2395 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 2396 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 2397 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 2398 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 2399 2400 #define S_FW_RDEV_WR_WR_XFER_RDY 6 2401 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 2402 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 2403 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 2404 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 2405 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 2406 2407 #define S_FW_RDEV_WR_FC_SP 5 2408 #define M_FW_RDEV_WR_FC_SP 0x1 2409 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 2410 #define G_FW_RDEV_WR_FC_SP(x) \ 2411 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 2412 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 2413 2414 #define S_FW_RDEV_WR_RPORT_TYPE 0 2415 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2416 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2417 #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2418 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2419 2420 #define S_FW_RDEV_WR_VFT 7 2421 #define M_FW_RDEV_WR_VFT 0x1 2422 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2423 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2424 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2425 2426 #define S_FW_RDEV_WR_NPIV 6 2427 #define M_FW_RDEV_WR_NPIV 0x1 2428 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2429 #define G_FW_RDEV_WR_NPIV(x) \ 2430 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2431 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2432 2433 #define S_FW_RDEV_WR_CLASS 4 2434 #define M_FW_RDEV_WR_CLASS 0x3 2435 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2436 #define G_FW_RDEV_WR_CLASS(x) \ 2437 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2438 2439 #define S_FW_RDEV_WR_SEQ_DEL 3 2440 #define M_FW_RDEV_WR_SEQ_DEL 0x1 2441 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2442 #define G_FW_RDEV_WR_SEQ_DEL(x) \ 2443 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2444 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2445 2446 #define S_FW_RDEV_WR_PRIO_PREEMP 2 2447 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2448 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2449 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2450 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2451 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2452 2453 #define S_FW_RDEV_WR_PREF 1 2454 #define M_FW_RDEV_WR_PREF 0x1 2455 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2456 #define G_FW_RDEV_WR_PREF(x) \ 2457 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2458 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2459 2460 #define S_FW_RDEV_WR_QOS 0 2461 #define M_FW_RDEV_WR_QOS 0x1 2462 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2463 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2464 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2465 2466 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2467 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2468 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2469 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2470 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2471 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2472 2473 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2474 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2475 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2476 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2477 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2478 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2479 2480 #define S_FW_RDEV_WR_IMAGE_PAIR 5 2481 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2482 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2483 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2484 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2485 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2486 2487 #define S_FW_RDEV_WR_ACC_RSP_CODE 0 2488 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2489 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2490 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2491 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2492 2493 #define S_FW_RDEV_WR_ENH_DISC 7 2494 #define M_FW_RDEV_WR_ENH_DISC 0x1 2495 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2496 #define G_FW_RDEV_WR_ENH_DISC(x) \ 2497 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2498 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2499 2500 #define S_FW_RDEV_WR_REC 6 2501 #define M_FW_RDEV_WR_REC 0x1 2502 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2503 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2504 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2505 2506 #define S_FW_RDEV_WR_TASK_RETRY_ID 5 2507 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2508 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2509 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2510 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2511 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2512 2513 #define S_FW_RDEV_WR_RETRY 4 2514 #define M_FW_RDEV_WR_RETRY 0x1 2515 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2516 #define G_FW_RDEV_WR_RETRY(x) \ 2517 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2518 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2519 2520 #define S_FW_RDEV_WR_CONF_CMPL 3 2521 #define M_FW_RDEV_WR_CONF_CMPL 0x1 2522 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2523 #define G_FW_RDEV_WR_CONF_CMPL(x) \ 2524 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2525 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2526 2527 #define S_FW_RDEV_WR_DATA_OVLY 2 2528 #define M_FW_RDEV_WR_DATA_OVLY 0x1 2529 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2530 #define G_FW_RDEV_WR_DATA_OVLY(x) \ 2531 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2532 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2533 2534 #define S_FW_RDEV_WR_INI 1 2535 #define M_FW_RDEV_WR_INI 0x1 2536 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2537 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2538 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2539 2540 #define S_FW_RDEV_WR_TGT 0 2541 #define M_FW_RDEV_WR_TGT 0x1 2542 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2543 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2544 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2545 2546 struct fw_foiscsi_node_wr { 2547 __be32 op_to_immdlen; 2548 __be32 flowid_len16; 2549 __u64 cookie; 2550 __u8 subop; 2551 __u8 status; 2552 __u8 alias_len; 2553 __u8 iqn_len; 2554 __be32 node_flowid; 2555 __be16 nodeid; 2556 __be16 login_retry; 2557 __be16 retry_timeout; 2558 __be16 r3; 2559 __u8 iqn[224]; 2560 __u8 alias[224]; 2561 }; 2562 2563 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2564 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2565 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2566 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2567 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2568 2569 struct fw_foiscsi_ctrl_wr { 2570 __be32 op_compl; 2571 __be32 flowid_len16; 2572 __u64 cookie; 2573 __u8 subop; 2574 __u8 status; 2575 __u8 ctrl_state; 2576 __u8 io_state; 2577 __be32 node_id; 2578 __be32 ctrl_id; 2579 __be32 io_id; 2580 struct fw_foiscsi_sess_attr { 2581 __be32 sess_type_to_erl; 2582 __be16 max_conn; 2583 __be16 max_r2t; 2584 __be16 time2wait; 2585 __be16 time2retain; 2586 __be32 max_burst; 2587 __be32 first_burst; 2588 __be32 r1; 2589 } sess_attr; 2590 struct fw_foiscsi_conn_attr { 2591 __be32 hdigest_to_ddp_pgsz; 2592 __be32 max_rcv_dsl; 2593 __be32 ping_tmo; 2594 __be16 dst_port; 2595 __be16 src_port; 2596 union fw_foiscsi_conn_attr_addr { 2597 struct fw_foiscsi_conn_attr_ipv6 { 2598 __be64 dst_addr[2]; 2599 __be64 src_addr[2]; 2600 } ipv6_addr; 2601 struct fw_foiscsi_conn_attr_ipv4 { 2602 __be32 dst_addr; 2603 __be32 src_addr; 2604 } ipv4_addr; 2605 } u; 2606 } conn_attr; 2607 __u8 tgt_name_len; 2608 __u8 r3[7]; 2609 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 2610 }; 2611 2612 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2613 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2614 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2615 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2616 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2617 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2618 2619 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2620 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2621 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2622 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2623 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2624 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2625 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2626 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2627 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2628 2629 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2630 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2631 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2632 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2633 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2634 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2635 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2636 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2637 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2638 2639 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2640 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2641 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2642 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2643 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2644 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2645 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2646 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2647 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2648 2649 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2650 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2651 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2652 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2653 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2654 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2655 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2656 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2657 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2658 2659 #define S_FW_FOISCSI_CTRL_WR_ERL 24 2660 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2661 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2662 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2663 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2664 2665 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2666 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2667 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2668 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2669 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2670 2671 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2672 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2673 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2674 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2675 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2676 2677 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2678 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2679 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2680 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2681 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2682 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2683 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2684 2685 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2686 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2687 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2688 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2689 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2690 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2691 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2692 2693 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2694 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2695 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2696 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2697 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2698 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2699 2700 #define S_FW_FOISCSI_CTRL_WR_IPV6 20 2701 #define M_FW_FOISCSI_CTRL_WR_IPV6 0x1 2702 #define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6) 2703 #define G_FW_FOISCSI_CTRL_WR_IPV6(x) \ 2704 (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6) 2705 #define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U) 2706 2707 struct fw_foiscsi_chap_wr { 2708 __be32 op_compl; 2709 __be32 flowid_len16; 2710 __u64 cookie; 2711 __u8 status; 2712 __u8 id_len; 2713 __u8 sec_len; 2714 __u8 node_type; 2715 __be16 node_id; 2716 __u8 r3[2]; 2717 __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN]; 2718 __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN]; 2719 }; 2720 2721 /****************************************************************************** 2722 * C O i S C S I W O R K R E Q U E S T S 2723 ********************************************/ 2724 2725 enum fw_chnet_addr_type { 2726 FW_CHNET_ADDD_TYPE_NONE = 0, 2727 FW_CHNET_ADDR_TYPE_IPV4, 2728 FW_CHNET_ADDR_TYPE_IPV6, 2729 }; 2730 2731 enum fw_msg_wr_type { 2732 FW_MSG_WR_TYPE_RPL = 0, 2733 FW_MSG_WR_TYPE_ERR, 2734 FW_MSG_WR_TYPE_PLD, 2735 }; 2736 2737 struct fw_coiscsi_tgt_wr { 2738 __be32 op_compl; 2739 __be32 flowid_len16; 2740 __u64 cookie; 2741 __u8 subop; 2742 __u8 status; 2743 __be16 r4; 2744 __be32 flags; 2745 struct fw_coiscsi_tgt_conn_attr { 2746 __be32 in_tid; 2747 __be16 in_port; 2748 __u8 in_type; 2749 __u8 r6; 2750 union fw_coiscsi_tgt_conn_attr_addr { 2751 struct fw_coiscsi_tgt_conn_attr_in_addr { 2752 __be32 addr; 2753 __be32 r7; 2754 __be32 r8[2]; 2755 } in_addr; 2756 struct fw_coiscsi_tgt_conn_attr_in_addr6 { 2757 __be64 addr[2]; 2758 } in_addr6; 2759 } u; 2760 } conn_attr; 2761 }; 2762 2763 struct fw_coiscsi_tgt_xmit_wr { 2764 __be32 op_to_immdlen; 2765 __be32 flowid_len16; 2766 __be64 cookie; 2767 __be16 iq_id; 2768 __be16 r4; 2769 __be32 datasn; 2770 __be32 t_xfer_len; 2771 __be32 flags; 2772 __be32 tag; 2773 __be32 tidx; 2774 __be32 r5[2]; 2775 }; 2776 2777 #define S_FW_COiSCSI_TGT_XMIT_WR_DDGST 23 2778 #define M_FW_COiSCSI_TGT_XMIT_WR_DDGST 0x1 2779 #define V_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \ 2780 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDGST) 2781 #define G_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \ 2782 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDGST) & M_FW_COiSCSI_TGT_XMIT_WR_DDGST) 2783 #define F_FW_COiSCSI_TGT_XMIT_WR_DDGST V_FW_COiSCSI_TGT_XMIT_WR_DDGST(1U) 2784 2785 #define S_FW_COiSCSI_TGT_XMIT_WR_HDGST 22 2786 #define M_FW_COiSCSI_TGT_XMIT_WR_HDGST 0x1 2787 #define V_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \ 2788 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_HDGST) 2789 #define G_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \ 2790 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_HDGST) & M_FW_COiSCSI_TGT_XMIT_WR_HDGST) 2791 #define F_FW_COiSCSI_TGT_XMIT_WR_HDGST V_FW_COiSCSI_TGT_XMIT_WR_HDGST(1U) 2792 2793 #define S_FW_COiSCSI_TGT_XMIT_WR_DDP 20 2794 #define M_FW_COiSCSI_TGT_XMIT_WR_DDP 0x1 2795 #define V_FW_COiSCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDP) 2796 #define G_FW_COiSCSI_TGT_XMIT_WR_DDP(x) \ 2797 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDP) & M_FW_COiSCSI_TGT_XMIT_WR_DDP) 2798 #define F_FW_COiSCSI_TGT_XMIT_WR_DDP V_FW_COiSCSI_TGT_XMIT_WR_DDP(1U) 2799 2800 #define S_FW_COiSCSI_TGT_XMIT_WR_ABORT 19 2801 #define M_FW_COiSCSI_TGT_XMIT_WR_ABORT 0x1 2802 #define V_FW_COiSCSI_TGT_XMIT_WR_ABORT(x) \ 2803 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_ABORT) 2804 #define G_FW_COiSCSI_TGT_XMIT_WR_ABORT(x) \ 2805 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_ABORT) & M_FW_COiSCSI_TGT_XMIT_WR_ABORT) 2806 #define F_FW_COiSCSI_TGT_XMIT_WR_ABORT V_FW_COiSCSI_TGT_XMIT_WR_ABORT(1U) 2807 2808 #define S_FW_COiSCSI_TGT_XMIT_WR_FINAL 18 2809 #define M_FW_COiSCSI_TGT_XMIT_WR_FINAL 0x1 2810 #define V_FW_COiSCSI_TGT_XMIT_WR_FINAL(x) \ 2811 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_FINAL) 2812 #define G_FW_COiSCSI_TGT_XMIT_WR_FINAL(x) \ 2813 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_FINAL) & M_FW_COiSCSI_TGT_XMIT_WR_FINAL) 2814 #define F_FW_COiSCSI_TGT_XMIT_WR_FINAL V_FW_COiSCSI_TGT_XMIT_WR_FINAL(1U) 2815 2816 #define S_FW_COiSCSI_TGT_XMIT_WR_PADLEN 16 2817 #define M_FW_COiSCSI_TGT_XMIT_WR_PADLEN 0x3 2818 #define V_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x) \ 2819 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) 2820 #define G_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x) \ 2821 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) & \ 2822 M_FW_COiSCSI_TGT_XMIT_WR_PADLEN) 2823 2824 #define S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0 2825 #define M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0xff 2826 #define V_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2827 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) 2828 #define G_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2829 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) & \ 2830 M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) 2831 2832 struct fw_isns_wr { 2833 __be32 op_compl; 2834 __be32 flowid_len16; 2835 __u64 cookie; 2836 __u8 subop; 2837 __u8 status; 2838 __be16 iq_id; 2839 __be32 r4; 2840 struct fw_tcp_conn_attr { 2841 __be32 in_tid; 2842 __be16 in_port; 2843 __u8 in_type; 2844 __u8 r6; 2845 union fw_tcp_conn_attr_addr { 2846 struct fw_tcp_conn_attr_in_addr { 2847 __be32 addr; 2848 __be32 r7; 2849 __be32 r8[2]; 2850 } in_addr; 2851 struct fw_tcp_conn_attr_in_addr6 { 2852 __be64 addr[2]; 2853 } in_addr6; 2854 } u; 2855 } conn_attr; 2856 }; 2857 2858 struct fw_isns_xmit_wr { 2859 __be32 op_to_immdlen; 2860 __be32 flowid_len16; 2861 __be64 cookie; 2862 __be16 iq_id; 2863 __be16 r4; 2864 __be32 xfer_len; 2865 __be64 r5; 2866 }; 2867 2868 #define S_FW_ISNS_XMIT_WR_IMMDLEN 0 2869 #define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff 2870 #define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN) 2871 #define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \ 2872 (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN) 2873 2874 /****************************************************************************** 2875 * F O F C O E W O R K R E Q U E S T s 2876 *******************************************/ 2877 2878 struct fw_fcoe_els_ct_wr { 2879 __be32 op_immdlen; 2880 __be32 flowid_len16; 2881 __be64 cookie; 2882 __be16 iqid; 2883 __u8 tmo_val; 2884 __u8 els_ct_type; 2885 __u8 ctl_pri; 2886 __u8 cp_en_class; 2887 __be16 xfer_cnt; 2888 __u8 fl_to_sp; 2889 __u8 l_id[3]; 2890 __u8 r5; 2891 __u8 r_id[3]; 2892 __be64 rsp_dmaaddr; 2893 __be32 rsp_dmalen; 2894 __be32 r6; 2895 }; 2896 2897 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 2898 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 2899 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 2900 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 2901 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 2902 2903 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 2904 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 2905 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 2906 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 2907 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 2908 2909 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 2910 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 2911 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 2912 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 2913 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 2914 2915 #define S_FW_FCOE_ELS_CT_WR_LEN16 0 2916 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 2917 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 2918 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 2919 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 2920 2921 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 2922 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 2923 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 2924 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 2925 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 2926 2927 #define S_FW_FCOE_ELS_CT_WR_CLASS 4 2928 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 2929 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 2930 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 2931 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 2932 2933 #define S_FW_FCOE_ELS_CT_WR_FL 2 2934 #define M_FW_FCOE_ELS_CT_WR_FL 0x1 2935 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 2936 #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 2937 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 2938 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 2939 2940 #define S_FW_FCOE_ELS_CT_WR_NPIV 1 2941 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 2942 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 2943 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 2944 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 2945 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 2946 2947 #define S_FW_FCOE_ELS_CT_WR_SP 0 2948 #define M_FW_FCOE_ELS_CT_WR_SP 0x1 2949 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 2950 #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 2951 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 2952 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 2953 2954 /****************************************************************************** 2955 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 2956 *****************************************************************************/ 2957 2958 struct fw_scsi_write_wr { 2959 __be32 op_immdlen; 2960 __be32 flowid_len16; 2961 __be64 cookie; 2962 __be16 iqid; 2963 __u8 tmo_val; 2964 __u8 use_xfer_cnt; 2965 union fw_scsi_write_priv { 2966 struct fcoe_write_priv { 2967 __u8 ctl_pri; 2968 __u8 cp_en_class; 2969 __u8 r3_lo[2]; 2970 } fcoe; 2971 struct iscsi_write_priv { 2972 __u8 r3[4]; 2973 } iscsi; 2974 } u; 2975 __be32 xfer_cnt; 2976 __be32 ini_xfer_cnt; 2977 __be64 rsp_dmaaddr; 2978 __be32 rsp_dmalen; 2979 __be32 r4; 2980 }; 2981 2982 #define S_FW_SCSI_WRITE_WR_OPCODE 24 2983 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 2984 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 2985 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 2986 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 2987 2988 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 2989 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 2990 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 2991 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 2992 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 2993 2994 #define S_FW_SCSI_WRITE_WR_FLOWID 8 2995 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 2996 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 2997 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 2998 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 2999 3000 #define S_FW_SCSI_WRITE_WR_LEN16 0 3001 #define M_FW_SCSI_WRITE_WR_LEN16 0xff 3002 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 3003 #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 3004 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 3005 3006 #define S_FW_SCSI_WRITE_WR_CP_EN 6 3007 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 3008 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 3009 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 3010 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 3011 3012 #define S_FW_SCSI_WRITE_WR_CLASS 4 3013 #define M_FW_SCSI_WRITE_WR_CLASS 0x3 3014 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 3015 #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 3016 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 3017 3018 struct fw_scsi_read_wr { 3019 __be32 op_immdlen; 3020 __be32 flowid_len16; 3021 __be64 cookie; 3022 __be16 iqid; 3023 __u8 tmo_val; 3024 __u8 use_xfer_cnt; 3025 union fw_scsi_read_priv { 3026 struct fcoe_read_priv { 3027 __u8 ctl_pri; 3028 __u8 cp_en_class; 3029 __u8 r3_lo[2]; 3030 } fcoe; 3031 struct iscsi_read_priv { 3032 __u8 r3[4]; 3033 } iscsi; 3034 } u; 3035 __be32 xfer_cnt; 3036 __be32 ini_xfer_cnt; 3037 __be64 rsp_dmaaddr; 3038 __be32 rsp_dmalen; 3039 __be32 r4; 3040 }; 3041 3042 #define S_FW_SCSI_READ_WR_OPCODE 24 3043 #define M_FW_SCSI_READ_WR_OPCODE 0xff 3044 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 3045 #define G_FW_SCSI_READ_WR_OPCODE(x) \ 3046 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 3047 3048 #define S_FW_SCSI_READ_WR_IMMDLEN 0 3049 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 3050 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 3051 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 3052 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 3053 3054 #define S_FW_SCSI_READ_WR_FLOWID 8 3055 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 3056 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 3057 #define G_FW_SCSI_READ_WR_FLOWID(x) \ 3058 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 3059 3060 #define S_FW_SCSI_READ_WR_LEN16 0 3061 #define M_FW_SCSI_READ_WR_LEN16 0xff 3062 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 3063 #define G_FW_SCSI_READ_WR_LEN16(x) \ 3064 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 3065 3066 #define S_FW_SCSI_READ_WR_CP_EN 6 3067 #define M_FW_SCSI_READ_WR_CP_EN 0x3 3068 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 3069 #define G_FW_SCSI_READ_WR_CP_EN(x) \ 3070 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 3071 3072 #define S_FW_SCSI_READ_WR_CLASS 4 3073 #define M_FW_SCSI_READ_WR_CLASS 0x3 3074 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 3075 #define G_FW_SCSI_READ_WR_CLASS(x) \ 3076 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 3077 3078 struct fw_scsi_cmd_wr { 3079 __be32 op_immdlen; 3080 __be32 flowid_len16; 3081 __be64 cookie; 3082 __be16 iqid; 3083 __u8 tmo_val; 3084 __u8 r3; 3085 union fw_scsi_cmd_priv { 3086 struct fcoe_cmd_priv { 3087 __u8 ctl_pri; 3088 __u8 cp_en_class; 3089 __u8 r4_lo[2]; 3090 } fcoe; 3091 struct iscsi_cmd_priv { 3092 __u8 r4[4]; 3093 } iscsi; 3094 } u; 3095 __u8 r5[8]; 3096 __be64 rsp_dmaaddr; 3097 __be32 rsp_dmalen; 3098 __be32 r6; 3099 }; 3100 3101 #define S_FW_SCSI_CMD_WR_OPCODE 24 3102 #define M_FW_SCSI_CMD_WR_OPCODE 0xff 3103 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 3104 #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 3105 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 3106 3107 #define S_FW_SCSI_CMD_WR_IMMDLEN 0 3108 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 3109 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 3110 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 3111 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 3112 3113 #define S_FW_SCSI_CMD_WR_FLOWID 8 3114 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 3115 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 3116 #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 3117 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 3118 3119 #define S_FW_SCSI_CMD_WR_LEN16 0 3120 #define M_FW_SCSI_CMD_WR_LEN16 0xff 3121 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 3122 #define G_FW_SCSI_CMD_WR_LEN16(x) \ 3123 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 3124 3125 #define S_FW_SCSI_CMD_WR_CP_EN 6 3126 #define M_FW_SCSI_CMD_WR_CP_EN 0x3 3127 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 3128 #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 3129 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 3130 3131 #define S_FW_SCSI_CMD_WR_CLASS 4 3132 #define M_FW_SCSI_CMD_WR_CLASS 0x3 3133 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 3134 #define G_FW_SCSI_CMD_WR_CLASS(x) \ 3135 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 3136 3137 struct fw_scsi_abrt_cls_wr { 3138 __be32 op_immdlen; 3139 __be32 flowid_len16; 3140 __be64 cookie; 3141 __be16 iqid; 3142 __u8 tmo_val; 3143 __u8 sub_opcode_to_chk_all_io; 3144 __u8 r3[4]; 3145 __be64 t_cookie; 3146 }; 3147 3148 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 3149 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 3150 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 3151 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 3152 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 3153 3154 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 3155 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 3156 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3157 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3158 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3159 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3160 3161 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 3162 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 3163 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 3164 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 3165 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 3166 3167 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 3168 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 3169 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 3170 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 3171 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 3172 3173 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 3174 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 3175 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3176 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3177 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3178 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 3179 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3180 3181 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 3182 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 3183 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 3184 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 3185 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 3186 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 3187 3188 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 3189 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 3190 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3191 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3192 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3193 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 3194 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3195 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 3196 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 3197 3198 struct fw_scsi_tgt_acc_wr { 3199 __be32 op_immdlen; 3200 __be32 flowid_len16; 3201 __be64 cookie; 3202 __be16 iqid; 3203 __u8 r3; 3204 __u8 use_burst_len; 3205 union fw_scsi_tgt_acc_priv { 3206 struct fcoe_tgt_acc_priv { 3207 __u8 ctl_pri; 3208 __u8 cp_en_class; 3209 __u8 r4_lo[2]; 3210 } fcoe; 3211 struct iscsi_tgt_acc_priv { 3212 __u8 r4[4]; 3213 } iscsi; 3214 } u; 3215 __be32 burst_len; 3216 __be32 rel_off; 3217 __be64 r5; 3218 __be32 r6; 3219 __be32 tot_xfer_len; 3220 }; 3221 3222 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 3223 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 3224 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 3225 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 3226 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 3227 3228 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 3229 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 3230 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3231 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 3232 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3233 3234 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 3235 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 3236 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 3237 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 3238 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 3239 3240 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 3241 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 3242 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 3243 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 3244 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 3245 3246 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 3247 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 3248 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 3249 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 3250 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 3251 3252 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 3253 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 3254 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 3255 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 3256 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 3257 3258 struct fw_scsi_tgt_xmit_wr { 3259 __be32 op_immdlen; 3260 __be32 flowid_len16; 3261 __be64 cookie; 3262 __be16 iqid; 3263 __u8 auto_rsp; 3264 __u8 use_xfer_cnt; 3265 union fw_scsi_tgt_xmit_priv { 3266 struct fcoe_tgt_xmit_priv { 3267 __u8 ctl_pri; 3268 __u8 cp_en_class; 3269 __u8 r3_lo[2]; 3270 } fcoe; 3271 struct iscsi_tgt_xmit_priv { 3272 __u8 r3[4]; 3273 } iscsi; 3274 } u; 3275 __be32 xfer_cnt; 3276 __be32 r4; 3277 __be64 r5; 3278 __be32 r6; 3279 __be32 tot_xfer_len; 3280 }; 3281 3282 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 3283 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 3284 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 3285 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 3286 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 3287 3288 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 3289 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 3290 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3291 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3292 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3293 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3294 3295 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 3296 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 3297 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 3298 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 3299 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 3300 3301 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 3302 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 3303 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 3304 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 3305 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 3306 3307 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 3308 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 3309 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 3310 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 3311 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 3312 3313 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 3314 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 3315 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 3316 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 3317 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 3318 3319 struct fw_scsi_tgt_rsp_wr { 3320 __be32 op_immdlen; 3321 __be32 flowid_len16; 3322 __be64 cookie; 3323 __be16 iqid; 3324 __u8 r3[2]; 3325 union fw_scsi_tgt_rsp_priv { 3326 struct fcoe_tgt_rsp_priv { 3327 __u8 ctl_pri; 3328 __u8 cp_en_class; 3329 __u8 r4_lo[2]; 3330 } fcoe; 3331 struct iscsi_tgt_rsp_priv { 3332 __u8 r4[4]; 3333 } iscsi; 3334 } u; 3335 __u8 r5[8]; 3336 }; 3337 3338 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 3339 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 3340 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 3341 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 3342 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 3343 3344 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 3345 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 3346 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3347 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 3348 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3349 3350 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 3351 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 3352 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 3353 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 3354 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 3355 3356 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 3357 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 3358 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 3359 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 3360 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 3361 3362 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 3363 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 3364 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 3365 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 3366 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 3367 3368 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 3369 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 3370 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 3371 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 3372 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 3373 3374 struct fw_pofcoe_tcb_wr { 3375 __be32 op_compl; 3376 __be32 equiq_to_len16; 3377 __be32 r4; 3378 __be32 xfer_len; 3379 __be32 tid_to_port; 3380 __be16 x_id; 3381 __be16 vlan_id; 3382 __be64 cookie; 3383 __be32 s_id; 3384 __be32 d_id; 3385 __be32 tag; 3386 __be16 r6; 3387 __be16 iqid; 3388 }; 3389 3390 #define S_FW_POFCOE_TCB_WR_TID 12 3391 #define M_FW_POFCOE_TCB_WR_TID 0xfffff 3392 #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 3393 #define G_FW_POFCOE_TCB_WR_TID(x) \ 3394 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 3395 3396 #define S_FW_POFCOE_TCB_WR_ALLOC 4 3397 #define M_FW_POFCOE_TCB_WR_ALLOC 0x1 3398 #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 3399 #define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 3400 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 3401 #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 3402 3403 #define S_FW_POFCOE_TCB_WR_FREE 3 3404 #define M_FW_POFCOE_TCB_WR_FREE 0x1 3405 #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 3406 #define G_FW_POFCOE_TCB_WR_FREE(x) \ 3407 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 3408 #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 3409 3410 #define S_FW_POFCOE_TCB_WR_PORT 0 3411 #define M_FW_POFCOE_TCB_WR_PORT 0x7 3412 #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 3413 #define G_FW_POFCOE_TCB_WR_PORT(x) \ 3414 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 3415 3416 struct fw_pofcoe_ulptx_wr { 3417 __be32 op_pkd; 3418 __be32 equiq_to_len16; 3419 __u64 cookie; 3420 }; 3421 3422 /******************************************************************* 3423 * T10 DIF related definition 3424 *******************************************************************/ 3425 struct fw_tx_pi_header { 3426 __be16 op_to_inline; 3427 __u8 pi_interval_tag_type; 3428 __u8 num_pi; 3429 __be32 pi_start4_pi_end4; 3430 __u8 tag_gen_enabled_pkd; 3431 __u8 num_pi_dsg; 3432 __be16 app_tag; 3433 __be32 ref_tag; 3434 }; 3435 3436 #define S_FW_TX_PI_HEADER_OP 8 3437 #define M_FW_TX_PI_HEADER_OP 0xff 3438 #define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP) 3439 #define G_FW_TX_PI_HEADER_OP(x) \ 3440 (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP) 3441 3442 #define S_FW_TX_PI_HEADER_ULPTXMORE 7 3443 #define M_FW_TX_PI_HEADER_ULPTXMORE 0x1 3444 #define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE) 3445 #define G_FW_TX_PI_HEADER_ULPTXMORE(x) \ 3446 (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE) 3447 #define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U) 3448 3449 #define S_FW_TX_PI_HEADER_PI_CONTROL 4 3450 #define M_FW_TX_PI_HEADER_PI_CONTROL 0x7 3451 #define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL) 3452 #define G_FW_TX_PI_HEADER_PI_CONTROL(x) \ 3453 (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL) 3454 3455 #define S_FW_TX_PI_HEADER_GUARD_TYPE 2 3456 #define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1 3457 #define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE) 3458 #define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \ 3459 (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE) 3460 #define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U) 3461 3462 #define S_FW_TX_PI_HEADER_VALIDATE 1 3463 #define M_FW_TX_PI_HEADER_VALIDATE 0x1 3464 #define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE) 3465 #define G_FW_TX_PI_HEADER_VALIDATE(x) \ 3466 (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE) 3467 #define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U) 3468 3469 #define S_FW_TX_PI_HEADER_INLINE 0 3470 #define M_FW_TX_PI_HEADER_INLINE 0x1 3471 #define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE) 3472 #define G_FW_TX_PI_HEADER_INLINE(x) \ 3473 (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE) 3474 #define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U) 3475 3476 #define S_FW_TX_PI_HEADER_PI_INTERVAL 7 3477 #define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1 3478 #define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3479 ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL) 3480 #define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3481 (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL) 3482 #define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U) 3483 3484 #define S_FW_TX_PI_HEADER_TAG_TYPE 5 3485 #define M_FW_TX_PI_HEADER_TAG_TYPE 0x3 3486 #define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE) 3487 #define G_FW_TX_PI_HEADER_TAG_TYPE(x) \ 3488 (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE) 3489 3490 #define S_FW_TX_PI_HEADER_PI_START4 22 3491 #define M_FW_TX_PI_HEADER_PI_START4 0x3ff 3492 #define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4) 3493 #define G_FW_TX_PI_HEADER_PI_START4(x) \ 3494 (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4) 3495 3496 #define S_FW_TX_PI_HEADER_PI_END4 0 3497 #define M_FW_TX_PI_HEADER_PI_END4 0x3fffff 3498 #define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4) 3499 #define G_FW_TX_PI_HEADER_PI_END4(x) \ 3500 (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4) 3501 3502 #define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6 3503 #define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3 3504 #define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3505 ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3506 #define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3507 (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \ 3508 M_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3509 3510 enum fw_pi_error_type { 3511 FW_PI_ERROR_GUARD_CHECK_FAILED = 0, 3512 }; 3513 3514 struct fw_pi_error { 3515 __be32 err_type_pkd; 3516 __be32 flowid_len16; 3517 __be16 r2; 3518 __be16 app_tag; 3519 __be32 ref_tag; 3520 __be32 pisc[4]; 3521 }; 3522 3523 #define S_FW_PI_ERROR_ERR_TYPE 24 3524 #define M_FW_PI_ERROR_ERR_TYPE 0xff 3525 #define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE) 3526 #define G_FW_PI_ERROR_ERR_TYPE(x) \ 3527 (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE) 3528 3529 struct fw_tlstx_data_wr { 3530 __be32 op_to_immdlen; 3531 __be32 flowid_len16; 3532 __be32 plen; 3533 __be32 lsodisable_to_flags; 3534 __be32 r5; 3535 __be32 ctxloc_to_exp; 3536 __be16 mfs; 3537 __be16 adjustedplen_pkd; 3538 __be16 expinplenmax_pkd; 3539 __u8 pdusinplenmax_pkd; 3540 __u8 r10; 3541 }; 3542 3543 #define S_FW_TLSTX_DATA_WR_OPCODE 24 3544 #define M_FW_TLSTX_DATA_WR_OPCODE 0xff 3545 #define V_FW_TLSTX_DATA_WR_OPCODE(x) ((x) << S_FW_TLSTX_DATA_WR_OPCODE) 3546 #define G_FW_TLSTX_DATA_WR_OPCODE(x) \ 3547 (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE) 3548 3549 #define S_FW_TLSTX_DATA_WR_COMPL 21 3550 #define M_FW_TLSTX_DATA_WR_COMPL 0x1 3551 #define V_FW_TLSTX_DATA_WR_COMPL(x) ((x) << S_FW_TLSTX_DATA_WR_COMPL) 3552 #define G_FW_TLSTX_DATA_WR_COMPL(x) \ 3553 (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL) 3554 #define F_FW_TLSTX_DATA_WR_COMPL V_FW_TLSTX_DATA_WR_COMPL(1U) 3555 3556 #define S_FW_TLSTX_DATA_WR_IMMDLEN 0 3557 #define M_FW_TLSTX_DATA_WR_IMMDLEN 0xff 3558 #define V_FW_TLSTX_DATA_WR_IMMDLEN(x) ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN) 3559 #define G_FW_TLSTX_DATA_WR_IMMDLEN(x) \ 3560 (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN) 3561 3562 #define S_FW_TLSTX_DATA_WR_FLOWID 8 3563 #define M_FW_TLSTX_DATA_WR_FLOWID 0xfffff 3564 #define V_FW_TLSTX_DATA_WR_FLOWID(x) ((x) << S_FW_TLSTX_DATA_WR_FLOWID) 3565 #define G_FW_TLSTX_DATA_WR_FLOWID(x) \ 3566 (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID) 3567 3568 #define S_FW_TLSTX_DATA_WR_LEN16 0 3569 #define M_FW_TLSTX_DATA_WR_LEN16 0xff 3570 #define V_FW_TLSTX_DATA_WR_LEN16(x) ((x) << S_FW_TLSTX_DATA_WR_LEN16) 3571 #define G_FW_TLSTX_DATA_WR_LEN16(x) \ 3572 (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16) 3573 3574 #define S_FW_TLSTX_DATA_WR_LSODISABLE 31 3575 #define M_FW_TLSTX_DATA_WR_LSODISABLE 0x1 3576 #define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 3577 ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE) 3578 #define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 3579 (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE) 3580 #define F_FW_TLSTX_DATA_WR_LSODISABLE V_FW_TLSTX_DATA_WR_LSODISABLE(1U) 3581 3582 #define S_FW_TLSTX_DATA_WR_ALIGNPLD 30 3583 #define M_FW_TLSTX_DATA_WR_ALIGNPLD 0x1 3584 #define V_FW_TLSTX_DATA_WR_ALIGNPLD(x) ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD) 3585 #define G_FW_TLSTX_DATA_WR_ALIGNPLD(x) \ 3586 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD) 3587 #define F_FW_TLSTX_DATA_WR_ALIGNPLD V_FW_TLSTX_DATA_WR_ALIGNPLD(1U) 3588 3589 #define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29 3590 #define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1 3591 #define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 3592 ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 3593 #define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 3594 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \ 3595 M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 3596 #define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U) 3597 3598 #define S_FW_TLSTX_DATA_WR_FLAGS 0 3599 #define M_FW_TLSTX_DATA_WR_FLAGS 0xfffffff 3600 #define V_FW_TLSTX_DATA_WR_FLAGS(x) ((x) << S_FW_TLSTX_DATA_WR_FLAGS) 3601 #define G_FW_TLSTX_DATA_WR_FLAGS(x) \ 3602 (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS) 3603 3604 #define S_FW_TLSTX_DATA_WR_CTXLOC 30 3605 #define M_FW_TLSTX_DATA_WR_CTXLOC 0x3 3606 #define V_FW_TLSTX_DATA_WR_CTXLOC(x) ((x) << S_FW_TLSTX_DATA_WR_CTXLOC) 3607 #define G_FW_TLSTX_DATA_WR_CTXLOC(x) \ 3608 (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC) 3609 3610 #define S_FW_TLSTX_DATA_WR_IVDSGL 29 3611 #define M_FW_TLSTX_DATA_WR_IVDSGL 0x1 3612 #define V_FW_TLSTX_DATA_WR_IVDSGL(x) ((x) << S_FW_TLSTX_DATA_WR_IVDSGL) 3613 #define G_FW_TLSTX_DATA_WR_IVDSGL(x) \ 3614 (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL) 3615 #define F_FW_TLSTX_DATA_WR_IVDSGL V_FW_TLSTX_DATA_WR_IVDSGL(1U) 3616 3617 #define S_FW_TLSTX_DATA_WR_KEYSIZE 24 3618 #define M_FW_TLSTX_DATA_WR_KEYSIZE 0x1f 3619 #define V_FW_TLSTX_DATA_WR_KEYSIZE(x) ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE) 3620 #define G_FW_TLSTX_DATA_WR_KEYSIZE(x) \ 3621 (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE) 3622 3623 #define S_FW_TLSTX_DATA_WR_NUMIVS 14 3624 #define M_FW_TLSTX_DATA_WR_NUMIVS 0xff 3625 #define V_FW_TLSTX_DATA_WR_NUMIVS(x) ((x) << S_FW_TLSTX_DATA_WR_NUMIVS) 3626 #define G_FW_TLSTX_DATA_WR_NUMIVS(x) \ 3627 (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS) 3628 3629 #define S_FW_TLSTX_DATA_WR_EXP 0 3630 #define M_FW_TLSTX_DATA_WR_EXP 0x3fff 3631 #define V_FW_TLSTX_DATA_WR_EXP(x) ((x) << S_FW_TLSTX_DATA_WR_EXP) 3632 #define G_FW_TLSTX_DATA_WR_EXP(x) \ 3633 (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP) 3634 3635 #define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1 3636 #define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff 3637 #define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 3638 ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 3639 #define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 3640 (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \ 3641 M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 3642 3643 #define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4 3644 #define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff 3645 #define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 3646 ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX) 3647 #define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 3648 (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \ 3649 M_FW_TLSTX_DATA_WR_EXPINPLENMAX) 3650 3651 #define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2 3652 #define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f 3653 #define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 3654 ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 3655 #define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 3656 (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \ 3657 M_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 3658 3659 struct fw_tls_keyctx_tx_wr { 3660 __be32 op_to_compl; 3661 __be32 flowid_len16; 3662 union fw_key_ctx { 3663 struct fw_tx_keyctx_hdr { 3664 __u8 ctxlen; 3665 __u8 r2; 3666 __be16 dualck_to_txvalid; 3667 __u8 txsalt[4]; 3668 __be64 r5; 3669 } txhdr; 3670 struct fw_rx_keyctx_hdr { 3671 __u8 flitcnt_hmacctrl; 3672 __u8 protover_ciphmode; 3673 __u8 authmode_to_rxvalid; 3674 __u8 ivpresent_to_rxmk_size; 3675 __u8 rxsalt[4]; 3676 __be64 ivinsert_to_authinsrt; 3677 } rxhdr; 3678 struct fw_keyctx_clear { 3679 __be32 tx_key; 3680 __be32 rx_key; 3681 } kctx_clr; 3682 } u; 3683 struct keys { 3684 __u8 edkey[32]; 3685 __u8 ipad[64]; 3686 __u8 opad[64]; 3687 } keys; 3688 __u8 reneg_to_write_rx; 3689 __u8 protocol; 3690 __be16 mfs; 3691 __be32 ftid; 3692 }; 3693 3694 #define S_FW_TLS_KEYCTX_TX_WR_OPCODE 24 3695 #define M_FW_TLS_KEYCTX_TX_WR_OPCODE 0xff 3696 #define V_FW_TLS_KEYCTX_TX_WR_OPCODE(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_OPCODE) 3697 #define G_FW_TLS_KEYCTX_TX_WR_OPCODE(x) \ 3698 (((x) >> S_FW_TLS_KEYCTX_TX_WR_OPCODE) & M_FW_TLS_KEYCTX_TX_WR_OPCODE) 3699 3700 #define S_FW_TLS_KEYCTX_TX_WR_ATOMIC 23 3701 #define M_FW_TLS_KEYCTX_TX_WR_ATOMIC 0x1 3702 #define V_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_ATOMIC) 3703 #define G_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) \ 3704 (((x) >> S_FW_TLS_KEYCTX_TX_WR_ATOMIC) & M_FW_TLS_KEYCTX_TX_WR_ATOMIC) 3705 #define F_FW_TLS_KEYCTX_TX_WR_ATOMIC V_FW_TLS_KEYCTX_TX_WR_ATOMIC(1U) 3706 3707 #define S_FW_TLS_KEYCTX_TX_WR_FLUSH 22 3708 #define M_FW_TLS_KEYCTX_TX_WR_FLUSH 0x1 3709 #define V_FW_TLS_KEYCTX_TX_WR_FLUSH(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_FLUSH) 3710 #define G_FW_TLS_KEYCTX_TX_WR_FLUSH(x) \ 3711 (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLUSH) & M_FW_TLS_KEYCTX_TX_WR_FLUSH) 3712 #define F_FW_TLS_KEYCTX_TX_WR_FLUSH V_FW_TLS_KEYCTX_TX_WR_FLUSH(1U) 3713 3714 #define S_FW_TLS_KEYCTX_TX_WR_COMPL 21 3715 #define M_FW_TLS_KEYCTX_TX_WR_COMPL 0x1 3716 #define V_FW_TLS_KEYCTX_TX_WR_COMPL(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_COMPL) 3717 #define G_FW_TLS_KEYCTX_TX_WR_COMPL(x) \ 3718 (((x) >> S_FW_TLS_KEYCTX_TX_WR_COMPL) & M_FW_TLS_KEYCTX_TX_WR_COMPL) 3719 #define F_FW_TLS_KEYCTX_TX_WR_COMPL V_FW_TLS_KEYCTX_TX_WR_COMPL(1U) 3720 3721 #define S_FW_TLS_KEYCTX_TX_WR_FLOWID 8 3722 #define M_FW_TLS_KEYCTX_TX_WR_FLOWID 0xfffff 3723 #define V_FW_TLS_KEYCTX_TX_WR_FLOWID(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_FLOWID) 3724 #define G_FW_TLS_KEYCTX_TX_WR_FLOWID(x) \ 3725 (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLOWID) & M_FW_TLS_KEYCTX_TX_WR_FLOWID) 3726 3727 #define S_FW_TLS_KEYCTX_TX_WR_LEN16 0 3728 #define M_FW_TLS_KEYCTX_TX_WR_LEN16 0xff 3729 #define V_FW_TLS_KEYCTX_TX_WR_LEN16(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_LEN16) 3730 #define G_FW_TLS_KEYCTX_TX_WR_LEN16(x) \ 3731 (((x) >> S_FW_TLS_KEYCTX_TX_WR_LEN16) & M_FW_TLS_KEYCTX_TX_WR_LEN16) 3732 3733 #define S_FW_TLS_KEYCTX_TX_WR_DUALCK 12 3734 #define M_FW_TLS_KEYCTX_TX_WR_DUALCK 0x1 3735 #define V_FW_TLS_KEYCTX_TX_WR_DUALCK(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_DUALCK) 3736 #define G_FW_TLS_KEYCTX_TX_WR_DUALCK(x) \ 3737 (((x) >> S_FW_TLS_KEYCTX_TX_WR_DUALCK) & M_FW_TLS_KEYCTX_TX_WR_DUALCK) 3738 #define F_FW_TLS_KEYCTX_TX_WR_DUALCK V_FW_TLS_KEYCTX_TX_WR_DUALCK(1U) 3739 3740 #define S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 11 3741 #define M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 0x1 3742 #define V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \ 3743 ((x) << S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) 3744 #define G_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \ 3745 (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) & \ 3746 M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) 3747 #define F_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT \ 3748 V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(1U) 3749 3750 #define S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 10 3751 #define M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 0x1 3752 #define V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \ 3753 ((x) << S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) 3754 #define G_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \ 3755 (((x) >> S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) & \ 3756 M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) 3757 #define F_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT \ 3758 V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(1U) 3759 3760 #define S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 6 3761 #define M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 0xf 3762 #define V_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \ 3763 ((x) << S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) 3764 #define G_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \ 3765 (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) & \ 3766 M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) 3767 3768 #define S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 2 3769 #define M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 0xf 3770 #define V_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \ 3771 ((x) << S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) 3772 #define G_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \ 3773 (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) & \ 3774 M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) 3775 3776 #define S_FW_TLS_KEYCTX_TX_WR_TXVALID 0 3777 #define M_FW_TLS_KEYCTX_TX_WR_TXVALID 0x1 3778 #define V_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \ 3779 ((x) << S_FW_TLS_KEYCTX_TX_WR_TXVALID) 3780 #define G_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \ 3781 (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXVALID) & M_FW_TLS_KEYCTX_TX_WR_TXVALID) 3782 #define F_FW_TLS_KEYCTX_TX_WR_TXVALID V_FW_TLS_KEYCTX_TX_WR_TXVALID(1U) 3783 3784 #define S_FW_TLS_KEYCTX_TX_WR_FLITCNT 3 3785 #define M_FW_TLS_KEYCTX_TX_WR_FLITCNT 0x1f 3786 #define V_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \ 3787 ((x) << S_FW_TLS_KEYCTX_TX_WR_FLITCNT) 3788 #define G_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \ 3789 (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLITCNT) & M_FW_TLS_KEYCTX_TX_WR_FLITCNT) 3790 3791 #define S_FW_TLS_KEYCTX_TX_WR_HMACCTRL 0 3792 #define M_FW_TLS_KEYCTX_TX_WR_HMACCTRL 0x7 3793 #define V_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \ 3794 ((x) << S_FW_TLS_KEYCTX_TX_WR_HMACCTRL) 3795 #define G_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \ 3796 (((x) >> S_FW_TLS_KEYCTX_TX_WR_HMACCTRL) & M_FW_TLS_KEYCTX_TX_WR_HMACCTRL) 3797 3798 #define S_FW_TLS_KEYCTX_TX_WR_PROTOVER 4 3799 #define M_FW_TLS_KEYCTX_TX_WR_PROTOVER 0xf 3800 #define V_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \ 3801 ((x) << S_FW_TLS_KEYCTX_TX_WR_PROTOVER) 3802 #define G_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \ 3803 (((x) >> S_FW_TLS_KEYCTX_TX_WR_PROTOVER) & M_FW_TLS_KEYCTX_TX_WR_PROTOVER) 3804 3805 #define S_FW_TLS_KEYCTX_TX_WR_CIPHMODE 0 3806 #define M_FW_TLS_KEYCTX_TX_WR_CIPHMODE 0xf 3807 #define V_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \ 3808 ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHMODE) 3809 #define G_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \ 3810 (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHMODE) & M_FW_TLS_KEYCTX_TX_WR_CIPHMODE) 3811 3812 #define S_FW_TLS_KEYCTX_TX_WR_AUTHMODE 4 3813 #define M_FW_TLS_KEYCTX_TX_WR_AUTHMODE 0xf 3814 #define V_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \ 3815 ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHMODE) 3816 #define G_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \ 3817 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHMODE) & M_FW_TLS_KEYCTX_TX_WR_AUTHMODE) 3818 3819 #define S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 3 3820 #define M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 0x1 3821 #define V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \ 3822 ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) 3823 #define G_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \ 3824 (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) & \ 3825 M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) 3826 #define F_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL \ 3827 V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(1U) 3828 3829 #define S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 1 3830 #define M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 0x3 3831 #define V_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \ 3832 ((x) << S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) 3833 #define G_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \ 3834 (((x) >> S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) & \ 3835 M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) 3836 3837 #define S_FW_TLS_KEYCTX_TX_WR_RXVALID 0 3838 #define M_FW_TLS_KEYCTX_TX_WR_RXVALID 0x1 3839 #define V_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \ 3840 ((x) << S_FW_TLS_KEYCTX_TX_WR_RXVALID) 3841 #define G_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \ 3842 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXVALID) & M_FW_TLS_KEYCTX_TX_WR_RXVALID) 3843 #define F_FW_TLS_KEYCTX_TX_WR_RXVALID V_FW_TLS_KEYCTX_TX_WR_RXVALID(1U) 3844 3845 #define S_FW_TLS_KEYCTX_TX_WR_IVPRESENT 7 3846 #define M_FW_TLS_KEYCTX_TX_WR_IVPRESENT 0x1 3847 #define V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \ 3848 ((x) << S_FW_TLS_KEYCTX_TX_WR_IVPRESENT) 3849 #define G_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \ 3850 (((x) >> S_FW_TLS_KEYCTX_TX_WR_IVPRESENT) & \ 3851 M_FW_TLS_KEYCTX_TX_WR_IVPRESENT) 3852 #define F_FW_TLS_KEYCTX_TX_WR_IVPRESENT V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(1U) 3853 3854 #define S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 6 3855 #define M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 0x1 3856 #define V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \ 3857 ((x) << S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) 3858 #define G_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \ 3859 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) & \ 3860 M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) 3861 #define F_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT \ 3862 V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(1U) 3863 3864 #define S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 3 3865 #define M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 0x7 3866 #define V_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \ 3867 ((x) << S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) 3868 #define G_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \ 3869 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) & \ 3870 M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) 3871 3872 #define S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0 3873 #define M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0x7 3874 #define V_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \ 3875 ((x) << S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) 3876 #define G_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \ 3877 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) & \ 3878 M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) 3879 3880 #define S_FW_TLS_KEYCTX_TX_WR_IVINSERT 55 3881 #define M_FW_TLS_KEYCTX_TX_WR_IVINSERT 0x1ffULL 3882 #define V_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \ 3883 ((x) << S_FW_TLS_KEYCTX_TX_WR_IVINSERT) 3884 #define G_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \ 3885 (((x) >> S_FW_TLS_KEYCTX_TX_WR_IVINSERT) & M_FW_TLS_KEYCTX_TX_WR_IVINSERT) 3886 3887 #define S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 47 3888 #define M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 0xffULL 3889 #define V_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \ 3890 ((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) 3891 #define G_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \ 3892 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) & \ 3893 M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) 3894 3895 #define S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 39 3896 #define M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 0xffULL 3897 #define V_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \ 3898 ((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) 3899 #define G_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \ 3900 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) & \ 3901 M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) 3902 3903 #define S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 30 3904 #define M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 0x1ffULL 3905 #define V_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \ 3906 ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) 3907 #define G_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \ 3908 (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) & \ 3909 M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) 3910 3911 #define S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 23 3912 #define M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 0x7f 3913 #define V_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \ 3914 ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) 3915 #define G_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \ 3916 (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) & \ 3917 M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) 3918 3919 #define S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 14 3920 #define M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 0x1ff 3921 #define V_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \ 3922 ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) 3923 #define G_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \ 3924 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) & \ 3925 M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) 3926 3927 #define S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 7 3928 #define M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 0x7f 3929 #define V_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \ 3930 ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) 3931 #define G_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \ 3932 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) & \ 3933 M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) 3934 3935 #define S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0 3936 #define M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0x7f 3937 #define V_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \ 3938 ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) 3939 #define G_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \ 3940 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) & \ 3941 M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) 3942 3943 #define S_FW_TLS_KEYCTX_TX_WR_RENEG 4 3944 #define M_FW_TLS_KEYCTX_TX_WR_RENEG 0x1 3945 #define V_FW_TLS_KEYCTX_TX_WR_RENEG(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_RENEG) 3946 #define G_FW_TLS_KEYCTX_TX_WR_RENEG(x) \ 3947 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RENEG) & M_FW_TLS_KEYCTX_TX_WR_RENEG) 3948 #define F_FW_TLS_KEYCTX_TX_WR_RENEG V_FW_TLS_KEYCTX_TX_WR_RENEG(1U) 3949 3950 #define S_FW_TLS_KEYCTX_TX_WR_DELETE_TX 3 3951 #define M_FW_TLS_KEYCTX_TX_WR_DELETE_TX 0x1 3952 #define V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \ 3953 ((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_TX) 3954 #define G_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \ 3955 (((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_TX) & \ 3956 M_FW_TLS_KEYCTX_TX_WR_DELETE_TX) 3957 #define F_FW_TLS_KEYCTX_TX_WR_DELETE_TX V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(1U) 3958 3959 #define S_FW_TLS_KEYCTX_TX_WR_DELETE_RX 2 3960 #define M_FW_TLS_KEYCTX_TX_WR_DELETE_RX 0x1 3961 #define V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \ 3962 ((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_RX) 3963 #define G_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \ 3964 (((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_RX) & \ 3965 M_FW_TLS_KEYCTX_TX_WR_DELETE_RX) 3966 #define F_FW_TLS_KEYCTX_TX_WR_DELETE_RX V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(1U) 3967 3968 #define S_FW_TLS_KEYCTX_TX_WR_WRITE_TX 1 3969 #define M_FW_TLS_KEYCTX_TX_WR_WRITE_TX 0x1 3970 #define V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \ 3971 ((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_TX) 3972 #define G_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \ 3973 (((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_TX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_TX) 3974 #define F_FW_TLS_KEYCTX_TX_WR_WRITE_TX V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(1U) 3975 3976 #define S_FW_TLS_KEYCTX_TX_WR_WRITE_RX 0 3977 #define M_FW_TLS_KEYCTX_TX_WR_WRITE_RX 0x1 3978 #define V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \ 3979 ((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_RX) 3980 #define G_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \ 3981 (((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_RX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_RX) 3982 #define F_FW_TLS_KEYCTX_TX_WR_WRITE_RX V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(1U) 3983 3984 struct fw_crypto_lookaside_wr { 3985 __be32 op_to_cctx_size; 3986 __be32 len16_pkd; 3987 __be32 session_id; 3988 __be32 rx_chid_to_rx_q_id; 3989 __be32 key_addr; 3990 __be32 pld_size_hash_size; 3991 __be64 cookie; 3992 }; 3993 3994 #define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24 3995 #define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff 3996 #define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 3997 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 3998 #define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 3999 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \ 4000 M_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 4001 4002 #define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23 4003 #define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1 4004 #define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 4005 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL) 4006 #define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 4007 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \ 4008 M_FW_CRYPTO_LOOKASIDE_WR_COMPL) 4009 #define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U) 4010 4011 #define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15 4012 #define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff 4013 #define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 4014 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 4015 #define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 4016 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \ 4017 M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 4018 4019 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5 4020 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3 4021 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 4022 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 4023 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 4024 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \ 4025 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 4026 4027 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0 4028 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f 4029 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 4030 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 4031 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 4032 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \ 4033 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 4034 4035 #define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0 4036 #define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff 4037 #define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 4038 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16) 4039 #define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 4040 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \ 4041 M_FW_CRYPTO_LOOKASIDE_WR_LEN16) 4042 4043 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29 4044 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3 4045 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 4046 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 4047 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 4048 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \ 4049 M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 4050 4051 #define S_FW_CRYPTO_LOOKASIDE_WR_LCB 27 4052 #define M_FW_CRYPTO_LOOKASIDE_WR_LCB 0x3 4053 #define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 4054 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB) 4055 #define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 4056 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB) 4057 4058 #define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25 4059 #define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3 4060 #define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 4061 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH) 4062 #define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 4063 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \ 4064 M_FW_CRYPTO_LOOKASIDE_WR_PHASH) 4065 4066 #define S_FW_CRYPTO_LOOKASIDE_WR_IV 23 4067 #define M_FW_CRYPTO_LOOKASIDE_WR_IV 0x3 4068 #define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 4069 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV) 4070 #define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 4071 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV) 4072 4073 #define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX 15 4074 #define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX 0xff 4075 #define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 4076 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 4077 #define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 4078 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\ 4079 M_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 4080 4081 #define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10 4082 #define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3 4083 #define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 4084 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 4085 #define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 4086 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \ 4087 M_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 4088 4089 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0 4090 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff 4091 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 4092 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 4093 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 4094 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \ 4095 M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 4096 4097 #define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24 4098 #define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff 4099 #define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 4100 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 4101 #define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 4102 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \ 4103 M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 4104 4105 #define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17 4106 #define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f 4107 #define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 4108 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 4109 #define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 4110 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \ 4111 M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 4112 4113 /****************************************************************************** 4114 * C O M M A N D s 4115 *********************/ 4116 4117 /* 4118 * The maximum length of time, in miliseconds, that we expect any firmware 4119 * command to take to execute and return a reply to the host. The RESET 4120 * and INITIALIZE commands can take a fair amount of time to execute but 4121 * most execute in far less time than this maximum. This constant is used 4122 * by host software to determine how long to wait for a firmware command 4123 * reply before declaring the firmware as dead/unreachable ... 4124 */ 4125 #define FW_CMD_MAX_TIMEOUT 10000 4126 4127 /* 4128 * If a host driver does a HELLO and discovers that there's already a MASTER 4129 * selected, we may have to wait for that MASTER to finish issuing RESET, 4130 * configuration and INITIALIZE commands. Also, there's a possibility that 4131 * our own HELLO may get lost if it happens right as the MASTER is issuign a 4132 * RESET command, so we need to be willing to make a few retries of our HELLO. 4133 */ 4134 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 4135 #define FW_CMD_HELLO_RETRIES 3 4136 4137 enum fw_cmd_opcodes { 4138 FW_LDST_CMD = 0x01, 4139 FW_RESET_CMD = 0x03, 4140 FW_HELLO_CMD = 0x04, 4141 FW_BYE_CMD = 0x05, 4142 FW_INITIALIZE_CMD = 0x06, 4143 FW_CAPS_CONFIG_CMD = 0x07, 4144 FW_PARAMS_CMD = 0x08, 4145 FW_PFVF_CMD = 0x09, 4146 FW_IQ_CMD = 0x10, 4147 FW_EQ_MNGT_CMD = 0x11, 4148 FW_EQ_ETH_CMD = 0x12, 4149 FW_EQ_CTRL_CMD = 0x13, 4150 FW_EQ_OFLD_CMD = 0x21, 4151 FW_VI_CMD = 0x14, 4152 FW_VI_MAC_CMD = 0x15, 4153 FW_VI_RXMODE_CMD = 0x16, 4154 FW_VI_ENABLE_CMD = 0x17, 4155 FW_VI_STATS_CMD = 0x1a, 4156 FW_ACL_MAC_CMD = 0x18, 4157 FW_ACL_VLAN_CMD = 0x19, 4158 FW_PORT_CMD = 0x1b, 4159 FW_PORT_STATS_CMD = 0x1c, 4160 FW_PORT_LB_STATS_CMD = 0x1d, 4161 FW_PORT_TRACE_CMD = 0x1e, 4162 FW_PORT_TRACE_MMAP_CMD = 0x1f, 4163 FW_RSS_IND_TBL_CMD = 0x20, 4164 FW_RSS_GLB_CONFIG_CMD = 0x22, 4165 FW_RSS_VI_CONFIG_CMD = 0x23, 4166 FW_SCHED_CMD = 0x24, 4167 FW_DEVLOG_CMD = 0x25, 4168 FW_WATCHDOG_CMD = 0x27, 4169 FW_CLIP_CMD = 0x28, 4170 FW_CHNET_IFACE_CMD = 0x26, 4171 FW_FCOE_RES_INFO_CMD = 0x31, 4172 FW_FCOE_LINK_CMD = 0x32, 4173 FW_FCOE_VNP_CMD = 0x33, 4174 FW_FCOE_SPARAMS_CMD = 0x35, 4175 FW_FCOE_STATS_CMD = 0x37, 4176 FW_FCOE_FCF_CMD = 0x38, 4177 FW_DCB_IEEE_CMD = 0x3a, 4178 FW_DIAG_CMD = 0x3d, 4179 FW_PTP_CMD = 0x3e, 4180 FW_HMA_CMD = 0x3f, 4181 FW_LASTC2E_CMD = 0x40, 4182 FW_ERROR_CMD = 0x80, 4183 FW_DEBUG_CMD = 0x81, 4184 }; 4185 4186 enum fw_cmd_cap { 4187 FW_CMD_CAP_PF = 0x01, 4188 FW_CMD_CAP_DMAQ = 0x02, 4189 FW_CMD_CAP_PORT = 0x04, 4190 FW_CMD_CAP_PORTPROMISC = 0x08, 4191 FW_CMD_CAP_PORTSTATS = 0x10, 4192 FW_CMD_CAP_VF = 0x80, 4193 }; 4194 4195 /* 4196 * Generic command header flit0 4197 */ 4198 struct fw_cmd_hdr { 4199 __be32 hi; 4200 __be32 lo; 4201 }; 4202 4203 #define S_FW_CMD_OP 24 4204 #define M_FW_CMD_OP 0xff 4205 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 4206 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 4207 4208 #define S_FW_CMD_REQUEST 23 4209 #define M_FW_CMD_REQUEST 0x1 4210 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 4211 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 4212 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 4213 4214 #define S_FW_CMD_READ 22 4215 #define M_FW_CMD_READ 0x1 4216 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 4217 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 4218 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 4219 4220 #define S_FW_CMD_WRITE 21 4221 #define M_FW_CMD_WRITE 0x1 4222 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 4223 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 4224 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 4225 4226 #define S_FW_CMD_EXEC 20 4227 #define M_FW_CMD_EXEC 0x1 4228 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 4229 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 4230 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 4231 4232 #define S_FW_CMD_RAMASK 20 4233 #define M_FW_CMD_RAMASK 0xf 4234 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 4235 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 4236 4237 #define S_FW_CMD_RETVAL 8 4238 #define M_FW_CMD_RETVAL 0xff 4239 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 4240 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 4241 4242 #define S_FW_CMD_LEN16 0 4243 #define M_FW_CMD_LEN16 0xff 4244 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 4245 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 4246 4247 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 4248 4249 /* 4250 * address spaces 4251 */ 4252 enum fw_ldst_addrspc { 4253 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 4254 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 4255 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 4256 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 4257 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 4258 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 4259 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 4260 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 4261 FW_LDST_ADDRSPC_MDIO = 0x0018, 4262 FW_LDST_ADDRSPC_MPS = 0x0020, 4263 FW_LDST_ADDRSPC_FUNC = 0x0028, 4264 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 4265 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 4266 FW_LDST_ADDRSPC_LE = 0x0030, 4267 FW_LDST_ADDRSPC_I2C = 0x0038, 4268 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 4269 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 4270 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 4271 FW_LDST_ADDRSPC_CIM_Q = 0x0048, 4272 }; 4273 4274 /* 4275 * MDIO VSC8634 register access control field 4276 */ 4277 enum fw_ldst_mdio_vsc8634_aid { 4278 FW_LDST_MDIO_VS_STANDARD, 4279 FW_LDST_MDIO_VS_EXTENDED, 4280 FW_LDST_MDIO_VS_GPIO 4281 }; 4282 4283 enum fw_ldst_mps_fid { 4284 FW_LDST_MPS_ATRB, 4285 FW_LDST_MPS_RPLC 4286 }; 4287 4288 enum fw_ldst_func_access_ctl { 4289 FW_LDST_FUNC_ACC_CTL_VIID, 4290 FW_LDST_FUNC_ACC_CTL_FID 4291 }; 4292 4293 enum fw_ldst_func_mod_index { 4294 FW_LDST_FUNC_MPS 4295 }; 4296 4297 struct fw_ldst_cmd { 4298 __be32 op_to_addrspace; 4299 __be32 cycles_to_len16; 4300 union fw_ldst { 4301 struct fw_ldst_addrval { 4302 __be32 addr; 4303 __be32 val; 4304 } addrval; 4305 struct fw_ldst_idctxt { 4306 __be32 physid; 4307 __be32 msg_ctxtflush; 4308 __be32 ctxt_data7; 4309 __be32 ctxt_data6; 4310 __be32 ctxt_data5; 4311 __be32 ctxt_data4; 4312 __be32 ctxt_data3; 4313 __be32 ctxt_data2; 4314 __be32 ctxt_data1; 4315 __be32 ctxt_data0; 4316 } idctxt; 4317 struct fw_ldst_mdio { 4318 __be16 paddr_mmd; 4319 __be16 raddr; 4320 __be16 vctl; 4321 __be16 rval; 4322 } mdio; 4323 struct fw_ldst_cim_rq { 4324 __u8 req_first64[8]; 4325 __u8 req_second64[8]; 4326 __u8 resp_first64[8]; 4327 __u8 resp_second64[8]; 4328 __be32 r3[2]; 4329 } cim_rq; 4330 union fw_ldst_mps { 4331 struct fw_ldst_mps_rplc { 4332 __be16 fid_idx; 4333 __be16 rplcpf_pkd; 4334 __be32 rplc255_224; 4335 __be32 rplc223_192; 4336 __be32 rplc191_160; 4337 __be32 rplc159_128; 4338 __be32 rplc127_96; 4339 __be32 rplc95_64; 4340 __be32 rplc63_32; 4341 __be32 rplc31_0; 4342 } rplc; 4343 struct fw_ldst_mps_atrb { 4344 __be16 fid_mpsid; 4345 __be16 r2[3]; 4346 __be32 r3[2]; 4347 __be32 r4; 4348 __be32 atrb; 4349 __be16 vlan[16]; 4350 } atrb; 4351 } mps; 4352 struct fw_ldst_func { 4353 __u8 access_ctl; 4354 __u8 mod_index; 4355 __be16 ctl_id; 4356 __be32 offset; 4357 __be64 data0; 4358 __be64 data1; 4359 } func; 4360 struct fw_ldst_pcie { 4361 __u8 ctrl_to_fn; 4362 __u8 bnum; 4363 __u8 r; 4364 __u8 ext_r; 4365 __u8 select_naccess; 4366 __u8 pcie_fn; 4367 __be16 nset_pkd; 4368 __be32 data[12]; 4369 } pcie; 4370 struct fw_ldst_i2c_deprecated { 4371 __u8 pid_pkd; 4372 __u8 base; 4373 __u8 boffset; 4374 __u8 data; 4375 __be32 r9; 4376 } i2c_deprecated; 4377 struct fw_ldst_i2c { 4378 __u8 pid; 4379 __u8 did; 4380 __u8 boffset; 4381 __u8 blen; 4382 __be32 r9; 4383 __u8 data[48]; 4384 } i2c; 4385 struct fw_ldst_le { 4386 __be32 index; 4387 __be32 r9; 4388 __u8 val[33]; 4389 __u8 r11[7]; 4390 } le; 4391 } u; 4392 }; 4393 4394 #define S_FW_LDST_CMD_ADDRSPACE 0 4395 #define M_FW_LDST_CMD_ADDRSPACE 0xff 4396 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 4397 #define G_FW_LDST_CMD_ADDRSPACE(x) \ 4398 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 4399 4400 #define S_FW_LDST_CMD_CYCLES 16 4401 #define M_FW_LDST_CMD_CYCLES 0xffff 4402 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 4403 #define G_FW_LDST_CMD_CYCLES(x) \ 4404 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 4405 4406 #define S_FW_LDST_CMD_MSG 31 4407 #define M_FW_LDST_CMD_MSG 0x1 4408 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 4409 #define G_FW_LDST_CMD_MSG(x) \ 4410 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 4411 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 4412 4413 #define S_FW_LDST_CMD_CTXTFLUSH 30 4414 #define M_FW_LDST_CMD_CTXTFLUSH 0x1 4415 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 4416 #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 4417 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 4418 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 4419 4420 #define S_FW_LDST_CMD_PADDR 8 4421 #define M_FW_LDST_CMD_PADDR 0x1f 4422 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 4423 #define G_FW_LDST_CMD_PADDR(x) \ 4424 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 4425 4426 #define S_FW_LDST_CMD_MMD 0 4427 #define M_FW_LDST_CMD_MMD 0x1f 4428 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 4429 #define G_FW_LDST_CMD_MMD(x) \ 4430 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 4431 4432 #define S_FW_LDST_CMD_FID 15 4433 #define M_FW_LDST_CMD_FID 0x1 4434 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 4435 #define G_FW_LDST_CMD_FID(x) \ 4436 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 4437 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 4438 4439 #define S_FW_LDST_CMD_IDX 0 4440 #define M_FW_LDST_CMD_IDX 0x7fff 4441 #define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX) 4442 #define G_FW_LDST_CMD_IDX(x) \ 4443 (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX) 4444 4445 #define S_FW_LDST_CMD_RPLCPF 0 4446 #define M_FW_LDST_CMD_RPLCPF 0xff 4447 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 4448 #define G_FW_LDST_CMD_RPLCPF(x) \ 4449 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 4450 4451 #define S_FW_LDST_CMD_MPSID 0 4452 #define M_FW_LDST_CMD_MPSID 0x7fff 4453 #define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID) 4454 #define G_FW_LDST_CMD_MPSID(x) \ 4455 (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID) 4456 4457 #define S_FW_LDST_CMD_CTRL 7 4458 #define M_FW_LDST_CMD_CTRL 0x1 4459 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 4460 #define G_FW_LDST_CMD_CTRL(x) \ 4461 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 4462 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 4463 4464 #define S_FW_LDST_CMD_LC 4 4465 #define M_FW_LDST_CMD_LC 0x1 4466 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 4467 #define G_FW_LDST_CMD_LC(x) \ 4468 (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 4469 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 4470 4471 #define S_FW_LDST_CMD_AI 3 4472 #define M_FW_LDST_CMD_AI 0x1 4473 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 4474 #define G_FW_LDST_CMD_AI(x) \ 4475 (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 4476 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 4477 4478 #define S_FW_LDST_CMD_FN 0 4479 #define M_FW_LDST_CMD_FN 0x7 4480 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 4481 #define G_FW_LDST_CMD_FN(x) \ 4482 (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 4483 4484 #define S_FW_LDST_CMD_SELECT 4 4485 #define M_FW_LDST_CMD_SELECT 0xf 4486 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 4487 #define G_FW_LDST_CMD_SELECT(x) \ 4488 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 4489 4490 #define S_FW_LDST_CMD_NACCESS 0 4491 #define M_FW_LDST_CMD_NACCESS 0xf 4492 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 4493 #define G_FW_LDST_CMD_NACCESS(x) \ 4494 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 4495 4496 #define S_FW_LDST_CMD_NSET 14 4497 #define M_FW_LDST_CMD_NSET 0x3 4498 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 4499 #define G_FW_LDST_CMD_NSET(x) \ 4500 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 4501 4502 #define S_FW_LDST_CMD_PID 6 4503 #define M_FW_LDST_CMD_PID 0x3 4504 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 4505 #define G_FW_LDST_CMD_PID(x) \ 4506 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 4507 4508 struct fw_reset_cmd { 4509 __be32 op_to_write; 4510 __be32 retval_len16; 4511 __be32 val; 4512 __be32 halt_pkd; 4513 }; 4514 4515 #define S_FW_RESET_CMD_HALT 31 4516 #define M_FW_RESET_CMD_HALT 0x1 4517 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 4518 #define G_FW_RESET_CMD_HALT(x) \ 4519 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 4520 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 4521 4522 enum { 4523 FW_HELLO_CMD_STAGE_OS = 0, 4524 FW_HELLO_CMD_STAGE_PREOS0 = 1, 4525 FW_HELLO_CMD_STAGE_PREOS1 = 2, 4526 FW_HELLO_CMD_STAGE_POSTOS = 3, 4527 }; 4528 4529 struct fw_hello_cmd { 4530 __be32 op_to_write; 4531 __be32 retval_len16; 4532 __be32 err_to_clearinit; 4533 __be32 fwrev; 4534 }; 4535 4536 #define S_FW_HELLO_CMD_ERR 31 4537 #define M_FW_HELLO_CMD_ERR 0x1 4538 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 4539 #define G_FW_HELLO_CMD_ERR(x) \ 4540 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 4541 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 4542 4543 #define S_FW_HELLO_CMD_INIT 30 4544 #define M_FW_HELLO_CMD_INIT 0x1 4545 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 4546 #define G_FW_HELLO_CMD_INIT(x) \ 4547 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 4548 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 4549 4550 #define S_FW_HELLO_CMD_MASTERDIS 29 4551 #define M_FW_HELLO_CMD_MASTERDIS 0x1 4552 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 4553 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 4554 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 4555 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 4556 4557 #define S_FW_HELLO_CMD_MASTERFORCE 28 4558 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 4559 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 4560 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 4561 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 4562 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 4563 4564 #define S_FW_HELLO_CMD_MBMASTER 24 4565 #define M_FW_HELLO_CMD_MBMASTER 0xf 4566 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 4567 #define G_FW_HELLO_CMD_MBMASTER(x) \ 4568 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 4569 4570 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 4571 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 4572 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 4573 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 4574 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 4575 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 4576 4577 #define S_FW_HELLO_CMD_MBASYNCNOT 20 4578 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 4579 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 4580 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 4581 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 4582 4583 #define S_FW_HELLO_CMD_STAGE 17 4584 #define M_FW_HELLO_CMD_STAGE 0x7 4585 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 4586 #define G_FW_HELLO_CMD_STAGE(x) \ 4587 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 4588 4589 #define S_FW_HELLO_CMD_CLEARINIT 16 4590 #define M_FW_HELLO_CMD_CLEARINIT 0x1 4591 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 4592 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 4593 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 4594 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 4595 4596 struct fw_bye_cmd { 4597 __be32 op_to_write; 4598 __be32 retval_len16; 4599 __be64 r3; 4600 }; 4601 4602 struct fw_initialize_cmd { 4603 __be32 op_to_write; 4604 __be32 retval_len16; 4605 __be64 r3; 4606 }; 4607 4608 enum fw_caps_config_hm { 4609 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 4610 FW_CAPS_CONFIG_HM_PL = 0x00000002, 4611 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 4612 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 4613 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 4614 FW_CAPS_CONFIG_HM_TP = 0x00000020, 4615 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 4616 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 4617 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 4618 FW_CAPS_CONFIG_HM_MC = 0x00000200, 4619 FW_CAPS_CONFIG_HM_LE = 0x00000400, 4620 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 4621 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 4622 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 4623 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 4624 FW_CAPS_CONFIG_HM_MI = 0x00008000, 4625 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 4626 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 4627 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 4628 FW_CAPS_CONFIG_HM_MA = 0x00080000, 4629 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 4630 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 4631 FW_CAPS_CONFIG_HM_UART = 0x00400000, 4632 FW_CAPS_CONFIG_HM_SF = 0x00800000, 4633 }; 4634 4635 /* 4636 * The VF Register Map. 4637 * 4638 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 4639 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 4640 * the Slice to Module Map Table (see below) in the Physical Function Register 4641 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 4642 * and Offset registers in the PF Register Map. The MBDATA base address is 4643 * quite constrained as it determines the Mailbox Data addresses for both PFs 4644 * and VFs, and therefore must fit in both the VF and PF Register Maps without 4645 * overlapping other registers. 4646 */ 4647 #define FW_T4VF_SGE_BASE_ADDR 0x0000 4648 #define FW_T4VF_MPS_BASE_ADDR 0x0100 4649 #define FW_T4VF_PL_BASE_ADDR 0x0200 4650 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 4651 #define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */ 4652 #define FW_T4VF_CIM_BASE_ADDR 0x0300 4653 4654 #define FW_T4VF_REGMAP_START 0x0000 4655 #define FW_T4VF_REGMAP_SIZE 0x0400 4656 4657 enum fw_caps_config_nbm { 4658 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 4659 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 4660 }; 4661 4662 enum fw_caps_config_link { 4663 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 4664 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 4665 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 4666 }; 4667 4668 enum fw_caps_config_switch { 4669 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 4670 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 4671 }; 4672 4673 enum fw_caps_config_nic { 4674 FW_CAPS_CONFIG_NIC = 0x00000001, 4675 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 4676 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 4677 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 4678 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 4679 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 4680 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 4681 }; 4682 4683 enum fw_caps_config_toe { 4684 FW_CAPS_CONFIG_TOE = 0x00000001, 4685 }; 4686 4687 enum fw_caps_config_rdma { 4688 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 4689 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 4690 }; 4691 4692 enum fw_caps_config_iscsi { 4693 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 4694 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 4695 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 4696 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 4697 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 4698 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 4699 FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040, 4700 FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080, 4701 FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100, 4702 }; 4703 4704 enum fw_caps_config_crypto { 4705 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001, 4706 FW_CAPS_CONFIG_TLSKEYS = 0x00000002, 4707 }; 4708 4709 enum fw_caps_config_fcoe { 4710 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 4711 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 4712 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 4713 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 4714 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 4715 }; 4716 4717 enum fw_memtype_cf { 4718 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0, 4719 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1, 4720 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM, 4721 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 4722 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL, 4723 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1, 4724 }; 4725 4726 struct fw_caps_config_cmd { 4727 __be32 op_to_write; 4728 __be32 cfvalid_to_len16; 4729 __be32 r2; 4730 __be32 hwmbitmap; 4731 __be16 nbmcaps; 4732 __be16 linkcaps; 4733 __be16 switchcaps; 4734 __be16 r3; 4735 __be16 niccaps; 4736 __be16 toecaps; 4737 __be16 rdmacaps; 4738 __be16 cryptocaps; 4739 __be16 iscsicaps; 4740 __be16 fcoecaps; 4741 __be32 cfcsum; 4742 __be32 finiver; 4743 __be32 finicsum; 4744 }; 4745 4746 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 4747 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 4748 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 4749 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 4750 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 4751 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 4752 4753 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 4754 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 4755 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4756 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4757 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4758 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 4759 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4760 4761 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 4762 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 4763 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4764 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4765 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4766 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 4767 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4768 4769 /* 4770 * params command mnemonics 4771 */ 4772 enum fw_params_mnem { 4773 FW_PARAMS_MNEM_DEV = 1, /* device params */ 4774 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 4775 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 4776 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 4777 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 4778 FW_PARAMS_MNEM_LAST 4779 }; 4780 4781 /* 4782 * device parameters 4783 */ 4784 #define S_FW_PARAMS_PARAM_FILTER_MODE 16 4785 #define M_FW_PARAMS_PARAM_FILTER_MODE 0xffff 4786 #define V_FW_PARAMS_PARAM_FILTER_MODE(x) \ 4787 ((x) << S_FW_PARAMS_PARAM_FILTER_MODE) 4788 #define G_FW_PARAMS_PARAM_FILTER_MODE(x) \ 4789 (((x) >> S_FW_PARAMS_PARAM_FILTER_MODE) & \ 4790 M_FW_PARAMS_PARAM_FILTER_MODE) 4791 4792 #define S_FW_PARAMS_PARAM_FILTER_MASK 0 4793 #define M_FW_PARAMS_PARAM_FILTER_MASK 0xffff 4794 #define V_FW_PARAMS_PARAM_FILTER_MASK(x) \ 4795 ((x) << S_FW_PARAMS_PARAM_FILTER_MASK) 4796 #define G_FW_PARAMS_PARAM_FILTER_MASK(x) \ 4797 (((x) >> S_FW_PARAMS_PARAM_FILTER_MASK) & \ 4798 M_FW_PARAMS_PARAM_FILTER_MASK) 4799 4800 enum fw_params_param_dev { 4801 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 4802 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 4803 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 4804 * allocated by the device's 4805 * Lookup Engine 4806 */ 4807 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 4808 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 4809 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 4810 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 4811 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 4812 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 4813 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 4814 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 4815 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 4816 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 4817 FW_PARAMS_PARAM_DEV_CF = 0x0D, 4818 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 4819 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 4820 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 4821 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 4822 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 4823 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 4824 */ 4825 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 4826 */ 4827 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 4828 FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 4829 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 4830 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 4831 FW_PARAMS_PARAM_DEV_RSSINFO = 0x19, 4832 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 4833 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 4834 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C, 4835 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 4836 4837 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E, 4838 FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F, 4839 FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20, 4840 FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21, 4841 FW_PARAMS_PARAM_DEV_RING_BACKBONE = 0x22, 4842 FW_PARAMS_PARAM_DEV_PPOD_EDRAM = 0x23, 4843 FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR = 0x24, 4844 FW_PARAMS_PARAM_DEV_ADD_SMAC = 0x25, 4845 FW_PARAMS_PARAM_DEV_HPFILTER_REGION_SUPPORT = 0x26, 4846 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27, 4847 FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28, 4848 FW_PARAMS_PARAM_DEV_DBQ_TIMER = 0x29, 4849 FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A, 4850 FW_PARAMS_PARAM_DEV_NUM_TM_CLASS = 0x2B, 4851 FW_PARAMS_PARAM_DEV_VF_TRVLAN = 0x2C, 4852 FW_PARAMS_PARAM_DEV_TCB_CACHE_FLUSH = 0x2D, 4853 FW_PARAMS_PARAM_DEV_FILTER = 0x2E, 4854 }; 4855 4856 /* 4857 * dev bypass parameters; actions and modes 4858 */ 4859 enum fw_params_param_dev_bypass { 4860 4861 /* actions 4862 */ 4863 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 4864 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 4865 4866 /* modes 4867 */ 4868 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 4869 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 4870 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 4871 }; 4872 4873 enum fw_params_param_dev_phyfw { 4874 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 4875 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 4876 }; 4877 4878 enum fw_params_param_dev_diag { 4879 FW_PARAM_DEV_DIAG_TMP = 0x00, 4880 FW_PARAM_DEV_DIAG_VDD = 0x01, 4881 FW_PARAM_DEV_DIAG_MAXTMPTHRESH = 0x02, 4882 }; 4883 4884 enum fw_params_param_dev_filter{ 4885 FW_PARAM_DEV_FILTER_VNIC_MODE = 0x00, 4886 FW_PARAM_DEV_FILTER_MODE_MASK = 0x01, 4887 }; 4888 4889 enum fw_params_param_dev_fwcache { 4890 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 4891 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 4892 }; 4893 4894 /* 4895 * physical and virtual function parameters 4896 */ 4897 enum fw_params_param_pfvf { 4898 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 4899 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 4900 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 4901 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 4902 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 4903 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 4904 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 4905 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 4906 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 4907 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 4908 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 4909 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 4910 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 4911 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 4912 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 4913 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 4914 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 4915 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 4916 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 4917 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 4918 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 4919 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 4920 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 4921 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 4922 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 4923 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19, 4924 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A, 4925 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 4926 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 4927 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 4928 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 4929 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 4930 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 4931 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 4932 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 4933 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 4934 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 4935 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 4936 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 4937 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 4938 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 4939 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 4940 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 4941 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 4942 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34, 4943 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35, 4944 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, 4945 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, 4946 FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38, 4947 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39, 4948 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, 4949 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B, 4950 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C, 4951 FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D, 4952 FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E, 4953 FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F, 4954 FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40, 4955 }; 4956 4957 /* 4958 * virtual link state as seen by the specified VF 4959 */ 4960 enum vf_link_states { 4961 VF_LINK_STATE_AUTO = 0x00, 4962 VF_LINK_STATE_ENABLE = 0x01, 4963 VF_LINK_STATE_DISABLE = 0x02, 4964 }; 4965 4966 /* 4967 * dma queue parameters 4968 */ 4969 enum fw_params_param_dmaq { 4970 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 4971 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 4972 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 4973 FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03, 4974 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 4975 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 4976 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 4977 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 4978 FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14, 4979 FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX = 0x15, 4980 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 4981 FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30 4982 }; 4983 4984 /* 4985 * chnet parameters 4986 */ 4987 enum fw_params_param_chnet { 4988 FW_PARAMS_PARAM_CHNET_FLAGS = 0x00, 4989 }; 4990 4991 enum fw_params_param_chnet_flags { 4992 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1, 4993 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2, 4994 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4, 4995 }; 4996 4997 #define S_FW_PARAMS_MNEM 24 4998 #define M_FW_PARAMS_MNEM 0xff 4999 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 5000 #define G_FW_PARAMS_MNEM(x) \ 5001 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 5002 5003 #define S_FW_PARAMS_PARAM_X 16 5004 #define M_FW_PARAMS_PARAM_X 0xff 5005 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 5006 #define G_FW_PARAMS_PARAM_X(x) \ 5007 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 5008 5009 #define S_FW_PARAMS_PARAM_Y 8 5010 #define M_FW_PARAMS_PARAM_Y 0xff 5011 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 5012 #define G_FW_PARAMS_PARAM_Y(x) \ 5013 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 5014 5015 #define S_FW_PARAMS_PARAM_Z 0 5016 #define M_FW_PARAMS_PARAM_Z 0xff 5017 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 5018 #define G_FW_PARAMS_PARAM_Z(x) \ 5019 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 5020 5021 #define S_FW_PARAMS_PARAM_XYZ 0 5022 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 5023 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 5024 #define G_FW_PARAMS_PARAM_XYZ(x) \ 5025 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 5026 5027 #define S_FW_PARAMS_PARAM_YZ 0 5028 #define M_FW_PARAMS_PARAM_YZ 0xffff 5029 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 5030 #define G_FW_PARAMS_PARAM_YZ(x) \ 5031 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 5032 5033 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31 5034 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1 5035 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 5036 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 5037 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 5038 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \ 5039 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 5040 5041 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24 5042 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3 5043 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 5044 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 5045 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 5046 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \ 5047 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 5048 5049 #define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0 5050 #define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff 5051 #define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 5052 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST) 5053 #define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 5054 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST) 5055 5056 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 29 5057 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 0x7 5058 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 5059 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 5060 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 5061 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \ 5062 M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 5063 5064 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0 5065 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0x3ff 5066 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 5067 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 5068 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 5069 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \ 5070 M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 5071 5072 struct fw_params_cmd { 5073 __be32 op_to_vfn; 5074 __be32 retval_len16; 5075 struct fw_params_param { 5076 __be32 mnem; 5077 __be32 val; 5078 } param[7]; 5079 }; 5080 5081 #define S_FW_PARAMS_CMD_PFN 8 5082 #define M_FW_PARAMS_CMD_PFN 0x7 5083 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 5084 #define G_FW_PARAMS_CMD_PFN(x) \ 5085 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 5086 5087 #define S_FW_PARAMS_CMD_VFN 0 5088 #define M_FW_PARAMS_CMD_VFN 0xff 5089 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 5090 #define G_FW_PARAMS_CMD_VFN(x) \ 5091 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 5092 5093 struct fw_pfvf_cmd { 5094 __be32 op_to_vfn; 5095 __be32 retval_len16; 5096 __be32 niqflint_niq; 5097 __be32 type_to_neq; 5098 __be32 tc_to_nexactf; 5099 __be32 r_caps_to_nethctrl; 5100 __be16 nricq; 5101 __be16 nriqp; 5102 __be32 r4; 5103 }; 5104 5105 #define S_FW_PFVF_CMD_PFN 8 5106 #define M_FW_PFVF_CMD_PFN 0x7 5107 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 5108 #define G_FW_PFVF_CMD_PFN(x) \ 5109 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 5110 5111 #define S_FW_PFVF_CMD_VFN 0 5112 #define M_FW_PFVF_CMD_VFN 0xff 5113 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 5114 #define G_FW_PFVF_CMD_VFN(x) \ 5115 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 5116 5117 #define S_FW_PFVF_CMD_NIQFLINT 20 5118 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 5119 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 5120 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 5121 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 5122 5123 #define S_FW_PFVF_CMD_NIQ 0 5124 #define M_FW_PFVF_CMD_NIQ 0xfffff 5125 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 5126 #define G_FW_PFVF_CMD_NIQ(x) \ 5127 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 5128 5129 #define S_FW_PFVF_CMD_TYPE 31 5130 #define M_FW_PFVF_CMD_TYPE 0x1 5131 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 5132 #define G_FW_PFVF_CMD_TYPE(x) \ 5133 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 5134 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 5135 5136 #define S_FW_PFVF_CMD_CMASK 24 5137 #define M_FW_PFVF_CMD_CMASK 0xf 5138 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 5139 #define G_FW_PFVF_CMD_CMASK(x) \ 5140 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 5141 5142 #define S_FW_PFVF_CMD_PMASK 20 5143 #define M_FW_PFVF_CMD_PMASK 0xf 5144 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 5145 #define G_FW_PFVF_CMD_PMASK(x) \ 5146 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 5147 5148 #define S_FW_PFVF_CMD_NEQ 0 5149 #define M_FW_PFVF_CMD_NEQ 0xfffff 5150 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 5151 #define G_FW_PFVF_CMD_NEQ(x) \ 5152 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 5153 5154 #define S_FW_PFVF_CMD_TC 24 5155 #define M_FW_PFVF_CMD_TC 0xff 5156 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 5157 #define G_FW_PFVF_CMD_TC(x) \ 5158 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 5159 5160 #define S_FW_PFVF_CMD_NVI 16 5161 #define M_FW_PFVF_CMD_NVI 0xff 5162 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 5163 #define G_FW_PFVF_CMD_NVI(x) \ 5164 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 5165 5166 #define S_FW_PFVF_CMD_NEXACTF 0 5167 #define M_FW_PFVF_CMD_NEXACTF 0xffff 5168 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 5169 #define G_FW_PFVF_CMD_NEXACTF(x) \ 5170 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 5171 5172 #define S_FW_PFVF_CMD_R_CAPS 24 5173 #define M_FW_PFVF_CMD_R_CAPS 0xff 5174 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 5175 #define G_FW_PFVF_CMD_R_CAPS(x) \ 5176 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 5177 5178 #define S_FW_PFVF_CMD_WX_CAPS 16 5179 #define M_FW_PFVF_CMD_WX_CAPS 0xff 5180 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 5181 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 5182 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 5183 5184 #define S_FW_PFVF_CMD_NETHCTRL 0 5185 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 5186 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 5187 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 5188 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 5189 5190 /* 5191 * ingress queue type; the first 1K ingress queues can have associated 0, 5192 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 5193 * capabilities 5194 */ 5195 enum fw_iq_type { 5196 FW_IQ_TYPE_FL_INT_CAP, 5197 FW_IQ_TYPE_NO_FL_INT_CAP, 5198 FW_IQ_TYPE_VF_CQ 5199 }; 5200 5201 enum fw_iq_iqtype { 5202 FW_IQ_IQTYPE_OTHER, 5203 FW_IQ_IQTYPE_NIC, 5204 FW_IQ_IQTYPE_OFLD, 5205 }; 5206 5207 struct fw_iq_cmd { 5208 __be32 op_to_vfn; 5209 __be32 alloc_to_len16; 5210 __be16 physiqid; 5211 __be16 iqid; 5212 __be16 fl0id; 5213 __be16 fl1id; 5214 __be32 type_to_iqandstindex; 5215 __be16 iqdroprss_to_iqesize; 5216 __be16 iqsize; 5217 __be64 iqaddr; 5218 __be32 iqns_to_fl0congen; 5219 __be16 fl0dcaen_to_fl0cidxfthresh; 5220 __be16 fl0size; 5221 __be64 fl0addr; 5222 __be32 fl1cngchmap_to_fl1congen; 5223 __be16 fl1dcaen_to_fl1cidxfthresh; 5224 __be16 fl1size; 5225 __be64 fl1addr; 5226 }; 5227 5228 #define S_FW_IQ_CMD_PFN 8 5229 #define M_FW_IQ_CMD_PFN 0x7 5230 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 5231 #define G_FW_IQ_CMD_PFN(x) \ 5232 (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 5233 5234 #define S_FW_IQ_CMD_VFN 0 5235 #define M_FW_IQ_CMD_VFN 0xff 5236 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 5237 #define G_FW_IQ_CMD_VFN(x) \ 5238 (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 5239 5240 #define S_FW_IQ_CMD_ALLOC 31 5241 #define M_FW_IQ_CMD_ALLOC 0x1 5242 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 5243 #define G_FW_IQ_CMD_ALLOC(x) \ 5244 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 5245 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 5246 5247 #define S_FW_IQ_CMD_FREE 30 5248 #define M_FW_IQ_CMD_FREE 0x1 5249 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 5250 #define G_FW_IQ_CMD_FREE(x) \ 5251 (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 5252 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 5253 5254 #define S_FW_IQ_CMD_MODIFY 29 5255 #define M_FW_IQ_CMD_MODIFY 0x1 5256 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 5257 #define G_FW_IQ_CMD_MODIFY(x) \ 5258 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 5259 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 5260 5261 #define S_FW_IQ_CMD_IQSTART 28 5262 #define M_FW_IQ_CMD_IQSTART 0x1 5263 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 5264 #define G_FW_IQ_CMD_IQSTART(x) \ 5265 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 5266 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 5267 5268 #define S_FW_IQ_CMD_IQSTOP 27 5269 #define M_FW_IQ_CMD_IQSTOP 0x1 5270 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 5271 #define G_FW_IQ_CMD_IQSTOP(x) \ 5272 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 5273 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 5274 5275 #define S_FW_IQ_CMD_TYPE 29 5276 #define M_FW_IQ_CMD_TYPE 0x7 5277 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 5278 #define G_FW_IQ_CMD_TYPE(x) \ 5279 (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 5280 5281 #define S_FW_IQ_CMD_IQASYNCH 28 5282 #define M_FW_IQ_CMD_IQASYNCH 0x1 5283 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 5284 #define G_FW_IQ_CMD_IQASYNCH(x) \ 5285 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 5286 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 5287 5288 #define S_FW_IQ_CMD_VIID 16 5289 #define M_FW_IQ_CMD_VIID 0xfff 5290 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 5291 #define G_FW_IQ_CMD_VIID(x) \ 5292 (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 5293 5294 #define S_FW_IQ_CMD_IQANDST 15 5295 #define M_FW_IQ_CMD_IQANDST 0x1 5296 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 5297 #define G_FW_IQ_CMD_IQANDST(x) \ 5298 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 5299 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 5300 5301 #define S_FW_IQ_CMD_IQANUS 14 5302 #define M_FW_IQ_CMD_IQANUS 0x1 5303 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 5304 #define G_FW_IQ_CMD_IQANUS(x) \ 5305 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 5306 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 5307 5308 #define S_FW_IQ_CMD_IQANUD 12 5309 #define M_FW_IQ_CMD_IQANUD 0x3 5310 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 5311 #define G_FW_IQ_CMD_IQANUD(x) \ 5312 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 5313 5314 #define S_FW_IQ_CMD_IQANDSTINDEX 0 5315 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 5316 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 5317 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 5318 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 5319 5320 #define S_FW_IQ_CMD_IQDROPRSS 15 5321 #define M_FW_IQ_CMD_IQDROPRSS 0x1 5322 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 5323 #define G_FW_IQ_CMD_IQDROPRSS(x) \ 5324 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 5325 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 5326 5327 #define S_FW_IQ_CMD_IQGTSMODE 14 5328 #define M_FW_IQ_CMD_IQGTSMODE 0x1 5329 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 5330 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 5331 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 5332 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 5333 5334 #define S_FW_IQ_CMD_IQPCIECH 12 5335 #define M_FW_IQ_CMD_IQPCIECH 0x3 5336 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 5337 #define G_FW_IQ_CMD_IQPCIECH(x) \ 5338 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 5339 5340 #define S_FW_IQ_CMD_IQDCAEN 11 5341 #define M_FW_IQ_CMD_IQDCAEN 0x1 5342 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 5343 #define G_FW_IQ_CMD_IQDCAEN(x) \ 5344 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 5345 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 5346 5347 #define S_FW_IQ_CMD_IQDCACPU 6 5348 #define M_FW_IQ_CMD_IQDCACPU 0x1f 5349 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 5350 #define G_FW_IQ_CMD_IQDCACPU(x) \ 5351 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 5352 5353 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 5354 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 5355 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 5356 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 5357 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 5358 5359 #define S_FW_IQ_CMD_IQO 3 5360 #define M_FW_IQ_CMD_IQO 0x1 5361 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 5362 #define G_FW_IQ_CMD_IQO(x) \ 5363 (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 5364 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 5365 5366 #define S_FW_IQ_CMD_IQCPRIO 2 5367 #define M_FW_IQ_CMD_IQCPRIO 0x1 5368 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 5369 #define G_FW_IQ_CMD_IQCPRIO(x) \ 5370 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 5371 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 5372 5373 #define S_FW_IQ_CMD_IQESIZE 0 5374 #define M_FW_IQ_CMD_IQESIZE 0x3 5375 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 5376 #define G_FW_IQ_CMD_IQESIZE(x) \ 5377 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 5378 5379 #define S_FW_IQ_CMD_IQNS 31 5380 #define M_FW_IQ_CMD_IQNS 0x1 5381 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 5382 #define G_FW_IQ_CMD_IQNS(x) \ 5383 (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 5384 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 5385 5386 #define S_FW_IQ_CMD_IQRO 30 5387 #define M_FW_IQ_CMD_IQRO 0x1 5388 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 5389 #define G_FW_IQ_CMD_IQRO(x) \ 5390 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 5391 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 5392 5393 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 5394 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 5395 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 5396 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 5397 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 5398 5399 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 5400 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 5401 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 5402 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 5403 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 5404 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 5405 5406 #define S_FW_IQ_CMD_IQFLINTISCSIC 26 5407 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 5408 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 5409 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 5410 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 5411 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 5412 5413 #define S_FW_IQ_CMD_IQTYPE 24 5414 #define M_FW_IQ_CMD_IQTYPE 0x3 5415 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE) 5416 #define G_FW_IQ_CMD_IQTYPE(x) \ 5417 (((x) >> S_FW_IQ_CMD_IQTYPE) & M_FW_IQ_CMD_IQTYPE) 5418 5419 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 5420 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 5421 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 5422 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 5423 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 5424 5425 #define S_FW_IQ_CMD_FL0CONGDROP 16 5426 #define M_FW_IQ_CMD_FL0CONGDROP 0x1 5427 #define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP) 5428 #define G_FW_IQ_CMD_FL0CONGDROP(x) \ 5429 (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP) 5430 #define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U) 5431 5432 #define S_FW_IQ_CMD_FL0CACHELOCK 15 5433 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 5434 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 5435 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 5436 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 5437 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 5438 5439 #define S_FW_IQ_CMD_FL0DBP 14 5440 #define M_FW_IQ_CMD_FL0DBP 0x1 5441 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 5442 #define G_FW_IQ_CMD_FL0DBP(x) \ 5443 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 5444 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 5445 5446 #define S_FW_IQ_CMD_FL0DATANS 13 5447 #define M_FW_IQ_CMD_FL0DATANS 0x1 5448 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 5449 #define G_FW_IQ_CMD_FL0DATANS(x) \ 5450 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 5451 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 5452 5453 #define S_FW_IQ_CMD_FL0DATARO 12 5454 #define M_FW_IQ_CMD_FL0DATARO 0x1 5455 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 5456 #define G_FW_IQ_CMD_FL0DATARO(x) \ 5457 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 5458 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 5459 5460 #define S_FW_IQ_CMD_FL0CONGCIF 11 5461 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 5462 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 5463 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 5464 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 5465 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 5466 5467 #define S_FW_IQ_CMD_FL0ONCHIP 10 5468 #define M_FW_IQ_CMD_FL0ONCHIP 0x1 5469 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 5470 #define G_FW_IQ_CMD_FL0ONCHIP(x) \ 5471 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 5472 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 5473 5474 #define S_FW_IQ_CMD_FL0STATUSPGNS 9 5475 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 5476 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 5477 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 5478 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 5479 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 5480 5481 #define S_FW_IQ_CMD_FL0STATUSPGRO 8 5482 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 5483 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 5484 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 5485 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 5486 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 5487 5488 #define S_FW_IQ_CMD_FL0FETCHNS 7 5489 #define M_FW_IQ_CMD_FL0FETCHNS 0x1 5490 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 5491 #define G_FW_IQ_CMD_FL0FETCHNS(x) \ 5492 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 5493 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 5494 5495 #define S_FW_IQ_CMD_FL0FETCHRO 6 5496 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 5497 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 5498 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 5499 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 5500 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 5501 5502 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 5503 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 5504 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 5505 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 5506 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 5507 5508 #define S_FW_IQ_CMD_FL0CPRIO 3 5509 #define M_FW_IQ_CMD_FL0CPRIO 0x1 5510 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 5511 #define G_FW_IQ_CMD_FL0CPRIO(x) \ 5512 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 5513 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 5514 5515 #define S_FW_IQ_CMD_FL0PADEN 2 5516 #define M_FW_IQ_CMD_FL0PADEN 0x1 5517 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 5518 #define G_FW_IQ_CMD_FL0PADEN(x) \ 5519 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 5520 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 5521 5522 #define S_FW_IQ_CMD_FL0PACKEN 1 5523 #define M_FW_IQ_CMD_FL0PACKEN 0x1 5524 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 5525 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 5526 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 5527 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 5528 5529 #define S_FW_IQ_CMD_FL0CONGEN 0 5530 #define M_FW_IQ_CMD_FL0CONGEN 0x1 5531 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 5532 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 5533 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 5534 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 5535 5536 #define S_FW_IQ_CMD_FL0DCAEN 15 5537 #define M_FW_IQ_CMD_FL0DCAEN 0x1 5538 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 5539 #define G_FW_IQ_CMD_FL0DCAEN(x) \ 5540 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 5541 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 5542 5543 #define S_FW_IQ_CMD_FL0DCACPU 10 5544 #define M_FW_IQ_CMD_FL0DCACPU 0x1f 5545 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 5546 #define G_FW_IQ_CMD_FL0DCACPU(x) \ 5547 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 5548 5549 #define S_FW_IQ_CMD_FL0FBMIN 7 5550 #define M_FW_IQ_CMD_FL0FBMIN 0x7 5551 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 5552 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 5553 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 5554 5555 #define S_FW_IQ_CMD_FL0FBMAX 4 5556 #define M_FW_IQ_CMD_FL0FBMAX 0x7 5557 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 5558 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 5559 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 5560 5561 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 5562 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 5563 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 5564 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 5565 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 5566 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 5567 5568 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 5569 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 5570 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 5571 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 5572 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 5573 5574 #define S_FW_IQ_CMD_FL1CNGCHMAP 20 5575 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 5576 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 5577 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 5578 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 5579 5580 #define S_FW_IQ_CMD_FL1CONGDROP 16 5581 #define M_FW_IQ_CMD_FL1CONGDROP 0x1 5582 #define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP) 5583 #define G_FW_IQ_CMD_FL1CONGDROP(x) \ 5584 (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP) 5585 #define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U) 5586 5587 #define S_FW_IQ_CMD_FL1CACHELOCK 15 5588 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 5589 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 5590 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 5591 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 5592 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 5593 5594 #define S_FW_IQ_CMD_FL1DBP 14 5595 #define M_FW_IQ_CMD_FL1DBP 0x1 5596 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 5597 #define G_FW_IQ_CMD_FL1DBP(x) \ 5598 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 5599 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 5600 5601 #define S_FW_IQ_CMD_FL1DATANS 13 5602 #define M_FW_IQ_CMD_FL1DATANS 0x1 5603 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 5604 #define G_FW_IQ_CMD_FL1DATANS(x) \ 5605 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 5606 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 5607 5608 #define S_FW_IQ_CMD_FL1DATARO 12 5609 #define M_FW_IQ_CMD_FL1DATARO 0x1 5610 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 5611 #define G_FW_IQ_CMD_FL1DATARO(x) \ 5612 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 5613 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 5614 5615 #define S_FW_IQ_CMD_FL1CONGCIF 11 5616 #define M_FW_IQ_CMD_FL1CONGCIF 0x1 5617 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 5618 #define G_FW_IQ_CMD_FL1CONGCIF(x) \ 5619 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 5620 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 5621 5622 #define S_FW_IQ_CMD_FL1ONCHIP 10 5623 #define M_FW_IQ_CMD_FL1ONCHIP 0x1 5624 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 5625 #define G_FW_IQ_CMD_FL1ONCHIP(x) \ 5626 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 5627 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 5628 5629 #define S_FW_IQ_CMD_FL1STATUSPGNS 9 5630 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 5631 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 5632 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 5633 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 5634 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 5635 5636 #define S_FW_IQ_CMD_FL1STATUSPGRO 8 5637 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 5638 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 5639 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 5640 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 5641 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 5642 5643 #define S_FW_IQ_CMD_FL1FETCHNS 7 5644 #define M_FW_IQ_CMD_FL1FETCHNS 0x1 5645 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 5646 #define G_FW_IQ_CMD_FL1FETCHNS(x) \ 5647 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 5648 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 5649 5650 #define S_FW_IQ_CMD_FL1FETCHRO 6 5651 #define M_FW_IQ_CMD_FL1FETCHRO 0x1 5652 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 5653 #define G_FW_IQ_CMD_FL1FETCHRO(x) \ 5654 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 5655 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 5656 5657 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 5658 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 5659 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 5660 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 5661 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 5662 5663 #define S_FW_IQ_CMD_FL1CPRIO 3 5664 #define M_FW_IQ_CMD_FL1CPRIO 0x1 5665 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 5666 #define G_FW_IQ_CMD_FL1CPRIO(x) \ 5667 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 5668 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 5669 5670 #define S_FW_IQ_CMD_FL1PADEN 2 5671 #define M_FW_IQ_CMD_FL1PADEN 0x1 5672 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 5673 #define G_FW_IQ_CMD_FL1PADEN(x) \ 5674 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 5675 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 5676 5677 #define S_FW_IQ_CMD_FL1PACKEN 1 5678 #define M_FW_IQ_CMD_FL1PACKEN 0x1 5679 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 5680 #define G_FW_IQ_CMD_FL1PACKEN(x) \ 5681 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 5682 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 5683 5684 #define S_FW_IQ_CMD_FL1CONGEN 0 5685 #define M_FW_IQ_CMD_FL1CONGEN 0x1 5686 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 5687 #define G_FW_IQ_CMD_FL1CONGEN(x) \ 5688 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 5689 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 5690 5691 #define S_FW_IQ_CMD_FL1DCAEN 15 5692 #define M_FW_IQ_CMD_FL1DCAEN 0x1 5693 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 5694 #define G_FW_IQ_CMD_FL1DCAEN(x) \ 5695 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 5696 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 5697 5698 #define S_FW_IQ_CMD_FL1DCACPU 10 5699 #define M_FW_IQ_CMD_FL1DCACPU 0x1f 5700 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 5701 #define G_FW_IQ_CMD_FL1DCACPU(x) \ 5702 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 5703 5704 #define S_FW_IQ_CMD_FL1FBMIN 7 5705 #define M_FW_IQ_CMD_FL1FBMIN 0x7 5706 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 5707 #define G_FW_IQ_CMD_FL1FBMIN(x) \ 5708 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 5709 5710 #define S_FW_IQ_CMD_FL1FBMAX 4 5711 #define M_FW_IQ_CMD_FL1FBMAX 0x7 5712 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 5713 #define G_FW_IQ_CMD_FL1FBMAX(x) \ 5714 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 5715 5716 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 5717 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 5718 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 5719 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 5720 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 5721 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 5722 5723 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 5724 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 5725 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 5726 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 5727 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 5728 5729 struct fw_eq_mngt_cmd { 5730 __be32 op_to_vfn; 5731 __be32 alloc_to_len16; 5732 __be32 cmpliqid_eqid; 5733 __be32 physeqid_pkd; 5734 __be32 fetchszm_to_iqid; 5735 __be32 dcaen_to_eqsize; 5736 __be64 eqaddr; 5737 }; 5738 5739 #define S_FW_EQ_MNGT_CMD_PFN 8 5740 #define M_FW_EQ_MNGT_CMD_PFN 0x7 5741 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 5742 #define G_FW_EQ_MNGT_CMD_PFN(x) \ 5743 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 5744 5745 #define S_FW_EQ_MNGT_CMD_VFN 0 5746 #define M_FW_EQ_MNGT_CMD_VFN 0xff 5747 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 5748 #define G_FW_EQ_MNGT_CMD_VFN(x) \ 5749 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 5750 5751 #define S_FW_EQ_MNGT_CMD_ALLOC 31 5752 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 5753 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 5754 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 5755 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 5756 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 5757 5758 #define S_FW_EQ_MNGT_CMD_FREE 30 5759 #define M_FW_EQ_MNGT_CMD_FREE 0x1 5760 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 5761 #define G_FW_EQ_MNGT_CMD_FREE(x) \ 5762 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 5763 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 5764 5765 #define S_FW_EQ_MNGT_CMD_MODIFY 29 5766 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 5767 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 5768 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 5769 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 5770 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 5771 5772 #define S_FW_EQ_MNGT_CMD_EQSTART 28 5773 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 5774 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 5775 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 5776 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 5777 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 5778 5779 #define S_FW_EQ_MNGT_CMD_EQSTOP 27 5780 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 5781 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 5782 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 5783 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 5784 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 5785 5786 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 5787 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 5788 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 5789 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 5790 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 5791 5792 #define S_FW_EQ_MNGT_CMD_EQID 0 5793 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff 5794 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 5795 #define G_FW_EQ_MNGT_CMD_EQID(x) \ 5796 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 5797 5798 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 5799 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 5800 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 5801 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 5802 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 5803 5804 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 5805 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 5806 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 5807 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 5808 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 5809 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 5810 5811 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 5812 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 5813 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 5814 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 5815 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 5816 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 5817 5818 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 5819 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 5820 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 5821 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 5822 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 5823 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 5824 5825 #define S_FW_EQ_MNGT_CMD_FETCHNS 23 5826 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 5827 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 5828 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 5829 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 5830 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 5831 5832 #define S_FW_EQ_MNGT_CMD_FETCHRO 22 5833 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 5834 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 5835 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 5836 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 5837 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 5838 5839 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 5840 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 5841 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 5842 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 5843 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 5844 5845 #define S_FW_EQ_MNGT_CMD_CPRIO 19 5846 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 5847 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 5848 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 5849 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 5850 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 5851 5852 #define S_FW_EQ_MNGT_CMD_ONCHIP 18 5853 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 5854 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 5855 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 5856 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 5857 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 5858 5859 #define S_FW_EQ_MNGT_CMD_PCIECHN 16 5860 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 5861 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 5862 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 5863 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 5864 5865 #define S_FW_EQ_MNGT_CMD_IQID 0 5866 #define M_FW_EQ_MNGT_CMD_IQID 0xffff 5867 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 5868 #define G_FW_EQ_MNGT_CMD_IQID(x) \ 5869 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 5870 5871 #define S_FW_EQ_MNGT_CMD_DCAEN 31 5872 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 5873 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 5874 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 5875 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 5876 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 5877 5878 #define S_FW_EQ_MNGT_CMD_DCACPU 26 5879 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 5880 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 5881 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 5882 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 5883 5884 #define S_FW_EQ_MNGT_CMD_FBMIN 23 5885 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 5886 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 5887 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 5888 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 5889 5890 #define S_FW_EQ_MNGT_CMD_FBMAX 20 5891 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 5892 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 5893 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 5894 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 5895 5896 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 5897 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 5898 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5899 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5900 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5901 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5902 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 5903 5904 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 5905 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 5906 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5907 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 5908 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5909 5910 #define S_FW_EQ_MNGT_CMD_EQSIZE 0 5911 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 5912 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 5913 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 5914 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 5915 5916 struct fw_eq_eth_cmd { 5917 __be32 op_to_vfn; 5918 __be32 alloc_to_len16; 5919 __be32 eqid_pkd; 5920 __be32 physeqid_pkd; 5921 __be32 fetchszm_to_iqid; 5922 __be32 dcaen_to_eqsize; 5923 __be64 eqaddr; 5924 __be32 autoequiqe_to_viid; 5925 __be32 timeren_timerix; 5926 __be64 r9; 5927 }; 5928 5929 #define S_FW_EQ_ETH_CMD_PFN 8 5930 #define M_FW_EQ_ETH_CMD_PFN 0x7 5931 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 5932 #define G_FW_EQ_ETH_CMD_PFN(x) \ 5933 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 5934 5935 #define S_FW_EQ_ETH_CMD_VFN 0 5936 #define M_FW_EQ_ETH_CMD_VFN 0xff 5937 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 5938 #define G_FW_EQ_ETH_CMD_VFN(x) \ 5939 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 5940 5941 #define S_FW_EQ_ETH_CMD_ALLOC 31 5942 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 5943 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 5944 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 5945 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 5946 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 5947 5948 #define S_FW_EQ_ETH_CMD_FREE 30 5949 #define M_FW_EQ_ETH_CMD_FREE 0x1 5950 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 5951 #define G_FW_EQ_ETH_CMD_FREE(x) \ 5952 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 5953 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 5954 5955 #define S_FW_EQ_ETH_CMD_MODIFY 29 5956 #define M_FW_EQ_ETH_CMD_MODIFY 0x1 5957 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 5958 #define G_FW_EQ_ETH_CMD_MODIFY(x) \ 5959 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 5960 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 5961 5962 #define S_FW_EQ_ETH_CMD_EQSTART 28 5963 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 5964 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 5965 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 5966 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 5967 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 5968 5969 #define S_FW_EQ_ETH_CMD_EQSTOP 27 5970 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 5971 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 5972 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 5973 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 5974 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 5975 5976 #define S_FW_EQ_ETH_CMD_EQID 0 5977 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 5978 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 5979 #define G_FW_EQ_ETH_CMD_EQID(x) \ 5980 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 5981 5982 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 5983 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 5984 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 5985 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 5986 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 5987 5988 #define S_FW_EQ_ETH_CMD_FETCHSZM 26 5989 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 5990 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 5991 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 5992 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 5993 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 5994 5995 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 5996 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 5997 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 5998 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 5999 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 6000 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 6001 6002 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 6003 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 6004 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 6005 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 6006 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 6007 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 6008 6009 #define S_FW_EQ_ETH_CMD_FETCHNS 23 6010 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 6011 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 6012 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 6013 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 6014 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 6015 6016 #define S_FW_EQ_ETH_CMD_FETCHRO 22 6017 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 6018 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 6019 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 6020 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 6021 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 6022 6023 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 6024 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 6025 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 6026 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 6027 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 6028 6029 #define S_FW_EQ_ETH_CMD_CPRIO 19 6030 #define M_FW_EQ_ETH_CMD_CPRIO 0x1 6031 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 6032 #define G_FW_EQ_ETH_CMD_CPRIO(x) \ 6033 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 6034 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 6035 6036 #define S_FW_EQ_ETH_CMD_ONCHIP 18 6037 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 6038 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 6039 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 6040 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 6041 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 6042 6043 #define S_FW_EQ_ETH_CMD_PCIECHN 16 6044 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 6045 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 6046 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 6047 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 6048 6049 #define S_FW_EQ_ETH_CMD_IQID 0 6050 #define M_FW_EQ_ETH_CMD_IQID 0xffff 6051 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 6052 #define G_FW_EQ_ETH_CMD_IQID(x) \ 6053 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 6054 6055 #define S_FW_EQ_ETH_CMD_DCAEN 31 6056 #define M_FW_EQ_ETH_CMD_DCAEN 0x1 6057 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 6058 #define G_FW_EQ_ETH_CMD_DCAEN(x) \ 6059 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 6060 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 6061 6062 #define S_FW_EQ_ETH_CMD_DCACPU 26 6063 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f 6064 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 6065 #define G_FW_EQ_ETH_CMD_DCACPU(x) \ 6066 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 6067 6068 #define S_FW_EQ_ETH_CMD_FBMIN 23 6069 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 6070 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 6071 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 6072 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 6073 6074 #define S_FW_EQ_ETH_CMD_FBMAX 20 6075 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 6076 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 6077 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 6078 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 6079 6080 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 6081 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 6082 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 6083 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 6084 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 6085 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 6086 6087 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 6088 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 6089 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 6090 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 6091 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 6092 6093 #define S_FW_EQ_ETH_CMD_EQSIZE 0 6094 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 6095 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 6096 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 6097 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 6098 6099 #define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31 6100 #define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1 6101 #define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE) 6102 #define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \ 6103 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE) 6104 #define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U) 6105 6106 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 6107 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 6108 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 6109 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 6110 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 6111 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 6112 6113 #define S_FW_EQ_ETH_CMD_VIID 16 6114 #define M_FW_EQ_ETH_CMD_VIID 0xfff 6115 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 6116 #define G_FW_EQ_ETH_CMD_VIID(x) \ 6117 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 6118 6119 #define S_FW_EQ_ETH_CMD_TIMEREN 3 6120 #define M_FW_EQ_ETH_CMD_TIMEREN 0x1 6121 #define V_FW_EQ_ETH_CMD_TIMEREN(x) ((x) << S_FW_EQ_ETH_CMD_TIMEREN) 6122 #define G_FW_EQ_ETH_CMD_TIMEREN(x) \ 6123 (((x) >> S_FW_EQ_ETH_CMD_TIMEREN) & M_FW_EQ_ETH_CMD_TIMEREN) 6124 #define F_FW_EQ_ETH_CMD_TIMEREN V_FW_EQ_ETH_CMD_TIMEREN(1U) 6125 6126 #define S_FW_EQ_ETH_CMD_TIMERIX 0 6127 #define M_FW_EQ_ETH_CMD_TIMERIX 0x7 6128 #define V_FW_EQ_ETH_CMD_TIMERIX(x) ((x) << S_FW_EQ_ETH_CMD_TIMERIX) 6129 #define G_FW_EQ_ETH_CMD_TIMERIX(x) \ 6130 (((x) >> S_FW_EQ_ETH_CMD_TIMERIX) & M_FW_EQ_ETH_CMD_TIMERIX) 6131 6132 struct fw_eq_ctrl_cmd { 6133 __be32 op_to_vfn; 6134 __be32 alloc_to_len16; 6135 __be32 cmpliqid_eqid; 6136 __be32 physeqid_pkd; 6137 __be32 fetchszm_to_iqid; 6138 __be32 dcaen_to_eqsize; 6139 __be64 eqaddr; 6140 }; 6141 6142 #define S_FW_EQ_CTRL_CMD_PFN 8 6143 #define M_FW_EQ_CTRL_CMD_PFN 0x7 6144 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 6145 #define G_FW_EQ_CTRL_CMD_PFN(x) \ 6146 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 6147 6148 #define S_FW_EQ_CTRL_CMD_VFN 0 6149 #define M_FW_EQ_CTRL_CMD_VFN 0xff 6150 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 6151 #define G_FW_EQ_CTRL_CMD_VFN(x) \ 6152 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 6153 6154 #define S_FW_EQ_CTRL_CMD_ALLOC 31 6155 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 6156 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 6157 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 6158 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 6159 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 6160 6161 #define S_FW_EQ_CTRL_CMD_FREE 30 6162 #define M_FW_EQ_CTRL_CMD_FREE 0x1 6163 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 6164 #define G_FW_EQ_CTRL_CMD_FREE(x) \ 6165 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 6166 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 6167 6168 #define S_FW_EQ_CTRL_CMD_MODIFY 29 6169 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 6170 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 6171 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 6172 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 6173 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 6174 6175 #define S_FW_EQ_CTRL_CMD_EQSTART 28 6176 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 6177 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 6178 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 6179 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 6180 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 6181 6182 #define S_FW_EQ_CTRL_CMD_EQSTOP 27 6183 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 6184 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 6185 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 6186 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 6187 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 6188 6189 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 6190 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 6191 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 6192 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 6193 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 6194 6195 #define S_FW_EQ_CTRL_CMD_EQID 0 6196 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 6197 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 6198 #define G_FW_EQ_CTRL_CMD_EQID(x) \ 6199 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 6200 6201 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 6202 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 6203 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 6204 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 6205 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 6206 6207 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 6208 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 6209 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 6210 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 6211 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 6212 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 6213 6214 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 6215 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 6216 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 6217 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 6218 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 6219 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 6220 6221 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 6222 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 6223 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 6224 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 6225 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 6226 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 6227 6228 #define S_FW_EQ_CTRL_CMD_FETCHNS 23 6229 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 6230 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 6231 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 6232 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 6233 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 6234 6235 #define S_FW_EQ_CTRL_CMD_FETCHRO 22 6236 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 6237 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 6238 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 6239 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 6240 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 6241 6242 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 6243 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 6244 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 6245 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 6246 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 6247 6248 #define S_FW_EQ_CTRL_CMD_CPRIO 19 6249 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 6250 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 6251 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 6252 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 6253 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 6254 6255 #define S_FW_EQ_CTRL_CMD_ONCHIP 18 6256 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 6257 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 6258 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 6259 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 6260 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 6261 6262 #define S_FW_EQ_CTRL_CMD_PCIECHN 16 6263 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 6264 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 6265 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 6266 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 6267 6268 #define S_FW_EQ_CTRL_CMD_IQID 0 6269 #define M_FW_EQ_CTRL_CMD_IQID 0xffff 6270 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 6271 #define G_FW_EQ_CTRL_CMD_IQID(x) \ 6272 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 6273 6274 #define S_FW_EQ_CTRL_CMD_DCAEN 31 6275 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 6276 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 6277 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 6278 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 6279 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 6280 6281 #define S_FW_EQ_CTRL_CMD_DCACPU 26 6282 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 6283 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 6284 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 6285 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 6286 6287 #define S_FW_EQ_CTRL_CMD_FBMIN 23 6288 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 6289 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 6290 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 6291 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 6292 6293 #define S_FW_EQ_CTRL_CMD_FBMAX 20 6294 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 6295 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 6296 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 6297 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 6298 6299 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 6300 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 6301 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 6302 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 6303 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 6304 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 6305 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 6306 6307 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 6308 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 6309 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 6310 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 6311 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 6312 6313 #define S_FW_EQ_CTRL_CMD_EQSIZE 0 6314 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 6315 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 6316 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 6317 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 6318 6319 struct fw_eq_ofld_cmd { 6320 __be32 op_to_vfn; 6321 __be32 alloc_to_len16; 6322 __be32 eqid_pkd; 6323 __be32 physeqid_pkd; 6324 __be32 fetchszm_to_iqid; 6325 __be32 dcaen_to_eqsize; 6326 __be64 eqaddr; 6327 }; 6328 6329 #define S_FW_EQ_OFLD_CMD_PFN 8 6330 #define M_FW_EQ_OFLD_CMD_PFN 0x7 6331 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 6332 #define G_FW_EQ_OFLD_CMD_PFN(x) \ 6333 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 6334 6335 #define S_FW_EQ_OFLD_CMD_VFN 0 6336 #define M_FW_EQ_OFLD_CMD_VFN 0xff 6337 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 6338 #define G_FW_EQ_OFLD_CMD_VFN(x) \ 6339 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 6340 6341 #define S_FW_EQ_OFLD_CMD_ALLOC 31 6342 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 6343 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 6344 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 6345 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 6346 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 6347 6348 #define S_FW_EQ_OFLD_CMD_FREE 30 6349 #define M_FW_EQ_OFLD_CMD_FREE 0x1 6350 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 6351 #define G_FW_EQ_OFLD_CMD_FREE(x) \ 6352 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 6353 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 6354 6355 #define S_FW_EQ_OFLD_CMD_MODIFY 29 6356 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 6357 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 6358 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 6359 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 6360 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 6361 6362 #define S_FW_EQ_OFLD_CMD_EQSTART 28 6363 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 6364 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 6365 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 6366 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 6367 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 6368 6369 #define S_FW_EQ_OFLD_CMD_EQSTOP 27 6370 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 6371 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 6372 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 6373 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 6374 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 6375 6376 #define S_FW_EQ_OFLD_CMD_EQID 0 6377 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff 6378 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 6379 #define G_FW_EQ_OFLD_CMD_EQID(x) \ 6380 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 6381 6382 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 6383 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 6384 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 6385 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 6386 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 6387 6388 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 6389 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 6390 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 6391 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 6392 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 6393 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 6394 6395 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 6396 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 6397 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 6398 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 6399 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 6400 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 6401 6402 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 6403 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 6404 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 6405 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 6406 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 6407 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 6408 6409 #define S_FW_EQ_OFLD_CMD_FETCHNS 23 6410 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 6411 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 6412 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 6413 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 6414 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 6415 6416 #define S_FW_EQ_OFLD_CMD_FETCHRO 22 6417 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 6418 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 6419 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 6420 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 6421 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 6422 6423 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 6424 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 6425 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 6426 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 6427 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 6428 6429 #define S_FW_EQ_OFLD_CMD_CPRIO 19 6430 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 6431 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 6432 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 6433 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 6434 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 6435 6436 #define S_FW_EQ_OFLD_CMD_ONCHIP 18 6437 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 6438 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 6439 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 6440 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 6441 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 6442 6443 #define S_FW_EQ_OFLD_CMD_PCIECHN 16 6444 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 6445 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 6446 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 6447 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 6448 6449 #define S_FW_EQ_OFLD_CMD_IQID 0 6450 #define M_FW_EQ_OFLD_CMD_IQID 0xffff 6451 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 6452 #define G_FW_EQ_OFLD_CMD_IQID(x) \ 6453 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 6454 6455 #define S_FW_EQ_OFLD_CMD_DCAEN 31 6456 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 6457 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 6458 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 6459 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 6460 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 6461 6462 #define S_FW_EQ_OFLD_CMD_DCACPU 26 6463 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 6464 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 6465 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 6466 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 6467 6468 #define S_FW_EQ_OFLD_CMD_FBMIN 23 6469 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 6470 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 6471 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 6472 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 6473 6474 #define S_FW_EQ_OFLD_CMD_FBMAX 20 6475 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 6476 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 6477 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 6478 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 6479 6480 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 6481 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 6482 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 6483 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 6484 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 6485 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 6486 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 6487 6488 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 6489 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 6490 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 6491 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 6492 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 6493 6494 #define S_FW_EQ_OFLD_CMD_EQSIZE 0 6495 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 6496 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 6497 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 6498 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 6499 6500 /* Macros for VIID parsing: 6501 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 6502 #define S_FW_VIID_PFN 8 6503 #define M_FW_VIID_PFN 0x7 6504 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 6505 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 6506 6507 #define S_FW_VIID_VIVLD 7 6508 #define M_FW_VIID_VIVLD 0x1 6509 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 6510 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 6511 6512 #define S_FW_VIID_VIN 0 6513 #define M_FW_VIID_VIN 0x7F 6514 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 6515 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 6516 6517 /* Macros for VIID parsing: 6518 VIID - [11:9] PFN, [8] VI Valid, [7:0] VI number */ 6519 #define S_FW_256VIID_PFN 9 6520 #define M_FW_256VIID_PFN 0x7 6521 #define V_FW_256VIID_PFN(x) ((x) << S_FW_256VIID_PFN) 6522 #define G_FW_256VIID_PFN(x) (((x) >> S_FW_256VIID_PFN) & M_FW_256VIID_PFN) 6523 6524 #define S_FW_256VIID_VIVLD 8 6525 #define M_FW_256VIID_VIVLD 0x1 6526 #define V_FW_256VIID_VIVLD(x) ((x) << S_FW_256VIID_VIVLD) 6527 #define G_FW_256VIID_VIVLD(x) (((x) >> S_FW_256VIID_VIVLD) & M_FW_256VIID_VIVLD) 6528 6529 #define S_FW_256VIID_VIN 0 6530 #define M_FW_256VIID_VIN 0xFF 6531 #define V_FW_256VIID_VIN(x) ((x) << S_FW_256VIID_VIN) 6532 #define G_FW_256VIID_VIN(x) (((x) >> S_FW_256VIID_VIN) & M_FW_256VIID_VIN) 6533 6534 enum fw_vi_func { 6535 FW_VI_FUNC_ETH, 6536 FW_VI_FUNC_OFLD, 6537 FW_VI_FUNC_IWARP, 6538 FW_VI_FUNC_OPENISCSI, 6539 FW_VI_FUNC_OPENFCOE, 6540 FW_VI_FUNC_FOISCSI, 6541 FW_VI_FUNC_FOFCOE, 6542 FW_VI_FUNC_FW, 6543 }; 6544 6545 struct fw_vi_cmd { 6546 __be32 op_to_vfn; 6547 __be32 alloc_to_len16; 6548 __be16 type_to_viid; 6549 __u8 mac[6]; 6550 __u8 portid_pkd; 6551 __u8 nmac; 6552 __u8 nmac0[6]; 6553 __be16 norss_rsssize; 6554 __u8 nmac1[6]; 6555 __be16 idsiiq_pkd; 6556 __u8 nmac2[6]; 6557 __be16 idseiq_pkd; 6558 __u8 nmac3[6]; 6559 __be64 r9; 6560 __be64 r10; 6561 }; 6562 6563 #define S_FW_VI_CMD_PFN 8 6564 #define M_FW_VI_CMD_PFN 0x7 6565 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 6566 #define G_FW_VI_CMD_PFN(x) \ 6567 (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 6568 6569 #define S_FW_VI_CMD_VFN 0 6570 #define M_FW_VI_CMD_VFN 0xff 6571 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 6572 #define G_FW_VI_CMD_VFN(x) \ 6573 (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 6574 6575 #define S_FW_VI_CMD_ALLOC 31 6576 #define M_FW_VI_CMD_ALLOC 0x1 6577 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 6578 #define G_FW_VI_CMD_ALLOC(x) \ 6579 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 6580 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 6581 6582 #define S_FW_VI_CMD_FREE 30 6583 #define M_FW_VI_CMD_FREE 0x1 6584 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 6585 #define G_FW_VI_CMD_FREE(x) \ 6586 (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 6587 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 6588 6589 #define S_FW_VI_CMD_VFVLD 24 6590 #define M_FW_VI_CMD_VFVLD 0x1 6591 #define V_FW_VI_CMD_VFVLD(x) ((x) << S_FW_VI_CMD_VFVLD) 6592 #define G_FW_VI_CMD_VFVLD(x) \ 6593 (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD) 6594 #define F_FW_VI_CMD_VFVLD V_FW_VI_CMD_VFVLD(1U) 6595 6596 #define S_FW_VI_CMD_VIN 16 6597 #define M_FW_VI_CMD_VIN 0xff 6598 #define V_FW_VI_CMD_VIN(x) ((x) << S_FW_VI_CMD_VIN) 6599 #define G_FW_VI_CMD_VIN(x) \ 6600 (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN) 6601 6602 #define S_FW_VI_CMD_TYPE 15 6603 #define M_FW_VI_CMD_TYPE 0x1 6604 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 6605 #define G_FW_VI_CMD_TYPE(x) \ 6606 (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 6607 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 6608 6609 #define S_FW_VI_CMD_FUNC 12 6610 #define M_FW_VI_CMD_FUNC 0x7 6611 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 6612 #define G_FW_VI_CMD_FUNC(x) \ 6613 (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 6614 6615 #define S_FW_VI_CMD_VIID 0 6616 #define M_FW_VI_CMD_VIID 0xfff 6617 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 6618 #define G_FW_VI_CMD_VIID(x) \ 6619 (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 6620 6621 #define S_FW_VI_CMD_PORTID 4 6622 #define M_FW_VI_CMD_PORTID 0xf 6623 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 6624 #define G_FW_VI_CMD_PORTID(x) \ 6625 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 6626 6627 #define S_FW_VI_CMD_NORSS 11 6628 #define M_FW_VI_CMD_NORSS 0x1 6629 #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 6630 #define G_FW_VI_CMD_NORSS(x) \ 6631 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 6632 #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 6633 6634 #define S_FW_VI_CMD_RSSSIZE 0 6635 #define M_FW_VI_CMD_RSSSIZE 0x7ff 6636 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 6637 #define G_FW_VI_CMD_RSSSIZE(x) \ 6638 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 6639 6640 #define S_FW_VI_CMD_IDSIIQ 0 6641 #define M_FW_VI_CMD_IDSIIQ 0x3ff 6642 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 6643 #define G_FW_VI_CMD_IDSIIQ(x) \ 6644 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 6645 6646 #define S_FW_VI_CMD_IDSEIQ 0 6647 #define M_FW_VI_CMD_IDSEIQ 0x3ff 6648 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 6649 #define G_FW_VI_CMD_IDSEIQ(x) \ 6650 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 6651 6652 /* Special VI_MAC command index ids */ 6653 #define FW_VI_MAC_ADD_MAC 0x3FF 6654 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 6655 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 6656 #define FW_VI_MAC_ID_BASED_FREE 0x3FC 6657 6658 enum fw_vi_mac_smac { 6659 FW_VI_MAC_MPS_TCAM_ENTRY, 6660 FW_VI_MAC_MPS_TCAM_ONLY, 6661 FW_VI_MAC_SMT_ONLY, 6662 FW_VI_MAC_SMT_AND_MPSTCAM 6663 }; 6664 6665 enum fw_vi_mac_result { 6666 FW_VI_MAC_R_SUCCESS, 6667 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 6668 FW_VI_MAC_R_SMAC_FAIL, 6669 FW_VI_MAC_R_F_ACL_CHECK 6670 }; 6671 6672 enum fw_vi_mac_entry_types { 6673 FW_VI_MAC_TYPE_EXACTMAC, 6674 FW_VI_MAC_TYPE_HASHVEC, 6675 FW_VI_MAC_TYPE_RAW, 6676 FW_VI_MAC_TYPE_EXACTMAC_VNI, 6677 }; 6678 6679 struct fw_vi_mac_cmd { 6680 __be32 op_to_viid; 6681 __be32 freemacs_to_len16; 6682 union fw_vi_mac { 6683 struct fw_vi_mac_exact { 6684 __be16 valid_to_idx; 6685 __u8 macaddr[6]; 6686 } exact[7]; 6687 struct fw_vi_mac_hash { 6688 __be64 hashvec; 6689 } hash; 6690 struct fw_vi_mac_raw { 6691 __be32 raw_idx_pkd; 6692 __be32 data0_pkd; 6693 __be32 data1[2]; 6694 __be64 data0m_pkd; 6695 __be32 data1m[2]; 6696 } raw; 6697 struct fw_vi_mac_vni { 6698 __be16 valid_to_idx; 6699 __u8 macaddr[6]; 6700 __be16 r7; 6701 __u8 macaddr_mask[6]; 6702 __be32 lookup_type_to_vni; 6703 __be32 vni_mask_pkd; 6704 } exact_vni[2]; 6705 } u; 6706 }; 6707 6708 #define S_FW_VI_MAC_CMD_SMTID 12 6709 #define M_FW_VI_MAC_CMD_SMTID 0xff 6710 #define V_FW_VI_MAC_CMD_SMTID(x) ((x) << S_FW_VI_MAC_CMD_SMTID) 6711 #define G_FW_VI_MAC_CMD_SMTID(x) \ 6712 (((x) >> S_FW_VI_MAC_CMD_SMTID) & M_FW_VI_MAC_CMD_SMTID) 6713 6714 #define S_FW_VI_MAC_CMD_VIID 0 6715 #define M_FW_VI_MAC_CMD_VIID 0xfff 6716 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 6717 #define G_FW_VI_MAC_CMD_VIID(x) \ 6718 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 6719 6720 #define S_FW_VI_MAC_CMD_FREEMACS 31 6721 #define M_FW_VI_MAC_CMD_FREEMACS 0x1 6722 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 6723 #define G_FW_VI_MAC_CMD_FREEMACS(x) \ 6724 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 6725 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 6726 6727 #define S_FW_VI_MAC_CMD_IS_SMAC 30 6728 #define M_FW_VI_MAC_CMD_IS_SMAC 0x1 6729 #define V_FW_VI_MAC_CMD_IS_SMAC(x) ((x) << S_FW_VI_MAC_CMD_IS_SMAC) 6730 #define G_FW_VI_MAC_CMD_IS_SMAC(x) \ 6731 (((x) >> S_FW_VI_MAC_CMD_IS_SMAC) & M_FW_VI_MAC_CMD_IS_SMAC) 6732 #define F_FW_VI_MAC_CMD_IS_SMAC V_FW_VI_MAC_CMD_IS_SMAC(1U) 6733 6734 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23 6735 #define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7 6736 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE) 6737 #define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \ 6738 (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE) 6739 6740 #define S_FW_VI_MAC_CMD_HASHUNIEN 22 6741 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 6742 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 6743 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 6744 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 6745 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 6746 6747 #define S_FW_VI_MAC_CMD_VALID 15 6748 #define M_FW_VI_MAC_CMD_VALID 0x1 6749 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 6750 #define G_FW_VI_MAC_CMD_VALID(x) \ 6751 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 6752 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 6753 6754 #define S_FW_VI_MAC_CMD_PRIO 12 6755 #define M_FW_VI_MAC_CMD_PRIO 0x7 6756 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 6757 #define G_FW_VI_MAC_CMD_PRIO(x) \ 6758 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 6759 6760 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 6761 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 6762 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 6763 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 6764 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 6765 6766 #define S_FW_VI_MAC_CMD_IDX 0 6767 #define M_FW_VI_MAC_CMD_IDX 0x3ff 6768 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 6769 #define G_FW_VI_MAC_CMD_IDX(x) \ 6770 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 6771 6772 #define S_FW_VI_MAC_CMD_RAW_IDX 16 6773 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff 6774 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX) 6775 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \ 6776 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX) 6777 6778 #define S_FW_VI_MAC_CMD_DATA0 0 6779 #define M_FW_VI_MAC_CMD_DATA0 0xffff 6780 #define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0) 6781 #define G_FW_VI_MAC_CMD_DATA0(x) \ 6782 (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0) 6783 6784 #define S_FW_VI_MAC_CMD_LOOKUP_TYPE 31 6785 #define M_FW_VI_MAC_CMD_LOOKUP_TYPE 0x1 6786 #define V_FW_VI_MAC_CMD_LOOKUP_TYPE(x) ((x) << S_FW_VI_MAC_CMD_LOOKUP_TYPE) 6787 #define G_FW_VI_MAC_CMD_LOOKUP_TYPE(x) \ 6788 (((x) >> S_FW_VI_MAC_CMD_LOOKUP_TYPE) & M_FW_VI_MAC_CMD_LOOKUP_TYPE) 6789 #define F_FW_VI_MAC_CMD_LOOKUP_TYPE V_FW_VI_MAC_CMD_LOOKUP_TYPE(1U) 6790 6791 #define S_FW_VI_MAC_CMD_DIP_HIT 30 6792 #define M_FW_VI_MAC_CMD_DIP_HIT 0x1 6793 #define V_FW_VI_MAC_CMD_DIP_HIT(x) ((x) << S_FW_VI_MAC_CMD_DIP_HIT) 6794 #define G_FW_VI_MAC_CMD_DIP_HIT(x) \ 6795 (((x) >> S_FW_VI_MAC_CMD_DIP_HIT) & M_FW_VI_MAC_CMD_DIP_HIT) 6796 #define F_FW_VI_MAC_CMD_DIP_HIT V_FW_VI_MAC_CMD_DIP_HIT(1U) 6797 6798 #define S_FW_VI_MAC_CMD_VNI 0 6799 #define M_FW_VI_MAC_CMD_VNI 0xffffff 6800 #define V_FW_VI_MAC_CMD_VNI(x) ((x) << S_FW_VI_MAC_CMD_VNI) 6801 #define G_FW_VI_MAC_CMD_VNI(x) \ 6802 (((x) >> S_FW_VI_MAC_CMD_VNI) & M_FW_VI_MAC_CMD_VNI) 6803 6804 /* Extracting loopback port number passed from driver. 6805 * as a part of fw_vi_mac_vni For non loopback entries 6806 * ignore the field and update port number from flowc. 6807 * Fw will ignore if physical port number received. 6808 * expected range (4-7). 6809 */ 6810 6811 #define S_FW_VI_MAC_CMD_PORT 24 6812 #define M_FW_VI_MAC_CMD_PORT 0x7 6813 #define V_FW_VI_MAC_CMD_PORT(x) ((x) << S_FW_VI_MAC_CMD_PORT) 6814 #define G_FW_VI_MAC_CMD_PORT(x) \ 6815 (((x) >> S_FW_VI_MAC_CMD_PORT) & M_FW_VI_MAC_CMD_PORT) 6816 6817 #define S_FW_VI_MAC_CMD_VNI_MASK 0 6818 #define M_FW_VI_MAC_CMD_VNI_MASK 0xffffff 6819 #define V_FW_VI_MAC_CMD_VNI_MASK(x) ((x) << S_FW_VI_MAC_CMD_VNI_MASK) 6820 #define G_FW_VI_MAC_CMD_VNI_MASK(x) \ 6821 (((x) >> S_FW_VI_MAC_CMD_VNI_MASK) & M_FW_VI_MAC_CMD_VNI_MASK) 6822 6823 /* T4 max MTU supported */ 6824 #define T4_MAX_MTU_SUPPORTED 9600 6825 #define FW_RXMODE_MTU_NO_CHG 65535 6826 6827 struct fw_vi_rxmode_cmd { 6828 __be32 op_to_viid; 6829 __be32 retval_len16; 6830 __be32 mtu_to_vlanexen; 6831 __be32 r4_lo; 6832 }; 6833 6834 #define S_FW_VI_RXMODE_CMD_VIID 0 6835 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 6836 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 6837 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 6838 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 6839 6840 #define S_FW_VI_RXMODE_CMD_MTU 16 6841 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 6842 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 6843 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 6844 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 6845 6846 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 6847 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 6848 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 6849 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 6850 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 6851 6852 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 6853 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 6854 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6855 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 6856 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6857 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 6858 6859 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 6860 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 6861 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6862 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 6863 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6864 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 6865 6866 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 6867 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 6868 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 6869 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 6870 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 6871 6872 struct fw_vi_enable_cmd { 6873 __be32 op_to_viid; 6874 __be32 ien_to_len16; 6875 __be16 blinkdur; 6876 __be16 r3; 6877 __be32 r4; 6878 }; 6879 6880 #define S_FW_VI_ENABLE_CMD_VIID 0 6881 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 6882 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 6883 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 6884 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 6885 6886 #define S_FW_VI_ENABLE_CMD_IEN 31 6887 #define M_FW_VI_ENABLE_CMD_IEN 0x1 6888 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 6889 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 6890 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 6891 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 6892 6893 #define S_FW_VI_ENABLE_CMD_EEN 30 6894 #define M_FW_VI_ENABLE_CMD_EEN 0x1 6895 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 6896 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 6897 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 6898 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 6899 6900 #define S_FW_VI_ENABLE_CMD_LED 29 6901 #define M_FW_VI_ENABLE_CMD_LED 0x1 6902 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 6903 #define G_FW_VI_ENABLE_CMD_LED(x) \ 6904 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 6905 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 6906 6907 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 6908 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 6909 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 6910 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 6911 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 6912 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 6913 6914 /* VI VF stats offset definitions */ 6915 #define VI_VF_NUM_STATS 16 6916 enum fw_vi_stats_vf_index { 6917 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 6918 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 6919 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 6920 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 6921 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 6922 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 6923 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 6924 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 6925 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 6926 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 6927 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 6928 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 6929 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 6930 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 6931 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 6932 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 6933 }; 6934 6935 /* VI PF stats offset definitions */ 6936 #define VI_PF_NUM_STATS 17 6937 enum fw_vi_stats_pf_index { 6938 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 6939 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 6940 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 6941 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 6942 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 6943 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 6944 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 6945 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 6946 FW_VI_PF_STAT_RX_BYTES_IX, 6947 FW_VI_PF_STAT_RX_FRAMES_IX, 6948 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 6949 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 6950 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 6951 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 6952 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 6953 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 6954 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 6955 }; 6956 6957 struct fw_vi_stats_cmd { 6958 __be32 op_to_viid; 6959 __be32 retval_len16; 6960 union fw_vi_stats { 6961 struct fw_vi_stats_ctl { 6962 __be16 nstats_ix; 6963 __be16 r6; 6964 __be32 r7; 6965 __be64 stat0; 6966 __be64 stat1; 6967 __be64 stat2; 6968 __be64 stat3; 6969 __be64 stat4; 6970 __be64 stat5; 6971 } ctl; 6972 struct fw_vi_stats_pf { 6973 __be64 tx_bcast_bytes; 6974 __be64 tx_bcast_frames; 6975 __be64 tx_mcast_bytes; 6976 __be64 tx_mcast_frames; 6977 __be64 tx_ucast_bytes; 6978 __be64 tx_ucast_frames; 6979 __be64 tx_offload_bytes; 6980 __be64 tx_offload_frames; 6981 __be64 rx_pf_bytes; 6982 __be64 rx_pf_frames; 6983 __be64 rx_bcast_bytes; 6984 __be64 rx_bcast_frames; 6985 __be64 rx_mcast_bytes; 6986 __be64 rx_mcast_frames; 6987 __be64 rx_ucast_bytes; 6988 __be64 rx_ucast_frames; 6989 __be64 rx_err_frames; 6990 } pf; 6991 struct fw_vi_stats_vf { 6992 __be64 tx_bcast_bytes; 6993 __be64 tx_bcast_frames; 6994 __be64 tx_mcast_bytes; 6995 __be64 tx_mcast_frames; 6996 __be64 tx_ucast_bytes; 6997 __be64 tx_ucast_frames; 6998 __be64 tx_drop_frames; 6999 __be64 tx_offload_bytes; 7000 __be64 tx_offload_frames; 7001 __be64 rx_bcast_bytes; 7002 __be64 rx_bcast_frames; 7003 __be64 rx_mcast_bytes; 7004 __be64 rx_mcast_frames; 7005 __be64 rx_ucast_bytes; 7006 __be64 rx_ucast_frames; 7007 __be64 rx_err_frames; 7008 } vf; 7009 } u; 7010 }; 7011 7012 #define S_FW_VI_STATS_CMD_VIID 0 7013 #define M_FW_VI_STATS_CMD_VIID 0xfff 7014 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 7015 #define G_FW_VI_STATS_CMD_VIID(x) \ 7016 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 7017 7018 #define S_FW_VI_STATS_CMD_NSTATS 12 7019 #define M_FW_VI_STATS_CMD_NSTATS 0x7 7020 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 7021 #define G_FW_VI_STATS_CMD_NSTATS(x) \ 7022 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 7023 7024 #define S_FW_VI_STATS_CMD_IX 0 7025 #define M_FW_VI_STATS_CMD_IX 0x1f 7026 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 7027 #define G_FW_VI_STATS_CMD_IX(x) \ 7028 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 7029 7030 struct fw_acl_mac_cmd { 7031 __be32 op_to_vfn; 7032 __be32 en_to_len16; 7033 __u8 nmac; 7034 __u8 r3[7]; 7035 __be16 r4; 7036 __u8 macaddr0[6]; 7037 __be16 r5; 7038 __u8 macaddr1[6]; 7039 __be16 r6; 7040 __u8 macaddr2[6]; 7041 __be16 r7; 7042 __u8 macaddr3[6]; 7043 }; 7044 7045 #define S_FW_ACL_MAC_CMD_PFN 8 7046 #define M_FW_ACL_MAC_CMD_PFN 0x7 7047 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 7048 #define G_FW_ACL_MAC_CMD_PFN(x) \ 7049 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 7050 7051 #define S_FW_ACL_MAC_CMD_VFN 0 7052 #define M_FW_ACL_MAC_CMD_VFN 0xff 7053 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 7054 #define G_FW_ACL_MAC_CMD_VFN(x) \ 7055 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 7056 7057 #define S_FW_ACL_MAC_CMD_EN 31 7058 #define M_FW_ACL_MAC_CMD_EN 0x1 7059 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 7060 #define G_FW_ACL_MAC_CMD_EN(x) \ 7061 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 7062 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 7063 7064 struct fw_acl_vlan_cmd { 7065 __be32 op_to_vfn; 7066 __be32 en_to_len16; 7067 __u8 nvlan; 7068 __u8 dropnovlan_fm; 7069 __u8 r3_lo[6]; 7070 __be16 vlanid[16]; 7071 }; 7072 7073 #define S_FW_ACL_VLAN_CMD_PFN 8 7074 #define M_FW_ACL_VLAN_CMD_PFN 0x7 7075 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 7076 #define G_FW_ACL_VLAN_CMD_PFN(x) \ 7077 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 7078 7079 #define S_FW_ACL_VLAN_CMD_VFN 0 7080 #define M_FW_ACL_VLAN_CMD_VFN 0xff 7081 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 7082 #define G_FW_ACL_VLAN_CMD_VFN(x) \ 7083 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 7084 7085 #define S_FW_ACL_VLAN_CMD_EN 31 7086 #define M_FW_ACL_VLAN_CMD_EN 0x1 7087 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 7088 #define G_FW_ACL_VLAN_CMD_EN(x) \ 7089 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 7090 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 7091 7092 #define S_FW_ACL_VLAN_CMD_TRANSPARENT 30 7093 #define M_FW_ACL_VLAN_CMD_TRANSPARENT 0x1 7094 #define V_FW_ACL_VLAN_CMD_TRANSPARENT(x) \ 7095 ((x) << S_FW_ACL_VLAN_CMD_TRANSPARENT) 7096 #define G_FW_ACL_VLAN_CMD_TRANSPARENT(x) \ 7097 (((x) >> S_FW_ACL_VLAN_CMD_TRANSPARENT) & M_FW_ACL_VLAN_CMD_TRANSPARENT) 7098 #define F_FW_ACL_VLAN_CMD_TRANSPARENT V_FW_ACL_VLAN_CMD_TRANSPARENT(1U) 7099 7100 #define S_FW_ACL_VLAN_CMD_PMASK 16 7101 #define M_FW_ACL_VLAN_CMD_PMASK 0xf 7102 #define V_FW_ACL_VLAN_CMD_PMASK(x) ((x) << S_FW_ACL_VLAN_CMD_PMASK) 7103 #define G_FW_ACL_VLAN_CMD_PMASK(x) \ 7104 (((x) >> S_FW_ACL_VLAN_CMD_PMASK) & M_FW_ACL_VLAN_CMD_PMASK) 7105 7106 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 7107 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 7108 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 7109 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 7110 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 7111 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 7112 7113 #define S_FW_ACL_VLAN_CMD_FM 6 7114 #define M_FW_ACL_VLAN_CMD_FM 0x1 7115 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 7116 #define G_FW_ACL_VLAN_CMD_FM(x) \ 7117 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 7118 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 7119 7120 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */ 7121 enum fw_port_cap { 7122 FW_PORT_CAP_SPEED_100M = 0x0001, 7123 FW_PORT_CAP_SPEED_1G = 0x0002, 7124 FW_PORT_CAP_SPEED_25G = 0x0004, 7125 FW_PORT_CAP_SPEED_10G = 0x0008, 7126 FW_PORT_CAP_SPEED_40G = 0x0010, 7127 FW_PORT_CAP_SPEED_100G = 0x0020, 7128 FW_PORT_CAP_FC_RX = 0x0040, 7129 FW_PORT_CAP_FC_TX = 0x0080, 7130 FW_PORT_CAP_ANEG = 0x0100, 7131 FW_PORT_CAP_MDIAUTO = 0x0200, 7132 FW_PORT_CAP_MDISTRAIGHT = 0x0400, 7133 FW_PORT_CAP_FEC_RS = 0x0800, 7134 FW_PORT_CAP_FEC_BASER_RS = 0x1000, 7135 FW_PORT_CAP_FORCE_PAUSE = 0x2000, 7136 FW_PORT_CAP_802_3_PAUSE = 0x4000, 7137 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 7138 }; 7139 7140 #define S_FW_PORT_CAP_SPEED 0 7141 #define M_FW_PORT_CAP_SPEED 0x3f 7142 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 7143 #define G_FW_PORT_CAP_SPEED(x) \ 7144 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 7145 7146 #define S_FW_PORT_CAP_FC 6 7147 #define M_FW_PORT_CAP_FC 0x3 7148 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 7149 #define G_FW_PORT_CAP_FC(x) \ 7150 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 7151 7152 #define S_FW_PORT_CAP_ANEG 8 7153 #define M_FW_PORT_CAP_ANEG 0x1 7154 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 7155 #define G_FW_PORT_CAP_ANEG(x) \ 7156 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 7157 7158 #define S_FW_PORT_CAP_FEC 11 7159 #define M_FW_PORT_CAP_FEC 0x3 7160 #define V_FW_PORT_CAP_FEC(x) ((x) << S_FW_PORT_CAP_FEC) 7161 #define G_FW_PORT_CAP_FEC(x) \ 7162 (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC) 7163 7164 #define S_FW_PORT_CAP_FORCE_PAUSE 13 7165 #define M_FW_PORT_CAP_FORCE_PAUSE 0x1 7166 #define V_FW_PORT_CAP_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP_FORCE_PAUSE) 7167 #define G_FW_PORT_CAP_FORCE_PAUSE(x) \ 7168 (((x) >> S_FW_PORT_CAP_FORCE_PAUSE) & M_FW_PORT_CAP_FORCE_PAUSE) 7169 7170 #define S_FW_PORT_CAP_802_3 14 7171 #define M_FW_PORT_CAP_802_3 0x3 7172 #define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3) 7173 #define G_FW_PORT_CAP_802_3(x) \ 7174 (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3) 7175 7176 enum fw_port_mdi { 7177 FW_PORT_CAP_MDI_UNCHANGED, 7178 FW_PORT_CAP_MDI_AUTO, 7179 FW_PORT_CAP_MDI_F_STRAIGHT, 7180 FW_PORT_CAP_MDI_F_CROSSOVER 7181 }; 7182 7183 #define S_FW_PORT_CAP_MDI 9 7184 #define M_FW_PORT_CAP_MDI 3 7185 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 7186 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 7187 7188 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 7189 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL 7190 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL 7191 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL 7192 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL 7193 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL 7194 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL 7195 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL 7196 #define FW_PORT_CAP32_SPEED_200G 0x00000080UL 7197 #define FW_PORT_CAP32_SPEED_400G 0x00000100UL 7198 #define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL 7199 #define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL 7200 #define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL 7201 #define FW_PORT_CAP32_RESERVED1 0x0000f000UL 7202 #define FW_PORT_CAP32_FC_RX 0x00010000UL 7203 #define FW_PORT_CAP32_FC_TX 0x00020000UL 7204 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 7205 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 7206 #define FW_PORT_CAP32_ANEG 0x00100000UL 7207 #define FW_PORT_CAP32_MDIAUTO 0x00200000UL 7208 #define FW_PORT_CAP32_MDISTRAIGHT 0x00400000UL 7209 #define FW_PORT_CAP32_FEC_RS 0x00800000UL 7210 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 7211 #define FW_PORT_CAP32_FEC_NO_FEC 0x02000000UL 7212 #define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL 7213 #define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL 7214 #define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL 7215 #define FW_PORT_CAP32_FORCE_FEC 0x20000000UL 7216 #define FW_PORT_CAP32_RESERVED2 0xc0000000UL 7217 7218 #define S_FW_PORT_CAP32_SPEED 0 7219 #define M_FW_PORT_CAP32_SPEED 0xfff 7220 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED) 7221 #define G_FW_PORT_CAP32_SPEED(x) \ 7222 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED) 7223 7224 #define S_FW_PORT_CAP32_FC 16 7225 #define M_FW_PORT_CAP32_FC 0x3 7226 #define V_FW_PORT_CAP32_FC(x) ((x) << S_FW_PORT_CAP32_FC) 7227 #define G_FW_PORT_CAP32_FC(x) \ 7228 (((x) >> S_FW_PORT_CAP32_FC) & M_FW_PORT_CAP32_FC) 7229 7230 #define S_FW_PORT_CAP32_802_3 18 7231 #define M_FW_PORT_CAP32_802_3 0x3 7232 #define V_FW_PORT_CAP32_802_3(x) ((x) << S_FW_PORT_CAP32_802_3) 7233 #define G_FW_PORT_CAP32_802_3(x) \ 7234 (((x) >> S_FW_PORT_CAP32_802_3) & M_FW_PORT_CAP32_802_3) 7235 7236 #define S_FW_PORT_CAP32_ANEG 20 7237 #define M_FW_PORT_CAP32_ANEG 0x1 7238 #define V_FW_PORT_CAP32_ANEG(x) ((x) << S_FW_PORT_CAP32_ANEG) 7239 #define G_FW_PORT_CAP32_ANEG(x) \ 7240 (((x) >> S_FW_PORT_CAP32_ANEG) & M_FW_PORT_CAP32_ANEG) 7241 7242 #define S_FW_PORT_CAP32_FORCE_PAUSE 28 7243 #define M_FW_PORT_CAP32_FORCE_PAUSE 0x1 7244 #define V_FW_PORT_CAP32_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP32_FORCE_PAUSE) 7245 #define G_FW_PORT_CAP32_FORCE_PAUSE(x) \ 7246 (((x) >> S_FW_PORT_CAP32_FORCE_PAUSE) & M_FW_PORT_CAP32_FORCE_PAUSE) 7247 7248 enum fw_port_mdi32 { 7249 FW_PORT_CAP32_MDI_UNCHANGED, 7250 FW_PORT_CAP32_MDI_AUTO, 7251 FW_PORT_CAP32_MDI_F_STRAIGHT, 7252 FW_PORT_CAP32_MDI_F_CROSSOVER 7253 }; 7254 7255 #define S_FW_PORT_CAP32_MDI 21 7256 #define M_FW_PORT_CAP32_MDI 3 7257 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI) 7258 #define G_FW_PORT_CAP32_MDI(x) \ 7259 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI) 7260 7261 #define S_FW_PORT_CAP32_FEC 23 7262 #define M_FW_PORT_CAP32_FEC 0x5f 7263 #define V_FW_PORT_CAP32_FEC(x) ((x) << S_FW_PORT_CAP32_FEC) 7264 #define G_FW_PORT_CAP32_FEC(x) \ 7265 (((x) >> S_FW_PORT_CAP32_FEC) & M_FW_PORT_CAP32_FEC) 7266 7267 /* macros to isolate various 32-bit Port Capabilities sub-fields */ 7268 #define CAP32_SPEED(__cap32) \ 7269 (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) & __cap32) 7270 7271 #define CAP32_FEC(__cap32) \ 7272 (V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC) & __cap32) 7273 7274 #define CAP32_FC(__cap32) \ 7275 (V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC) & __cap32) 7276 7277 #ifdef _KERNEL 7278 static inline boolean_t 7279 fec_supported(uint32_t caps) 7280 { 7281 return ((caps & (FW_PORT_CAP32_SPEED_25G | FW_PORT_CAP32_SPEED_50G | 7282 FW_PORT_CAP32_SPEED_100G)) != 0); 7283 } 7284 #endif 7285 7286 enum fw_port_action { 7287 FW_PORT_ACTION_L1_CFG = 0x0001, 7288 FW_PORT_ACTION_L2_CFG = 0x0002, 7289 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 7290 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 7291 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 7292 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 7293 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 7294 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 7295 FW_PORT_ACTION_L1_CFG32 = 0x0009, 7296 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 7297 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 7298 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 7299 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 7300 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 7301 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022, 7302 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023, 7303 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025, 7304 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026, 7305 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 7306 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028, 7307 FW_PORT_ACTION_PHY_RESET = 0x0040, 7308 FW_PORT_ACTION_PMA_RESET = 0x0041, 7309 FW_PORT_ACTION_PCS_RESET = 0x0042, 7310 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 7311 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 7312 FW_PORT_ACTION_AN_RESET = 0x0045, 7313 7314 }; 7315 7316 enum fw_port_l2cfg_ctlbf { 7317 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 7318 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 7319 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 7320 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 7321 FW_PORT_L2_CTLBF_IVLAN = 0x10, 7322 FW_PORT_L2_CTLBF_TXIPG = 0x20, 7323 FW_PORT_L2_CTLBF_MTU = 0x40, 7324 FW_PORT_L2_CTLBF_OVLAN_FILT = 0x80, 7325 }; 7326 7327 enum fw_dcb_app_tlv_sf { 7328 FW_DCB_APP_SF_ETHERTYPE, 7329 FW_DCB_APP_SF_SOCKET_TCP, 7330 FW_DCB_APP_SF_SOCKET_UDP, 7331 FW_DCB_APP_SF_SOCKET_ALL, 7332 }; 7333 7334 enum fw_port_dcb_versions { 7335 FW_PORT_DCB_VER_UNKNOWN, 7336 FW_PORT_DCB_VER_CEE1D0, 7337 FW_PORT_DCB_VER_CEE1D01, 7338 FW_PORT_DCB_VER_IEEE, 7339 FW_PORT_DCB_VER_AUTO=7 7340 }; 7341 7342 enum fw_port_dcb_cfg { 7343 FW_PORT_DCB_CFG_PG = 0x01, 7344 FW_PORT_DCB_CFG_PFC = 0x02, 7345 FW_PORT_DCB_CFG_APPL = 0x04 7346 }; 7347 7348 enum fw_port_dcb_cfg_rc { 7349 FW_PORT_DCB_CFG_SUCCESS = 0x0, 7350 FW_PORT_DCB_CFG_ERROR = 0x1 7351 }; 7352 7353 enum fw_port_dcb_type { 7354 FW_PORT_DCB_TYPE_PGID = 0x00, 7355 FW_PORT_DCB_TYPE_PGRATE = 0x01, 7356 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 7357 FW_PORT_DCB_TYPE_PFC = 0x03, 7358 FW_PORT_DCB_TYPE_APP_ID = 0x04, 7359 FW_PORT_DCB_TYPE_CONTROL = 0x05, 7360 }; 7361 7362 enum fw_port_dcb_feature_state { 7363 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 7364 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 7365 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 7366 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 7367 }; 7368 7369 enum fw_port_diag_ops { 7370 FW_PORT_DIAGS_TEMP = 0x00, 7371 FW_PORT_DIAGS_TX_POWER = 0x01, 7372 FW_PORT_DIAGS_RX_POWER = 0x02, 7373 FW_PORT_DIAGS_TX_DIS = 0x03, 7374 }; 7375 7376 struct fw_port_cmd { 7377 __be32 op_to_portid; 7378 __be32 action_to_len16; 7379 union fw_port { 7380 struct fw_port_l1cfg { 7381 __be32 rcap; 7382 __be32 r; 7383 } l1cfg; 7384 struct fw_port_l2cfg { 7385 __u8 ctlbf; 7386 __u8 ovlan3_to_ivlan0; 7387 __be16 ivlantype; 7388 __be16 txipg_force_pinfo; 7389 __be16 mtu; 7390 __be16 ovlan0mask; 7391 __be16 ovlan0type; 7392 __be16 ovlan1mask; 7393 __be16 ovlan1type; 7394 __be16 ovlan2mask; 7395 __be16 ovlan2type; 7396 __be16 ovlan3mask; 7397 __be16 ovlan3type; 7398 } l2cfg; 7399 struct fw_port_info { 7400 __be32 lstatus_to_modtype; 7401 __be16 pcap; 7402 __be16 acap; 7403 __be16 mtu; 7404 __u8 cbllen; 7405 __u8 auxlinfo; 7406 __u8 dcbxdis_pkd; 7407 __u8 r8_lo; 7408 __be16 lpacap; 7409 __be64 r9; 7410 } info; 7411 struct fw_port_diags { 7412 __u8 diagop; 7413 __u8 r[3]; 7414 __be32 diagval; 7415 } diags; 7416 union fw_port_dcb { 7417 struct fw_port_dcb_pgid { 7418 __u8 type; 7419 __u8 apply_pkd; 7420 __u8 r10_lo[2]; 7421 __be32 pgid; 7422 __be64 r11; 7423 } pgid; 7424 struct fw_port_dcb_pgrate { 7425 __u8 type; 7426 __u8 apply_pkd; 7427 __u8 r10_lo[5]; 7428 __u8 num_tcs_supported; 7429 __u8 pgrate[8]; 7430 __u8 tsa[8]; 7431 } pgrate; 7432 struct fw_port_dcb_priorate { 7433 __u8 type; 7434 __u8 apply_pkd; 7435 __u8 r10_lo[6]; 7436 __u8 strict_priorate[8]; 7437 } priorate; 7438 struct fw_port_dcb_pfc { 7439 __u8 type; 7440 __u8 pfcen; 7441 __u8 apply_pkd; 7442 __u8 r10_lo[4]; 7443 __u8 max_pfc_tcs; 7444 __be64 r11; 7445 } pfc; 7446 struct fw_port_app_priority { 7447 __u8 type; 7448 __u8 apply_pkd; 7449 __u8 r10_lo; 7450 __u8 idx; 7451 __u8 user_prio_map; 7452 __u8 sel_field; 7453 __be16 protocolid; 7454 __be64 r12; 7455 } app_priority; 7456 struct fw_port_dcb_control { 7457 __u8 type; 7458 __u8 all_syncd_pkd; 7459 __be16 dcb_version_to_app_state; 7460 __be32 r11; 7461 __be64 r12; 7462 } control; 7463 } dcb; 7464 struct fw_port_l1cfg32 { 7465 __be32 rcap32; 7466 __be32 r; 7467 } l1cfg32; 7468 struct fw_port_info32 { 7469 __be32 lstatus32_to_cbllen32; 7470 __be32 auxlinfo32_mtu32; 7471 __be32 linkattr32; 7472 __be32 pcaps32; 7473 __be32 acaps32; 7474 __be32 lpacaps32; 7475 } info32; 7476 } u; 7477 }; 7478 7479 #define S_FW_PORT_CMD_READ 22 7480 #define M_FW_PORT_CMD_READ 0x1 7481 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 7482 #define G_FW_PORT_CMD_READ(x) \ 7483 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 7484 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 7485 7486 #define S_FW_PORT_CMD_PORTID 0 7487 #define M_FW_PORT_CMD_PORTID 0xf 7488 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 7489 #define G_FW_PORT_CMD_PORTID(x) \ 7490 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 7491 7492 #define S_FW_PORT_CMD_ACTION 16 7493 #define M_FW_PORT_CMD_ACTION 0xffff 7494 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 7495 #define G_FW_PORT_CMD_ACTION(x) \ 7496 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 7497 7498 #define S_FW_PORT_CMD_OVLAN3 7 7499 #define M_FW_PORT_CMD_OVLAN3 0x1 7500 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 7501 #define G_FW_PORT_CMD_OVLAN3(x) \ 7502 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 7503 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 7504 7505 #define S_FW_PORT_CMD_OVLAN2 6 7506 #define M_FW_PORT_CMD_OVLAN2 0x1 7507 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 7508 #define G_FW_PORT_CMD_OVLAN2(x) \ 7509 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 7510 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 7511 7512 #define S_FW_PORT_CMD_OVLAN1 5 7513 #define M_FW_PORT_CMD_OVLAN1 0x1 7514 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 7515 #define G_FW_PORT_CMD_OVLAN1(x) \ 7516 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 7517 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 7518 7519 #define S_FW_PORT_CMD_OVLAN0 4 7520 #define M_FW_PORT_CMD_OVLAN0 0x1 7521 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 7522 #define G_FW_PORT_CMD_OVLAN0(x) \ 7523 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 7524 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 7525 7526 #define S_FW_PORT_CMD_IVLAN0 3 7527 #define M_FW_PORT_CMD_IVLAN0 0x1 7528 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 7529 #define G_FW_PORT_CMD_IVLAN0(x) \ 7530 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 7531 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 7532 7533 #define S_FW_PORT_CMD_OVLAN_FILT 2 7534 #define M_FW_PORT_CMD_OVLAN_FILT 0x1 7535 #define V_FW_PORT_CMD_OVLAN_FILT(x) ((x) << S_FW_PORT_CMD_OVLAN_FILT) 7536 #define G_FW_PORT_CMD_OVLAN_FILT(x) \ 7537 (((x) >> S_FW_PORT_CMD_OVLAN_FILT) & M_FW_PORT_CMD_OVLAN_FILT) 7538 #define F_FW_PORT_CMD_OVLAN_FILT V_FW_PORT_CMD_OVLAN_FILT(1U) 7539 7540 #define S_FW_PORT_CMD_TXIPG 3 7541 #define M_FW_PORT_CMD_TXIPG 0x1fff 7542 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 7543 #define G_FW_PORT_CMD_TXIPG(x) \ 7544 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 7545 7546 #define S_FW_PORT_CMD_FORCE_PINFO 0 7547 #define M_FW_PORT_CMD_FORCE_PINFO 0x1 7548 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 7549 #define G_FW_PORT_CMD_FORCE_PINFO(x) \ 7550 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 7551 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 7552 7553 #define S_FW_PORT_CMD_LSTATUS 31 7554 #define M_FW_PORT_CMD_LSTATUS 0x1 7555 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 7556 #define G_FW_PORT_CMD_LSTATUS(x) \ 7557 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 7558 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 7559 7560 #define S_FW_PORT_CMD_LSPEED 24 7561 #define M_FW_PORT_CMD_LSPEED 0x3f 7562 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 7563 #define G_FW_PORT_CMD_LSPEED(x) \ 7564 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 7565 7566 #define S_FW_PORT_CMD_TXPAUSE 23 7567 #define M_FW_PORT_CMD_TXPAUSE 0x1 7568 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 7569 #define G_FW_PORT_CMD_TXPAUSE(x) \ 7570 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 7571 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 7572 7573 #define S_FW_PORT_CMD_RXPAUSE 22 7574 #define M_FW_PORT_CMD_RXPAUSE 0x1 7575 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 7576 #define G_FW_PORT_CMD_RXPAUSE(x) \ 7577 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 7578 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 7579 7580 #define S_FW_PORT_CMD_MDIOCAP 21 7581 #define M_FW_PORT_CMD_MDIOCAP 0x1 7582 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 7583 #define G_FW_PORT_CMD_MDIOCAP(x) \ 7584 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 7585 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 7586 7587 #define S_FW_PORT_CMD_MDIOADDR 16 7588 #define M_FW_PORT_CMD_MDIOADDR 0x1f 7589 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 7590 #define G_FW_PORT_CMD_MDIOADDR(x) \ 7591 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 7592 7593 #define S_FW_PORT_CMD_LPTXPAUSE 15 7594 #define M_FW_PORT_CMD_LPTXPAUSE 0x1 7595 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 7596 #define G_FW_PORT_CMD_LPTXPAUSE(x) \ 7597 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 7598 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 7599 7600 #define S_FW_PORT_CMD_LPRXPAUSE 14 7601 #define M_FW_PORT_CMD_LPRXPAUSE 0x1 7602 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 7603 #define G_FW_PORT_CMD_LPRXPAUSE(x) \ 7604 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 7605 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 7606 7607 #define S_FW_PORT_CMD_PTYPE 8 7608 #define M_FW_PORT_CMD_PTYPE 0x1f 7609 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 7610 #define G_FW_PORT_CMD_PTYPE(x) \ 7611 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 7612 7613 #define S_FW_PORT_CMD_LINKDNRC 5 7614 #define M_FW_PORT_CMD_LINKDNRC 0x7 7615 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 7616 #define G_FW_PORT_CMD_LINKDNRC(x) \ 7617 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 7618 7619 #define S_FW_PORT_CMD_MODTYPE 0 7620 #define M_FW_PORT_CMD_MODTYPE 0x1f 7621 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 7622 #define G_FW_PORT_CMD_MODTYPE(x) \ 7623 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 7624 7625 #define S_FW_PORT_AUXLINFO_KX4 2 7626 #define M_FW_PORT_AUXLINFO_KX4 0x1 7627 #define V_FW_PORT_AUXLINFO_KX4(x) \ 7628 ((x) << S_FW_PORT_AUXLINFO_KX4) 7629 #define G_FW_PORT_AUXLINFO_KX4(x) \ 7630 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 7631 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 7632 7633 #define S_FW_PORT_AUXLINFO_KR 1 7634 #define M_FW_PORT_AUXLINFO_KR 0x1 7635 #define V_FW_PORT_AUXLINFO_KR(x) \ 7636 ((x) << S_FW_PORT_AUXLINFO_KR) 7637 #define G_FW_PORT_AUXLINFO_KR(x) \ 7638 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 7639 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 7640 7641 #define S_FW_PORT_CMD_DCBXDIS 7 7642 #define M_FW_PORT_CMD_DCBXDIS 0x1 7643 #define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS) 7644 #define G_FW_PORT_CMD_DCBXDIS(x) \ 7645 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS) 7646 #define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) 7647 7648 #define S_FW_PORT_CMD_APPLY 7 7649 #define M_FW_PORT_CMD_APPLY 0x1 7650 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 7651 #define G_FW_PORT_CMD_APPLY(x) \ 7652 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 7653 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 7654 7655 #define S_FW_PORT_CMD_ALL_SYNCD 7 7656 #define M_FW_PORT_CMD_ALL_SYNCD 0x1 7657 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 7658 #define G_FW_PORT_CMD_ALL_SYNCD(x) \ 7659 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 7660 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 7661 7662 #define S_FW_PORT_CMD_DCB_VERSION 12 7663 #define M_FW_PORT_CMD_DCB_VERSION 0x7 7664 #define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION) 7665 #define G_FW_PORT_CMD_DCB_VERSION(x) \ 7666 (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION) 7667 7668 #define S_FW_PORT_CMD_PFC_STATE 8 7669 #define M_FW_PORT_CMD_PFC_STATE 0xf 7670 #define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE) 7671 #define G_FW_PORT_CMD_PFC_STATE(x) \ 7672 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE) 7673 7674 #define S_FW_PORT_CMD_ETS_STATE 4 7675 #define M_FW_PORT_CMD_ETS_STATE 0xf 7676 #define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE) 7677 #define G_FW_PORT_CMD_ETS_STATE(x) \ 7678 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE) 7679 7680 #define S_FW_PORT_CMD_APP_STATE 0 7681 #define M_FW_PORT_CMD_APP_STATE 0xf 7682 #define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE) 7683 #define G_FW_PORT_CMD_APP_STATE(x) \ 7684 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE) 7685 7686 #define S_FW_PORT_CMD_LSTATUS32 31 7687 #define M_FW_PORT_CMD_LSTATUS32 0x1 7688 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32) 7689 #define G_FW_PORT_CMD_LSTATUS32(x) \ 7690 (((x) >> S_FW_PORT_CMD_LSTATUS32) & M_FW_PORT_CMD_LSTATUS32) 7691 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U) 7692 7693 #define S_FW_PORT_CMD_LINKDNRC32 28 7694 #define M_FW_PORT_CMD_LINKDNRC32 0x7 7695 #define V_FW_PORT_CMD_LINKDNRC32(x) ((x) << S_FW_PORT_CMD_LINKDNRC32) 7696 #define G_FW_PORT_CMD_LINKDNRC32(x) \ 7697 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32) 7698 7699 #define S_FW_PORT_CMD_DCBXDIS32 27 7700 #define M_FW_PORT_CMD_DCBXDIS32 0x1 7701 #define V_FW_PORT_CMD_DCBXDIS32(x) ((x) << S_FW_PORT_CMD_DCBXDIS32) 7702 #define G_FW_PORT_CMD_DCBXDIS32(x) \ 7703 (((x) >> S_FW_PORT_CMD_DCBXDIS32) & M_FW_PORT_CMD_DCBXDIS32) 7704 #define F_FW_PORT_CMD_DCBXDIS32 V_FW_PORT_CMD_DCBXDIS32(1U) 7705 7706 #define S_FW_PORT_CMD_MDIOCAP32 26 7707 #define M_FW_PORT_CMD_MDIOCAP32 0x1 7708 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32) 7709 #define G_FW_PORT_CMD_MDIOCAP32(x) \ 7710 (((x) >> S_FW_PORT_CMD_MDIOCAP32) & M_FW_PORT_CMD_MDIOCAP32) 7711 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U) 7712 7713 #define S_FW_PORT_CMD_MDIOADDR32 21 7714 #define M_FW_PORT_CMD_MDIOADDR32 0x1f 7715 #define V_FW_PORT_CMD_MDIOADDR32(x) ((x) << S_FW_PORT_CMD_MDIOADDR32) 7716 #define G_FW_PORT_CMD_MDIOADDR32(x) \ 7717 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32) 7718 7719 #define S_FW_PORT_CMD_PORTTYPE32 13 7720 #define M_FW_PORT_CMD_PORTTYPE32 0xff 7721 #define V_FW_PORT_CMD_PORTTYPE32(x) ((x) << S_FW_PORT_CMD_PORTTYPE32) 7722 #define G_FW_PORT_CMD_PORTTYPE32(x) \ 7723 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32) 7724 7725 #define S_FW_PORT_CMD_MODTYPE32 8 7726 #define M_FW_PORT_CMD_MODTYPE32 0x1f 7727 #define V_FW_PORT_CMD_MODTYPE32(x) ((x) << S_FW_PORT_CMD_MODTYPE32) 7728 #define G_FW_PORT_CMD_MODTYPE32(x) \ 7729 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32) 7730 7731 #define S_FW_PORT_CMD_CBLLEN32 0 7732 #define M_FW_PORT_CMD_CBLLEN32 0xff 7733 #define V_FW_PORT_CMD_CBLLEN32(x) ((x) << S_FW_PORT_CMD_CBLLEN32) 7734 #define G_FW_PORT_CMD_CBLLEN32(x) \ 7735 (((x) >> S_FW_PORT_CMD_CBLLEN32) & M_FW_PORT_CMD_CBLLEN32) 7736 7737 #define S_FW_PORT_CMD_AUXLINFO32 24 7738 #define M_FW_PORT_CMD_AUXLINFO32 0xff 7739 #define V_FW_PORT_CMD_AUXLINFO32(x) ((x) << S_FW_PORT_CMD_AUXLINFO32) 7740 #define G_FW_PORT_CMD_AUXLINFO32(x) \ 7741 (((x) >> S_FW_PORT_CMD_AUXLINFO32) & M_FW_PORT_CMD_AUXLINFO32) 7742 7743 #define S_FW_PORT_AUXLINFO32_KX4 2 7744 #define M_FW_PORT_AUXLINFO32_KX4 0x1 7745 #define V_FW_PORT_AUXLINFO32_KX4(x) \ 7746 ((x) << S_FW_PORT_AUXLINFO32_KX4) 7747 #define G_FW_PORT_AUXLINFO32_KX4(x) \ 7748 (((x) >> S_FW_PORT_AUXLINFO32_KX4) & M_FW_PORT_AUXLINFO32_KX4) 7749 #define F_FW_PORT_AUXLINFO32_KX4 V_FW_PORT_AUXLINFO32_KX4(1U) 7750 7751 #define S_FW_PORT_AUXLINFO32_KR 1 7752 #define M_FW_PORT_AUXLINFO32_KR 0x1 7753 #define V_FW_PORT_AUXLINFO32_KR(x) \ 7754 ((x) << S_FW_PORT_AUXLINFO32_KR) 7755 #define G_FW_PORT_AUXLINFO32_KR(x) \ 7756 (((x) >> S_FW_PORT_AUXLINFO32_KR) & M_FW_PORT_AUXLINFO32_KR) 7757 #define F_FW_PORT_AUXLINFO32_KR V_FW_PORT_AUXLINFO32_KR(1U) 7758 7759 #define S_FW_PORT_CMD_MTU32 0 7760 #define M_FW_PORT_CMD_MTU32 0xffff 7761 #define V_FW_PORT_CMD_MTU32(x) ((x) << S_FW_PORT_CMD_MTU32) 7762 #define G_FW_PORT_CMD_MTU32(x) \ 7763 (((x) >> S_FW_PORT_CMD_MTU32) & M_FW_PORT_CMD_MTU32) 7764 7765 /* 7766 * These are configured into the VPD and hence tools that generate 7767 * VPD may use this enumeration. 7768 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 7769 * 7770 * REMEMBER: 7771 * Update the Common Code t4_hw.c:t4_get_port_type_description() 7772 * with any new Firmware Port Technology Types! 7773 */ 7774 enum fw_port_type { 7775 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 7776 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 7777 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 7778 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */ 7779 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */ 7780 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 7781 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 7782 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 7783 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 7784 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 7785 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 7786 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 7787 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 7788 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 7789 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 7790 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 7791 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */ 7792 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */ 7793 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */ 7794 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */ 7795 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */ 7796 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */ 7797 FW_PORT_TYPE_KR_XLAUI = 22, /* No, 4, 40G/10G/1G, No AN*/ 7798 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 7799 }; 7800 7801 /* These are read from module's EEPROM and determined once the 7802 module is inserted. */ 7803 enum fw_port_module_type { 7804 FW_PORT_MOD_TYPE_NA = 0x0, 7805 FW_PORT_MOD_TYPE_LR = 0x1, 7806 FW_PORT_MOD_TYPE_SR = 0x2, 7807 FW_PORT_MOD_TYPE_ER = 0x3, 7808 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 7809 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 7810 FW_PORT_MOD_TYPE_LRM = 0x6, 7811 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 7812 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 7813 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 7814 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 7815 }; 7816 7817 /* used by FW and tools may use this to generate VPD */ 7818 enum fw_port_mod_sub_type { 7819 FW_PORT_MOD_SUB_TYPE_NA, 7820 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 7821 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 7822 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 7823 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 7824 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 7825 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, 7826 FW_PORT_MOD_SUB_TYPE_BCM84856=0x7, 7827 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 7828 7829 /* 7830 * The following will never been in the VPD. They are TWINAX cable 7831 * lengths decoded from SFP+ module i2c PROMs. These should almost 7832 * certainly go somewhere else ... 7833 */ 7834 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 7835 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 7836 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 7837 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 7838 }; 7839 7840 /* link down reason codes (3b) */ 7841 enum fw_port_link_dn_rc { 7842 FW_PORT_LINK_DN_RC_NONE, 7843 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 7844 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 7845 FW_PORT_LINK_DN_RESERVED3, 7846 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 7847 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 7848 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 7849 FW_PORT_LINK_DN_RESERVED7 7850 }; 7851 enum fw_port_stats_tx_index { 7852 FW_STAT_TX_PORT_BYTES_IX = 0, 7853 FW_STAT_TX_PORT_FRAMES_IX, 7854 FW_STAT_TX_PORT_BCAST_IX, 7855 FW_STAT_TX_PORT_MCAST_IX, 7856 FW_STAT_TX_PORT_UCAST_IX, 7857 FW_STAT_TX_PORT_ERROR_IX, 7858 FW_STAT_TX_PORT_64B_IX, 7859 FW_STAT_TX_PORT_65B_127B_IX, 7860 FW_STAT_TX_PORT_128B_255B_IX, 7861 FW_STAT_TX_PORT_256B_511B_IX, 7862 FW_STAT_TX_PORT_512B_1023B_IX, 7863 FW_STAT_TX_PORT_1024B_1518B_IX, 7864 FW_STAT_TX_PORT_1519B_MAX_IX, 7865 FW_STAT_TX_PORT_DROP_IX, 7866 FW_STAT_TX_PORT_PAUSE_IX, 7867 FW_STAT_TX_PORT_PPP0_IX, 7868 FW_STAT_TX_PORT_PPP1_IX, 7869 FW_STAT_TX_PORT_PPP2_IX, 7870 FW_STAT_TX_PORT_PPP3_IX, 7871 FW_STAT_TX_PORT_PPP4_IX, 7872 FW_STAT_TX_PORT_PPP5_IX, 7873 FW_STAT_TX_PORT_PPP6_IX, 7874 FW_STAT_TX_PORT_PPP7_IX, 7875 FW_NUM_PORT_TX_STATS 7876 }; 7877 7878 enum fw_port_stat_rx_index { 7879 FW_STAT_RX_PORT_BYTES_IX = 0, 7880 FW_STAT_RX_PORT_FRAMES_IX, 7881 FW_STAT_RX_PORT_BCAST_IX, 7882 FW_STAT_RX_PORT_MCAST_IX, 7883 FW_STAT_RX_PORT_UCAST_IX, 7884 FW_STAT_RX_PORT_MTU_ERROR_IX, 7885 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 7886 FW_STAT_RX_PORT_CRC_ERROR_IX, 7887 FW_STAT_RX_PORT_LEN_ERROR_IX, 7888 FW_STAT_RX_PORT_SYM_ERROR_IX, 7889 FW_STAT_RX_PORT_64B_IX, 7890 FW_STAT_RX_PORT_65B_127B_IX, 7891 FW_STAT_RX_PORT_128B_255B_IX, 7892 FW_STAT_RX_PORT_256B_511B_IX, 7893 FW_STAT_RX_PORT_512B_1023B_IX, 7894 FW_STAT_RX_PORT_1024B_1518B_IX, 7895 FW_STAT_RX_PORT_1519B_MAX_IX, 7896 FW_STAT_RX_PORT_PAUSE_IX, 7897 FW_STAT_RX_PORT_PPP0_IX, 7898 FW_STAT_RX_PORT_PPP1_IX, 7899 FW_STAT_RX_PORT_PPP2_IX, 7900 FW_STAT_RX_PORT_PPP3_IX, 7901 FW_STAT_RX_PORT_PPP4_IX, 7902 FW_STAT_RX_PORT_PPP5_IX, 7903 FW_STAT_RX_PORT_PPP6_IX, 7904 FW_STAT_RX_PORT_PPP7_IX, 7905 FW_STAT_RX_PORT_LESS_64B_IX, 7906 FW_STAT_RX_PORT_MAC_ERROR_IX, 7907 FW_NUM_PORT_RX_STATS 7908 }; 7909 /* port stats */ 7910 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \ 7911 FW_NUM_PORT_RX_STATS) 7912 7913 7914 struct fw_port_stats_cmd { 7915 __be32 op_to_portid; 7916 __be32 retval_len16; 7917 union fw_port_stats { 7918 struct fw_port_stats_ctl { 7919 __u8 nstats_bg_bm; 7920 __u8 tx_ix; 7921 __be16 r6; 7922 __be32 r7; 7923 __be64 stat0; 7924 __be64 stat1; 7925 __be64 stat2; 7926 __be64 stat3; 7927 __be64 stat4; 7928 __be64 stat5; 7929 } ctl; 7930 struct fw_port_stats_all { 7931 __be64 tx_bytes; 7932 __be64 tx_frames; 7933 __be64 tx_bcast; 7934 __be64 tx_mcast; 7935 __be64 tx_ucast; 7936 __be64 tx_error; 7937 __be64 tx_64b; 7938 __be64 tx_65b_127b; 7939 __be64 tx_128b_255b; 7940 __be64 tx_256b_511b; 7941 __be64 tx_512b_1023b; 7942 __be64 tx_1024b_1518b; 7943 __be64 tx_1519b_max; 7944 __be64 tx_drop; 7945 __be64 tx_pause; 7946 __be64 tx_ppp0; 7947 __be64 tx_ppp1; 7948 __be64 tx_ppp2; 7949 __be64 tx_ppp3; 7950 __be64 tx_ppp4; 7951 __be64 tx_ppp5; 7952 __be64 tx_ppp6; 7953 __be64 tx_ppp7; 7954 __be64 rx_bytes; 7955 __be64 rx_frames; 7956 __be64 rx_bcast; 7957 __be64 rx_mcast; 7958 __be64 rx_ucast; 7959 __be64 rx_mtu_error; 7960 __be64 rx_mtu_crc_error; 7961 __be64 rx_crc_error; 7962 __be64 rx_len_error; 7963 __be64 rx_sym_error; 7964 __be64 rx_64b; 7965 __be64 rx_65b_127b; 7966 __be64 rx_128b_255b; 7967 __be64 rx_256b_511b; 7968 __be64 rx_512b_1023b; 7969 __be64 rx_1024b_1518b; 7970 __be64 rx_1519b_max; 7971 __be64 rx_pause; 7972 __be64 rx_ppp0; 7973 __be64 rx_ppp1; 7974 __be64 rx_ppp2; 7975 __be64 rx_ppp3; 7976 __be64 rx_ppp4; 7977 __be64 rx_ppp5; 7978 __be64 rx_ppp6; 7979 __be64 rx_ppp7; 7980 __be64 rx_less_64b; 7981 __be64 rx_bg_drop; 7982 __be64 rx_bg_trunc; 7983 } all; 7984 } u; 7985 }; 7986 7987 #define S_FW_PORT_STATS_CMD_NSTATS 4 7988 #define M_FW_PORT_STATS_CMD_NSTATS 0x7 7989 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 7990 #define G_FW_PORT_STATS_CMD_NSTATS(x) \ 7991 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 7992 7993 #define S_FW_PORT_STATS_CMD_BG_BM 0 7994 #define M_FW_PORT_STATS_CMD_BG_BM 0x3 7995 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 7996 #define G_FW_PORT_STATS_CMD_BG_BM(x) \ 7997 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 7998 7999 #define S_FW_PORT_STATS_CMD_TX 7 8000 #define M_FW_PORT_STATS_CMD_TX 0x1 8001 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 8002 #define G_FW_PORT_STATS_CMD_TX(x) \ 8003 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 8004 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 8005 8006 #define S_FW_PORT_STATS_CMD_IX 0 8007 #define M_FW_PORT_STATS_CMD_IX 0x3f 8008 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 8009 #define G_FW_PORT_STATS_CMD_IX(x) \ 8010 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 8011 8012 /* port loopback stats */ 8013 #define FW_NUM_LB_STATS 14 8014 enum fw_port_lb_stats_index { 8015 FW_STAT_LB_PORT_BYTES_IX, 8016 FW_STAT_LB_PORT_FRAMES_IX, 8017 FW_STAT_LB_PORT_BCAST_IX, 8018 FW_STAT_LB_PORT_MCAST_IX, 8019 FW_STAT_LB_PORT_UCAST_IX, 8020 FW_STAT_LB_PORT_ERROR_IX, 8021 FW_STAT_LB_PORT_64B_IX, 8022 FW_STAT_LB_PORT_65B_127B_IX, 8023 FW_STAT_LB_PORT_128B_255B_IX, 8024 FW_STAT_LB_PORT_256B_511B_IX, 8025 FW_STAT_LB_PORT_512B_1023B_IX, 8026 FW_STAT_LB_PORT_1024B_1518B_IX, 8027 FW_STAT_LB_PORT_1519B_MAX_IX, 8028 FW_STAT_LB_PORT_DROP_FRAMES_IX 8029 }; 8030 8031 struct fw_port_lb_stats_cmd { 8032 __be32 op_to_lbport; 8033 __be32 retval_len16; 8034 union fw_port_lb_stats { 8035 struct fw_port_lb_stats_ctl { 8036 __u8 nstats_bg_bm; 8037 __u8 ix_pkd; 8038 __be16 r6; 8039 __be32 r7; 8040 __be64 stat0; 8041 __be64 stat1; 8042 __be64 stat2; 8043 __be64 stat3; 8044 __be64 stat4; 8045 __be64 stat5; 8046 } ctl; 8047 struct fw_port_lb_stats_all { 8048 __be64 tx_bytes; 8049 __be64 tx_frames; 8050 __be64 tx_bcast; 8051 __be64 tx_mcast; 8052 __be64 tx_ucast; 8053 __be64 tx_error; 8054 __be64 tx_64b; 8055 __be64 tx_65b_127b; 8056 __be64 tx_128b_255b; 8057 __be64 tx_256b_511b; 8058 __be64 tx_512b_1023b; 8059 __be64 tx_1024b_1518b; 8060 __be64 tx_1519b_max; 8061 __be64 rx_lb_drop; 8062 __be64 rx_lb_trunc; 8063 } all; 8064 } u; 8065 }; 8066 8067 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 8068 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 8069 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 8070 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 8071 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 8072 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 8073 8074 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 8075 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 8076 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 8077 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 8078 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 8079 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 8080 8081 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 8082 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 8083 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 8084 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 8085 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 8086 8087 #define S_FW_PORT_LB_STATS_CMD_IX 0 8088 #define M_FW_PORT_LB_STATS_CMD_IX 0xf 8089 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 8090 #define G_FW_PORT_LB_STATS_CMD_IX(x) \ 8091 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 8092 8093 /* Trace related defines */ 8094 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 8095 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 8096 8097 struct fw_port_trace_cmd { 8098 __be32 op_to_portid; 8099 __be32 retval_len16; 8100 __be16 traceen_to_pciech; 8101 __be16 qnum; 8102 __be32 r5; 8103 }; 8104 8105 #define S_FW_PORT_TRACE_CMD_PORTID 0 8106 #define M_FW_PORT_TRACE_CMD_PORTID 0xf 8107 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 8108 #define G_FW_PORT_TRACE_CMD_PORTID(x) \ 8109 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 8110 8111 #define S_FW_PORT_TRACE_CMD_TRACEEN 15 8112 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 8113 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 8114 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 8115 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 8116 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 8117 8118 #define S_FW_PORT_TRACE_CMD_FLTMODE 14 8119 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 8120 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 8121 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 8122 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 8123 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 8124 8125 #define S_FW_PORT_TRACE_CMD_DUPLEN 13 8126 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 8127 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 8128 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 8129 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 8130 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 8131 8132 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 8133 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 8134 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 8135 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 8136 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 8137 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 8138 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 8139 8140 #define S_FW_PORT_TRACE_CMD_PCIECH 6 8141 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 8142 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 8143 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 8144 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 8145 8146 struct fw_port_trace_mmap_cmd { 8147 __be32 op_to_portid; 8148 __be32 retval_len16; 8149 __be32 fid_to_skipoffset; 8150 __be32 minpktsize_capturemax; 8151 __u8 map[224]; 8152 }; 8153 8154 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 8155 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 8156 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 8157 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 8158 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 8159 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 8160 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 8161 8162 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 8163 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 8164 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 8165 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 8166 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 8167 8168 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 8169 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 8170 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 8171 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 8172 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 8173 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 8174 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 8175 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 8176 8177 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 8178 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 8179 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 8180 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 8181 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 8182 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 8183 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 8184 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 8185 8186 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 8187 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 8188 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 8189 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 8190 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 8191 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 8192 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 8193 8194 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 8195 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 8196 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 8197 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 8198 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 8199 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 8200 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 8201 8202 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 8203 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 8204 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 8205 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 8206 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 8207 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 8208 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 8209 8210 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 8211 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 8212 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 8213 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 8214 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 8215 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 8216 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 8217 8218 enum fw_ptp_subop { 8219 8220 /* none */ 8221 FW_PTP_SC_INIT_TIMER = 0x00, 8222 FW_PTP_SC_TX_TYPE = 0x01, 8223 8224 /* init */ 8225 FW_PTP_SC_RXTIME_STAMP = 0x08, 8226 FW_PTP_SC_RDRX_TYPE = 0x09, 8227 8228 /* ts */ 8229 FW_PTP_SC_ADJ_FREQ = 0x10, 8230 FW_PTP_SC_ADJ_TIME = 0x11, 8231 FW_PTP_SC_ADJ_FTIME = 0x12, 8232 FW_PTP_SC_WALL_CLOCK = 0x13, 8233 FW_PTP_SC_GET_TIME = 0x14, 8234 FW_PTP_SC_SET_TIME = 0x15, 8235 }; 8236 8237 struct fw_ptp_cmd { 8238 __be32 op_to_portid; 8239 __be32 retval_len16; 8240 union fw_ptp { 8241 struct fw_ptp_sc { 8242 __u8 sc; 8243 __u8 r3[7]; 8244 } scmd; 8245 struct fw_ptp_init { 8246 __u8 sc; 8247 __u8 txchan; 8248 __be16 absid; 8249 __be16 mode; 8250 __be16 ptp_rx_ctrl_pkd; 8251 } init; 8252 struct fw_ptp_ts { 8253 __u8 sc; 8254 __u8 sign; 8255 __be16 r3; 8256 __be32 ppb; 8257 __be64 tm; 8258 } ts; 8259 } u; 8260 __be64 r3; 8261 }; 8262 8263 #define S_FW_PTP_CMD_PORTID 0 8264 #define M_FW_PTP_CMD_PORTID 0xf 8265 #define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID) 8266 #define G_FW_PTP_CMD_PORTID(x) \ 8267 (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID) 8268 8269 #define S_FW_PTP_CMD_PTP_RX_CTRL 15 8270 #define M_FW_PTP_CMD_PTP_RX_CTRL 0x1 8271 #define V_FW_PTP_CMD_PTP_RX_CTRL(x) ((x) << S_FW_PTP_CMD_PTP_RX_CTRL) 8272 #define G_FW_PTP_CMD_PTP_RX_CTRL(x) \ 8273 (((x) >> S_FW_PTP_CMD_PTP_RX_CTRL) & M_FW_PTP_CMD_PTP_RX_CTRL) 8274 #define F_FW_PTP_CMD_PTP_RX_CTRL V_FW_PTP_CMD_PTP_RX_CTRL(1U) 8275 8276 8277 struct fw_rss_ind_tbl_cmd { 8278 __be32 op_to_viid; 8279 __be32 retval_len16; 8280 __be16 niqid; 8281 __be16 startidx; 8282 __be32 r3; 8283 __be32 iq0_to_iq2; 8284 __be32 iq3_to_iq5; 8285 __be32 iq6_to_iq8; 8286 __be32 iq9_to_iq11; 8287 __be32 iq12_to_iq14; 8288 __be32 iq15_to_iq17; 8289 __be32 iq18_to_iq20; 8290 __be32 iq21_to_iq23; 8291 __be32 iq24_to_iq26; 8292 __be32 iq27_to_iq29; 8293 __be32 iq30_iq31; 8294 __be32 r15_lo; 8295 }; 8296 8297 #define S_FW_RSS_IND_TBL_CMD_VIID 0 8298 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 8299 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 8300 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 8301 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 8302 8303 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 8304 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 8305 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 8306 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 8307 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 8308 8309 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 8310 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 8311 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 8312 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 8313 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 8314 8315 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 8316 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 8317 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 8318 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 8319 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 8320 8321 #define S_FW_RSS_IND_TBL_CMD_IQ3 20 8322 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 8323 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 8324 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 8325 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 8326 8327 #define S_FW_RSS_IND_TBL_CMD_IQ4 10 8328 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 8329 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 8330 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 8331 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 8332 8333 #define S_FW_RSS_IND_TBL_CMD_IQ5 0 8334 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 8335 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 8336 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 8337 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 8338 8339 #define S_FW_RSS_IND_TBL_CMD_IQ6 20 8340 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 8341 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 8342 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 8343 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 8344 8345 #define S_FW_RSS_IND_TBL_CMD_IQ7 10 8346 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 8347 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 8348 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 8349 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 8350 8351 #define S_FW_RSS_IND_TBL_CMD_IQ8 0 8352 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 8353 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 8354 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 8355 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 8356 8357 #define S_FW_RSS_IND_TBL_CMD_IQ9 20 8358 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 8359 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 8360 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 8361 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 8362 8363 #define S_FW_RSS_IND_TBL_CMD_IQ10 10 8364 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 8365 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 8366 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 8367 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 8368 8369 #define S_FW_RSS_IND_TBL_CMD_IQ11 0 8370 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 8371 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 8372 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 8373 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 8374 8375 #define S_FW_RSS_IND_TBL_CMD_IQ12 20 8376 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 8377 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 8378 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 8379 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 8380 8381 #define S_FW_RSS_IND_TBL_CMD_IQ13 10 8382 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 8383 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 8384 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 8385 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 8386 8387 #define S_FW_RSS_IND_TBL_CMD_IQ14 0 8388 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 8389 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 8390 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 8391 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 8392 8393 #define S_FW_RSS_IND_TBL_CMD_IQ15 20 8394 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 8395 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 8396 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 8397 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 8398 8399 #define S_FW_RSS_IND_TBL_CMD_IQ16 10 8400 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 8401 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 8402 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 8403 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 8404 8405 #define S_FW_RSS_IND_TBL_CMD_IQ17 0 8406 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 8407 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 8408 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 8409 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 8410 8411 #define S_FW_RSS_IND_TBL_CMD_IQ18 20 8412 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 8413 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 8414 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 8415 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 8416 8417 #define S_FW_RSS_IND_TBL_CMD_IQ19 10 8418 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 8419 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 8420 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 8421 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 8422 8423 #define S_FW_RSS_IND_TBL_CMD_IQ20 0 8424 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 8425 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 8426 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 8427 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 8428 8429 #define S_FW_RSS_IND_TBL_CMD_IQ21 20 8430 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 8431 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 8432 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 8433 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 8434 8435 #define S_FW_RSS_IND_TBL_CMD_IQ22 10 8436 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 8437 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 8438 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 8439 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 8440 8441 #define S_FW_RSS_IND_TBL_CMD_IQ23 0 8442 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 8443 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 8444 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 8445 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 8446 8447 #define S_FW_RSS_IND_TBL_CMD_IQ24 20 8448 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 8449 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 8450 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 8451 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 8452 8453 #define S_FW_RSS_IND_TBL_CMD_IQ25 10 8454 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 8455 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 8456 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 8457 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 8458 8459 #define S_FW_RSS_IND_TBL_CMD_IQ26 0 8460 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 8461 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 8462 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 8463 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 8464 8465 #define S_FW_RSS_IND_TBL_CMD_IQ27 20 8466 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 8467 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 8468 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 8469 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 8470 8471 #define S_FW_RSS_IND_TBL_CMD_IQ28 10 8472 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 8473 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 8474 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 8475 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 8476 8477 #define S_FW_RSS_IND_TBL_CMD_IQ29 0 8478 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 8479 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 8480 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 8481 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 8482 8483 #define S_FW_RSS_IND_TBL_CMD_IQ30 20 8484 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 8485 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 8486 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 8487 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 8488 8489 #define S_FW_RSS_IND_TBL_CMD_IQ31 10 8490 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 8491 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 8492 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 8493 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 8494 8495 struct fw_rss_glb_config_cmd { 8496 __be32 op_to_write; 8497 __be32 retval_len16; 8498 union fw_rss_glb_config { 8499 struct fw_rss_glb_config_manual { 8500 __be32 mode_pkd; 8501 __be32 r3; 8502 __be64 r4; 8503 __be64 r5; 8504 } manual; 8505 struct fw_rss_glb_config_basicvirtual { 8506 __be32 mode_keymode; 8507 __be32 synmapen_to_hashtoeplitz; 8508 __be64 r8; 8509 __be64 r9; 8510 } basicvirtual; 8511 } u; 8512 }; 8513 8514 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 8515 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 8516 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 8517 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 8518 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 8519 8520 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 8521 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 8522 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 8523 8524 #define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE 26 8525 #define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE 0x3 8526 #define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 8527 ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 8528 #define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 8529 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \ 8530 M_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 8531 8532 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY 0 8533 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY 1 8534 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY 2 8535 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY 3 8536 8537 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 8538 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 8539 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 8540 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 8541 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 8542 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 8543 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 8544 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 8545 8546 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 8547 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 8548 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 8549 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 8550 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 8551 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 8552 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 8553 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 8554 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 8555 8556 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 8557 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 8558 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 8559 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 8560 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 8561 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 8562 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 8563 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 8564 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 8565 8566 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 8567 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 8568 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 8569 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 8570 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 8571 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 8572 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 8573 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 8574 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 8575 8576 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 8577 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 8578 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 8579 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 8580 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 8581 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 8582 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 8583 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 8584 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 8585 8586 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 8587 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 8588 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 8589 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 8590 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 8591 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 8592 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 8593 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 8594 8595 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 8596 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 8597 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 8598 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 8599 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 8600 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 8601 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 8602 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 8603 8604 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 8605 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 8606 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 8607 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 8608 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 8609 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 8610 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 8611 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 8612 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 8613 8614 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 8615 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 8616 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 8617 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 8618 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 8619 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 8620 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 8621 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 8622 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 8623 8624 struct fw_rss_vi_config_cmd { 8625 __be32 op_to_viid; 8626 __be32 retval_len16; 8627 union fw_rss_vi_config { 8628 struct fw_rss_vi_config_manual { 8629 __be64 r3; 8630 __be64 r4; 8631 __be64 r5; 8632 } manual; 8633 struct fw_rss_vi_config_basicvirtual { 8634 __be32 r6; 8635 __be32 defaultq_to_udpen; 8636 __be32 secretkeyidx_pkd; 8637 __be32 secretkeyxor; 8638 __be64 r10; 8639 } basicvirtual; 8640 } u; 8641 }; 8642 8643 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 8644 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 8645 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 8646 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 8647 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 8648 8649 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 8650 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 8651 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 8652 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 8653 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 8654 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 8655 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 8656 8657 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 8658 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 8659 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 8660 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 8661 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 8662 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 8663 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 8664 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 8665 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 8666 8667 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 8668 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 8669 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 8670 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 8671 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 8672 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 8673 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 8674 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 8675 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 8676 8677 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 8678 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 8679 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 8680 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 8681 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 8682 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 8683 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 8684 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 8685 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 8686 8687 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 8688 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 8689 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 8690 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 8691 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 8692 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 8693 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 8694 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 8695 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 8696 8697 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 8698 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 8699 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 8700 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 8701 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 8702 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 8703 8704 #define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0 8705 #define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf 8706 #define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 8707 ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 8708 #define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 8709 (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \ 8710 M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 8711 8712 enum fw_sched_sc { 8713 FW_SCHED_SC_CONFIG = 0, 8714 FW_SCHED_SC_PARAMS = 1, 8715 }; 8716 8717 enum fw_sched_type { 8718 FW_SCHED_TYPE_PKTSCHED = 0, 8719 FW_SCHED_TYPE_STREAMSCHED = 1, 8720 }; 8721 8722 enum fw_sched_params_level { 8723 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 8724 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 8725 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 8726 }; 8727 8728 enum fw_sched_params_mode { 8729 FW_SCHED_PARAMS_MODE_CLASS = 0, 8730 FW_SCHED_PARAMS_MODE_FLOW = 1, 8731 }; 8732 8733 enum fw_sched_params_unit { 8734 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 8735 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 8736 }; 8737 8738 enum fw_sched_params_rate { 8739 FW_SCHED_PARAMS_RATE_REL = 0, 8740 FW_SCHED_PARAMS_RATE_ABS = 1, 8741 }; 8742 8743 struct fw_sched_cmd { 8744 __be32 op_to_write; 8745 __be32 retval_len16; 8746 union fw_sched { 8747 struct fw_sched_config { 8748 __u8 sc; 8749 __u8 type; 8750 __u8 minmaxen; 8751 __u8 r3[5]; 8752 __u8 nclasses[4]; 8753 __be32 r4; 8754 } config; 8755 struct fw_sched_params { 8756 __u8 sc; 8757 __u8 type; 8758 __u8 level; 8759 __u8 mode; 8760 __u8 unit; 8761 __u8 rate; 8762 __u8 ch; 8763 __u8 cl; 8764 __be32 min; 8765 __be32 max; 8766 __be16 weight; 8767 __be16 pktsize; 8768 __be16 burstsize; 8769 __be16 r4; 8770 } params; 8771 } u; 8772 }; 8773 8774 /* 8775 * length of the formatting string 8776 */ 8777 #define FW_DEVLOG_FMT_LEN 192 8778 8779 /* 8780 * maximum number of the formatting string parameters 8781 */ 8782 #define FW_DEVLOG_FMT_PARAMS_NUM 8 8783 8784 /* 8785 * priority levels 8786 */ 8787 enum fw_devlog_level { 8788 FW_DEVLOG_LEVEL_EMERG = 0x0, 8789 FW_DEVLOG_LEVEL_CRIT = 0x1, 8790 FW_DEVLOG_LEVEL_ERR = 0x2, 8791 FW_DEVLOG_LEVEL_NOTICE = 0x3, 8792 FW_DEVLOG_LEVEL_INFO = 0x4, 8793 FW_DEVLOG_LEVEL_DEBUG = 0x5, 8794 FW_DEVLOG_LEVEL_MAX = 0x5, 8795 }; 8796 8797 /* 8798 * facilities that may send a log message 8799 */ 8800 enum fw_devlog_facility { 8801 FW_DEVLOG_FACILITY_CORE = 0x00, 8802 FW_DEVLOG_FACILITY_CF = 0x01, 8803 FW_DEVLOG_FACILITY_SCHED = 0x02, 8804 FW_DEVLOG_FACILITY_TIMER = 0x04, 8805 FW_DEVLOG_FACILITY_RES = 0x06, 8806 FW_DEVLOG_FACILITY_HW = 0x08, 8807 FW_DEVLOG_FACILITY_FLR = 0x10, 8808 FW_DEVLOG_FACILITY_DMAQ = 0x12, 8809 FW_DEVLOG_FACILITY_PHY = 0x14, 8810 FW_DEVLOG_FACILITY_MAC = 0x16, 8811 FW_DEVLOG_FACILITY_PORT = 0x18, 8812 FW_DEVLOG_FACILITY_VI = 0x1A, 8813 FW_DEVLOG_FACILITY_FILTER = 0x1C, 8814 FW_DEVLOG_FACILITY_ACL = 0x1E, 8815 FW_DEVLOG_FACILITY_TM = 0x20, 8816 FW_DEVLOG_FACILITY_QFC = 0x22, 8817 FW_DEVLOG_FACILITY_DCB = 0x24, 8818 FW_DEVLOG_FACILITY_ETH = 0x26, 8819 FW_DEVLOG_FACILITY_OFLD = 0x28, 8820 FW_DEVLOG_FACILITY_RI = 0x2A, 8821 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 8822 FW_DEVLOG_FACILITY_FCOE = 0x2E, 8823 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 8824 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 8825 FW_DEVLOG_FACILITY_CHNET = 0x34, 8826 FW_DEVLOG_FACILITY_COISCSI = 0x36, 8827 FW_DEVLOG_FACILITY_MAX = 0x38, 8828 }; 8829 8830 /* 8831 * log message format 8832 */ 8833 struct fw_devlog_e { 8834 __be64 timestamp; 8835 __be32 seqno; 8836 __be16 reserved1; 8837 __u8 level; 8838 __u8 facility; 8839 __u8 fmt[FW_DEVLOG_FMT_LEN]; 8840 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 8841 __be32 reserved3[4]; 8842 }; 8843 8844 struct fw_devlog_cmd { 8845 __be32 op_to_write; 8846 __be32 retval_len16; 8847 __u8 level; 8848 __u8 r2[7]; 8849 __be32 memtype_devlog_memaddr16_devlog; 8850 __be32 memsize_devlog; 8851 __be32 r3[2]; 8852 }; 8853 8854 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 8855 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 8856 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 8857 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 8858 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 8859 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 8860 8861 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 8862 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 8863 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 8864 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 8865 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 8866 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 8867 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 8868 8869 enum fw_watchdog_actions { 8870 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 8871 FW_WATCHDOG_ACTION_FLR = 1, 8872 FW_WATCHDOG_ACTION_BYPASS = 2, 8873 FW_WATCHDOG_ACTION_TMPCHK = 3, 8874 FW_WATCHDOG_ACTION_PAUSEOFF = 4, 8875 8876 FW_WATCHDOG_ACTION_MAX = 5, 8877 }; 8878 8879 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 8880 8881 struct fw_watchdog_cmd { 8882 __be32 op_to_vfn; 8883 __be32 retval_len16; 8884 __be32 timeout; 8885 __be32 action; 8886 }; 8887 8888 #define S_FW_WATCHDOG_CMD_PFN 8 8889 #define M_FW_WATCHDOG_CMD_PFN 0x7 8890 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 8891 #define G_FW_WATCHDOG_CMD_PFN(x) \ 8892 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 8893 8894 #define S_FW_WATCHDOG_CMD_VFN 0 8895 #define M_FW_WATCHDOG_CMD_VFN 0xff 8896 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 8897 #define G_FW_WATCHDOG_CMD_VFN(x) \ 8898 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 8899 8900 struct fw_clip_cmd { 8901 __be32 op_to_write; 8902 __be32 alloc_to_len16; 8903 __be64 ip_hi; 8904 __be64 ip_lo; 8905 __be32 r4[2]; 8906 }; 8907 8908 #define S_FW_CLIP_CMD_ALLOC 31 8909 #define M_FW_CLIP_CMD_ALLOC 0x1 8910 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 8911 #define G_FW_CLIP_CMD_ALLOC(x) \ 8912 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 8913 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 8914 8915 #define S_FW_CLIP_CMD_FREE 30 8916 #define M_FW_CLIP_CMD_FREE 0x1 8917 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 8918 #define G_FW_CLIP_CMD_FREE(x) \ 8919 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 8920 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 8921 8922 #define S_FW_CLIP_CMD_INDEX 16 8923 #define M_FW_CLIP_CMD_INDEX 0x1fff 8924 #define V_FW_CLIP_CMD_INDEX(x) ((x) << S_FW_CLIP_CMD_INDEX) 8925 #define G_FW_CLIP_CMD_INDEX(x) \ 8926 (((x) >> S_FW_CLIP_CMD_INDEX) & M_FW_CLIP_CMD_INDEX) 8927 8928 /****************************************************************************** 8929 * F O i S C S I C O M M A N D s 8930 **************************************/ 8931 8932 #define FW_CHNET_IFACE_ADDR_MAX 3 8933 8934 enum fw_chnet_iface_cmd_subop { 8935 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 8936 8937 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 8938 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 8939 8940 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 8941 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 8942 8943 FW_CHNET_IFACE_CMD_SUBOP_MAX, 8944 }; 8945 8946 struct fw_chnet_iface_cmd { 8947 __be32 op_to_portid; 8948 __be32 retval_len16; 8949 __u8 subop; 8950 __u8 r2[2]; 8951 __u8 flags; 8952 __be32 ifid_ifstate; 8953 __be16 mtu; 8954 __be16 vlanid; 8955 __be32 r3; 8956 __be16 r4; 8957 __u8 mac[6]; 8958 }; 8959 8960 #define S_FW_CHNET_IFACE_CMD_PORTID 0 8961 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf 8962 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 8963 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 8964 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 8965 8966 #define S_FW_CHNET_IFACE_CMD_IFID 8 8967 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 8968 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 8969 #define G_FW_CHNET_IFACE_CMD_IFID(x) \ 8970 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 8971 8972 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0 8973 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 8974 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 8975 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 8976 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 8977 8978 struct fw_fcoe_res_info_cmd { 8979 __be32 op_to_read; 8980 __be32 retval_len16; 8981 __be16 e_d_tov; 8982 __be16 r_a_tov_seq; 8983 __be16 r_a_tov_els; 8984 __be16 r_r_tov; 8985 __be32 max_xchgs; 8986 __be32 max_ssns; 8987 __be32 used_xchgs; 8988 __be32 used_ssns; 8989 __be32 max_fcfs; 8990 __be32 max_vnps; 8991 __be32 used_fcfs; 8992 __be32 used_vnps; 8993 }; 8994 8995 struct fw_fcoe_link_cmd { 8996 __be32 op_to_portid; 8997 __be32 retval_len16; 8998 __be32 sub_opcode_fcfi; 8999 __u8 r3; 9000 __u8 lstatus; 9001 __be16 flags; 9002 __u8 r4; 9003 __u8 set_vlan; 9004 __be16 vlan_id; 9005 __be32 vnpi_pkd; 9006 __be16 r6; 9007 __u8 phy_mac[6]; 9008 __u8 vnport_wwnn[8]; 9009 __u8 vnport_wwpn[8]; 9010 }; 9011 9012 #define S_FW_FCOE_LINK_CMD_PORTID 0 9013 #define M_FW_FCOE_LINK_CMD_PORTID 0xf 9014 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 9015 #define G_FW_FCOE_LINK_CMD_PORTID(x) \ 9016 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 9017 9018 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 9019 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 9020 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 9021 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 9022 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 9023 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 9024 9025 #define S_FW_FCOE_LINK_CMD_FCFI 0 9026 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 9027 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 9028 #define G_FW_FCOE_LINK_CMD_FCFI(x) \ 9029 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 9030 9031 #define S_FW_FCOE_LINK_CMD_VNPI 0 9032 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 9033 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 9034 #define G_FW_FCOE_LINK_CMD_VNPI(x) \ 9035 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 9036 9037 struct fw_fcoe_vnp_cmd { 9038 __be32 op_to_fcfi; 9039 __be32 alloc_to_len16; 9040 __be32 gen_wwn_to_vnpi; 9041 __be32 vf_id; 9042 __be16 iqid; 9043 __u8 vnport_mac[6]; 9044 __u8 vnport_wwnn[8]; 9045 __u8 vnport_wwpn[8]; 9046 __u8 cmn_srv_parms[16]; 9047 __u8 clsp_word_0_1[8]; 9048 }; 9049 9050 #define S_FW_FCOE_VNP_CMD_FCFI 0 9051 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 9052 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 9053 #define G_FW_FCOE_VNP_CMD_FCFI(x) \ 9054 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 9055 9056 #define S_FW_FCOE_VNP_CMD_ALLOC 31 9057 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1 9058 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 9059 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 9060 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 9061 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 9062 9063 #define S_FW_FCOE_VNP_CMD_FREE 30 9064 #define M_FW_FCOE_VNP_CMD_FREE 0x1 9065 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 9066 #define G_FW_FCOE_VNP_CMD_FREE(x) \ 9067 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 9068 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 9069 9070 #define S_FW_FCOE_VNP_CMD_MODIFY 29 9071 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 9072 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 9073 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 9074 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 9075 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 9076 9077 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22 9078 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 9079 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 9080 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 9081 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 9082 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 9083 9084 #define S_FW_FCOE_VNP_CMD_PERSIST 21 9085 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1 9086 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 9087 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 9088 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 9089 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 9090 9091 #define S_FW_FCOE_VNP_CMD_VFID_EN 20 9092 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 9093 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 9094 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 9095 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 9096 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 9097 9098 #define S_FW_FCOE_VNP_CMD_VNPI 0 9099 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 9100 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 9101 #define G_FW_FCOE_VNP_CMD_VNPI(x) \ 9102 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 9103 9104 struct fw_fcoe_sparams_cmd { 9105 __be32 op_to_portid; 9106 __be32 retval_len16; 9107 __u8 r3[7]; 9108 __u8 cos; 9109 __u8 lport_wwnn[8]; 9110 __u8 lport_wwpn[8]; 9111 __u8 cmn_srv_parms[16]; 9112 __u8 cls_srv_parms[16]; 9113 }; 9114 9115 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0 9116 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 9117 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 9118 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 9119 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 9120 9121 struct fw_fcoe_stats_cmd { 9122 __be32 op_to_flowid; 9123 __be32 free_to_len16; 9124 union fw_fcoe_stats { 9125 struct fw_fcoe_stats_ctl { 9126 __u8 nstats_port; 9127 __u8 port_valid_ix; 9128 __be16 r6; 9129 __be32 r7; 9130 __be64 stat0; 9131 __be64 stat1; 9132 __be64 stat2; 9133 __be64 stat3; 9134 __be64 stat4; 9135 __be64 stat5; 9136 } ctl; 9137 struct fw_fcoe_port_stats { 9138 __be64 tx_bcast_bytes; 9139 __be64 tx_bcast_frames; 9140 __be64 tx_mcast_bytes; 9141 __be64 tx_mcast_frames; 9142 __be64 tx_ucast_bytes; 9143 __be64 tx_ucast_frames; 9144 __be64 tx_drop_frames; 9145 __be64 tx_offload_bytes; 9146 __be64 tx_offload_frames; 9147 __be64 rx_bcast_bytes; 9148 __be64 rx_bcast_frames; 9149 __be64 rx_mcast_bytes; 9150 __be64 rx_mcast_frames; 9151 __be64 rx_ucast_bytes; 9152 __be64 rx_ucast_frames; 9153 __be64 rx_err_frames; 9154 } port_stats; 9155 struct fw_fcoe_fcf_stats { 9156 __be32 fip_tx_bytes; 9157 __be32 fip_tx_fr; 9158 __be64 fcf_ka; 9159 __be64 mcast_adv_rcvd; 9160 __be16 ucast_adv_rcvd; 9161 __be16 sol_sent; 9162 __be16 vlan_req; 9163 __be16 vlan_rpl; 9164 __be16 clr_vlink; 9165 __be16 link_down; 9166 __be16 link_up; 9167 __be16 logo; 9168 __be16 flogi_req; 9169 __be16 flogi_rpl; 9170 __be16 fdisc_req; 9171 __be16 fdisc_rpl; 9172 __be16 fka_prd_chg; 9173 __be16 fc_map_chg; 9174 __be16 vfid_chg; 9175 __u8 no_fka_req; 9176 __u8 no_vnp; 9177 } fcf_stats; 9178 struct fw_fcoe_pcb_stats { 9179 __be64 tx_bytes; 9180 __be64 tx_frames; 9181 __be64 rx_bytes; 9182 __be64 rx_frames; 9183 __be32 vnp_ka; 9184 __be32 unsol_els_rcvd; 9185 __be64 unsol_cmd_rcvd; 9186 __be16 implicit_logo; 9187 __be16 flogi_inv_sparm; 9188 __be16 fdisc_inv_sparm; 9189 __be16 flogi_rjt; 9190 __be16 fdisc_rjt; 9191 __be16 no_ssn; 9192 __be16 mac_flt_fail; 9193 __be16 inv_fr_rcvd; 9194 } pcb_stats; 9195 struct fw_fcoe_scb_stats { 9196 __be64 tx_bytes; 9197 __be64 tx_frames; 9198 __be64 rx_bytes; 9199 __be64 rx_frames; 9200 __be32 host_abrt_req; 9201 __be32 adap_auto_abrt; 9202 __be32 adap_abrt_rsp; 9203 __be32 host_ios_req; 9204 __be16 ssn_offl_ios; 9205 __be16 ssn_not_rdy_ios; 9206 __u8 rx_data_ddp_err; 9207 __u8 ddp_flt_set_err; 9208 __be16 rx_data_fr_err; 9209 __u8 bad_st_abrt_req; 9210 __u8 no_io_abrt_req; 9211 __u8 abort_tmo; 9212 __u8 abort_tmo_2; 9213 __be32 abort_req; 9214 __u8 no_ppod_res_tmo; 9215 __u8 bp_tmo; 9216 __u8 adap_auto_cls; 9217 __u8 no_io_cls_req; 9218 __be32 host_cls_req; 9219 __be64 unsol_cmd_rcvd; 9220 __be32 plogi_req_rcvd; 9221 __be32 prli_req_rcvd; 9222 __be16 logo_req_rcvd; 9223 __be16 prlo_req_rcvd; 9224 __be16 plogi_rjt_rcvd; 9225 __be16 prli_rjt_rcvd; 9226 __be32 adisc_req_rcvd; 9227 __be32 rscn_rcvd; 9228 __be32 rrq_req_rcvd; 9229 __be32 unsol_els_rcvd; 9230 __u8 adisc_rjt_rcvd; 9231 __u8 scr_rjt; 9232 __u8 ct_rjt; 9233 __u8 inval_bls_rcvd; 9234 __be32 ba_rjt_rcvd; 9235 } scb_stats; 9236 } u; 9237 }; 9238 9239 #define S_FW_FCOE_STATS_CMD_FLOWID 0 9240 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 9241 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 9242 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 9243 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 9244 9245 #define S_FW_FCOE_STATS_CMD_FREE 30 9246 #define M_FW_FCOE_STATS_CMD_FREE 0x1 9247 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 9248 #define G_FW_FCOE_STATS_CMD_FREE(x) \ 9249 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 9250 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 9251 9252 #define S_FW_FCOE_STATS_CMD_NSTATS 4 9253 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7 9254 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 9255 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 9256 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 9257 9258 #define S_FW_FCOE_STATS_CMD_PORT 0 9259 #define M_FW_FCOE_STATS_CMD_PORT 0x3 9260 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 9261 #define G_FW_FCOE_STATS_CMD_PORT(x) \ 9262 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 9263 9264 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7 9265 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 9266 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 9267 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 9268 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 9269 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 9270 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 9271 9272 #define S_FW_FCOE_STATS_CMD_IX 0 9273 #define M_FW_FCOE_STATS_CMD_IX 0x3f 9274 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 9275 #define G_FW_FCOE_STATS_CMD_IX(x) \ 9276 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 9277 9278 struct fw_fcoe_fcf_cmd { 9279 __be32 op_to_fcfi; 9280 __be32 retval_len16; 9281 __be16 priority_pkd; 9282 __u8 mac[6]; 9283 __u8 name_id[8]; 9284 __u8 fabric[8]; 9285 __be16 vf_id; 9286 __be16 max_fcoe_size; 9287 __u8 vlan_id; 9288 __u8 fc_map[3]; 9289 __be32 fka_adv; 9290 __be32 r6; 9291 __u8 r7_hi; 9292 __u8 fpma_to_portid; 9293 __u8 spma_mac[6]; 9294 __be64 r8; 9295 }; 9296 9297 #define S_FW_FCOE_FCF_CMD_FCFI 0 9298 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 9299 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 9300 #define G_FW_FCOE_FCF_CMD_FCFI(x) \ 9301 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 9302 9303 #define S_FW_FCOE_FCF_CMD_PRIORITY 0 9304 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 9305 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 9306 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 9307 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 9308 9309 #define S_FW_FCOE_FCF_CMD_FPMA 6 9310 #define M_FW_FCOE_FCF_CMD_FPMA 0x1 9311 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 9312 #define G_FW_FCOE_FCF_CMD_FPMA(x) \ 9313 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 9314 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 9315 9316 #define S_FW_FCOE_FCF_CMD_SPMA 5 9317 #define M_FW_FCOE_FCF_CMD_SPMA 0x1 9318 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 9319 #define G_FW_FCOE_FCF_CMD_SPMA(x) \ 9320 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 9321 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 9322 9323 #define S_FW_FCOE_FCF_CMD_LOGIN 4 9324 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 9325 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 9326 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 9327 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 9328 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 9329 9330 #define S_FW_FCOE_FCF_CMD_PORTID 0 9331 #define M_FW_FCOE_FCF_CMD_PORTID 0xf 9332 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 9333 #define G_FW_FCOE_FCF_CMD_PORTID(x) \ 9334 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 9335 9336 /****************************************************************************** 9337 * E R R O R a n d D E B U G C O M M A N D s 9338 ******************************************************/ 9339 9340 enum fw_error_type { 9341 FW_ERROR_TYPE_EXCEPTION = 0x0, 9342 FW_ERROR_TYPE_HWMODULE = 0x1, 9343 FW_ERROR_TYPE_WR = 0x2, 9344 FW_ERROR_TYPE_ACL = 0x3, 9345 }; 9346 9347 enum fw_dcb_ieee_locations { 9348 FW_IEEE_LOC_LOCAL, 9349 FW_IEEE_LOC_PEER, 9350 FW_IEEE_LOC_OPERATIONAL, 9351 }; 9352 9353 struct fw_dcb_ieee_cmd { 9354 __be32 op_to_location; 9355 __be32 changed_to_len16; 9356 union fw_dcbx_stats { 9357 struct fw_dcbx_pfc_stats_ieee { 9358 __be32 pfc_mbc_pkd; 9359 __be32 pfc_willing_to_pfc_en; 9360 } dcbx_pfc_stats; 9361 struct fw_dcbx_ets_stats_ieee { 9362 __be32 cbs_to_ets_max_tc; 9363 __be32 pg_table; 9364 __u8 pg_percent[8]; 9365 __u8 tsa[8]; 9366 } dcbx_ets_stats; 9367 struct fw_dcbx_app_stats_ieee { 9368 __be32 num_apps_pkd; 9369 __be32 r6; 9370 __be32 app[4]; 9371 } dcbx_app_stats; 9372 struct fw_dcbx_control { 9373 __be32 multi_peer_invalidated; 9374 __u8 version; 9375 __u8 r6[3]; 9376 } dcbx_control; 9377 } u; 9378 }; 9379 9380 #define S_FW_DCB_IEEE_CMD_PORT 8 9381 #define M_FW_DCB_IEEE_CMD_PORT 0x7 9382 #define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT) 9383 #define G_FW_DCB_IEEE_CMD_PORT(x) \ 9384 (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT) 9385 9386 #define S_FW_DCB_IEEE_CMD_FEATURE 2 9387 #define M_FW_DCB_IEEE_CMD_FEATURE 0x7 9388 #define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE) 9389 #define G_FW_DCB_IEEE_CMD_FEATURE(x) \ 9390 (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE) 9391 9392 #define S_FW_DCB_IEEE_CMD_LOCATION 0 9393 #define M_FW_DCB_IEEE_CMD_LOCATION 0x3 9394 #define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION) 9395 #define G_FW_DCB_IEEE_CMD_LOCATION(x) \ 9396 (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION) 9397 9398 #define S_FW_DCB_IEEE_CMD_CHANGED 20 9399 #define M_FW_DCB_IEEE_CMD_CHANGED 0x1 9400 #define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED) 9401 #define G_FW_DCB_IEEE_CMD_CHANGED(x) \ 9402 (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED) 9403 #define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U) 9404 9405 #define S_FW_DCB_IEEE_CMD_RECEIVED 19 9406 #define M_FW_DCB_IEEE_CMD_RECEIVED 0x1 9407 #define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED) 9408 #define G_FW_DCB_IEEE_CMD_RECEIVED(x) \ 9409 (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED) 9410 #define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U) 9411 9412 #define S_FW_DCB_IEEE_CMD_APPLY 18 9413 #define M_FW_DCB_IEEE_CMD_APPLY 0x1 9414 #define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY) 9415 #define G_FW_DCB_IEEE_CMD_APPLY(x) \ 9416 (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY) 9417 #define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U) 9418 9419 #define S_FW_DCB_IEEE_CMD_DISABLED 17 9420 #define M_FW_DCB_IEEE_CMD_DISABLED 0x1 9421 #define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED) 9422 #define G_FW_DCB_IEEE_CMD_DISABLED(x) \ 9423 (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED) 9424 #define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U) 9425 9426 #define S_FW_DCB_IEEE_CMD_MORE 16 9427 #define M_FW_DCB_IEEE_CMD_MORE 0x1 9428 #define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE) 9429 #define G_FW_DCB_IEEE_CMD_MORE(x) \ 9430 (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE) 9431 #define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U) 9432 9433 #define S_FW_DCB_IEEE_CMD_PFC_MBC 0 9434 #define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1 9435 #define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC) 9436 #define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \ 9437 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC) 9438 #define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U) 9439 9440 #define S_FW_DCB_IEEE_CMD_PFC_WILLING 16 9441 #define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1 9442 #define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 9443 ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING) 9444 #define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 9445 (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING) 9446 #define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U) 9447 9448 #define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8 9449 #define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff 9450 #define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC) 9451 #define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \ 9452 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC) 9453 9454 #define S_FW_DCB_IEEE_CMD_PFC_EN 0 9455 #define M_FW_DCB_IEEE_CMD_PFC_EN 0xff 9456 #define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN) 9457 #define G_FW_DCB_IEEE_CMD_PFC_EN(x) \ 9458 (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN) 9459 9460 #define S_FW_DCB_IEEE_CMD_CBS 16 9461 #define M_FW_DCB_IEEE_CMD_CBS 0x1 9462 #define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS) 9463 #define G_FW_DCB_IEEE_CMD_CBS(x) \ 9464 (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS) 9465 #define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U) 9466 9467 #define S_FW_DCB_IEEE_CMD_ETS_WILLING 8 9468 #define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1 9469 #define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 9470 ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING) 9471 #define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 9472 (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING) 9473 #define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U) 9474 9475 #define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0 9476 #define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff 9477 #define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC) 9478 #define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \ 9479 (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC) 9480 9481 #define S_FW_DCB_IEEE_CMD_NUM_APPS 0 9482 #define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7 9483 #define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS) 9484 #define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \ 9485 (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS) 9486 9487 #define S_FW_DCB_IEEE_CMD_MULTI_PEER 31 9488 #define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1 9489 #define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER) 9490 #define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \ 9491 (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER) 9492 #define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U) 9493 9494 #define S_FW_DCB_IEEE_CMD_INVALIDATED 30 9495 #define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1 9496 #define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 9497 ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED) 9498 #define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 9499 (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED) 9500 #define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U) 9501 9502 /* Hand-written */ 9503 #define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16 9504 #define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff 9505 #define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL) 9506 #define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \ 9507 (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL) 9508 9509 #define S_FW_DCB_IEEE_CMD_APP_SELECT 3 9510 #define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7 9511 #define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT) 9512 #define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \ 9513 (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT) 9514 9515 #define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0 9516 #define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7 9517 #define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY) 9518 #define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \ 9519 (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY) 9520 9521 9522 struct fw_error_cmd { 9523 __be32 op_to_type; 9524 __be32 len16_pkd; 9525 union fw_error { 9526 struct fw_error_exception { 9527 __be32 info[6]; 9528 } exception; 9529 struct fw_error_hwmodule { 9530 __be32 regaddr; 9531 __be32 regval; 9532 } hwmodule; 9533 struct fw_error_wr { 9534 __be16 cidx; 9535 __be16 pfn_vfn; 9536 __be32 eqid; 9537 __u8 wrhdr[16]; 9538 } wr; 9539 struct fw_error_acl { 9540 __be16 cidx; 9541 __be16 pfn_vfn; 9542 __be32 eqid; 9543 __be16 mv_pkd; 9544 __u8 val[6]; 9545 __be64 r4; 9546 } acl; 9547 } u; 9548 }; 9549 9550 #define S_FW_ERROR_CMD_FATAL 4 9551 #define M_FW_ERROR_CMD_FATAL 0x1 9552 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 9553 #define G_FW_ERROR_CMD_FATAL(x) \ 9554 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 9555 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 9556 9557 #define S_FW_ERROR_CMD_TYPE 0 9558 #define M_FW_ERROR_CMD_TYPE 0xf 9559 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 9560 #define G_FW_ERROR_CMD_TYPE(x) \ 9561 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 9562 9563 #define S_FW_ERROR_CMD_PFN 8 9564 #define M_FW_ERROR_CMD_PFN 0x7 9565 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 9566 #define G_FW_ERROR_CMD_PFN(x) \ 9567 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 9568 9569 #define S_FW_ERROR_CMD_VFN 0 9570 #define M_FW_ERROR_CMD_VFN 0xff 9571 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 9572 #define G_FW_ERROR_CMD_VFN(x) \ 9573 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 9574 9575 #define S_FW_ERROR_CMD_PFN 8 9576 #define M_FW_ERROR_CMD_PFN 0x7 9577 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 9578 #define G_FW_ERROR_CMD_PFN(x) \ 9579 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 9580 9581 #define S_FW_ERROR_CMD_VFN 0 9582 #define M_FW_ERROR_CMD_VFN 0xff 9583 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 9584 #define G_FW_ERROR_CMD_VFN(x) \ 9585 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 9586 9587 #define S_FW_ERROR_CMD_MV 15 9588 #define M_FW_ERROR_CMD_MV 0x1 9589 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 9590 #define G_FW_ERROR_CMD_MV(x) \ 9591 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 9592 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 9593 9594 struct fw_debug_cmd { 9595 __be32 op_type; 9596 __be32 len16_pkd; 9597 union fw_debug { 9598 struct fw_debug_assert { 9599 __be32 fcid; 9600 __be32 line; 9601 __be32 x; 9602 __be32 y; 9603 __u8 filename_0_7[8]; 9604 __u8 filename_8_15[8]; 9605 __be64 r3; 9606 } assert; 9607 struct fw_debug_prt { 9608 __be16 dprtstridx; 9609 __be16 r3[3]; 9610 __be32 dprtstrparam0; 9611 __be32 dprtstrparam1; 9612 __be32 dprtstrparam2; 9613 __be32 dprtstrparam3; 9614 } prt; 9615 } u; 9616 }; 9617 9618 #define S_FW_DEBUG_CMD_TYPE 0 9619 #define M_FW_DEBUG_CMD_TYPE 0xff 9620 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 9621 #define G_FW_DEBUG_CMD_TYPE(x) \ 9622 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 9623 9624 enum fw_diag_cmd_type { 9625 FW_DIAG_CMD_TYPE_OFLDIAG = 0, 9626 }; 9627 9628 enum fw_diag_cmd_ofldiag_op { 9629 FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0, 9630 FW_DIAG_CMD_OFLDIAG_TEST_START, 9631 FW_DIAG_CMD_OFLDIAG_TEST_STOP, 9632 FW_DIAG_CMD_OFLDIAG_TEST_STATUS, 9633 }; 9634 9635 enum fw_diag_cmd_ofldiag_status { 9636 FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0, 9637 FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING, 9638 FW_DIAG_CMD_OFLDIAG_STATUS_FAILED, 9639 FW_DIAG_CMD_OFLDIAG_STATUS_PASSED, 9640 }; 9641 9642 struct fw_diag_cmd { 9643 __be32 op_type; 9644 __be32 len16_pkd; 9645 union fw_diag_test { 9646 struct fw_diag_test_ofldiag { 9647 __u8 test_op; 9648 __u8 r3; 9649 __be16 test_status; 9650 __be32 duration; 9651 } ofldiag; 9652 } u; 9653 }; 9654 9655 #define S_FW_DIAG_CMD_TYPE 0 9656 #define M_FW_DIAG_CMD_TYPE 0xff 9657 #define V_FW_DIAG_CMD_TYPE(x) ((x) << S_FW_DIAG_CMD_TYPE) 9658 #define G_FW_DIAG_CMD_TYPE(x) \ 9659 (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE) 9660 9661 struct fw_hma_cmd { 9662 __be32 op_pkd; 9663 __be32 retval_len16; 9664 __be32 mode_to_pcie_params; 9665 __be32 naddr_size; 9666 __be32 addr_size_pkd; 9667 __be32 r6; 9668 __be64 phy_address[5]; 9669 }; 9670 9671 #define S_FW_HMA_CMD_MODE 31 9672 #define M_FW_HMA_CMD_MODE 0x1 9673 #define V_FW_HMA_CMD_MODE(x) ((x) << S_FW_HMA_CMD_MODE) 9674 #define G_FW_HMA_CMD_MODE(x) \ 9675 (((x) >> S_FW_HMA_CMD_MODE) & M_FW_HMA_CMD_MODE) 9676 #define F_FW_HMA_CMD_MODE V_FW_HMA_CMD_MODE(1U) 9677 9678 #define S_FW_HMA_CMD_SOC 30 9679 #define M_FW_HMA_CMD_SOC 0x1 9680 #define V_FW_HMA_CMD_SOC(x) ((x) << S_FW_HMA_CMD_SOC) 9681 #define G_FW_HMA_CMD_SOC(x) (((x) >> S_FW_HMA_CMD_SOC) & M_FW_HMA_CMD_SOC) 9682 #define F_FW_HMA_CMD_SOC V_FW_HMA_CMD_SOC(1U) 9683 9684 #define S_FW_HMA_CMD_EOC 29 9685 #define M_FW_HMA_CMD_EOC 0x1 9686 #define V_FW_HMA_CMD_EOC(x) ((x) << S_FW_HMA_CMD_EOC) 9687 #define G_FW_HMA_CMD_EOC(x) (((x) >> S_FW_HMA_CMD_EOC) & M_FW_HMA_CMD_EOC) 9688 #define F_FW_HMA_CMD_EOC V_FW_HMA_CMD_EOC(1U) 9689 9690 #define S_FW_HMA_CMD_PCIE_PARAMS 0 9691 #define M_FW_HMA_CMD_PCIE_PARAMS 0x7ffffff 9692 #define V_FW_HMA_CMD_PCIE_PARAMS(x) ((x) << S_FW_HMA_CMD_PCIE_PARAMS) 9693 #define G_FW_HMA_CMD_PCIE_PARAMS(x) \ 9694 (((x) >> S_FW_HMA_CMD_PCIE_PARAMS) & M_FW_HMA_CMD_PCIE_PARAMS) 9695 9696 #define S_FW_HMA_CMD_NADDR 12 9697 #define M_FW_HMA_CMD_NADDR 0x3f 9698 #define V_FW_HMA_CMD_NADDR(x) ((x) << S_FW_HMA_CMD_NADDR) 9699 #define G_FW_HMA_CMD_NADDR(x) \ 9700 (((x) >> S_FW_HMA_CMD_NADDR) & M_FW_HMA_CMD_NADDR) 9701 9702 #define S_FW_HMA_CMD_SIZE 0 9703 #define M_FW_HMA_CMD_SIZE 0xfff 9704 #define V_FW_HMA_CMD_SIZE(x) ((x) << S_FW_HMA_CMD_SIZE) 9705 #define G_FW_HMA_CMD_SIZE(x) \ 9706 (((x) >> S_FW_HMA_CMD_SIZE) & M_FW_HMA_CMD_SIZE) 9707 9708 #define S_FW_HMA_CMD_ADDR_SIZE 11 9709 #define M_FW_HMA_CMD_ADDR_SIZE 0x1fffff 9710 #define V_FW_HMA_CMD_ADDR_SIZE(x) ((x) << S_FW_HMA_CMD_ADDR_SIZE) 9711 #define G_FW_HMA_CMD_ADDR_SIZE(x) \ 9712 (((x) >> S_FW_HMA_CMD_ADDR_SIZE) & M_FW_HMA_CMD_ADDR_SIZE) 9713 9714 /****************************************************************************** 9715 * P C I E F W R E G I S T E R 9716 **************************************/ 9717 9718 enum pcie_fw_eval { 9719 PCIE_FW_EVAL_CRASH = 0, 9720 PCIE_FW_EVAL_PREP = 1, 9721 PCIE_FW_EVAL_CONF = 2, 9722 PCIE_FW_EVAL_INIT = 3, 9723 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 9724 PCIE_FW_EVAL_OVERHEAT = 5, 9725 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 9726 }; 9727 9728 /** 9729 * Register definitions for the PCIE_FW register which the firmware uses 9730 * to retain status across RESETs. This register should be considered 9731 * as a READ-ONLY register for Host Software and only to be used to 9732 * track firmware initialization/error state, etc. 9733 */ 9734 #define S_PCIE_FW_ERR 31 9735 #define M_PCIE_FW_ERR 0x1 9736 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 9737 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 9738 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 9739 9740 #define S_PCIE_FW_INIT 30 9741 #define M_PCIE_FW_INIT 0x1 9742 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 9743 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 9744 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 9745 9746 #define S_PCIE_FW_HALT 29 9747 #define M_PCIE_FW_HALT 0x1 9748 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 9749 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 9750 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 9751 9752 #define S_PCIE_FW_EVAL 24 9753 #define M_PCIE_FW_EVAL 0x7 9754 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 9755 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 9756 9757 #define S_PCIE_FW_STAGE 21 9758 #define M_PCIE_FW_STAGE 0x7 9759 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 9760 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 9761 9762 #define S_PCIE_FW_ASYNCNOT_VLD 20 9763 #define M_PCIE_FW_ASYNCNOT_VLD 0x1 9764 #define V_PCIE_FW_ASYNCNOT_VLD(x) \ 9765 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 9766 #define G_PCIE_FW_ASYNCNOT_VLD(x) \ 9767 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 9768 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 9769 9770 #define S_PCIE_FW_ASYNCNOTINT 19 9771 #define M_PCIE_FW_ASYNCNOTINT 0x1 9772 #define V_PCIE_FW_ASYNCNOTINT(x) \ 9773 ((x) << S_PCIE_FW_ASYNCNOTINT) 9774 #define G_PCIE_FW_ASYNCNOTINT(x) \ 9775 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 9776 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 9777 9778 #define S_PCIE_FW_ASYNCNOT 16 9779 #define M_PCIE_FW_ASYNCNOT 0x7 9780 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 9781 #define G_PCIE_FW_ASYNCNOT(x) \ 9782 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 9783 9784 #define S_PCIE_FW_MASTER_VLD 15 9785 #define M_PCIE_FW_MASTER_VLD 0x1 9786 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 9787 #define G_PCIE_FW_MASTER_VLD(x) \ 9788 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 9789 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 9790 9791 #define S_PCIE_FW_MASTER 12 9792 #define M_PCIE_FW_MASTER 0x7 9793 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 9794 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 9795 9796 #define S_PCIE_FW_RESET_VLD 11 9797 #define M_PCIE_FW_RESET_VLD 0x1 9798 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 9799 #define G_PCIE_FW_RESET_VLD(x) \ 9800 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 9801 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 9802 9803 #define S_PCIE_FW_RESET 8 9804 #define M_PCIE_FW_RESET 0x7 9805 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 9806 #define G_PCIE_FW_RESET(x) \ 9807 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 9808 9809 #define S_PCIE_FW_REGISTERED 0 9810 #define M_PCIE_FW_REGISTERED 0xff 9811 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 9812 #define G_PCIE_FW_REGISTERED(x) \ 9813 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 9814 9815 9816 /****************************************************************************** 9817 * P C I E F W P F 0 R E G I S T E R 9818 **********************************************/ 9819 9820 /* 9821 * this register is available as 32-bit of persistent storage (accross 9822 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver 9823 * will not write it) 9824 */ 9825 9826 9827 /****************************************************************************** 9828 * P C I E F W P F 7 R E G I S T E R 9829 **********************************************/ 9830 9831 /* 9832 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to 9833 * access the "devlog" which needing to contact firmware. The encoding is 9834 * mostly the same as that returned by the DEVLOG command except for the size 9835 * which is encoded as the number of entries in multiples-1 of 128 here rather 9836 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 9837 * and 15 means 2048. This of course in turn constrains the allowed values 9838 * for the devlog size ... 9839 */ 9840 #define PCIE_FW_PF_DEVLOG 7 9841 9842 #define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28 9843 #define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf 9844 #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 9845 ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128) 9846 #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 9847 (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \ 9848 M_PCIE_FW_PF_DEVLOG_NENTRIES128) 9849 9850 #define S_PCIE_FW_PF_DEVLOG_ADDR16 4 9851 #define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff 9852 #define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16) 9853 #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \ 9854 (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16) 9855 9856 #define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0 9857 #define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0xf 9858 #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE) 9859 #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \ 9860 (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE) 9861 9862 9863 /****************************************************************************** 9864 * B I N A R Y H E A D E R F O R M A T 9865 **********************************************/ 9866 9867 /* 9868 * firmware binary header format 9869 */ 9870 struct fw_hdr { 9871 __u8 ver; 9872 __u8 chip; /* terminator chip family */ 9873 __be16 len512; /* bin length in units of 512-bytes */ 9874 __be32 fw_ver; /* firmware version */ 9875 __be32 tp_microcode_ver; /* tcp processor microcode version */ 9876 __u8 intfver_nic; 9877 __u8 intfver_vnic; 9878 __u8 intfver_ofld; 9879 __u8 intfver_ri; 9880 __u8 intfver_iscsipdu; 9881 __u8 intfver_iscsi; 9882 __u8 intfver_fcoepdu; 9883 __u8 intfver_fcoe; 9884 __u32 reserved2; 9885 __u32 reserved3; 9886 __be32 magic; /* runtime or bootstrap fw */ 9887 __be32 flags; 9888 __be32 reserved6[23]; 9889 }; 9890 9891 enum fw_hdr_chip { 9892 FW_HDR_CHIP_T4, 9893 FW_HDR_CHIP_T5, 9894 FW_HDR_CHIP_T6 9895 }; 9896 9897 #define S_FW_HDR_FW_VER_MAJOR 24 9898 #define M_FW_HDR_FW_VER_MAJOR 0xff 9899 #define V_FW_HDR_FW_VER_MAJOR(x) \ 9900 ((x) << S_FW_HDR_FW_VER_MAJOR) 9901 #define G_FW_HDR_FW_VER_MAJOR(x) \ 9902 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 9903 9904 #define S_FW_HDR_FW_VER_MINOR 16 9905 #define M_FW_HDR_FW_VER_MINOR 0xff 9906 #define V_FW_HDR_FW_VER_MINOR(x) \ 9907 ((x) << S_FW_HDR_FW_VER_MINOR) 9908 #define G_FW_HDR_FW_VER_MINOR(x) \ 9909 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 9910 9911 #define S_FW_HDR_FW_VER_MICRO 8 9912 #define M_FW_HDR_FW_VER_MICRO 0xff 9913 #define V_FW_HDR_FW_VER_MICRO(x) \ 9914 ((x) << S_FW_HDR_FW_VER_MICRO) 9915 #define G_FW_HDR_FW_VER_MICRO(x) \ 9916 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 9917 9918 #define S_FW_HDR_FW_VER_BUILD 0 9919 #define M_FW_HDR_FW_VER_BUILD 0xff 9920 #define V_FW_HDR_FW_VER_BUILD(x) \ 9921 ((x) << S_FW_HDR_FW_VER_BUILD) 9922 #define G_FW_HDR_FW_VER_BUILD(x) \ 9923 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 9924 9925 enum { 9926 /* T4 9927 */ 9928 FW_HDR_INTFVER_NIC = 0x00, 9929 FW_HDR_INTFVER_VNIC = 0x00, 9930 FW_HDR_INTFVER_OFLD = 0x00, 9931 FW_HDR_INTFVER_RI = 0x00, 9932 FW_HDR_INTFVER_ISCSIPDU = 0x00, 9933 FW_HDR_INTFVER_ISCSI = 0x00, 9934 FW_HDR_INTFVER_FCOEPDU = 0x00, 9935 FW_HDR_INTFVER_FCOE = 0x00, 9936 9937 /* T5 9938 */ 9939 T5FW_HDR_INTFVER_NIC = 0x00, 9940 T5FW_HDR_INTFVER_VNIC = 0x00, 9941 T5FW_HDR_INTFVER_OFLD = 0x00, 9942 T5FW_HDR_INTFVER_RI = 0x00, 9943 T5FW_HDR_INTFVER_ISCSIPDU= 0x00, 9944 T5FW_HDR_INTFVER_ISCSI = 0x00, 9945 T5FW_HDR_INTFVER_FCOEPDU= 0x00, 9946 T5FW_HDR_INTFVER_FCOE = 0x00, 9947 9948 /* T6 9949 */ 9950 T6FW_HDR_INTFVER_NIC = 0x00, 9951 T6FW_HDR_INTFVER_VNIC = 0x00, 9952 T6FW_HDR_INTFVER_OFLD = 0x00, 9953 T6FW_HDR_INTFVER_RI = 0x00, 9954 T6FW_HDR_INTFVER_ISCSIPDU= 0x00, 9955 T6FW_HDR_INTFVER_ISCSI = 0x00, 9956 T6FW_HDR_INTFVER_FCOEPDU= 0x00, 9957 T6FW_HDR_INTFVER_FCOE = 0x00, 9958 }; 9959 9960 enum { 9961 FW_HDR_MAGIC_RUNTIME = 0x00000000, 9962 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 9963 }; 9964 9965 enum fw_hdr_flags { 9966 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 9967 }; 9968 9969 /* 9970 * External PHY firmware binary header format 9971 */ 9972 struct fw_ephy_hdr { 9973 __u8 ver; 9974 __u8 reserved; 9975 __be16 len512; /* bin length in units of 512-bytes */ 9976 __be32 magic; 9977 9978 __be16 vendor_id; 9979 __be16 device_id; 9980 __be32 version; 9981 9982 __be32 reserved1[4]; 9983 }; 9984 9985 enum { 9986 FW_EPHY_HDR_MAGIC = 0x65706879, 9987 }; 9988 9989 struct fw_ifconf_dhcp_info { 9990 __be32 addr; 9991 __be32 mask; 9992 __be16 vlanid; 9993 __be16 mtu; 9994 __be32 gw; 9995 __u8 op; 9996 __u8 len; 9997 __u8 data[270]; 9998 }; 9999 10000 struct fw_ifconf_ping_info { 10001 __be16 ping_pldsize; 10002 }; 10003 10004 #endif /* _T4FW_INTERFACE_H_ */ 10005