1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Chelsio Terminator 4 (T4) Firmware interface header file. 14 * 15 * Copyright (C) 2009-2013 Chelsio Communications. All rights reserved. 16 * 17 * Written by felix marti (felix@chelsio.com) 18 * 19 * This program is distributed in the hope that it will be useful, but WITHOUT 20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 21 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 22 * release for licensing terms and conditions. 23 */ 24 #ifndef _T4FW_INTERFACE_H_ 25 #define _T4FW_INTERFACE_H_ 26 27 /* 28 * ****************************** 29 * R E T U R N V A L U E S 30 * ****************************** 31 */ 32 33 enum fw_retval { 34 FW_SUCCESS = 0, /* completed sucessfully */ 35 FW_EPERM = 1, /* operation not permitted */ 36 FW_ENOENT = 2, /* no such file or directory */ 37 FW_EIO = 5, /* input/output error; hw bad */ 38 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 39 FW_EAGAIN = 11, /* try again */ 40 FW_ENOMEM = 12, /* out of memory */ 41 FW_EFAULT = 14, /* bad address; fw bad */ 42 FW_EBUSY = 16, /* resource busy */ 43 FW_EEXIST = 17, /* file exists */ 44 FW_ENODEV = 19, /* no such device */ 45 FW_EINVAL = 22, /* invalid argument */ 46 FW_ENOSPC = 28, /* no space left on device */ 47 FW_ENOSYS = 38, /* functionality not implemented */ 48 FW_ENODATA = 61, /* no data available */ 49 FW_EPROTO = 71, /* protocol error */ 50 FW_EADDRINUSE = 98, /* address already in use */ 51 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 52 FW_ENETDOWN = 100, /* network is down */ 53 FW_ENETUNREACH = 101, /* network is unreachable */ 54 FW_ENOBUFS = 105, /* no buffer space available */ 55 FW_ETIMEDOUT = 110, /* timeout */ 56 FW_EINPROGRESS = 115, /* fw internal */ 57 FW_SCSI_ABORT_REQUESTED = 128, /* */ 58 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 59 FW_SCSI_ABORTED = 130, /* */ 60 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 61 FW_ERR_LINK_DOWN = 132, /* */ 62 FW_RDEV_NOT_READY = 133, /* */ 63 FW_ERR_RDEV_LOST = 134, /* */ 64 FW_ERR_RDEV_LOGO = 135, /* */ 65 FW_FCOE_NO_XCHG = 136, /* */ 66 FW_SCSI_RSP_ERR = 137, /* */ 67 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 68 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 69 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 70 FW_SCSI_DDP_ERR = 141, /* DDP error */ 71 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 72 }; 73 74 /* 75 * ****************************** 76 * W O R K R E Q U E S T s 77 * ****************************** 78 */ 79 80 enum fw_wr_opcodes { 81 FW_FRAG_WR = 0x1d, 82 FW_FILTER_WR = 0x02, 83 FW_ULPTX_WR = 0x04, 84 FW_TP_WR = 0x05, 85 FW_ETH_TX_PKT_WR = 0x08, 86 FW_ETH_TX_PKT2_WR = 0x44, 87 FW_ETH_TX_PKTS_WR = 0x09, 88 FW_ETH_TX_UO_WR = 0x1c, 89 FW_EQ_FLUSH_WR = 0x1b, 90 FW_OFLD_CONNECTION_WR = 0x2f, 91 FW_FLOWC_WR = 0x0a, 92 FW_OFLD_TX_DATA_WR = 0x0b, 93 FW_CMD_WR = 0x10, 94 FW_ETH_TX_PKT_VM_WR = 0x11, 95 FW_RI_RES_WR = 0x0c, 96 FW_RI_RDMA_WRITE_WR = 0x14, 97 FW_RI_SEND_WR = 0x15, 98 FW_RI_RDMA_READ_WR = 0x16, 99 FW_RI_RECV_WR = 0x17, 100 FW_RI_BIND_MW_WR = 0x18, 101 FW_RI_FR_NSMR_WR = 0x19, 102 FW_RI_INV_LSTAG_WR = 0x1a, 103 FW_RI_SEND_IMMEDIATE_WR = 0x15, 104 FW_RI_ATOMIC_WR = 0x16, 105 FW_RI_WR = 0x0d, 106 FW_CHNET_IFCONF_WR = 0x6b, 107 FW_RDEV_WR = 0x38, 108 FW_FOISCSI_NODE_WR = 0x60, 109 FW_FOISCSI_CTRL_WR = 0x6a, 110 FW_FOISCSI_CHAP_WR = 0x6c, 111 FW_FCOE_ELS_CT_WR = 0x30, 112 FW_SCSI_WRITE_WR = 0x31, 113 FW_SCSI_READ_WR = 0x32, 114 FW_SCSI_CMD_WR = 0x33, 115 FW_SCSI_ABRT_CLS_WR = 0x34, 116 FW_SCSI_TGT_ACC_WR = 0x35, 117 FW_SCSI_TGT_XMIT_WR = 0x36, 118 FW_SCSI_TGT_RSP_WR = 0x37, 119 FW_POFCOE_TCB_WR = 0x42, 120 FW_POFCOE_ULPTX_WR = 0x43, 121 FW_LASTC2E_WR = 0x70 122 }; 123 124 /* 125 * Generic work request header flit0 126 */ 127 struct fw_wr_hdr { 128 __be32 hi; 129 __be32 lo; 130 }; 131 132 /* work request opcode (hi) */ 133 #define S_FW_WR_OP 24 134 #define M_FW_WR_OP 0xff 135 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 136 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 137 138 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */ 139 #define S_FW_WR_ATOMIC 23 140 #define M_FW_WR_ATOMIC 0x1 141 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 142 #define G_FW_WR_ATOMIC(x) \ 143 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 144 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 145 146 /* 147 * flush flag (hi) - firmware flushes flushable work request buffered 148 * in the flow context. 149 */ 150 #define S_FW_WR_FLUSH 22 151 #define M_FW_WR_FLUSH 0x1 152 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 153 #define G_FW_WR_FLUSH(x) \ 154 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 155 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 156 157 /* completion flag (hi) - firmware generates a cpl_fw6_ack */ 158 #define S_FW_WR_COMPL 21 159 #define M_FW_WR_COMPL 0x1 160 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 161 #define G_FW_WR_COMPL(x) \ 162 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 163 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 164 165 /* work request immediate data lengh (hi) */ 166 #define S_FW_WR_IMMDLEN 0 167 #define M_FW_WR_IMMDLEN 0xff 168 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 169 #define G_FW_WR_IMMDLEN(x) \ 170 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 171 172 /* egress queue status update to associated ingress queue entry (lo) */ 173 #define S_FW_WR_EQUIQ 31 174 #define M_FW_WR_EQUIQ 0x1 175 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 176 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 177 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 178 179 /* egress queue status update to egress queue status entry (lo) */ 180 #define S_FW_WR_EQUEQ 30 181 #define M_FW_WR_EQUEQ 0x1 182 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 183 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 184 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 185 186 /* flow context identifier (lo) */ 187 #define S_FW_WR_FLOWID 8 188 #define M_FW_WR_FLOWID 0xfffff 189 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 190 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 191 192 /* length in units of 16-bytes (lo) */ 193 #define S_FW_WR_LEN16 0 194 #define M_FW_WR_LEN16 0xff 195 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 196 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 197 198 struct fw_frag_wr { 199 __be32 op_to_fragoff16; 200 __be32 flowid_len16; 201 __be64 r4; 202 }; 203 204 #define S_FW_FRAG_WR_EOF 15 205 #define M_FW_FRAG_WR_EOF 0x1 206 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 207 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 208 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 209 210 #define S_FW_FRAG_WR_FRAGOFF16 8 211 #define M_FW_FRAG_WR_FRAGOFF16 0x7f 212 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 213 #define G_FW_FRAG_WR_FRAGOFF16(x) \ 214 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 215 216 /* 217 * valid filter configurations for compressed tuple 218 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 219 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 220 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 221 * OV - Outer VLAN/VNIC_ID, 222 */ 223 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 224 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 225 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 226 #define HW_TPL_FR_MT_M_OV_P_FC 0x387 227 #define HW_TPL_FR_MT_E_PR_T 0x370 228 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 229 #define HW_TPL_FR_MT_E_T_P_FC 0X353 230 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 231 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 232 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 233 #define HW_TPL_FR_MT_T_OV_P_FC 0X317 234 #define HW_TPL_FR_M_E_PR_FC 0X2E1 235 #define HW_TPL_FR_M_E_T_FC 0X2D1 236 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 237 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 238 #define HW_TPL_FR_M_T_IV_FC 0X299 239 #define HW_TPL_FR_M_T_OV_FC 0X295 240 #define HW_TPL_FR_E_PR_T_P 0X272 241 #define HW_TPL_FR_E_PR_T_FC 0X271 242 #define HW_TPL_FR_E_IV_FC 0X249 243 #define HW_TPL_FR_E_OV_FC 0X245 244 #define HW_TPL_FR_PR_T_IV_FC 0X239 245 #define HW_TPL_FR_PR_T_OV_FC 0X235 246 #define HW_TPL_FR_IV_OV_FC 0X20D 247 #define HW_TPL_MT_M_E_PR 0X1E0 248 #define HW_TPL_MT_M_E_T 0X1D0 249 #define HW_TPL_MT_E_PR_T_FC 0X171 250 #define HW_TPL_MT_E_IV 0X148 251 #define HW_TPL_MT_E_OV 0X144 252 #define HW_TPL_MT_PR_T_IV 0X138 253 #define HW_TPL_MT_PR_T_OV 0X134 254 #define HW_TPL_M_E_PR_P 0X0E2 255 #define HW_TPL_M_E_T_P 0X0D2 256 #define HW_TPL_E_PR_T_P_FC 0X073 257 #define HW_TPL_E_IV_P 0X04A 258 #define HW_TPL_E_OV_P 0X046 259 #define HW_TPL_PR_T_IV_P 0X03A 260 #define HW_TPL_PR_T_OV_P 0X036 261 262 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 263 enum fw_filter_wr_cookie { 264 FW_FILTER_WR_SUCCESS, 265 FW_FILTER_WR_FLT_ADDED, 266 FW_FILTER_WR_FLT_DELETED, 267 FW_FILTER_WR_SMT_TBL_FULL, 268 FW_FILTER_WR_EINVAL, 269 }; 270 271 struct fw_filter_wr { 272 __be32 op_pkd; 273 __be32 len16_pkd; 274 __be64 r3; 275 __be32 tid_to_iq; 276 __be32 del_filter_to_l2tix; 277 __be16 ethtype; 278 __be16 ethtypem; 279 __u8 frag_to_ovlan_vldm; 280 __u8 smac_sel; 281 __be16 rx_chan_rx_rpl_iq; 282 __be32 maci_to_matchtypem; 283 __u8 ptcl; 284 __u8 ptclm; 285 __u8 ttyp; 286 __u8 ttypm; 287 __be16 ivlan; 288 __be16 ivlanm; 289 __be16 ovlan; 290 __be16 ovlanm; 291 __u8 lip[16]; 292 __u8 lipm[16]; 293 __u8 fip[16]; 294 __u8 fipm[16]; 295 __be16 lp; 296 __be16 lpm; 297 __be16 fp; 298 __be16 fpm; 299 __be16 r7; 300 __u8 sma[6]; 301 }; 302 303 #define S_FW_FILTER_WR_TID 12 304 #define M_FW_FILTER_WR_TID 0xfffff 305 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 306 #define G_FW_FILTER_WR_TID(x) \ 307 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 308 309 #define S_FW_FILTER_WR_RQTYPE 11 310 #define M_FW_FILTER_WR_RQTYPE 0x1 311 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 312 #define G_FW_FILTER_WR_RQTYPE(x) \ 313 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 314 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 315 316 #define S_FW_FILTER_WR_NOREPLY 10 317 #define M_FW_FILTER_WR_NOREPLY 0x1 318 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 319 #define G_FW_FILTER_WR_NOREPLY(x) \ 320 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 321 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 322 323 #define S_FW_FILTER_WR_IQ 0 324 #define M_FW_FILTER_WR_IQ 0x3ff 325 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 326 #define G_FW_FILTER_WR_IQ(x) \ 327 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 328 329 #define S_FW_FILTER_WR_DEL_FILTER 31 330 #define M_FW_FILTER_WR_DEL_FILTER 0x1 331 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 332 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 333 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 334 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 335 336 #define S_FW_FILTER_WR_RPTTID 25 337 #define M_FW_FILTER_WR_RPTTID 0x1 338 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 339 #define G_FW_FILTER_WR_RPTTID(x) \ 340 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 341 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 342 343 #define S_FW_FILTER_WR_DROP 24 344 #define M_FW_FILTER_WR_DROP 0x1 345 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 346 #define G_FW_FILTER_WR_DROP(x) \ 347 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 348 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 349 350 #define S_FW_FILTER_WR_DIRSTEER 23 351 #define M_FW_FILTER_WR_DIRSTEER 0x1 352 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 353 #define G_FW_FILTER_WR_DIRSTEER(x) \ 354 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 355 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 356 357 #define S_FW_FILTER_WR_MASKHASH 22 358 #define M_FW_FILTER_WR_MASKHASH 0x1 359 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 360 #define G_FW_FILTER_WR_MASKHASH(x) \ 361 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 362 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 363 364 #define S_FW_FILTER_WR_DIRSTEERHASH 21 365 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 366 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 367 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 368 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 369 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 370 371 #define S_FW_FILTER_WR_LPBK 20 372 #define M_FW_FILTER_WR_LPBK 0x1 373 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 374 #define G_FW_FILTER_WR_LPBK(x) \ 375 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 376 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 377 378 #define S_FW_FILTER_WR_DMAC 19 379 #define M_FW_FILTER_WR_DMAC 0x1 380 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 381 #define G_FW_FILTER_WR_DMAC(x) \ 382 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 383 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 384 385 #define S_FW_FILTER_WR_SMAC 18 386 #define M_FW_FILTER_WR_SMAC 0x1 387 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 388 #define G_FW_FILTER_WR_SMAC(x) \ 389 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 390 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 391 392 #define S_FW_FILTER_WR_INSVLAN 17 393 #define M_FW_FILTER_WR_INSVLAN 0x1 394 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 395 #define G_FW_FILTER_WR_INSVLAN(x) \ 396 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 397 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 398 399 #define S_FW_FILTER_WR_RMVLAN 16 400 #define M_FW_FILTER_WR_RMVLAN 0x1 401 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 402 #define G_FW_FILTER_WR_RMVLAN(x) \ 403 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 404 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 405 406 #define S_FW_FILTER_WR_HITCNTS 15 407 #define M_FW_FILTER_WR_HITCNTS 0x1 408 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 409 #define G_FW_FILTER_WR_HITCNTS(x) \ 410 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 411 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 412 413 #define S_FW_FILTER_WR_TXCHAN 13 414 #define M_FW_FILTER_WR_TXCHAN 0x3 415 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 416 #define G_FW_FILTER_WR_TXCHAN(x) \ 417 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 418 419 #define S_FW_FILTER_WR_PRIO 12 420 #define M_FW_FILTER_WR_PRIO 0x1 421 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 422 #define G_FW_FILTER_WR_PRIO(x) \ 423 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 424 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 425 426 #define S_FW_FILTER_WR_L2TIX 0 427 #define M_FW_FILTER_WR_L2TIX 0xfff 428 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 429 #define G_FW_FILTER_WR_L2TIX(x) \ 430 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 431 432 #define S_FW_FILTER_WR_FRAG 7 433 #define M_FW_FILTER_WR_FRAG 0x1 434 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 435 #define G_FW_FILTER_WR_FRAG(x) \ 436 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 437 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 438 439 #define S_FW_FILTER_WR_FRAGM 6 440 #define M_FW_FILTER_WR_FRAGM 0x1 441 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 442 #define G_FW_FILTER_WR_FRAGM(x) \ 443 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 444 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 445 446 #define S_FW_FILTER_WR_IVLAN_VLD 5 447 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 448 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 449 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 450 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 451 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 452 453 #define S_FW_FILTER_WR_OVLAN_VLD 4 454 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 455 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 456 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 457 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 458 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 459 460 #define S_FW_FILTER_WR_IVLAN_VLDM 3 461 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 462 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 463 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 464 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 465 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 466 467 #define S_FW_FILTER_WR_OVLAN_VLDM 2 468 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 469 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 470 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 471 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 472 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 473 474 #define S_FW_FILTER_WR_RX_CHAN 15 475 #define M_FW_FILTER_WR_RX_CHAN 0x1 476 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 477 #define G_FW_FILTER_WR_RX_CHAN(x) \ 478 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 479 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 480 481 #define S_FW_FILTER_WR_RX_RPL_IQ 0 482 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 483 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 484 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 485 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 486 487 #define S_FW_FILTER_WR_MACI 23 488 #define M_FW_FILTER_WR_MACI 0x1ff 489 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 490 #define G_FW_FILTER_WR_MACI(x) \ 491 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 492 493 #define S_FW_FILTER_WR_MACIM 14 494 #define M_FW_FILTER_WR_MACIM 0x1ff 495 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 496 #define G_FW_FILTER_WR_MACIM(x) \ 497 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 498 499 #define S_FW_FILTER_WR_FCOE 13 500 #define M_FW_FILTER_WR_FCOE 0x1 501 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 502 #define G_FW_FILTER_WR_FCOE(x) \ 503 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 504 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 505 506 #define S_FW_FILTER_WR_FCOEM 12 507 #define M_FW_FILTER_WR_FCOEM 0x1 508 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 509 #define G_FW_FILTER_WR_FCOEM(x) \ 510 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 511 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 512 513 #define S_FW_FILTER_WR_PORT 9 514 #define M_FW_FILTER_WR_PORT 0x7 515 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 516 #define G_FW_FILTER_WR_PORT(x) \ 517 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 518 519 #define S_FW_FILTER_WR_PORTM 6 520 #define M_FW_FILTER_WR_PORTM 0x7 521 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 522 #define G_FW_FILTER_WR_PORTM(x) \ 523 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 524 525 #define S_FW_FILTER_WR_MATCHTYPE 3 526 #define M_FW_FILTER_WR_MATCHTYPE 0x7 527 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 528 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 529 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 530 531 #define S_FW_FILTER_WR_MATCHTYPEM 0 532 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 533 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 534 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 535 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 536 537 struct fw_ulptx_wr { 538 __be32 op_to_compl; 539 __be32 flowid_len16; 540 __u64 cookie; 541 }; 542 543 struct fw_tp_wr { 544 __be32 op_to_immdlen; 545 __be32 flowid_len16; 546 __u64 cookie; 547 }; 548 549 struct fw_eth_tx_pkt_wr { 550 __be32 op_immdlen; 551 __be32 equiq_to_len16; 552 __be64 r3; 553 }; 554 555 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 556 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 557 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 558 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 559 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 560 561 struct fw_eth_tx_pkt2_wr { 562 __be32 op_immdlen; 563 __be32 equiq_to_len16; 564 __be32 r3; 565 __be32 L4ChkDisable_to_IpHdrLen; 566 }; 567 568 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 569 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 570 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 571 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 572 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 573 574 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 575 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 576 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 577 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 578 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 579 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 580 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 581 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 582 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 583 584 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 585 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 586 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 587 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 588 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 589 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 590 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 591 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 592 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 593 594 #define S_FW_ETH_TX_PKT2_WR_IVLAN 28 595 #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 596 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 597 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 598 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 599 #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 600 601 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 602 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 603 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 604 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 605 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 606 607 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 608 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 609 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 610 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 611 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 612 613 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 614 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 615 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 616 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 617 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 618 619 struct fw_eth_tx_pkts_wr { 620 __be32 op_pkd; 621 __be32 equiq_to_len16; 622 __be32 r3; 623 __be16 plen; 624 __u8 npkt; 625 __u8 type; 626 }; 627 628 struct fw_eth_tx_uo_wr { 629 __be32 op_immdlen; 630 __be32 equiq_to_len16; 631 __be64 r3; 632 __u8 r4; 633 __u8 ethlen; 634 __be16 iplen; 635 __u8 udplen; 636 __u8 rtplen; 637 __be16 r5; 638 __be16 mss; 639 __be16 schedpktsize; 640 __be32 length; 641 }; 642 643 struct fw_eq_flush_wr { 644 __u8 opcode; 645 __u8 r1[3]; 646 __be32 equiq_to_len16; 647 __be64 r3; 648 }; 649 650 struct fw_ofld_connection_wr { 651 __be32 op_compl; 652 __be32 len16_pkd; 653 __u64 cookie; 654 __be64 r2; 655 __be64 r3; 656 struct fw_ofld_connection_le { 657 __be32 version_cpl; 658 __be32 filter; 659 __be32 r1; 660 __be16 lport; 661 __be16 pport; 662 union fw_ofld_connection_leip { 663 struct fw_ofld_connection_le_ipv4 { 664 __be32 pip; 665 __be32 lip; 666 __be64 r0; 667 __be64 r1; 668 __be64 r2; 669 } ipv4; 670 struct fw_ofld_connection_le_ipv6 { 671 __be64 pip_hi; 672 __be64 pip_lo; 673 __be64 lip_hi; 674 __be64 lip_lo; 675 } ipv6; 676 } u; 677 } le; 678 struct fw_ofld_connection_tcb { 679 __be32 t_state_to_astid; 680 __be16 cplrxdataack_cplpassacceptrpl; 681 __be16 rcv_adv; 682 __be32 rcv_nxt; 683 __be32 tx_max; 684 __be64 opt0; 685 __be32 opt2; 686 __be32 r1; 687 __be64 r2; 688 __be64 r3; 689 } tcb; 690 }; 691 692 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 693 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 694 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 695 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 696 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 697 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 698 M_FW_OFLD_CONNECTION_WR_VERSION) 699 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 700 701 #define S_FW_OFLD_CONNECTION_WR_CPL 30 702 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 703 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 704 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 705 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 706 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 707 708 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 709 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 710 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 711 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 712 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 713 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 714 M_FW_OFLD_CONNECTION_WR_T_STATE) 715 716 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 717 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 718 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 719 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 720 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 721 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 722 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 723 724 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 725 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 726 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 727 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 728 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 729 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 730 731 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 732 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 733 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 734 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 735 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 736 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 737 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 738 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 739 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 740 741 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 742 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 743 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 744 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 745 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 746 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 747 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 748 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 749 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 750 751 enum fw_flowc_mnem_tcpstate { 752 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 753 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 754 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 755 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 756 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 757 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 758 /* haven't gotten ACK for FIN and will resend FIN - equiv ESTAB */ 759 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, 760 /* haven't gotten ACK for FIN & will resend FIN but have received FIN */ 761 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, 762 /* haven't gotten ACK for FIN & will resend FIN but have received FIN */ 763 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, 764 /* sent FIN and got FIN + ACK, waiting for FIN */ 765 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, 766 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 767 }; 768 769 enum fw_flowc_mnem_uostate { 770 FW_FLOWC_MNEM_UOSTATE_CLOSED = 0, /* illegal */ 771 FW_FLOWC_MNEM_UOSTATE_ESTABLISHED = 1, /* default */ 772 /* graceful close, after sending outstanding payload */ 773 FW_FLOWC_MNEM_UOSTATE_CLOSING = 2, 774 /* immediate close, after discarding outstanding payload */ 775 FW_FLOWC_MNEM_UOSTATE_ABORTING = 3, 776 }; 777 778 enum fw_flowc_mnem { 779 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 780 FW_FLOWC_MNEM_CH = 1, 781 FW_FLOWC_MNEM_PORT = 2, 782 FW_FLOWC_MNEM_IQID = 3, 783 FW_FLOWC_MNEM_SNDNXT = 4, 784 FW_FLOWC_MNEM_RCVNXT = 5, 785 FW_FLOWC_MNEM_SNDBUF = 6, 786 FW_FLOWC_MNEM_MSS = 7, 787 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 788 FW_FLOWC_MNEM_TCPSTATE = 9, 789 FW_FLOWC_MNEM_UOSTATE = 10, 790 FW_FLOWC_MNEM_SCHEDCLASS = 11, 791 FW_FLOWC_MNEM_DCBPRIO = 12, 792 }; 793 794 struct fw_flowc_mnemval { 795 __u8 mnemonic; 796 __u8 r4[3]; 797 __be32 val; 798 }; 799 800 struct fw_flowc_wr { 801 __be32 op_to_nparams; 802 __be32 flowid_len16; 803 #ifndef C99_NOT_SUPPORTED 804 struct fw_flowc_mnemval mnemval[]; 805 #endif 806 }; 807 808 #define S_FW_FLOWC_WR_NPARAMS 0 809 #define M_FW_FLOWC_WR_NPARAMS 0xff 810 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 811 #define G_FW_FLOWC_WR_NPARAMS(x) \ 812 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 813 814 struct fw_ofld_tx_data_wr { 815 __be32 op_to_immdlen; 816 __be32 flowid_len16; 817 __be32 plen; 818 __be32 tunnel_to_proxy; 819 }; 820 821 #define S_FW_OFLD_TX_DATA_WR_TUNNEL 19 822 #define M_FW_OFLD_TX_DATA_WR_TUNNEL 0x1 823 #define V_FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL) 824 #define G_FW_OFLD_TX_DATA_WR_TUNNEL(x) \ 825 (((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL) 826 #define F_FW_OFLD_TX_DATA_WR_TUNNEL V_FW_OFLD_TX_DATA_WR_TUNNEL(1U) 827 828 #define S_FW_OFLD_TX_DATA_WR_SAVE 18 829 #define M_FW_OFLD_TX_DATA_WR_SAVE 0x1 830 #define V_FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SAVE) 831 #define G_FW_OFLD_TX_DATA_WR_SAVE(x) \ 832 (((x) >> S_FW_OFLD_TX_DATA_WR_SAVE) & M_FW_OFLD_TX_DATA_WR_SAVE) 833 #define F_FW_OFLD_TX_DATA_WR_SAVE V_FW_OFLD_TX_DATA_WR_SAVE(1U) 834 835 #define S_FW_OFLD_TX_DATA_WR_FLUSH 17 836 #define M_FW_OFLD_TX_DATA_WR_FLUSH 0x1 837 #define V_FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLUSH) 838 #define G_FW_OFLD_TX_DATA_WR_FLUSH(x) \ 839 (((x) >> S_FW_OFLD_TX_DATA_WR_FLUSH) & M_FW_OFLD_TX_DATA_WR_FLUSH) 840 #define F_FW_OFLD_TX_DATA_WR_FLUSH V_FW_OFLD_TX_DATA_WR_FLUSH(1U) 841 842 #define S_FW_OFLD_TX_DATA_WR_URGENT 16 843 #define M_FW_OFLD_TX_DATA_WR_URGENT 0x1 844 #define V_FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << S_FW_OFLD_TX_DATA_WR_URGENT) 845 #define G_FW_OFLD_TX_DATA_WR_URGENT(x) \ 846 (((x) >> S_FW_OFLD_TX_DATA_WR_URGENT) & M_FW_OFLD_TX_DATA_WR_URGENT) 847 #define F_FW_OFLD_TX_DATA_WR_URGENT V_FW_OFLD_TX_DATA_WR_URGENT(1U) 848 849 #define S_FW_OFLD_TX_DATA_WR_MORE 15 850 #define M_FW_OFLD_TX_DATA_WR_MORE 0x1 851 #define V_FW_OFLD_TX_DATA_WR_MORE(x) ((x) << S_FW_OFLD_TX_DATA_WR_MORE) 852 #define G_FW_OFLD_TX_DATA_WR_MORE(x) \ 853 (((x) >> S_FW_OFLD_TX_DATA_WR_MORE) & M_FW_OFLD_TX_DATA_WR_MORE) 854 #define F_FW_OFLD_TX_DATA_WR_MORE V_FW_OFLD_TX_DATA_WR_MORE(1U) 855 856 #define S_FW_OFLD_TX_DATA_WR_SHOVE 14 857 #define M_FW_OFLD_TX_DATA_WR_SHOVE 0x1 858 #define V_FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SHOVE) 859 #define G_FW_OFLD_TX_DATA_WR_SHOVE(x) \ 860 (((x) >> S_FW_OFLD_TX_DATA_WR_SHOVE) & M_FW_OFLD_TX_DATA_WR_SHOVE) 861 #define F_FW_OFLD_TX_DATA_WR_SHOVE V_FW_OFLD_TX_DATA_WR_SHOVE(1U) 862 863 #define S_FW_OFLD_TX_DATA_WR_ULPMODE 10 864 #define M_FW_OFLD_TX_DATA_WR_ULPMODE 0xf 865 #define V_FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << S_FW_OFLD_TX_DATA_WR_ULPMODE) 866 #define G_FW_OFLD_TX_DATA_WR_ULPMODE(x) \ 867 (((x) >> S_FW_OFLD_TX_DATA_WR_ULPMODE) & M_FW_OFLD_TX_DATA_WR_ULPMODE) 868 869 #define S_FW_OFLD_TX_DATA_WR_ULPSUBMODE 6 870 #define M_FW_OFLD_TX_DATA_WR_ULPSUBMODE 0xf 871 #define V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ 872 ((x) << S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) 873 #define G_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ 874 (((x) >> S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) & \ 875 M_FW_OFLD_TX_DATA_WR_ULPSUBMODE) 876 877 #define S_FW_OFLD_TX_DATA_WR_PROXY 5 878 #define M_FW_OFLD_TX_DATA_WR_PROXY 0x1 879 #define V_FW_OFLD_TX_DATA_WR_PROXY(x) ((x) << S_FW_OFLD_TX_DATA_WR_PROXY) 880 #define G_FW_OFLD_TX_DATA_WR_PROXY(x) \ 881 (((x) >> S_FW_OFLD_TX_DATA_WR_PROXY) & M_FW_OFLD_TX_DATA_WR_PROXY) 882 #define F_FW_OFLD_TX_DATA_WR_PROXY V_FW_OFLD_TX_DATA_WR_PROXY(1U) 883 884 struct fw_cmd_wr { 885 __be32 op_dma; 886 __be32 len16_pkd; 887 __be64 cookie_daddr; 888 }; 889 890 #define S_FW_CMD_WR_DMA 17 891 #define M_FW_CMD_WR_DMA 0x1 892 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 893 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 894 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 895 896 struct fw_eth_tx_pkt_vm_wr { 897 __be32 op_immdlen; 898 __be32 equiq_to_len16; 899 __be32 r3[2]; 900 __u8 ethmacdst[6]; 901 __u8 ethmacsrc[6]; 902 __be16 ethtype; 903 __be16 vlantci; 904 }; 905 906 /* 907 * ************************************ 908 * R I W O R K R E Q U E S T s 909 * ************************************ 910 */ 911 912 enum fw_ri_wr_opcode { 913 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 914 FW_RI_READ_REQ = 0x1, 915 FW_RI_READ_RESP = 0x2, 916 FW_RI_SEND = 0x3, 917 FW_RI_SEND_WITH_INV = 0x4, 918 FW_RI_SEND_WITH_SE = 0x5, 919 FW_RI_SEND_WITH_SE_INV = 0x6, 920 FW_RI_TERMINATE = 0x7, 921 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 922 FW_RI_BIND_MW = 0x9, 923 FW_RI_FAST_REGISTER = 0xa, 924 FW_RI_LOCAL_INV = 0xb, 925 FW_RI_QP_MODIFY = 0xc, 926 FW_RI_BYPASS = 0xd, 927 FW_RI_RECEIVE = 0xe, 928 FW_RI_SGE_EC_CR_RETURN = 0xf 929 930 }; 931 932 enum fw_ri_wr_flags { 933 FW_RI_COMPLETION_FLAG = 0x01, 934 FW_RI_NOTIFICATION_FLAG = 0x02, 935 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 936 FW_RI_READ_FENCE_FLAG = 0x08, 937 FW_RI_LOCAL_FENCE_FLAG = 0x10, 938 FW_RI_RDMA_READ_INVALIDATE = 0x20 939 }; 940 941 enum fw_ri_mpa_attrs { 942 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 943 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 944 FW_RI_MPA_CRC_ENABLE = 0x04, 945 FW_RI_MPA_IETF_ENABLE = 0x08 946 }; 947 948 enum fw_ri_qp_caps { 949 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 950 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 951 FW_RI_QP_BIND_ENABLE = 0x04, 952 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 953 FW_RI_QP_STAG0_ENABLE = 0x10, 954 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE = 0x80, 955 }; 956 957 enum fw_ri_addr_type { 958 FW_RI_ZERO_BASED_TO = 0x00, 959 FW_RI_VA_BASED_TO = 0x01 960 }; 961 962 enum fw_ri_mem_perms { 963 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 964 FW_RI_MEM_ACCESS_REM_READ = 0x02, 965 FW_RI_MEM_ACCESS_REM = 0x03, 966 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 967 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 968 FW_RI_MEM_ACCESS_LOCAL = 0x0C 969 }; 970 971 enum fw_ri_stag_type { 972 FW_RI_STAG_NSMR = 0x00, 973 FW_RI_STAG_SMR = 0x01, 974 FW_RI_STAG_MW = 0x02, 975 FW_RI_STAG_MW_RELAXED = 0x03 976 }; 977 978 enum fw_ri_data_op { 979 FW_RI_DATA_IMMD = 0x81, 980 FW_RI_DATA_DSGL = 0x82, 981 FW_RI_DATA_ISGL = 0x83 982 }; 983 984 enum fw_ri_sgl_depth { 985 FW_RI_SGL_DEPTH_MAX_SQ = 16, 986 FW_RI_SGL_DEPTH_MAX_RQ = 4 987 }; 988 989 enum fw_ri_cqe_err { 990 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 991 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 992 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 993 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 994 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 995 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 996 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 997 /* attempt to invalidate a SMR */ 998 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, 999 /* attempt to invalidate a MR w MW */ 1000 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, 1001 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1002 /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1003 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, 1004 /* pbl address out of bound : software error */ 1005 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, 1006 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 1007 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 1008 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 1009 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 1010 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 1011 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 1012 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 1013 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 1014 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 1015 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1016 /* MO not zero for TERMINATE or READ_REQ */ 1017 FW_RI_CQE_ERR_MO = 0x1A, 1018 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 1019 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 1020 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1021 /* RQE address out of bound : software error */ 1022 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, 1023 /* internel error (opcode mismatch) */ 1024 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F 1025 1026 }; 1027 1028 struct fw_ri_dsge_pair { 1029 __be32 len[2]; 1030 __be64 addr[2]; 1031 }; 1032 1033 struct fw_ri_dsgl { 1034 __u8 op; 1035 __u8 r1; 1036 __be16 nsge; 1037 __be32 len0; 1038 __be64 addr0; 1039 #ifndef C99_NOT_SUPPORTED 1040 struct fw_ri_dsge_pair sge[]; 1041 #endif 1042 }; 1043 1044 struct fw_ri_sge { 1045 __be32 stag; 1046 __be32 len; 1047 __be64 to; 1048 }; 1049 1050 struct fw_ri_isgl { 1051 __u8 op; 1052 __u8 r1; 1053 __be16 nsge; 1054 __be32 r2; 1055 #ifndef C99_NOT_SUPPORTED 1056 struct fw_ri_sge sge[]; 1057 #endif 1058 }; 1059 1060 struct fw_ri_immd { 1061 __u8 op; 1062 __u8 r1; 1063 __be16 r2; 1064 __be32 immdlen; 1065 #ifndef C99_NOT_SUPPORTED 1066 __u8 data[]; 1067 #endif 1068 }; 1069 1070 struct fw_ri_tpte { 1071 __be32 valid_to_pdid; 1072 __be32 locread_to_qpid; 1073 __be32 nosnoop_pbladdr; 1074 __be32 len_lo; 1075 __be32 va_hi; 1076 __be32 va_lo_fbo; 1077 __be32 dca_mwbcnt_pstag; 1078 __be32 len_hi; 1079 }; 1080 1081 #define S_FW_RI_TPTE_VALID 31 1082 #define M_FW_RI_TPTE_VALID 0x1 1083 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1084 #define G_FW_RI_TPTE_VALID(x) \ 1085 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1086 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1087 1088 #define S_FW_RI_TPTE_STAGKEY 23 1089 #define M_FW_RI_TPTE_STAGKEY 0xff 1090 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1091 #define G_FW_RI_TPTE_STAGKEY(x) \ 1092 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1093 1094 #define S_FW_RI_TPTE_STAGSTATE 22 1095 #define M_FW_RI_TPTE_STAGSTATE 0x1 1096 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1097 #define G_FW_RI_TPTE_STAGSTATE(x) \ 1098 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1099 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1100 1101 #define S_FW_RI_TPTE_STAGTYPE 20 1102 #define M_FW_RI_TPTE_STAGTYPE 0x3 1103 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1104 #define G_FW_RI_TPTE_STAGTYPE(x) \ 1105 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1106 1107 #define S_FW_RI_TPTE_PDID 0 1108 #define M_FW_RI_TPTE_PDID 0xfffff 1109 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1110 #define G_FW_RI_TPTE_PDID(x) \ 1111 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1112 1113 #define S_FW_RI_TPTE_PERM 28 1114 #define M_FW_RI_TPTE_PERM 0xf 1115 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1116 #define G_FW_RI_TPTE_PERM(x) \ 1117 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1118 1119 #define S_FW_RI_TPTE_REMINVDIS 27 1120 #define M_FW_RI_TPTE_REMINVDIS 0x1 1121 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1122 #define G_FW_RI_TPTE_REMINVDIS(x) \ 1123 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1124 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1125 1126 #define S_FW_RI_TPTE_ADDRTYPE 26 1127 #define M_FW_RI_TPTE_ADDRTYPE 1 1128 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1129 #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1130 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1131 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1132 1133 #define S_FW_RI_TPTE_MWBINDEN 25 1134 #define M_FW_RI_TPTE_MWBINDEN 0x1 1135 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1136 #define G_FW_RI_TPTE_MWBINDEN(x) \ 1137 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1138 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1139 1140 #define S_FW_RI_TPTE_PS 20 1141 #define M_FW_RI_TPTE_PS 0x1f 1142 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1143 #define G_FW_RI_TPTE_PS(x) \ 1144 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1145 1146 #define S_FW_RI_TPTE_QPID 0 1147 #define M_FW_RI_TPTE_QPID 0xfffff 1148 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1149 #define G_FW_RI_TPTE_QPID(x) \ 1150 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1151 1152 #define S_FW_RI_TPTE_NOSNOOP 31 1153 #define M_FW_RI_TPTE_NOSNOOP 0x1 1154 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1155 #define G_FW_RI_TPTE_NOSNOOP(x) \ 1156 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1157 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1158 1159 #define S_FW_RI_TPTE_PBLADDR 0 1160 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1161 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1162 #define G_FW_RI_TPTE_PBLADDR(x) \ 1163 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1164 1165 #define S_FW_RI_TPTE_DCA 24 1166 #define M_FW_RI_TPTE_DCA 0x1f 1167 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1168 #define G_FW_RI_TPTE_DCA(x) \ 1169 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1170 1171 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1172 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1173 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1174 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1175 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1176 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1177 1178 enum fw_ri_cqe_rxtx { 1179 FW_RI_CQE_RXTX_RX = 0x0, 1180 FW_RI_CQE_RXTX_TX = 0x1, 1181 }; 1182 1183 struct fw_ri_cqe { 1184 union fw_ri_rxtx { 1185 struct fw_ri_scqe { 1186 __be32 qpid_n_stat_rxtx_type; 1187 __be32 plen; 1188 __be32 reserved; 1189 __be32 wrid; 1190 } scqe; 1191 struct fw_ri_rcqe { 1192 __be32 qpid_n_stat_rxtx_type; 1193 __be32 plen; 1194 __be32 stag; 1195 __be32 msn; 1196 } rcqe; 1197 } u; 1198 }; 1199 1200 #define S_FW_RI_CQE_QPID 12 1201 #define M_FW_RI_CQE_QPID 0xfffff 1202 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1203 #define G_FW_RI_CQE_QPID(x) \ 1204 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1205 1206 #define S_FW_RI_CQE_NOTIFY 10 1207 #define M_FW_RI_CQE_NOTIFY 0x1 1208 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1209 #define G_FW_RI_CQE_NOTIFY(x) \ 1210 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1211 1212 #define S_FW_RI_CQE_STATUS 5 1213 #define M_FW_RI_CQE_STATUS 0x1f 1214 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1215 #define G_FW_RI_CQE_STATUS(x) \ 1216 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1217 1218 #define S_FW_RI_CQE_RXTX 4 1219 #define M_FW_RI_CQE_RXTX 0x1 1220 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1221 #define G_FW_RI_CQE_RXTX(x) \ 1222 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1223 1224 #define S_FW_RI_CQE_TYPE 0 1225 #define M_FW_RI_CQE_TYPE 0xf 1226 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1227 #define G_FW_RI_CQE_TYPE(x) \ 1228 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1229 1230 enum fw_ri_res_type { 1231 FW_RI_RES_TYPE_SQ, 1232 FW_RI_RES_TYPE_RQ, 1233 FW_RI_RES_TYPE_CQ, 1234 }; 1235 1236 enum fw_ri_res_op { 1237 FW_RI_RES_OP_WRITE, 1238 FW_RI_RES_OP_RESET, 1239 }; 1240 1241 struct fw_ri_res { 1242 union fw_ri_restype { 1243 struct fw_ri_res_sqrq { 1244 __u8 restype; 1245 __u8 op; 1246 __be16 r3; 1247 __be32 eqid; 1248 __be32 r4[2]; 1249 __be32 fetchszm_to_iqid; 1250 __be32 dcaen_to_eqsize; 1251 __be64 eqaddr; 1252 } sqrq; 1253 struct fw_ri_res_cq { 1254 __u8 restype; 1255 __u8 op; 1256 __be16 r3; 1257 __be32 iqid; 1258 __be32 r4[2]; 1259 __be32 iqandst_to_iqandstindex; 1260 __be16 iqdroprss_to_iqesize; 1261 __be16 iqsize; 1262 __be64 iqaddr; 1263 __be32 iqns_iqro; 1264 __be32 r6_lo; 1265 __be64 r7; 1266 } cq; 1267 } u; 1268 }; 1269 1270 struct fw_ri_res_wr { 1271 __be32 op_nres; 1272 __be32 len16_pkd; 1273 __u64 cookie; 1274 #ifndef C99_NOT_SUPPORTED 1275 struct fw_ri_res res[]; 1276 #endif 1277 }; 1278 1279 #define S_FW_RI_RES_WR_NRES 0 1280 #define M_FW_RI_RES_WR_NRES 0xff 1281 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1282 #define G_FW_RI_RES_WR_NRES(x) \ 1283 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1284 1285 #define S_FW_RI_RES_WR_FETCHSZM 26 1286 #define M_FW_RI_RES_WR_FETCHSZM 0x1 1287 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1288 #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1289 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1290 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1291 1292 #define S_FW_RI_RES_WR_STATUSPGNS 25 1293 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1294 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1295 #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1296 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1297 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1298 1299 #define S_FW_RI_RES_WR_STATUSPGRO 24 1300 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1301 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1302 #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1303 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1304 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1305 1306 #define S_FW_RI_RES_WR_FETCHNS 23 1307 #define M_FW_RI_RES_WR_FETCHNS 0x1 1308 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1309 #define G_FW_RI_RES_WR_FETCHNS(x) \ 1310 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1311 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1312 1313 #define S_FW_RI_RES_WR_FETCHRO 22 1314 #define M_FW_RI_RES_WR_FETCHRO 0x1 1315 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1316 #define G_FW_RI_RES_WR_FETCHRO(x) \ 1317 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1318 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1319 1320 #define S_FW_RI_RES_WR_HOSTFCMODE 20 1321 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1322 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1323 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1324 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1325 1326 #define S_FW_RI_RES_WR_CPRIO 19 1327 #define M_FW_RI_RES_WR_CPRIO 0x1 1328 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1329 #define G_FW_RI_RES_WR_CPRIO(x) \ 1330 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1331 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1332 1333 #define S_FW_RI_RES_WR_ONCHIP 18 1334 #define M_FW_RI_RES_WR_ONCHIP 0x1 1335 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1336 #define G_FW_RI_RES_WR_ONCHIP(x) \ 1337 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1338 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1339 1340 #define S_FW_RI_RES_WR_PCIECHN 16 1341 #define M_FW_RI_RES_WR_PCIECHN 0x3 1342 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1343 #define G_FW_RI_RES_WR_PCIECHN(x) \ 1344 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1345 1346 #define S_FW_RI_RES_WR_IQID 0 1347 #define M_FW_RI_RES_WR_IQID 0xffff 1348 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1349 #define G_FW_RI_RES_WR_IQID(x) \ 1350 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1351 1352 #define S_FW_RI_RES_WR_DCAEN 31 1353 #define M_FW_RI_RES_WR_DCAEN 0x1 1354 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1355 #define G_FW_RI_RES_WR_DCAEN(x) \ 1356 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1357 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1358 1359 #define S_FW_RI_RES_WR_DCACPU 26 1360 #define M_FW_RI_RES_WR_DCACPU 0x1f 1361 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1362 #define G_FW_RI_RES_WR_DCACPU(x) \ 1363 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1364 1365 #define S_FW_RI_RES_WR_FBMIN 23 1366 #define M_FW_RI_RES_WR_FBMIN 0x7 1367 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1368 #define G_FW_RI_RES_WR_FBMIN(x) \ 1369 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1370 1371 #define S_FW_RI_RES_WR_FBMAX 20 1372 #define M_FW_RI_RES_WR_FBMAX 0x7 1373 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1374 #define G_FW_RI_RES_WR_FBMAX(x) \ 1375 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1376 1377 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1378 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1379 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1380 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1381 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1382 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1383 1384 #define S_FW_RI_RES_WR_CIDXFTHRESH 16 1385 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1386 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1387 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1388 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1389 1390 #define S_FW_RI_RES_WR_EQSIZE 0 1391 #define M_FW_RI_RES_WR_EQSIZE 0xffff 1392 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1393 #define G_FW_RI_RES_WR_EQSIZE(x) \ 1394 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1395 1396 #define S_FW_RI_RES_WR_IQANDST 15 1397 #define M_FW_RI_RES_WR_IQANDST 0x1 1398 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1399 #define G_FW_RI_RES_WR_IQANDST(x) \ 1400 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1401 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1402 1403 #define S_FW_RI_RES_WR_IQANUS 14 1404 #define M_FW_RI_RES_WR_IQANUS 0x1 1405 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1406 #define G_FW_RI_RES_WR_IQANUS(x) \ 1407 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1408 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1409 1410 #define S_FW_RI_RES_WR_IQANUD 12 1411 #define M_FW_RI_RES_WR_IQANUD 0x3 1412 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1413 #define G_FW_RI_RES_WR_IQANUD(x) \ 1414 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1415 1416 #define S_FW_RI_RES_WR_IQANDSTINDEX 0 1417 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1418 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1419 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1420 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1421 1422 #define S_FW_RI_RES_WR_IQDROPRSS 15 1423 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 1424 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1425 #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1426 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1427 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1428 1429 #define S_FW_RI_RES_WR_IQGTSMODE 14 1430 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 1431 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1432 #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1433 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1434 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1435 1436 #define S_FW_RI_RES_WR_IQPCIECH 12 1437 #define M_FW_RI_RES_WR_IQPCIECH 0x3 1438 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1439 #define G_FW_RI_RES_WR_IQPCIECH(x) \ 1440 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1441 1442 #define S_FW_RI_RES_WR_IQDCAEN 11 1443 #define M_FW_RI_RES_WR_IQDCAEN 0x1 1444 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1445 #define G_FW_RI_RES_WR_IQDCAEN(x) \ 1446 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1447 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1448 1449 #define S_FW_RI_RES_WR_IQDCACPU 6 1450 #define M_FW_RI_RES_WR_IQDCACPU 0x1f 1451 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1452 #define G_FW_RI_RES_WR_IQDCACPU(x) \ 1453 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1454 1455 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1456 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1457 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1458 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1459 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1460 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1461 1462 #define S_FW_RI_RES_WR_IQO 3 1463 #define M_FW_RI_RES_WR_IQO 0x1 1464 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1465 #define G_FW_RI_RES_WR_IQO(x) \ 1466 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1467 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1468 1469 #define S_FW_RI_RES_WR_IQCPRIO 2 1470 #define M_FW_RI_RES_WR_IQCPRIO 0x1 1471 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1472 #define G_FW_RI_RES_WR_IQCPRIO(x) \ 1473 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1474 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1475 1476 #define S_FW_RI_RES_WR_IQESIZE 0 1477 #define M_FW_RI_RES_WR_IQESIZE 0x3 1478 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1479 #define G_FW_RI_RES_WR_IQESIZE(x) \ 1480 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1481 1482 #define S_FW_RI_RES_WR_IQNS 31 1483 #define M_FW_RI_RES_WR_IQNS 0x1 1484 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1485 #define G_FW_RI_RES_WR_IQNS(x) \ 1486 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1487 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1488 1489 #define S_FW_RI_RES_WR_IQRO 30 1490 #define M_FW_RI_RES_WR_IQRO 0x1 1491 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1492 #define G_FW_RI_RES_WR_IQRO(x) \ 1493 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1494 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1495 1496 struct fw_ri_rdma_write_wr { 1497 __u8 opcode; 1498 __u8 flags; 1499 __u16 wrid; 1500 __u8 r1[3]; 1501 __u8 len16; 1502 __be64 r2; 1503 __be32 plen; 1504 __be32 stag_sink; 1505 __be64 to_sink; 1506 }; 1507 1508 struct fw_ri_send_wr { 1509 __u8 opcode; 1510 __u8 flags; 1511 __u16 wrid; 1512 __u8 r1[3]; 1513 __u8 len16; 1514 __be32 sendop_pkd; 1515 __be32 stag_inv; 1516 __be32 plen; 1517 __be32 r3; 1518 __be64 r4; 1519 }; 1520 1521 #define S_FW_RI_SEND_WR_SENDOP 0 1522 #define M_FW_RI_SEND_WR_SENDOP 0xf 1523 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1524 #define G_FW_RI_SEND_WR_SENDOP(x) \ 1525 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1526 1527 struct fw_ri_rdma_read_wr { 1528 __u8 opcode; 1529 __u8 flags; 1530 __u16 wrid; 1531 __u8 r1[3]; 1532 __u8 len16; 1533 __be64 r2; 1534 __be32 stag_sink; 1535 __be32 to_sink_hi; 1536 __be32 to_sink_lo; 1537 __be32 plen; 1538 __be32 stag_src; 1539 __be32 to_src_hi; 1540 __be32 to_src_lo; 1541 __be32 r5; 1542 }; 1543 1544 struct fw_ri_recv_wr { 1545 __u8 opcode; 1546 __u8 r1; 1547 __u16 wrid; 1548 __u8 r2[3]; 1549 __u8 len16; 1550 }; 1551 1552 struct fw_ri_bind_mw_wr { 1553 __u8 opcode; 1554 __u8 flags; 1555 __u16 wrid; 1556 __u8 r1[3]; 1557 __u8 len16; 1558 __u8 qpbinde_to_dcacpu; 1559 __u8 pgsz_shift; 1560 __u8 addr_type; 1561 __u8 mem_perms; 1562 __be32 stag_mr; 1563 __be32 stag_mw; 1564 __be32 r3; 1565 __be64 len_mw; 1566 __be64 va_fbo; 1567 __be64 r4; 1568 }; 1569 1570 #define S_FW_RI_BIND_MW_WR_QPBINDE 6 1571 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1572 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1573 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1574 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1575 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1576 1577 #define S_FW_RI_BIND_MW_WR_NS 5 1578 #define M_FW_RI_BIND_MW_WR_NS 0x1 1579 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1580 #define G_FW_RI_BIND_MW_WR_NS(x) \ 1581 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1582 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1583 1584 #define S_FW_RI_BIND_MW_WR_DCACPU 0 1585 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1586 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1587 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1588 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1589 1590 struct fw_ri_fr_nsmr_wr { 1591 __u8 opcode; 1592 __u8 flags; 1593 __u16 wrid; 1594 __u8 r1[3]; 1595 __u8 len16; 1596 __u8 qpbinde_to_dcacpu; 1597 __u8 pgsz_shift; 1598 __u8 addr_type; 1599 __u8 mem_perms; 1600 __be32 stag; 1601 __be32 len_hi; 1602 __be32 len_lo; 1603 __be32 va_hi; 1604 __be32 va_lo_fbo; 1605 }; 1606 1607 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1608 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1609 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1610 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1611 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1612 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1613 1614 #define S_FW_RI_FR_NSMR_WR_NS 5 1615 #define M_FW_RI_FR_NSMR_WR_NS 0x1 1616 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1617 #define G_FW_RI_FR_NSMR_WR_NS(x) \ 1618 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1619 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1620 1621 #define S_FW_RI_FR_NSMR_WR_DCACPU 0 1622 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1623 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1624 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1625 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1626 1627 struct fw_ri_inv_lstag_wr { 1628 __u8 opcode; 1629 __u8 flags; 1630 __u16 wrid; 1631 __u8 r1[3]; 1632 __u8 len16; 1633 __be32 r2; 1634 __be32 stag_inv; 1635 }; 1636 1637 struct fw_ri_send_immediate_wr { 1638 __u8 opcode; 1639 __u8 flags; 1640 __u16 wrid; 1641 __u8 r1[3]; 1642 __u8 len16; 1643 __be32 sendimmop_pkd; 1644 __be32 r3; 1645 __be32 plen; 1646 __be32 r4; 1647 __be64 r5; 1648 }; 1649 1650 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 1651 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 1652 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1653 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1654 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1655 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 1656 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1657 1658 enum fw_ri_atomic_op { 1659 FW_RI_ATOMIC_OP_FETCHADD, 1660 FW_RI_ATOMIC_OP_SWAP, 1661 FW_RI_ATOMIC_OP_CMDSWAP, 1662 }; 1663 1664 struct fw_ri_atomic_wr { 1665 __u8 opcode; 1666 __u8 flags; 1667 __u16 wrid; 1668 __u8 r1[3]; 1669 __u8 len16; 1670 __be32 atomicop_pkd; 1671 __be64 r3; 1672 __be32 aopcode_pkd; 1673 __be32 reqid; 1674 __be32 stag; 1675 __be32 to_hi; 1676 __be32 to_lo; 1677 __be32 addswap_data_hi; 1678 __be32 addswap_data_lo; 1679 __be32 addswap_mask_hi; 1680 __be32 addswap_mask_lo; 1681 __be32 compare_data_hi; 1682 __be32 compare_data_lo; 1683 __be32 compare_mask_hi; 1684 __be32 compare_mask_lo; 1685 __be32 r5; 1686 }; 1687 1688 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 1689 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 1690 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 1691 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 1692 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 1693 1694 #define S_FW_RI_ATOMIC_WR_AOPCODE 0 1695 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 1696 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 1697 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 1698 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 1699 1700 enum fw_ri_type { 1701 FW_RI_TYPE_INIT, 1702 FW_RI_TYPE_FINI, 1703 FW_RI_TYPE_TERMINATE 1704 }; 1705 1706 enum fw_ri_init_p2ptype { 1707 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 1708 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 1709 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 1710 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 1711 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 1712 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 1713 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 1714 }; 1715 1716 struct fw_ri_wr { 1717 __be32 op_compl; 1718 __be32 flowid_len16; 1719 __u64 cookie; 1720 union fw_ri { 1721 struct fw_ri_init { 1722 __u8 type; 1723 __u8 mpareqbit_p2ptype; 1724 __u8 r4[2]; 1725 __u8 mpa_attrs; 1726 __u8 qp_caps; 1727 __be16 nrqe; 1728 __be32 pdid; 1729 __be32 qpid; 1730 __be32 sq_eqid; 1731 __be32 rq_eqid; 1732 __be32 scqid; 1733 __be32 rcqid; 1734 __be32 ord_max; 1735 __be32 ird_max; 1736 __be32 iss; 1737 __be32 irs; 1738 __be32 hwrqsize; 1739 __be32 hwrqaddr; 1740 __be64 r5; 1741 union fw_ri_init_p2p { 1742 struct fw_ri_rdma_write_wr write; 1743 struct fw_ri_rdma_read_wr read; 1744 struct fw_ri_send_wr send; 1745 } u; 1746 } init; 1747 struct fw_ri_fini { 1748 __u8 type; 1749 __u8 r3[7]; 1750 __be64 r4; 1751 } fini; 1752 struct fw_ri_terminate { 1753 __u8 type; 1754 __u8 r3[3]; 1755 __be32 immdlen; 1756 __u8 termmsg[40]; 1757 } terminate; 1758 } u; 1759 }; 1760 1761 #define S_FW_RI_WR_MPAREQBIT 7 1762 #define M_FW_RI_WR_MPAREQBIT 0x1 1763 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 1764 #define G_FW_RI_WR_MPAREQBIT(x) \ 1765 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 1766 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 1767 1768 #define S_FW_RI_WR_0BRRBIT 6 1769 #define M_FW_RI_WR_0BRRBIT 0x1 1770 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 1771 #define G_FW_RI_WR_0BRRBIT(x) \ 1772 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 1773 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 1774 1775 #define S_FW_RI_WR_P2PTYPE 0 1776 #define M_FW_RI_WR_P2PTYPE 0xf 1777 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 1778 #define G_FW_RI_WR_P2PTYPE(x) \ 1779 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 1780 1781 /* 1782 * ******************************************* 1783 * F O i S C S I W O R K R E Q U E S T s 1784 * ******************************************* 1785 */ 1786 1787 #define FW_FOISCSI_NAME_MAX_LEN 224 1788 #define FW_FOISCSI_ALIAS_MAX_LEN 224 1789 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 1790 #define FW_FOISCSI_INIT_NODE_MAX 8 1791 1792 enum fw_chnet_ifconf_wr_subop { 1793 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 1794 1795 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 1796 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 1797 1798 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 1799 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 1800 1801 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 1802 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 1803 1804 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 1805 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 1806 1807 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 1808 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 1809 1810 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 1811 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 1812 1813 FW_CHNET_IFCONF_WR_SUBOP_MAX, 1814 }; 1815 1816 struct fw_chnet_ifconf_wr { 1817 __be32 op_compl; 1818 __be32 flowid_len16; 1819 __be64 cookie; 1820 __be32 if_flowid; 1821 __u8 idx; 1822 __u8 subop; 1823 __u8 retval; 1824 __u8 r2; 1825 __be64 r3; 1826 struct fw_chnet_ifconf_params { 1827 __be32 r0; 1828 __be16 vlanid; 1829 __be16 mtu; 1830 union fw_chnet_ifconf_addr_type { 1831 struct fw_chnet_ifconf_ipv4 { 1832 __be32 addr; 1833 __be32 mask; 1834 __be32 router; 1835 __be32 r0; 1836 __be64 r1; 1837 } ipv4; 1838 struct fw_chnet_ifconf_ipv6 { 1839 __be64 linklocal_lo; 1840 __be64 linklocal_hi; 1841 __be64 router_hi; 1842 __be64 router_lo; 1843 __be64 aconf_hi; 1844 __be64 aconf_lo; 1845 __be64 linklocal_aconf_hi; 1846 __be64 linklocal_aconf_lo; 1847 __be64 router_aconf_hi; 1848 __be64 router_aconf_lo; 1849 __be64 r0; 1850 } ipv6; 1851 } in_attr; 1852 } param; 1853 }; 1854 1855 enum fw_foiscsi_node_type { 1856 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 1857 FW_FOISCSI_NODE_TYPE_TARGET, 1858 }; 1859 1860 enum fw_foiscsi_session_type { 1861 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 1862 FW_FOISCSI_SESSION_TYPE_NORMAL, 1863 }; 1864 1865 enum fw_foiscsi_auth_policy { 1866 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 1867 FW_FOISCSI_AUTH_POLICY_MUTUAL, 1868 }; 1869 1870 enum fw_foiscsi_auth_method { 1871 FW_FOISCSI_AUTH_METHOD_NONE = 0, 1872 FW_FOISCSI_AUTH_METHOD_CHAP, 1873 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 1874 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 1875 }; 1876 1877 enum fw_foiscsi_digest_type { 1878 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 1879 FW_FOISCSI_DIGEST_TYPE_CRC32, 1880 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 1881 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 1882 }; 1883 1884 enum fw_foiscsi_wr_subop { 1885 FW_FOISCSI_WR_SUBOP_ADD = 1, 1886 FW_FOISCSI_WR_SUBOP_DEL = 2, 1887 FW_FOISCSI_WR_SUBOP_MOD = 4, 1888 }; 1889 1890 enum fw_foiscsi_ctrl_state { 1891 FW_FOISCSI_CTRL_STATE_FREE = 0, 1892 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 1893 FW_FOISCSI_CTRL_STATE_FAILED, 1894 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 1895 FW_FOISCSI_CTRL_STATE_REDIRECT, 1896 }; 1897 1898 struct fw_rdev_wr { 1899 __be32 op_to_immdlen; 1900 __be32 alloc_to_len16; 1901 __be64 cookie; 1902 __u8 protocol; 1903 __u8 event_cause; 1904 __u8 cur_state; 1905 __u8 prev_state; 1906 __be32 flags_to_assoc_flowid; 1907 union rdev_entry { 1908 struct fcoe_rdev_entry { 1909 __be32 flowid; 1910 __u8 protocol; 1911 __u8 event_cause; 1912 __u8 flags; 1913 __u8 rjt_reason; 1914 __u8 cur_login_st; 1915 __u8 prev_login_st; 1916 __be16 rcv_fr_sz; 1917 __u8 rd_xfer_rdy_to_rport_type; 1918 __u8 vft_to_qos; 1919 __u8 org_proc_assoc_to_acc_rsp_code; 1920 __u8 enh_disc_to_tgt; 1921 __u8 wwnn[8]; 1922 __u8 wwpn[8]; 1923 __be16 iqid; 1924 __u8 fc_oui[3]; 1925 __u8 r_id[3]; 1926 } fcoe_rdev; 1927 struct iscsi_rdev_entry { 1928 __be32 flowid; 1929 __u8 protocol; 1930 __u8 event_cause; 1931 __u8 flags; 1932 __u8 r3; 1933 __be16 iscsi_opts; 1934 __be16 tcp_opts; 1935 __be16 ip_opts; 1936 __be16 max_rcv_len; 1937 __be16 max_snd_len; 1938 __be16 first_brst_len; 1939 __be16 max_brst_len; 1940 __be16 r4; 1941 __be16 def_time2wait; 1942 __be16 def_time2ret; 1943 __be16 nop_out_intrvl; 1944 __be16 non_scsi_to; 1945 __be16 isid; 1946 __be16 tsid; 1947 __be16 port; 1948 __be16 tpgt; 1949 __u8 r5[6]; 1950 __be16 iqid; 1951 } iscsi_rdev; 1952 } u; 1953 }; 1954 1955 #define S_FW_RDEV_WR_IMMDLEN 0 1956 #define M_FW_RDEV_WR_IMMDLEN 0xff 1957 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 1958 #define G_FW_RDEV_WR_IMMDLEN(x) \ 1959 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 1960 1961 #define S_FW_RDEV_WR_ALLOC 31 1962 #define M_FW_RDEV_WR_ALLOC 0x1 1963 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 1964 #define G_FW_RDEV_WR_ALLOC(x) \ 1965 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 1966 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 1967 1968 #define S_FW_RDEV_WR_FREE 30 1969 #define M_FW_RDEV_WR_FREE 0x1 1970 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 1971 #define G_FW_RDEV_WR_FREE(x) \ 1972 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 1973 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 1974 1975 #define S_FW_RDEV_WR_MODIFY 29 1976 #define M_FW_RDEV_WR_MODIFY 0x1 1977 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 1978 #define G_FW_RDEV_WR_MODIFY(x) \ 1979 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 1980 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 1981 1982 #define S_FW_RDEV_WR_FLOWID 8 1983 #define M_FW_RDEV_WR_FLOWID 0xfffff 1984 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 1985 #define G_FW_RDEV_WR_FLOWID(x) \ 1986 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 1987 1988 #define S_FW_RDEV_WR_LEN16 0 1989 #define M_FW_RDEV_WR_LEN16 0xff 1990 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 1991 #define G_FW_RDEV_WR_LEN16(x) \ 1992 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 1993 1994 #define S_FW_RDEV_WR_FLAGS 24 1995 #define M_FW_RDEV_WR_FLAGS 0xff 1996 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 1997 #define G_FW_RDEV_WR_FLAGS(x) \ 1998 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 1999 2000 #define S_FW_RDEV_WR_GET_NEXT 20 2001 #define M_FW_RDEV_WR_GET_NEXT 0xf 2002 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 2003 #define G_FW_RDEV_WR_GET_NEXT(x) \ 2004 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 2005 2006 #define S_FW_RDEV_WR_ASSOC_FLOWID 0 2007 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 2008 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 2009 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 2010 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 2011 2012 #define S_FW_RDEV_WR_RJT 7 2013 #define M_FW_RDEV_WR_RJT 0x1 2014 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 2015 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 2016 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 2017 2018 #define S_FW_RDEV_WR_REASON 0 2019 #define M_FW_RDEV_WR_REASON 0x7f 2020 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 2021 #define G_FW_RDEV_WR_REASON(x) \ 2022 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 2023 2024 #define S_FW_RDEV_WR_RD_XFER_RDY 7 2025 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 2026 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 2027 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 2028 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 2029 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 2030 2031 #define S_FW_RDEV_WR_WR_XFER_RDY 6 2032 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 2033 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 2034 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 2035 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 2036 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 2037 2038 #define S_FW_RDEV_WR_FC_SP 5 2039 #define M_FW_RDEV_WR_FC_SP 0x1 2040 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 2041 #define G_FW_RDEV_WR_FC_SP(x) \ 2042 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 2043 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 2044 2045 #define S_FW_RDEV_WR_RPORT_TYPE 0 2046 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2047 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2048 #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2049 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2050 2051 #define S_FW_RDEV_WR_VFT 7 2052 #define M_FW_RDEV_WR_VFT 0x1 2053 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2054 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2055 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2056 2057 #define S_FW_RDEV_WR_NPIV 6 2058 #define M_FW_RDEV_WR_NPIV 0x1 2059 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2060 #define G_FW_RDEV_WR_NPIV(x) \ 2061 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2062 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2063 2064 #define S_FW_RDEV_WR_CLASS 4 2065 #define M_FW_RDEV_WR_CLASS 0x3 2066 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2067 #define G_FW_RDEV_WR_CLASS(x) \ 2068 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2069 2070 #define S_FW_RDEV_WR_SEQ_DEL 3 2071 #define M_FW_RDEV_WR_SEQ_DEL 0x1 2072 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2073 #define G_FW_RDEV_WR_SEQ_DEL(x) \ 2074 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2075 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2076 2077 #define S_FW_RDEV_WR_PRIO_PREEMP 2 2078 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2079 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2080 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2081 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2082 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2083 2084 #define S_FW_RDEV_WR_PREF 1 2085 #define M_FW_RDEV_WR_PREF 0x1 2086 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2087 #define G_FW_RDEV_WR_PREF(x) \ 2088 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2089 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2090 2091 #define S_FW_RDEV_WR_QOS 0 2092 #define M_FW_RDEV_WR_QOS 0x1 2093 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2094 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2095 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2096 2097 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2098 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2099 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2100 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2101 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2102 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2103 2104 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2105 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2106 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2107 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2108 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2109 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2110 2111 #define S_FW_RDEV_WR_IMAGE_PAIR 5 2112 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2113 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2114 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2115 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2116 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2117 2118 #define S_FW_RDEV_WR_ACC_RSP_CODE 0 2119 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2120 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2121 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2122 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2123 2124 #define S_FW_RDEV_WR_ENH_DISC 7 2125 #define M_FW_RDEV_WR_ENH_DISC 0x1 2126 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2127 #define G_FW_RDEV_WR_ENH_DISC(x) \ 2128 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2129 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2130 2131 #define S_FW_RDEV_WR_REC 6 2132 #define M_FW_RDEV_WR_REC 0x1 2133 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2134 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2135 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2136 2137 #define S_FW_RDEV_WR_TASK_RETRY_ID 5 2138 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2139 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2140 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2141 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2142 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2143 2144 #define S_FW_RDEV_WR_RETRY 4 2145 #define M_FW_RDEV_WR_RETRY 0x1 2146 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2147 #define G_FW_RDEV_WR_RETRY(x) \ 2148 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2149 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2150 2151 #define S_FW_RDEV_WR_CONF_CMPL 3 2152 #define M_FW_RDEV_WR_CONF_CMPL 0x1 2153 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2154 #define G_FW_RDEV_WR_CONF_CMPL(x) \ 2155 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2156 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2157 2158 #define S_FW_RDEV_WR_DATA_OVLY 2 2159 #define M_FW_RDEV_WR_DATA_OVLY 0x1 2160 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2161 #define G_FW_RDEV_WR_DATA_OVLY(x) \ 2162 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2163 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2164 2165 #define S_FW_RDEV_WR_INI 1 2166 #define M_FW_RDEV_WR_INI 0x1 2167 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2168 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2169 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2170 2171 #define S_FW_RDEV_WR_TGT 0 2172 #define M_FW_RDEV_WR_TGT 0x1 2173 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2174 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2175 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2176 2177 struct fw_foiscsi_node_wr { 2178 __be32 op_to_immdlen; 2179 __be32 flowid_len16; 2180 __u64 cookie; 2181 __u8 subop; 2182 __u8 status; 2183 __u8 alias_len; 2184 __u8 iqn_len; 2185 __be32 node_flowid; 2186 __be16 nodeid; 2187 __be16 login_retry; 2188 __be16 retry_timeout; 2189 __be16 r3; 2190 __u8 iqn[224]; 2191 __u8 alias[224]; 2192 }; 2193 2194 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2195 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2196 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2197 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2198 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2199 2200 struct fw_foiscsi_ctrl_wr { 2201 __be32 op_compl; 2202 __be32 flowid_len16; 2203 __u64 cookie; 2204 __u8 subop; 2205 __u8 status; 2206 __u8 ctrl_state; 2207 __u8 io_state; 2208 __be32 node_id; 2209 __be32 ctrl_id; 2210 __be32 io_id; 2211 struct fw_foiscsi_sess_attr { 2212 __be32 sess_type_to_erl; 2213 __be16 max_conn; 2214 __be16 max_r2t; 2215 __be16 time2wait; 2216 __be16 time2retain; 2217 __be32 max_burst; 2218 __be32 first_burst; 2219 __be32 r1; 2220 } sess_attr; 2221 struct fw_foiscsi_conn_attr { 2222 __be32 hdigest_to_ddp_pgsz; 2223 __be32 max_rcv_dsl; 2224 __be32 ping_tmo; 2225 __be16 dst_port; 2226 __be16 src_port; 2227 union fw_foiscsi_conn_attr_addr { 2228 struct fw_foiscsi_conn_attr_ipv6 { 2229 __be64 dst_addr[2]; 2230 __be64 src_addr[2]; 2231 } ipv6_addr; 2232 struct fw_foiscsi_conn_attr_ipv4 { 2233 __be32 dst_addr; 2234 __be32 src_addr; 2235 } ipv4_addr; 2236 } u; 2237 } conn_attr; 2238 __u8 tgt_name_len; 2239 __u8 r3[7]; 2240 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 2241 }; 2242 2243 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2244 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2245 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2246 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2247 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2248 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & \ 2249 M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2250 2251 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2252 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2253 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2254 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2255 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2256 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2257 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2258 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2259 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2260 2261 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2262 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2263 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2264 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2265 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2266 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2267 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2268 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2269 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2270 2271 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2272 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2273 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2274 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2275 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2276 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2277 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2278 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2279 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2280 2281 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2282 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2283 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2284 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2285 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2286 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2287 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2288 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2289 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2290 2291 #define S_FW_FOISCSI_CTRL_WR_ERL 24 2292 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2293 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2294 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2295 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2296 2297 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2298 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2299 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2300 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2301 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2302 2303 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2304 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2305 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2306 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2307 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2308 2309 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2310 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2311 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2312 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2313 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2314 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2315 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2316 2317 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2318 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2319 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2320 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2321 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2322 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2323 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2324 2325 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2326 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2327 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2328 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2329 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2330 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2331 2332 struct fw_foiscsi_chap_wr { 2333 __be32 op_compl; 2334 __be32 flowid_len16; 2335 __u64 cookie; 2336 __u8 status; 2337 __u8 id_len; 2338 __u8 sec_len; 2339 __u8 node_type; 2340 __be16 node_id; 2341 __u8 r3[2]; 2342 __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN]; 2343 __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN]; 2344 }; 2345 2346 /* 2347 * ***************************************** 2348 * F O F C O E W O R K R E Q U E S T s 2349 * ***************************************** 2350 */ 2351 2352 struct fw_fcoe_els_ct_wr { 2353 __be32 op_immdlen; 2354 __be32 flowid_len16; 2355 __be64 cookie; 2356 __be16 iqid; 2357 __u8 tmo_val; 2358 __u8 els_ct_type; 2359 __u8 ctl_pri; 2360 __u8 cp_en_class; 2361 __be16 xfer_cnt; 2362 __u8 fl_to_sp; 2363 __u8 l_id[3]; 2364 __u8 r5; 2365 __u8 r_id[3]; 2366 __be64 rsp_dmaaddr; 2367 __be32 rsp_dmalen; 2368 __be32 r6; 2369 }; 2370 2371 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 2372 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 2373 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 2374 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 2375 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 2376 2377 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 2378 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 2379 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 2380 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 2381 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 2382 2383 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 2384 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 2385 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 2386 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 2387 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 2388 2389 #define S_FW_FCOE_ELS_CT_WR_LEN16 0 2390 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 2391 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 2392 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 2393 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 2394 2395 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 2396 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 2397 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 2398 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 2399 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 2400 2401 #define S_FW_FCOE_ELS_CT_WR_CLASS 4 2402 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 2403 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 2404 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 2405 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 2406 2407 #define S_FW_FCOE_ELS_CT_WR_FL 2 2408 #define M_FW_FCOE_ELS_CT_WR_FL 0x1 2409 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 2410 #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 2411 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 2412 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 2413 2414 #define S_FW_FCOE_ELS_CT_WR_NPIV 1 2415 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 2416 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 2417 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 2418 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 2419 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 2420 2421 #define S_FW_FCOE_ELS_CT_WR_SP 0 2422 #define M_FW_FCOE_ELS_CT_WR_SP 0x1 2423 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 2424 #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 2425 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 2426 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 2427 2428 /* 2429 * **************************************** 2430 * S C S I W O R K R E Q U E S T s 2431 * (FOiSCSI and FCOE unified data path) 2432 * **************************************** 2433 */ 2434 2435 struct fw_scsi_write_wr { 2436 __be32 op_immdlen; 2437 __be32 flowid_len16; 2438 __be64 cookie; 2439 __be16 iqid; 2440 __u8 tmo_val; 2441 __u8 use_xfer_cnt; 2442 union fw_scsi_write_priv { 2443 struct fcoe_write_priv { 2444 __u8 ctl_pri; 2445 __u8 cp_en_class; 2446 __u8 r3_lo[2]; 2447 } fcoe; 2448 struct iscsi_write_priv { 2449 __u8 r3[4]; 2450 } iscsi; 2451 } u; 2452 __be32 xfer_cnt; 2453 __be32 ini_xfer_cnt; 2454 __be64 rsp_dmaaddr; 2455 __be32 rsp_dmalen; 2456 __be32 r4; 2457 }; 2458 2459 #define S_FW_SCSI_WRITE_WR_OPCODE 24 2460 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 2461 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 2462 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 2463 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 2464 2465 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 2466 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 2467 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 2468 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 2469 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 2470 2471 #define S_FW_SCSI_WRITE_WR_FLOWID 8 2472 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 2473 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 2474 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 2475 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 2476 2477 #define S_FW_SCSI_WRITE_WR_LEN16 0 2478 #define M_FW_SCSI_WRITE_WR_LEN16 0xff 2479 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 2480 #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 2481 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 2482 2483 #define S_FW_SCSI_WRITE_WR_CP_EN 6 2484 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 2485 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 2486 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 2487 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 2488 2489 #define S_FW_SCSI_WRITE_WR_CLASS 4 2490 #define M_FW_SCSI_WRITE_WR_CLASS 0x3 2491 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 2492 #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 2493 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 2494 2495 struct fw_scsi_read_wr { 2496 __be32 op_immdlen; 2497 __be32 flowid_len16; 2498 __be64 cookie; 2499 __be16 iqid; 2500 __u8 tmo_val; 2501 __u8 use_xfer_cnt; 2502 union fw_scsi_read_priv { 2503 struct fcoe_read_priv { 2504 __u8 ctl_pri; 2505 __u8 cp_en_class; 2506 __u8 r3_lo[2]; 2507 } fcoe; 2508 struct iscsi_read_priv { 2509 __u8 r3[4]; 2510 } iscsi; 2511 } u; 2512 __be32 xfer_cnt; 2513 __be32 ini_xfer_cnt; 2514 __be64 rsp_dmaaddr; 2515 __be32 rsp_dmalen; 2516 __be32 r4; 2517 }; 2518 2519 #define S_FW_SCSI_READ_WR_OPCODE 24 2520 #define M_FW_SCSI_READ_WR_OPCODE 0xff 2521 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 2522 #define G_FW_SCSI_READ_WR_OPCODE(x) \ 2523 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 2524 2525 #define S_FW_SCSI_READ_WR_IMMDLEN 0 2526 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 2527 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 2528 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 2529 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 2530 2531 #define S_FW_SCSI_READ_WR_FLOWID 8 2532 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 2533 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 2534 #define G_FW_SCSI_READ_WR_FLOWID(x) \ 2535 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 2536 2537 #define S_FW_SCSI_READ_WR_LEN16 0 2538 #define M_FW_SCSI_READ_WR_LEN16 0xff 2539 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 2540 #define G_FW_SCSI_READ_WR_LEN16(x) \ 2541 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 2542 2543 #define S_FW_SCSI_READ_WR_CP_EN 6 2544 #define M_FW_SCSI_READ_WR_CP_EN 0x3 2545 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 2546 #define G_FW_SCSI_READ_WR_CP_EN(x) \ 2547 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 2548 2549 #define S_FW_SCSI_READ_WR_CLASS 4 2550 #define M_FW_SCSI_READ_WR_CLASS 0x3 2551 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 2552 #define G_FW_SCSI_READ_WR_CLASS(x) \ 2553 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 2554 2555 struct fw_scsi_cmd_wr { 2556 __be32 op_immdlen; 2557 __be32 flowid_len16; 2558 __be64 cookie; 2559 __be16 iqid; 2560 __u8 tmo_val; 2561 __u8 r3; 2562 union fw_scsi_cmd_priv { 2563 struct fcoe_cmd_priv { 2564 __u8 ctl_pri; 2565 __u8 cp_en_class; 2566 __u8 r4_lo[2]; 2567 } fcoe; 2568 struct iscsi_cmd_priv { 2569 __u8 r4[4]; 2570 } iscsi; 2571 } u; 2572 __u8 r5[8]; 2573 __be64 rsp_dmaaddr; 2574 __be32 rsp_dmalen; 2575 __be32 r6; 2576 }; 2577 2578 #define S_FW_SCSI_CMD_WR_OPCODE 24 2579 #define M_FW_SCSI_CMD_WR_OPCODE 0xff 2580 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 2581 #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 2582 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 2583 2584 #define S_FW_SCSI_CMD_WR_IMMDLEN 0 2585 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 2586 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 2587 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 2588 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 2589 2590 #define S_FW_SCSI_CMD_WR_FLOWID 8 2591 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 2592 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 2593 #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 2594 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 2595 2596 #define S_FW_SCSI_CMD_WR_LEN16 0 2597 #define M_FW_SCSI_CMD_WR_LEN16 0xff 2598 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 2599 #define G_FW_SCSI_CMD_WR_LEN16(x) \ 2600 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 2601 2602 #define S_FW_SCSI_CMD_WR_CP_EN 6 2603 #define M_FW_SCSI_CMD_WR_CP_EN 0x3 2604 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 2605 #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 2606 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 2607 2608 #define S_FW_SCSI_CMD_WR_CLASS 4 2609 #define M_FW_SCSI_CMD_WR_CLASS 0x3 2610 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 2611 #define G_FW_SCSI_CMD_WR_CLASS(x) \ 2612 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 2613 2614 struct fw_scsi_abrt_cls_wr { 2615 __be32 op_immdlen; 2616 __be32 flowid_len16; 2617 __be64 cookie; 2618 __be16 iqid; 2619 __u8 tmo_val; 2620 __u8 sub_opcode_to_chk_all_io; 2621 __u8 r3[4]; 2622 __be64 t_cookie; 2623 }; 2624 2625 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 2626 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 2627 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 2628 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 2629 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 2630 2631 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 2632 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 2633 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2634 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2635 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2636 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2637 2638 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 2639 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 2640 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 2641 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 2642 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 2643 2644 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 2645 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 2646 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 2647 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 2648 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 2649 2650 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 2651 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 2652 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2653 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2654 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2655 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 2656 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2657 2658 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 2659 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 2660 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 2661 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 2662 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 2663 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 2664 2665 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 2666 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 2667 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2668 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2669 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2670 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 2671 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2672 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 2673 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 2674 2675 struct fw_scsi_tgt_acc_wr { 2676 __be32 op_immdlen; 2677 __be32 flowid_len16; 2678 __be64 cookie; 2679 __be16 iqid; 2680 __u8 r3; 2681 __u8 use_burst_len; 2682 union fw_scsi_tgt_acc_priv { 2683 struct fcoe_tgt_acc_priv { 2684 __u8 ctl_pri; 2685 __u8 cp_en_class; 2686 __u8 r4_lo[2]; 2687 } fcoe; 2688 struct iscsi_tgt_acc_priv { 2689 __u8 r4[4]; 2690 } iscsi; 2691 } u; 2692 __be32 burst_len; 2693 __be32 rel_off; 2694 __be64 r5; 2695 __be32 r6; 2696 __be32 tot_xfer_len; 2697 }; 2698 2699 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 2700 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 2701 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 2702 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 2703 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 2704 2705 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 2706 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 2707 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2708 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 2709 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2710 2711 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 2712 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 2713 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 2714 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 2715 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 2716 2717 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 2718 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 2719 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 2720 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 2721 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 2722 2723 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 2724 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 2725 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 2726 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 2727 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 2728 2729 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 2730 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 2731 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 2732 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 2733 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 2734 2735 struct fw_scsi_tgt_xmit_wr { 2736 __be32 op_immdlen; 2737 __be32 flowid_len16; 2738 __be64 cookie; 2739 __be16 iqid; 2740 __u8 auto_rsp; 2741 __u8 use_xfer_cnt; 2742 union fw_scsi_tgt_xmit_priv { 2743 struct fcoe_tgt_xmit_priv { 2744 __u8 ctl_pri; 2745 __u8 cp_en_class; 2746 __u8 r3_lo[2]; 2747 } fcoe; 2748 struct iscsi_tgt_xmit_priv { 2749 __u8 r3[4]; 2750 } iscsi; 2751 } u; 2752 __be32 xfer_cnt; 2753 __be32 r4; 2754 __be64 r5; 2755 __be32 r6; 2756 __be32 tot_xfer_len; 2757 }; 2758 2759 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 2760 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 2761 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 2762 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 2763 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 2764 2765 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 2766 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 2767 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2768 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2769 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2770 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2771 2772 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 2773 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 2774 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 2775 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 2776 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 2777 2778 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 2779 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 2780 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 2781 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 2782 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 2783 2784 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 2785 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 2786 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 2787 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 2788 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 2789 2790 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 2791 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 2792 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 2793 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 2794 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 2795 2796 struct fw_scsi_tgt_rsp_wr { 2797 __be32 op_immdlen; 2798 __be32 flowid_len16; 2799 __be64 cookie; 2800 __be16 iqid; 2801 __u8 r3[2]; 2802 union fw_scsi_tgt_rsp_priv { 2803 struct fcoe_tgt_rsp_priv { 2804 __u8 ctl_pri; 2805 __u8 cp_en_class; 2806 __u8 r4_lo[2]; 2807 } fcoe; 2808 struct iscsi_tgt_rsp_priv { 2809 __u8 r4[4]; 2810 } iscsi; 2811 } u; 2812 __u8 r5[8]; 2813 }; 2814 2815 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 2816 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 2817 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 2818 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 2819 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 2820 2821 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 2822 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 2823 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2824 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 2825 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2826 2827 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 2828 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 2829 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 2830 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 2831 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 2832 2833 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 2834 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 2835 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 2836 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 2837 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 2838 2839 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 2840 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 2841 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 2842 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 2843 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 2844 2845 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 2846 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 2847 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 2848 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 2849 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 2850 2851 struct fw_pofcoe_tcb_wr { 2852 __be32 op_compl; 2853 __be32 equiq_to_len16; 2854 __be64 cookie; 2855 __be32 tid_to_port; 2856 __be16 x_id; 2857 __be16 vlan_id; 2858 __be32 s_id; 2859 __be32 d_id; 2860 __be32 tag; 2861 __be32 xfer_len; 2862 __be32 r4; 2863 __be16 r5; 2864 __be16 iqid; 2865 }; 2866 2867 #define S_FW_POFCOE_TCB_WR_TID 12 2868 #define M_FW_POFCOE_TCB_WR_TID 0xfffff 2869 #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 2870 #define G_FW_POFCOE_TCB_WR_TID(x) \ 2871 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 2872 2873 #define S_FW_POFCOE_TCB_WR_ALLO 4 2874 #define M_FW_POFCOE_TCB_WR_ALLOC 0x1 2875 #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 2876 #define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 2877 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 2878 #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 2879 2880 #define S_FW_POFCOE_TCB_WR_FREE 3 2881 #define M_FW_POFCOE_TCB_WR_FREE 0x1 2882 #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 2883 #define G_FW_POFCOE_TCB_WR_FREE(x) \ 2884 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 2885 #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 2886 2887 #define S_FW_POFCOE_TCB_WR_PORT 0 2888 #define M_FW_POFCOE_TCB_WR_PORT 0x7 2889 #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 2890 #define G_FW_POFCOE_TCB_WR_PORT(x) \ 2891 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 2892 2893 struct fw_pofcoe_ulptx_wr { 2894 __be32 op_pkd; 2895 __be32 equiq_to_len16; 2896 __u64 cookie; 2897 }; 2898 2899 2900 /* 2901 * ******************* 2902 * C O M M A N D s 2903 * ******************* 2904 */ 2905 2906 /* 2907 * The maximum length of time, in miliseconds, that we expect any firmware 2908 * command to take to execute and return a reply to the host. The RESET 2909 * and INITIALIZE commands can take a fair amount of time to execute but 2910 * most execute in far less time than this maximum. This constant is used 2911 * by host software to determine how long to wait for a firmware command 2912 * reply before declaring the firmware as dead/unreachable ... 2913 */ 2914 #define FW_CMD_MAX_TIMEOUT 10000 2915 2916 /* 2917 * If a host driver does a HELLO and discovers that there's already a MASTER 2918 * selected, we may have to wait for that MASTER to finish issuing RESET, 2919 * configuration and INITIALIZE commands. Also, there's a possibility that 2920 * our own HELLO may get lost if it happens right as the MASTER is issuign a 2921 * RESET command, so we need to be willing to make a few retries of our HELLO. 2922 */ 2923 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 2924 #define FW_CMD_HELLO_RETRIES 3 2925 2926 enum fw_cmd_opcodes { 2927 FW_LDST_CMD = 0x01, 2928 FW_RESET_CMD = 0x03, 2929 FW_HELLO_CMD = 0x04, 2930 FW_BYE_CMD = 0x05, 2931 FW_INITIALIZE_CMD = 0x06, 2932 FW_CAPS_CONFIG_CMD = 0x07, 2933 FW_PARAMS_CMD = 0x08, 2934 FW_PFVF_CMD = 0x09, 2935 FW_IQ_CMD = 0x10, 2936 FW_EQ_MNGT_CMD = 0x11, 2937 FW_EQ_ETH_CMD = 0x12, 2938 FW_EQ_CTRL_CMD = 0x13, 2939 FW_EQ_OFLD_CMD = 0x21, 2940 FW_VI_CMD = 0x14, 2941 FW_VI_MAC_CMD = 0x15, 2942 FW_VI_RXMODE_CMD = 0x16, 2943 FW_VI_ENABLE_CMD = 0x17, 2944 FW_VI_STATS_CMD = 0x1a, 2945 FW_ACL_MAC_CMD = 0x18, 2946 FW_ACL_VLAN_CMD = 0x19, 2947 FW_PORT_CMD = 0x1b, 2948 FW_PORT_STATS_CMD = 0x1c, 2949 FW_PORT_LB_STATS_CMD = 0x1d, 2950 FW_PORT_TRACE_CMD = 0x1e, 2951 FW_PORT_TRACE_MMAP_CMD = 0x1f, 2952 FW_RSS_IND_TBL_CMD = 0x20, 2953 FW_RSS_GLB_CONFIG_CMD = 0x22, 2954 FW_RSS_VI_CONFIG_CMD = 0x23, 2955 FW_SCHED_CMD = 0x24, 2956 FW_DEVLOG_CMD = 0x25, 2957 FW_WATCHDOG_CMD = 0x27, 2958 FW_CLIP_CMD = 0x28, 2959 FW_CHNET_IFACE_CMD = 0x26, 2960 FW_FCOE_RES_INFO_CMD = 0x31, 2961 FW_FCOE_LINK_CMD = 0x32, 2962 FW_FCOE_VNP_CMD = 0x33, 2963 FW_FCOE_SPARAMS_CMD = 0x35, 2964 FW_FCOE_STATS_CMD = 0x37, 2965 FW_FCOE_FCF_CMD = 0x38, 2966 FW_LASTC2E_CMD = 0x40, 2967 FW_ERROR_CMD = 0x80, 2968 FW_DEBUG_CMD = 0x81, 2969 }; 2970 2971 enum fw_cmd_cap { 2972 FW_CMD_CAP_PF = 0x01, 2973 FW_CMD_CAP_DMAQ = 0x02, 2974 FW_CMD_CAP_PORT = 0x04, 2975 FW_CMD_CAP_PORTPROMISC = 0x08, 2976 FW_CMD_CAP_PORTSTATS = 0x10, 2977 FW_CMD_CAP_VF = 0x80, 2978 }; 2979 2980 /* 2981 * Generic command header flit0 2982 */ 2983 struct fw_cmd_hdr { 2984 __be32 hi; 2985 __be32 lo; 2986 }; 2987 2988 #define S_FW_CMD_OP 24 2989 #define M_FW_CMD_OP 0xff 2990 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 2991 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 2992 2993 #define S_FW_CMD_REQUEST 23 2994 #define M_FW_CMD_REQUEST 0x1 2995 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 2996 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 2997 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 2998 2999 #define S_FW_CMD_READ 22 3000 #define M_FW_CMD_READ 0x1 3001 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 3002 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 3003 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 3004 3005 #define S_FW_CMD_WRITE 21 3006 #define M_FW_CMD_WRITE 0x1 3007 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 3008 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 3009 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 3010 3011 #define S_FW_CMD_EXEC 20 3012 #define M_FW_CMD_EXEC 0x1 3013 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 3014 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 3015 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 3016 3017 #define S_FW_CMD_RAMASK 20 3018 #define M_FW_CMD_RAMASK 0xf 3019 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 3020 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 3021 3022 #define S_FW_CMD_RETVAL 8 3023 #define M_FW_CMD_RETVAL 0xff 3024 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 3025 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 3026 3027 #define S_FW_CMD_LEN16 0 3028 #define M_FW_CMD_LEN16 0xff 3029 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 3030 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 3031 3032 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof (fw_struct) / 16) 3033 3034 /* 3035 * address spaces 3036 */ 3037 enum fw_ldst_addrspc { 3038 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 3039 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 3040 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 3041 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 3042 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 3043 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 3044 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 3045 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 3046 FW_LDST_ADDRSPC_MDIO = 0x0018, 3047 FW_LDST_ADDRSPC_MPS = 0x0020, 3048 FW_LDST_ADDRSPC_FUNC = 0x0028, 3049 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 3050 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 3051 FW_LDST_ADDRSPC_LE = 0x0030, 3052 FW_LDST_ADDRSPC_I2C = 0x0038, 3053 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 3054 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 3055 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 3056 }; 3057 3058 /* 3059 * MDIO VSC8634 register access control field 3060 */ 3061 enum fw_ldst_mdio_vsc8634_aid { 3062 FW_LDST_MDIO_VS_STANDARD, 3063 FW_LDST_MDIO_VS_EXTENDED, 3064 FW_LDST_MDIO_VS_GPIO 3065 }; 3066 3067 enum fw_ldst_mps_fid { 3068 FW_LDST_MPS_ATRB, 3069 FW_LDST_MPS_RPLC 3070 }; 3071 3072 enum fw_ldst_func_access_ctl { 3073 FW_LDST_FUNC_ACC_CTL_VIID, 3074 FW_LDST_FUNC_ACC_CTL_FID 3075 }; 3076 3077 enum fw_ldst_func_mod_index { 3078 FW_LDST_FUNC_MPS 3079 }; 3080 3081 struct fw_ldst_cmd { 3082 __be32 op_to_addrspace; 3083 __be32 cycles_to_len16; 3084 union fw_ldst { 3085 struct fw_ldst_addrval { 3086 __be32 addr; 3087 __be32 val; 3088 } addrval; 3089 struct fw_ldst_idctxt { 3090 __be32 physid; 3091 __be32 msg_ctxtflush; 3092 __be32 ctxt_data7; 3093 __be32 ctxt_data6; 3094 __be32 ctxt_data5; 3095 __be32 ctxt_data4; 3096 __be32 ctxt_data3; 3097 __be32 ctxt_data2; 3098 __be32 ctxt_data1; 3099 __be32 ctxt_data0; 3100 } idctxt; 3101 struct fw_ldst_mdio { 3102 __be16 paddr_mmd; 3103 __be16 raddr; 3104 __be16 vctl; 3105 __be16 rval; 3106 } mdio; 3107 struct fw_ldst_mps { 3108 __be16 fid_ctl; 3109 __be16 rplcpf_pkd; 3110 __be32 rplc127_96; 3111 __be32 rplc95_64; 3112 __be32 rplc63_32; 3113 __be32 rplc31_0; 3114 __be32 atrb; 3115 __be16 vlan[16]; 3116 } mps; 3117 struct fw_ldst_func { 3118 __u8 access_ctl; 3119 __u8 mod_index; 3120 __be16 ctl_id; 3121 __be32 offset; 3122 __be64 data0; 3123 __be64 data1; 3124 } func; 3125 struct fw_ldst_pcie { 3126 __u8 ctrl_to_fn; 3127 __u8 bnum; 3128 __u8 r; 3129 __u8 ext_r; 3130 __u8 select_naccess; 3131 __u8 pcie_fn; 3132 __be16 nset_pkd; 3133 __be32 data[12]; 3134 } pcie; 3135 struct fw_ldst_i2c_deprecated { 3136 __u8 pid_pkd; 3137 __u8 base; 3138 __u8 boffset; 3139 __u8 data; 3140 __be32 r9; 3141 } i2c_deprecated; 3142 struct fw_ldst_i2c { 3143 __u8 pid; 3144 __u8 did; 3145 __u8 boffset; 3146 __u8 blen; 3147 __be32 r9; 3148 __u8 data[48]; 3149 } i2c; 3150 struct fw_ldst_le { 3151 __be32 index; 3152 __be32 r9; 3153 __u8 val[33]; 3154 __u8 r11[7]; 3155 } le; 3156 } u; 3157 }; 3158 3159 #define S_FW_LDST_CMD_ADDRSPACE 0 3160 #define M_FW_LDST_CMD_ADDRSPACE 0xff 3161 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 3162 #define G_FW_LDST_CMD_ADDRSPACE(x) \ 3163 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 3164 3165 #define S_FW_LDST_CMD_CYCLES 16 3166 #define M_FW_LDST_CMD_CYCLES 0xffff 3167 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 3168 #define G_FW_LDST_CMD_CYCLES(x) \ 3169 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 3170 3171 #define S_FW_LDST_CMD_MSG 31 3172 #define M_FW_LDST_CMD_MSG 0x1 3173 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 3174 #define G_FW_LDST_CMD_MSG(x) \ 3175 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 3176 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 3177 3178 #define S_FW_LDST_CMD_CTXTFLUSH 30 3179 #define M_FW_LDST_CMD_CTXTFLUSH 0x1 3180 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 3181 #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 3182 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 3183 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 3184 3185 #define S_FW_LDST_CMD_PADDR 8 3186 #define M_FW_LDST_CMD_PADDR 0x1f 3187 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 3188 #define G_FW_LDST_CMD_PADDR(x) \ 3189 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 3190 3191 #define S_FW_LDST_CMD_MMD 0 3192 #define M_FW_LDST_CMD_MMD 0x1f 3193 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 3194 #define G_FW_LDST_CMD_MMD(x) \ 3195 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 3196 3197 #define S_FW_LDST_CMD_FID 15 3198 #define M_FW_LDST_CMD_FID 0x1 3199 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 3200 #define G_FW_LDST_CMD_FID(x) \ 3201 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 3202 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 3203 3204 #define S_FW_LDST_CMD_CTL 0 3205 #define M_FW_LDST_CMD_CTL 0x7fff 3206 #define V_FW_LDST_CMD_CTL(x) ((x) << S_FW_LDST_CMD_CTL) 3207 #define G_FW_LDST_CMD_CTL(x) \ 3208 (((x) >> S_FW_LDST_CMD_CTL) & M_FW_LDST_CMD_CTL) 3209 3210 #define S_FW_LDST_CMD_RPLCPF 0 3211 #define M_FW_LDST_CMD_RPLCPF 0xff 3212 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 3213 #define G_FW_LDST_CMD_RPLCPF(x) \ 3214 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 3215 3216 #define S_FW_LDST_CMD_CTRL 7 3217 #define M_FW_LDST_CMD_CTRL 0x1 3218 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 3219 #define G_FW_LDST_CMD_CTRL(x) \ 3220 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 3221 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 3222 3223 #define S_FW_LDST_CMD_LC 4 3224 #define M_FW_LDST_CMD_LC 0x1 3225 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 3226 #define G_FW_LDST_CMD_LC(x) (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 3227 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 3228 3229 #define S_FW_LDST_CMD_AI 3 3230 #define M_FW_LDST_CMD_AI 0x1 3231 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 3232 #define G_FW_LDST_CMD_AI(x) (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 3233 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 3234 3235 #define S_FW_LDST_CMD_FN 0 3236 #define M_FW_LDST_CMD_FN 0x7 3237 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 3238 #define G_FW_LDST_CMD_FN(x) (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 3239 3240 #define S_FW_LDST_CMD_SELECT 4 3241 #define M_FW_LDST_CMD_SELECT 0xf 3242 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 3243 #define G_FW_LDST_CMD_SELECT(x) \ 3244 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 3245 3246 #define S_FW_LDST_CMD_NACCESS 0 3247 #define M_FW_LDST_CMD_NACCESS 0xf 3248 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 3249 #define G_FW_LDST_CMD_NACCESS(x) \ 3250 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 3251 3252 #define S_FW_LDST_CMD_NSET 14 3253 #define M_FW_LDST_CMD_NSET 0x3 3254 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 3255 #define G_FW_LDST_CMD_NSET(x) \ 3256 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 3257 3258 #define S_FW_LDST_CMD_PID 6 3259 #define M_FW_LDST_CMD_PID 0x3 3260 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 3261 #define G_FW_LDST_CMD_PID(x) \ 3262 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 3263 3264 struct fw_reset_cmd { 3265 __be32 op_to_write; 3266 __be32 retval_len16; 3267 __be32 val; 3268 __be32 halt_pkd; 3269 }; 3270 3271 #define S_FW_RESET_CMD_HALT 31 3272 #define M_FW_RESET_CMD_HALT 0x1 3273 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 3274 #define G_FW_RESET_CMD_HALT(x) \ 3275 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 3276 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 3277 3278 enum { 3279 FW_HELLO_CMD_STAGE_OS = 0, 3280 FW_HELLO_CMD_STAGE_PREOS0 = 1, 3281 FW_HELLO_CMD_STAGE_PREOS1 = 2, 3282 FW_HELLO_CMD_STAGE_POSTOS = 3, 3283 }; 3284 3285 struct fw_hello_cmd { 3286 __be32 op_to_write; 3287 __be32 retval_len16; 3288 __be32 err_to_clearinit; 3289 __be32 fwrev; 3290 }; 3291 3292 #define S_FW_HELLO_CMD_ERR 31 3293 #define M_FW_HELLO_CMD_ERR 0x1 3294 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 3295 #define G_FW_HELLO_CMD_ERR(x) \ 3296 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 3297 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 3298 3299 #define S_FW_HELLO_CMD_INIT 30 3300 #define M_FW_HELLO_CMD_INIT 0x1 3301 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 3302 #define G_FW_HELLO_CMD_INIT(x) \ 3303 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 3304 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 3305 3306 #define S_FW_HELLO_CMD_MASTERDIS 29 3307 #define M_FW_HELLO_CMD_MASTERDIS 0x1 3308 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 3309 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 3310 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 3311 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 3312 3313 #define S_FW_HELLO_CMD_MASTERFORCE 28 3314 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 3315 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 3316 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 3317 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 3318 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 3319 3320 #define S_FW_HELLO_CMD_MBMASTER 24 3321 #define M_FW_HELLO_CMD_MBMASTER 0xf 3322 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 3323 #define G_FW_HELLO_CMD_MBMASTER(x) \ 3324 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 3325 3326 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 3327 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 3328 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 3329 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 3330 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 3331 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 3332 3333 #define S_FW_HELLO_CMD_MBASYNCNOT 20 3334 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 3335 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 3336 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 3337 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 3338 3339 #define S_FW_HELLO_CMD_STAGE 17 3340 #define M_FW_HELLO_CMD_STAGE 0x7 3341 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 3342 #define G_FW_HELLO_CMD_STAGE(x) \ 3343 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 3344 3345 #define S_FW_HELLO_CMD_CLEARINIT 16 3346 #define M_FW_HELLO_CMD_CLEARINIT 0x1 3347 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 3348 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 3349 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 3350 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 3351 3352 struct fw_bye_cmd { 3353 __be32 op_to_write; 3354 __be32 retval_len16; 3355 __be64 r3; 3356 }; 3357 3358 struct fw_initialize_cmd { 3359 __be32 op_to_write; 3360 __be32 retval_len16; 3361 __be64 r3; 3362 }; 3363 3364 enum fw_caps_config_hm { 3365 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 3366 FW_CAPS_CONFIG_HM_PL = 0x00000002, 3367 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 3368 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 3369 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 3370 FW_CAPS_CONFIG_HM_TP = 0x00000020, 3371 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 3372 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 3373 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 3374 FW_CAPS_CONFIG_HM_MC = 0x00000200, 3375 FW_CAPS_CONFIG_HM_LE = 0x00000400, 3376 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 3377 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 3378 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 3379 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 3380 FW_CAPS_CONFIG_HM_MI = 0x00008000, 3381 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 3382 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 3383 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 3384 FW_CAPS_CONFIG_HM_MA = 0x00080000, 3385 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 3386 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 3387 FW_CAPS_CONFIG_HM_UART = 0x00400000, 3388 FW_CAPS_CONFIG_HM_SF = 0x00800000, 3389 }; 3390 3391 /* 3392 * The VF Register Map. 3393 * 3394 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 3395 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 3396 * the Slice to Module Map Table (see below) in the Physical Function Register 3397 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 3398 * and Offset registers in the PF Register Map. The MBDATA base address is 3399 * quite constrained as it determines the Mailbox Data addresses for both PFs 3400 * and VFs, and therefore must fit in both the VF and PF Register Maps without 3401 * overlapping other registers. 3402 */ 3403 #define FW_T4VF_SGE_BASE_ADDR 0x0000 3404 #define FW_T4VF_MPS_BASE_ADDR 0x0100 3405 #define FW_T4VF_PL_BASE_ADDR 0x0200 3406 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 3407 #define FW_T4VF_CIM_BASE_ADDR 0x0300 3408 3409 #define FW_T4VF_REGMAP_START 0x0000 3410 #define FW_T4VF_REGMAP_SIZE 0x0400 3411 3412 enum fw_caps_config_nbm { 3413 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 3414 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 3415 }; 3416 3417 enum fw_caps_config_link { 3418 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 3419 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 3420 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 3421 }; 3422 3423 enum fw_caps_config_switch { 3424 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 3425 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 3426 }; 3427 3428 enum fw_caps_config_nic { 3429 FW_CAPS_CONFIG_NIC = 0x00000001, 3430 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 3431 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 3432 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 3433 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 3434 }; 3435 3436 enum fw_caps_config_toe { 3437 FW_CAPS_CONFIG_TOE = 0x00000001, 3438 }; 3439 3440 enum fw_caps_config_rdma { 3441 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 3442 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 3443 }; 3444 3445 enum fw_caps_config_iscsi { 3446 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 3447 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 3448 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 3449 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 3450 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 3451 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 3452 3453 }; 3454 3455 enum fw_caps_config_fcoe { 3456 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 3457 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 3458 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 3459 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 3460 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 3461 }; 3462 3463 enum fw_memtype_cf { 3464 FW_MEMTYPE_CF_EDC0 = 0x0, 3465 FW_MEMTYPE_CF_EDC1 = 0x1, 3466 FW_MEMTYPE_CF_EXTMEM = 0x2, 3467 FW_MEMTYPE_CF_FLASH = 0x4, 3468 FW_MEMTYPE_CF_INTERNAL = 0x5, 3469 FW_MEMTYPE_CF_EXTMEM1 = 0x6, 3470 }; 3471 3472 struct fw_caps_config_cmd { 3473 __be32 op_to_write; 3474 __be32 cfvalid_to_len16; 3475 __be32 r2; 3476 __be32 hwmbitmap; 3477 __be16 nbmcaps; 3478 __be16 linkcaps; 3479 __be16 switchcaps; 3480 __be16 r3; 3481 __be16 niccaps; 3482 __be16 toecaps; 3483 __be16 rdmacaps; 3484 __be16 r4; 3485 __be16 iscsicaps; 3486 __be16 fcoecaps; 3487 __be32 cfcsum; 3488 __be32 finiver; 3489 __be32 finicsum; 3490 }; 3491 3492 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 3493 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 3494 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 3495 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 3496 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 3497 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 3498 3499 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 3500 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 3501 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 3502 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 3503 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 3504 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 3505 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 3506 3507 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 3508 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 3509 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 3510 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 3511 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 3512 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 3513 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 3514 3515 /* 3516 * params command mnemonics 3517 */ 3518 enum fw_params_mnem { 3519 FW_PARAMS_MNEM_DEV = 1, /* device params */ 3520 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 3521 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 3522 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 3523 FW_PARAMS_MNEM_LAST 3524 }; 3525 3526 /* 3527 * device parameters 3528 */ 3529 enum fw_params_param_dev { 3530 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 3531 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 3532 /* reads the number of TIDs allocated by the device's Lookup Engine */ 3533 FW_PARAMS_PARAM_DEV_NTID = 0x02, 3534 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 3535 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 3536 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 3537 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 3538 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 3539 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 3540 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 3541 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 3542 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 3543 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 3544 FW_PARAMS_PARAM_DEV_CF = 0x0D, 3545 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 3546 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 3547 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 3548 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 3549 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 3550 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 3551 */ 3552 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 3553 */ 3554 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 3555 FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 3556 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 3557 }; 3558 3559 /* 3560 * physical and virtual function parameters 3561 */ 3562 enum fw_params_param_pfvf { 3563 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 3564 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 3565 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 3566 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 3567 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 3568 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 3569 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 3570 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 3571 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 3572 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 3573 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 3574 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 3575 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 3576 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 3577 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 3578 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 3579 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 3580 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 3581 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 3582 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 3583 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 3584 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 3585 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 3586 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 3587 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 3588 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 3589 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 3590 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 3591 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 3592 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 3593 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 3594 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 3595 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 3596 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 3597 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 3598 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 3599 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 3600 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 3601 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 3602 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31 3603 }; 3604 3605 /* 3606 * dma queue parameters 3607 */ 3608 enum fw_params_param_dmaq { 3609 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 3610 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 3611 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 3612 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 3613 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 3614 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 3615 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 3616 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 3617 }; 3618 3619 /* 3620 * dev bypass parameters; actions and modes 3621 */ 3622 enum fw_params_param_dev_bypass { 3623 3624 /* actions */ 3625 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 3626 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 3627 3628 /* modes */ 3629 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 3630 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 3631 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 3632 }; 3633 3634 enum fw_params_phyfw_actions { 3635 FW_PARAMS_PARAM_PHYFW_DOWNLOAD = 0x00, 3636 FW_PARAMS_PARAM_PHYFW_VERSION = 0x01, 3637 }; 3638 3639 enum fw_params_param_dev_diag { 3640 FW_PARAM_DEV_DIAG_TMP = 0x00, 3641 FW_PARAM_DEV_DIAG_VDD = 0x01, 3642 }; 3643 3644 #define S_FW_PARAMS_MNEM 24 3645 #define M_FW_PARAMS_MNEM 0xff 3646 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 3647 #define G_FW_PARAMS_MNEM(x) \ 3648 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 3649 3650 #define S_FW_PARAMS_PARAM_X 16 3651 #define M_FW_PARAMS_PARAM_X 0xff 3652 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 3653 #define G_FW_PARAMS_PARAM_X(x) \ 3654 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 3655 3656 #define S_FW_PARAMS_PARAM_Y 8 3657 #define M_FW_PARAMS_PARAM_Y 0xff 3658 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 3659 #define G_FW_PARAMS_PARAM_Y(x) \ 3660 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 3661 3662 #define S_FW_PARAMS_PARAM_Z 0 3663 #define M_FW_PARAMS_PARAM_Z 0xff 3664 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 3665 #define G_FW_PARAMS_PARAM_Z(x) \ 3666 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 3667 3668 #define S_FW_PARAMS_PARAM_XYZ 0 3669 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 3670 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 3671 #define G_FW_PARAMS_PARAM_XYZ(x) \ 3672 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 3673 3674 #define S_FW_PARAMS_PARAM_YZ 0 3675 #define M_FW_PARAMS_PARAM_YZ 0xffff 3676 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 3677 #define G_FW_PARAMS_PARAM_YZ(x) \ 3678 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 3679 3680 struct fw_params_cmd { 3681 __be32 op_to_vfn; 3682 __be32 retval_len16; 3683 struct fw_params_param { 3684 __be32 mnem; 3685 __be32 val; 3686 } param[7]; 3687 }; 3688 3689 #define S_FW_PARAMS_CMD_PFN 8 3690 #define M_FW_PARAMS_CMD_PFN 0x7 3691 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 3692 #define G_FW_PARAMS_CMD_PFN(x) \ 3693 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 3694 3695 #define S_FW_PARAMS_CMD_VFN 0 3696 #define M_FW_PARAMS_CMD_VFN 0xff 3697 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 3698 #define G_FW_PARAMS_CMD_VFN(x) \ 3699 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 3700 3701 struct fw_pfvf_cmd { 3702 __be32 op_to_vfn; 3703 __be32 retval_len16; 3704 __be32 niqflint_niq; 3705 __be32 type_to_neq; 3706 __be32 tc_to_nexactf; 3707 __be32 r_caps_to_nethctrl; 3708 __be16 nricq; 3709 __be16 nriqp; 3710 __be32 r4; 3711 }; 3712 3713 #define S_FW_PFVF_CMD_PFN 8 3714 #define M_FW_PFVF_CMD_PFN 0x7 3715 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 3716 #define G_FW_PFVF_CMD_PFN(x) \ 3717 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 3718 3719 #define S_FW_PFVF_CMD_VFN 0 3720 #define M_FW_PFVF_CMD_VFN 0xff 3721 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 3722 #define G_FW_PFVF_CMD_VFN(x) \ 3723 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 3724 3725 #define S_FW_PFVF_CMD_NIQFLINT 20 3726 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 3727 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 3728 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 3729 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 3730 3731 #define S_FW_PFVF_CMD_NIQ 0 3732 #define M_FW_PFVF_CMD_NIQ 0xfffff 3733 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 3734 #define G_FW_PFVF_CMD_NIQ(x) \ 3735 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 3736 3737 #define S_FW_PFVF_CMD_TYPE 31 3738 #define M_FW_PFVF_CMD_TYPE 0x1 3739 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 3740 #define G_FW_PFVF_CMD_TYPE(x) \ 3741 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 3742 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 3743 3744 #define S_FW_PFVF_CMD_CMASK 24 3745 #define M_FW_PFVF_CMD_CMASK 0xf 3746 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 3747 #define G_FW_PFVF_CMD_CMASK(x) \ 3748 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 3749 3750 #define S_FW_PFVF_CMD_PMASK 20 3751 #define M_FW_PFVF_CMD_PMASK 0xf 3752 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 3753 #define G_FW_PFVF_CMD_PMASK(x) \ 3754 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 3755 3756 #define S_FW_PFVF_CMD_NEQ 0 3757 #define M_FW_PFVF_CMD_NEQ 0xfffff 3758 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 3759 #define G_FW_PFVF_CMD_NEQ(x) \ 3760 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 3761 3762 #define S_FW_PFVF_CMD_TC 24 3763 #define M_FW_PFVF_CMD_TC 0xff 3764 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 3765 #define G_FW_PFVF_CMD_TC(x) (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 3766 3767 #define S_FW_PFVF_CMD_NVI 16 3768 #define M_FW_PFVF_CMD_NVI 0xff 3769 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 3770 #define G_FW_PFVF_CMD_NVI(x) \ 3771 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 3772 3773 #define S_FW_PFVF_CMD_NEXACTF 0 3774 #define M_FW_PFVF_CMD_NEXACTF 0xffff 3775 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 3776 #define G_FW_PFVF_CMD_NEXACTF(x) \ 3777 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 3778 3779 #define S_FW_PFVF_CMD_R_CAPS 24 3780 #define M_FW_PFVF_CMD_R_CAPS 0xff 3781 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 3782 #define G_FW_PFVF_CMD_R_CAPS(x) \ 3783 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 3784 3785 #define S_FW_PFVF_CMD_WX_CAPS 16 3786 #define M_FW_PFVF_CMD_WX_CAPS 0xff 3787 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 3788 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 3789 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 3790 3791 #define S_FW_PFVF_CMD_NETHCTRL 0 3792 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 3793 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 3794 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 3795 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 3796 3797 /* 3798 * ingress queue type; the first 1K ingress queues can have associated 0, 3799 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 3800 * capabilities 3801 */ 3802 enum fw_iq_type { 3803 FW_IQ_TYPE_FL_INT_CAP, 3804 FW_IQ_TYPE_NO_FL_INT_CAP 3805 }; 3806 3807 struct fw_iq_cmd { 3808 __be32 op_to_vfn; 3809 __be32 alloc_to_len16; 3810 __be16 physiqid; 3811 __be16 iqid; 3812 __be16 fl0id; 3813 __be16 fl1id; 3814 __be32 type_to_iqandstindex; 3815 __be16 iqdroprss_to_iqesize; 3816 __be16 iqsize; 3817 __be64 iqaddr; 3818 __be32 iqns_to_fl0congen; 3819 __be16 fl0dcaen_to_fl0cidxfthresh; 3820 __be16 fl0size; 3821 __be64 fl0addr; 3822 __be32 fl1cngchmap_to_fl1congen; 3823 __be16 fl1dcaen_to_fl1cidxfthresh; 3824 __be16 fl1size; 3825 __be64 fl1addr; 3826 }; 3827 3828 #define S_FW_IQ_CMD_PFN 8 3829 #define M_FW_IQ_CMD_PFN 0x7 3830 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 3831 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 3832 3833 #define S_FW_IQ_CMD_VFN 0 3834 #define M_FW_IQ_CMD_VFN 0xff 3835 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 3836 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 3837 3838 #define S_FW_IQ_CMD_ALLOC 31 3839 #define M_FW_IQ_CMD_ALLOC 0x1 3840 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 3841 #define G_FW_IQ_CMD_ALLOC(x) \ 3842 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 3843 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 3844 3845 #define S_FW_IQ_CMD_FREE 30 3846 #define M_FW_IQ_CMD_FREE 0x1 3847 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 3848 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 3849 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 3850 3851 #define S_FW_IQ_CMD_MODIFY 29 3852 #define M_FW_IQ_CMD_MODIFY 0x1 3853 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 3854 #define G_FW_IQ_CMD_MODIFY(x) \ 3855 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 3856 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 3857 3858 #define S_FW_IQ_CMD_IQSTART 28 3859 #define M_FW_IQ_CMD_IQSTART 0x1 3860 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 3861 #define G_FW_IQ_CMD_IQSTART(x) \ 3862 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 3863 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 3864 3865 #define S_FW_IQ_CMD_IQSTOP 27 3866 #define M_FW_IQ_CMD_IQSTOP 0x1 3867 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 3868 #define G_FW_IQ_CMD_IQSTOP(x) \ 3869 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 3870 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 3871 3872 #define S_FW_IQ_CMD_TYPE 29 3873 #define M_FW_IQ_CMD_TYPE 0x7 3874 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 3875 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 3876 3877 #define S_FW_IQ_CMD_IQASYNCH 28 3878 #define M_FW_IQ_CMD_IQASYNCH 0x1 3879 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 3880 #define G_FW_IQ_CMD_IQASYNCH(x) \ 3881 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 3882 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 3883 3884 #define S_FW_IQ_CMD_VIID 16 3885 #define M_FW_IQ_CMD_VIID 0xfff 3886 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 3887 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 3888 3889 #define S_FW_IQ_CMD_IQANDST 15 3890 #define M_FW_IQ_CMD_IQANDST 0x1 3891 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 3892 #define G_FW_IQ_CMD_IQANDST(x) \ 3893 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 3894 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 3895 3896 #define S_FW_IQ_CMD_IQANUS 14 3897 #define M_FW_IQ_CMD_IQANUS 0x1 3898 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 3899 #define G_FW_IQ_CMD_IQANUS(x) \ 3900 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 3901 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 3902 3903 #define S_FW_IQ_CMD_IQANUD 12 3904 #define M_FW_IQ_CMD_IQANUD 0x3 3905 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 3906 #define G_FW_IQ_CMD_IQANUD(x) \ 3907 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 3908 3909 #define S_FW_IQ_CMD_IQANDSTINDEX 0 3910 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 3911 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 3912 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 3913 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 3914 3915 #define S_FW_IQ_CMD_IQDROPRSS 15 3916 #define M_FW_IQ_CMD_IQDROPRSS 0x1 3917 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 3918 #define G_FW_IQ_CMD_IQDROPRSS(x) \ 3919 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 3920 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 3921 3922 #define S_FW_IQ_CMD_IQGTSMODE 14 3923 #define M_FW_IQ_CMD_IQGTSMODE 0x1 3924 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 3925 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 3926 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 3927 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 3928 3929 #define S_FW_IQ_CMD_IQPCIECH 12 3930 #define M_FW_IQ_CMD_IQPCIECH 0x3 3931 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 3932 #define G_FW_IQ_CMD_IQPCIECH(x) \ 3933 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 3934 3935 #define S_FW_IQ_CMD_IQDCAEN 11 3936 #define M_FW_IQ_CMD_IQDCAEN 0x1 3937 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 3938 #define G_FW_IQ_CMD_IQDCAEN(x) \ 3939 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 3940 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 3941 3942 #define S_FW_IQ_CMD_IQDCACPU 6 3943 #define M_FW_IQ_CMD_IQDCACPU 0x1f 3944 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 3945 #define G_FW_IQ_CMD_IQDCACPU(x) \ 3946 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 3947 3948 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 3949 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 3950 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 3951 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 3952 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 3953 3954 #define S_FW_IQ_CMD_IQO 3 3955 #define M_FW_IQ_CMD_IQO 0x1 3956 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 3957 #define G_FW_IQ_CMD_IQO(x) (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 3958 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 3959 3960 #define S_FW_IQ_CMD_IQCPRIO 2 3961 #define M_FW_IQ_CMD_IQCPRIO 0x1 3962 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 3963 #define G_FW_IQ_CMD_IQCPRIO(x) \ 3964 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 3965 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 3966 3967 #define S_FW_IQ_CMD_IQESIZE 0 3968 #define M_FW_IQ_CMD_IQESIZE 0x3 3969 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 3970 #define G_FW_IQ_CMD_IQESIZE(x) \ 3971 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 3972 3973 #define S_FW_IQ_CMD_IQNS 31 3974 #define M_FW_IQ_CMD_IQNS 0x1 3975 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 3976 #define G_FW_IQ_CMD_IQNS(x) (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 3977 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 3978 3979 #define S_FW_IQ_CMD_IQRO 30 3980 #define M_FW_IQ_CMD_IQRO 0x1 3981 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 3982 #define G_FW_IQ_CMD_IQRO(x) (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 3983 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 3984 3985 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 3986 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 3987 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 3988 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 3989 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 3990 3991 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 3992 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 3993 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 3994 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 3995 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 3996 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 3997 3998 #define S_FW_IQ_CMD_IQFLINTISCSIC 26 3999 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 4000 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 4001 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 4002 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 4003 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 4004 4005 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 4006 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 4007 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 4008 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 4009 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 4010 4011 #define S_FW_IQ_CMD_FL0CACHELOCK 15 4012 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 4013 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 4014 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 4015 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 4016 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 4017 4018 #define S_FW_IQ_CMD_FL0DBP 14 4019 #define M_FW_IQ_CMD_FL0DBP 0x1 4020 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 4021 #define G_FW_IQ_CMD_FL0DBP(x) \ 4022 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 4023 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 4024 4025 #define S_FW_IQ_CMD_FL0DATANS 13 4026 #define M_FW_IQ_CMD_FL0DATANS 0x1 4027 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 4028 #define G_FW_IQ_CMD_FL0DATANS(x) \ 4029 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 4030 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 4031 4032 #define S_FW_IQ_CMD_FL0DATARO 12 4033 #define M_FW_IQ_CMD_FL0DATARO 0x1 4034 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 4035 #define G_FW_IQ_CMD_FL0DATARO(x) \ 4036 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 4037 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 4038 4039 #define S_FW_IQ_CMD_FL0CONGCIF 11 4040 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 4041 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 4042 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 4043 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 4044 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 4045 4046 #define S_FW_IQ_CMD_FL0ONCHIP 10 4047 #define M_FW_IQ_CMD_FL0ONCHIP 0x1 4048 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 4049 #define G_FW_IQ_CMD_FL0ONCHIP(x) \ 4050 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 4051 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 4052 4053 #define S_FW_IQ_CMD_FL0STATUSPGNS 9 4054 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 4055 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 4056 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 4057 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 4058 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 4059 4060 #define S_FW_IQ_CMD_FL0STATUSPGRO 8 4061 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 4062 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 4063 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 4064 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 4065 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 4066 4067 #define S_FW_IQ_CMD_FL0FETCHNS 7 4068 #define M_FW_IQ_CMD_FL0FETCHNS 0x1 4069 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 4070 #define G_FW_IQ_CMD_FL0FETCHNS(x) \ 4071 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 4072 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 4073 4074 #define S_FW_IQ_CMD_FL0FETCHRO 6 4075 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 4076 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 4077 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 4078 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 4079 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 4080 4081 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 4082 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 4083 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 4084 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 4085 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 4086 4087 #define S_FW_IQ_CMD_FL0CPRIO 3 4088 #define M_FW_IQ_CMD_FL0CPRIO 0x1 4089 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 4090 #define G_FW_IQ_CMD_FL0CPRIO(x) \ 4091 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 4092 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 4093 4094 #define S_FW_IQ_CMD_FL0PADEN 2 4095 #define M_FW_IQ_CMD_FL0PADEN 0x1 4096 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 4097 #define G_FW_IQ_CMD_FL0PADEN(x) \ 4098 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 4099 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 4100 4101 #define S_FW_IQ_CMD_FL0PACKEN 1 4102 #define M_FW_IQ_CMD_FL0PACKEN 0x1 4103 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 4104 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 4105 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 4106 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 4107 4108 #define S_FW_IQ_CMD_FL0CONGEN 0 4109 #define M_FW_IQ_CMD_FL0CONGEN 0x1 4110 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 4111 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 4112 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 4113 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 4114 4115 #define S_FW_IQ_CMD_FL0DCAEN 15 4116 #define M_FW_IQ_CMD_FL0DCAEN 0x1 4117 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 4118 #define G_FW_IQ_CMD_FL0DCAEN(x) \ 4119 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 4120 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 4121 4122 #define S_FW_IQ_CMD_FL0DCACPU 10 4123 #define M_FW_IQ_CMD_FL0DCACPU 0x1f 4124 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 4125 #define G_FW_IQ_CMD_FL0DCACPU(x) \ 4126 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 4127 4128 #define S_FW_IQ_CMD_FL0FBMIN 7 4129 #define M_FW_IQ_CMD_FL0FBMIN 0x7 4130 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 4131 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 4132 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 4133 4134 #define S_FW_IQ_CMD_FL0FBMAX 4 4135 #define M_FW_IQ_CMD_FL0FBMAX 0x7 4136 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 4137 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 4138 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 4139 4140 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 4141 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 4142 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 4143 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 4144 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 4145 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 4146 4147 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 4148 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 4149 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 4150 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 4151 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 4152 4153 #define S_FW_IQ_CMD_FL1CNGCHMAP 20 4154 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 4155 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 4156 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 4157 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 4158 4159 #define S_FW_IQ_CMD_FL1CACHELOCK 15 4160 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 4161 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 4162 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 4163 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 4164 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 4165 4166 #define S_FW_IQ_CMD_FL1DBP 14 4167 #define M_FW_IQ_CMD_FL1DBP 0x1 4168 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 4169 #define G_FW_IQ_CMD_FL1DBP(x) \ 4170 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 4171 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 4172 4173 #define S_FW_IQ_CMD_FL1DATANS 13 4174 #define M_FW_IQ_CMD_FL1DATANS 0x1 4175 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 4176 #define G_FW_IQ_CMD_FL1DATANS(x) \ 4177 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 4178 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 4179 4180 #define S_FW_IQ_CMD_FL1DATARO 12 4181 #define M_FW_IQ_CMD_FL1DATARO 0x1 4182 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 4183 #define G_FW_IQ_CMD_FL1DATARO(x) \ 4184 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 4185 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 4186 4187 #define S_FW_IQ_CMD_FL1CONGCIF 11 4188 #define M_FW_IQ_CMD_FL1CONGCIF 0x1 4189 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 4190 #define G_FW_IQ_CMD_FL1CONGCIF(x) \ 4191 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 4192 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 4193 4194 #define S_FW_IQ_CMD_FL1ONCHIP 10 4195 #define M_FW_IQ_CMD_FL1ONCHIP 0x1 4196 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 4197 #define G_FW_IQ_CMD_FL1ONCHIP(x) \ 4198 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 4199 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 4200 4201 #define S_FW_IQ_CMD_FL1STATUSPGNS 9 4202 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 4203 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 4204 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 4205 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 4206 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 4207 4208 #define S_FW_IQ_CMD_FL1STATUSPGRO 8 4209 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 4210 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 4211 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 4212 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 4213 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 4214 4215 #define S_FW_IQ_CMD_FL1FETCHNS 7 4216 #define M_FW_IQ_CMD_FL1FETCHNS 0x1 4217 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 4218 #define G_FW_IQ_CMD_FL1FETCHNS(x) \ 4219 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 4220 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 4221 4222 #define S_FW_IQ_CMD_FL1FETCHRO 6 4223 #define M_FW_IQ_CMD_FL1FETCHRO 0x1 4224 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 4225 #define G_FW_IQ_CMD_FL1FETCHRO(x) \ 4226 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 4227 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 4228 4229 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 4230 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 4231 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 4232 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 4233 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 4234 4235 #define S_FW_IQ_CMD_FL1CPRIO 3 4236 #define M_FW_IQ_CMD_FL1CPRIO 0x1 4237 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 4238 #define G_FW_IQ_CMD_FL1CPRIO(x) \ 4239 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 4240 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 4241 4242 #define S_FW_IQ_CMD_FL1PADEN 2 4243 #define M_FW_IQ_CMD_FL1PADEN 0x1 4244 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 4245 #define G_FW_IQ_CMD_FL1PADEN(x) \ 4246 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 4247 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 4248 4249 #define S_FW_IQ_CMD_FL1PACKEN 1 4250 #define M_FW_IQ_CMD_FL1PACKEN 0x1 4251 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 4252 #define G_FW_IQ_CMD_FL1PACKEN(x) \ 4253 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 4254 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 4255 4256 #define S_FW_IQ_CMD_FL1CONGEN 0 4257 #define M_FW_IQ_CMD_FL1CONGEN 0x1 4258 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 4259 #define G_FW_IQ_CMD_FL1CONGEN(x) \ 4260 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 4261 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 4262 4263 #define S_FW_IQ_CMD_FL1DCAEN 15 4264 #define M_FW_IQ_CMD_FL1DCAEN 0x1 4265 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 4266 #define G_FW_IQ_CMD_FL1DCAEN(x) \ 4267 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 4268 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 4269 4270 #define S_FW_IQ_CMD_FL1DCACPU 10 4271 #define M_FW_IQ_CMD_FL1DCACPU 0x1f 4272 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 4273 #define G_FW_IQ_CMD_FL1DCACPU(x) \ 4274 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 4275 4276 #define S_FW_IQ_CMD_FL1FBMIN 7 4277 #define M_FW_IQ_CMD_FL1FBMIN 0x7 4278 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 4279 #define G_FW_IQ_CMD_FL1FBMIN(x) \ 4280 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 4281 4282 #define S_FW_IQ_CMD_FL1FBMAX 4 4283 #define M_FW_IQ_CMD_FL1FBMAX 0x7 4284 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 4285 #define G_FW_IQ_CMD_FL1FBMAX(x) \ 4286 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 4287 4288 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 4289 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 4290 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 4291 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 4292 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 4293 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 4294 4295 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 4296 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 4297 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 4298 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 4299 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 4300 4301 struct fw_eq_mngt_cmd { 4302 __be32 op_to_vfn; 4303 __be32 alloc_to_len16; 4304 __be32 cmpliqid_eqid; 4305 __be32 physeqid_pkd; 4306 __be32 fetchszm_to_iqid; 4307 __be32 dcaen_to_eqsize; 4308 __be64 eqaddr; 4309 }; 4310 4311 #define S_FW_EQ_MNGT_CMD_PFN 8 4312 #define M_FW_EQ_MNGT_CMD_PFN 0x7 4313 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 4314 #define G_FW_EQ_MNGT_CMD_PFN(x) \ 4315 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 4316 4317 #define S_FW_EQ_MNGT_CMD_VFN 0 4318 #define M_FW_EQ_MNGT_CMD_VFN 0xff 4319 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 4320 #define G_FW_EQ_MNGT_CMD_VFN(x) \ 4321 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 4322 4323 #define S_FW_EQ_MNGT_CMD_ALLOC 31 4324 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 4325 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 4326 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 4327 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 4328 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 4329 4330 #define S_FW_EQ_MNGT_CMD_FREE 30 4331 #define M_FW_EQ_MNGT_CMD_FREE 0x1 4332 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 4333 #define G_FW_EQ_MNGT_CMD_FREE(x) \ 4334 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 4335 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 4336 4337 #define S_FW_EQ_MNGT_CMD_MODIFY 29 4338 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 4339 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 4340 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 4341 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 4342 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 4343 4344 #define S_FW_EQ_MNGT_CMD_EQSTART 28 4345 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 4346 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 4347 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 4348 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 4349 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 4350 4351 #define S_FW_EQ_MNGT_CMD_EQSTOP 27 4352 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 4353 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 4354 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 4355 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 4356 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 4357 4358 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 4359 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 4360 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 4361 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 4362 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 4363 4364 #define S_FW_EQ_MNGT_CMD_EQID 0 4365 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff 4366 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 4367 #define G_FW_EQ_MNGT_CMD_EQID(x) \ 4368 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 4369 4370 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 4371 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 4372 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 4373 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 4374 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 4375 4376 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 4377 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 4378 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 4379 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 4380 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 4381 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 4382 4383 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 4384 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 4385 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 4386 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 4387 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 4388 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 4389 4390 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 4391 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 4392 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 4393 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 4394 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 4395 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 4396 4397 #define S_FW_EQ_MNGT_CMD_FETCHNS 23 4398 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 4399 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 4400 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 4401 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 4402 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 4403 4404 #define S_FW_EQ_MNGT_CMD_FETCHRO 22 4405 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 4406 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 4407 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 4408 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 4409 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 4410 4411 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 4412 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 4413 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 4414 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 4415 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 4416 4417 #define S_FW_EQ_MNGT_CMD_CPRIO 19 4418 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 4419 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 4420 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 4421 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 4422 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 4423 4424 #define S_FW_EQ_MNGT_CMD_ONCHIP 18 4425 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 4426 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 4427 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 4428 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 4429 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 4430 4431 #define S_FW_EQ_MNGT_CMD_PCIECHN 16 4432 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 4433 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 4434 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 4435 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 4436 4437 #define S_FW_EQ_MNGT_CMD_IQID 0 4438 #define M_FW_EQ_MNGT_CMD_IQID 0xffff 4439 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 4440 #define G_FW_EQ_MNGT_CMD_IQID(x) \ 4441 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 4442 4443 #define S_FW_EQ_MNGT_CMD_DCAEN 31 4444 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 4445 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 4446 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 4447 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 4448 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 4449 4450 #define S_FW_EQ_MNGT_CMD_DCACPU 26 4451 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 4452 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 4453 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 4454 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 4455 4456 #define S_FW_EQ_MNGT_CMD_FBMIN 23 4457 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 4458 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 4459 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 4460 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 4461 4462 #define S_FW_EQ_MNGT_CMD_FBMAX 20 4463 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 4464 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 4465 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 4466 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 4467 4468 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 4469 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 4470 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 4471 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 4472 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 4473 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 4474 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 4475 4476 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 4477 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 4478 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 4479 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 4480 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 4481 4482 #define S_FW_EQ_MNGT_CMD_EQSIZE 0 4483 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 4484 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 4485 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 4486 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 4487 4488 struct fw_eq_eth_cmd { 4489 __be32 op_to_vfn; 4490 __be32 alloc_to_len16; 4491 __be32 eqid_pkd; 4492 __be32 physeqid_pkd; 4493 __be32 fetchszm_to_iqid; 4494 __be32 dcaen_to_eqsize; 4495 __be64 eqaddr; 4496 __be32 viid_pkd; 4497 __be32 r8_lo; 4498 __be64 r9; 4499 }; 4500 4501 #define S_FW_EQ_ETH_CMD_PFN 8 4502 #define M_FW_EQ_ETH_CMD_PFN 0x7 4503 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 4504 #define G_FW_EQ_ETH_CMD_PFN(x) \ 4505 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 4506 4507 #define S_FW_EQ_ETH_CMD_VFN 0 4508 #define M_FW_EQ_ETH_CMD_VFN 0xff 4509 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 4510 #define G_FW_EQ_ETH_CMD_VFN(x) \ 4511 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 4512 4513 #define S_FW_EQ_ETH_CMD_ALLOC 31 4514 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 4515 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 4516 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 4517 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 4518 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 4519 4520 #define S_FW_EQ_ETH_CMD_FREE 30 4521 #define M_FW_EQ_ETH_CMD_FREE 0x1 4522 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 4523 #define G_FW_EQ_ETH_CMD_FREE(x) \ 4524 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 4525 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 4526 4527 #define S_FW_EQ_ETH_CMD_MODIFY 29 4528 #define M_FW_EQ_ETH_CMD_MODIFY 0x1 4529 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 4530 #define G_FW_EQ_ETH_CMD_MODIFY(x) \ 4531 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 4532 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 4533 4534 #define S_FW_EQ_ETH_CMD_EQSTART 28 4535 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 4536 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 4537 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 4538 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 4539 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 4540 4541 #define S_FW_EQ_ETH_CMD_EQSTOP 27 4542 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 4543 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 4544 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 4545 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 4546 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 4547 4548 #define S_FW_EQ_ETH_CMD_EQID 0 4549 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 4550 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 4551 #define G_FW_EQ_ETH_CMD_EQID(x) \ 4552 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 4553 4554 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 4555 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 4556 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 4557 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 4558 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 4559 4560 #define S_FW_EQ_ETH_CMD_FETCHSZM 26 4561 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 4562 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 4563 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 4564 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 4565 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 4566 4567 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 4568 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 4569 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 4570 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 4571 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 4572 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 4573 4574 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 4575 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 4576 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 4577 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 4578 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 4579 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 4580 4581 #define S_FW_EQ_ETH_CMD_FETCHNS 23 4582 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 4583 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 4584 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 4585 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 4586 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 4587 4588 #define S_FW_EQ_ETH_CMD_FETCHRO 22 4589 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 4590 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 4591 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 4592 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 4593 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 4594 4595 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 4596 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 4597 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 4598 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 4599 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 4600 4601 #define S_FW_EQ_ETH_CMD_CPRIO 19 4602 #define M_FW_EQ_ETH_CMD_CPRIO 0x1 4603 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 4604 #define G_FW_EQ_ETH_CMD_CPRIO(x) \ 4605 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 4606 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 4607 4608 #define S_FW_EQ_ETH_CMD_ONCHIP 18 4609 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 4610 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 4611 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 4612 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 4613 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 4614 4615 #define S_FW_EQ_ETH_CMD_PCIECHN 16 4616 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 4617 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 4618 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 4619 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 4620 4621 #define S_FW_EQ_ETH_CMD_IQID 0 4622 #define M_FW_EQ_ETH_CMD_IQID 0xffff 4623 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 4624 #define G_FW_EQ_ETH_CMD_IQID(x) \ 4625 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 4626 4627 #define S_FW_EQ_ETH_CMD_DCAEN 31 4628 #define M_FW_EQ_ETH_CMD_DCAEN 0x1 4629 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 4630 #define G_FW_EQ_ETH_CMD_DCAEN(x) \ 4631 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 4632 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 4633 4634 #define S_FW_EQ_ETH_CMD_DCACPU 26 4635 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f 4636 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 4637 #define G_FW_EQ_ETH_CMD_DCACPU(x) \ 4638 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 4639 4640 #define S_FW_EQ_ETH_CMD_FBMIN 23 4641 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 4642 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 4643 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 4644 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 4645 4646 #define S_FW_EQ_ETH_CMD_FBMAX 20 4647 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 4648 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 4649 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 4650 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 4651 4652 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 4653 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 4654 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 4655 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 4656 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 4657 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 4658 4659 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 4660 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 4661 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 4662 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 4663 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 4664 4665 #define S_FW_EQ_ETH_CMD_EQSIZE 0 4666 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 4667 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 4668 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 4669 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 4670 4671 #define S_FW_EQ_ETH_CMD_VIID 16 4672 #define M_FW_EQ_ETH_CMD_VIID 0xfff 4673 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 4674 #define G_FW_EQ_ETH_CMD_VIID(x) \ 4675 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 4676 4677 struct fw_eq_ctrl_cmd { 4678 __be32 op_to_vfn; 4679 __be32 alloc_to_len16; 4680 __be32 cmpliqid_eqid; 4681 __be32 physeqid_pkd; 4682 __be32 fetchszm_to_iqid; 4683 __be32 dcaen_to_eqsize; 4684 __be64 eqaddr; 4685 }; 4686 4687 #define S_FW_EQ_CTRL_CMD_PFN 8 4688 #define M_FW_EQ_CTRL_CMD_PFN 0x7 4689 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 4690 #define G_FW_EQ_CTRL_CMD_PFN(x) \ 4691 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 4692 4693 #define S_FW_EQ_CTRL_CMD_VFN 0 4694 #define M_FW_EQ_CTRL_CMD_VFN 0xff 4695 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 4696 #define G_FW_EQ_CTRL_CMD_VFN(x) \ 4697 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 4698 4699 #define S_FW_EQ_CTRL_CMD_ALLOC 31 4700 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 4701 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 4702 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 4703 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 4704 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 4705 4706 #define S_FW_EQ_CTRL_CMD_FREE 30 4707 #define M_FW_EQ_CTRL_CMD_FREE 0x1 4708 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 4709 #define G_FW_EQ_CTRL_CMD_FREE(x) \ 4710 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 4711 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 4712 4713 #define S_FW_EQ_CTRL_CMD_MODIFY 29 4714 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 4715 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 4716 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 4717 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 4718 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 4719 4720 #define S_FW_EQ_CTRL_CMD_EQSTART 28 4721 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 4722 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 4723 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 4724 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 4725 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 4726 4727 #define S_FW_EQ_CTRL_CMD_EQSTOP 27 4728 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 4729 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 4730 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 4731 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 4732 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 4733 4734 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 4735 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 4736 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 4737 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 4738 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 4739 4740 #define S_FW_EQ_CTRL_CMD_EQID 0 4741 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 4742 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 4743 #define G_FW_EQ_CTRL_CMD_EQID(x) \ 4744 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 4745 4746 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 4747 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 4748 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 4749 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 4750 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 4751 4752 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 4753 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 4754 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 4755 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 4756 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 4757 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 4758 4759 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 4760 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 4761 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 4762 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 4763 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 4764 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 4765 4766 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 4767 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 4768 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 4769 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 4770 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 4771 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 4772 4773 #define S_FW_EQ_CTRL_CMD_FETCHNS 23 4774 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 4775 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 4776 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 4777 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 4778 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 4779 4780 #define S_FW_EQ_CTRL_CMD_FETCHRO 22 4781 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 4782 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 4783 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 4784 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 4785 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 4786 4787 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 4788 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 4789 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 4790 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 4791 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 4792 4793 #define S_FW_EQ_CTRL_CMD_CPRIO 19 4794 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 4795 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 4796 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 4797 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 4798 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 4799 4800 #define S_FW_EQ_CTRL_CMD_ONCHIP 18 4801 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 4802 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 4803 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 4804 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 4805 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 4806 4807 #define S_FW_EQ_CTRL_CMD_PCIECHN 16 4808 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 4809 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 4810 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 4811 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 4812 4813 #define S_FW_EQ_CTRL_CMD_IQID 0 4814 #define M_FW_EQ_CTRL_CMD_IQID 0xffff 4815 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 4816 #define G_FW_EQ_CTRL_CMD_IQID(x) \ 4817 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 4818 4819 #define S_FW_EQ_CTRL_CMD_DCAEN 31 4820 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 4821 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 4822 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 4823 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 4824 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 4825 4826 #define S_FW_EQ_CTRL_CMD_DCACPU 26 4827 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 4828 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 4829 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 4830 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 4831 4832 #define S_FW_EQ_CTRL_CMD_FBMIN 23 4833 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 4834 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 4835 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 4836 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 4837 4838 #define S_FW_EQ_CTRL_CMD_FBMAX 20 4839 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 4840 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 4841 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 4842 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 4843 4844 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 4845 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 4846 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 4847 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 4848 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 4849 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 4850 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 4851 4852 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 4853 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 4854 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 4855 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 4856 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 4857 4858 #define S_FW_EQ_CTRL_CMD_EQSIZE 0 4859 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 4860 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 4861 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 4862 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 4863 4864 struct fw_eq_ofld_cmd { 4865 __be32 op_to_vfn; 4866 __be32 alloc_to_len16; 4867 __be32 eqid_pkd; 4868 __be32 physeqid_pkd; 4869 __be32 fetchszm_to_iqid; 4870 __be32 dcaen_to_eqsize; 4871 __be64 eqaddr; 4872 }; 4873 4874 #define S_FW_EQ_OFLD_CMD_PFN 8 4875 #define M_FW_EQ_OFLD_CMD_PFN 0x7 4876 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 4877 #define G_FW_EQ_OFLD_CMD_PFN(x) \ 4878 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 4879 4880 #define S_FW_EQ_OFLD_CMD_VFN 0 4881 #define M_FW_EQ_OFLD_CMD_VFN 0xff 4882 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 4883 #define G_FW_EQ_OFLD_CMD_VFN(x) \ 4884 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 4885 4886 #define S_FW_EQ_OFLD_CMD_ALLOC 31 4887 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 4888 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 4889 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 4890 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 4891 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 4892 4893 #define S_FW_EQ_OFLD_CMD_FREE 30 4894 #define M_FW_EQ_OFLD_CMD_FREE 0x1 4895 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 4896 #define G_FW_EQ_OFLD_CMD_FREE(x) \ 4897 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 4898 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 4899 4900 #define S_FW_EQ_OFLD_CMD_MODIFY 29 4901 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 4902 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 4903 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 4904 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 4905 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 4906 4907 #define S_FW_EQ_OFLD_CMD_EQSTART 28 4908 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 4909 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 4910 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 4911 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 4912 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 4913 4914 #define S_FW_EQ_OFLD_CMD_EQSTOP 27 4915 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 4916 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 4917 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 4918 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 4919 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 4920 4921 #define S_FW_EQ_OFLD_CMD_EQID 0 4922 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff 4923 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 4924 #define G_FW_EQ_OFLD_CMD_EQID(x) \ 4925 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 4926 4927 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 4928 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 4929 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 4930 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 4931 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 4932 4933 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 4934 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 4935 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 4936 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 4937 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 4938 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 4939 4940 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 4941 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 4942 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 4943 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 4944 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 4945 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 4946 4947 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 4948 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 4949 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 4950 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 4951 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 4952 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 4953 4954 #define S_FW_EQ_OFLD_CMD_FETCHNS 23 4955 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 4956 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 4957 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 4958 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 4959 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 4960 4961 #define S_FW_EQ_OFLD_CMD_FETCHRO 22 4962 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 4963 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 4964 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 4965 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 4966 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 4967 4968 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 4969 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 4970 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 4971 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 4972 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 4973 4974 #define S_FW_EQ_OFLD_CMD_CPRIO 19 4975 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 4976 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 4977 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 4978 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 4979 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 4980 4981 #define S_FW_EQ_OFLD_CMD_ONCHIP 18 4982 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 4983 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 4984 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 4985 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 4986 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 4987 4988 #define S_FW_EQ_OFLD_CMD_PCIECHN 16 4989 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 4990 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 4991 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 4992 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 4993 4994 #define S_FW_EQ_OFLD_CMD_IQID 0 4995 #define M_FW_EQ_OFLD_CMD_IQID 0xffff 4996 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 4997 #define G_FW_EQ_OFLD_CMD_IQID(x) \ 4998 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 4999 5000 #define S_FW_EQ_OFLD_CMD_DCAEN 31 5001 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 5002 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 5003 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 5004 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 5005 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 5006 5007 #define S_FW_EQ_OFLD_CMD_DCACPU 26 5008 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 5009 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 5010 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 5011 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 5012 5013 #define S_FW_EQ_OFLD_CMD_FBMIN 23 5014 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 5015 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 5016 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 5017 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 5018 5019 #define S_FW_EQ_OFLD_CMD_FBMAX 20 5020 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 5021 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 5022 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 5023 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 5024 5025 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 5026 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 5027 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 5028 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 5029 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 5030 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 5031 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 5032 5033 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 5034 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 5035 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 5036 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 5037 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 5038 5039 #define S_FW_EQ_OFLD_CMD_EQSIZE 0 5040 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 5041 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 5042 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 5043 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 5044 5045 /* 5046 * Macros for VIID parsing: 5047 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number 5048 */ 5049 #define S_FW_VIID_PFN 8 5050 #define M_FW_VIID_PFN 0x7 5051 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 5052 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 5053 5054 #define S_FW_VIID_VIVLD 7 5055 #define M_FW_VIID_VIVLD 0x1 5056 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 5057 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 5058 5059 #define S_FW_VIID_VIN 0 5060 #define M_FW_VIID_VIN 0x7F 5061 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 5062 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 5063 5064 enum fw_vi_func { 5065 FW_VI_FUNC_ETH, 5066 FW_VI_FUNC_OFLD, 5067 FW_VI_FUNC_IWARP, 5068 FW_VI_FUNC_OPENISCSI, 5069 FW_VI_FUNC_OPENFCOE, 5070 FW_VI_FUNC_FOISCSI, 5071 FW_VI_FUNC_FOFCOE, 5072 FW_VI_FUNC_FW, 5073 }; 5074 5075 struct fw_vi_cmd { 5076 __be32 op_to_vfn; 5077 __be32 alloc_to_len16; 5078 __be16 type_to_viid; 5079 __u8 mac[6]; 5080 __u8 portid_pkd; 5081 __u8 nmac; 5082 __u8 nmac0[6]; 5083 __be16 norss_rsssize; 5084 __u8 nmac1[6]; 5085 __be16 idsiiq_pkd; 5086 __u8 nmac2[6]; 5087 __be16 idseiq_pkd; 5088 __u8 nmac3[6]; 5089 __be64 r9; 5090 __be64 r10; 5091 }; 5092 5093 #define S_FW_VI_CMD_PFN 8 5094 #define M_FW_VI_CMD_PFN 0x7 5095 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 5096 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 5097 5098 #define S_FW_VI_CMD_VFN 0 5099 #define M_FW_VI_CMD_VFN 0xff 5100 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 5101 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 5102 5103 #define S_FW_VI_CMD_ALLOC 31 5104 #define M_FW_VI_CMD_ALLOC 0x1 5105 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 5106 #define G_FW_VI_CMD_ALLOC(x) \ 5107 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 5108 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 5109 5110 #define S_FW_VI_CMD_FREE 30 5111 #define M_FW_VI_CMD_FREE 0x1 5112 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 5113 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 5114 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 5115 5116 #define S_FW_VI_CMD_TYPE 15 5117 #define M_FW_VI_CMD_TYPE 0x1 5118 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 5119 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 5120 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 5121 5122 #define S_FW_VI_CMD_FUNC 12 5123 #define M_FW_VI_CMD_FUNC 0x7 5124 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 5125 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 5126 5127 #define S_FW_VI_CMD_VIID 0 5128 #define M_FW_VI_CMD_VIID 0xfff 5129 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 5130 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 5131 5132 #define S_FW_VI_CMD_PORTID 4 5133 #define M_FW_VI_CMD_PORTID 0xf 5134 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 5135 #define G_FW_VI_CMD_PORTID(x) \ 5136 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 5137 5138 #define S_FW_VI_CMD_NORSS 11 5139 #define M_FW_VI_CMD_NORSS 0x1 5140 #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 5141 #define G_FW_VI_CMD_NORSS(x) \ 5142 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 5143 #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 5144 5145 #define S_FW_VI_CMD_RSSSIZE 0 5146 #define M_FW_VI_CMD_RSSSIZE 0x7ff 5147 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 5148 #define G_FW_VI_CMD_RSSSIZE(x) \ 5149 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 5150 5151 #define S_FW_VI_CMD_IDSIIQ 0 5152 #define M_FW_VI_CMD_IDSIIQ 0x3ff 5153 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 5154 #define G_FW_VI_CMD_IDSIIQ(x) \ 5155 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 5156 5157 #define S_FW_VI_CMD_IDSEIQ 0 5158 #define M_FW_VI_CMD_IDSEIQ 0x3ff 5159 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 5160 #define G_FW_VI_CMD_IDSEIQ(x) \ 5161 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 5162 5163 /* Special VI_MAC command index ids */ 5164 #define FW_VI_MAC_ADD_MAC 0x3FF 5165 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 5166 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 5167 5168 enum fw_vi_mac_smac { 5169 FW_VI_MAC_MPS_TCAM_ENTRY, 5170 FW_VI_MAC_MPS_TCAM_ONLY, 5171 FW_VI_MAC_SMT_ONLY, 5172 FW_VI_MAC_SMT_AND_MPSTCAM 5173 }; 5174 5175 enum fw_vi_mac_result { 5176 FW_VI_MAC_R_SUCCESS, 5177 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 5178 FW_VI_MAC_R_SMAC_FAIL, 5179 FW_VI_MAC_R_F_ACL_CHECK 5180 }; 5181 5182 struct fw_vi_mac_cmd { 5183 __be32 op_to_viid; 5184 __be32 freemacs_to_len16; 5185 union fw_vi_mac { 5186 struct fw_vi_mac_exact { 5187 __be16 valid_to_idx; 5188 __u8 macaddr[6]; 5189 } exact[7]; 5190 struct fw_vi_mac_hash { 5191 __be64 hashvec; 5192 } hash; 5193 } u; 5194 }; 5195 5196 #define S_FW_VI_MAC_CMD_VIID 0 5197 #define M_FW_VI_MAC_CMD_VIID 0xfff 5198 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 5199 #define G_FW_VI_MAC_CMD_VIID(x) \ 5200 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 5201 5202 #define S_FW_VI_MAC_CMD_FREEMACS 31 5203 #define M_FW_VI_MAC_CMD_FREEMACS 0x1 5204 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 5205 #define G_FW_VI_MAC_CMD_FREEMACS(x) \ 5206 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 5207 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 5208 5209 #define S_FW_VI_MAC_CMD_HASHVECEN 23 5210 #define M_FW_VI_MAC_CMD_HASHVECEN 0x1 5211 #define V_FW_VI_MAC_CMD_HASHVECEN(x) ((x) << S_FW_VI_MAC_CMD_HASHVECEN) 5212 #define G_FW_VI_MAC_CMD_HASHVECEN(x) \ 5213 (((x) >> S_FW_VI_MAC_CMD_HASHVECEN) & M_FW_VI_MAC_CMD_HASHVECEN) 5214 #define F_FW_VI_MAC_CMD_HASHVECEN V_FW_VI_MAC_CMD_HASHVECEN(1U) 5215 5216 #define S_FW_VI_MAC_CMD_HASHUNIEN 22 5217 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 5218 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 5219 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 5220 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 5221 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 5222 5223 #define S_FW_VI_MAC_CMD_VALID 15 5224 #define M_FW_VI_MAC_CMD_VALID 0x1 5225 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 5226 #define G_FW_VI_MAC_CMD_VALID(x) \ 5227 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 5228 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 5229 5230 #define S_FW_VI_MAC_CMD_PRIO 12 5231 #define M_FW_VI_MAC_CMD_PRIO 0x7 5232 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 5233 #define G_FW_VI_MAC_CMD_PRIO(x) \ 5234 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 5235 5236 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 5237 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 5238 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 5239 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 5240 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 5241 5242 #define S_FW_VI_MAC_CMD_IDX 0 5243 #define M_FW_VI_MAC_CMD_IDX 0x3ff 5244 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 5245 #define G_FW_VI_MAC_CMD_IDX(x) \ 5246 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 5247 5248 /* T4 max MTU supported */ 5249 #define T4_MAX_MTU_SUPPORTED 9600 5250 #define FW_RXMODE_MTU_NO_CHG 65535 5251 5252 struct fw_vi_rxmode_cmd { 5253 __be32 op_to_viid; 5254 __be32 retval_len16; 5255 __be32 mtu_to_vlanexen; 5256 __be32 r4_lo; 5257 }; 5258 5259 #define S_FW_VI_RXMODE_CMD_VIID 0 5260 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 5261 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 5262 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 5263 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 5264 5265 #define S_FW_VI_RXMODE_CMD_MTU 16 5266 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 5267 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 5268 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 5269 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 5270 5271 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 5272 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 5273 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 5274 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 5275 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 5276 5277 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 5278 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 5279 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 5280 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 5281 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 5282 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 5283 5284 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 5285 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 5286 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 5287 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 5288 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 5289 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \ 5290 M_FW_VI_RXMODE_CMD_BROADCASTEN) 5291 5292 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 5293 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 5294 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 5295 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 5296 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 5297 5298 struct fw_vi_enable_cmd { 5299 __be32 op_to_viid; 5300 __be32 ien_to_len16; 5301 __be16 blinkdur; 5302 __be16 r3; 5303 __be32 r4; 5304 }; 5305 5306 #define S_FW_VI_ENABLE_CMD_VIID 0 5307 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 5308 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 5309 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 5310 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 5311 5312 #define S_FW_VI_ENABLE_CMD_IEN 31 5313 #define M_FW_VI_ENABLE_CMD_IEN 0x1 5314 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 5315 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 5316 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 5317 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 5318 5319 #define S_FW_VI_ENABLE_CMD_EEN 30 5320 #define M_FW_VI_ENABLE_CMD_EEN 0x1 5321 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 5322 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 5323 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 5324 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 5325 5326 #define S_FW_VI_ENABLE_CMD_LED 29 5327 #define M_FW_VI_ENABLE_CMD_LED 0x1 5328 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 5329 #define G_FW_VI_ENABLE_CMD_LED(x) \ 5330 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 5331 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 5332 5333 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 5334 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 5335 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 5336 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 5337 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 5338 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 5339 5340 /* VI VF stats offset definitions */ 5341 #define VI_VF_NUM_STATS 16 5342 enum fw_vi_stats_vf_index { 5343 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 5344 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 5345 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 5346 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 5347 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 5348 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 5349 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 5350 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 5351 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 5352 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 5353 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 5354 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 5355 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 5356 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 5357 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 5358 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 5359 }; 5360 5361 /* VI PF stats offset definitions */ 5362 #define VI_PF_NUM_STATS 17 5363 enum fw_vi_stats_pf_index { 5364 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 5365 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 5366 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 5367 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 5368 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 5369 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 5370 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 5371 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 5372 FW_VI_PF_STAT_RX_BYTES_IX, 5373 FW_VI_PF_STAT_RX_FRAMES_IX, 5374 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 5375 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 5376 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 5377 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 5378 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 5379 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 5380 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 5381 }; 5382 5383 struct fw_vi_stats_cmd { 5384 __be32 op_to_viid; 5385 __be32 retval_len16; 5386 union fw_vi_stats { 5387 struct fw_vi_stats_ctl { 5388 __be16 nstats_ix; 5389 __be16 r6; 5390 __be32 r7; 5391 __be64 stat0; 5392 __be64 stat1; 5393 __be64 stat2; 5394 __be64 stat3; 5395 __be64 stat4; 5396 __be64 stat5; 5397 } ctl; 5398 struct fw_vi_stats_pf { 5399 __be64 tx_bcast_bytes; 5400 __be64 tx_bcast_frames; 5401 __be64 tx_mcast_bytes; 5402 __be64 tx_mcast_frames; 5403 __be64 tx_ucast_bytes; 5404 __be64 tx_ucast_frames; 5405 __be64 tx_offload_bytes; 5406 __be64 tx_offload_frames; 5407 __be64 rx_pf_bytes; 5408 __be64 rx_pf_frames; 5409 __be64 rx_bcast_bytes; 5410 __be64 rx_bcast_frames; 5411 __be64 rx_mcast_bytes; 5412 __be64 rx_mcast_frames; 5413 __be64 rx_ucast_bytes; 5414 __be64 rx_ucast_frames; 5415 __be64 rx_err_frames; 5416 } pf; 5417 struct fw_vi_stats_vf { 5418 __be64 tx_bcast_bytes; 5419 __be64 tx_bcast_frames; 5420 __be64 tx_mcast_bytes; 5421 __be64 tx_mcast_frames; 5422 __be64 tx_ucast_bytes; 5423 __be64 tx_ucast_frames; 5424 __be64 tx_drop_frames; 5425 __be64 tx_offload_bytes; 5426 __be64 tx_offload_frames; 5427 __be64 rx_bcast_bytes; 5428 __be64 rx_bcast_frames; 5429 __be64 rx_mcast_bytes; 5430 __be64 rx_mcast_frames; 5431 __be64 rx_ucast_bytes; 5432 __be64 rx_ucast_frames; 5433 __be64 rx_err_frames; 5434 } vf; 5435 } u; 5436 }; 5437 5438 #define S_FW_VI_STATS_CMD_VIID 0 5439 #define M_FW_VI_STATS_CMD_VIID 0xfff 5440 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 5441 #define G_FW_VI_STATS_CMD_VIID(x) \ 5442 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 5443 5444 #define S_FW_VI_STATS_CMD_NSTATS 12 5445 #define M_FW_VI_STATS_CMD_NSTATS 0x7 5446 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 5447 #define G_FW_VI_STATS_CMD_NSTATS(x) \ 5448 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 5449 5450 #define S_FW_VI_STATS_CMD_IX 0 5451 #define M_FW_VI_STATS_CMD_IX 0x1f 5452 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 5453 #define G_FW_VI_STATS_CMD_IX(x) \ 5454 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 5455 5456 struct fw_acl_mac_cmd { 5457 __be32 op_to_vfn; 5458 __be32 en_to_len16; 5459 __u8 nmac; 5460 __u8 r3[7]; 5461 __be16 r4; 5462 __u8 macaddr0[6]; 5463 __be16 r5; 5464 __u8 macaddr1[6]; 5465 __be16 r6; 5466 __u8 macaddr2[6]; 5467 __be16 r7; 5468 __u8 macaddr3[6]; 5469 }; 5470 5471 #define S_FW_ACL_MAC_CMD_PFN 8 5472 #define M_FW_ACL_MAC_CMD_PFN 0x7 5473 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 5474 #define G_FW_ACL_MAC_CMD_PFN(x) \ 5475 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 5476 5477 #define S_FW_ACL_MAC_CMD_VFN 0 5478 #define M_FW_ACL_MAC_CMD_VFN 0xff 5479 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 5480 #define G_FW_ACL_MAC_CMD_VFN(x) \ 5481 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 5482 5483 #define S_FW_ACL_MAC_CMD_EN 31 5484 #define M_FW_ACL_MAC_CMD_EN 0x1 5485 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 5486 #define G_FW_ACL_MAC_CMD_EN(x) \ 5487 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 5488 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 5489 5490 struct fw_acl_vlan_cmd { 5491 __be32 op_to_vfn; 5492 __be32 en_to_len16; 5493 __u8 nvlan; 5494 __u8 dropnovlan_fm; 5495 __u8 r3_lo[6]; 5496 __be16 vlanid[16]; 5497 }; 5498 5499 #define S_FW_ACL_VLAN_CMD_PFN 8 5500 #define M_FW_ACL_VLAN_CMD_PFN 0x7 5501 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 5502 #define G_FW_ACL_VLAN_CMD_PFN(x) \ 5503 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 5504 5505 #define S_FW_ACL_VLAN_CMD_VFN 0 5506 #define M_FW_ACL_VLAN_CMD_VFN 0xff 5507 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 5508 #define G_FW_ACL_VLAN_CMD_VFN(x) \ 5509 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 5510 5511 #define S_FW_ACL_VLAN_CMD_EN 31 5512 #define M_FW_ACL_VLAN_CMD_EN 0x1 5513 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 5514 #define G_FW_ACL_VLAN_CMD_EN(x) \ 5515 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 5516 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 5517 5518 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 5519 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 5520 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 5521 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 5522 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 5523 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 5524 5525 #define S_FW_ACL_VLAN_CMD_FM 6 5526 #define M_FW_ACL_VLAN_CMD_FM 0x1 5527 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 5528 #define G_FW_ACL_VLAN_CMD_FM(x) \ 5529 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 5530 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 5531 5532 /* port capabilities bitmap */ 5533 enum fw_port_cap { 5534 FW_PORT_CAP_SPEED_100M = 0x0001, 5535 FW_PORT_CAP_SPEED_1G = 0x0002, 5536 FW_PORT_CAP_SPEED_2_5G = 0x0004, 5537 FW_PORT_CAP_SPEED_10G = 0x0008, 5538 FW_PORT_CAP_SPEED_40G = 0x0010, 5539 FW_PORT_CAP_SPEED_100G = 0x0020, 5540 FW_PORT_CAP_FC_RX = 0x0040, 5541 FW_PORT_CAP_FC_TX = 0x0080, 5542 FW_PORT_CAP_ANEG = 0x0100, 5543 FW_PORT_CAP_MDIX = 0x0200, 5544 FW_PORT_CAP_MDIAUTO = 0x0400, 5545 FW_PORT_CAP_FEC = 0x0800, 5546 FW_PORT_CAP_TECHKR = 0x1000, 5547 FW_PORT_CAP_TECHKX4 = 0x2000, 5548 }; 5549 5550 #define S_FW_PORT_AUXLINFO_MDI 3 5551 #define M_FW_PORT_AUXLINFO_MDI 0x3 5552 #define V_FW_PORT_AUXLINFO_MDI(x) ((x) << S_FW_PORT_AUXLINFO_MDI) 5553 #define G_FW_PORT_AUXLINFO_MDI(x) \ 5554 (((x) >> S_FW_PORT_AUXLINFO_MDI) & M_FW_PORT_AUXLINFO_MDI) 5555 5556 #define S_FW_PORT_AUXLINFO_KX4 2 5557 #define M_FW_PORT_AUXLINFO_KX4 0x1 5558 #define V_FW_PORT_AUXLINFO_KX4(x) ((x) << S_FW_PORT_AUXLINFO_KX4) 5559 #define G_FW_PORT_AUXLINFO_KX4(x) \ 5560 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 5561 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 5562 5563 #define S_FW_PORT_AUXLINFO_KR 1 5564 #define M_FW_PORT_AUXLINFO_KR 0x1 5565 #define V_FW_PORT_AUXLINFO_KR(x) ((x) << S_FW_PORT_AUXLINFO_KR) 5566 #define G_FW_PORT_AUXLINFO_KR(x) \ 5567 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 5568 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 5569 5570 #define S_FW_PORT_AUXLINFO_FEC 0 5571 #define M_FW_PORT_AUXLINFO_FEC 0x1 5572 #define V_FW_PORT_AUXLINFO_FEC(x) ((x) << S_FW_PORT_AUXLINFO_FEC) 5573 #define G_FW_PORT_AUXLINFO_FEC(x) \ 5574 (((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC) 5575 #define F_FW_PORT_AUXLINFO_FEC V_FW_PORT_AUXLINFO_FEC(1U) 5576 5577 #define S_FW_PORT_RCAP_AUX 11 5578 #define M_FW_PORT_RCAP_AUX 0x7 5579 #define V_FW_PORT_RCAP_AUX(x) ((x) << S_FW_PORT_RCAP_AUX) 5580 #define G_FW_PORT_RCAP_AUX(x) \ 5581 (((x) >> S_FW_PORT_RCAP_AUX) & M_FW_PORT_RCAP_AUX) 5582 5583 #define S_FW_PORT_CAP_SPEED 0 5584 #define M_FW_PORT_CAP_SPEED 0x3f 5585 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 5586 #define G_FW_PORT_CAP_SPEED(x) \ 5587 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 5588 5589 #define S_FW_PORT_CAP_FC 6 5590 #define M_FW_PORT_CAP_FC 0x3 5591 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 5592 #define G_FW_PORT_CAP_FC(x) \ 5593 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 5594 5595 #define S_FW_PORT_CAP_ANEG 8 5596 #define M_FW_PORT_CAP_ANEG 0x1 5597 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 5598 #define G_FW_PORT_CAP_ANEG(x) \ 5599 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 5600 5601 enum fw_port_mdi { 5602 FW_PORT_CAP_MDI_UNCHANGED, 5603 FW_PORT_CAP_MDI_AUTO, 5604 FW_PORT_CAP_MDI_F_STRAIGHT, 5605 FW_PORT_CAP_MDI_F_CROSSOVER 5606 }; 5607 5608 #define S_FW_PORT_CAP_MDI 9 5609 #define M_FW_PORT_CAP_MDI 3 5610 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 5611 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 5612 5613 enum fw_port_action { 5614 FW_PORT_ACTION_L1_CFG = 0x0001, 5615 FW_PORT_ACTION_L2_CFG = 0x0002, 5616 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 5617 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 5618 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 5619 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 5620 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 5621 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 5622 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 5623 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 5624 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 5625 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 5626 FW_PORT_ACTION_L1_SS_LPBK_ASIC = 0x0021, 5627 FW_PORT_ACTION_MAC_LPBK = 0x0022, 5628 FW_PORT_ACTION_L1_WS_LPBK_ASIC = 0x0023, 5629 FW_PORT_ACTION_L1_EXT_LPBK = 0x0026, 5630 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 5631 FW_PORT_ACTION_PCS_LPBK = 0x0028, 5632 FW_PORT_ACTION_PHY_RESET = 0x0040, 5633 FW_PORT_ACTION_PMA_RESET = 0x0041, 5634 FW_PORT_ACTION_PCS_RESET = 0x0042, 5635 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 5636 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 5637 FW_PORT_ACTION_AN_RESET = 0x0045, 5638 }; 5639 5640 enum fw_port_l2cfg_ctlbf { 5641 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 5642 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 5643 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 5644 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 5645 FW_PORT_L2_CTLBF_IVLAN = 0x10, 5646 FW_PORT_L2_CTLBF_TXIPG = 0x20, 5647 FW_PORT_L2_CTLBF_MTU = 0x40 5648 }; 5649 5650 enum fw_port_dcb_cfg { 5651 FW_PORT_DCB_CFG_PG = 0x01, 5652 FW_PORT_DCB_CFG_PFC = 0x02, 5653 FW_PORT_DCB_CFG_APPL = 0x04 5654 }; 5655 5656 enum fw_port_dcb_cfg_rc { 5657 FW_PORT_DCB_CFG_SUCCESS = 0x0, 5658 FW_PORT_DCB_CFG_ERROR = 0x1 5659 }; 5660 5661 enum fw_port_dcb_type { 5662 FW_PORT_DCB_TYPE_PGID = 0x00, 5663 FW_PORT_DCB_TYPE_PGRATE = 0x01, 5664 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 5665 FW_PORT_DCB_TYPE_PFC = 0x03, 5666 FW_PORT_DCB_TYPE_APP_ID = 0x04, 5667 FW_PORT_DCB_TYPE_CONTROL = 0x04, 5668 }; 5669 5670 enum fw_port_diag_ops { 5671 FW_PORT_DIAGS_TEMP = 0x00, 5672 FW_PORT_DIAGS_TX_POWER = 0x01, 5673 FW_PORT_DIAGS_RX_POWER = 0x02, 5674 }; 5675 5676 struct fw_port_cmd { 5677 __be32 op_to_portid; 5678 __be32 action_to_len16; 5679 union fw_port { 5680 struct fw_port_l1cfg { 5681 __be32 rcap; 5682 __be32 r; 5683 } l1cfg; 5684 struct fw_port_l2cfg { 5685 __u8 ctlbf; 5686 __u8 ovlan3_to_ivlan0; 5687 __be16 ivlantype; 5688 __be16 txipg_force_pinfo; 5689 __be16 mtu; 5690 __be16 ovlan0mask; 5691 __be16 ovlan0type; 5692 __be16 ovlan1mask; 5693 __be16 ovlan1type; 5694 __be16 ovlan2mask; 5695 __be16 ovlan2type; 5696 __be16 ovlan3mask; 5697 __be16 ovlan3type; 5698 } l2cfg; 5699 struct fw_port_info { 5700 __be32 lstatus_to_modtype; 5701 __be16 pcap; 5702 __be16 acap; 5703 __be16 mtu; 5704 __u8 cbllen; 5705 __u8 auxlinfo; 5706 __be32 r8; 5707 __be64 r9; 5708 } info; 5709 struct fw_port_diags { 5710 __u8 diagop; 5711 __u8 r[3]; 5712 __be32 diagval; 5713 } diags; 5714 union fw_port_dcb { 5715 struct fw_port_dcb_pgid { 5716 __u8 type; 5717 __u8 apply_pkd; 5718 __u8 r10_lo[2]; 5719 __be32 pgid; 5720 __be64 r11; 5721 } pgid; 5722 struct fw_port_dcb_pgrate { 5723 __u8 type; 5724 __u8 apply_pkd; 5725 __u8 r10_lo[5]; 5726 __u8 num_tcs_supported; 5727 __u8 pgrate[8]; 5728 } pgrate; 5729 struct fw_port_dcb_priorate { 5730 __u8 type; 5731 __u8 apply_pkd; 5732 __u8 r10_lo[6]; 5733 __u8 strict_priorate[8]; 5734 } priorate; 5735 struct fw_port_dcb_pfc { 5736 __u8 type; 5737 __u8 pfcen; 5738 __be16 r10[3]; 5739 __be64 r11; 5740 } pfc; 5741 struct fw_port_app_priority { 5742 __u8 type; 5743 __u8 r10[2]; 5744 __u8 idx; 5745 __u8 user_prio_map; 5746 __u8 sel_field; 5747 __be16 protocolid; 5748 __be64 r12; 5749 } app_priority; 5750 struct fw_port_dcb_control { 5751 __u8 type; 5752 __u8 all_syncd_pkd; 5753 __be16 r10_lo[3]; 5754 __be64 r11; 5755 } control; 5756 } dcb; 5757 } u; 5758 }; 5759 5760 #define S_FW_PORT_CMD_READ 22 5761 #define M_FW_PORT_CMD_READ 0x1 5762 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 5763 #define G_FW_PORT_CMD_READ(x) \ 5764 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 5765 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 5766 5767 #define S_FW_PORT_CMD_PORTID 0 5768 #define M_FW_PORT_CMD_PORTID 0xf 5769 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 5770 #define G_FW_PORT_CMD_PORTID(x) \ 5771 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 5772 5773 #define S_FW_PORT_CMD_ACTION 16 5774 #define M_FW_PORT_CMD_ACTION 0xffff 5775 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 5776 #define G_FW_PORT_CMD_ACTION(x) \ 5777 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 5778 5779 #define S_FW_PORT_CMD_OVLAN3 7 5780 #define M_FW_PORT_CMD_OVLAN3 0x1 5781 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 5782 #define G_FW_PORT_CMD_OVLAN3(x) \ 5783 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 5784 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 5785 5786 #define S_FW_PORT_CMD_OVLAN2 6 5787 #define M_FW_PORT_CMD_OVLAN2 0x1 5788 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 5789 #define G_FW_PORT_CMD_OVLAN2(x) \ 5790 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 5791 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 5792 5793 #define S_FW_PORT_CMD_OVLAN1 5 5794 #define M_FW_PORT_CMD_OVLAN1 0x1 5795 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 5796 #define G_FW_PORT_CMD_OVLAN1(x) \ 5797 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 5798 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 5799 5800 #define S_FW_PORT_CMD_OVLAN0 4 5801 #define M_FW_PORT_CMD_OVLAN0 0x1 5802 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 5803 #define G_FW_PORT_CMD_OVLAN0(x) \ 5804 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 5805 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 5806 5807 #define S_FW_PORT_CMD_IVLAN0 3 5808 #define M_FW_PORT_CMD_IVLAN0 0x1 5809 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 5810 #define G_FW_PORT_CMD_IVLAN0(x) \ 5811 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 5812 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 5813 5814 #define S_FW_PORT_CMD_TXIPG 3 5815 #define M_FW_PORT_CMD_TXIPG 0x1fff 5816 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 5817 #define G_FW_PORT_CMD_TXIPG(x) \ 5818 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 5819 5820 #define S_FW_PORT_CMD_FORCE_PINFO 0 5821 #define M_FW_PORT_CMD_FORCE_PINFO 0x1 5822 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 5823 #define G_FW_PORT_CMD_FORCE_PINFO(x) \ 5824 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 5825 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 5826 5827 #define S_FW_PORT_CMD_LSTATUS 31 5828 #define M_FW_PORT_CMD_LSTATUS 0x1 5829 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 5830 #define G_FW_PORT_CMD_LSTATUS(x) \ 5831 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 5832 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 5833 5834 #define S_FW_PORT_CMD_LSPEED 24 5835 #define M_FW_PORT_CMD_LSPEED 0x3f 5836 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 5837 #define G_FW_PORT_CMD_LSPEED(x) \ 5838 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 5839 5840 #define S_FW_PORT_CMD_TXPAUSE 23 5841 #define M_FW_PORT_CMD_TXPAUSE 0x1 5842 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 5843 #define G_FW_PORT_CMD_TXPAUSE(x) \ 5844 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 5845 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 5846 5847 #define S_FW_PORT_CMD_RXPAUSE 22 5848 #define M_FW_PORT_CMD_RXPAUSE 0x1 5849 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 5850 #define G_FW_PORT_CMD_RXPAUSE(x) \ 5851 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 5852 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 5853 5854 #define S_FW_PORT_CMD_MDIOCAP 21 5855 #define M_FW_PORT_CMD_MDIOCAP 0x1 5856 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 5857 #define G_FW_PORT_CMD_MDIOCAP(x) \ 5858 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 5859 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 5860 5861 #define S_FW_PORT_CMD_MDIOADDR 16 5862 #define M_FW_PORT_CMD_MDIOADDR 0x1f 5863 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 5864 #define G_FW_PORT_CMD_MDIOADDR(x) \ 5865 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 5866 5867 #define S_FW_PORT_CMD_LPTXPAUSE 15 5868 #define M_FW_PORT_CMD_LPTXPAUSE 0x1 5869 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 5870 #define G_FW_PORT_CMD_LPTXPAUSE(x) \ 5871 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 5872 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 5873 5874 #define S_FW_PORT_CMD_LPRXPAUSE 14 5875 #define M_FW_PORT_CMD_LPRXPAUSE 0x1 5876 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 5877 #define G_FW_PORT_CMD_LPRXPAUSE(x) \ 5878 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 5879 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 5880 5881 #define S_FW_PORT_CMD_PTYPE 8 5882 #define M_FW_PORT_CMD_PTYPE 0x1f 5883 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 5884 #define G_FW_PORT_CMD_PTYPE(x) \ 5885 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 5886 5887 #define S_FW_PORT_CMD_LINKDNRC 5 5888 #define M_FW_PORT_CMD_LINKDNRC 0x7 5889 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 5890 #define G_FW_PORT_CMD_LINKDNRC(x) \ 5891 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 5892 5893 #define S_FW_PORT_CMD_MODTYPE 0 5894 #define M_FW_PORT_CMD_MODTYPE 0x1f 5895 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 5896 #define G_FW_PORT_CMD_MODTYPE(x) \ 5897 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 5898 5899 #define S_FW_PORT_CMD_APPLY 7 5900 #define M_FW_PORT_CMD_APPLY 0x1 5901 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 5902 #define G_FW_PORT_CMD_APPLY(x) \ 5903 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 5904 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 5905 5906 #define S_FW_PORT_CMD_ALL_SYNCD 7 5907 #define M_FW_PORT_CMD_ALL_SYNCD 0x1 5908 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 5909 #define G_FW_PORT_CMD_ALL_SYNCD(x) \ 5910 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 5911 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 5912 5913 /* 5914 * These are configured into the VPD and hence tools that generate 5915 * VPD may use this enumeration. 5916 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 5917 */ 5918 enum fw_port_type { 5919 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 5920 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 5921 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 5922 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */ 5923 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */ 5924 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 5925 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 5926 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 5927 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 5928 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 5929 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 5930 FW_PORT_TYPE_BP_AP = 10, 5931 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 5932 FW_PORT_TYPE_BP4_AP = 11, 5933 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 5934 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 5935 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 5936 FW_PORT_TYPE_BP40_BA = 15, 5937 5938 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 5939 }; 5940 5941 /* 5942 * These are read from module's EEPROM and determined once the module is 5943 * inserted. 5944 */ 5945 enum fw_port_module_type { 5946 FW_PORT_MOD_TYPE_NA = 0x0, 5947 FW_PORT_MOD_TYPE_LR = 0x1, 5948 FW_PORT_MOD_TYPE_SR = 0x2, 5949 FW_PORT_MOD_TYPE_ER = 0x3, 5950 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 5951 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 5952 FW_PORT_MOD_TYPE_LRM = 0x6, 5953 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 5954 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 5955 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 5956 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 5957 }; 5958 5959 /* used by FW and tools may use this to generate VPD */ 5960 enum fw_port_mod_sub_type { 5961 FW_PORT_MOD_SUB_TYPE_NA, 5962 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, 5963 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, 5964 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, 5965 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, 5966 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, 5967 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, 5968 5969 /* 5970 * The following will never been in the VPD. They are TWINAX cable 5971 * lengths decoded from SFP+ module i2c PROMs. These should almost 5972 * certainly go somewhere else ... 5973 */ 5974 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, 5975 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, 5976 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, 5977 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, 5978 }; 5979 5980 /* link down reason codes (3b) */ 5981 enum fw_port_link_dn_rc { 5982 FW_PORT_LINK_DN_RC_NONE, 5983 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 5984 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 5985 FW_PORT_LINK_DN_RESERVED3, 5986 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 5987 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 5988 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 5989 FW_PORT_LINK_DN_RESERVED7 5990 }; 5991 5992 /* port stats */ 5993 #define FW_NUM_PORT_STATS 50 5994 #define FW_NUM_PORT_TX_STATS 23 5995 #define FW_NUM_PORT_RX_STATS 27 5996 5997 enum fw_port_stats_tx_index { 5998 FW_STAT_TX_PORT_BYTES_IX, 5999 FW_STAT_TX_PORT_FRAMES_IX, 6000 FW_STAT_TX_PORT_BCAST_IX, 6001 FW_STAT_TX_PORT_MCAST_IX, 6002 FW_STAT_TX_PORT_UCAST_IX, 6003 FW_STAT_TX_PORT_ERROR_IX, 6004 FW_STAT_TX_PORT_64B_IX, 6005 FW_STAT_TX_PORT_65B_127B_IX, 6006 FW_STAT_TX_PORT_128B_255B_IX, 6007 FW_STAT_TX_PORT_256B_511B_IX, 6008 FW_STAT_TX_PORT_512B_1023B_IX, 6009 FW_STAT_TX_PORT_1024B_1518B_IX, 6010 FW_STAT_TX_PORT_1519B_MAX_IX, 6011 FW_STAT_TX_PORT_DROP_IX, 6012 FW_STAT_TX_PORT_PAUSE_IX, 6013 FW_STAT_TX_PORT_PPP0_IX, 6014 FW_STAT_TX_PORT_PPP1_IX, 6015 FW_STAT_TX_PORT_PPP2_IX, 6016 FW_STAT_TX_PORT_PPP3_IX, 6017 FW_STAT_TX_PORT_PPP4_IX, 6018 FW_STAT_TX_PORT_PPP5_IX, 6019 FW_STAT_TX_PORT_PPP6_IX, 6020 FW_STAT_TX_PORT_PPP7_IX 6021 }; 6022 6023 enum fw_port_stat_rx_index { 6024 FW_STAT_RX_PORT_BYTES_IX, 6025 FW_STAT_RX_PORT_FRAMES_IX, 6026 FW_STAT_RX_PORT_BCAST_IX, 6027 FW_STAT_RX_PORT_MCAST_IX, 6028 FW_STAT_RX_PORT_UCAST_IX, 6029 FW_STAT_RX_PORT_MTU_ERROR_IX, 6030 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 6031 FW_STAT_RX_PORT_CRC_ERROR_IX, 6032 FW_STAT_RX_PORT_LEN_ERROR_IX, 6033 FW_STAT_RX_PORT_SYM_ERROR_IX, 6034 FW_STAT_RX_PORT_64B_IX, 6035 FW_STAT_RX_PORT_65B_127B_IX, 6036 FW_STAT_RX_PORT_128B_255B_IX, 6037 FW_STAT_RX_PORT_256B_511B_IX, 6038 FW_STAT_RX_PORT_512B_1023B_IX, 6039 FW_STAT_RX_PORT_1024B_1518B_IX, 6040 FW_STAT_RX_PORT_1519B_MAX_IX, 6041 FW_STAT_RX_PORT_PAUSE_IX, 6042 FW_STAT_RX_PORT_PPP0_IX, 6043 FW_STAT_RX_PORT_PPP1_IX, 6044 FW_STAT_RX_PORT_PPP2_IX, 6045 FW_STAT_RX_PORT_PPP3_IX, 6046 FW_STAT_RX_PORT_PPP4_IX, 6047 FW_STAT_RX_PORT_PPP5_IX, 6048 FW_STAT_RX_PORT_PPP6_IX, 6049 FW_STAT_RX_PORT_PPP7_IX, 6050 FW_STAT_RX_PORT_LESS_64B_IX 6051 }; 6052 6053 struct fw_port_stats_cmd { 6054 __be32 op_to_portid; 6055 __be32 retval_len16; 6056 union fw_port_stats { 6057 struct fw_port_stats_ctl { 6058 __u8 nstats_bg_bm; 6059 __u8 tx_ix; 6060 __be16 r6; 6061 __be32 r7; 6062 __be64 stat0; 6063 __be64 stat1; 6064 __be64 stat2; 6065 __be64 stat3; 6066 __be64 stat4; 6067 __be64 stat5; 6068 } ctl; 6069 struct fw_port_stats_all { 6070 __be64 tx_bytes; 6071 __be64 tx_frames; 6072 __be64 tx_bcast; 6073 __be64 tx_mcast; 6074 __be64 tx_ucast; 6075 __be64 tx_error; 6076 __be64 tx_64b; 6077 __be64 tx_65b_127b; 6078 __be64 tx_128b_255b; 6079 __be64 tx_256b_511b; 6080 __be64 tx_512b_1023b; 6081 __be64 tx_1024b_1518b; 6082 __be64 tx_1519b_max; 6083 __be64 tx_drop; 6084 __be64 tx_pause; 6085 __be64 tx_ppp0; 6086 __be64 tx_ppp1; 6087 __be64 tx_ppp2; 6088 __be64 tx_ppp3; 6089 __be64 tx_ppp4; 6090 __be64 tx_ppp5; 6091 __be64 tx_ppp6; 6092 __be64 tx_ppp7; 6093 __be64 rx_bytes; 6094 __be64 rx_frames; 6095 __be64 rx_bcast; 6096 __be64 rx_mcast; 6097 __be64 rx_ucast; 6098 __be64 rx_mtu_error; 6099 __be64 rx_mtu_crc_error; 6100 __be64 rx_crc_error; 6101 __be64 rx_len_error; 6102 __be64 rx_sym_error; 6103 __be64 rx_64b; 6104 __be64 rx_65b_127b; 6105 __be64 rx_128b_255b; 6106 __be64 rx_256b_511b; 6107 __be64 rx_512b_1023b; 6108 __be64 rx_1024b_1518b; 6109 __be64 rx_1519b_max; 6110 __be64 rx_pause; 6111 __be64 rx_ppp0; 6112 __be64 rx_ppp1; 6113 __be64 rx_ppp2; 6114 __be64 rx_ppp3; 6115 __be64 rx_ppp4; 6116 __be64 rx_ppp5; 6117 __be64 rx_ppp6; 6118 __be64 rx_ppp7; 6119 __be64 rx_less_64b; 6120 __be64 rx_bg_drop; 6121 __be64 rx_bg_trunc; 6122 } all; 6123 } u; 6124 }; 6125 6126 #define S_FW_PORT_STATS_CMD_NSTATS 4 6127 #define M_FW_PORT_STATS_CMD_NSTATS 0x7 6128 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 6129 #define G_FW_PORT_STATS_CMD_NSTATS(x) \ 6130 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 6131 6132 #define S_FW_PORT_STATS_CMD_BG_BM 0 6133 #define M_FW_PORT_STATS_CMD_BG_BM 0x3 6134 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 6135 #define G_FW_PORT_STATS_CMD_BG_BM(x) \ 6136 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 6137 6138 #define S_FW_PORT_STATS_CMD_TX 7 6139 #define M_FW_PORT_STATS_CMD_TX 0x1 6140 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 6141 #define G_FW_PORT_STATS_CMD_TX(x) \ 6142 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 6143 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 6144 6145 #define S_FW_PORT_STATS_CMD_IX 0 6146 #define M_FW_PORT_STATS_CMD_IX 0x3f 6147 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 6148 #define G_FW_PORT_STATS_CMD_IX(x) \ 6149 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 6150 6151 /* port loopback stats */ 6152 #define FW_NUM_LB_STATS 14 6153 enum fw_port_lb_stats_index { 6154 FW_STAT_LB_PORT_BYTES_IX, 6155 FW_STAT_LB_PORT_FRAMES_IX, 6156 FW_STAT_LB_PORT_BCAST_IX, 6157 FW_STAT_LB_PORT_MCAST_IX, 6158 FW_STAT_LB_PORT_UCAST_IX, 6159 FW_STAT_LB_PORT_ERROR_IX, 6160 FW_STAT_LB_PORT_64B_IX, 6161 FW_STAT_LB_PORT_65B_127B_IX, 6162 FW_STAT_LB_PORT_128B_255B_IX, 6163 FW_STAT_LB_PORT_256B_511B_IX, 6164 FW_STAT_LB_PORT_512B_1023B_IX, 6165 FW_STAT_LB_PORT_1024B_1518B_IX, 6166 FW_STAT_LB_PORT_1519B_MAX_IX, 6167 FW_STAT_LB_PORT_DROP_FRAMES_IX 6168 }; 6169 6170 struct fw_port_lb_stats_cmd { 6171 __be32 op_to_lbport; 6172 __be32 retval_len16; 6173 union fw_port_lb_stats { 6174 struct fw_port_lb_stats_ctl { 6175 __u8 nstats_bg_bm; 6176 __u8 ix_pkd; 6177 __be16 r6; 6178 __be32 r7; 6179 __be64 stat0; 6180 __be64 stat1; 6181 __be64 stat2; 6182 __be64 stat3; 6183 __be64 stat4; 6184 __be64 stat5; 6185 } ctl; 6186 struct fw_port_lb_stats_all { 6187 __be64 tx_bytes; 6188 __be64 tx_frames; 6189 __be64 tx_bcast; 6190 __be64 tx_mcast; 6191 __be64 tx_ucast; 6192 __be64 tx_error; 6193 __be64 tx_64b; 6194 __be64 tx_65b_127b; 6195 __be64 tx_128b_255b; 6196 __be64 tx_256b_511b; 6197 __be64 tx_512b_1023b; 6198 __be64 tx_1024b_1518b; 6199 __be64 tx_1519b_max; 6200 __be64 rx_lb_drop; 6201 __be64 rx_lb_trunc; 6202 } all; 6203 } u; 6204 }; 6205 6206 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 6207 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 6208 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 6209 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 6210 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 6211 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 6212 6213 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 6214 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 6215 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 6216 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 6217 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 6218 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 6219 6220 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 6221 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 6222 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 6223 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 6224 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 6225 6226 #define S_FW_PORT_LB_STATS_CMD_IX 0 6227 #define M_FW_PORT_LB_STATS_CMD_IX 0xf 6228 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 6229 #define G_FW_PORT_LB_STATS_CMD_IX(x) \ 6230 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 6231 6232 /* Trace related defines */ 6233 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 6234 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 6235 6236 struct fw_port_trace_cmd { 6237 __be32 op_to_portid; 6238 __be32 retval_len16; 6239 __be16 traceen_to_pciech; 6240 __be16 qnum; 6241 __be32 r5; 6242 }; 6243 6244 #define S_FW_PORT_TRACE_CMD_PORTID 0 6245 #define M_FW_PORT_TRACE_CMD_PORTID 0xf 6246 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 6247 #define G_FW_PORT_TRACE_CMD_PORTID(x) \ 6248 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 6249 6250 #define S_FW_PORT_TRACE_CMD_TRACEEN 15 6251 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 6252 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 6253 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 6254 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 6255 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 6256 6257 #define S_FW_PORT_TRACE_CMD_FLTMODE 14 6258 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 6259 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 6260 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 6261 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 6262 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 6263 6264 #define S_FW_PORT_TRACE_CMD_DUPLEN 13 6265 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 6266 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 6267 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 6268 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 6269 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 6270 6271 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 6272 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 6273 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 6274 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 6275 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 6276 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 6277 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 6278 6279 #define S_FW_PORT_TRACE_CMD_PCIECH 6 6280 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 6281 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 6282 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 6283 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 6284 6285 struct fw_port_trace_mmap_cmd { 6286 __be32 op_to_portid; 6287 __be32 retval_len16; 6288 __be32 fid_to_skipoffset; 6289 __be32 minpktsize_capturemax; 6290 __u8 map[224]; 6291 }; 6292 6293 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 6294 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 6295 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 6296 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 6297 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 6298 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 6299 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 6300 6301 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 6302 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 6303 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 6304 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 6305 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 6306 6307 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 6308 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 6309 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 6310 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 6311 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 6312 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 6313 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 6314 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 6315 6316 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 6317 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 6318 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 6319 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 6320 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 6321 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 6322 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 6323 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN \ 6324 V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 6325 6326 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 6327 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 6328 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 6329 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 6330 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 6331 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 6332 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 6333 6334 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 6335 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 6336 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 6337 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 6338 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 6339 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 6340 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 6341 6342 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 6343 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 6344 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 6345 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 6346 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 6347 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 6348 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 6349 6350 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 6351 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 6352 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 6353 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 6354 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 6355 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 6356 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 6357 6358 struct fw_rss_ind_tbl_cmd { 6359 __be32 op_to_viid; 6360 __be32 retval_len16; 6361 __be16 niqid; 6362 __be16 startidx; 6363 __be32 r3; 6364 __be32 iq0_to_iq2; 6365 __be32 iq3_to_iq5; 6366 __be32 iq6_to_iq8; 6367 __be32 iq9_to_iq11; 6368 __be32 iq12_to_iq14; 6369 __be32 iq15_to_iq17; 6370 __be32 iq18_to_iq20; 6371 __be32 iq21_to_iq23; 6372 __be32 iq24_to_iq26; 6373 __be32 iq27_to_iq29; 6374 __be32 iq30_iq31; 6375 __be32 r15_lo; 6376 }; 6377 6378 #define S_FW_RSS_IND_TBL_CMD_VIID 0 6379 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 6380 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 6381 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 6382 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 6383 6384 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 6385 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 6386 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 6387 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 6388 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 6389 6390 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 6391 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 6392 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 6393 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 6394 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 6395 6396 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 6397 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 6398 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 6399 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 6400 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 6401 6402 #define S_FW_RSS_IND_TBL_CMD_IQ3 20 6403 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 6404 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 6405 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 6406 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 6407 6408 #define S_FW_RSS_IND_TBL_CMD_IQ4 10 6409 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 6410 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 6411 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 6412 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 6413 6414 #define S_FW_RSS_IND_TBL_CMD_IQ5 0 6415 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 6416 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 6417 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 6418 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 6419 6420 #define S_FW_RSS_IND_TBL_CMD_IQ6 20 6421 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 6422 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 6423 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 6424 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 6425 6426 #define S_FW_RSS_IND_TBL_CMD_IQ7 10 6427 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 6428 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 6429 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 6430 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 6431 6432 #define S_FW_RSS_IND_TBL_CMD_IQ8 0 6433 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 6434 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 6435 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 6436 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 6437 6438 #define S_FW_RSS_IND_TBL_CMD_IQ9 20 6439 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 6440 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 6441 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 6442 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 6443 6444 #define S_FW_RSS_IND_TBL_CMD_IQ10 10 6445 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 6446 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 6447 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 6448 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 6449 6450 #define S_FW_RSS_IND_TBL_CMD_IQ11 0 6451 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 6452 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 6453 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 6454 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 6455 6456 #define S_FW_RSS_IND_TBL_CMD_IQ12 20 6457 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 6458 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 6459 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 6460 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 6461 6462 #define S_FW_RSS_IND_TBL_CMD_IQ13 10 6463 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 6464 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 6465 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 6466 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 6467 6468 #define S_FW_RSS_IND_TBL_CMD_IQ14 0 6469 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 6470 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 6471 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 6472 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 6473 6474 #define S_FW_RSS_IND_TBL_CMD_IQ15 20 6475 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 6476 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 6477 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 6478 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 6479 6480 #define S_FW_RSS_IND_TBL_CMD_IQ16 10 6481 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 6482 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 6483 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 6484 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 6485 6486 #define S_FW_RSS_IND_TBL_CMD_IQ17 0 6487 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 6488 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 6489 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 6490 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 6491 6492 #define S_FW_RSS_IND_TBL_CMD_IQ18 20 6493 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 6494 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 6495 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 6496 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 6497 6498 #define S_FW_RSS_IND_TBL_CMD_IQ19 10 6499 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 6500 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 6501 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 6502 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 6503 6504 #define S_FW_RSS_IND_TBL_CMD_IQ20 0 6505 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 6506 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 6507 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 6508 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 6509 6510 #define S_FW_RSS_IND_TBL_CMD_IQ21 20 6511 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 6512 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 6513 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 6514 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 6515 6516 #define S_FW_RSS_IND_TBL_CMD_IQ22 10 6517 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 6518 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 6519 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 6520 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 6521 6522 #define S_FW_RSS_IND_TBL_CMD_IQ23 0 6523 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 6524 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 6525 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 6526 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 6527 6528 #define S_FW_RSS_IND_TBL_CMD_IQ24 20 6529 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 6530 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 6531 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 6532 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 6533 6534 #define S_FW_RSS_IND_TBL_CMD_IQ25 10 6535 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 6536 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 6537 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 6538 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 6539 6540 #define S_FW_RSS_IND_TBL_CMD_IQ26 0 6541 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 6542 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 6543 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 6544 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 6545 6546 #define S_FW_RSS_IND_TBL_CMD_IQ27 20 6547 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 6548 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 6549 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 6550 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 6551 6552 #define S_FW_RSS_IND_TBL_CMD_IQ28 10 6553 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 6554 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 6555 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 6556 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 6557 6558 #define S_FW_RSS_IND_TBL_CMD_IQ29 0 6559 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 6560 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 6561 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 6562 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 6563 6564 #define S_FW_RSS_IND_TBL_CMD_IQ30 20 6565 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 6566 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 6567 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 6568 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 6569 6570 #define S_FW_RSS_IND_TBL_CMD_IQ31 10 6571 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 6572 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 6573 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 6574 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 6575 6576 struct fw_rss_glb_config_cmd { 6577 __be32 op_to_write; 6578 __be32 retval_len16; 6579 union fw_rss_glb_config { 6580 struct fw_rss_glb_config_manual { 6581 __be32 mode_pkd; 6582 __be32 r3; 6583 __be64 r4; 6584 __be64 r5; 6585 } manual; 6586 struct fw_rss_glb_config_basicvirtual { 6587 __be32 mode_pkd; 6588 __be32 synmapen_to_hashtoeplitz; 6589 __be64 r8; 6590 __be64 r9; 6591 } basicvirtual; 6592 } u; 6593 }; 6594 6595 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 6596 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 6597 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 6598 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 6599 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 6600 6601 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 6602 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 6603 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 6604 6605 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 6606 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 6607 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 6608 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 6609 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 6610 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 6611 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 6612 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN \ 6613 V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 6614 6615 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 6616 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 6617 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 6618 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 6619 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 6620 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 6621 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 6622 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 6623 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 6624 6625 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 6626 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 6627 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 6628 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 6629 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 6630 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 6631 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 6632 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 6633 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 6634 6635 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 6636 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 6637 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 6638 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 6639 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 6640 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 6641 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 6642 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 6643 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 6644 6645 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 6646 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 6647 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 6648 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 6649 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 6650 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 6651 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 6652 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 6653 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 6654 6655 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 6656 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 6657 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 6658 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 6659 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 6660 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 6661 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 6662 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN \ 6663 V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 6664 6665 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 6666 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 6667 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 6668 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 6669 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 6670 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 6671 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 6672 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN \ 6673 V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 6674 6675 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 6676 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 6677 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 6678 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 6679 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 6680 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 6681 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 6682 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 6683 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 6684 6685 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 6686 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 6687 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 6688 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 6689 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 6690 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 6691 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 6692 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 6693 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 6694 6695 struct fw_rss_vi_config_cmd { 6696 __be32 op_to_viid; 6697 __be32 retval_len16; 6698 union fw_rss_vi_config { 6699 struct fw_rss_vi_config_manual { 6700 __be64 r3; 6701 __be64 r4; 6702 __be64 r5; 6703 } manual; 6704 struct fw_rss_vi_config_basicvirtual { 6705 __be32 r6; 6706 __be32 defaultq_to_udpen; 6707 __be64 r9; 6708 __be64 r10; 6709 } basicvirtual; 6710 } u; 6711 }; 6712 6713 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 6714 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 6715 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 6716 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 6717 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 6718 6719 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 6720 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 6721 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 6722 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 6723 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 6724 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 6725 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 6726 6727 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 6728 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 6729 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 6730 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6731 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 6732 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 6733 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6734 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 6735 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 6736 6737 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 6738 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 6739 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 6740 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6741 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 6742 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 6743 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6744 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 6745 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 6746 6747 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 6748 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 6749 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 6750 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6751 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 6752 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 6753 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6754 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 6755 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 6756 6757 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 6758 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 6759 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 6760 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6761 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 6762 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 6763 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6764 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 6765 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 6766 6767 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 6768 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 6769 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 6770 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 6771 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 6772 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 6773 6774 enum fw_sched_sc { 6775 FW_SCHED_SC_CONFIG = 0, 6776 FW_SCHED_SC_PARAMS = 1, 6777 }; 6778 6779 enum fw_sched_type { 6780 FW_SCHED_TYPE_PKTSCHED = 0, 6781 FW_SCHED_TYPE_STREAMSCHED = 1, 6782 }; 6783 6784 enum fw_sched_params_level { 6785 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 6786 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 6787 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 6788 }; 6789 6790 enum fw_sched_params_mode { 6791 FW_SCHED_PARAMS_MODE_CLASS = 0, 6792 FW_SCHED_PARAMS_MODE_FLOW = 1, 6793 }; 6794 6795 enum fw_sched_params_unit { 6796 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 6797 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 6798 }; 6799 6800 enum fw_sched_params_rate { 6801 FW_SCHED_PARAMS_RATE_REL = 0, 6802 FW_SCHED_PARAMS_RATE_ABS = 1, 6803 }; 6804 6805 struct fw_sched_cmd { 6806 __be32 op_to_write; 6807 __be32 retval_len16; 6808 union fw_sched { 6809 struct fw_sched_config { 6810 __u8 sc; 6811 __u8 type; 6812 __u8 minmaxen; 6813 __u8 r3[5]; 6814 __u8 nclasses[4]; 6815 __be32 r4; 6816 } config; 6817 struct fw_sched_params { 6818 __u8 sc; 6819 __u8 type; 6820 __u8 level; 6821 __u8 mode; 6822 __u8 unit; 6823 __u8 rate; 6824 __u8 ch; 6825 __u8 cl; 6826 __be32 min; 6827 __be32 max; 6828 __be16 weight; 6829 __be16 pktsize; 6830 __be16 burstsize; 6831 __be16 r4; 6832 } params; 6833 } u; 6834 }; 6835 6836 /* 6837 * length of the formatting string 6838 */ 6839 #define FW_DEVLOG_FMT_LEN 192 6840 6841 /* 6842 * maximum number of the formatting string parameters 6843 */ 6844 #define FW_DEVLOG_FMT_PARAMS_NUM 8 6845 6846 /* 6847 * priority levels 6848 */ 6849 enum fw_devlog_level { 6850 FW_DEVLOG_LEVEL_EMERG = 0x0, 6851 FW_DEVLOG_LEVEL_CRIT = 0x1, 6852 FW_DEVLOG_LEVEL_ERR = 0x2, 6853 FW_DEVLOG_LEVEL_NOTICE = 0x3, 6854 FW_DEVLOG_LEVEL_INFO = 0x4, 6855 FW_DEVLOG_LEVEL_DEBUG = 0x5, 6856 FW_DEVLOG_LEVEL_MAX = 0x5, 6857 }; 6858 6859 /* 6860 * facilities that may send a log message 6861 */ 6862 enum fw_devlog_facility { 6863 FW_DEVLOG_FACILITY_CORE = 0x00, 6864 FW_DEVLOG_FACILITY_CF = 0x01, 6865 FW_DEVLOG_FACILITY_SCHED = 0x02, 6866 FW_DEVLOG_FACILITY_TIMER = 0x04, 6867 FW_DEVLOG_FACILITY_RES = 0x06, 6868 FW_DEVLOG_FACILITY_HW = 0x08, 6869 FW_DEVLOG_FACILITY_FLR = 0x10, 6870 FW_DEVLOG_FACILITY_DMAQ = 0x12, 6871 FW_DEVLOG_FACILITY_PHY = 0x14, 6872 FW_DEVLOG_FACILITY_MAC = 0x16, 6873 FW_DEVLOG_FACILITY_PORT = 0x18, 6874 FW_DEVLOG_FACILITY_VI = 0x1A, 6875 FW_DEVLOG_FACILITY_FILTER = 0x1C, 6876 FW_DEVLOG_FACILITY_ACL = 0x1E, 6877 FW_DEVLOG_FACILITY_TM = 0x20, 6878 FW_DEVLOG_FACILITY_QFC = 0x22, 6879 FW_DEVLOG_FACILITY_DCB = 0x24, 6880 FW_DEVLOG_FACILITY_ETH = 0x26, 6881 FW_DEVLOG_FACILITY_OFLD = 0x28, 6882 FW_DEVLOG_FACILITY_RI = 0x2A, 6883 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 6884 FW_DEVLOG_FACILITY_FCOE = 0x2E, 6885 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 6886 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 6887 FW_DEVLOG_FACILITY_MAX = 0x32, 6888 }; 6889 6890 /* 6891 * log message format 6892 */ 6893 struct fw_devlog_e { 6894 __be64 timestamp; 6895 __be32 seqno; 6896 __be16 reserved1; 6897 __u8 level; 6898 __u8 facility; 6899 __u8 fmt[FW_DEVLOG_FMT_LEN]; 6900 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 6901 __be32 reserved3[4]; 6902 }; 6903 6904 struct fw_devlog_cmd { 6905 __be32 op_to_write; 6906 __be32 retval_len16; 6907 __u8 level; 6908 __u8 r2[7]; 6909 __be32 memtype_devlog_memaddr16_devlog; 6910 __be32 memsize_devlog; 6911 __be32 r3[2]; 6912 }; 6913 6914 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 6915 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 6916 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 6917 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 6918 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 6919 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & \ 6920 M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 6921 6922 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 6923 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 6924 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 6925 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 6926 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 6927 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 6928 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 6929 6930 enum fw_watchdog_actions { 6931 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 6932 FW_WATCHDOG_ACTION_FLR = 1, 6933 FW_WATCHDOG_ACTION_BYPASS = 2, 6934 FW_WATCHDOG_ACTION_TMPCHK = 3, 6935 6936 FW_WATCHDOG_ACTION_MAX = 4, 6937 }; 6938 6939 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 6940 6941 struct fw_watchdog_cmd { 6942 __be32 op_to_vfn; 6943 __be32 retval_len16; 6944 __be32 timeout; 6945 __be32 action; 6946 }; 6947 6948 #define S_FW_WATCHDOG_CMD_PFN 8 6949 #define M_FW_WATCHDOG_CMD_PFN 0x7 6950 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 6951 #define G_FW_WATCHDOG_CMD_PFN(x) \ 6952 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 6953 6954 #define S_FW_WATCHDOG_CMD_VFN 0 6955 #define M_FW_WATCHDOG_CMD_VFN 0xff 6956 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 6957 #define G_FW_WATCHDOG_CMD_VFN(x) \ 6958 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 6959 6960 struct fw_clip_cmd { 6961 __be32 op_to_write; 6962 __be32 alloc_to_len16; 6963 __be64 ip_hi; 6964 __be64 ip_lo; 6965 __be32 r4[2]; 6966 }; 6967 6968 #define S_FW_CLIP_CMD_ALLOC 31 6969 #define M_FW_CLIP_CMD_ALLOC 0x1 6970 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 6971 #define G_FW_CLIP_CMD_ALLOC(x) \ 6972 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 6973 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 6974 6975 #define S_FW_CLIP_CMD_FREE 30 6976 #define M_FW_CLIP_CMD_FREE 0x1 6977 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 6978 #define G_FW_CLIP_CMD_FREE(x) \ 6979 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 6980 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 6981 6982 /* 6983 * ************************************ 6984 * F O i S C S I C O M M A N D s 6985 * ************************************ 6986 */ 6987 6988 #define FW_CHNET_IFACE_ADDR_MAX 3 6989 6990 enum fw_chnet_iface_cmd_subop { 6991 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 6992 6993 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 6994 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 6995 6996 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 6997 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 6998 6999 FW_CHNET_IFACE_CMD_SUBOP_MAX, 7000 }; 7001 7002 struct fw_chnet_iface_cmd { 7003 __be32 op_to_portid; 7004 __be32 retval_len16; 7005 __u8 subop; 7006 __u8 r2[3]; 7007 __be32 ifid_ifstate; 7008 __be16 mtu; 7009 __be16 vlanid; 7010 __be32 r3; 7011 __be16 r4; 7012 __u8 mac[6]; 7013 }; 7014 7015 #define S_FW_CHNET_IFACE_CMD_PORTID 0 7016 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf 7017 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 7018 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 7019 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 7020 7021 #define S_FW_CHNET_IFACE_CMD_IFID 8 7022 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 7023 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 7024 #define G_FW_CHNET_IFACE_CMD_IFID(x) \ 7025 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 7026 7027 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0 7028 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 7029 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 7030 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 7031 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 7032 7033 /* 7034 * ********************************** 7035 * F O F C O E C O M M A N D s 7036 * ********************************** 7037 */ 7038 7039 struct fw_fcoe_res_info_cmd { 7040 __be32 op_to_read; 7041 __be32 retval_len16; 7042 __be16 e_d_tov; 7043 __be16 r_a_tov_seq; 7044 __be16 r_a_tov_els; 7045 __be16 r_r_tov; 7046 __be32 max_xchgs; 7047 __be32 max_ssns; 7048 __be32 used_xchgs; 7049 __be32 used_ssns; 7050 __be32 max_fcfs; 7051 __be32 max_vnps; 7052 __be32 used_fcfs; 7053 __be32 used_vnps; 7054 }; 7055 7056 struct fw_fcoe_link_cmd { 7057 __be32 op_to_portid; 7058 __be32 retval_len16; 7059 __be32 sub_opcode_fcfi; 7060 __u8 r3; 7061 __u8 lstatus; 7062 __be16 flags; 7063 __u8 r4; 7064 __u8 set_vlan; 7065 __be16 vlan_id; 7066 __be32 vnpi_pkd; 7067 __be16 r6; 7068 __u8 phy_mac[6]; 7069 __u8 vnport_wwnn[8]; 7070 __u8 vnport_wwpn[8]; 7071 }; 7072 7073 #define S_FW_FCOE_LINK_CMD_PORTID 0 7074 #define M_FW_FCOE_LINK_CMD_PORTID 0xf 7075 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 7076 #define G_FW_FCOE_LINK_CMD_PORTID(x) \ 7077 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 7078 7079 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 7080 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 7081 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 7082 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 7083 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 7084 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 7085 7086 #define S_FW_FCOE_LINK_CMD_FCFI 0 7087 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 7088 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 7089 #define G_FW_FCOE_LINK_CMD_FCFI(x) \ 7090 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 7091 7092 #define S_FW_FCOE_LINK_CMD_VNPI 0 7093 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 7094 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 7095 #define G_FW_FCOE_LINK_CMD_VNPI(x) \ 7096 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 7097 7098 struct fw_fcoe_vnp_cmd { 7099 __be32 op_to_fcfi; 7100 __be32 alloc_to_len16; 7101 __be32 gen_wwn_to_vnpi; 7102 __be32 vf_id; 7103 __be16 iqid; 7104 __u8 vnport_mac[6]; 7105 __u8 vnport_wwnn[8]; 7106 __u8 vnport_wwpn[8]; 7107 __u8 cmn_srv_parms[16]; 7108 __u8 clsp_word_0_1[8]; 7109 }; 7110 7111 #define S_FW_FCOE_VNP_CMD_FCFI 0 7112 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 7113 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 7114 #define G_FW_FCOE_VNP_CMD_FCFI(x) \ 7115 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 7116 7117 #define S_FW_FCOE_VNP_CMD_ALLOC 31 7118 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1 7119 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 7120 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 7121 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 7122 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 7123 7124 #define S_FW_FCOE_VNP_CMD_FREE 30 7125 #define M_FW_FCOE_VNP_CMD_FREE 0x1 7126 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 7127 #define G_FW_FCOE_VNP_CMD_FREE(x) \ 7128 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 7129 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 7130 7131 #define S_FW_FCOE_VNP_CMD_MODIFY 29 7132 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 7133 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 7134 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 7135 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 7136 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 7137 7138 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22 7139 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 7140 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 7141 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 7142 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 7143 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 7144 7145 #define S_FW_FCOE_VNP_CMD_PERSIST 21 7146 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1 7147 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 7148 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 7149 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 7150 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 7151 7152 #define S_FW_FCOE_VNP_CMD_VFID_EN 20 7153 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 7154 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 7155 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 7156 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 7157 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 7158 7159 #define S_FW_FCOE_VNP_CMD_VNPI 0 7160 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 7161 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 7162 #define G_FW_FCOE_VNP_CMD_VNPI(x) \ 7163 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 7164 7165 struct fw_fcoe_sparams_cmd { 7166 __be32 op_to_portid; 7167 __be32 retval_len16; 7168 __u8 r3[7]; 7169 __u8 cos; 7170 __u8 lport_wwnn[8]; 7171 __u8 lport_wwpn[8]; 7172 __u8 cmn_srv_parms[16]; 7173 __u8 cls_srv_parms[16]; 7174 }; 7175 7176 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0 7177 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 7178 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 7179 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 7180 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 7181 7182 struct fw_fcoe_stats_cmd { 7183 __be32 op_to_flowid; 7184 __be32 free_to_len16; 7185 union fw_fcoe_stats { 7186 struct fw_fcoe_stats_ctl { 7187 __u8 nstats_port; 7188 __u8 port_valid_ix; 7189 __be16 r6; 7190 __be32 r7; 7191 __be64 stat0; 7192 __be64 stat1; 7193 __be64 stat2; 7194 __be64 stat3; 7195 __be64 stat4; 7196 __be64 stat5; 7197 } ctl; 7198 struct fw_fcoe_port_stats { 7199 __be64 tx_bcast_bytes; 7200 __be64 tx_bcast_frames; 7201 __be64 tx_mcast_bytes; 7202 __be64 tx_mcast_frames; 7203 __be64 tx_ucast_bytes; 7204 __be64 tx_ucast_frames; 7205 __be64 tx_drop_frames; 7206 __be64 tx_offload_bytes; 7207 __be64 tx_offload_frames; 7208 __be64 rx_bcast_bytes; 7209 __be64 rx_bcast_frames; 7210 __be64 rx_mcast_bytes; 7211 __be64 rx_mcast_frames; 7212 __be64 rx_ucast_bytes; 7213 __be64 rx_ucast_frames; 7214 __be64 rx_err_frames; 7215 } port_stats; 7216 struct fw_fcoe_fcf_stats { 7217 __be32 fip_tx_bytes; 7218 __be32 fip_tx_fr; 7219 __be64 fcf_ka; 7220 __be64 mcast_adv_rcvd; 7221 __be16 ucast_adv_rcvd; 7222 __be16 sol_sent; 7223 __be16 vlan_req; 7224 __be16 vlan_rpl; 7225 __be16 clr_vlink; 7226 __be16 link_down; 7227 __be16 link_up; 7228 __be16 logo; 7229 __be16 flogi_req; 7230 __be16 flogi_rpl; 7231 __be16 fdisc_req; 7232 __be16 fdisc_rpl; 7233 __be16 fka_prd_chg; 7234 __be16 fc_map_chg; 7235 __be16 vfid_chg; 7236 __u8 no_fka_req; 7237 __u8 no_vnp; 7238 } fcf_stats; 7239 struct fw_fcoe_pcb_stats { 7240 __be64 tx_bytes; 7241 __be64 tx_frames; 7242 __be64 rx_bytes; 7243 __be64 rx_frames; 7244 __be32 vnp_ka; 7245 __be32 unsol_els_rcvd; 7246 __be64 unsol_cmd_rcvd; 7247 __be16 implicit_logo; 7248 __be16 flogi_inv_sparm; 7249 __be16 fdisc_inv_sparm; 7250 __be16 flogi_rjt; 7251 __be16 fdisc_rjt; 7252 __be16 no_ssn; 7253 __be16 mac_flt_fail; 7254 __be16 inv_fr_rcvd; 7255 } pcb_stats; 7256 struct fw_fcoe_scb_stats { 7257 __be64 tx_bytes; 7258 __be64 tx_frames; 7259 __be64 rx_bytes; 7260 __be64 rx_frames; 7261 __be32 host_abrt_req; 7262 __be32 adap_auto_abrt; 7263 __be32 adap_abrt_rsp; 7264 __be32 host_ios_req; 7265 __be16 ssn_offl_ios; 7266 __be16 ssn_not_rdy_ios; 7267 __u8 rx_data_ddp_err; 7268 __u8 ddp_flt_set_err; 7269 __be16 rx_data_fr_err; 7270 __u8 bad_st_abrt_req; 7271 __u8 no_io_abrt_req; 7272 __u8 abort_tmo; 7273 __u8 abort_tmo_2; 7274 __be32 abort_req; 7275 __u8 no_ppod_res_tmo; 7276 __u8 bp_tmo; 7277 __u8 adap_auto_cls; 7278 __u8 no_io_cls_req; 7279 __be32 host_cls_req; 7280 __be64 unsol_cmd_rcvd; 7281 __be32 plogi_req_rcvd; 7282 __be32 prli_req_rcvd; 7283 __be16 logo_req_rcvd; 7284 __be16 prlo_req_rcvd; 7285 __be16 plogi_rjt_rcvd; 7286 __be16 prli_rjt_rcvd; 7287 __be32 adisc_req_rcvd; 7288 __be32 rscn_rcvd; 7289 __be32 rrq_req_rcvd; 7290 __be32 unsol_els_rcvd; 7291 __u8 adisc_rjt_rcvd; 7292 __u8 scr_rjt; 7293 __u8 ct_rjt; 7294 __u8 inval_bls_rcvd; 7295 __be32 ba_rjt_rcvd; 7296 } scb_stats; 7297 } u; 7298 }; 7299 7300 #define S_FW_FCOE_STATS_CMD_FLOWID 0 7301 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 7302 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 7303 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 7304 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 7305 7306 #define S_FW_FCOE_STATS_CMD_FREE 30 7307 #define M_FW_FCOE_STATS_CMD_FREE 0x1 7308 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 7309 #define G_FW_FCOE_STATS_CMD_FREE(x) \ 7310 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 7311 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 7312 7313 #define S_FW_FCOE_STATS_CMD_NSTATS 4 7314 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7 7315 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 7316 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 7317 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 7318 7319 #define S_FW_FCOE_STATS_CMD_PORT 0 7320 #define M_FW_FCOE_STATS_CMD_PORT 0x3 7321 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 7322 #define G_FW_FCOE_STATS_CMD_PORT(x) \ 7323 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 7324 7325 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7 7326 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 7327 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 7328 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 7329 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 7330 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & \ 7331 M_FW_FCOE_STATS_CMD_PORT_VALID) 7332 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 7333 7334 #define S_FW_FCOE_STATS_CMD_IX 0 7335 #define M_FW_FCOE_STATS_CMD_IX 0x3f 7336 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 7337 #define G_FW_FCOE_STATS_CMD_IX(x) \ 7338 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 7339 7340 struct fw_fcoe_fcf_cmd { 7341 __be32 op_to_fcfi; 7342 __be32 retval_len16; 7343 __be16 priority_pkd; 7344 __u8 mac[6]; 7345 __u8 name_id[8]; 7346 __u8 fabric[8]; 7347 __be16 vf_id; 7348 __be16 max_fcoe_size; 7349 __u8 vlan_id; 7350 __u8 fc_map[3]; 7351 __be32 fka_adv; 7352 __be32 r6; 7353 __u8 r7_hi; 7354 __u8 fpma_to_portid; 7355 __u8 spma_mac[6]; 7356 __be64 r8; 7357 }; 7358 7359 #define S_FW_FCOE_FCF_CMD_FCFI 0 7360 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 7361 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 7362 #define G_FW_FCOE_FCF_CMD_FCFI(x) \ 7363 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 7364 7365 #define S_FW_FCOE_FCF_CMD_PRIORITY 0 7366 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 7367 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 7368 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 7369 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 7370 7371 #define S_FW_FCOE_FCF_CMD_FPMA 6 7372 #define M_FW_FCOE_FCF_CMD_FPMA 0x1 7373 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 7374 #define G_FW_FCOE_FCF_CMD_FPMA(x) \ 7375 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 7376 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 7377 7378 #define S_FW_FCOE_FCF_CMD_SPMA 5 7379 #define M_FW_FCOE_FCF_CMD_SPMA 0x1 7380 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 7381 #define G_FW_FCOE_FCF_CMD_SPMA(x) \ 7382 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 7383 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 7384 7385 #define S_FW_FCOE_FCF_CMD_LOGIN 4 7386 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 7387 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 7388 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 7389 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 7390 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 7391 7392 #define S_FW_FCOE_FCF_CMD_PORTID 0 7393 #define M_FW_FCOE_FCF_CMD_PORTID 0xf 7394 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 7395 #define G_FW_FCOE_FCF_CMD_PORTID(x) \ 7396 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 7397 7398 /* 7399 * **************************************************** 7400 * E R R O R a n d D E B U G C O M M A N D s 7401 * **************************************************** 7402 */ 7403 7404 enum fw_error_type { 7405 FW_ERROR_TYPE_EXCEPTION = 0x0, 7406 FW_ERROR_TYPE_HWMODULE = 0x1, 7407 FW_ERROR_TYPE_WR = 0x2, 7408 FW_ERROR_TYPE_ACL = 0x3, 7409 }; 7410 7411 struct fw_error_cmd { 7412 __be32 op_to_type; 7413 __be32 len16_pkd; 7414 union fw_error { 7415 struct fw_error_exception { 7416 __be32 info[6]; 7417 } exception; 7418 struct fw_error_hwmodule { 7419 __be32 regaddr; 7420 __be32 regval; 7421 } hwmodule; 7422 struct fw_error_wr { 7423 __be16 cidx; 7424 __be16 pfn_vfn; 7425 __be32 eqid; 7426 __u8 wrhdr[16]; 7427 } wr; 7428 struct fw_error_acl { 7429 __be16 cidx; 7430 __be16 pfn_vfn; 7431 __be32 eqid; 7432 __be16 mv_pkd; 7433 __u8 val[6]; 7434 __be64 r4; 7435 } acl; 7436 } u; 7437 }; 7438 7439 #define S_FW_ERROR_CMD_FATAL 4 7440 #define M_FW_ERROR_CMD_FATAL 0x1 7441 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 7442 #define G_FW_ERROR_CMD_FATAL(x) \ 7443 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 7444 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 7445 7446 #define S_FW_ERROR_CMD_TYPE 0 7447 #define M_FW_ERROR_CMD_TYPE 0xf 7448 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 7449 #define G_FW_ERROR_CMD_TYPE(x) \ 7450 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 7451 7452 #define S_FW_ERROR_CMD_PFN 8 7453 #define M_FW_ERROR_CMD_PFN 0x7 7454 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 7455 #define G_FW_ERROR_CMD_PFN(x) \ 7456 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 7457 7458 #define S_FW_ERROR_CMD_VFN 0 7459 #define M_FW_ERROR_CMD_VFN 0xff 7460 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 7461 #define G_FW_ERROR_CMD_VFN(x) \ 7462 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 7463 7464 #define S_FW_ERROR_CMD_PFN 8 7465 #define M_FW_ERROR_CMD_PFN 0x7 7466 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 7467 #define G_FW_ERROR_CMD_PFN(x) \ 7468 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 7469 7470 #define S_FW_ERROR_CMD_VFN 0 7471 #define M_FW_ERROR_CMD_VFN 0xff 7472 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 7473 #define G_FW_ERROR_CMD_VFN(x) \ 7474 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 7475 7476 #define S_FW_ERROR_CMD_MV 15 7477 #define M_FW_ERROR_CMD_MV 0x1 7478 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 7479 #define G_FW_ERROR_CMD_MV(x) \ 7480 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 7481 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 7482 7483 struct fw_debug_cmd { 7484 __be32 op_type; 7485 __be32 len16_pkd; 7486 union fw_debug { 7487 struct fw_debug_assert { 7488 __be32 fcid; 7489 __be32 line; 7490 __be32 x; 7491 __be32 y; 7492 __u8 filename_0_7[8]; 7493 __u8 filename_8_15[8]; 7494 __be64 r3; 7495 } assert; 7496 struct fw_debug_prt { 7497 __be16 dprtstridx; 7498 __be16 r3[3]; 7499 __be32 dprtstrparam0; 7500 __be32 dprtstrparam1; 7501 __be32 dprtstrparam2; 7502 __be32 dprtstrparam3; 7503 } prt; 7504 } u; 7505 }; 7506 7507 #define S_FW_DEBUG_CMD_TYPE 0 7508 #define M_FW_DEBUG_CMD_TYPE 0xff 7509 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 7510 #define G_FW_DEBUG_CMD_TYPE(x) \ 7511 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 7512 7513 /* 7514 * ************************************ 7515 * P C I E F W R E G I S T E R 7516 * ************************************ 7517 */ 7518 7519 enum pcie_fw_eval { 7520 PCIE_FW_EVAL_CRASH = 0, 7521 PCIE_FW_EVAL_PREP = 1, 7522 PCIE_FW_EVAL_CONF = 2, 7523 PCIE_FW_EVAL_INIT = 3, 7524 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 7525 PCIE_FW_EVAL_OVERHEAT = 5, 7526 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 7527 }; 7528 7529 /* 7530 * Register definitions for the PCIE_FW register which the firmware uses 7531 * to retain status across RESETs. This register should be considered 7532 * as a READ-ONLY register for Host Software and only to be used to 7533 * track firmware initialization/error state, etc. 7534 */ 7535 #define S_PCIE_FW_ERR 31 7536 #define M_PCIE_FW_ERR 0x1 7537 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 7538 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 7539 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 7540 7541 #define S_PCIE_FW_INIT 30 7542 #define M_PCIE_FW_INIT 0x1 7543 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 7544 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 7545 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 7546 7547 #define S_PCIE_FW_HALT 29 7548 #define M_PCIE_FW_HALT 0x1 7549 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 7550 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 7551 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 7552 7553 #define S_PCIE_FW_EVAL 24 7554 #define M_PCIE_FW_EVAL 0x7 7555 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 7556 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 7557 7558 #define S_PCIE_FW_STAGE 21 7559 #define M_PCIE_FW_STAGE 0x7 7560 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 7561 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 7562 7563 #define S_PCIE_FW_ASYNCNOT_VLD 20 7564 #define M_PCIE_FW_ASYNCNOT_VLD 0x1 7565 #define V_PCIE_FW_ASYNCNOT_VLD(x) \ 7566 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 7567 #define G_PCIE_FW_ASYNCNOT_VLD(x) \ 7568 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 7569 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 7570 7571 #define S_PCIE_FW_ASYNCNOTINT 19 7572 #define M_PCIE_FW_ASYNCNOTINT 0x1 7573 #define V_PCIE_FW_ASYNCNOTINT(x) \ 7574 ((x) << S_PCIE_FW_ASYNCNOTINT) 7575 #define G_PCIE_FW_ASYNCNOTINT(x) \ 7576 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 7577 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 7578 7579 #define S_PCIE_FW_ASYNCNOT 16 7580 #define M_PCIE_FW_ASYNCNOT 0x7 7581 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 7582 #define G_PCIE_FW_ASYNCNOT(x) \ 7583 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 7584 7585 #define S_PCIE_FW_MASTER_VLD 15 7586 #define M_PCIE_FW_MASTER_VLD 0x1 7587 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 7588 #define G_PCIE_FW_MASTER_VLD(x) \ 7589 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 7590 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 7591 7592 #define S_PCIE_FW_MASTER 12 7593 #define M_PCIE_FW_MASTER 0x7 7594 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 7595 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 7596 7597 #define S_PCIE_FW_RESET_VLD 11 7598 #define M_PCIE_FW_RESET_VLD 0x1 7599 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 7600 #define G_PCIE_FW_RESET_VLD(x) \ 7601 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 7602 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 7603 7604 #define S_PCIE_FW_RESET 8 7605 #define M_PCIE_FW_RESET 0x7 7606 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 7607 #define G_PCIE_FW_RESET(x) \ 7608 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 7609 7610 #define S_PCIE_FW_REGISTERED 0 7611 #define M_PCIE_FW_REGISTERED 0xff 7612 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 7613 #define G_PCIE_FW_REGISTERED(x) \ 7614 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 7615 7616 /* 7617 * ******************************************** 7618 * B I N A R Y H E A D E R F O R M A T 7619 * ******************************************** 7620 */ 7621 7622 /* 7623 * firmware binary header format 7624 */ 7625 struct fw_hdr { 7626 __u8 ver; 7627 __u8 chip; /* terminator chip family */ 7628 __be16 len512; /* bin length in units of 512-bytes */ 7629 __be32 fw_ver; /* firmware version */ 7630 __be32 tp_microcode_ver; /* tcp processor microcode version */ 7631 __u8 intfver_nic; 7632 __u8 intfver_vnic; 7633 __u8 intfver_ofld; 7634 __u8 intfver_ri; 7635 __u8 intfver_iscsipdu; 7636 __u8 intfver_iscsi; 7637 __u8 intfver_fcoepdu; 7638 __u8 intfver_fcoe; 7639 __u32 reserved2; 7640 __u32 reserved3; 7641 __u32 magic; /* runtime or bootstrap fw */ 7642 __be32 flags; 7643 __be32 reserved6[23]; 7644 }; 7645 7646 enum fw_hdr_chip { 7647 FW_HDR_CHIP_T4, 7648 FW_HDR_CHIP_T5 7649 }; 7650 7651 #define S_FW_HDR_FW_VER_MAJOR 24 7652 #define M_FW_HDR_FW_VER_MAJOR 0xff 7653 #define V_FW_HDR_FW_VER_MAJOR(x) \ 7654 ((x) << S_FW_HDR_FW_VER_MAJOR) 7655 #define G_FW_HDR_FW_VER_MAJOR(x) \ 7656 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 7657 7658 #define S_FW_HDR_FW_VER_MINOR 16 7659 #define M_FW_HDR_FW_VER_MINOR 0xff 7660 #define V_FW_HDR_FW_VER_MINOR(x) \ 7661 ((x) << S_FW_HDR_FW_VER_MINOR) 7662 #define G_FW_HDR_FW_VER_MINOR(x) \ 7663 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 7664 7665 #define S_FW_HDR_FW_VER_MICRO 8 7666 #define M_FW_HDR_FW_VER_MICRO 0xff 7667 #define V_FW_HDR_FW_VER_MICRO(x) \ 7668 ((x) << S_FW_HDR_FW_VER_MICRO) 7669 #define G_FW_HDR_FW_VER_MICRO(x) \ 7670 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 7671 7672 #define S_FW_HDR_FW_VER_BUILD 0 7673 #define M_FW_HDR_FW_VER_BUILD 0xff 7674 #define V_FW_HDR_FW_VER_BUILD(x) \ 7675 ((x) << S_FW_HDR_FW_VER_BUILD) 7676 #define G_FW_HDR_FW_VER_BUILD(x) \ 7677 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 7678 7679 enum { 7680 T4FW_VERSION_MAJOR = 0x01, 7681 T4FW_VERSION_MINOR = 0x08, 7682 T4FW_VERSION_MICRO = 0x18, 7683 T4FW_VERSION_BUILD = 0x00, 7684 7685 T5FW_VERSION_MAJOR = 0x01, 7686 T5FW_VERSION_MINOR = 0x08, 7687 T5FW_VERSION_MICRO = 0x1b, 7688 T5FW_VERSION_BUILD = 0x00, 7689 }; 7690 7691 enum { 7692 T4FW_HDR_INTFVER_NIC = 0x00, 7693 T4FW_HDR_INTFVER_VNIC = 0x00, 7694 T4FW_HDR_INTFVER_OFLD = 0x00, 7695 T4FW_HDR_INTFVER_RI = 0x00, 7696 T4FW_HDR_INTFVER_ISCSIPDU = 0x00, 7697 T4FW_HDR_INTFVER_ISCSI = 0x00, 7698 T4FW_HDR_INTFVER_FCOEPDU = 0x00, 7699 T4FW_HDR_INTFVER_FCOE = 0x00, 7700 7701 T5FW_HDR_INTFVER_NIC = 0x00, 7702 T5FW_HDR_INTFVER_VNIC = 0x00, 7703 T5FW_HDR_INTFVER_OFLD = 0x00, 7704 T5FW_HDR_INTFVER_RI = 0x00, 7705 T5FW_HDR_INTFVER_ISCSIPDU = 0x00, 7706 T5FW_HDR_INTFVER_ISCSI = 0x00, 7707 T5FW_HDR_INTFVER_FCOEPDU = 0x00, 7708 T5FW_HDR_INTFVER_FCOE = 0x00, 7709 }; 7710 7711 enum { 7712 FW_HDR_MAGIC_RUNTIME = 0x00000000, 7713 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 7714 }; 7715 7716 enum fw_hdr_flags { 7717 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 7718 }; 7719 7720 #endif /* _T4FW_INTERFACE_H_ */ 7721