xref: /illumos-gate/usr/src/uts/common/io/cxgbe/common/t4_regs.h (revision a629ded1d7b2e67c2028ccbc5ba9099328cc4e1b)

/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source. A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/* This file is automatically generated --- changes will be lost */
/* Generation Date : Thu Feb 16 10:13:37 IST 2017 */
/* Directory name: t4_reg.txt, Changeset:  */
/* Directory name: t5_reg.txt, Changeset: 6939:9fe6306ea018 */
/* Directory name: t6_reg.txt, Changeset: 4259:6bffc83b6848 */

#define MYPF_BASE 0x1b000
#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))

#define PF0_BASE 0x1e000
#define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))

#define PF1_BASE 0x1e400
#define PF1_REG(reg_addr) (PF1_BASE + (reg_addr))

#define PF2_BASE 0x1e800
#define PF2_REG(reg_addr) (PF2_BASE + (reg_addr))

#define PF3_BASE 0x1ec00
#define PF3_REG(reg_addr) (PF3_BASE + (reg_addr))

#define PF4_BASE 0x1f000
#define PF4_REG(reg_addr) (PF4_BASE + (reg_addr))

#define PF5_BASE 0x1f400
#define PF5_REG(reg_addr) (PF5_BASE + (reg_addr))

#define PF6_BASE 0x1f800
#define PF6_REG(reg_addr) (PF6_BASE + (reg_addr))

#define PF7_BASE 0x1fc00
#define PF7_REG(reg_addr) (PF7_BASE + (reg_addr))

#define PF_STRIDE 0x400
#define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
#define PF_REG(idx, reg) (PF_BASE(idx) + (reg))

#define VF_SGE_BASE 0x0
#define VF_SGE_REG(reg_addr) (VF_SGE_BASE + (reg_addr))

#define VF_MPS_BASE 0x100
#define VF_MPS_REG(reg_addr) (VF_MPS_BASE + (reg_addr))

#define VF_PL_BASE 0x200
#define VF_PL_REG(reg_addr) (VF_PL_BASE + (reg_addr))

#define VF_MBDATA_BASE 0x240
#define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr))

#define VF_CIM_BASE 0x300
#define VF_CIM_REG(reg_addr) (VF_CIM_BASE + (reg_addr))

#define MYPORT_BASE 0x1c000
#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))

#define PORT0_BASE 0x20000
#define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))

#define PORT1_BASE 0x22000
#define PORT1_REG(reg_addr) (PORT1_BASE + (reg_addr))

#define PORT2_BASE 0x24000
#define PORT2_REG(reg_addr) (PORT2_BASE + (reg_addr))

#define PORT3_BASE 0x26000
#define PORT3_REG(reg_addr) (PORT3_BASE + (reg_addr))

#define PORT_STRIDE 0x2000
#define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
#define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))

#define SGE_QUEUE_BASE_MAP_HIGH(idx) (A_SGE_QUEUE_BASE_MAP_HIGH + (idx) * 8)
#define NUM_SGE_QUEUE_BASE_MAP_HIGH_INSTANCES 136

#define SGE_QUEUE_BASE_MAP_LOW(idx) (A_SGE_QUEUE_BASE_MAP_LOW + (idx) * 8)
#define NUM_SGE_QUEUE_BASE_MAP_LOW_INSTANCES 136

#define PCIE_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
#define NUM_PCIE_DMA_INSTANCES 4

#define PCIE_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
#define NUM_PCIE_CMD_INSTANCES 2

#define PCIE_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
#define NUM_PCIE_HMA_INSTANCES 1

#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
#define NUM_PCIE_MEM_ACCESS_INSTANCES 8

#define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
#define NUM_PCIE_MAILBOX_INSTANCES 1

#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_PCIE_FW_INSTANCES 8

#define PCIE_FUNC_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
#define NUM_PCIE_FUNC_INSTANCES 256

#define PCIE_FID(idx) (A_PCIE_FID + (idx) * 4)
#define NUM_PCIE_FID_INSTANCES 2048

#define PCIE_DMA_BUF_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
#define NUM_PCIE_DMA_BUF_INSTANCES 4

#define MC_DDR3PHYDATX8_REG(reg_addr, idx) ((reg_addr) + (idx) * 256)
#define NUM_MC_DDR3PHYDATX8_INSTANCES 9

#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_MC_BIST_STATUS_INSTANCES 18

#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_EDC_BIST_STATUS_INSTANCES 18

#define CIM_PF_MAILBOX_DATA(idx) (A_CIM_PF_MAILBOX_DATA + (idx) * 4)
#define NUM_CIM_PF_MAILBOX_DATA_INSTANCES 16

#define MPS_TRC_FILTER_MATCH_CTL_A(idx) (A_MPS_TRC_FILTER_MATCH_CTL_A + (idx) * 4)
#define NUM_MPS_TRC_FILTER_MATCH_CTL_A_INSTANCES 4

#define MPS_TRC_FILTER_MATCH_CTL_B(idx) (A_MPS_TRC_FILTER_MATCH_CTL_B + (idx) * 4)
#define NUM_MPS_TRC_FILTER_MATCH_CTL_B_INSTANCES 4

#define MPS_TRC_FILTER_RUNT_CTL(idx) (A_MPS_TRC_FILTER_RUNT_CTL + (idx) * 4)
#define NUM_MPS_TRC_FILTER_RUNT_CTL_INSTANCES 4

#define MPS_TRC_FILTER_DROP(idx) (A_MPS_TRC_FILTER_DROP + (idx) * 4)
#define NUM_MPS_TRC_FILTER_DROP_INSTANCES 4

#define MPS_TRC_FILTER0_MATCH(idx) (A_MPS_TRC_FILTER0_MATCH + (idx) * 4)
#define NUM_MPS_TRC_FILTER0_MATCH_INSTANCES 28

#define MPS_TRC_FILTER0_DONT_CARE(idx) (A_MPS_TRC_FILTER0_DONT_CARE + (idx) * 4)
#define NUM_MPS_TRC_FILTER0_DONT_CARE_INSTANCES 28

#define MPS_TRC_FILTER1_MATCH(idx) (A_MPS_TRC_FILTER1_MATCH + (idx) * 4)
#define NUM_MPS_TRC_FILTER1_MATCH_INSTANCES 28

#define MPS_TRC_FILTER1_DONT_CARE(idx) (A_MPS_TRC_FILTER1_DONT_CARE + (idx) * 4)
#define NUM_MPS_TRC_FILTER1_DONT_CARE_INSTANCES 28

#define MPS_TRC_FILTER2_MATCH(idx) (A_MPS_TRC_FILTER2_MATCH + (idx) * 4)
#define NUM_MPS_TRC_FILTER2_MATCH_INSTANCES 28

#define MPS_TRC_FILTER2_DONT_CARE(idx) (A_MPS_TRC_FILTER2_DONT_CARE + (idx) * 4)
#define NUM_MPS_TRC_FILTER2_DONT_CARE_INSTANCES 28

#define MPS_TRC_FILTER3_MATCH(idx) (A_MPS_TRC_FILTER3_MATCH + (idx) * 4)
#define NUM_MPS_TRC_FILTER3_MATCH_INSTANCES 28

#define MPS_TRC_FILTER3_DONT_CARE(idx) (A_MPS_TRC_FILTER3_DONT_CARE + (idx) * 4)
#define NUM_MPS_TRC_FILTER3_DONT_CARE_INSTANCES 28

#define MPS_PORT_CLS_HASH_SRAM(idx) (A_MPS_PORT_CLS_HASH_SRAM + (idx) * 4)
#define NUM_MPS_PORT_CLS_HASH_SRAM_INSTANCES 65

#define MPS_CLS_VLAN_TABLE(idx) (A_MPS_CLS_VLAN_TABLE + (idx) * 4)
#define NUM_MPS_CLS_VLAN_TABLE_INSTANCES 9

#define MPS_CLS_SRAM_L(idx) (A_MPS_CLS_SRAM_L + (idx) * 8)
#define NUM_MPS_CLS_SRAM_L_INSTANCES 336

#define MPS_CLS_SRAM_H(idx) (A_MPS_CLS_SRAM_H + (idx) * 8)
#define NUM_MPS_CLS_SRAM_H_INSTANCES 336

#define MPS_CLS_TCAM_Y_L(idx) (A_MPS_CLS_TCAM_Y_L + (idx) * 16)
#define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512

#define MPS_CLS_TCAM_Y_H(idx) (A_MPS_CLS_TCAM_Y_H + (idx) * 16)
#define NUM_MPS_CLS_TCAM_Y_H_INSTANCES 512

#define MPS_CLS_TCAM_X_L(idx) (A_MPS_CLS_TCAM_X_L + (idx) * 16)
#define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512

#define MPS_CLS_TCAM_X_H(idx) (A_MPS_CLS_TCAM_X_H + (idx) * 16)
#define NUM_MPS_CLS_TCAM_X_H_INSTANCES 512

#define PL_SEMAPHORE_LOCK(idx) (A_PL_SEMAPHORE_LOCK + (idx) * 4)
#define NUM_PL_SEMAPHORE_LOCK_INSTANCES 8

#define PL_VF_SLICE_L(idx) (A_PL_VF_SLICE_L + (idx) * 8)
#define NUM_PL_VF_SLICE_L_INSTANCES 8

#define PL_VF_SLICE_H(idx) (A_PL_VF_SLICE_H + (idx) * 8)
#define NUM_PL_VF_SLICE_H_INSTANCES 8

#define PL_FLR_VF_STATUS(idx) (A_PL_FLR_VF_STATUS + (idx) * 4)
#define NUM_PL_FLR_VF_STATUS_INSTANCES 4

#define PL_VFID_MAP(idx) (A_PL_VFID_MAP + (idx) * 4)
#define NUM_PL_VFID_MAP_INSTANCES 256

#define LE_DB_MASK_IPV4(idx) (A_LE_DB_MASK_IPV4 + (idx) * 4)
#define NUM_LE_DB_MASK_IPV4_INSTANCES 17

#define LE_DB_MASK_IPV6(idx) (A_LE_DB_MASK_IPV6 + (idx) * 4)
#define NUM_LE_DB_MASK_IPV6_INSTANCES 17

#define LE_DB_DBGI_REQ_DATA(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
#define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 17

#define LE_DB_DBGI_REQ_MASK(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
#define NUM_LE_DB_DBGI_REQ_MASK_INSTANCES 17

#define LE_DB_DBGI_RSP_DATA(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4)
#define NUM_LE_DB_DBGI_RSP_DATA_INSTANCES 17

#define LE_DB_ACTIVE_MASK_IPV4(idx) (A_LE_DB_ACTIVE_MASK_IPV4 + (idx) * 4)
#define NUM_LE_DB_ACTIVE_MASK_IPV4_INSTANCES 17

#define LE_DB_ACTIVE_MASK_IPV6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
#define NUM_LE_DB_ACTIVE_MASK_IPV6_INSTANCES 17

#define LE_HASH_MASK_GEN_IPV4(idx) (A_LE_HASH_MASK_GEN_IPV4 + (idx) * 4)
#define NUM_LE_HASH_MASK_GEN_IPV4_INSTANCES 4

#define LE_HASH_MASK_GEN_IPV6(idx) (A_LE_HASH_MASK_GEN_IPV6 + (idx) * 4)
#define NUM_LE_HASH_MASK_GEN_IPV6_INSTANCES 12

#define LE_HASH_MASK_CMP_IPV4(idx) (A_LE_HASH_MASK_CMP_IPV4 + (idx) * 4)
#define NUM_LE_HASH_MASK_CMP_IPV4_INSTANCES 4

#define LE_HASH_MASK_CMP_IPV6(idx) (A_LE_HASH_MASK_CMP_IPV6 + (idx) * 4)
#define NUM_LE_HASH_MASK_CMP_IPV6_INSTANCES 12

#define UP_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
#define NUM_UP_TSCH_CHANNEL_INSTANCES 4

#define CIM_CTL_MAILBOX_VF_STATUS(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
#define NUM_CIM_CTL_MAILBOX_VF_STATUS_INSTANCES 4

#define CIM_CTL_MAILBOX_VFN_CTL(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 16)
#define NUM_CIM_CTL_MAILBOX_VFN_CTL_INSTANCES 128

#define CIM_CTL_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 288)
#define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 4

#define CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
#define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16

#define T5_MYPORT_BASE 0x2c000
#define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr))

#define T5_PORT0_BASE 0x30000
#define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr))

#define T5_PORT1_BASE 0x34000
#define T5_PORT1_REG(reg_addr) (T5_PORT1_BASE + (reg_addr))

#define T5_PORT2_BASE 0x38000
#define T5_PORT2_REG(reg_addr) (T5_PORT2_BASE + (reg_addr))

#define T5_PORT3_BASE 0x3c000
#define T5_PORT3_REG(reg_addr) (T5_PORT3_BASE + (reg_addr))

#define T5_PORT_STRIDE 0x4000
#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))

#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
#define MC_REG(reg, idx) (reg + MC_STRIDE * idx)

#define PCIE_PF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
#define NUM_PCIE_PF_INT_INSTANCES 8

#define PCIE_VF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
#define NUM_PCIE_VF_INT_INSTANCES 128

#define PCIE_FID_VFID(idx) (A_PCIE_FID_VFID + (idx) * 4)
#define NUM_PCIE_FID_VFID_INSTANCES 2048

#define PCIE_COOKIE_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_PCIE_COOKIE_INSTANCES 8

#define PCIE_T5_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
#define NUM_PCIE_T5_DMA_INSTANCES 4

#define PCIE_T5_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
#define NUM_PCIE_T5_CMD_INSTANCES 3

#define PCIE_T5_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
#define NUM_PCIE_T5_HMA_INSTANCES 1

#define PCIE_PHY_PRESET_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_PCIE_PHY_PRESET_INSTANCES 11

#define MPS_T5_CLS_SRAM_L(idx) (A_MPS_T5_CLS_SRAM_L + (idx) * 8)
#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512

#define MPS_T5_CLS_SRAM_H(idx) (A_MPS_T5_CLS_SRAM_H + (idx) * 8)
#define NUM_MPS_T5_CLS_SRAM_H_INSTANCES 512

#define LE_T5_DB_MASK_IPV4(idx) (A_LE_T5_DB_MASK_IPV4 + (idx) * 4)
#define NUM_LE_T5_DB_MASK_IPV4_INSTANCES 5

#define LE_T5_DB_ACTIVE_MASK_IPV4(idx) (A_LE_T5_DB_ACTIVE_MASK_IPV4 + (idx) * 4)
#define NUM_LE_T5_DB_ACTIVE_MASK_IPV4_INSTANCES 5

#define LE_HASH_MASK_GEN_IPV4T5(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
#define NUM_LE_HASH_MASK_GEN_IPV4T5_INSTANCES 5

#define LE_HASH_MASK_GEN_IPV6T5(idx) (A_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
#define NUM_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 12

#define LE_HASH_MASK_CMP_IPV4T5(idx) (A_LE_HASH_MASK_CMP_IPV4T5 + (idx) * 4)
#define NUM_LE_HASH_MASK_CMP_IPV4T5_INSTANCES 5

#define LE_HASH_MASK_CMP_IPV6T5(idx) (A_LE_HASH_MASK_CMP_IPV6T5 + (idx) * 4)
#define NUM_LE_HASH_MASK_CMP_IPV6T5_INSTANCES 12

#define LE_DB_SECOND_ACTIVE_MASK_IPV4(idx) (A_LE_DB_SECOND_ACTIVE_MASK_IPV4 + (idx) * 4)
#define NUM_LE_DB_SECOND_ACTIVE_MASK_IPV4_INSTANCES 5

#define LE_DB_SECOND_GEN_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
#define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_INSTANCES 5

#define LE_DB_SECOND_CMP_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 + (idx) * 4)
#define NUM_LE_DB_SECOND_CMP_HASH_MASK_IPV4_INSTANCES 5

#define MC_ADR_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
#define NUM_MC_ADR_INSTANCES 2

#define MC_DDRPHY_DP18_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
#define NUM_MC_DDRPHY_DP18_INSTANCES 5

#define MC_CE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_MC_CE_ERR_DATA_INSTANCES 8

#define MC_CE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_MC_CE_COR_DATA_INSTANCES 8

#define MC_UE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_MC_UE_ERR_DATA_INSTANCES 8

#define MC_UE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_MC_UE_COR_DATA_INSTANCES 8

#define MC_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_MC_P_BIST_STATUS_INSTANCES 18

#define EDC_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_EDC_H_BIST_STATUS_INSTANCES 18

#define EDC_H_ECC_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_EDC_H_ECC_ERR_DATA_INSTANCES 16

#define SGE_DEBUG1_DBP_THREAD(idx) (A_SGE_DEBUG1_DBP_THREAD + (idx) * 4)
#define NUM_SGE_DEBUG1_DBP_THREAD_INSTANCES 4

#define SGE_DEBUG0_DBP_THREAD(idx) (A_SGE_DEBUG0_DBP_THREAD + (idx) * 4)
#define NUM_SGE_DEBUG0_DBP_THREAD_INSTANCES 5

#define SGE_WC_EGRS_BAR2_OFF_PF(idx) (A_SGE_WC_EGRS_BAR2_OFF_PF + (idx) * 4)
#define NUM_SGE_WC_EGRS_BAR2_OFF_PF_INSTANCES 8

#define SGE_WC_EGRS_BAR2_OFF_VF(idx) (A_SGE_WC_EGRS_BAR2_OFF_VF + (idx) * 4)
#define NUM_SGE_WC_EGRS_BAR2_OFF_VF_INSTANCES 8

#define PCIE_T6_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
#define NUM_PCIE_T6_DMA_INSTANCES 2

#define PCIE_T6_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
#define NUM_PCIE_T6_CMD_INSTANCES 1

#define PCIE_VF_256_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_PCIE_VF_256_INT_INSTANCES 128

#define MPS_CLS_REQUEST_TRACE_MAC_DA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_L + (idx) * 32)
#define NUM_MPS_CLS_REQUEST_TRACE_MAC_DA_L_INSTANCES 8

#define MPS_CLS_REQUEST_TRACE_MAC_DA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_H + (idx) * 32)
#define NUM_MPS_CLS_REQUEST_TRACE_MAC_DA_H_INSTANCES 8

#define MPS_CLS_REQUEST_TRACE_MAC_SA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_L + (idx) * 32)
#define NUM_MPS_CLS_REQUEST_TRACE_MAC_SA_L_INSTANCES 8

#define MPS_CLS_REQUEST_TRACE_MAC_SA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_H + (idx) * 32)
#define NUM_MPS_CLS_REQUEST_TRACE_MAC_SA_H_INSTANCES 8

#define MPS_CLS_REQUEST_TRACE_PORT_VLAN(idx) (A_MPS_CLS_REQUEST_TRACE_PORT_VLAN + (idx) * 32)
#define NUM_MPS_CLS_REQUEST_TRACE_PORT_VLAN_INSTANCES 8

#define MPS_CLS_REQUEST_TRACE_ENCAP(idx) (A_MPS_CLS_REQUEST_TRACE_ENCAP + (idx) * 32)
#define NUM_MPS_CLS_REQUEST_TRACE_ENCAP_INSTANCES 8

#define MPS_CLS_RESULT_TRACE(idx) (A_MPS_CLS_RESULT_TRACE + (idx) * 4)
#define NUM_MPS_CLS_RESULT_TRACE_INSTANCES 8

#define MPS_CLS_DIPIPV4_ID_TABLE(idx) (A_MPS_CLS_DIPIPV4_ID_TABLE + (idx) * 8)
#define NUM_MPS_CLS_DIPIPV4_ID_TABLE_INSTANCES 4

#define MPS_CLS_DIPIPV4_MASK_TABLE(idx) (A_MPS_CLS_DIPIPV4_MASK_TABLE + (idx) * 8)
#define NUM_MPS_CLS_DIPIPV4_MASK_TABLE_INSTANCES 4

#define MPS_CLS_DIPIPV6ID_0_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_0_TABLE + (idx) * 32)
#define NUM_MPS_CLS_DIPIPV6ID_0_TABLE_INSTANCES 2

#define MPS_CLS_DIPIPV6ID_1_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_1_TABLE + (idx) * 32)
#define NUM_MPS_CLS_DIPIPV6ID_1_TABLE_INSTANCES 2

#define MPS_CLS_DIPIPV6ID_2_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_2_TABLE + (idx) * 32)
#define NUM_MPS_CLS_DIPIPV6ID_2_TABLE_INSTANCES 2

#define MPS_CLS_DIPIPV6ID_3_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_3_TABLE + (idx) * 32)
#define NUM_MPS_CLS_DIPIPV6ID_3_TABLE_INSTANCES 2

#define MPS_CLS_DIPIPV6MASK_0_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_0_TABLE + (idx) * 32)
#define NUM_MPS_CLS_DIPIPV6MASK_0_TABLE_INSTANCES 2

#define MPS_CLS_DIPIPV6MASK_1_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_1_TABLE + (idx) * 32)
#define NUM_MPS_CLS_DIPIPV6MASK_1_TABLE_INSTANCES 2

#define MPS_CLS_DIPIPV6MASK_2_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_2_TABLE + (idx) * 32)
#define NUM_MPS_CLS_DIPIPV6MASK_2_TABLE_INSTANCES 2

#define MPS_CLS_DIPIPV6MASK_3_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_3_TABLE + (idx) * 32)
#define NUM_MPS_CLS_DIPIPV6MASK_3_TABLE_INSTANCES 2

#define MPS_RX_HASH_LKP_TABLE(idx) (A_MPS_RX_HASH_LKP_TABLE + (idx) * 4)
#define NUM_MPS_RX_HASH_LKP_TABLE_INSTANCES 4

#define LE_DB_DBG_MATCH_DATA_MASK(idx) (A_LE_DB_DBG_MATCH_DATA_MASK + (idx) * 4)
#define NUM_LE_DB_DBG_MATCH_DATA_MASK_INSTANCES 8

#define LE_DB_DBG_MATCH_DATA(idx) (A_LE_DB_DBG_MATCH_DATA + (idx) * 4)
#define NUM_LE_DB_DBG_MATCH_DATA_INSTANCES 8

#define LE_DB_DBGI_REQ_DATA_T6(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
#define NUM_LE_DB_DBGI_REQ_DATA_T6_INSTANCES 11

#define LE_DB_DBGI_REQ_MASK_T6(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
#define NUM_LE_DB_DBGI_REQ_MASK_T6_INSTANCES 11

#define LE_DB_DBGI_RSP_DATA_T6(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4)
#define NUM_LE_DB_DBGI_RSP_DATA_T6_INSTANCES 11

#define LE_DB_ACTIVE_MASK_IPV6_T6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
#define NUM_LE_DB_ACTIVE_MASK_IPV6_T6_INSTANCES 8

#define LE_HASH_MASK_GEN_IPV4T6(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
#define NUM_LE_HASH_MASK_GEN_IPV4T6_INSTANCES 8

#define T6_LE_HASH_MASK_GEN_IPV6T5(idx) (A_T6_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
#define NUM_T6_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 8

#define LE_DB_PSV_FILTER_MASK_TUP_IPV4(idx) (A_LE_DB_PSV_FILTER_MASK_TUP_IPV4 + (idx) * 4)
#define NUM_LE_DB_PSV_FILTER_MASK_TUP_IPV4_INSTANCES 3

#define LE_DB_PSV_FILTER_MASK_FLT_IPV4(idx) (A_LE_DB_PSV_FILTER_MASK_FLT_IPV4 + (idx) * 4)
#define NUM_LE_DB_PSV_FILTER_MASK_FLT_IPV4_INSTANCES 2

#define LE_DB_PSV_FILTER_MASK_TUP_IPV6(idx) (A_LE_DB_PSV_FILTER_MASK_TUP_IPV6 + (idx) * 4)
#define NUM_LE_DB_PSV_FILTER_MASK_TUP_IPV6_INSTANCES 9

#define LE_DB_PSV_FILTER_MASK_FLT_IPV6(idx) (A_LE_DB_PSV_FILTER_MASK_FLT_IPV6 + (idx) * 4)
#define NUM_LE_DB_PSV_FILTER_MASK_FLT_IPV6_INSTANCES 2

#define LE_DB_SECOND_GEN_HASH_MASK_IPV4_T6(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
#define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_T6_INSTANCES 8

#define MC_DDRPHY_DP18_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
#define NUM_MC_DDRPHY_DP18_T6_INSTANCES 9

#define MC_CE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_MC_CE_ERR_DATA_T6_INSTANCES 16

#define MC_UE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_MC_UE_ERR_DATA_T6_INSTANCES 16

#define CIM_CTL_MAILBOX_VF_STATUS_T6(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
#define NUM_CIM_CTL_MAILBOX_VF_STATUS_T6_INSTANCES 8

#define CIM_CTL_MAILBOX_VFN_CTL_T6(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 4)
#define NUM_CIM_CTL_MAILBOX_VFN_CTL_T6_INSTANCES 256

#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)

#define EDC_T5_STRIDE (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
#define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx)

/* registers for module SGE */
#define SGE_BASE_ADDR 0x1000

#define A_SGE_PF_KDOORBELL 0x0

#define S_QID    15
#define M_QID    0x1ffffU
#define V_QID(x) ((x) << S_QID)
#define G_QID(x) (((x) >> S_QID) & M_QID)

#define S_DBPRIO    14
#define V_DBPRIO(x) ((x) << S_DBPRIO)
#define F_DBPRIO    V_DBPRIO(1U)

#define S_PIDX    0
#define M_PIDX    0x3fffU
#define V_PIDX(x) ((x) << S_PIDX)
#define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX)

#define A_SGE_VF_KDOORBELL 0x0

#define S_DBTYPE    13
#define V_DBTYPE(x) ((x) << S_DBTYPE)
#define F_DBTYPE    V_DBTYPE(1U)

#define S_PIDX_T5    0
#define M_PIDX_T5    0x1fffU
#define V_PIDX_T5(x) ((x) << S_PIDX_T5)
#define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)

#define S_SYNC_T6    14
#define V_SYNC_T6(x) ((x) << S_SYNC_T6)
#define F_SYNC_T6    V_SYNC_T6(1U)

#define A_SGE_PF_GTS 0x4

#define S_INGRESSQID    16
#define M_INGRESSQID    0xffffU
#define V_INGRESSQID(x) ((x) << S_INGRESSQID)
#define G_INGRESSQID(x) (((x) >> S_INGRESSQID) & M_INGRESSQID)

#define S_TIMERREG    13
#define M_TIMERREG    0x7U
#define V_TIMERREG(x) ((x) << S_TIMERREG)
#define G_TIMERREG(x) (((x) >> S_TIMERREG) & M_TIMERREG)

#define S_SEINTARM    12
#define V_SEINTARM(x) ((x) << S_SEINTARM)
#define F_SEINTARM    V_SEINTARM(1U)

#define S_CIDXINC    0
#define M_CIDXINC    0xfffU
#define V_CIDXINC(x) ((x) << S_CIDXINC)
#define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC)

#define A_SGE_VF_GTS 0x4
#define A_SGE_PF_KTIMESTAMP_LO 0x8
#define A_SGE_VF_KTIMESTAMP_LO 0x8
#define A_SGE_PF_KTIMESTAMP_HI 0xc

#define S_TSTAMPVAL    0
#define M_TSTAMPVAL    0xfffffffU
#define V_TSTAMPVAL(x) ((x) << S_TSTAMPVAL)
#define G_TSTAMPVAL(x) (((x) >> S_TSTAMPVAL) & M_TSTAMPVAL)

#define A_SGE_VF_KTIMESTAMP_HI 0xc
#define A_SGE_CONTROL 0x1008

#define S_FLSPLITMODE    20
#define M_FLSPLITMODE    0x3U
#define V_FLSPLITMODE(x) ((x) << S_FLSPLITMODE)
#define G_FLSPLITMODE(x) (((x) >> S_FLSPLITMODE) & M_FLSPLITMODE)

#define S_RXPKTCPLMODE    18
#define V_RXPKTCPLMODE(x) ((x) << S_RXPKTCPLMODE)
#define F_RXPKTCPLMODE    V_RXPKTCPLMODE(1U)

#define S_EGRSTATUSPAGESIZE    17
#define V_EGRSTATUSPAGESIZE(x) ((x) << S_EGRSTATUSPAGESIZE)
#define F_EGRSTATUSPAGESIZE    V_EGRSTATUSPAGESIZE(1U)

#define S_PKTSHIFT    10
#define M_PKTSHIFT    0x7U
#define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
#define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)

#define S_INGPADBOUNDARY    4
#define M_INGPADBOUNDARY    0x7U
#define V_INGPADBOUNDARY(x) ((x) << S_INGPADBOUNDARY)
#define G_INGPADBOUNDARY(x) (((x) >> S_INGPADBOUNDARY) & M_INGPADBOUNDARY)

#define S_GLOBALENABLE    0
#define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
#define F_GLOBALENABLE    V_GLOBALENABLE(1U)

#define S_IGRALLCPLTOFL    31
#define V_IGRALLCPLTOFL(x) ((x) << S_IGRALLCPLTOFL)
#define F_IGRALLCPLTOFL    V_IGRALLCPLTOFL(1U)

#define S_FLSPLITMIN    22
#define M_FLSPLITMIN    0x1ffU
#define V_FLSPLITMIN(x) ((x) << S_FLSPLITMIN)
#define G_FLSPLITMIN(x) (((x) >> S_FLSPLITMIN) & M_FLSPLITMIN)

#define S_INGHINTENABLE1    15
#define V_INGHINTENABLE1(x) ((x) << S_INGHINTENABLE1)
#define F_INGHINTENABLE1    V_INGHINTENABLE1(1U)

#define S_INGHINTENABLE0    14
#define V_INGHINTENABLE0(x) ((x) << S_INGHINTENABLE0)
#define F_INGHINTENABLE0    V_INGHINTENABLE0(1U)

#define S_INGINTCOMPAREIDX    13
#define V_INGINTCOMPAREIDX(x) ((x) << S_INGINTCOMPAREIDX)
#define F_INGINTCOMPAREIDX    V_INGINTCOMPAREIDX(1U)

#define S_INGPCIEBOUNDARY    7
#define M_INGPCIEBOUNDARY    0x7U
#define V_INGPCIEBOUNDARY(x) ((x) << S_INGPCIEBOUNDARY)
#define G_INGPCIEBOUNDARY(x) (((x) >> S_INGPCIEBOUNDARY) & M_INGPCIEBOUNDARY)

#define A_SGE_HOST_PAGE_SIZE 0x100c

#define S_HOSTPAGESIZEPF7    28
#define M_HOSTPAGESIZEPF7    0xfU
#define V_HOSTPAGESIZEPF7(x) ((x) << S_HOSTPAGESIZEPF7)
#define G_HOSTPAGESIZEPF7(x) (((x) >> S_HOSTPAGESIZEPF7) & M_HOSTPAGESIZEPF7)

#define S_HOSTPAGESIZEPF6    24
#define M_HOSTPAGESIZEPF6    0xfU
#define V_HOSTPAGESIZEPF6(x) ((x) << S_HOSTPAGESIZEPF6)
#define G_HOSTPAGESIZEPF6(x) (((x) >> S_HOSTPAGESIZEPF6) & M_HOSTPAGESIZEPF6)

#define S_HOSTPAGESIZEPF5    20
#define M_HOSTPAGESIZEPF5    0xfU
#define V_HOSTPAGESIZEPF5(x) ((x) << S_HOSTPAGESIZEPF5)
#define G_HOSTPAGESIZEPF5(x) (((x) >> S_HOSTPAGESIZEPF5) & M_HOSTPAGESIZEPF5)

#define S_HOSTPAGESIZEPF4    16
#define M_HOSTPAGESIZEPF4    0xfU
#define V_HOSTPAGESIZEPF4(x) ((x) << S_HOSTPAGESIZEPF4)
#define G_HOSTPAGESIZEPF4(x) (((x) >> S_HOSTPAGESIZEPF4) & M_HOSTPAGESIZEPF4)

#define S_HOSTPAGESIZEPF3    12
#define M_HOSTPAGESIZEPF3    0xfU
#define V_HOSTPAGESIZEPF3(x) ((x) << S_HOSTPAGESIZEPF3)
#define G_HOSTPAGESIZEPF3(x) (((x) >> S_HOSTPAGESIZEPF3) & M_HOSTPAGESIZEPF3)

#define S_HOSTPAGESIZEPF2    8
#define M_HOSTPAGESIZEPF2    0xfU
#define V_HOSTPAGESIZEPF2(x) ((x) << S_HOSTPAGESIZEPF2)
#define G_HOSTPAGESIZEPF2(x) (((x) >> S_HOSTPAGESIZEPF2) & M_HOSTPAGESIZEPF2)

#define S_HOSTPAGESIZEPF1    4
#define M_HOSTPAGESIZEPF1    0xfU
#define V_HOSTPAGESIZEPF1(x) ((x) << S_HOSTPAGESIZEPF1)
#define G_HOSTPAGESIZEPF1(x) (((x) >> S_HOSTPAGESIZEPF1) & M_HOSTPAGESIZEPF1)

#define S_HOSTPAGESIZEPF0    0
#define M_HOSTPAGESIZEPF0    0xfU
#define V_HOSTPAGESIZEPF0(x) ((x) << S_HOSTPAGESIZEPF0)
#define G_HOSTPAGESIZEPF0(x) (((x) >> S_HOSTPAGESIZEPF0) & M_HOSTPAGESIZEPF0)

#define A_SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010

#define S_QUEUESPERPAGEPF7    28
#define M_QUEUESPERPAGEPF7    0xfU
#define V_QUEUESPERPAGEPF7(x) ((x) << S_QUEUESPERPAGEPF7)
#define G_QUEUESPERPAGEPF7(x) (((x) >> S_QUEUESPERPAGEPF7) & M_QUEUESPERPAGEPF7)

#define S_QUEUESPERPAGEPF6    24
#define M_QUEUESPERPAGEPF6    0xfU
#define V_QUEUESPERPAGEPF6(x) ((x) << S_QUEUESPERPAGEPF6)
#define G_QUEUESPERPAGEPF6(x) (((x) >> S_QUEUESPERPAGEPF6) & M_QUEUESPERPAGEPF6)

#define S_QUEUESPERPAGEPF5    20
#define M_QUEUESPERPAGEPF5    0xfU
#define V_QUEUESPERPAGEPF5(x) ((x) << S_QUEUESPERPAGEPF5)
#define G_QUEUESPERPAGEPF5(x) (((x) >> S_QUEUESPERPAGEPF5) & M_QUEUESPERPAGEPF5)

#define S_QUEUESPERPAGEPF4    16
#define M_QUEUESPERPAGEPF4    0xfU
#define V_QUEUESPERPAGEPF4(x) ((x) << S_QUEUESPERPAGEPF4)
#define G_QUEUESPERPAGEPF4(x) (((x) >> S_QUEUESPERPAGEPF4) & M_QUEUESPERPAGEPF4)

#define S_QUEUESPERPAGEPF3    12
#define M_QUEUESPERPAGEPF3    0xfU
#define V_QUEUESPERPAGEPF3(x) ((x) << S_QUEUESPERPAGEPF3)
#define G_QUEUESPERPAGEPF3(x) (((x) >> S_QUEUESPERPAGEPF3) & M_QUEUESPERPAGEPF3)

#define S_QUEUESPERPAGEPF2    8
#define M_QUEUESPERPAGEPF2    0xfU
#define V_QUEUESPERPAGEPF2(x) ((x) << S_QUEUESPERPAGEPF2)
#define G_QUEUESPERPAGEPF2(x) (((x) >> S_QUEUESPERPAGEPF2) & M_QUEUESPERPAGEPF2)

#define S_QUEUESPERPAGEPF1    4
#define M_QUEUESPERPAGEPF1    0xfU
#define V_QUEUESPERPAGEPF1(x) ((x) << S_QUEUESPERPAGEPF1)
#define G_QUEUESPERPAGEPF1(x) (((x) >> S_QUEUESPERPAGEPF1) & M_QUEUESPERPAGEPF1)

#define S_QUEUESPERPAGEPF0    0
#define M_QUEUESPERPAGEPF0    0xfU
#define V_QUEUESPERPAGEPF0(x) ((x) << S_QUEUESPERPAGEPF0)
#define G_QUEUESPERPAGEPF0(x) (((x) >> S_QUEUESPERPAGEPF0) & M_QUEUESPERPAGEPF0)

#define A_SGE_EGRESS_QUEUES_PER_PAGE_VF 0x1014

#define S_QUEUESPERPAGEVFPF7    28
#define M_QUEUESPERPAGEVFPF7    0xfU
#define V_QUEUESPERPAGEVFPF7(x) ((x) << S_QUEUESPERPAGEVFPF7)
#define G_QUEUESPERPAGEVFPF7(x) (((x) >> S_QUEUESPERPAGEVFPF7) & M_QUEUESPERPAGEVFPF7)

#define S_QUEUESPERPAGEVFPF6    24
#define M_QUEUESPERPAGEVFPF6    0xfU
#define V_QUEUESPERPAGEVFPF6(x) ((x) << S_QUEUESPERPAGEVFPF6)
#define G_QUEUESPERPAGEVFPF6(x) (((x) >> S_QUEUESPERPAGEVFPF6) & M_QUEUESPERPAGEVFPF6)

#define S_QUEUESPERPAGEVFPF5    20
#define M_QUEUESPERPAGEVFPF5    0xfU
#define V_QUEUESPERPAGEVFPF5(x) ((x) << S_QUEUESPERPAGEVFPF5)
#define G_QUEUESPERPAGEVFPF5(x) (((x) >> S_QUEUESPERPAGEVFPF5) & M_QUEUESPERPAGEVFPF5)

#define S_QUEUESPERPAGEVFPF4    16
#define M_QUEUESPERPAGEVFPF4    0xfU
#define V_QUEUESPERPAGEVFPF4(x) ((x) << S_QUEUESPERPAGEVFPF4)
#define G_QUEUESPERPAGEVFPF4(x) (((x) >> S_QUEUESPERPAGEVFPF4) & M_QUEUESPERPAGEVFPF4)

#define S_QUEUESPERPAGEVFPF3    12
#define M_QUEUESPERPAGEVFPF3    0xfU
#define V_QUEUESPERPAGEVFPF3(x) ((x) << S_QUEUESPERPAGEVFPF3)
#define G_QUEUESPERPAGEVFPF3(x) (((x) >> S_QUEUESPERPAGEVFPF3) & M_QUEUESPERPAGEVFPF3)

#define S_QUEUESPERPAGEVFPF2    8
#define M_QUEUESPERPAGEVFPF2    0xfU
#define V_QUEUESPERPAGEVFPF2(x) ((x) << S_QUEUESPERPAGEVFPF2)
#define G_QUEUESPERPAGEVFPF2(x) (((x) >> S_QUEUESPERPAGEVFPF2) & M_QUEUESPERPAGEVFPF2)

#define S_QUEUESPERPAGEVFPF1    4
#define M_QUEUESPERPAGEVFPF1    0xfU
#define V_QUEUESPERPAGEVFPF1(x) ((x) << S_QUEUESPERPAGEVFPF1)
#define G_QUEUESPERPAGEVFPF1(x) (((x) >> S_QUEUESPERPAGEVFPF1) & M_QUEUESPERPAGEVFPF1)

#define S_QUEUESPERPAGEVFPF0    0
#define M_QUEUESPERPAGEVFPF0    0xfU
#define V_QUEUESPERPAGEVFPF0(x) ((x) << S_QUEUESPERPAGEVFPF0)
#define G_QUEUESPERPAGEVFPF0(x) (((x) >> S_QUEUESPERPAGEVFPF0) & M_QUEUESPERPAGEVFPF0)

#define A_SGE_USER_MODE_LIMITS 0x1018

#define S_OPCODE_MIN    24
#define M_OPCODE_MIN    0xffU
#define V_OPCODE_MIN(x) ((x) << S_OPCODE_MIN)
#define G_OPCODE_MIN(x) (((x) >> S_OPCODE_MIN) & M_OPCODE_MIN)

#define S_OPCODE_MAX    16
#define M_OPCODE_MAX    0xffU
#define V_OPCODE_MAX(x) ((x) << S_OPCODE_MAX)
#define G_OPCODE_MAX(x) (((x) >> S_OPCODE_MAX) & M_OPCODE_MAX)

#define S_LENGTH_MIN    8
#define M_LENGTH_MIN    0xffU
#define V_LENGTH_MIN(x) ((x) << S_LENGTH_MIN)
#define G_LENGTH_MIN(x) (((x) >> S_LENGTH_MIN) & M_LENGTH_MIN)

#define S_LENGTH_MAX    0
#define M_LENGTH_MAX    0xffU
#define V_LENGTH_MAX(x) ((x) << S_LENGTH_MAX)
#define G_LENGTH_MAX(x) (((x) >> S_LENGTH_MAX) & M_LENGTH_MAX)

#define A_SGE_WR_ERROR 0x101c

#define S_WR_ERROR_OPCODE    0
#define M_WR_ERROR_OPCODE    0xffU
#define V_WR_ERROR_OPCODE(x) ((x) << S_WR_ERROR_OPCODE)
#define G_WR_ERROR_OPCODE(x) (((x) >> S_WR_ERROR_OPCODE) & M_WR_ERROR_OPCODE)

#define A_SGE_INT_CAUSE1 0x1024

#define S_PERR_FLM_CREDITFIFO    30
#define V_PERR_FLM_CREDITFIFO(x) ((x) << S_PERR_FLM_CREDITFIFO)
#define F_PERR_FLM_CREDITFIFO    V_PERR_FLM_CREDITFIFO(1U)

#define S_PERR_IMSG_HINT_FIFO    29
#define V_PERR_IMSG_HINT_FIFO(x) ((x) << S_PERR_IMSG_HINT_FIFO)
#define F_PERR_IMSG_HINT_FIFO    V_PERR_IMSG_HINT_FIFO(1U)

#define S_PERR_MC_PC    28
#define V_PERR_MC_PC(x) ((x) << S_PERR_MC_PC)
#define F_PERR_MC_PC    V_PERR_MC_PC(1U)

#define S_PERR_MC_IGR_CTXT    27
#define V_PERR_MC_IGR_CTXT(x) ((x) << S_PERR_MC_IGR_CTXT)
#define F_PERR_MC_IGR_CTXT    V_PERR_MC_IGR_CTXT(1U)

#define S_PERR_MC_EGR_CTXT    26
#define V_PERR_MC_EGR_CTXT(x) ((x) << S_PERR_MC_EGR_CTXT)
#define F_PERR_MC_EGR_CTXT    V_PERR_MC_EGR_CTXT(1U)

#define S_PERR_MC_FLM    25
#define V_PERR_MC_FLM(x) ((x) << S_PERR_MC_FLM)
#define F_PERR_MC_FLM    V_PERR_MC_FLM(1U)

#define S_PERR_PC_MCTAG    24
#define V_PERR_PC_MCTAG(x) ((x) << S_PERR_PC_MCTAG)
#define F_PERR_PC_MCTAG    V_PERR_PC_MCTAG(1U)

#define S_PERR_PC_CHPI_RSP1    23
#define V_PERR_PC_CHPI_RSP1(x) ((x) << S_PERR_PC_CHPI_RSP1)
#define F_PERR_PC_CHPI_RSP1    V_PERR_PC_CHPI_RSP1(1U)

#define S_PERR_PC_CHPI_RSP0    22
#define V_PERR_PC_CHPI_RSP0(x) ((x) << S_PERR_PC_CHPI_RSP0)
#define F_PERR_PC_CHPI_RSP0    V_PERR_PC_CHPI_RSP0(1U)

#define S_PERR_DBP_PC_RSP_FIFO3    21
#define V_PERR_DBP_PC_RSP_FIFO3(x) ((x) << S_PERR_DBP_PC_RSP_FIFO3)
#define F_PERR_DBP_PC_RSP_FIFO3    V_PERR_DBP_PC_RSP_FIFO3(1U)

#define S_PERR_DBP_PC_RSP_FIFO2    20
#define V_PERR_DBP_PC_RSP_FIFO2(x) ((x) << S_PERR_DBP_PC_RSP_FIFO2)
#define F_PERR_DBP_PC_RSP_FIFO2    V_PERR_DBP_PC_RSP_FIFO2(1U)

#define S_PERR_DBP_PC_RSP_FIFO1    19
#define V_PERR_DBP_PC_RSP_FIFO1(x) ((x) << S_PERR_DBP_PC_RSP_FIFO1)
#define F_PERR_DBP_PC_RSP_FIFO1    V_PERR_DBP_PC_RSP_FIFO1(1U)

#define S_PERR_DBP_PC_RSP_FIFO0    18
#define V_PERR_DBP_PC_RSP_FIFO0(x) ((x) << S_PERR_DBP_PC_RSP_FIFO0)
#define F_PERR_DBP_PC_RSP_FIFO0    V_PERR_DBP_PC_RSP_FIFO0(1U)

#define S_PERR_DMARBT    17
#define V_PERR_DMARBT(x) ((x) << S_PERR_DMARBT)
#define F_PERR_DMARBT    V_PERR_DMARBT(1U)

#define S_PERR_FLM_DBPFIFO    16
#define V_PERR_FLM_DBPFIFO(x) ((x) << S_PERR_FLM_DBPFIFO)
#define F_PERR_FLM_DBPFIFO    V_PERR_FLM_DBPFIFO(1U)

#define S_PERR_FLM_MCREQ_FIFO    15
#define V_PERR_FLM_MCREQ_FIFO(x) ((x) << S_PERR_FLM_MCREQ_FIFO)
#define F_PERR_FLM_MCREQ_FIFO    V_PERR_FLM_MCREQ_FIFO(1U)

#define S_PERR_FLM_HINTFIFO    14
#define V_PERR_FLM_HINTFIFO(x) ((x) << S_PERR_FLM_HINTFIFO)
#define F_PERR_FLM_HINTFIFO    V_PERR_FLM_HINTFIFO(1U)

#define S_PERR_ALIGN_CTL_FIFO3    13
#define V_PERR_ALIGN_CTL_FIFO3(x) ((x) << S_PERR_ALIGN_CTL_FIFO3)
#define F_PERR_ALIGN_CTL_FIFO3    V_PERR_ALIGN_CTL_FIFO3(1U)

#define S_PERR_ALIGN_CTL_FIFO2    12
#define V_PERR_ALIGN_CTL_FIFO2(x) ((x) << S_PERR_ALIGN_CTL_FIFO2)
#define F_PERR_ALIGN_CTL_FIFO2    V_PERR_ALIGN_CTL_FIFO2(1U)

#define S_PERR_ALIGN_CTL_FIFO1    11
#define V_PERR_ALIGN_CTL_FIFO1(x) ((x) << S_PERR_ALIGN_CTL_FIFO1)
#define F_PERR_ALIGN_CTL_FIFO1    V_PERR_ALIGN_CTL_FIFO1(1U)

#define S_PERR_ALIGN_CTL_FIFO0    10
#define V_PERR_ALIGN_CTL_FIFO0(x) ((x) << S_PERR_ALIGN_CTL_FIFO0)
#define F_PERR_ALIGN_CTL_FIFO0    V_PERR_ALIGN_CTL_FIFO0(1U)

#define S_PERR_EDMA_FIFO3    9
#define V_PERR_EDMA_FIFO3(x) ((x) << S_PERR_EDMA_FIFO3)
#define F_PERR_EDMA_FIFO3    V_PERR_EDMA_FIFO3(1U)

#define S_PERR_EDMA_FIFO2    8
#define V_PERR_EDMA_FIFO2(x) ((x) << S_PERR_EDMA_FIFO2)
#define F_PERR_EDMA_FIFO2    V_PERR_EDMA_FIFO2(1U)

#define S_PERR_EDMA_FIFO1    7
#define V_PERR_EDMA_FIFO1(x) ((x) << S_PERR_EDMA_FIFO1)
#define F_PERR_EDMA_FIFO1    V_PERR_EDMA_FIFO1(1U)

#define S_PERR_EDMA_FIFO0    6
#define V_PERR_EDMA_FIFO0(x) ((x) << S_PERR_EDMA_FIFO0)
#define F_PERR_EDMA_FIFO0    V_PERR_EDMA_FIFO0(1U)

#define S_PERR_PD_FIFO3    5
#define V_PERR_PD_FIFO3(x) ((x) << S_PERR_PD_FIFO3)
#define F_PERR_PD_FIFO3    V_PERR_PD_FIFO3(1U)

#define S_PERR_PD_FIFO2    4
#define V_PERR_PD_FIFO2(x) ((x) << S_PERR_PD_FIFO2)
#define F_PERR_PD_FIFO2    V_PERR_PD_FIFO2(1U)

#define S_PERR_PD_FIFO1    3
#define V_PERR_PD_FIFO1(x) ((x) << S_PERR_PD_FIFO1)
#define F_PERR_PD_FIFO1    V_PERR_PD_FIFO1(1U)

#define S_PERR_PD_FIFO0    2
#define V_PERR_PD_FIFO0(x) ((x) << S_PERR_PD_FIFO0)
#define F_PERR_PD_FIFO0    V_PERR_PD_FIFO0(1U)

#define S_PERR_ING_CTXT_MIFRSP    1
#define V_PERR_ING_CTXT_MIFRSP(x) ((x) << S_PERR_ING_CTXT_MIFRSP)
#define F_PERR_ING_CTXT_MIFRSP    V_PERR_ING_CTXT_MIFRSP(1U)

#define S_PERR_EGR_CTXT_MIFRSP    0
#define V_PERR_EGR_CTXT_MIFRSP(x) ((x) << S_PERR_EGR_CTXT_MIFRSP)
#define F_PERR_EGR_CTXT_MIFRSP    V_PERR_EGR_CTXT_MIFRSP(1U)

#define S_PERR_PC_CHPI_RSP2    31
#define V_PERR_PC_CHPI_RSP2(x) ((x) << S_PERR_PC_CHPI_RSP2)
#define F_PERR_PC_CHPI_RSP2    V_PERR_PC_CHPI_RSP2(1U)

#define S_PERR_PC_RSP    23
#define V_PERR_PC_RSP(x) ((x) << S_PERR_PC_RSP)
#define F_PERR_PC_RSP    V_PERR_PC_RSP(1U)

#define S_PERR_PC_REQ    22
#define V_PERR_PC_REQ(x) ((x) << S_PERR_PC_REQ)
#define F_PERR_PC_REQ    V_PERR_PC_REQ(1U)

#define A_SGE_INT_ENABLE1 0x1028
#define A_SGE_PERR_ENABLE1 0x102c
#define A_SGE_INT_CAUSE2 0x1030

#define S_PERR_HINT_DELAY_FIFO1    30
#define V_PERR_HINT_DELAY_FIFO1(x) ((x) << S_PERR_HINT_DELAY_FIFO1)
#define F_PERR_HINT_DELAY_FIFO1    V_PERR_HINT_DELAY_FIFO1(1U)

#define S_PERR_HINT_DELAY_FIFO0    29
#define V_PERR_HINT_DELAY_FIFO0(x) ((x) << S_PERR_HINT_DELAY_FIFO0)
#define F_PERR_HINT_DELAY_FIFO0    V_PERR_HINT_DELAY_FIFO0(1U)

#define S_PERR_IMSG_PD_FIFO    28
#define V_PERR_IMSG_PD_FIFO(x) ((x) << S_PERR_IMSG_PD_FIFO)
#define F_PERR_IMSG_PD_FIFO    V_PERR_IMSG_PD_FIFO(1U)

#define S_PERR_ULPTX_FIFO1    27
#define V_PERR_ULPTX_FIFO1(x) ((x) << S_PERR_ULPTX_FIFO1)
#define F_PERR_ULPTX_FIFO1    V_PERR_ULPTX_FIFO1(1U)

#define S_PERR_ULPTX_FIFO0    26
#define V_PERR_ULPTX_FIFO0(x) ((x) << S_PERR_ULPTX_FIFO0)
#define F_PERR_ULPTX_FIFO0    V_PERR_ULPTX_FIFO0(1U)

#define S_PERR_IDMA2IMSG_FIFO1    25
#define V_PERR_IDMA2IMSG_FIFO1(x) ((x) << S_PERR_IDMA2IMSG_FIFO1)
#define F_PERR_IDMA2IMSG_FIFO1    V_PERR_IDMA2IMSG_FIFO1(1U)

#define S_PERR_IDMA2IMSG_FIFO0    24
#define V_PERR_IDMA2IMSG_FIFO0(x) ((x) << S_PERR_IDMA2IMSG_FIFO0)
#define F_PERR_IDMA2IMSG_FIFO0    V_PERR_IDMA2IMSG_FIFO0(1U)

#define S_PERR_HEADERSPLIT_FIFO1    23
#define V_PERR_HEADERSPLIT_FIFO1(x) ((x) << S_PERR_HEADERSPLIT_FIFO1)
#define F_PERR_HEADERSPLIT_FIFO1    V_PERR_HEADERSPLIT_FIFO1(1U)

#define S_PERR_HEADERSPLIT_FIFO0    22
#define V_PERR_HEADERSPLIT_FIFO0(x) ((x) << S_PERR_HEADERSPLIT_FIFO0)
#define F_PERR_HEADERSPLIT_FIFO0    V_PERR_HEADERSPLIT_FIFO0(1U)

#define S_PERR_ESWITCH_FIFO3    21
#define V_PERR_ESWITCH_FIFO3(x) ((x) << S_PERR_ESWITCH_FIFO3)
#define F_PERR_ESWITCH_FIFO3    V_PERR_ESWITCH_FIFO3(1U)

#define S_PERR_ESWITCH_FIFO2    20
#define V_PERR_ESWITCH_FIFO2(x) ((x) << S_PERR_ESWITCH_FIFO2)
#define F_PERR_ESWITCH_FIFO2    V_PERR_ESWITCH_FIFO2(1U)

#define S_PERR_ESWITCH_FIFO1    19
#define V_PERR_ESWITCH_FIFO1(x) ((x) << S_PERR_ESWITCH_FIFO1)
#define F_PERR_ESWITCH_FIFO1    V_PERR_ESWITCH_FIFO1(1U)

#define S_PERR_ESWITCH_FIFO0    18
#define V_PERR_ESWITCH_FIFO0(x) ((x) << S_PERR_ESWITCH_FIFO0)
#define F_PERR_ESWITCH_FIFO0    V_PERR_ESWITCH_FIFO0(1U)

#define S_PERR_PC_DBP1    17
#define V_PERR_PC_DBP1(x) ((x) << S_PERR_PC_DBP1)
#define F_PERR_PC_DBP1    V_PERR_PC_DBP1(1U)

#define S_PERR_PC_DBP0    16
#define V_PERR_PC_DBP0(x) ((x) << S_PERR_PC_DBP0)
#define F_PERR_PC_DBP0    V_PERR_PC_DBP0(1U)

#define S_PERR_IMSG_OB_FIFO    15
#define V_PERR_IMSG_OB_FIFO(x) ((x) << S_PERR_IMSG_OB_FIFO)
#define F_PERR_IMSG_OB_FIFO    V_PERR_IMSG_OB_FIFO(1U)

#define S_PERR_CONM_SRAM    14
#define V_PERR_CONM_SRAM(x) ((x) << S_PERR_CONM_SRAM)
#define F_PERR_CONM_SRAM    V_PERR_CONM_SRAM(1U)

#define S_PERR_PC_MC_RSP    13
#define V_PERR_PC_MC_RSP(x) ((x) << S_PERR_PC_MC_RSP)
#define F_PERR_PC_MC_RSP    V_PERR_PC_MC_RSP(1U)

#define S_PERR_ISW_IDMA0_FIFO    12
#define V_PERR_ISW_IDMA0_FIFO(x) ((x) << S_PERR_ISW_IDMA0_FIFO)
#define F_PERR_ISW_IDMA0_FIFO    V_PERR_ISW_IDMA0_FIFO(1U)

#define S_PERR_ISW_IDMA1_FIFO    11
#define V_PERR_ISW_IDMA1_FIFO(x) ((x) << S_PERR_ISW_IDMA1_FIFO)
#define F_PERR_ISW_IDMA1_FIFO    V_PERR_ISW_IDMA1_FIFO(1U)

#define S_PERR_ISW_DBP_FIFO    10
#define V_PERR_ISW_DBP_FIFO(x) ((x) << S_PERR_ISW_DBP_FIFO)
#define F_PERR_ISW_DBP_FIFO    V_PERR_ISW_DBP_FIFO(1U)

#define S_PERR_ISW_GTS_FIFO    9
#define V_PERR_ISW_GTS_FIFO(x) ((x) << S_PERR_ISW_GTS_FIFO)
#define F_PERR_ISW_GTS_FIFO    V_PERR_ISW_GTS_FIFO(1U)

#define S_PERR_ITP_EVR    8
#define V_PERR_ITP_EVR(x) ((x) << S_PERR_ITP_EVR)
#define F_PERR_ITP_EVR    V_PERR_ITP_EVR(1U)

#define S_PERR_FLM_CNTXMEM    7
#define V_PERR_FLM_CNTXMEM(x) ((x) << S_PERR_FLM_CNTXMEM)
#define F_PERR_FLM_CNTXMEM    V_PERR_FLM_CNTXMEM(1U)

#define S_PERR_FLM_L1CACHE    6
#define V_PERR_FLM_L1CACHE(x) ((x) << S_PERR_FLM_L1CACHE)
#define F_PERR_FLM_L1CACHE    V_PERR_FLM_L1CACHE(1U)

#define S_PERR_DBP_HINT_FIFO    5
#define V_PERR_DBP_HINT_FIFO(x) ((x) << S_PERR_DBP_HINT_FIFO)
#define F_PERR_DBP_HINT_FIFO    V_PERR_DBP_HINT_FIFO(1U)

#define S_PERR_DBP_HP_FIFO    4
#define V_PERR_DBP_HP_FIFO(x) ((x) << S_PERR_DBP_HP_FIFO)
#define F_PERR_DBP_HP_FIFO    V_PERR_DBP_HP_FIFO(1U)

#define S_PERR_DBP_LP_FIFO    3
#define V_PERR_DBP_LP_FIFO(x) ((x) << S_PERR_DBP_LP_FIFO)
#define F_PERR_DBP_LP_FIFO    V_PERR_DBP_LP_FIFO(1U)

#define S_PERR_ING_CTXT_CACHE    2
#define V_PERR_ING_CTXT_CACHE(x) ((x) << S_PERR_ING_CTXT_CACHE)
#define F_PERR_ING_CTXT_CACHE    V_PERR_ING_CTXT_CACHE(1U)

#define S_PERR_EGR_CTXT_CACHE    1
#define V_PERR_EGR_CTXT_CACHE(x) ((x) << S_PERR_EGR_CTXT_CACHE)
#define F_PERR_EGR_CTXT_CACHE    V_PERR_EGR_CTXT_CACHE(1U)

#define S_PERR_BASE_SIZE    0
#define V_PERR_BASE_SIZE(x) ((x) << S_PERR_BASE_SIZE)
#define F_PERR_BASE_SIZE    V_PERR_BASE_SIZE(1U)

#define S_PERR_DBP_HINT_FL_FIFO    24
#define V_PERR_DBP_HINT_FL_FIFO(x) ((x) << S_PERR_DBP_HINT_FL_FIFO)
#define F_PERR_DBP_HINT_FL_FIFO    V_PERR_DBP_HINT_FL_FIFO(1U)

#define S_PERR_EGR_DBP_TX_COAL    23
#define V_PERR_EGR_DBP_TX_COAL(x) ((x) << S_PERR_EGR_DBP_TX_COAL)
#define F_PERR_EGR_DBP_TX_COAL    V_PERR_EGR_DBP_TX_COAL(1U)

#define S_PERR_DBP_FL_FIFO    22
#define V_PERR_DBP_FL_FIFO(x) ((x) << S_PERR_DBP_FL_FIFO)
#define F_PERR_DBP_FL_FIFO    V_PERR_DBP_FL_FIFO(1U)

#define S_PERR_PC_DBP2    15
#define V_PERR_PC_DBP2(x) ((x) << S_PERR_PC_DBP2)
#define F_PERR_PC_DBP2    V_PERR_PC_DBP2(1U)

#define S_DEQ_LL_PERR    21
#define V_DEQ_LL_PERR(x) ((x) << S_DEQ_LL_PERR)
#define F_DEQ_LL_PERR    V_DEQ_LL_PERR(1U)

#define S_ENQ_PERR    20
#define V_ENQ_PERR(x) ((x) << S_ENQ_PERR)
#define F_ENQ_PERR    V_ENQ_PERR(1U)

#define S_DEQ_OUT_PERR    19
#define V_DEQ_OUT_PERR(x) ((x) << S_DEQ_OUT_PERR)
#define F_DEQ_OUT_PERR    V_DEQ_OUT_PERR(1U)

#define S_BUF_PERR    18
#define V_BUF_PERR(x) ((x) << S_BUF_PERR)
#define F_BUF_PERR    V_BUF_PERR(1U)

#define S_PERR_DB_FIFO    3
#define V_PERR_DB_FIFO(x) ((x) << S_PERR_DB_FIFO)
#define F_PERR_DB_FIFO    V_PERR_DB_FIFO(1U)

#define A_SGE_INT_ENABLE2 0x1034
#define A_SGE_PERR_ENABLE2 0x1038
#define A_SGE_INT_CAUSE3 0x103c

#define S_ERR_FLM_DBP    31
#define V_ERR_FLM_DBP(x) ((x) << S_ERR_FLM_DBP)
#define F_ERR_FLM_DBP    V_ERR_FLM_DBP(1U)

#define S_ERR_FLM_IDMA1    30
#define V_ERR_FLM_IDMA1(x) ((x) << S_ERR_FLM_IDMA1)
#define F_ERR_FLM_IDMA1    V_ERR_FLM_IDMA1(1U)

#define S_ERR_FLM_IDMA0    29
#define V_ERR_FLM_IDMA0(x) ((x) << S_ERR_FLM_IDMA0)
#define F_ERR_FLM_IDMA0    V_ERR_FLM_IDMA0(1U)

#define S_ERR_FLM_HINT    28
#define V_ERR_FLM_HINT(x) ((x) << S_ERR_FLM_HINT)
#define F_ERR_FLM_HINT    V_ERR_FLM_HINT(1U)

#define S_ERR_PCIE_ERROR3    27
#define V_ERR_PCIE_ERROR3(x) ((x) << S_ERR_PCIE_ERROR3)
#define F_ERR_PCIE_ERROR3    V_ERR_PCIE_ERROR3(1U)

#define S_ERR_PCIE_ERROR2    26
#define V_ERR_PCIE_ERROR2(x) ((x) << S_ERR_PCIE_ERROR2)
#define F_ERR_PCIE_ERROR2    V_ERR_PCIE_ERROR2(1U)

#define S_ERR_PCIE_ERROR1    25
#define V_ERR_PCIE_ERROR1(x) ((x) << S_ERR_PCIE_ERROR1)
#define F_ERR_PCIE_ERROR1    V_ERR_PCIE_ERROR1(1U)

#define S_ERR_PCIE_ERROR0    24
#define V_ERR_PCIE_ERROR0(x) ((x) << S_ERR_PCIE_ERROR0)
#define F_ERR_PCIE_ERROR0    V_ERR_PCIE_ERROR0(1U)

#define S_ERR_TIMER_ABOVE_MAX_QID    23
#define V_ERR_TIMER_ABOVE_MAX_QID(x) ((x) << S_ERR_TIMER_ABOVE_MAX_QID)
#define F_ERR_TIMER_ABOVE_MAX_QID    V_ERR_TIMER_ABOVE_MAX_QID(1U)

#define S_ERR_CPL_EXCEED_IQE_SIZE    22
#define V_ERR_CPL_EXCEED_IQE_SIZE(x) ((x) << S_ERR_CPL_EXCEED_IQE_SIZE)
#define F_ERR_CPL_EXCEED_IQE_SIZE    V_ERR_CPL_EXCEED_IQE_SIZE(1U)

#define S_ERR_INVALID_CIDX_INC    21
#define V_ERR_INVALID_CIDX_INC(x) ((x) << S_ERR_INVALID_CIDX_INC)
#define F_ERR_INVALID_CIDX_INC    V_ERR_INVALID_CIDX_INC(1U)

#define S_ERR_ITP_TIME_PAUSED    20
#define V_ERR_ITP_TIME_PAUSED(x) ((x) << S_ERR_ITP_TIME_PAUSED)
#define F_ERR_ITP_TIME_PAUSED    V_ERR_ITP_TIME_PAUSED(1U)

#define S_ERR_CPL_OPCODE_0    19
#define V_ERR_CPL_OPCODE_0(x) ((x) << S_ERR_CPL_OPCODE_0)
#define F_ERR_CPL_OPCODE_0    V_ERR_CPL_OPCODE_0(1U)

#define S_ERR_DROPPED_DB    18
#define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB)
#define F_ERR_DROPPED_DB    V_ERR_DROPPED_DB(1U)

#define S_ERR_DATA_CPL_ON_HIGH_QID1    17
#define V_ERR_DATA_CPL_ON_HIGH_QID1(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID1)
#define F_ERR_DATA_CPL_ON_HIGH_QID1    V_ERR_DATA_CPL_ON_HIGH_QID1(1U)

#define S_ERR_DATA_CPL_ON_HIGH_QID0    16
#define V_ERR_DATA_CPL_ON_HIGH_QID0(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID0)
#define F_ERR_DATA_CPL_ON_HIGH_QID0    V_ERR_DATA_CPL_ON_HIGH_QID0(1U)

#define S_ERR_BAD_DB_PIDX3    15
#define V_ERR_BAD_DB_PIDX3(x) ((x) << S_ERR_BAD_DB_PIDX3)
#define F_ERR_BAD_DB_PIDX3    V_ERR_BAD_DB_PIDX3(1U)

#define S_ERR_BAD_DB_PIDX2    14
#define V_ERR_BAD_DB_PIDX2(x) ((x) << S_ERR_BAD_DB_PIDX2)
#define F_ERR_BAD_DB_PIDX2    V_ERR_BAD_DB_PIDX2(1U)

#define S_ERR_BAD_DB_PIDX1    13
#define V_ERR_BAD_DB_PIDX1(x) ((x) << S_ERR_BAD_DB_PIDX1)
#define F_ERR_BAD_DB_PIDX1    V_ERR_BAD_DB_PIDX1(1U)

#define S_ERR_BAD_DB_PIDX0    12
#define V_ERR_BAD_DB_PIDX0(x) ((x) << S_ERR_BAD_DB_PIDX0)
#define F_ERR_BAD_DB_PIDX0    V_ERR_BAD_DB_PIDX0(1U)

#define S_ERR_ING_PCIE_CHAN    11
#define V_ERR_ING_PCIE_CHAN(x) ((x) << S_ERR_ING_PCIE_CHAN)
#define F_ERR_ING_PCIE_CHAN    V_ERR_ING_PCIE_CHAN(1U)

#define S_ERR_ING_CTXT_PRIO    10
#define V_ERR_ING_CTXT_PRIO(x) ((x) << S_ERR_ING_CTXT_PRIO)
#define F_ERR_ING_CTXT_PRIO    V_ERR_ING_CTXT_PRIO(1U)

#define S_ERR_EGR_CTXT_PRIO    9
#define V_ERR_EGR_CTXT_PRIO(x) ((x) << S_ERR_EGR_CTXT_PRIO)
#define F_ERR_EGR_CTXT_PRIO    V_ERR_EGR_CTXT_PRIO(1U)

#define S_DBFIFO_HP_INT    8
#define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT)
#define F_DBFIFO_HP_INT    V_DBFIFO_HP_INT(1U)

#define S_DBFIFO_LP_INT    7
#define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT)
#define F_DBFIFO_LP_INT    V_DBFIFO_LP_INT(1U)

#define S_REG_ADDRESS_ERR    6
#define V_REG_ADDRESS_ERR(x) ((x) << S_REG_ADDRESS_ERR)
#define F_REG_ADDRESS_ERR    V_REG_ADDRESS_ERR(1U)

#define S_INGRESS_SIZE_ERR    5
#define V_INGRESS_SIZE_ERR(x) ((x) << S_INGRESS_SIZE_ERR)
#define F_INGRESS_SIZE_ERR    V_INGRESS_SIZE_ERR(1U)

#define S_EGRESS_SIZE_ERR    4
#define V_EGRESS_SIZE_ERR(x) ((x) << S_EGRESS_SIZE_ERR)
#define F_EGRESS_SIZE_ERR    V_EGRESS_SIZE_ERR(1U)

#define S_ERR_INV_CTXT3    3
#define V_ERR_INV_CTXT3(x) ((x) << S_ERR_INV_CTXT3)
#define F_ERR_INV_CTXT3    V_ERR_INV_CTXT3(1U)

#define S_ERR_INV_CTXT2    2
#define V_ERR_INV_CTXT2(x) ((x) << S_ERR_INV_CTXT2)
#define F_ERR_INV_CTXT2    V_ERR_INV_CTXT2(1U)

#define S_ERR_INV_CTXT1    1
#define V_ERR_INV_CTXT1(x) ((x) << S_ERR_INV_CTXT1)
#define F_ERR_INV_CTXT1    V_ERR_INV_CTXT1(1U)

#define S_ERR_INV_CTXT0    0
#define V_ERR_INV_CTXT0(x) ((x) << S_ERR_INV_CTXT0)
#define F_ERR_INV_CTXT0    V_ERR_INV_CTXT0(1U)

#define S_DBP_TBUF_FULL    8
#define V_DBP_TBUF_FULL(x) ((x) << S_DBP_TBUF_FULL)
#define F_DBP_TBUF_FULL    V_DBP_TBUF_FULL(1U)

#define S_FATAL_WRE_LEN    7
#define V_FATAL_WRE_LEN(x) ((x) << S_FATAL_WRE_LEN)
#define F_FATAL_WRE_LEN    V_FATAL_WRE_LEN(1U)

#define A_SGE_INT_ENABLE3 0x1040
#define A_SGE_FL_BUFFER_SIZE0 0x1044

#define S_SIZE    4
#define M_SIZE    0xfffffffU
#define V_SIZE(x) ((x) << S_SIZE)
#define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE)

#define S_T6_SIZE    4
#define M_T6_SIZE    0xfffffU
#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)

#define A_SGE_FL_BUFFER_SIZE1 0x1048

#define S_T6_SIZE    4
#define M_T6_SIZE    0xfffffU
#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)

#define A_SGE_FL_BUFFER_SIZE2 0x104c

#define S_T6_SIZE    4
#define M_T6_SIZE    0xfffffU
#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)

#define A_SGE_FL_BUFFER_SIZE3 0x1050

#define S_T6_SIZE    4
#define M_T6_SIZE    0xfffffU
#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)

#define A_SGE_FL_BUFFER_SIZE4 0x1054

#define S_T6_SIZE    4
#define M_T6_SIZE    0xfffffU
#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)

#define A_SGE_FL_BUFFER_SIZE5 0x1058

#define S_T6_SIZE    4
#define M_T6_SIZE    0xfffffU
#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)

#define A_SGE_FL_BUFFER_SIZE6 0x105c

#define S_T6_SIZE    4
#define M_T6_SIZE    0xfffffU
#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)

#define A_SGE_FL_BUFFER_SIZE7 0x1060

#define S_T6_SIZE    4
#define M_T6_SIZE    0xfffffU
#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)

#define A_SGE_FL_BUFFER_SIZE8 0x1064

#define S_T6_SIZE    4
#define M_T6_SIZE    0xfffffU
#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)

#define A_SGE_FL_BUFFER_SIZE9 0x1068

#define S_T6_SIZE    4
#define M_T6_SIZE    0xfffffU
#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)

#define A_SGE_FL_BUFFER_SIZE10 0x106c

#define S_T6_SIZE    4
#define M_T6_SIZE    0xfffffU
#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)

#define A_SGE_FL_BUFFER_SIZE11 0x1070

#define S_T6_SIZE    4
#define M_T6_SIZE    0xfffffU
#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)

#define A_SGE_FL_BUFFER_SIZE12 0x1074

#define S_T6_SIZE    4
#define M_T6_SIZE    0xfffffU
#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)

#define A_SGE_FL_BUFFER_SIZE13 0x1078

#define S_T6_SIZE    4
#define M_T6_SIZE    0xfffffU
#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)

#define A_SGE_FL_BUFFER_SIZE14 0x107c

#define S_T6_SIZE    4
#define M_T6_SIZE    0xfffffU
#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)

#define A_SGE_FL_BUFFER_SIZE15 0x1080

#define S_T6_SIZE    4
#define M_T6_SIZE    0xfffffU
#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)

#define A_SGE_DBQ_CTXT_BADDR 0x1084

#define S_BASEADDR    3
#define M_BASEADDR    0x1fffffffU
#define V_BASEADDR(x) ((x) << S_BASEADDR)
#define G_BASEADDR(x) (((x) >> S_BASEADDR) & M_BASEADDR)

#define A_SGE_IMSG_CTXT_BADDR 0x1088
#define A_SGE_FLM_CACHE_BADDR 0x108c
#define A_SGE_FLM_CFG 0x1090

#define S_OPMODE    26
#define M_OPMODE    0x3fU
#define V_OPMODE(x) ((x) << S_OPMODE)
#define G_OPMODE(x) (((x) >> S_OPMODE) & M_OPMODE)

#define S_NULLPTR    20
#define M_NULLPTR    0xfU
#define V_NULLPTR(x) ((x) << S_NULLPTR)
#define G_NULLPTR(x) (((x) >> S_NULLPTR) & M_NULLPTR)

#define S_NULLPTREN    19
#define V_NULLPTREN(x) ((x) << S_NULLPTREN)
#define F_NULLPTREN    V_NULLPTREN(1U)

#define S_NOHDR    18
#define V_NOHDR(x) ((x) << S_NOHDR)
#define F_NOHDR    V_NOHDR(1U)

#define S_CACHEPTRCNT    16
#define M_CACHEPTRCNT    0x3U
#define V_CACHEPTRCNT(x) ((x) << S_CACHEPTRCNT)
#define G_CACHEPTRCNT(x) (((x) >> S_CACHEPTRCNT) & M_CACHEPTRCNT)

#define S_EDRAMPTRCNT    14
#define M_EDRAMPTRCNT    0x3U
#define V_EDRAMPTRCNT(x) ((x) << S_EDRAMPTRCNT)
#define G_EDRAMPTRCNT(x) (((x) >> S_EDRAMPTRCNT) & M_EDRAMPTRCNT)

#define S_HDRSTARTFLQ    11
#define M_HDRSTARTFLQ    0x7U
#define V_HDRSTARTFLQ(x) ((x) << S_HDRSTARTFLQ)
#define G_HDRSTARTFLQ(x) (((x) >> S_HDRSTARTFLQ) & M_HDRSTARTFLQ)

#define S_FETCHTHRESH    6
#define M_FETCHTHRESH    0x1fU
#define V_FETCHTHRESH(x) ((x) << S_FETCHTHRESH)
#define G_FETCHTHRESH(x) (((x) >> S_FETCHTHRESH) & M_FETCHTHRESH)

#define S_CREDITCNT    4
#define M_CREDITCNT    0x3U
#define V_CREDITCNT(x) ((x) << S_CREDITCNT)
#define G_CREDITCNT(x) (((x) >> S_CREDITCNT) & M_CREDITCNT)

#define S_CREDITCNTPACKING    2
#define M_CREDITCNTPACKING    0x3U
#define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING)
#define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING)

#define S_NOEDRAM    0
#define V_NOEDRAM(x) ((x) << S_NOEDRAM)
#define F_NOEDRAM    V_NOEDRAM(1U)

#define A_SGE_CONM_CTRL 0x1094

#define S_EGRTHRESHOLD    8
#define M_EGRTHRESHOLD    0x3fU
#define V_EGRTHRESHOLD(x) ((x) << S_EGRTHRESHOLD)
#define G_EGRTHRESHOLD(x) (((x) >> S_EGRTHRESHOLD) & M_EGRTHRESHOLD)

#define S_EGRTHRESHOLDPACKING    14
#define M_EGRTHRESHOLDPACKING    0x3fU
#define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING)
#define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & M_EGRTHRESHOLDPACKING)

#define S_T6_EGRTHRESHOLDPACKING    16
#define M_T6_EGRTHRESHOLDPACKING    0xffU
#define V_T6_EGRTHRESHOLDPACKING(x) ((x) << S_T6_EGRTHRESHOLDPACKING)
#define G_T6_EGRTHRESHOLDPACKING(x) (((x) >> S_T6_EGRTHRESHOLDPACKING) & M_T6_EGRTHRESHOLDPACKING)

#define S_T6_EGRTHRESHOLD    8
#define M_T6_EGRTHRESHOLD    0xffU
#define V_T6_EGRTHRESHOLD(x) ((x) << S_T6_EGRTHRESHOLD)
#define G_T6_EGRTHRESHOLD(x) (((x) >> S_T6_EGRTHRESHOLD) & M_T6_EGRTHRESHOLD)

#define S_INGTHRESHOLD    2
#define M_INGTHRESHOLD    0x3fU
#define V_INGTHRESHOLD(x) ((x) << S_INGTHRESHOLD)
#define G_INGTHRESHOLD(x) (((x) >> S_INGTHRESHOLD) & M_INGTHRESHOLD)

#define A_SGE_TIMESTAMP_LO 0x1098
#define A_SGE_TIMESTAMP_HI 0x109c

#define S_TSOP    28
#define M_TSOP    0x3U
#define V_TSOP(x) ((x) << S_TSOP)
#define G_TSOP(x) (((x) >> S_TSOP) & M_TSOP)

#define S_TSVAL    0
#define M_TSVAL    0xfffffffU
#define V_TSVAL(x) ((x) << S_TSVAL)
#define G_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL)

#define A_SGE_INGRESS_RX_THRESHOLD 0x10a0

#define S_THRESHOLD_0    24
#define M_THRESHOLD_0    0x3fU
#define V_THRESHOLD_0(x) ((x) << S_THRESHOLD_0)
#define G_THRESHOLD_0(x) (((x) >> S_THRESHOLD_0) & M_THRESHOLD_0)

#define S_THRESHOLD_1    16
#define M_THRESHOLD_1    0x3fU
#define V_THRESHOLD_1(x) ((x) << S_THRESHOLD_1)
#define G_THRESHOLD_1(x) (((x) >> S_THRESHOLD_1) & M_THRESHOLD_1)

#define S_THRESHOLD_2    8
#define M_THRESHOLD_2    0x3fU
#define V_THRESHOLD_2(x) ((x) << S_THRESHOLD_2)
#define G_THRESHOLD_2(x) (((x) >> S_THRESHOLD_2) & M_THRESHOLD_2)

#define S_THRESHOLD_3    0
#define M_THRESHOLD_3    0x3fU
#define V_THRESHOLD_3(x) ((x) << S_THRESHOLD_3)
#define G_THRESHOLD_3(x) (((x) >> S_THRESHOLD_3) & M_THRESHOLD_3)

#define A_SGE_DBFIFO_STATUS 0x10a4

#define S_HP_INT_THRESH    28
#define M_HP_INT_THRESH    0xfU
#define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
#define G_HP_INT_THRESH(x) (((x) >> S_HP_INT_THRESH) & M_HP_INT_THRESH)

#define S_HP_COUNT    16
#define M_HP_COUNT    0x7ffU
#define V_HP_COUNT(x) ((x) << S_HP_COUNT)
#define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)

#define S_LP_INT_THRESH    12
#define M_LP_INT_THRESH    0xfU
#define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
#define G_LP_INT_THRESH(x) (((x) >> S_LP_INT_THRESH) & M_LP_INT_THRESH)

#define S_LP_COUNT    0
#define M_LP_COUNT    0x7ffU
#define V_LP_COUNT(x) ((x) << S_LP_COUNT)
#define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)

#define S_BAR2VALID    31
#define V_BAR2VALID(x) ((x) << S_BAR2VALID)
#define F_BAR2VALID    V_BAR2VALID(1U)

#define S_BAR2FULL    30
#define V_BAR2FULL(x) ((x) << S_BAR2FULL)
#define F_BAR2FULL    V_BAR2FULL(1U)

#define S_LP_INT_THRESH_T5    18
#define M_LP_INT_THRESH_T5    0xfffU
#define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
#define G_LP_INT_THRESH_T5(x) (((x) >> S_LP_INT_THRESH_T5) & M_LP_INT_THRESH_T5)

#define S_LP_COUNT_T5    0
#define M_LP_COUNT_T5    0x3ffffU
#define V_LP_COUNT_T5(x) ((x) << S_LP_COUNT_T5)
#define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT_T5) & M_LP_COUNT_T5)

#define S_VFIFO_CNT    15
#define M_VFIFO_CNT    0x1ffffU
#define V_VFIFO_CNT(x) ((x) << S_VFIFO_CNT)
#define G_VFIFO_CNT(x) (((x) >> S_VFIFO_CNT) & M_VFIFO_CNT)

#define S_COAL_CTL_FIFO_CNT    8
#define M_COAL_CTL_FIFO_CNT    0x3fU
#define V_COAL_CTL_FIFO_CNT(x) ((x) << S_COAL_CTL_FIFO_CNT)
#define G_COAL_CTL_FIFO_CNT(x) (((x) >> S_COAL_CTL_FIFO_CNT) & M_COAL_CTL_FIFO_CNT)

#define S_MERGE_FIFO_CNT    0
#define M_MERGE_FIFO_CNT    0x3fU
#define V_MERGE_FIFO_CNT(x) ((x) << S_MERGE_FIFO_CNT)
#define G_MERGE_FIFO_CNT(x) (((x) >> S_MERGE_FIFO_CNT) & M_MERGE_FIFO_CNT)

#define A_SGE_DOORBELL_CONTROL 0x10a8

#define S_HINTDEPTHCTL    27
#define M_HINTDEPTHCTL    0x1fU
#define V_HINTDEPTHCTL(x) ((x) << S_HINTDEPTHCTL)
#define G_HINTDEPTHCTL(x) (((x) >> S_HINTDEPTHCTL) & M_HINTDEPTHCTL)

#define S_NOCOALESCE    26
#define V_NOCOALESCE(x) ((x) << S_NOCOALESCE)
#define F_NOCOALESCE    V_NOCOALESCE(1U)

#define S_HP_WEIGHT    24
#define M_HP_WEIGHT    0x3U
#define V_HP_WEIGHT(x) ((x) << S_HP_WEIGHT)
#define G_HP_WEIGHT(x) (((x) >> S_HP_WEIGHT) & M_HP_WEIGHT)

#define S_HP_DISABLE    23
#define V_HP_DISABLE(x) ((x) << S_HP_DISABLE)
#define F_HP_DISABLE    V_HP_DISABLE(1U)

#define S_FORCEUSERDBTOLP    22
#define V_FORCEUSERDBTOLP(x) ((x) << S_FORCEUSERDBTOLP)
#define F_FORCEUSERDBTOLP    V_FORCEUSERDBTOLP(1U)

#define S_FORCEVFPF0DBTOLP    21
#define V_FORCEVFPF0DBTOLP(x) ((x) << S_FORCEVFPF0DBTOLP)
#define F_FORCEVFPF0DBTOLP    V_FORCEVFPF0DBTOLP(1U)

#define S_FORCEVFPF1DBTOLP    20
#define V_FORCEVFPF1DBTOLP(x) ((x) << S_FORCEVFPF1DBTOLP)
#define F_FORCEVFPF1DBTOLP    V_FORCEVFPF1DBTOLP(1U)

#define S_FORCEVFPF2DBTOLP    19
#define V_FORCEVFPF2DBTOLP(x) ((x) << S_FORCEVFPF2DBTOLP)
#define F_FORCEVFPF2DBTOLP    V_FORCEVFPF2DBTOLP(1U)

#define S_FORCEVFPF3DBTOLP    18
#define V_FORCEVFPF3DBTOLP(x) ((x) << S_FORCEVFPF3DBTOLP)
#define F_FORCEVFPF3DBTOLP    V_FORCEVFPF3DBTOLP(1U)

#define S_FORCEVFPF4DBTOLP    17
#define V_FORCEVFPF4DBTOLP(x) ((x) << S_FORCEVFPF4DBTOLP)
#define F_FORCEVFPF4DBTOLP    V_FORCEVFPF4DBTOLP(1U)

#define S_FORCEVFPF5DBTOLP    16
#define V_FORCEVFPF5DBTOLP(x) ((x) << S_FORCEVFPF5DBTOLP)
#define F_FORCEVFPF5DBTOLP    V_FORCEVFPF5DBTOLP(1U)

#define S_FORCEVFPF6DBTOLP    15
#define V_FORCEVFPF6DBTOLP(x) ((x) << S_FORCEVFPF6DBTOLP)
#define F_FORCEVFPF6DBTOLP    V_FORCEVFPF6DBTOLP(1U)

#define S_FORCEVFPF7DBTOLP    14
#define V_FORCEVFPF7DBTOLP(x) ((x) << S_FORCEVFPF7DBTOLP)
#define F_FORCEVFPF7DBTOLP    V_FORCEVFPF7DBTOLP(1U)

#define S_ENABLE_DROP    13
#define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
#define F_ENABLE_DROP    V_ENABLE_DROP(1U)

#define S_DROP_TIMEOUT    1
#define M_DROP_TIMEOUT    0xfffU
#define V_DROP_TIMEOUT(x) ((x) << S_DROP_TIMEOUT)
#define G_DROP_TIMEOUT(x) (((x) >> S_DROP_TIMEOUT) & M_DROP_TIMEOUT)

#define S_DROPPED_DB    0
#define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
#define F_DROPPED_DB    V_DROPPED_DB(1U)

#define S_T6_DROP_TIMEOUT    7
#define M_T6_DROP_TIMEOUT    0x3fU
#define V_T6_DROP_TIMEOUT(x) ((x) << S_T6_DROP_TIMEOUT)
#define G_T6_DROP_TIMEOUT(x) (((x) >> S_T6_DROP_TIMEOUT) & M_T6_DROP_TIMEOUT)

#define S_INVONDBSYNC    6
#define V_INVONDBSYNC(x) ((x) << S_INVONDBSYNC)
#define F_INVONDBSYNC    V_INVONDBSYNC(1U)

#define S_INVONGTSSYNC    5
#define V_INVONGTSSYNC(x) ((x) << S_INVONGTSSYNC)
#define F_INVONGTSSYNC    V_INVONGTSSYNC(1U)

#define S_DB_DBG_EN    4
#define V_DB_DBG_EN(x) ((x) << S_DB_DBG_EN)
#define F_DB_DBG_EN    V_DB_DBG_EN(1U)

#define S_GTS_DBG_TIMER_REG    1
#define M_GTS_DBG_TIMER_REG    0x7U
#define V_GTS_DBG_TIMER_REG(x) ((x) << S_GTS_DBG_TIMER_REG)
#define G_GTS_DBG_TIMER_REG(x) (((x) >> S_GTS_DBG_TIMER_REG) & M_GTS_DBG_TIMER_REG)

#define S_GTS_DBG_EN    0
#define V_GTS_DBG_EN(x) ((x) << S_GTS_DBG_EN)
#define F_GTS_DBG_EN    V_GTS_DBG_EN(1U)

#define A_SGE_DOORBELL_THROTTLE_CONTROL 0x10b0

#define S_BAR2THROTTLECOUNT    16
#define M_BAR2THROTTLECOUNT    0xffU
#define V_BAR2THROTTLECOUNT(x) ((x) << S_BAR2THROTTLECOUNT)
#define G_BAR2THROTTLECOUNT(x) (((x) >> S_BAR2THROTTLECOUNT) & M_BAR2THROTTLECOUNT)

#define S_CLRCOALESCEDISABLE    15
#define V_CLRCOALESCEDISABLE(x) ((x) << S_CLRCOALESCEDISABLE)
#define F_CLRCOALESCEDISABLE    V_CLRCOALESCEDISABLE(1U)

#define S_OPENBAR2GATEONCE    14
#define V_OPENBAR2GATEONCE(x) ((x) << S_OPENBAR2GATEONCE)
#define F_OPENBAR2GATEONCE    V_OPENBAR2GATEONCE(1U)

#define S_FORCEOPENBAR2GATE    13
#define V_FORCEOPENBAR2GATE(x) ((x) << S_FORCEOPENBAR2GATE)
#define F_FORCEOPENBAR2GATE    V_FORCEOPENBAR2GATE(1U)

#define A_SGE_ITP_CONTROL 0x10b4

#define S_TSCALE    28
#define M_TSCALE    0xfU
#define V_TSCALE(x) ((x) << S_TSCALE)
#define G_TSCALE(x) (((x) >> S_TSCALE) & M_TSCALE)

#define S_CRITICAL_TIME    10
#define M_CRITICAL_TIME    0x7fffU
#define V_CRITICAL_TIME(x) ((x) << S_CRITICAL_TIME)
#define G_CRITICAL_TIME(x) (((x) >> S_CRITICAL_TIME) & M_CRITICAL_TIME)

#define S_LL_EMPTY    4
#define M_LL_EMPTY    0x3fU
#define V_LL_EMPTY(x) ((x) << S_LL_EMPTY)
#define G_LL_EMPTY(x) (((x) >> S_LL_EMPTY) & M_LL_EMPTY)

#define S_LL_READ_WAIT_DISABLE    0
#define V_LL_READ_WAIT_DISABLE(x) ((x) << S_LL_READ_WAIT_DISABLE)
#define F_LL_READ_WAIT_DISABLE    V_LL_READ_WAIT_DISABLE(1U)

#define A_SGE_TIMER_VALUE_0_AND_1 0x10b8

#define S_TIMERVALUE0    16
#define M_TIMERVALUE0    0xffffU
#define V_TIMERVALUE0(x) ((x) << S_TIMERVALUE0)
#define G_TIMERVALUE0(x) (((x) >> S_TIMERVALUE0) & M_TIMERVALUE0)

#define S_TIMERVALUE1    0
#define M_TIMERVALUE1    0xffffU
#define V_TIMERVALUE1(x) ((x) << S_TIMERVALUE1)
#define G_TIMERVALUE1(x) (((x) >> S_TIMERVALUE1) & M_TIMERVALUE1)

#define A_SGE_TIMER_VALUE_2_AND_3 0x10bc

#define S_TIMERVALUE2    16
#define M_TIMERVALUE2    0xffffU
#define V_TIMERVALUE2(x) ((x) << S_TIMERVALUE2)
#define G_TIMERVALUE2(x) (((x) >> S_TIMERVALUE2) & M_TIMERVALUE2)

#define S_TIMERVALUE3    0
#define M_TIMERVALUE3    0xffffU
#define V_TIMERVALUE3(x) ((x) << S_TIMERVALUE3)
#define G_TIMERVALUE3(x) (((x) >> S_TIMERVALUE3) & M_TIMERVALUE3)

#define A_SGE_TIMER_VALUE_4_AND_5 0x10c0

#define S_TIMERVALUE4    16
#define M_TIMERVALUE4    0xffffU
#define V_TIMERVALUE4(x) ((x) << S_TIMERVALUE4)
#define G_TIMERVALUE4(x) (((x) >> S_TIMERVALUE4) & M_TIMERVALUE4)

#define S_TIMERVALUE5    0
#define M_TIMERVALUE5    0xffffU
#define V_TIMERVALUE5(x) ((x) << S_TIMERVALUE5)
#define G_TIMERVALUE5(x) (((x) >> S_TIMERVALUE5) & M_TIMERVALUE5)

#define A_SGE_GK_CONTROL 0x10c4

#define S_EN_FLM_FIFTH    29
#define V_EN_FLM_FIFTH(x) ((x) << S_EN_FLM_FIFTH)
#define F_EN_FLM_FIFTH    V_EN_FLM_FIFTH(1U)

#define S_FL_PROG_THRESH    20
#define M_FL_PROG_THRESH    0x1ffU
#define V_FL_PROG_THRESH(x) ((x) << S_FL_PROG_THRESH)
#define G_FL_PROG_THRESH(x) (((x) >> S_FL_PROG_THRESH) & M_FL_PROG_THRESH)

#define S_COAL_ALL_THREAD    19
#define V_COAL_ALL_THREAD(x) ((x) << S_COAL_ALL_THREAD)
#define F_COAL_ALL_THREAD    V_COAL_ALL_THREAD(1U)

#define S_EN_PSHB    18
#define V_EN_PSHB(x) ((x) << S_EN_PSHB)
#define F_EN_PSHB    V_EN_PSHB(1U)

#define S_EN_DB_FIFTH    17
#define V_EN_DB_FIFTH(x) ((x) << S_EN_DB_FIFTH)
#define F_EN_DB_FIFTH    V_EN_DB_FIFTH(1U)

#define S_DB_PROG_THRESH    8
#define M_DB_PROG_THRESH    0x1ffU
#define V_DB_PROG_THRESH(x) ((x) << S_DB_PROG_THRESH)
#define G_DB_PROG_THRESH(x) (((x) >> S_DB_PROG_THRESH) & M_DB_PROG_THRESH)

#define S_100NS_TIMER    0
#define M_100NS_TIMER    0xffU
#define V_100NS_TIMER(x) ((x) << S_100NS_TIMER)
#define G_100NS_TIMER(x) (((x) >> S_100NS_TIMER) & M_100NS_TIMER)

#define A_SGE_GK_CONTROL2 0x10c8

#define S_DBQ_TIMER_TICK    16
#define M_DBQ_TIMER_TICK    0xffffU
#define V_DBQ_TIMER_TICK(x) ((x) << S_DBQ_TIMER_TICK)
#define G_DBQ_TIMER_TICK(x) (((x) >> S_DBQ_TIMER_TICK) & M_DBQ_TIMER_TICK)

#define S_FL_MERGE_CNT_THRESH    8
#define M_FL_MERGE_CNT_THRESH    0xfU
#define V_FL_MERGE_CNT_THRESH(x) ((x) << S_FL_MERGE_CNT_THRESH)
#define G_FL_MERGE_CNT_THRESH(x) (((x) >> S_FL_MERGE_CNT_THRESH) & M_FL_MERGE_CNT_THRESH)

#define S_MERGE_CNT_THRESH    0
#define M_MERGE_CNT_THRESH    0x3fU
#define V_MERGE_CNT_THRESH(x) ((x) << S_MERGE_CNT_THRESH)
#define G_MERGE_CNT_THRESH(x) (((x) >> S_MERGE_CNT_THRESH) & M_MERGE_CNT_THRESH)

#define A_SGE_DEBUG_INDEX 0x10cc
#define A_SGE_DEBUG_DATA_HIGH 0x10d0
#define A_SGE_DEBUG_DATA_LOW 0x10d4
#define A_SGE_INT_CAUSE4 0x10dc

#define S_ERR_BAD_UPFL_INC_CREDIT3    8
#define V_ERR_BAD_UPFL_INC_CREDIT3(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT3)
#define F_ERR_BAD_UPFL_INC_CREDIT3    V_ERR_BAD_UPFL_INC_CREDIT3(1U)

#define S_ERR_BAD_UPFL_INC_CREDIT2    7
#define V_ERR_BAD_UPFL_INC_CREDIT2(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT2)
#define F_ERR_BAD_UPFL_INC_CREDIT2    V_ERR_BAD_UPFL_INC_CREDIT2(1U)

#define S_ERR_BAD_UPFL_INC_CREDIT1    6
#define V_ERR_BAD_UPFL_INC_CREDIT1(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT1)
#define F_ERR_BAD_UPFL_INC_CREDIT1    V_ERR_BAD_UPFL_INC_CREDIT1(1U)

#define S_ERR_BAD_UPFL_INC_CREDIT0    5
#define V_ERR_BAD_UPFL_INC_CREDIT0(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT0)
#define F_ERR_BAD_UPFL_INC_CREDIT0    V_ERR_BAD_UPFL_INC_CREDIT0(1U)

#define S_ERR_PHYSADDR_LEN0_IDMA1    4
#define V_ERR_PHYSADDR_LEN0_IDMA1(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA1)
#define F_ERR_PHYSADDR_LEN0_IDMA1    V_ERR_PHYSADDR_LEN0_IDMA1(1U)

#define S_ERR_PHYSADDR_LEN0_IDMA0    3
#define V_ERR_PHYSADDR_LEN0_IDMA0(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA0)
#define F_ERR_PHYSADDR_LEN0_IDMA0    V_ERR_PHYSADDR_LEN0_IDMA0(1U)

#define S_ERR_FLM_INVALID_PKT_DROP1    2
#define V_ERR_FLM_INVALID_PKT_DROP1(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP1)
#define F_ERR_FLM_INVALID_PKT_DROP1    V_ERR_FLM_INVALID_PKT_DROP1(1U)

#define S_ERR_FLM_INVALID_PKT_DROP0    1
#define V_ERR_FLM_INVALID_PKT_DROP0(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP0)
#define F_ERR_FLM_INVALID_PKT_DROP0    V_ERR_FLM_INVALID_PKT_DROP0(1U)

#define S_ERR_UNEXPECTED_TIMER    0
#define V_ERR_UNEXPECTED_TIMER(x) ((x) << S_ERR_UNEXPECTED_TIMER)
#define F_ERR_UNEXPECTED_TIMER    V_ERR_UNEXPECTED_TIMER(1U)

#define S_BAR2_EGRESS_LEN_OR_ADDR_ERR    29
#define V_BAR2_EGRESS_LEN_OR_ADDR_ERR(x) ((x) << S_BAR2_EGRESS_LEN_OR_ADDR_ERR)
#define F_BAR2_EGRESS_LEN_OR_ADDR_ERR    V_BAR2_EGRESS_LEN_OR_ADDR_ERR(1U)

#define S_ERR_CPL_EXCEED_MAX_IQE_SIZE1    28
#define V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE1)
#define F_ERR_CPL_EXCEED_MAX_IQE_SIZE1    V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(1U)

#define S_ERR_CPL_EXCEED_MAX_IQE_SIZE0    27
#define V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE0)
#define F_ERR_CPL_EXCEED_MAX_IQE_SIZE0    V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(1U)

#define S_ERR_WR_LEN_TOO_LARGE3    26
#define V_ERR_WR_LEN_TOO_LARGE3(x) ((x) << S_ERR_WR_LEN_TOO_LARGE3)
#define F_ERR_WR_LEN_TOO_LARGE3    V_ERR_WR_LEN_TOO_LARGE3(1U)

#define S_ERR_WR_LEN_TOO_LARGE2    25
#define V_ERR_WR_LEN_TOO_LARGE2(x) ((x) << S_ERR_WR_LEN_TOO_LARGE2)
#define F_ERR_WR_LEN_TOO_LARGE2    V_ERR_WR_LEN_TOO_LARGE2(1U)

#define S_ERR_WR_LEN_TOO_LARGE1    24
#define V_ERR_WR_LEN_TOO_LARGE1(x) ((x) << S_ERR_WR_LEN_TOO_LARGE1)
#define F_ERR_WR_LEN_TOO_LARGE1    V_ERR_WR_LEN_TOO_LARGE1(1U)

#define S_ERR_WR_LEN_TOO_LARGE0    23
#define V_ERR_WR_LEN_TOO_LARGE0(x) ((x) << S_ERR_WR_LEN_TOO_LARGE0)
#define F_ERR_WR_LEN_TOO_LARGE0    V_ERR_WR_LEN_TOO_LARGE0(1U)

#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL3    22
#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL3)
#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL3    V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(1U)

#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL2    21
#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL2)
#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL2    V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(1U)

#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL1    20
#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL1)
#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL1    V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(1U)

#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL0    19
#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL0)
#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL0    V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(1U)

#define S_COAL_WITH_HP_DISABLE_ERR    18
#define V_COAL_WITH_HP_DISABLE_ERR(x) ((x) << S_COAL_WITH_HP_DISABLE_ERR)
#define F_COAL_WITH_HP_DISABLE_ERR    V_COAL_WITH_HP_DISABLE_ERR(1U)

#define S_BAR2_EGRESS_COAL0_ERR    17
#define V_BAR2_EGRESS_COAL0_ERR(x) ((x) << S_BAR2_EGRESS_COAL0_ERR)
#define F_BAR2_EGRESS_COAL0_ERR    V_BAR2_EGRESS_COAL0_ERR(1U)

#define S_BAR2_EGRESS_SIZE_ERR    16
#define V_BAR2_EGRESS_SIZE_ERR(x) ((x) << S_BAR2_EGRESS_SIZE_ERR)
#define F_BAR2_EGRESS_SIZE_ERR    V_BAR2_EGRESS_SIZE_ERR(1U)

#define S_FLM_PC_RSP_ERR    15
#define V_FLM_PC_RSP_ERR(x) ((x) << S_FLM_PC_RSP_ERR)
#define F_FLM_PC_RSP_ERR    V_FLM_PC_RSP_ERR(1U)

#define S_DBFIFO_HP_INT_LOW    14
#define V_DBFIFO_HP_INT_LOW(x) ((x) << S_DBFIFO_HP_INT_LOW)
#define F_DBFIFO_HP_INT_LOW    V_DBFIFO_HP_INT_LOW(1U)

#define S_DBFIFO_LP_INT_LOW    13
#define V_DBFIFO_LP_INT_LOW(x) ((x) << S_DBFIFO_LP_INT_LOW)
#define F_DBFIFO_LP_INT_LOW    V_DBFIFO_LP_INT_LOW(1U)

#define S_DBFIFO_FL_INT_LOW    12
#define V_DBFIFO_FL_INT_LOW(x) ((x) << S_DBFIFO_FL_INT_LOW)
#define F_DBFIFO_FL_INT_LOW    V_DBFIFO_FL_INT_LOW(1U)

#define S_DBFIFO_FL_INT    11
#define V_DBFIFO_FL_INT(x) ((x) << S_DBFIFO_FL_INT)
#define F_DBFIFO_FL_INT    V_DBFIFO_FL_INT(1U)

#define S_ERR_RX_CPL_PACKET_SIZE1    10
#define V_ERR_RX_CPL_PACKET_SIZE1(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE1)
#define F_ERR_RX_CPL_PACKET_SIZE1    V_ERR_RX_CPL_PACKET_SIZE1(1U)

#define S_ERR_RX_CPL_PACKET_SIZE0    9
#define V_ERR_RX_CPL_PACKET_SIZE0(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE0)
#define F_ERR_RX_CPL_PACKET_SIZE0    V_ERR_RX_CPL_PACKET_SIZE0(1U)

#define S_ERR_ISHIFT_UR1    31
#define V_ERR_ISHIFT_UR1(x) ((x) << S_ERR_ISHIFT_UR1)
#define F_ERR_ISHIFT_UR1    V_ERR_ISHIFT_UR1(1U)

#define S_ERR_ISHIFT_UR0    30
#define V_ERR_ISHIFT_UR0(x) ((x) << S_ERR_ISHIFT_UR0)
#define F_ERR_ISHIFT_UR0    V_ERR_ISHIFT_UR0(1U)

#define S_ERR_TH3_MAX_FETCH    14
#define V_ERR_TH3_MAX_FETCH(x) ((x) << S_ERR_TH3_MAX_FETCH)
#define F_ERR_TH3_MAX_FETCH    V_ERR_TH3_MAX_FETCH(1U)

#define S_ERR_TH2_MAX_FETCH    13
#define V_ERR_TH2_MAX_FETCH(x) ((x) << S_ERR_TH2_MAX_FETCH)
#define F_ERR_TH2_MAX_FETCH    V_ERR_TH2_MAX_FETCH(1U)

#define S_ERR_TH1_MAX_FETCH    12
#define V_ERR_TH1_MAX_FETCH(x) ((x) << S_ERR_TH1_MAX_FETCH)
#define F_ERR_TH1_MAX_FETCH    V_ERR_TH1_MAX_FETCH(1U)

#define S_ERR_TH0_MAX_FETCH    11
#define V_ERR_TH0_MAX_FETCH(x) ((x) << S_ERR_TH0_MAX_FETCH)
#define F_ERR_TH0_MAX_FETCH    V_ERR_TH0_MAX_FETCH(1U)

#define A_SGE_INT_ENABLE4 0x10e0
#define A_SGE_STAT_TOTAL 0x10e4
#define A_SGE_STAT_MATCH 0x10e8
#define A_SGE_STAT_CFG 0x10ec

#define S_STATMODE    2
#define M_STATMODE    0x3U
#define V_STATMODE(x) ((x) << S_STATMODE)
#define G_STATMODE(x) (((x) >> S_STATMODE) & M_STATMODE)

#define S_STATSOURCE    0
#define M_STATSOURCE    0x3U
#define V_STATSOURCE(x) ((x) << S_STATSOURCE)
#define G_STATSOURCE(x) (((x) >> S_STATSOURCE) & M_STATSOURCE)

#define S_STATSOURCE_T5    9
#define M_STATSOURCE_T5    0xfU
#define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
#define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5)

#define S_ITPOPMODE    8
#define V_ITPOPMODE(x) ((x) << S_ITPOPMODE)
#define F_ITPOPMODE    V_ITPOPMODE(1U)

#define S_EGRCTXTOPMODE    6
#define M_EGRCTXTOPMODE    0x3U
#define V_EGRCTXTOPMODE(x) ((x) << S_EGRCTXTOPMODE)
#define G_EGRCTXTOPMODE(x) (((x) >> S_EGRCTXTOPMODE) & M_EGRCTXTOPMODE)

#define S_INGCTXTOPMODE    4
#define M_INGCTXTOPMODE    0x3U
#define V_INGCTXTOPMODE(x) ((x) << S_INGCTXTOPMODE)
#define G_INGCTXTOPMODE(x) (((x) >> S_INGCTXTOPMODE) & M_INGCTXTOPMODE)

#define S_T6_STATMODE    0
#define M_T6_STATMODE    0xfU
#define V_T6_STATMODE(x) ((x) << S_T6_STATMODE)
#define G_T6_STATMODE(x) (((x) >> S_T6_STATMODE) & M_T6_STATMODE)

#define A_SGE_HINT_CFG 0x10f0

#define S_UPCUTOFFTHRESHLP    12
#define M_UPCUTOFFTHRESHLP    0x7ffU
#define V_UPCUTOFFTHRESHLP(x) ((x) << S_UPCUTOFFTHRESHLP)
#define G_UPCUTOFFTHRESHLP(x) (((x) >> S_UPCUTOFFTHRESHLP) & M_UPCUTOFFTHRESHLP)

#define S_HINTSALLOWEDNOHDR    6
#define M_HINTSALLOWEDNOHDR    0x3fU
#define V_HINTSALLOWEDNOHDR(x) ((x) << S_HINTSALLOWEDNOHDR)
#define G_HINTSALLOWEDNOHDR(x) (((x) >> S_HINTSALLOWEDNOHDR) & M_HINTSALLOWEDNOHDR)

#define S_HINTSALLOWEDHDR    0
#define M_HINTSALLOWEDHDR    0x3fU
#define V_HINTSALLOWEDHDR(x) ((x) << S_HINTSALLOWEDHDR)
#define G_HINTSALLOWEDHDR(x) (((x) >> S_HINTSALLOWEDHDR) & M_HINTSALLOWEDHDR)

#define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
#define A_SGE_INGRESS_QUEUES_PER_PAGE_VF 0x10f8
#define A_SGE_ERROR_STATS 0x1100

#define S_UNCAPTURED_ERROR    18
#define V_UNCAPTURED_ERROR(x) ((x) << S_UNCAPTURED_ERROR)
#define F_UNCAPTURED_ERROR    V_UNCAPTURED_ERROR(1U)

#define S_ERROR_QID_VALID    17
#define V_ERROR_QID_VALID(x) ((x) << S_ERROR_QID_VALID)
#define F_ERROR_QID_VALID    V_ERROR_QID_VALID(1U)

#define S_ERROR_QID    0
#define M_ERROR_QID    0x1ffffU
#define V_ERROR_QID(x) ((x) << S_ERROR_QID)
#define G_ERROR_QID(x) (((x) >> S_ERROR_QID) & M_ERROR_QID)

#define S_CAUSE_REGISTER    24
#define M_CAUSE_REGISTER    0x7U
#define V_CAUSE_REGISTER(x) ((x) << S_CAUSE_REGISTER)
#define G_CAUSE_REGISTER(x) (((x) >> S_CAUSE_REGISTER) & M_CAUSE_REGISTER)

#define S_CAUSE_BIT    19
#define M_CAUSE_BIT    0x1fU
#define V_CAUSE_BIT(x) ((x) << S_CAUSE_BIT)
#define G_CAUSE_BIT(x) (((x) >> S_CAUSE_BIT) & M_CAUSE_BIT)

#define A_SGE_IDMA0_DROP_CNT 0x1104
#define A_SGE_IDMA1_DROP_CNT 0x1108
#define A_SGE_INT_CAUSE5 0x110c

#define S_ERR_T_RXCRC    31
#define V_ERR_T_RXCRC(x) ((x) << S_ERR_T_RXCRC)
#define F_ERR_T_RXCRC    V_ERR_T_RXCRC(1U)

#define S_PERR_MC_RSPDATA    30
#define V_PERR_MC_RSPDATA(x) ((x) << S_PERR_MC_RSPDATA)
#define F_PERR_MC_RSPDATA    V_PERR_MC_RSPDATA(1U)

#define S_PERR_PC_RSPDATA    29
#define V_PERR_PC_RSPDATA(x) ((x) << S_PERR_PC_RSPDATA)
#define F_PERR_PC_RSPDATA    V_PERR_PC_RSPDATA(1U)

#define S_PERR_PD_RDRSPDATA    28
#define V_PERR_PD_RDRSPDATA(x) ((x) << S_PERR_PD_RDRSPDATA)
#define F_PERR_PD_RDRSPDATA    V_PERR_PD_RDRSPDATA(1U)

#define S_PERR_U_RXDATA    27
#define V_PERR_U_RXDATA(x) ((x) << S_PERR_U_RXDATA)
#define F_PERR_U_RXDATA    V_PERR_U_RXDATA(1U)

#define S_PERR_UD_RXDATA    26
#define V_PERR_UD_RXDATA(x) ((x) << S_PERR_UD_RXDATA)
#define F_PERR_UD_RXDATA    V_PERR_UD_RXDATA(1U)

#define S_PERR_UP_DATA    25
#define V_PERR_UP_DATA(x) ((x) << S_PERR_UP_DATA)
#define F_PERR_UP_DATA    V_PERR_UP_DATA(1U)

#define S_PERR_CIM2SGE_RXDATA    24
#define V_PERR_CIM2SGE_RXDATA(x) ((x) << S_PERR_CIM2SGE_RXDATA)
#define F_PERR_CIM2SGE_RXDATA    V_PERR_CIM2SGE_RXDATA(1U)

#define S_PERR_HINT_DELAY_FIFO1_T5    23
#define V_PERR_HINT_DELAY_FIFO1_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO1_T5)
#define F_PERR_HINT_DELAY_FIFO1_T5    V_PERR_HINT_DELAY_FIFO1_T5(1U)

#define S_PERR_HINT_DELAY_FIFO0_T5    22
#define V_PERR_HINT_DELAY_FIFO0_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO0_T5)
#define F_PERR_HINT_DELAY_FIFO0_T5    V_PERR_HINT_DELAY_FIFO0_T5(1U)

#define S_PERR_IMSG_PD_FIFO_T5    21
#define V_PERR_IMSG_PD_FIFO_T5(x) ((x) << S_PERR_IMSG_PD_FIFO_T5)
#define F_PERR_IMSG_PD_FIFO_T5    V_PERR_IMSG_PD_FIFO_T5(1U)

#define S_PERR_ULPTX_FIFO1_T5    20
#define V_PERR_ULPTX_FIFO1_T5(x) ((x) << S_PERR_ULPTX_FIFO1_T5)
#define F_PERR_ULPTX_FIFO1_T5    V_PERR_ULPTX_FIFO1_T5(1U)

#define S_PERR_ULPTX_FIFO0_T5    19
#define V_PERR_ULPTX_FIFO0_T5(x) ((x) << S_PERR_ULPTX_FIFO0_T5)
#define F_PERR_ULPTX_FIFO0_T5    V_PERR_ULPTX_FIFO0_T5(1U)

#define S_PERR_IDMA2IMSG_FIFO1_T5    18
#define V_PERR_IDMA2IMSG_FIFO1_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO1_T5)
#define F_PERR_IDMA2IMSG_FIFO1_T5    V_PERR_IDMA2IMSG_FIFO1_T5(1U)

#define S_PERR_IDMA2IMSG_FIFO0_T5    17
#define V_PERR_IDMA2IMSG_FIFO0_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO0_T5)
#define F_PERR_IDMA2IMSG_FIFO0_T5    V_PERR_IDMA2IMSG_FIFO0_T5(1U)

#define S_PERR_POINTER_DATA_FIFO0    16
#define V_PERR_POINTER_DATA_FIFO0(x) ((x) << S_PERR_POINTER_DATA_FIFO0)
#define F_PERR_POINTER_DATA_FIFO0    V_PERR_POINTER_DATA_FIFO0(1U)

#define S_PERR_POINTER_DATA_FIFO1    15
#define V_PERR_POINTER_DATA_FIFO1(x) ((x) << S_PERR_POINTER_DATA_FIFO1)
#define F_PERR_POINTER_DATA_FIFO1    V_PERR_POINTER_DATA_FIFO1(1U)

#define S_PERR_POINTER_HDR_FIFO0    14
#define V_PERR_POINTER_HDR_FIFO0(x) ((x) << S_PERR_POINTER_HDR_FIFO0)
#define F_PERR_POINTER_HDR_FIFO0    V_PERR_POINTER_HDR_FIFO0(1U)

#define S_PERR_POINTER_HDR_FIFO1    13
#define V_PERR_POINTER_HDR_FIFO1(x) ((x) << S_PERR_POINTER_HDR_FIFO1)
#define F_PERR_POINTER_HDR_FIFO1    V_PERR_POINTER_HDR_FIFO1(1U)

#define S_PERR_PAYLOAD_FIFO0    12
#define V_PERR_PAYLOAD_FIFO0(x) ((x) << S_PERR_PAYLOAD_FIFO0)
#define F_PERR_PAYLOAD_FIFO0    V_PERR_PAYLOAD_FIFO0(1U)

#define S_PERR_PAYLOAD_FIFO1    11
#define V_PERR_PAYLOAD_FIFO1(x) ((x) << S_PERR_PAYLOAD_FIFO1)
#define F_PERR_PAYLOAD_FIFO1    V_PERR_PAYLOAD_FIFO1(1U)

#define S_PERR_EDMA_INPUT_FIFO3    10
#define V_PERR_EDMA_INPUT_FIFO3(x) ((x) << S_PERR_EDMA_INPUT_FIFO3)
#define F_PERR_EDMA_INPUT_FIFO3    V_PERR_EDMA_INPUT_FIFO3(1U)

#define S_PERR_EDMA_INPUT_FIFO2    9
#define V_PERR_EDMA_INPUT_FIFO2(x) ((x) << S_PERR_EDMA_INPUT_FIFO2)
#define F_PERR_EDMA_INPUT_FIFO2    V_PERR_EDMA_INPUT_FIFO2(1U)

#define S_PERR_EDMA_INPUT_FIFO1    8
#define V_PERR_EDMA_INPUT_FIFO1(x) ((x) << S_PERR_EDMA_INPUT_FIFO1)
#define F_PERR_EDMA_INPUT_FIFO1    V_PERR_EDMA_INPUT_FIFO1(1U)

#define S_PERR_EDMA_INPUT_FIFO0    7
#define V_PERR_EDMA_INPUT_FIFO0(x) ((x) << S_PERR_EDMA_INPUT_FIFO0)
#define F_PERR_EDMA_INPUT_FIFO0    V_PERR_EDMA_INPUT_FIFO0(1U)

#define S_PERR_MGT_BAR2_FIFO    6
#define V_PERR_MGT_BAR2_FIFO(x) ((x) << S_PERR_MGT_BAR2_FIFO)
#define F_PERR_MGT_BAR2_FIFO    V_PERR_MGT_BAR2_FIFO(1U)

#define S_PERR_HEADERSPLIT_FIFO1_T5    5
#define V_PERR_HEADERSPLIT_FIFO1_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO1_T5)
#define F_PERR_HEADERSPLIT_FIFO1_T5    V_PERR_HEADERSPLIT_FIFO1_T5(1U)

#define S_PERR_HEADERSPLIT_FIFO0_T5    4
#define V_PERR_HEADERSPLIT_FIFO0_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO0_T5)
#define F_PERR_HEADERSPLIT_FIFO0_T5    V_PERR_HEADERSPLIT_FIFO0_T5(1U)

#define S_PERR_CIM_FIFO1    3
#define V_PERR_CIM_FIFO1(x) ((x) << S_PERR_CIM_FIFO1)
#define F_PERR_CIM_FIFO1    V_PERR_CIM_FIFO1(1U)

#define S_PERR_CIM_FIFO0    2
#define V_PERR_CIM_FIFO0(x) ((x) << S_PERR_CIM_FIFO0)
#define F_PERR_CIM_FIFO0    V_PERR_CIM_FIFO0(1U)

#define S_PERR_IDMA_SWITCH_OUTPUT_FIFO1    1
#define V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO1)
#define F_PERR_IDMA_SWITCH_OUTPUT_FIFO1    V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(1U)

#define S_PERR_IDMA_SWITCH_OUTPUT_FIFO0    0
#define V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO0)
#define F_PERR_IDMA_SWITCH_OUTPUT_FIFO0    V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(1U)

#define A_SGE_INT_ENABLE5 0x1110
#define A_SGE_PERR_ENABLE5 0x1114
#define A_SGE_DBFIFO_STATUS2 0x1118

#define S_FL_INT_THRESH    24
#define M_FL_INT_THRESH    0xfU
#define V_FL_INT_THRESH(x) ((x) << S_FL_INT_THRESH)
#define G_FL_INT_THRESH(x) (((x) >> S_FL_INT_THRESH) & M_FL_INT_THRESH)

#define S_FL_COUNT    14
#define M_FL_COUNT    0x3ffU
#define V_FL_COUNT(x) ((x) << S_FL_COUNT)
#define G_FL_COUNT(x) (((x) >> S_FL_COUNT) & M_FL_COUNT)

#define S_HP_INT_THRESH_T5    10
#define M_HP_INT_THRESH_T5    0xfU
#define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
#define G_HP_INT_THRESH_T5(x) (((x) >> S_HP_INT_THRESH_T5) & M_HP_INT_THRESH_T5)

#define S_HP_COUNT_T5    0
#define M_HP_COUNT_T5    0x3ffU
#define V_HP_COUNT_T5(x) ((x) << S_HP_COUNT_T5)
#define G_HP_COUNT_T5(x) (((x) >> S_HP_COUNT_T5) & M_HP_COUNT_T5)

#define A_SGE_FETCH_BURST_MAX_0_AND_1 0x111c

#define S_FETCHBURSTMAX0    16
#define M_FETCHBURSTMAX0    0x3ffU
#define V_FETCHBURSTMAX0(x) ((x) << S_FETCHBURSTMAX0)
#define G_FETCHBURSTMAX0(x) (((x) >> S_FETCHBURSTMAX0) & M_FETCHBURSTMAX0)

#define S_FETCHBURSTMAX1    0
#define M_FETCHBURSTMAX1    0x3ffU
#define V_FETCHBURSTMAX1(x) ((x) << S_FETCHBURSTMAX1)
#define G_FETCHBURSTMAX1(x) (((x) >> S_FETCHBURSTMAX1) & M_FETCHBURSTMAX1)

#define A_SGE_FETCH_BURST_MAX_2_AND_3 0x1120

#define S_FETCHBURSTMAX2    16
#define M_FETCHBURSTMAX2    0x3ffU
#define V_FETCHBURSTMAX2(x) ((x) << S_FETCHBURSTMAX2)
#define G_FETCHBURSTMAX2(x) (((x) >> S_FETCHBURSTMAX2) & M_FETCHBURSTMAX2)

#define S_FETCHBURSTMAX3    0
#define M_FETCHBURSTMAX3    0x3ffU
#define V_FETCHBURSTMAX3(x) ((x) << S_FETCHBURSTMAX3)
#define G_FETCHBURSTMAX3(x) (((x) >> S_FETCHBURSTMAX3) & M_FETCHBURSTMAX3)

#define A_SGE_CONTROL2 0x1124

#define S_INGPACKBOUNDARY    16
#define M_INGPACKBOUNDARY    0x7U
#define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY)
#define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY)

#define S_VFIFO_ENABLE    10
#define V_VFIFO_ENABLE(x) ((x) << S_VFIFO_ENABLE)
#define F_VFIFO_ENABLE    V_VFIFO_ENABLE(1U)

#define S_FLM_RESCHEDULE_MODE    9
#define V_FLM_RESCHEDULE_MODE(x) ((x) << S_FLM_RESCHEDULE_MODE)
#define F_FLM_RESCHEDULE_MODE    V_FLM_RESCHEDULE_MODE(1U)

#define S_HINTDEPTHCTLFL    4
#define M_HINTDEPTHCTLFL    0x1fU
#define V_HINTDEPTHCTLFL(x) ((x) << S_HINTDEPTHCTLFL)
#define G_HINTDEPTHCTLFL(x) (((x) >> S_HINTDEPTHCTLFL) & M_HINTDEPTHCTLFL)

#define S_FORCE_ORDERING    3
#define V_FORCE_ORDERING(x) ((x) << S_FORCE_ORDERING)
#define F_FORCE_ORDERING    V_FORCE_ORDERING(1U)

#define S_TX_COALESCE_SIZE    2
#define V_TX_COALESCE_SIZE(x) ((x) << S_TX_COALESCE_SIZE)
#define F_TX_COALESCE_SIZE    V_TX_COALESCE_SIZE(1U)

#define S_COAL_STRICT_CIM_PRI    1
#define V_COAL_STRICT_CIM_PRI(x) ((x) << S_COAL_STRICT_CIM_PRI)
#define F_COAL_STRICT_CIM_PRI    V_COAL_STRICT_CIM_PRI(1U)

#define S_TX_COALESCE_PRI    0
#define V_TX_COALESCE_PRI(x) ((x) << S_TX_COALESCE_PRI)
#define F_TX_COALESCE_PRI    V_TX_COALESCE_PRI(1U)

#define S_UPFLCUTOFFDIS    21
#define V_UPFLCUTOFFDIS(x) ((x) << S_UPFLCUTOFFDIS)
#define F_UPFLCUTOFFDIS    V_UPFLCUTOFFDIS(1U)

#define S_RXCPLSIZEAUTOCORRECT    20
#define V_RXCPLSIZEAUTOCORRECT(x) ((x) << S_RXCPLSIZEAUTOCORRECT)
#define F_RXCPLSIZEAUTOCORRECT    V_RXCPLSIZEAUTOCORRECT(1U)

#define S_IDMAARBROUNDROBIN    19
#define V_IDMAARBROUNDROBIN(x) ((x) << S_IDMAARBROUNDROBIN)
#define F_IDMAARBROUNDROBIN    V_IDMAARBROUNDROBIN(1U)

#define S_CGEN_EGRESS_CONTEXT    15
#define V_CGEN_EGRESS_CONTEXT(x) ((x) << S_CGEN_EGRESS_CONTEXT)
#define F_CGEN_EGRESS_CONTEXT    V_CGEN_EGRESS_CONTEXT(1U)

#define S_CGEN_INGRESS_CONTEXT    14
#define V_CGEN_INGRESS_CONTEXT(x) ((x) << S_CGEN_INGRESS_CONTEXT)
#define F_CGEN_INGRESS_CONTEXT    V_CGEN_INGRESS_CONTEXT(1U)

#define S_CGEN_IDMA    13
#define V_CGEN_IDMA(x) ((x) << S_CGEN_IDMA)
#define F_CGEN_IDMA    V_CGEN_IDMA(1U)

#define S_CGEN_DBP    12
#define V_CGEN_DBP(x) ((x) << S_CGEN_DBP)
#define F_CGEN_DBP    V_CGEN_DBP(1U)

#define S_CGEN_EDMA    11
#define V_CGEN_EDMA(x) ((x) << S_CGEN_EDMA)
#define F_CGEN_EDMA    V_CGEN_EDMA(1U)

#define A_SGE_INT_CAUSE6 0x1128

#define S_ERR_DB_SYNC    21
#define V_ERR_DB_SYNC(x) ((x) << S_ERR_DB_SYNC)
#define F_ERR_DB_SYNC    V_ERR_DB_SYNC(1U)

#define S_ERR_GTS_SYNC    20
#define V_ERR_GTS_SYNC(x) ((x) << S_ERR_GTS_SYNC)
#define F_ERR_GTS_SYNC    V_ERR_GTS_SYNC(1U)

#define S_FATAL_LARGE_COAL    19
#define V_FATAL_LARGE_COAL(x) ((x) << S_FATAL_LARGE_COAL)
#define F_FATAL_LARGE_COAL    V_FATAL_LARGE_COAL(1U)

#define S_PL_BAR2_FRM_ERR    18
#define V_PL_BAR2_FRM_ERR(x) ((x) << S_PL_BAR2_FRM_ERR)
#define F_PL_BAR2_FRM_ERR    V_PL_BAR2_FRM_ERR(1U)

#define S_SILENT_DROP_TX_COAL    17
#define V_SILENT_DROP_TX_COAL(x) ((x) << S_SILENT_DROP_TX_COAL)
#define F_SILENT_DROP_TX_COAL    V_SILENT_DROP_TX_COAL(1U)

#define S_ERR_INV_CTXT4    16
#define V_ERR_INV_CTXT4(x) ((x) << S_ERR_INV_CTXT4)
#define F_ERR_INV_CTXT4    V_ERR_INV_CTXT4(1U)

#define S_ERR_BAD_DB_PIDX4    15
#define V_ERR_BAD_DB_PIDX4(x) ((x) << S_ERR_BAD_DB_PIDX4)
#define F_ERR_BAD_DB_PIDX4    V_ERR_BAD_DB_PIDX4(1U)

#define S_ERR_BAD_UPFL_INC_CREDIT4    14
#define V_ERR_BAD_UPFL_INC_CREDIT4(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT4)
#define F_ERR_BAD_UPFL_INC_CREDIT4    V_ERR_BAD_UPFL_INC_CREDIT4(1U)

#define S_ERR_PC_RSP_LEN3    11
#define V_ERR_PC_RSP_LEN3(x) ((x) << S_ERR_PC_RSP_LEN3)
#define F_ERR_PC_RSP_LEN3    V_ERR_PC_RSP_LEN3(1U)

#define S_ERR_PC_RSP_LEN2    10
#define V_ERR_PC_RSP_LEN2(x) ((x) << S_ERR_PC_RSP_LEN2)
#define F_ERR_PC_RSP_LEN2    V_ERR_PC_RSP_LEN2(1U)

#define S_ERR_PC_RSP_LEN1    9
#define V_ERR_PC_RSP_LEN1(x) ((x) << S_ERR_PC_RSP_LEN1)
#define F_ERR_PC_RSP_LEN1    V_ERR_PC_RSP_LEN1(1U)

#define S_ERR_PC_RSP_LEN0    8
#define V_ERR_PC_RSP_LEN0(x) ((x) << S_ERR_PC_RSP_LEN0)
#define F_ERR_PC_RSP_LEN0    V_ERR_PC_RSP_LEN0(1U)

#define S_FATAL_ENQ2LL_VLD    7
#define V_FATAL_ENQ2LL_VLD(x) ((x) << S_FATAL_ENQ2LL_VLD)
#define F_FATAL_ENQ2LL_VLD    V_FATAL_ENQ2LL_VLD(1U)

#define S_FATAL_LL_EMPTY    6
#define V_FATAL_LL_EMPTY(x) ((x) << S_FATAL_LL_EMPTY)
#define F_FATAL_LL_EMPTY    V_FATAL_LL_EMPTY(1U)

#define S_FATAL_OFF_WDENQ    5
#define V_FATAL_OFF_WDENQ(x) ((x) << S_FATAL_OFF_WDENQ)
#define F_FATAL_OFF_WDENQ    V_FATAL_OFF_WDENQ(1U)

#define S_FATAL_DEQ_DRDY    3
#define M_FATAL_DEQ_DRDY    0x3U
#define V_FATAL_DEQ_DRDY(x) ((x) << S_FATAL_DEQ_DRDY)
#define G_FATAL_DEQ_DRDY(x) (((x) >> S_FATAL_DEQ_DRDY) & M_FATAL_DEQ_DRDY)

#define S_FATAL_OUTP_DRDY    1
#define M_FATAL_OUTP_DRDY    0x3U
#define V_FATAL_OUTP_DRDY(x) ((x) << S_FATAL_OUTP_DRDY)
#define G_FATAL_OUTP_DRDY(x) (((x) >> S_FATAL_OUTP_DRDY) & M_FATAL_OUTP_DRDY)

#define S_FATAL_DEQ    0
#define V_FATAL_DEQ(x) ((x) << S_FATAL_DEQ)
#define F_FATAL_DEQ    V_FATAL_DEQ(1U)

#define A_SGE_INT_ENABLE6 0x112c

#define S_FATAL_TAG_MISMATCH    13
#define V_FATAL_TAG_MISMATCH(x) ((x) << S_FATAL_TAG_MISMATCH)
#define F_FATAL_TAG_MISMATCH    V_FATAL_TAG_MISMATCH(1U)

#define S_FATAL_ENQ_CTL_RDY    12
#define V_FATAL_ENQ_CTL_RDY(x) ((x) << S_FATAL_ENQ_CTL_RDY)
#define F_FATAL_ENQ_CTL_RDY    V_FATAL_ENQ_CTL_RDY(1U)

#define A_SGE_DBVFIFO_BADDR 0x1138
#define A_SGE_DBVFIFO_SIZE 0x113c

#define S_DBVFIFO_SIZE    6
#define M_DBVFIFO_SIZE    0xfffU
#define V_DBVFIFO_SIZE(x) ((x) << S_DBVFIFO_SIZE)
#define G_DBVFIFO_SIZE(x) (((x) >> S_DBVFIFO_SIZE) & M_DBVFIFO_SIZE)

#define S_T6_DBVFIFO_SIZE    0
#define M_T6_DBVFIFO_SIZE    0x1fffU
#define V_T6_DBVFIFO_SIZE(x) ((x) << S_T6_DBVFIFO_SIZE)
#define G_T6_DBVFIFO_SIZE(x) (((x) >> S_T6_DBVFIFO_SIZE) & M_T6_DBVFIFO_SIZE)

#define A_SGE_DBFIFO_STATUS3 0x1140

#define S_LP_PTRS_EQUAL    21
#define V_LP_PTRS_EQUAL(x) ((x) << S_LP_PTRS_EQUAL)
#define F_LP_PTRS_EQUAL    V_LP_PTRS_EQUAL(1U)

#define S_LP_SNAPHOT    20
#define V_LP_SNAPHOT(x) ((x) << S_LP_SNAPHOT)
#define F_LP_SNAPHOT    V_LP_SNAPHOT(1U)

#define S_FL_INT_THRESH_LOW    16
#define M_FL_INT_THRESH_LOW    0xfU
#define V_FL_INT_THRESH_LOW(x) ((x) << S_FL_INT_THRESH_LOW)
#define G_FL_INT_THRESH_LOW(x) (((x) >> S_FL_INT_THRESH_LOW) & M_FL_INT_THRESH_LOW)

#define S_HP_INT_THRESH_LOW    12
#define M_HP_INT_THRESH_LOW    0xfU
#define V_HP_INT_THRESH_LOW(x) ((x) << S_HP_INT_THRESH_LOW)
#define G_HP_INT_THRESH_LOW(x) (((x) >> S_HP_INT_THRESH_LOW) & M_HP_INT_THRESH_LOW)

#define S_LP_INT_THRESH_LOW    0
#define M_LP_INT_THRESH_LOW    0xfffU
#define V_LP_INT_THRESH_LOW(x) ((x) << S_LP_INT_THRESH_LOW)
#define G_LP_INT_THRESH_LOW(x) (((x) >> S_LP_INT_THRESH_LOW) & M_LP_INT_THRESH_LOW)

#define A_SGE_CHANGESET 0x1144
#define A_SGE_PC_RSP_ERROR 0x1148
#define A_SGE_TBUF_CONTROL 0x114c

#define S_DBPTBUFRSV1    9
#define M_DBPTBUFRSV1    0x1ffU
#define V_DBPTBUFRSV1(x) ((x) << S_DBPTBUFRSV1)
#define G_DBPTBUFRSV1(x) (((x) >> S_DBPTBUFRSV1) & M_DBPTBUFRSV1)

#define S_DBPTBUFRSV0    0
#define M_DBPTBUFRSV0    0x1ffU
#define V_DBPTBUFRSV0(x) ((x) << S_DBPTBUFRSV0)
#define G_DBPTBUFRSV0(x) (((x) >> S_DBPTBUFRSV0) & M_DBPTBUFRSV0)

#define A_SGE_PC0_REQ_BIST_CMD 0x1180
#define A_SGE_PC0_REQ_BIST_ERROR_CNT 0x1184
#define A_SGE_PC1_REQ_BIST_CMD 0x1190
#define A_SGE_PC1_REQ_BIST_ERROR_CNT 0x1194
#define A_SGE_PC0_RSP_BIST_CMD 0x11a0
#define A_SGE_PC0_RSP_BIST_ERROR_CNT 0x11a4
#define A_SGE_PC1_RSP_BIST_CMD 0x11b0
#define A_SGE_PC1_RSP_BIST_ERROR_CNT 0x11b4
#define A_SGE_CTXT_CMD 0x11fc

#define S_BUSY    31
#define V_BUSY(x) ((x) << S_BUSY)
#define F_BUSY    V_BUSY(1U)

#define S_CTXTOP    28
#define M_CTXTOP    0x3U
#define V_CTXTOP(x) ((x) << S_CTXTOP)
#define G_CTXTOP(x) (((x) >> S_CTXTOP) & M_CTXTOP)

#define S_CTXTTYPE    24
#define M_CTXTTYPE    0x3U
#define V_CTXTTYPE(x) ((x) << S_CTXTTYPE)
#define G_CTXTTYPE(x) (((x) >> S_CTXTTYPE) & M_CTXTTYPE)

#define S_CTXTQID    0
#define M_CTXTQID    0x1ffffU
#define V_CTXTQID(x) ((x) << S_CTXTQID)
#define G_CTXTQID(x) (((x) >> S_CTXTQID) & M_CTXTQID)

#define A_SGE_CTXT_DATA0 0x1200
#define A_SGE_CTXT_DATA1 0x1204
#define A_SGE_CTXT_DATA2 0x1208
#define A_SGE_CTXT_DATA3 0x120c
#define A_SGE_CTXT_DATA4 0x1210
#define A_SGE_CTXT_DATA5 0x1214
#define A_SGE_CTXT_DATA6 0x1218
#define A_SGE_CTXT_DATA7 0x121c
#define A_SGE_CTXT_MASK0 0x1220
#define A_SGE_CTXT_MASK1 0x1224
#define A_SGE_CTXT_MASK2 0x1228
#define A_SGE_CTXT_MASK3 0x122c
#define A_SGE_CTXT_MASK4 0x1230
#define A_SGE_CTXT_MASK5 0x1234
#define A_SGE_CTXT_MASK6 0x1238
#define A_SGE_CTXT_MASK7 0x123c
#define A_SGE_QBASE_MAP0 0x1240

#define S_EGRESS0_SIZE    24
#define M_EGRESS0_SIZE    0x1fU
#define V_EGRESS0_SIZE(x) ((x) << S_EGRESS0_SIZE)
#define G_EGRESS0_SIZE(x) (((x) >> S_EGRESS0_SIZE) & M_EGRESS0_SIZE)

#define S_EGRESS1_SIZE    16
#define M_EGRESS1_SIZE    0x1fU
#define V_EGRESS1_SIZE(x) ((x) << S_EGRESS1_SIZE)
#define G_EGRESS1_SIZE(x) (((x) >> S_EGRESS1_SIZE) & M_EGRESS1_SIZE)

#define S_INGRESS0_SIZE    8
#define M_INGRESS0_SIZE    0x1fU
#define V_INGRESS0_SIZE(x) ((x) << S_INGRESS0_SIZE)
#define G_INGRESS0_SIZE(x) (((x) >> S_INGRESS0_SIZE) & M_INGRESS0_SIZE)

#define S_INGRESS1_SIZE    0
#define M_INGRESS1_SIZE    0x1fU
#define V_INGRESS1_SIZE(x) ((x) << S_INGRESS1_SIZE)
#define G_INGRESS1_SIZE(x) (((x) >> S_INGRESS1_SIZE) & M_INGRESS1_SIZE)

#define A_SGE_QBASE_MAP1 0x1244

#define S_EGRESS0_BASE    0
#define M_EGRESS0_BASE    0x1ffffU
#define V_EGRESS0_BASE(x) ((x) << S_EGRESS0_BASE)
#define G_EGRESS0_BASE(x) (((x) >> S_EGRESS0_BASE) & M_EGRESS0_BASE)

#define A_SGE_QBASE_MAP2 0x1248

#define S_EGRESS1_BASE    0
#define M_EGRESS1_BASE    0x1ffffU
#define V_EGRESS1_BASE(x) ((x) << S_EGRESS1_BASE)
#define G_EGRESS1_BASE(x) (((x) >> S_EGRESS1_BASE) & M_EGRESS1_BASE)

#define A_SGE_QBASE_MAP3 0x124c

#define S_INGRESS1_BASE_256VF    16
#define M_INGRESS1_BASE_256VF    0xffffU
#define V_INGRESS1_BASE_256VF(x) ((x) << S_INGRESS1_BASE_256VF)
#define G_INGRESS1_BASE_256VF(x) (((x) >> S_INGRESS1_BASE_256VF) & M_INGRESS1_BASE_256VF)

#define S_INGRESS0_BASE    0
#define M_INGRESS0_BASE    0xffffU
#define V_INGRESS0_BASE(x) ((x) << S_INGRESS0_BASE)
#define G_INGRESS0_BASE(x) (((x) >> S_INGRESS0_BASE) & M_INGRESS0_BASE)

#define A_SGE_QBASE_INDEX 0x1250

#define S_QIDX    0
#define M_QIDX    0x1ffU
#define V_QIDX(x) ((x) << S_QIDX)
#define G_QIDX(x) (((x) >> S_QIDX) & M_QIDX)

#define A_SGE_CONM_CTRL2 0x1254

#define S_FLMTHRESHPACK    8
#define M_FLMTHRESHPACK    0x7fU
#define V_FLMTHRESHPACK(x) ((x) << S_FLMTHRESHPACK)
#define G_FLMTHRESHPACK(x) (((x) >> S_FLMTHRESHPACK) & M_FLMTHRESHPACK)

#define S_FLMTHRESH    0
#define M_FLMTHRESH    0x7fU
#define V_FLMTHRESH(x) ((x) << S_FLMTHRESH)
#define G_FLMTHRESH(x) (((x) >> S_FLMTHRESH) & M_FLMTHRESH)

#define A_SGE_DEBUG_CONM 0x1258

#define S_MPS_CH_CNG    16
#define M_MPS_CH_CNG    0xffffU
#define V_MPS_CH_CNG(x) ((x) << S_MPS_CH_CNG)
#define G_MPS_CH_CNG(x) (((x) >> S_MPS_CH_CNG) & M_MPS_CH_CNG)

#define S_TP_CH_CNG    14
#define M_TP_CH_CNG    0x3U
#define V_TP_CH_CNG(x) ((x) << S_TP_CH_CNG)
#define G_TP_CH_CNG(x) (((x) >> S_TP_CH_CNG) & M_TP_CH_CNG)

#define S_ST_CONG    12
#define M_ST_CONG    0x3U
#define V_ST_CONG(x) ((x) << S_ST_CONG)
#define G_ST_CONG(x) (((x) >> S_ST_CONG) & M_ST_CONG)

#define S_LAST_XOFF    10
#define V_LAST_XOFF(x) ((x) << S_LAST_XOFF)
#define F_LAST_XOFF    V_LAST_XOFF(1U)

#define S_LAST_QID    0
#define M_LAST_QID    0x3ffU
#define V_LAST_QID(x) ((x) << S_LAST_QID)
#define G_LAST_QID(x) (((x) >> S_LAST_QID) & M_LAST_QID)

#define A_SGE_DBG_QUEUE_STAT0_CTRL 0x125c

#define S_IMSG_GTS_SEL    18
#define V_IMSG_GTS_SEL(x) ((x) << S_IMSG_GTS_SEL)
#define F_IMSG_GTS_SEL    V_IMSG_GTS_SEL(1U)

#define S_MGT_SEL    17
#define V_MGT_SEL(x) ((x) << S_MGT_SEL)
#define F_MGT_SEL    V_MGT_SEL(1U)

#define S_DB_GTS_QID    0
#define M_DB_GTS_QID    0x1ffffU
#define V_DB_GTS_QID(x) ((x) << S_DB_GTS_QID)
#define G_DB_GTS_QID(x) (((x) >> S_DB_GTS_QID) & M_DB_GTS_QID)

#define A_SGE_DBG_QUEUE_STAT1_CTRL 0x1260
#define A_SGE_DBG_QUEUE_STAT0 0x1264
#define A_SGE_DBG_QUEUE_STAT1 0x1268
#define A_SGE_DBG_BAR2_PKT_CNT 0x126c
#define A_SGE_DBG_DB_PKT_CNT 0x1270
#define A_SGE_DBG_GTS_PKT_CNT 0x1274
#define A_SGE_DEBUG_DATA_HIGH_INDEX_0 0x1280

#define S_CIM_WM    24
#define M_CIM_WM    0x3U
#define V_CIM_WM(x) ((x) << S_CIM_WM)
#define G_CIM_WM(x) (((x) >> S_CIM_WM) & M_CIM_WM)

#define S_DEBUG_UP_SOP_CNT    20
#define M_DEBUG_UP_SOP_CNT    0xfU
#define V_DEBUG_UP_SOP_CNT(x) ((x) << S_DEBUG_UP_SOP_CNT)
#define G_DEBUG_UP_SOP_CNT(x) (((x) >> S_DEBUG_UP_SOP_CNT) & M_DEBUG_UP_SOP_CNT)

#define S_DEBUG_UP_EOP_CNT    16
#define M_DEBUG_UP_EOP_CNT    0xfU
#define V_DEBUG_UP_EOP_CNT(x) ((x) << S_DEBUG_UP_EOP_CNT)
#define G_DEBUG_UP_EOP_CNT(x) (((x) >> S_DEBUG_UP_EOP_CNT) & M_DEBUG_UP_EOP_CNT)

#define S_DEBUG_CIM_SOP1_CNT    12
#define M_DEBUG_CIM_SOP1_CNT    0xfU
#define V_DEBUG_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CIM_SOP1_CNT)
#define G_DEBUG_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CIM_SOP1_CNT) & M_DEBUG_CIM_SOP1_CNT)

#define S_DEBUG_CIM_EOP1_CNT    8
#define M_DEBUG_CIM_EOP1_CNT    0xfU
#define V_DEBUG_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CIM_EOP1_CNT)
#define G_DEBUG_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CIM_EOP1_CNT) & M_DEBUG_CIM_EOP1_CNT)

#define S_DEBUG_CIM_SOP0_CNT    4
#define M_DEBUG_CIM_SOP0_CNT    0xfU
#define V_DEBUG_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CIM_SOP0_CNT)
#define G_DEBUG_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CIM_SOP0_CNT) & M_DEBUG_CIM_SOP0_CNT)

#define S_DEBUG_CIM_EOP0_CNT    0
#define M_DEBUG_CIM_EOP0_CNT    0xfU
#define V_DEBUG_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CIM_EOP0_CNT)
#define G_DEBUG_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CIM_EOP0_CNT) & M_DEBUG_CIM_EOP0_CNT)

#define S_DEBUG_BAR2_SOP_CNT    28
#define M_DEBUG_BAR2_SOP_CNT    0xfU
#define V_DEBUG_BAR2_SOP_CNT(x) ((x) << S_DEBUG_BAR2_SOP_CNT)
#define G_DEBUG_BAR2_SOP_CNT(x) (((x) >> S_DEBUG_BAR2_SOP_CNT) & M_DEBUG_BAR2_SOP_CNT)

#define S_DEBUG_BAR2_EOP_CNT    24
#define M_DEBUG_BAR2_EOP_CNT    0xfU
#define V_DEBUG_BAR2_EOP_CNT(x) ((x) << S_DEBUG_BAR2_EOP_CNT)
#define G_DEBUG_BAR2_EOP_CNT(x) (((x) >> S_DEBUG_BAR2_EOP_CNT) & M_DEBUG_BAR2_EOP_CNT)

#define A_SGE_DEBUG_DATA_HIGH_INDEX_1 0x1284

#define S_DEBUG_T_RX_SOP1_CNT    28
#define M_DEBUG_T_RX_SOP1_CNT    0xfU
#define V_DEBUG_T_RX_SOP1_CNT(x) ((x) << S_DEBUG_T_RX_SOP1_CNT)
#define G_DEBUG_T_RX_SOP1_CNT(x) (((x) >> S_DEBUG_T_RX_SOP1_CNT) & M_DEBUG_T_RX_SOP1_CNT)

#define S_DEBUG_T_RX_EOP1_CNT    24
#define M_DEBUG_T_RX_EOP1_CNT    0xfU
#define V_DEBUG_T_RX_EOP1_CNT(x) ((x) << S_DEBUG_T_RX_EOP1_CNT)
#define G_DEBUG_T_RX_EOP1_CNT(x) (((x) >> S_DEBUG_T_RX_EOP1_CNT) & M_DEBUG_T_RX_EOP1_CNT)

#define S_DEBUG_T_RX_SOP0_CNT    20
#define M_DEBUG_T_RX_SOP0_CNT    0xfU
#define V_DEBUG_T_RX_SOP0_CNT(x) ((x) << S_DEBUG_T_RX_SOP0_CNT)
#define G_DEBUG_T_RX_SOP0_CNT(x) (((x) >> S_DEBUG_T_RX_SOP0_CNT) & M_DEBUG_T_RX_SOP0_CNT)

#define S_DEBUG_T_RX_EOP0_CNT    16
#define M_DEBUG_T_RX_EOP0_CNT    0xfU
#define V_DEBUG_T_RX_EOP0_CNT(x) ((x) << S_DEBUG_T_RX_EOP0_CNT)
#define G_DEBUG_T_RX_EOP0_CNT(x) (((x) >> S_DEBUG_T_RX_EOP0_CNT) & M_DEBUG_T_RX_EOP0_CNT)

#define S_DEBUG_U_RX_SOP1_CNT    12
#define M_DEBUG_U_RX_SOP1_CNT    0xfU
#define V_DEBUG_U_RX_SOP1_CNT(x) ((x) << S_DEBUG_U_RX_SOP1_CNT)
#define G_DEBUG_U_RX_SOP1_CNT(x) (((x) >> S_DEBUG_U_RX_SOP1_CNT) & M_DEBUG_U_RX_SOP1_CNT)

#define S_DEBUG_U_RX_EOP1_CNT    8
#define M_DEBUG_U_RX_EOP1_CNT    0xfU
#define V_DEBUG_U_RX_EOP1_CNT(x) ((x) << S_DEBUG_U_RX_EOP1_CNT)
#define G_DEBUG_U_RX_EOP1_CNT(x) (((x) >> S_DEBUG_U_RX_EOP1_CNT) & M_DEBUG_U_RX_EOP1_CNT)

#define S_DEBUG_U_RX_SOP0_CNT    4
#define M_DEBUG_U_RX_SOP0_CNT    0xfU
#define V_DEBUG_U_RX_SOP0_CNT(x) ((x) << S_DEBUG_U_RX_SOP0_CNT)
#define G_DEBUG_U_RX_SOP0_CNT(x) (((x) >> S_DEBUG_U_RX_SOP0_CNT) & M_DEBUG_U_RX_SOP0_CNT)

#define S_DEBUG_U_RX_EOP0_CNT    0
#define M_DEBUG_U_RX_EOP0_CNT    0xfU
#define V_DEBUG_U_RX_EOP0_CNT(x) ((x) << S_DEBUG_U_RX_EOP0_CNT)
#define G_DEBUG_U_RX_EOP0_CNT(x) (((x) >> S_DEBUG_U_RX_EOP0_CNT) & M_DEBUG_U_RX_EOP0_CNT)

#define A_SGE_DEBUG_DATA_HIGH_INDEX_2 0x1288

#define S_DEBUG_UD_RX_SOP3_CNT    28
#define M_DEBUG_UD_RX_SOP3_CNT    0xfU
#define V_DEBUG_UD_RX_SOP3_CNT(x) ((x) << S_DEBUG_UD_RX_SOP3_CNT)
#define G_DEBUG_UD_RX_SOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP3_CNT) & M_DEBUG_UD_RX_SOP3_CNT)

#define S_DEBUG_UD_RX_EOP3_CNT    24
#define M_DEBUG_UD_RX_EOP3_CNT    0xfU
#define V_DEBUG_UD_RX_EOP3_CNT(x) ((x) << S_DEBUG_UD_RX_EOP3_CNT)
#define G_DEBUG_UD_RX_EOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP3_CNT) & M_DEBUG_UD_RX_EOP3_CNT)

#define S_DEBUG_UD_RX_SOP2_CNT    20
#define M_DEBUG_UD_RX_SOP2_CNT    0xfU
#define V_DEBUG_UD_RX_SOP2_CNT(x) ((x) << S_DEBUG_UD_RX_SOP2_CNT)
#define G_DEBUG_UD_RX_SOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP2_CNT) & M_DEBUG_UD_RX_SOP2_CNT)

#define S_DEBUG_UD_RX_EOP2_CNT    16
#define M_DEBUG_UD_RX_EOP2_CNT    0xfU
#define V_DEBUG_UD_RX_EOP2_CNT(x) ((x) << S_DEBUG_UD_RX_EOP2_CNT)
#define G_DEBUG_UD_RX_EOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP2_CNT) & M_DEBUG_UD_RX_EOP2_CNT)

#define S_DEBUG_UD_RX_SOP1_CNT    12
#define M_DEBUG_UD_RX_SOP1_CNT    0xfU
#define V_DEBUG_UD_RX_SOP1_CNT(x) ((x) << S_DEBUG_UD_RX_SOP1_CNT)
#define G_DEBUG_UD_RX_SOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP1_CNT) & M_DEBUG_UD_RX_SOP1_CNT)

#define S_DEBUG_UD_RX_EOP1_CNT    8
#define M_DEBUG_UD_RX_EOP1_CNT    0xfU
#define V_DEBUG_UD_RX_EOP1_CNT(x) ((x) << S_DEBUG_UD_RX_EOP1_CNT)
#define G_DEBUG_UD_RX_EOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP1_CNT) & M_DEBUG_UD_RX_EOP1_CNT)

#define S_DEBUG_UD_RX_SOP0_CNT    4
#define M_DEBUG_UD_RX_SOP0_CNT    0xfU
#define V_DEBUG_UD_RX_SOP0_CNT(x) ((x) << S_DEBUG_UD_RX_SOP0_CNT)
#define G_DEBUG_UD_RX_SOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP0_CNT) & M_DEBUG_UD_RX_SOP0_CNT)

#define S_DEBUG_UD_RX_EOP0_CNT    0
#define M_DEBUG_UD_RX_EOP0_CNT    0xfU
#define V_DEBUG_UD_RX_EOP0_CNT(x) ((x) << S_DEBUG_UD_RX_EOP0_CNT)
#define G_DEBUG_UD_RX_EOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP0_CNT) & M_DEBUG_UD_RX_EOP0_CNT)

#define S_DBG_TBUF_USED1    9
#define M_DBG_TBUF_USED1    0x1ffU
#define V_DBG_TBUF_USED1(x) ((x) << S_DBG_TBUF_USED1)
#define G_DBG_TBUF_USED1(x) (((x) >> S_DBG_TBUF_USED1) & M_DBG_TBUF_USED1)

#define S_DBG_TBUF_USED0    0
#define M_DBG_TBUF_USED0    0x1ffU
#define V_DBG_TBUF_USED0(x) ((x) << S_DBG_TBUF_USED0)
#define G_DBG_TBUF_USED0(x) (((x) >> S_DBG_TBUF_USED0) & M_DBG_TBUF_USED0)

#define A_SGE_DEBUG_DATA_HIGH_INDEX_3 0x128c

#define S_DEBUG_U_TX_SOP3_CNT    28
#define M_DEBUG_U_TX_SOP3_CNT    0xfU
#define V_DEBUG_U_TX_SOP3_CNT(x) ((x) << S_DEBUG_U_TX_SOP3_CNT)
#define G_DEBUG_U_TX_SOP3_CNT(x) (((x) >> S_DEBUG_U_TX_SOP3_CNT) & M_DEBUG_U_TX_SOP3_CNT)

#define S_DEBUG_U_TX_EOP3_CNT    24
#define M_DEBUG_U_TX_EOP3_CNT    0xfU
#define V_DEBUG_U_TX_EOP3_CNT(x) ((x) << S_DEBUG_U_TX_EOP3_CNT)
#define G_DEBUG_U_TX_EOP3_CNT(x) (((x) >> S_DEBUG_U_TX_EOP3_CNT) & M_DEBUG_U_TX_EOP3_CNT)

#define S_DEBUG_U_TX_SOP2_CNT    20
#define M_DEBUG_U_TX_SOP2_CNT    0xfU
#define V_DEBUG_U_TX_SOP2_CNT(x) ((x) << S_DEBUG_U_TX_SOP2_CNT)
#define G_DEBUG_U_TX_SOP2_CNT(x) (((x) >> S_DEBUG_U_TX_SOP2_CNT) & M_DEBUG_U_TX_SOP2_CNT)

#define S_DEBUG_U_TX_EOP2_CNT    16
#define M_DEBUG_U_TX_EOP2_CNT    0xfU
#define V_DEBUG_U_TX_EOP2_CNT(x) ((x) << S_DEBUG_U_TX_EOP2_CNT)
#define G_DEBUG_U_TX_EOP2_CNT(x) (((x) >> S_DEBUG_U_TX_EOP2_CNT) & M_DEBUG_U_TX_EOP2_CNT)

#define S_DEBUG_U_TX_SOP1_CNT    12
#define M_DEBUG_U_TX_SOP1_CNT    0xfU
#define V_DEBUG_U_TX_SOP1_CNT(x) ((x) << S_DEBUG_U_TX_SOP1_CNT)
#define G_DEBUG_U_TX_SOP1_CNT(x) (((x) >> S_DEBUG_U_TX_SOP1_CNT) & M_DEBUG_U_TX_SOP1_CNT)

#define S_DEBUG_U_TX_EOP1_CNT    8
#define M_DEBUG_U_TX_EOP1_CNT    0xfU
#define V_DEBUG_U_TX_EOP1_CNT(x) ((x) << S_DEBUG_U_TX_EOP1_CNT)
#define G_DEBUG_U_TX_EOP1_CNT(x) (((x) >> S_DEBUG_U_TX_EOP1_CNT) & M_DEBUG_U_TX_EOP1_CNT)

#define S_DEBUG_U_TX_SOP0_CNT    4
#define M_DEBUG_U_TX_SOP0_CNT    0xfU
#define V_DEBUG_U_TX_SOP0_CNT(x) ((x) << S_DEBUG_U_TX_SOP0_CNT)
#define G_DEBUG_U_TX_SOP0_CNT(x) (((x) >> S_DEBUG_U_TX_SOP0_CNT) & M_DEBUG_U_TX_SOP0_CNT)

#define S_DEBUG_U_TX_EOP0_CNT    0
#define M_DEBUG_U_TX_EOP0_CNT    0xfU
#define V_DEBUG_U_TX_EOP0_CNT(x) ((x) << S_DEBUG_U_TX_EOP0_CNT)
#define G_DEBUG_U_TX_EOP0_CNT(x) (((x) >> S_DEBUG_U_TX_EOP0_CNT) & M_DEBUG_U_TX_EOP0_CNT)

#define A_SGE_DEBUG1_DBP_THREAD 0x128c

#define S_WR_DEQ_CNT    12
#define M_WR_DEQ_CNT    0xfU
#define V_WR_DEQ_CNT(x) ((x) << S_WR_DEQ_CNT)
#define G_WR_DEQ_CNT(x) (((x) >> S_WR_DEQ_CNT) & M_WR_DEQ_CNT)

#define S_WR_ENQ_CNT    8
#define M_WR_ENQ_CNT    0xfU
#define V_WR_ENQ_CNT(x) ((x) << S_WR_ENQ_CNT)
#define G_WR_ENQ_CNT(x) (((x) >> S_WR_ENQ_CNT) & M_WR_ENQ_CNT)

#define S_FL_DEQ_CNT    4
#define M_FL_DEQ_CNT    0xfU
#define V_FL_DEQ_CNT(x) ((x) << S_FL_DEQ_CNT)
#define G_FL_DEQ_CNT(x) (((x) >> S_FL_DEQ_CNT) & M_FL_DEQ_CNT)

#define S_FL_ENQ_CNT    0
#define M_FL_ENQ_CNT    0xfU
#define V_FL_ENQ_CNT(x) ((x) << S_FL_ENQ_CNT)
#define G_FL_ENQ_CNT(x) (((x) >> S_FL_ENQ_CNT) & M_FL_ENQ_CNT)

#define A_SGE_DEBUG_DATA_HIGH_INDEX_4 0x1290

#define S_DEBUG_PC_RSP_SOP1_CNT    28
#define M_DEBUG_PC_RSP_SOP1_CNT    0xfU
#define V_DEBUG_PC_RSP_SOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP1_CNT)
#define G_DEBUG_PC_RSP_SOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP1_CNT) & M_DEBUG_PC_RSP_SOP1_CNT)

#define S_DEBUG_PC_RSP_EOP1_CNT    24
#define M_DEBUG_PC_RSP_EOP1_CNT    0xfU
#define V_DEBUG_PC_RSP_EOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP1_CNT)
#define G_DEBUG_PC_RSP_EOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP1_CNT) & M_DEBUG_PC_RSP_EOP1_CNT)

#define S_DEBUG_PC_RSP_SOP0_CNT    20
#define M_DEBUG_PC_RSP_SOP0_CNT    0xfU
#define V_DEBUG_PC_RSP_SOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP0_CNT)
#define G_DEBUG_PC_RSP_SOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP0_CNT) & M_DEBUG_PC_RSP_SOP0_CNT)

#define S_DEBUG_PC_RSP_EOP0_CNT    16
#define M_DEBUG_PC_RSP_EOP0_CNT    0xfU
#define V_DEBUG_PC_RSP_EOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP0_CNT)
#define G_DEBUG_PC_RSP_EOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP0_CNT) & M_DEBUG_PC_RSP_EOP0_CNT)

#define S_DEBUG_PC_REQ_SOP1_CNT    12
#define M_DEBUG_PC_REQ_SOP1_CNT    0xfU
#define V_DEBUG_PC_REQ_SOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP1_CNT)
#define G_DEBUG_PC_REQ_SOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP1_CNT) & M_DEBUG_PC_REQ_SOP1_CNT)

#define S_DEBUG_PC_REQ_EOP1_CNT    8
#define M_DEBUG_PC_REQ_EOP1_CNT    0xfU
#define V_DEBUG_PC_REQ_EOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP1_CNT)
#define G_DEBUG_PC_REQ_EOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP1_CNT) & M_DEBUG_PC_REQ_EOP1_CNT)

#define S_DEBUG_PC_REQ_SOP0_CNT    4
#define M_DEBUG_PC_REQ_SOP0_CNT    0xfU
#define V_DEBUG_PC_REQ_SOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP0_CNT)
#define G_DEBUG_PC_REQ_SOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP0_CNT) & M_DEBUG_PC_REQ_SOP0_CNT)

#define S_DEBUG_PC_REQ_EOP0_CNT    0
#define M_DEBUG_PC_REQ_EOP0_CNT    0xfU
#define V_DEBUG_PC_REQ_EOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP0_CNT)
#define G_DEBUG_PC_REQ_EOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP0_CNT) & M_DEBUG_PC_REQ_EOP0_CNT)

#define A_SGE_DEBUG_DATA_HIGH_INDEX_5 0x1294

#define S_DEBUG_PD_RDREQ_SOP3_CNT    28
#define M_DEBUG_PD_RDREQ_SOP3_CNT    0xfU
#define V_DEBUG_PD_RDREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP3_CNT)
#define G_DEBUG_PD_RDREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP3_CNT) & M_DEBUG_PD_RDREQ_SOP3_CNT)

#define S_DEBUG_PD_RDREQ_EOP3_CNT    24
#define M_DEBUG_PD_RDREQ_EOP3_CNT    0xfU
#define V_DEBUG_PD_RDREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP3_CNT)
#define G_DEBUG_PD_RDREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP3_CNT) & M_DEBUG_PD_RDREQ_EOP3_CNT)

#define S_DEBUG_PD_RDREQ_SOP2_CNT    20
#define M_DEBUG_PD_RDREQ_SOP2_CNT    0xfU
#define V_DEBUG_PD_RDREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP2_CNT)
#define G_DEBUG_PD_RDREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP2_CNT) & M_DEBUG_PD_RDREQ_SOP2_CNT)

#define S_DEBUG_PD_RDREQ_EOP2_CNT    16
#define M_DEBUG_PD_RDREQ_EOP2_CNT    0xfU
#define V_DEBUG_PD_RDREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP2_CNT)
#define G_DEBUG_PD_RDREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP2_CNT) & M_DEBUG_PD_RDREQ_EOP2_CNT)

#define S_DEBUG_PD_RDREQ_SOP1_CNT    12
#define M_DEBUG_PD_RDREQ_SOP1_CNT    0xfU
#define V_DEBUG_PD_RDREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP1_CNT)
#define G_DEBUG_PD_RDREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP1_CNT) & M_DEBUG_PD_RDREQ_SOP1_CNT)

#define S_DEBUG_PD_RDREQ_EOP1_CNT    8
#define M_DEBUG_PD_RDREQ_EOP1_CNT    0xfU
#define V_DEBUG_PD_RDREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP1_CNT)
#define G_DEBUG_PD_RDREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP1_CNT) & M_DEBUG_PD_RDREQ_EOP1_CNT)

#define S_DEBUG_PD_RDREQ_SOP0_CNT    4
#define M_DEBUG_PD_RDREQ_SOP0_CNT    0xfU
#define V_DEBUG_PD_RDREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP0_CNT)
#define G_DEBUG_PD_RDREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP0_CNT) & M_DEBUG_PD_RDREQ_SOP0_CNT)

#define S_DEBUG_PD_RDREQ_EOP0_CNT    0
#define M_DEBUG_PD_RDREQ_EOP0_CNT    0xfU
#define V_DEBUG_PD_RDREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP0_CNT)
#define G_DEBUG_PD_RDREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP0_CNT) & M_DEBUG_PD_RDREQ_EOP0_CNT)

#define A_SGE_DEBUG_DATA_HIGH_INDEX_6 0x1298

#define S_DEBUG_PD_RDRSP_SOP3_CNT    28
#define M_DEBUG_PD_RDRSP_SOP3_CNT    0xfU
#define V_DEBUG_PD_RDRSP_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP3_CNT)
#define G_DEBUG_PD_RDRSP_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP3_CNT) & M_DEBUG_PD_RDRSP_SOP3_CNT)

#define S_DEBUG_PD_RDRSP_EOP3_CNT    24
#define M_DEBUG_PD_RDRSP_EOP3_CNT    0xfU
#define V_DEBUG_PD_RDRSP_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP3_CNT)
#define G_DEBUG_PD_RDRSP_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP3_CNT) & M_DEBUG_PD_RDRSP_EOP3_CNT)

#define S_DEBUG_PD_RDRSP_SOP2_CNT    20
#define M_DEBUG_PD_RDRSP_SOP2_CNT    0xfU
#define V_DEBUG_PD_RDRSP_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP2_CNT)
#define G_DEBUG_PD_RDRSP_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP2_CNT) & M_DEBUG_PD_RDRSP_SOP2_CNT)

#define S_DEBUG_PD_RDRSP_EOP2_CNT    16
#define M_DEBUG_PD_RDRSP_EOP2_CNT    0xfU
#define V_DEBUG_PD_RDRSP_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP2_CNT)
#define G_DEBUG_PD_RDRSP_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP2_CNT) & M_DEBUG_PD_RDRSP_EOP2_CNT)

#define S_DEBUG_PD_RDRSP_SOP1_CNT    12
#define M_DEBUG_PD_RDRSP_SOP1_CNT    0xfU
#define V_DEBUG_PD_RDRSP_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP1_CNT)
#define G_DEBUG_PD_RDRSP_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP1_CNT) & M_DEBUG_PD_RDRSP_SOP1_CNT)

#define S_DEBUG_PD_RDRSP_EOP1_CNT    8
#define M_DEBUG_PD_RDRSP_EOP1_CNT    0xfU
#define V_DEBUG_PD_RDRSP_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP1_CNT)
#define G_DEBUG_PD_RDRSP_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP1_CNT) & M_DEBUG_PD_RDRSP_EOP1_CNT)

#define S_DEBUG_PD_RDRSP_SOP0_CNT    4
#define M_DEBUG_PD_RDRSP_SOP0_CNT    0xfU
#define V_DEBUG_PD_RDRSP_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP0_CNT)
#define G_DEBUG_PD_RDRSP_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP0_CNT) & M_DEBUG_PD_RDRSP_SOP0_CNT)

#define S_DEBUG_PD_RDRSP_EOP0_CNT    0
#define M_DEBUG_PD_RDRSP_EOP0_CNT    0xfU
#define V_DEBUG_PD_RDRSP_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP0_CNT)
#define G_DEBUG_PD_RDRSP_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP0_CNT) & M_DEBUG_PD_RDRSP_EOP0_CNT)

#define A_SGE_DEBUG_DATA_HIGH_INDEX_7 0x129c

#define S_DEBUG_PD_WRREQ_SOP3_CNT    28
#define M_DEBUG_PD_WRREQ_SOP3_CNT    0xfU
#define V_DEBUG_PD_WRREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP3_CNT)
#define G_DEBUG_PD_WRREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP3_CNT) & M_DEBUG_PD_WRREQ_SOP3_CNT)

#define S_DEBUG_PD_WRREQ_EOP3_CNT    24
#define M_DEBUG_PD_WRREQ_EOP3_CNT    0xfU
#define V_DEBUG_PD_WRREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP3_CNT)
#define G_DEBUG_PD_WRREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP3_CNT) & M_DEBUG_PD_WRREQ_EOP3_CNT)

#define S_DEBUG_PD_WRREQ_SOP2_CNT    20
#define M_DEBUG_PD_WRREQ_SOP2_CNT    0xfU
#define V_DEBUG_PD_WRREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP2_CNT)
#define G_DEBUG_PD_WRREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP2_CNT) & M_DEBUG_PD_WRREQ_SOP2_CNT)

#define S_DEBUG_PD_WRREQ_EOP2_CNT    16
#define M_DEBUG_PD_WRREQ_EOP2_CNT    0xfU
#define V_DEBUG_PD_WRREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP2_CNT)
#define G_DEBUG_PD_WRREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP2_CNT) & M_DEBUG_PD_WRREQ_EOP2_CNT)

#define S_DEBUG_PD_WRREQ_SOP1_CNT    12
#define M_DEBUG_PD_WRREQ_SOP1_CNT    0xfU
#define V_DEBUG_PD_WRREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP1_CNT)
#define G_DEBUG_PD_WRREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP1_CNT) & M_DEBUG_PD_WRREQ_SOP1_CNT)

#define S_DEBUG_PD_WRREQ_EOP1_CNT    8
#define M_DEBUG_PD_WRREQ_EOP1_CNT    0xfU
#define V_DEBUG_PD_WRREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP1_CNT)
#define G_DEBUG_PD_WRREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP1_CNT) & M_DEBUG_PD_WRREQ_EOP1_CNT)

#define S_DEBUG_PD_WRREQ_SOP0_CNT    4
#define M_DEBUG_PD_WRREQ_SOP0_CNT    0xfU
#define V_DEBUG_PD_WRREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP0_CNT)
#define G_DEBUG_PD_WRREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP0_CNT) & M_DEBUG_PD_WRREQ_SOP0_CNT)

#define S_DEBUG_PD_WRREQ_EOP0_CNT    0
#define M_DEBUG_PD_WRREQ_EOP0_CNT    0xfU
#define V_DEBUG_PD_WRREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP0_CNT)
#define G_DEBUG_PD_WRREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP0_CNT) & M_DEBUG_PD_WRREQ_EOP0_CNT)

#define S_DEBUG_PC_RSP_SOP_CNT    28
#define M_DEBUG_PC_RSP_SOP_CNT    0xfU
#define V_DEBUG_PC_RSP_SOP_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP_CNT)
#define G_DEBUG_PC_RSP_SOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP_CNT) & M_DEBUG_PC_RSP_SOP_CNT)

#define S_DEBUG_PC_RSP_EOP_CNT    24
#define M_DEBUG_PC_RSP_EOP_CNT    0xfU
#define V_DEBUG_PC_RSP_EOP_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP_CNT)
#define G_DEBUG_PC_RSP_EOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP_CNT) & M_DEBUG_PC_RSP_EOP_CNT)

#define S_DEBUG_PC_REQ_SOP_CNT    20
#define M_DEBUG_PC_REQ_SOP_CNT    0xfU
#define V_DEBUG_PC_REQ_SOP_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP_CNT)
#define G_DEBUG_PC_REQ_SOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP_CNT) & M_DEBUG_PC_REQ_SOP_CNT)

#define S_DEBUG_PC_REQ_EOP_CNT    16
#define M_DEBUG_PC_REQ_EOP_CNT    0xfU
#define V_DEBUG_PC_REQ_EOP_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP_CNT)
#define G_DEBUG_PC_REQ_EOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP_CNT) & M_DEBUG_PC_REQ_EOP_CNT)

#define A_SGE_DEBUG_DATA_HIGH_INDEX_8 0x12a0

#define S_GLOBALENABLE_OFF    29
#define V_GLOBALENABLE_OFF(x) ((x) << S_GLOBALENABLE_OFF)
#define F_GLOBALENABLE_OFF    V_GLOBALENABLE_OFF(1U)

#define S_DEBUG_CIM2SGE_RXAFULL_D    27
#define M_DEBUG_CIM2SGE_RXAFULL_D    0x3U
#define V_DEBUG_CIM2SGE_RXAFULL_D(x) ((x) << S_DEBUG_CIM2SGE_RXAFULL_D)
#define G_DEBUG_CIM2SGE_RXAFULL_D(x) (((x) >> S_DEBUG_CIM2SGE_RXAFULL_D) & M_DEBUG_CIM2SGE_RXAFULL_D)

#define S_DEBUG_CPLSW_CIM_TXAFULL_D    25
#define M_DEBUG_CPLSW_CIM_TXAFULL_D    0x3U
#define V_DEBUG_CPLSW_CIM_TXAFULL_D(x) ((x) << S_DEBUG_CPLSW_CIM_TXAFULL_D)
#define G_DEBUG_CPLSW_CIM_TXAFULL_D(x) (((x) >> S_DEBUG_CPLSW_CIM_TXAFULL_D) & M_DEBUG_CPLSW_CIM_TXAFULL_D)

#define S_DEBUG_UP_FULL    24
#define V_DEBUG_UP_FULL(x) ((x) << S_DEBUG_UP_FULL)
#define F_DEBUG_UP_FULL    V_DEBUG_UP_FULL(1U)

#define S_DEBUG_M_RD_REQ_OUTSTANDING_PC    23
#define V_DEBUG_M_RD_REQ_OUTSTANDING_PC(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_PC)
#define F_DEBUG_M_RD_REQ_OUTSTANDING_PC    V_DEBUG_M_RD_REQ_OUTSTANDING_PC(1U)

#define S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO    22
#define V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO)
#define F_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO    V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(1U)

#define S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG    21
#define V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG)
#define F_DEBUG_M_RD_REQ_OUTSTANDING_IMSG    V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(1U)

#define S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB    20
#define V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB)
#define F_DEBUG_M_RD_REQ_OUTSTANDING_CMARB    V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(1U)

#define S_DEBUG_M_RD_REQ_OUTSTANDING_FLM    19
#define V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_FLM)
#define F_DEBUG_M_RD_REQ_OUTSTANDING_FLM    V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(1U)

#define S_DEBUG_M_REQVLD    18
#define V_DEBUG_M_REQVLD(x) ((x) << S_DEBUG_M_REQVLD)
#define F_DEBUG_M_REQVLD    V_DEBUG_M_REQVLD(1U)

#define S_DEBUG_M_REQRDY    17
#define V_DEBUG_M_REQRDY(x) ((x) << S_DEBUG_M_REQRDY)
#define F_DEBUG_M_REQRDY    V_DEBUG_M_REQRDY(1U)

#define S_DEBUG_M_RSPVLD    16
#define V_DEBUG_M_RSPVLD(x) ((x) << S_DEBUG_M_RSPVLD)
#define F_DEBUG_M_RSPVLD    V_DEBUG_M_RSPVLD(1U)

#define S_DEBUG_PD_WRREQ_INT3_CNT    12
#define M_DEBUG_PD_WRREQ_INT3_CNT    0xfU
#define V_DEBUG_PD_WRREQ_INT3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT3_CNT)
#define G_DEBUG_PD_WRREQ_INT3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT3_CNT) & M_DEBUG_PD_WRREQ_INT3_CNT)

#define S_DEBUG_PD_WRREQ_INT2_CNT    8
#define M_DEBUG_PD_WRREQ_INT2_CNT    0xfU
#define V_DEBUG_PD_WRREQ_INT2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT2_CNT)
#define G_DEBUG_PD_WRREQ_INT2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT2_CNT) & M_DEBUG_PD_WRREQ_INT2_CNT)

#define S_DEBUG_PD_WRREQ_INT1_CNT    4
#define M_DEBUG_PD_WRREQ_INT1_CNT    0xfU
#define V_DEBUG_PD_WRREQ_INT1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT1_CNT)
#define G_DEBUG_PD_WRREQ_INT1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT1_CNT) & M_DEBUG_PD_WRREQ_INT1_CNT)

#define S_DEBUG_PD_WRREQ_INT0_CNT    0
#define M_DEBUG_PD_WRREQ_INT0_CNT    0xfU
#define V_DEBUG_PD_WRREQ_INT0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT0_CNT)
#define G_DEBUG_PD_WRREQ_INT0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT0_CNT) & M_DEBUG_PD_WRREQ_INT0_CNT)

#define S_DEBUG_PL_BAR2_REQVLD    31
#define V_DEBUG_PL_BAR2_REQVLD(x) ((x) << S_DEBUG_PL_BAR2_REQVLD)
#define F_DEBUG_PL_BAR2_REQVLD    V_DEBUG_PL_BAR2_REQVLD(1U)

#define S_DEBUG_PL_BAR2_REQFULL    30
#define V_DEBUG_PL_BAR2_REQFULL(x) ((x) << S_DEBUG_PL_BAR2_REQFULL)
#define F_DEBUG_PL_BAR2_REQFULL    V_DEBUG_PL_BAR2_REQFULL(1U)

#define A_SGE_DEBUG_DATA_HIGH_INDEX_9 0x12a4

#define S_DEBUG_CPLSW_TP_RX_SOP1_CNT    28
#define M_DEBUG_CPLSW_TP_RX_SOP1_CNT    0xfU
#define V_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP1_CNT)
#define G_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP1_CNT) & M_DEBUG_CPLSW_TP_RX_SOP1_CNT)

#define S_DEBUG_CPLSW_TP_RX_EOP1_CNT    24
#define M_DEBUG_CPLSW_TP_RX_EOP1_CNT    0xfU
#define V_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP1_CNT)
#define G_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP1_CNT) & M_DEBUG_CPLSW_TP_RX_EOP1_CNT)

#define S_DEBUG_CPLSW_TP_RX_SOP0_CNT    20
#define M_DEBUG_CPLSW_TP_RX_SOP0_CNT    0xfU
#define V_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP0_CNT)
#define G_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP0_CNT) & M_DEBUG_CPLSW_TP_RX_SOP0_CNT)

#define S_DEBUG_CPLSW_TP_RX_EOP0_CNT    16
#define M_DEBUG_CPLSW_TP_RX_EOP0_CNT    0xfU
#define V_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP0_CNT)
#define G_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP0_CNT) & M_DEBUG_CPLSW_TP_RX_EOP0_CNT)

#define S_DEBUG_CPLSW_CIM_SOP1_CNT    12
#define M_DEBUG_CPLSW_CIM_SOP1_CNT    0xfU
#define V_DEBUG_CPLSW_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP1_CNT)
#define G_DEBUG_CPLSW_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP1_CNT) & M_DEBUG_CPLSW_CIM_SOP1_CNT)

#define S_DEBUG_CPLSW_CIM_EOP1_CNT    8
#define M_DEBUG_CPLSW_CIM_EOP1_CNT    0xfU
#define V_DEBUG_CPLSW_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP1_CNT)
#define G_DEBUG_CPLSW_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP1_CNT) & M_DEBUG_CPLSW_CIM_EOP1_CNT)

#define S_DEBUG_CPLSW_CIM_SOP0_CNT    4
#define M_DEBUG_CPLSW_CIM_SOP0_CNT    0xfU
#define V_DEBUG_CPLSW_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP0_CNT)
#define G_DEBUG_CPLSW_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP0_CNT) & M_DEBUG_CPLSW_CIM_SOP0_CNT)

#define S_DEBUG_CPLSW_CIM_EOP0_CNT    0
#define M_DEBUG_CPLSW_CIM_EOP0_CNT    0xfU
#define V_DEBUG_CPLSW_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP0_CNT)
#define G_DEBUG_CPLSW_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP0_CNT) & M_DEBUG_CPLSW_CIM_EOP0_CNT)

#define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8

#define S_DEBUG_T_RXAFULL_D    30
#define M_DEBUG_T_RXAFULL_D    0x3U
#define V_DEBUG_T_RXAFULL_D(x) ((x) << S_DEBUG_T_RXAFULL_D)
#define G_DEBUG_T_RXAFULL_D(x) (((x) >> S_DEBUG_T_RXAFULL_D) & M_DEBUG_T_RXAFULL_D)

#define S_DEBUG_PD_RDRSPAFULL_D    26
#define M_DEBUG_PD_RDRSPAFULL_D    0xfU
#define V_DEBUG_PD_RDRSPAFULL_D(x) ((x) << S_DEBUG_PD_RDRSPAFULL_D)
#define G_DEBUG_PD_RDRSPAFULL_D(x) (((x) >> S_DEBUG_PD_RDRSPAFULL_D) & M_DEBUG_PD_RDRSPAFULL_D)

#define S_DEBUG_PD_RDREQAFULL_D    22
#define M_DEBUG_PD_RDREQAFULL_D    0xfU
#define V_DEBUG_PD_RDREQAFULL_D(x) ((x) << S_DEBUG_PD_RDREQAFULL_D)
#define G_DEBUG_PD_RDREQAFULL_D(x) (((x) >> S_DEBUG_PD_RDREQAFULL_D) & M_DEBUG_PD_RDREQAFULL_D)

#define S_DEBUG_PD_WRREQAFULL_D    18
#define M_DEBUG_PD_WRREQAFULL_D    0xfU
#define V_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_DEBUG_PD_WRREQAFULL_D)
#define G_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_DEBUG_PD_WRREQAFULL_D) & M_DEBUG_PD_WRREQAFULL_D)

#define S_DEBUG_PC_RSPAFULL_D    15
#define M_DEBUG_PC_RSPAFULL_D    0x7U
#define V_DEBUG_PC_RSPAFULL_D(x) ((x) << S_DEBUG_PC_RSPAFULL_D)
#define G_DEBUG_PC_RSPAFULL_D(x) (((x) >> S_DEBUG_PC_RSPAFULL_D) & M_DEBUG_PC_RSPAFULL_D)

#define S_DEBUG_PC_REQAFULL_D    12
#define M_DEBUG_PC_REQAFULL_D    0x7U
#define V_DEBUG_PC_REQAFULL_D(x) ((x) << S_DEBUG_PC_REQAFULL_D)
#define G_DEBUG_PC_REQAFULL_D(x) (((x) >> S_DEBUG_PC_REQAFULL_D) & M_DEBUG_PC_REQAFULL_D)

#define S_DEBUG_U_TXAFULL_D    8
#define M_DEBUG_U_TXAFULL_D    0xfU
#define V_DEBUG_U_TXAFULL_D(x) ((x) << S_DEBUG_U_TXAFULL_D)
#define G_DEBUG_U_TXAFULL_D(x) (((x) >> S_DEBUG_U_TXAFULL_D) & M_DEBUG_U_TXAFULL_D)

#define S_DEBUG_UD_RXAFULL_D    4
#define M_DEBUG_UD_RXAFULL_D    0xfU
#define V_DEBUG_UD_RXAFULL_D(x) ((x) << S_DEBUG_UD_RXAFULL_D)
#define G_DEBUG_UD_RXAFULL_D(x) (((x) >> S_DEBUG_UD_RXAFULL_D) & M_DEBUG_UD_RXAFULL_D)

#define S_DEBUG_U_RXAFULL_D    2
#define M_DEBUG_U_RXAFULL_D    0x3U
#define V_DEBUG_U_RXAFULL_D(x) ((x) << S_DEBUG_U_RXAFULL_D)
#define G_DEBUG_U_RXAFULL_D(x) (((x) >> S_DEBUG_U_RXAFULL_D) & M_DEBUG_U_RXAFULL_D)

#define S_DEBUG_CIM_AFULL_D    0
#define M_DEBUG_CIM_AFULL_D    0x3U
#define V_DEBUG_CIM_AFULL_D(x) ((x) << S_DEBUG_CIM_AFULL_D)
#define G_DEBUG_CIM_AFULL_D(x) (((x) >> S_DEBUG_CIM_AFULL_D) & M_DEBUG_CIM_AFULL_D)

#define S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING    28
#define M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING    0xfU
#define V_DEBUG_IDMA1_S_CPL_FLIT_REMAINING(x) ((x) << S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING)
#define G_DEBUG_IDMA1_S_CPL_FLIT_REMAINING(x) (((x) >> S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING) & M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING)

#define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY    27
#define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY)
#define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY(1U)

#define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS    26
#define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS)
#define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS(1U)

#define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL    25
#define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL)
#define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL(1U)

#define S_DEBUG_IDMA1_IDMA2IMSG_FULL    24
#define V_DEBUG_IDMA1_IDMA2IMSG_FULL(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_FULL)
#define F_DEBUG_IDMA1_IDMA2IMSG_FULL    V_DEBUG_IDMA1_IDMA2IMSG_FULL(1U)

#define S_DEBUG_IDMA1_IDMA2IMSG_EOP    23
#define V_DEBUG_IDMA1_IDMA2IMSG_EOP(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_EOP)
#define F_DEBUG_IDMA1_IDMA2IMSG_EOP    V_DEBUG_IDMA1_IDMA2IMSG_EOP(1U)

#define S_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY    22
#define V_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY)
#define F_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY    V_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY(1U)

#define S_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY    21
#define V_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY)
#define F_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY    V_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY(1U)

#define S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING    17
#define M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING    0xfU
#define V_DEBUG_IDMA0_S_CPL_FLIT_REMAINING(x) ((x) << S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING)
#define G_DEBUG_IDMA0_S_CPL_FLIT_REMAINING(x) (((x) >> S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING) & M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING)

#define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY    16
#define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY)
#define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY(1U)

#define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS    15
#define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS)
#define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS(1U)

#define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL    14
#define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL)
#define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL(1U)

#define S_DEBUG_IDMA0_IDMA2IMSG_FULL    13
#define V_DEBUG_IDMA0_IDMA2IMSG_FULL(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_FULL)
#define F_DEBUG_IDMA0_IDMA2IMSG_FULL    V_DEBUG_IDMA0_IDMA2IMSG_FULL(1U)

#define S_DEBUG_IDMA0_IDMA2IMSG_EOP    12
#define V_DEBUG_IDMA0_IDMA2IMSG_EOP(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_EOP)
#define F_DEBUG_IDMA0_IDMA2IMSG_EOP    V_DEBUG_IDMA0_IDMA2IMSG_EOP(1U)

#define S_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY    11
#define V_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY)
#define F_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY    V_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY(1U)

#define S_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY    10
#define V_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY)
#define F_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY    V_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY(1U)

#define S_T6_DEBUG_T_RXAFULL_D    8
#define M_T6_DEBUG_T_RXAFULL_D    0x3U
#define V_T6_DEBUG_T_RXAFULL_D(x) ((x) << S_T6_DEBUG_T_RXAFULL_D)
#define G_T6_DEBUG_T_RXAFULL_D(x) (((x) >> S_T6_DEBUG_T_RXAFULL_D) & M_T6_DEBUG_T_RXAFULL_D)

#define S_T6_DEBUG_PD_WRREQAFULL_D    6
#define M_T6_DEBUG_PD_WRREQAFULL_D    0x3U
#define V_T6_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_T6_DEBUG_PD_WRREQAFULL_D)
#define G_T6_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_T6_DEBUG_PD_WRREQAFULL_D) & M_T6_DEBUG_PD_WRREQAFULL_D)

#define S_T6_DEBUG_PC_RSPAFULL_D    5
#define V_T6_DEBUG_PC_RSPAFULL_D(x) ((x) << S_T6_DEBUG_PC_RSPAFULL_D)
#define F_T6_DEBUG_PC_RSPAFULL_D    V_T6_DEBUG_PC_RSPAFULL_D(1U)

#define S_T6_DEBUG_PC_REQAFULL_D    4
#define V_T6_DEBUG_PC_REQAFULL_D(x) ((x) << S_T6_DEBUG_PC_REQAFULL_D)
#define F_T6_DEBUG_PC_REQAFULL_D    V_T6_DEBUG_PC_REQAFULL_D(1U)

#define S_T6_DEBUG_CIM_AFULL_D    0
#define V_T6_DEBUG_CIM_AFULL_D(x) ((x) << S_T6_DEBUG_CIM_AFULL_D)
#define F_T6_DEBUG_CIM_AFULL_D    V_T6_DEBUG_CIM_AFULL_D(1U)

#define A_SGE_DEBUG_DATA_HIGH_INDEX_11 0x12ac

#define S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE    24
#define V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE)
#define F_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE    V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(1U)

#define S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE    23
#define V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE)
#define F_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE    V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(1U)

#define S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE    22
#define V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE)
#define F_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE    V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(1U)

#define S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE    21
#define V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE)
#define F_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE    V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(1U)

#define S_DEBUG_ST_FLM_IDMA1_CACHE    19
#define M_DEBUG_ST_FLM_IDMA1_CACHE    0x3U
#define V_DEBUG_ST_FLM_IDMA1_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CACHE)
#define G_DEBUG_ST_FLM_IDMA1_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CACHE) & M_DEBUG_ST_FLM_IDMA1_CACHE)

#define S_DEBUG_ST_FLM_IDMA1_CTXT    16
#define M_DEBUG_ST_FLM_IDMA1_CTXT    0x7U
#define V_DEBUG_ST_FLM_IDMA1_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CTXT)
#define G_DEBUG_ST_FLM_IDMA1_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CTXT) & M_DEBUG_ST_FLM_IDMA1_CTXT)

#define S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE    8
#define V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE)
#define F_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE    V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(1U)

#define S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE    7
#define V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE)
#define F_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE    V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(1U)

#define S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE    6
#define V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE)
#define F_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE    V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(1U)

#define S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE    5
#define V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE)
#define F_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE    V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(1U)

#define S_DEBUG_ST_FLM_IDMA0_CACHE    3
#define M_DEBUG_ST_FLM_IDMA0_CACHE    0x3U
#define V_DEBUG_ST_FLM_IDMA0_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CACHE)
#define G_DEBUG_ST_FLM_IDMA0_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CACHE) & M_DEBUG_ST_FLM_IDMA0_CACHE)

#define S_DEBUG_ST_FLM_IDMA0_CTXT    0
#define M_DEBUG_ST_FLM_IDMA0_CTXT    0x7U
#define V_DEBUG_ST_FLM_IDMA0_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CTXT)
#define G_DEBUG_ST_FLM_IDMA0_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CTXT) & M_DEBUG_ST_FLM_IDMA0_CTXT)

#define A_SGE_DEBUG_DATA_HIGH_INDEX_12 0x12b0

#define S_DEBUG_CPLSW_SOP1_CNT    28
#define M_DEBUG_CPLSW_SOP1_CNT    0xfU
#define V_DEBUG_CPLSW_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_SOP1_CNT)
#define G_DEBUG_CPLSW_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP1_CNT) & M_DEBUG_CPLSW_SOP1_CNT)

#define S_DEBUG_CPLSW_EOP1_CNT    24
#define M_DEBUG_CPLSW_EOP1_CNT    0xfU
#define V_DEBUG_CPLSW_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_EOP1_CNT)
#define G_DEBUG_CPLSW_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP1_CNT) & M_DEBUG_CPLSW_EOP1_CNT)

#define S_DEBUG_CPLSW_SOP0_CNT    20
#define M_DEBUG_CPLSW_SOP0_CNT    0xfU
#define V_DEBUG_CPLSW_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_SOP0_CNT)
#define G_DEBUG_CPLSW_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP0_CNT) & M_DEBUG_CPLSW_SOP0_CNT)

#define S_DEBUG_CPLSW_EOP0_CNT    16
#define M_DEBUG_CPLSW_EOP0_CNT    0xfU
#define V_DEBUG_CPLSW_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_EOP0_CNT)
#define G_DEBUG_CPLSW_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP0_CNT) & M_DEBUG_CPLSW_EOP0_CNT)

#define S_DEBUG_PC_RSP_SOP2_CNT    12
#define M_DEBUG_PC_RSP_SOP2_CNT    0xfU
#define V_DEBUG_PC_RSP_SOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP2_CNT)
#define G_DEBUG_PC_RSP_SOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP2_CNT) & M_DEBUG_PC_RSP_SOP2_CNT)

#define S_DEBUG_PC_RSP_EOP2_CNT    8
#define M_DEBUG_PC_RSP_EOP2_CNT    0xfU
#define V_DEBUG_PC_RSP_EOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP2_CNT)
#define G_DEBUG_PC_RSP_EOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP2_CNT) & M_DEBUG_PC_RSP_EOP2_CNT)

#define S_DEBUG_PC_REQ_SOP2_CNT    4
#define M_DEBUG_PC_REQ_SOP2_CNT    0xfU
#define V_DEBUG_PC_REQ_SOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP2_CNT)
#define G_DEBUG_PC_REQ_SOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP2_CNT) & M_DEBUG_PC_REQ_SOP2_CNT)

#define S_DEBUG_PC_REQ_EOP2_CNT    0
#define M_DEBUG_PC_REQ_EOP2_CNT    0xfU
#define V_DEBUG_PC_REQ_EOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP2_CNT)
#define G_DEBUG_PC_REQ_EOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP2_CNT) & M_DEBUG_PC_REQ_EOP2_CNT)

#define S_DEBUG_IDMA1_ISHIFT_TX_SIZE    8
#define M_DEBUG_IDMA1_ISHIFT_TX_SIZE    0x7fU
#define V_DEBUG_IDMA1_ISHIFT_TX_SIZE(x) ((x) << S_DEBUG_IDMA1_ISHIFT_TX_SIZE)
#define G_DEBUG_IDMA1_ISHIFT_TX_SIZE(x) (((x) >> S_DEBUG_IDMA1_ISHIFT_TX_SIZE) & M_DEBUG_IDMA1_ISHIFT_TX_SIZE)

#define S_DEBUG_IDMA0_ISHIFT_TX_SIZE    0
#define M_DEBUG_IDMA0_ISHIFT_TX_SIZE    0x7fU
#define V_DEBUG_IDMA0_ISHIFT_TX_SIZE(x) ((x) << S_DEBUG_IDMA0_ISHIFT_TX_SIZE)
#define G_DEBUG_IDMA0_ISHIFT_TX_SIZE(x) (((x) >> S_DEBUG_IDMA0_ISHIFT_TX_SIZE) & M_DEBUG_IDMA0_ISHIFT_TX_SIZE)

#define A_SGE_DEBUG_DATA_HIGH_INDEX_13 0x12b4
#define A_SGE_DEBUG_DATA_HIGH_INDEX_14 0x12b8
#define A_SGE_DEBUG_DATA_HIGH_INDEX_15 0x12bc
#define A_SGE_DEBUG_DATA_LOW_INDEX_0 0x12c0

#define S_DEBUG_ST_IDMA1_FLM_REQ    29
#define M_DEBUG_ST_IDMA1_FLM_REQ    0x7U
#define V_DEBUG_ST_IDMA1_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA1_FLM_REQ)
#define G_DEBUG_ST_IDMA1_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA1_FLM_REQ) & M_DEBUG_ST_IDMA1_FLM_REQ)

#define S_DEBUG_ST_IDMA0_FLM_REQ    26
#define M_DEBUG_ST_IDMA0_FLM_REQ    0x7U
#define V_DEBUG_ST_IDMA0_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA0_FLM_REQ)
#define G_DEBUG_ST_IDMA0_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA0_FLM_REQ) & M_DEBUG_ST_IDMA0_FLM_REQ)

#define S_DEBUG_ST_IMSG_CTXT    23
#define M_DEBUG_ST_IMSG_CTXT    0x7U
#define V_DEBUG_ST_IMSG_CTXT(x) ((x) << S_DEBUG_ST_IMSG_CTXT)
#define G_DEBUG_ST_IMSG_CTXT(x) (((x) >> S_DEBUG_ST_IMSG_CTXT) & M_DEBUG_ST_IMSG_CTXT)

#define S_DEBUG_ST_IMSG    18
#define M_DEBUG_ST_IMSG    0x1fU
#define V_DEBUG_ST_IMSG(x) ((x) << S_DEBUG_ST_IMSG)
#define G_DEBUG_ST_IMSG(x) (((x) >> S_DEBUG_ST_IMSG) & M_DEBUG_ST_IMSG)

#define S_DEBUG_ST_IDMA1_IALN    16
#define M_DEBUG_ST_IDMA1_IALN    0x3U
#define V_DEBUG_ST_IDMA1_IALN(x) ((x) << S_DEBUG_ST_IDMA1_IALN)
#define G_DEBUG_ST_IDMA1_IALN(x) (((x) >> S_DEBUG_ST_IDMA1_IALN) & M_DEBUG_ST_IDMA1_IALN)

#define S_DEBUG_ST_IDMA1_IDMA_SM    9
#define M_DEBUG_ST_IDMA1_IDMA_SM    0x3fU
#define V_DEBUG_ST_IDMA1_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA1_IDMA_SM)
#define G_DEBUG_ST_IDMA1_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA1_IDMA_SM) & M_DEBUG_ST_IDMA1_IDMA_SM)

#define S_DEBUG_ST_IDMA0_IALN    7
#define M_DEBUG_ST_IDMA0_IALN    0x3U
#define V_DEBUG_ST_IDMA0_IALN(x) ((x) << S_DEBUG_ST_IDMA0_IALN)
#define G_DEBUG_ST_IDMA0_IALN(x) (((x) >> S_DEBUG_ST_IDMA0_IALN) & M_DEBUG_ST_IDMA0_IALN)

#define S_DEBUG_ST_IDMA0_IDMA_SM    0
#define M_DEBUG_ST_IDMA0_IDMA_SM    0x3fU
#define V_DEBUG_ST_IDMA0_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA0_IDMA_SM)
#define G_DEBUG_ST_IDMA0_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA0_IDMA_SM) & M_DEBUG_ST_IDMA0_IDMA_SM)

#define A_SGE_DEBUG_DATA_LOW_INDEX_1 0x12c4

#define S_DEBUG_ITP_EMPTY    12
#define M_DEBUG_ITP_EMPTY    0x3fU
#define V_DEBUG_ITP_EMPTY(x) ((x) << S_DEBUG_ITP_EMPTY)
#define G_DEBUG_ITP_EMPTY(x) (((x) >> S_DEBUG_ITP_EMPTY) & M_DEBUG_ITP_EMPTY)

#define S_DEBUG_ITP_EXPIRED    6
#define M_DEBUG_ITP_EXPIRED    0x3fU
#define V_DEBUG_ITP_EXPIRED(x) ((x) << S_DEBUG_ITP_EXPIRED)
#define G_DEBUG_ITP_EXPIRED(x) (((x) >> S_DEBUG_ITP_EXPIRED) & M_DEBUG_ITP_EXPIRED)

#define S_DEBUG_ITP_PAUSE    5
#define V_DEBUG_ITP_PAUSE(x) ((x) << S_DEBUG_ITP_PAUSE)
#define F_DEBUG_ITP_PAUSE    V_DEBUG_ITP_PAUSE(1U)

#define S_DEBUG_ITP_DEL_DONE    4
#define V_DEBUG_ITP_DEL_DONE(x) ((x) << S_DEBUG_ITP_DEL_DONE)
#define F_DEBUG_ITP_DEL_DONE    V_DEBUG_ITP_DEL_DONE(1U)

#define S_DEBUG_ITP_ADD_DONE    3
#define V_DEBUG_ITP_ADD_DONE(x) ((x) << S_DEBUG_ITP_ADD_DONE)
#define F_DEBUG_ITP_ADD_DONE    V_DEBUG_ITP_ADD_DONE(1U)

#define S_DEBUG_ITP_EVR_STATE    0
#define M_DEBUG_ITP_EVR_STATE    0x7U
#define V_DEBUG_ITP_EVR_STATE(x) ((x) << S_DEBUG_ITP_EVR_STATE)
#define G_DEBUG_ITP_EVR_STATE(x) (((x) >> S_DEBUG_ITP_EVR_STATE) & M_DEBUG_ITP_EVR_STATE)

#define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8

#define S_DEBUG_ST_DBP_THREAD2_CIMFL    25
#define M_DEBUG_ST_DBP_THREAD2_CIMFL    0x1fU
#define V_DEBUG_ST_DBP_THREAD2_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD2_CIMFL)
#define G_DEBUG_ST_DBP_THREAD2_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_CIMFL) & M_DEBUG_ST_DBP_THREAD2_CIMFL)

#define S_DEBUG_ST_DBP_THREAD2_MAIN    20
#define M_DEBUG_ST_DBP_THREAD2_MAIN    0x1fU
#define V_DEBUG_ST_DBP_THREAD2_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD2_MAIN)
#define G_DEBUG_ST_DBP_THREAD2_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_MAIN) & M_DEBUG_ST_DBP_THREAD2_MAIN)

#define S_DEBUG_ST_DBP_THREAD1_CIMFL    15
#define M_DEBUG_ST_DBP_THREAD1_CIMFL    0x1fU
#define V_DEBUG_ST_DBP_THREAD1_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD1_CIMFL)
#define G_DEBUG_ST_DBP_THREAD1_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_CIMFL) & M_DEBUG_ST_DBP_THREAD1_CIMFL)

#define S_DEBUG_ST_DBP_THREAD1_MAIN    10
#define M_DEBUG_ST_DBP_THREAD1_MAIN    0x1fU
#define V_DEBUG_ST_DBP_THREAD1_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD1_MAIN)
#define G_DEBUG_ST_DBP_THREAD1_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_MAIN) & M_DEBUG_ST_DBP_THREAD1_MAIN)

#define S_DEBUG_ST_DBP_THREAD0_CIMFL    5
#define M_DEBUG_ST_DBP_THREAD0_CIMFL    0x1fU
#define V_DEBUG_ST_DBP_THREAD0_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD0_CIMFL)
#define G_DEBUG_ST_DBP_THREAD0_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_CIMFL) & M_DEBUG_ST_DBP_THREAD0_CIMFL)

#define S_DEBUG_ST_DBP_THREAD0_MAIN    0
#define M_DEBUG_ST_DBP_THREAD0_MAIN    0x1fU
#define V_DEBUG_ST_DBP_THREAD0_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD0_MAIN)
#define G_DEBUG_ST_DBP_THREAD0_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_MAIN) & M_DEBUG_ST_DBP_THREAD0_MAIN)

#define S_T6_DEBUG_ST_DBP_UPCP_MAIN    14
#define M_T6_DEBUG_ST_DBP_UPCP_MAIN    0x7U
#define V_T6_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_T6_DEBUG_ST_DBP_UPCP_MAIN)
#define G_T6_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_T6_DEBUG_ST_DBP_UPCP_MAIN) & M_T6_DEBUG_ST_DBP_UPCP_MAIN)

#define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc

#define S_DEBUG_ST_DBP_UPCP_MAIN    14
#define M_DEBUG_ST_DBP_UPCP_MAIN    0x1fU
#define V_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_DEBUG_ST_DBP_UPCP_MAIN)
#define G_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_DEBUG_ST_DBP_UPCP_MAIN) & M_DEBUG_ST_DBP_UPCP_MAIN)

#define S_DEBUG_ST_DBP_DBFIFO_MAIN    13
#define V_DEBUG_ST_DBP_DBFIFO_MAIN(x) ((x) << S_DEBUG_ST_DBP_DBFIFO_MAIN)
#define F_DEBUG_ST_DBP_DBFIFO_MAIN    V_DEBUG_ST_DBP_DBFIFO_MAIN(1U)

#define S_DEBUG_ST_DBP_CTXT    10
#define M_DEBUG_ST_DBP_CTXT    0x7U
#define V_DEBUG_ST_DBP_CTXT(x) ((x) << S_DEBUG_ST_DBP_CTXT)
#define G_DEBUG_ST_DBP_CTXT(x) (((x) >> S_DEBUG_ST_DBP_CTXT) & M_DEBUG_ST_DBP_CTXT)

#define S_DEBUG_ST_DBP_THREAD3_CIMFL    5
#define M_DEBUG_ST_DBP_THREAD3_CIMFL    0x1fU
#define V_DEBUG_ST_DBP_THREAD3_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD3_CIMFL)
#define G_DEBUG_ST_DBP_THREAD3_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_CIMFL) & M_DEBUG_ST_DBP_THREAD3_CIMFL)

#define S_DEBUG_ST_DBP_THREAD3_MAIN    0
#define M_DEBUG_ST_DBP_THREAD3_MAIN    0x1fU
#define V_DEBUG_ST_DBP_THREAD3_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD3_MAIN)
#define G_DEBUG_ST_DBP_THREAD3_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_MAIN) & M_DEBUG_ST_DBP_THREAD3_MAIN)

#define A_SGE_DEBUG_DATA_LOW_INDEX_4 0x12d0

#define S_DEBUG_ST_EDMA3_ALIGN_SUB    29
#define M_DEBUG_ST_EDMA3_ALIGN_SUB    0x7U
#define V_DEBUG_ST_EDMA3_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN_SUB)
#define G_DEBUG_ST_EDMA3_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN_SUB) & M_DEBUG_ST_EDMA3_ALIGN_SUB)

#define S_DEBUG_ST_EDMA3_ALIGN    27
#define M_DEBUG_ST_EDMA3_ALIGN    0x3U
#define V_DEBUG_ST_EDMA3_ALIGN(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN)
#define G_DEBUG_ST_EDMA3_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN) & M_DEBUG_ST_EDMA3_ALIGN)

#define S_DEBUG_ST_EDMA3_REQ    24
#define M_DEBUG_ST_EDMA3_REQ    0x7U
#define V_DEBUG_ST_EDMA3_REQ(x) ((x) << S_DEBUG_ST_EDMA3_REQ)
#define G_DEBUG_ST_EDMA3_REQ(x) (((x) >> S_DEBUG_ST_EDMA3_REQ) & M_DEBUG_ST_EDMA3_REQ)

#define S_DEBUG_ST_EDMA2_ALIGN_SUB    21
#define M_DEBUG_ST_EDMA2_ALIGN_SUB    0x7U
#define V_DEBUG_ST_EDMA2_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN_SUB)
#define G_DEBUG_ST_EDMA2_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN_SUB) & M_DEBUG_ST_EDMA2_ALIGN_SUB)

#define S_DEBUG_ST_EDMA2_ALIGN    19
#define M_DEBUG_ST_EDMA2_ALIGN    0x3U
#define V_DEBUG_ST_EDMA2_ALIGN(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN)
#define G_DEBUG_ST_EDMA2_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN) & M_DEBUG_ST_EDMA2_ALIGN)

#define S_DEBUG_ST_EDMA2_REQ    16
#define M_DEBUG_ST_EDMA2_REQ    0x7U
#define V_DEBUG_ST_EDMA2_REQ(x) ((x) << S_DEBUG_ST_EDMA2_REQ)
#define G_DEBUG_ST_EDMA2_REQ(x) (((x) >> S_DEBUG_ST_EDMA2_REQ) & M_DEBUG_ST_EDMA2_REQ)

#define S_DEBUG_ST_EDMA1_ALIGN_SUB    13
#define M_DEBUG_ST_EDMA1_ALIGN_SUB    0x7U
#define V_DEBUG_ST_EDMA1_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN_SUB)
#define G_DEBUG_ST_EDMA1_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN_SUB) & M_DEBUG_ST_EDMA1_ALIGN_SUB)

#define S_DEBUG_ST_EDMA1_ALIGN    11
#define M_DEBUG_ST_EDMA1_ALIGN    0x3U
#define V_DEBUG_ST_EDMA1_ALIGN(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN)
#define G_DEBUG_ST_EDMA1_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN) & M_DEBUG_ST_EDMA1_ALIGN)

#define S_DEBUG_ST_EDMA1_REQ    8
#define M_DEBUG_ST_EDMA1_REQ    0x7U
#define V_DEBUG_ST_EDMA1_REQ(x) ((x) << S_DEBUG_ST_EDMA1_REQ)
#define G_DEBUG_ST_EDMA1_REQ(x) (((x) >> S_DEBUG_ST_EDMA1_REQ) & M_DEBUG_ST_EDMA1_REQ)

#define S_DEBUG_ST_EDMA0_ALIGN_SUB    5
#define M_DEBUG_ST_EDMA0_ALIGN_SUB    0x7U
#define V_DEBUG_ST_EDMA0_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN_SUB)
#define G_DEBUG_ST_EDMA0_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN_SUB) & M_DEBUG_ST_EDMA0_ALIGN_SUB)

#define S_DEBUG_ST_EDMA0_ALIGN    3
#define M_DEBUG_ST_EDMA0_ALIGN    0x3U
#define V_DEBUG_ST_EDMA0_ALIGN(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN)
#define G_DEBUG_ST_EDMA0_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN) & M_DEBUG_ST_EDMA0_ALIGN)

#define S_DEBUG_ST_EDMA0_REQ    0
#define M_DEBUG_ST_EDMA0_REQ    0x7U
#define V_DEBUG_ST_EDMA0_REQ(x) ((x) << S_DEBUG_ST_EDMA0_REQ)
#define G_DEBUG_ST_EDMA0_REQ(x) (((x) >> S_DEBUG_ST_EDMA0_REQ) & M_DEBUG_ST_EDMA0_REQ)

#define A_SGE_DEBUG_DATA_LOW_INDEX_5 0x12d4

#define S_DEBUG_ST_FLM_DBPTR    30
#define M_DEBUG_ST_FLM_DBPTR    0x3U
#define V_DEBUG_ST_FLM_DBPTR(x) ((x) << S_DEBUG_ST_FLM_DBPTR)
#define G_DEBUG_ST_FLM_DBPTR(x) (((x) >> S_DEBUG_ST_FLM_DBPTR) & M_DEBUG_ST_FLM_DBPTR)

#define S_DEBUG_FLM_CACHE_LOCKED_COUNT    23
#define M_DEBUG_FLM_CACHE_LOCKED_COUNT    0x7fU
#define V_DEBUG_FLM_CACHE_LOCKED_COUNT(x) ((x) << S_DEBUG_FLM_CACHE_LOCKED_COUNT)
#define G_DEBUG_FLM_CACHE_LOCKED_COUNT(x) (((x) >> S_DEBUG_FLM_CACHE_LOCKED_COUNT) & M_DEBUG_FLM_CACHE_LOCKED_COUNT)

#define S_DEBUG_FLM_CACHE_AGENT    20
#define M_DEBUG_FLM_CACHE_AGENT    0x7U
#define V_DEBUG_FLM_CACHE_AGENT(x) ((x) << S_DEBUG_FLM_CACHE_AGENT)
#define G_DEBUG_FLM_CACHE_AGENT(x) (((x) >> S_DEBUG_FLM_CACHE_AGENT) & M_DEBUG_FLM_CACHE_AGENT)

#define S_DEBUG_ST_FLM_CACHE    16
#define M_DEBUG_ST_FLM_CACHE    0xfU
#define V_DEBUG_ST_FLM_CACHE(x) ((x) << S_DEBUG_ST_FLM_CACHE)
#define G_DEBUG_ST_FLM_CACHE(x) (((x) >> S_DEBUG_ST_FLM_CACHE) & M_DEBUG_ST_FLM_CACHE)

#define S_DEBUG_FLM_DBPTR_CIDX_STALL    12
#define V_DEBUG_FLM_DBPTR_CIDX_STALL(x) ((x) << S_DEBUG_FLM_DBPTR_CIDX_STALL)
#define F_DEBUG_FLM_DBPTR_CIDX_STALL    V_DEBUG_FLM_DBPTR_CIDX_STALL(1U)

#define S_DEBUG_FLM_DBPTR_QID    0
#define M_DEBUG_FLM_DBPTR_QID    0xfffU
#define V_DEBUG_FLM_DBPTR_QID(x) ((x) << S_DEBUG_FLM_DBPTR_QID)
#define G_DEBUG_FLM_DBPTR_QID(x) (((x) >> S_DEBUG_FLM_DBPTR_QID) & M_DEBUG_FLM_DBPTR_QID)

#define A_SGE_DEBUG0_DBP_THREAD 0x12d4

#define S_THREAD_ST_MAIN    25
#define M_THREAD_ST_MAIN    0x3fU
#define V_THREAD_ST_MAIN(x) ((x) << S_THREAD_ST_MAIN)
#define G_THREAD_ST_MAIN(x) (((x) >> S_THREAD_ST_MAIN) & M_THREAD_ST_MAIN)

#define S_THREAD_ST_CIMFL    21
#define M_THREAD_ST_CIMFL    0xfU
#define V_THREAD_ST_CIMFL(x) ((x) << S_THREAD_ST_CIMFL)
#define G_THREAD_ST_CIMFL(x) (((x) >> S_THREAD_ST_CIMFL) & M_THREAD_ST_CIMFL)

#define S_THREAD_CMDOP    17
#define M_THREAD_CMDOP    0xfU
#define V_THREAD_CMDOP(x) ((x) << S_THREAD_CMDOP)
#define G_THREAD_CMDOP(x) (((x) >> S_THREAD_CMDOP) & M_THREAD_CMDOP)

#define S_THREAD_QID    0
#define M_THREAD_QID    0x1ffffU
#define V_THREAD_QID(x) ((x) << S_THREAD_QID)
#define G_THREAD_QID(x) (((x) >> S_THREAD_QID) & M_THREAD_QID)

#define A_SGE_DEBUG_DATA_LOW_INDEX_6 0x12d8

#define S_DEBUG_DBP_THREAD0_QID    0
#define M_DEBUG_DBP_THREAD0_QID    0x1ffffU
#define V_DEBUG_DBP_THREAD0_QID(x) ((x) << S_DEBUG_DBP_THREAD0_QID)
#define G_DEBUG_DBP_THREAD0_QID(x) (((x) >> S_DEBUG_DBP_THREAD0_QID) & M_DEBUG_DBP_THREAD0_QID)

#define A_SGE_DEBUG_DATA_LOW_INDEX_7 0x12dc

#define S_DEBUG_DBP_THREAD1_QID    0
#define M_DEBUG_DBP_THREAD1_QID    0x1ffffU
#define V_DEBUG_DBP_THREAD1_QID(x) ((x) << S_DEBUG_DBP_THREAD1_QID)
#define G_DEBUG_DBP_THREAD1_QID(x) (((x) >> S_DEBUG_DBP_THREAD1_QID) & M_DEBUG_DBP_THREAD1_QID)

#define A_SGE_DEBUG_DATA_LOW_INDEX_8 0x12e0

#define S_DEBUG_DBP_THREAD2_QID    0
#define M_DEBUG_DBP_THREAD2_QID    0x1ffffU
#define V_DEBUG_DBP_THREAD2_QID(x) ((x) << S_DEBUG_DBP_THREAD2_QID)
#define G_DEBUG_DBP_THREAD2_QID(x) (((x) >> S_DEBUG_DBP_THREAD2_QID) & M_DEBUG_DBP_THREAD2_QID)

#define A_SGE_DEBUG_DATA_LOW_INDEX_9 0x12e4

#define S_DEBUG_DBP_THREAD3_QID    0
#define M_DEBUG_DBP_THREAD3_QID    0x1ffffU
#define V_DEBUG_DBP_THREAD3_QID(x) ((x) << S_DEBUG_DBP_THREAD3_QID)
#define G_DEBUG_DBP_THREAD3_QID(x) (((x) >> S_DEBUG_DBP_THREAD3_QID) & M_DEBUG_DBP_THREAD3_QID)

#define A_SGE_DEBUG_DATA_LOW_INDEX_10 0x12e8

#define S_DEBUG_IMSG_CPL    16
#define M_DEBUG_IMSG_CPL    0xffU
#define V_DEBUG_IMSG_CPL(x) ((x) << S_DEBUG_IMSG_CPL)
#define G_DEBUG_IMSG_CPL(x) (((x) >> S_DEBUG_IMSG_CPL) & M_DEBUG_IMSG_CPL)

#define S_DEBUG_IMSG_QID    0
#define M_DEBUG_IMSG_QID    0xffffU
#define V_DEBUG_IMSG_QID(x) ((x) << S_DEBUG_IMSG_QID)
#define G_DEBUG_IMSG_QID(x) (((x) >> S_DEBUG_IMSG_QID) & M_DEBUG_IMSG_QID)

#define A_SGE_DEBUG_DATA_LOW_INDEX_11 0x12ec

#define S_DEBUG_IDMA1_QID    16
#define M_DEBUG_IDMA1_QID    0xffffU
#define V_DEBUG_IDMA1_QID(x) ((x) << S_DEBUG_IDMA1_QID)
#define G_DEBUG_IDMA1_QID(x) (((x) >> S_DEBUG_IDMA1_QID) & M_DEBUG_IDMA1_QID)

#define S_DEBUG_IDMA0_QID    0
#define M_DEBUG_IDMA0_QID    0xffffU
#define V_DEBUG_IDMA0_QID(x) ((x) << S_DEBUG_IDMA0_QID)
#define G_DEBUG_IDMA0_QID(x) (((x) >> S_DEBUG_IDMA0_QID) & M_DEBUG_IDMA0_QID)

#define A_SGE_DEBUG_DATA_LOW_INDEX_12 0x12f0

#define S_DEBUG_IDMA1_FLM_REQ_QID    16
#define M_DEBUG_IDMA1_FLM_REQ_QID    0xffffU
#define V_DEBUG_IDMA1_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA1_FLM_REQ_QID)
#define G_DEBUG_IDMA1_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA1_FLM_REQ_QID) & M_DEBUG_IDMA1_FLM_REQ_QID)

#define S_DEBUG_IDMA0_FLM_REQ_QID    0
#define M_DEBUG_IDMA0_FLM_REQ_QID    0xffffU
#define V_DEBUG_IDMA0_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA0_FLM_REQ_QID)
#define G_DEBUG_IDMA0_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA0_FLM_REQ_QID) & M_DEBUG_IDMA0_FLM_REQ_QID)

#define A_SGE_DEBUG_DATA_LOW_INDEX_13 0x12f4
#define A_SGE_DEBUG_DATA_LOW_INDEX_14 0x12f8
#define A_SGE_DEBUG_DATA_LOW_INDEX_15 0x12fc
#define A_SGE_WC_EGRS_BAR2_OFF_PF 0x1300

#define S_PFIQSPERPAGE    28
#define M_PFIQSPERPAGE    0xfU
#define V_PFIQSPERPAGE(x) ((x) << S_PFIQSPERPAGE)
#define G_PFIQSPERPAGE(x) (((x) >> S_PFIQSPERPAGE) & M_PFIQSPERPAGE)

#define S_PFEQSPERPAGE    24
#define M_PFEQSPERPAGE    0xfU
#define V_PFEQSPERPAGE(x) ((x) << S_PFEQSPERPAGE)
#define G_PFEQSPERPAGE(x) (((x) >> S_PFEQSPERPAGE) & M_PFEQSPERPAGE)

#define S_PFWCQSPERPAGE    20
#define M_PFWCQSPERPAGE    0xfU
#define V_PFWCQSPERPAGE(x) ((x) << S_PFWCQSPERPAGE)
#define G_PFWCQSPERPAGE(x) (((x) >> S_PFWCQSPERPAGE) & M_PFWCQSPERPAGE)

#define S_PFWCOFFEN    19
#define V_PFWCOFFEN(x) ((x) << S_PFWCOFFEN)
#define F_PFWCOFFEN    V_PFWCOFFEN(1U)

#define S_PFMAXWCSIZE    17
#define M_PFMAXWCSIZE    0x3U
#define V_PFMAXWCSIZE(x) ((x) << S_PFMAXWCSIZE)
#define G_PFMAXWCSIZE(x) (((x) >> S_PFMAXWCSIZE) & M_PFMAXWCSIZE)

#define S_PFWCOFFSET    0
#define M_PFWCOFFSET    0x1ffffU
#define V_PFWCOFFSET(x) ((x) << S_PFWCOFFSET)
#define G_PFWCOFFSET(x) (((x) >> S_PFWCOFFSET) & M_PFWCOFFSET)

#define A_SGE_WC_EGRS_BAR2_OFF_VF 0x1320

#define S_VFIQSPERPAGE    28
#define M_VFIQSPERPAGE    0xfU
#define V_VFIQSPERPAGE(x) ((x) << S_VFIQSPERPAGE)
#define G_VFIQSPERPAGE(x) (((x) >> S_VFIQSPERPAGE) & M_VFIQSPERPAGE)

#define S_VFEQSPERPAGE    24
#define M_VFEQSPERPAGE    0xfU
#define V_VFEQSPERPAGE(x) ((x) << S_VFEQSPERPAGE)
#define G_VFEQSPERPAGE(x) (((x) >> S_VFEQSPERPAGE) & M_VFEQSPERPAGE)

#define S_VFWCQSPERPAGE    20
#define M_VFWCQSPERPAGE    0xfU
#define V_VFWCQSPERPAGE(x) ((x) << S_VFWCQSPERPAGE)
#define G_VFWCQSPERPAGE(x) (((x) >> S_VFWCQSPERPAGE) & M_VFWCQSPERPAGE)

#define S_VFWCOFFEN    19
#define V_VFWCOFFEN(x) ((x) << S_VFWCOFFEN)
#define F_VFWCOFFEN    V_VFWCOFFEN(1U)

#define S_VFMAXWCSIZE    17
#define M_VFMAXWCSIZE    0x3U
#define V_VFMAXWCSIZE(x) ((x) << S_VFMAXWCSIZE)
#define G_VFMAXWCSIZE(x) (((x) >> S_VFMAXWCSIZE) & M_VFMAXWCSIZE)

#define S_VFWCOFFSET    0
#define M_VFWCOFFSET    0x1ffffU
#define V_VFWCOFFSET(x) ((x) << S_VFWCOFFSET)
#define G_VFWCOFFSET(x) (((x) >> S_VFWCOFFSET) & M_VFWCOFFSET)

#define A_SGE_LA_RDPTR_0 0x1800
#define A_SGE_LA_RDDATA_0 0x1804
#define A_SGE_LA_WRPTR_0 0x1808
#define A_SGE_LA_RESERVED_0 0x180c
#define A_SGE_LA_RDPTR_1 0x1810
#define A_SGE_LA_RDDATA_1 0x1814
#define A_SGE_LA_WRPTR_1 0x1818
#define A_SGE_LA_RESERVED_1 0x181c
#define A_SGE_LA_RDPTR_2 0x1820
#define A_SGE_LA_RDDATA_2 0x1824
#define A_SGE_LA_WRPTR_2 0x1828
#define A_SGE_LA_RESERVED_2 0x182c
#define A_SGE_LA_RDPTR_3 0x1830
#define A_SGE_LA_RDDATA_3 0x1834
#define A_SGE_LA_WRPTR_3 0x1838
#define A_SGE_LA_RESERVED_3 0x183c
#define A_SGE_LA_RDPTR_4 0x1840
#define A_SGE_LA_RDDATA_4 0x1844
#define A_SGE_LA_WRPTR_4 0x1848
#define A_SGE_LA_RESERVED_4 0x184c
#define A_SGE_LA_RDPTR_5 0x1850
#define A_SGE_LA_RDDATA_5 0x1854
#define A_SGE_LA_WRPTR_5 0x1858
#define A_SGE_LA_RESERVED_5 0x185c
#define A_SGE_LA_RDPTR_6 0x1860
#define A_SGE_LA_RDDATA_6 0x1864
#define A_SGE_LA_WRPTR_6 0x1868
#define A_SGE_LA_RESERVED_6 0x186c
#define A_SGE_LA_RDPTR_7 0x1870
#define A_SGE_LA_RDDATA_7 0x1874
#define A_SGE_LA_WRPTR_7 0x1878
#define A_SGE_LA_RESERVED_7 0x187c
#define A_SGE_LA_RDPTR_8 0x1880
#define A_SGE_LA_RDDATA_8 0x1884
#define A_SGE_LA_WRPTR_8 0x1888
#define A_SGE_LA_RESERVED_8 0x188c
#define A_SGE_LA_RDPTR_9 0x1890
#define A_SGE_LA_RDDATA_9 0x1894
#define A_SGE_LA_WRPTR_9 0x1898
#define A_SGE_LA_RESERVED_9 0x189c
#define A_SGE_LA_RDPTR_10 0x18a0
#define A_SGE_LA_RDDATA_10 0x18a4
#define A_SGE_LA_WRPTR_10 0x18a8
#define A_SGE_LA_RESERVED_10 0x18ac
#define A_SGE_LA_RDPTR_11 0x18b0
#define A_SGE_LA_RDDATA_11 0x18b4
#define A_SGE_LA_WRPTR_11 0x18b8
#define A_SGE_LA_RESERVED_11 0x18bc
#define A_SGE_LA_RDPTR_12 0x18c0
#define A_SGE_LA_RDDATA_12 0x18c4
#define A_SGE_LA_WRPTR_12 0x18c8
#define A_SGE_LA_RESERVED_12 0x18cc
#define A_SGE_LA_RDPTR_13 0x18d0
#define A_SGE_LA_RDDATA_13 0x18d4
#define A_SGE_LA_WRPTR_13 0x18d8
#define A_SGE_LA_RESERVED_13 0x18dc
#define A_SGE_LA_RDPTR_14 0x18e0
#define A_SGE_LA_RDDATA_14 0x18e4
#define A_SGE_LA_WRPTR_14 0x18e8
#define A_SGE_LA_RESERVED_14 0x18ec
#define A_SGE_LA_RDPTR_15 0x18f0
#define A_SGE_LA_RDDATA_15 0x18f4
#define A_SGE_LA_WRPTR_15 0x18f8
#define A_SGE_LA_RESERVED_15 0x18fc

/* registers for module PCIE */
#define PCIE_BASE_ADDR 0x3000

#define A_PCIE_PF_CFG 0x40

#define S_AIVEC    4
#define M_AIVEC    0x3ffU
#define V_AIVEC(x) ((x) << S_AIVEC)
#define G_AIVEC(x) (((x) >> S_AIVEC) & M_AIVEC)

#define A_PCIE_PF_CLI 0x44
#define A_PCIE_PF_EXPROM_OFST 0x4c

#define S_OFFSET    10
#define M_OFFSET    0x3fffU
#define V_OFFSET(x) ((x) << S_OFFSET)
#define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET)

#define A_PCIE_INT_CAUSE 0x3004

#define S_NONFATALERR    30
#define V_NONFATALERR(x) ((x) << S_NONFATALERR)
#define F_NONFATALERR    V_NONFATALERR(1U)

#define S_UNXSPLCPLERR    29
#define V_UNXSPLCPLERR(x) ((x) << S_UNXSPLCPLERR)
#define F_UNXSPLCPLERR    V_UNXSPLCPLERR(1U)

#define S_PCIEPINT    28
#define V_PCIEPINT(x) ((x) << S_PCIEPINT)
#define F_PCIEPINT    V_PCIEPINT(1U)

#define S_PCIESINT    27
#define V_PCIESINT(x) ((x) << S_PCIESINT)
#define F_PCIESINT    V_PCIESINT(1U)

#define S_RPLPERR    26
#define V_RPLPERR(x) ((x) << S_RPLPERR)
#define F_RPLPERR    V_RPLPERR(1U)

#define S_RXWRPERR    25
#define V_RXWRPERR(x) ((x) << S_RXWRPERR)
#define F_RXWRPERR    V_RXWRPERR(1U)

#define S_RXCPLPERR    24
#define V_RXCPLPERR(x) ((x) << S_RXCPLPERR)
#define F_RXCPLPERR    V_RXCPLPERR(1U)

#define S_PIOTAGPERR    23
#define V_PIOTAGPERR(x) ((x) << S_PIOTAGPERR)
#define F_PIOTAGPERR    V_PIOTAGPERR(1U)

#define S_MATAGPERR    22
#define V_MATAGPERR(x) ((x) << S_MATAGPERR)
#define F_MATAGPERR    V_MATAGPERR(1U)

#define S_INTXCLRPERR    21
#define V_INTXCLRPERR(x) ((x) << S_INTXCLRPERR)
#define F_INTXCLRPERR    V_INTXCLRPERR(1U)

#define S_FIDPERR    20
#define V_FIDPERR(x) ((x) << S_FIDPERR)
#define F_FIDPERR    V_FIDPERR(1U)

#define S_CFGSNPPERR    19
#define V_CFGSNPPERR(x) ((x) << S_CFGSNPPERR)
#define F_CFGSNPPERR    V_CFGSNPPERR(1U)

#define S_HRSPPERR    18
#define V_HRSPPERR(x) ((x) << S_HRSPPERR)
#define F_HRSPPERR    V_HRSPPERR(1U)

#define S_HREQPERR    17
#define V_HREQPERR(x) ((x) << S_HREQPERR)
#define F_HREQPERR    V_HREQPERR(1U)

#define S_HCNTPERR    16
#define V_HCNTPERR(x) ((x) << S_HCNTPERR)
#define F_HCNTPERR    V_HCNTPERR(1U)

#define S_DRSPPERR    15
#define V_DRSPPERR(x) ((x) << S_DRSPPERR)
#define F_DRSPPERR    V_DRSPPERR(1U)

#define S_DREQPERR    14
#define V_DREQPERR(x) ((x) << S_DREQPERR)
#define F_DREQPERR    V_DREQPERR(1U)

#define S_DCNTPERR    13
#define V_DCNTPERR(x) ((x) << S_DCNTPERR)
#define F_DCNTPERR    V_DCNTPERR(1U)

#define S_CRSPPERR    12
#define V_CRSPPERR(x) ((x) << S_CRSPPERR)
#define F_CRSPPERR    V_CRSPPERR(1U)

#define S_CREQPERR    11
#define V_CREQPERR(x) ((x) << S_CREQPERR)
#define F_CREQPERR    V_CREQPERR(1U)

#define S_CCNTPERR    10
#define V_CCNTPERR(x) ((x) << S_CCNTPERR)
#define F_CCNTPERR    V_CCNTPERR(1U)

#define S_TARTAGPERR    9
#define V_TARTAGPERR(x) ((x) << S_TARTAGPERR)
#define F_TARTAGPERR    V_TARTAGPERR(1U)

#define S_PIOREQPERR    8
#define V_PIOREQPERR(x) ((x) << S_PIOREQPERR)
#define F_PIOREQPERR    V_PIOREQPERR(1U)

#define S_PIOCPLPERR    7
#define V_PIOCPLPERR(x) ((x) << S_PIOCPLPERR)
#define F_PIOCPLPERR    V_PIOCPLPERR(1U)

#define S_MSIXDIPERR    6
#define V_MSIXDIPERR(x) ((x) << S_MSIXDIPERR)
#define F_MSIXDIPERR    V_MSIXDIPERR(1U)

#define S_MSIXDATAPERR    5
#define V_MSIXDATAPERR(x) ((x) << S_MSIXDATAPERR)
#define F_MSIXDATAPERR    V_MSIXDATAPERR(1U)

#define S_MSIXADDRHPERR    4
#define V_MSIXADDRHPERR(x) ((x) << S_MSIXADDRHPERR)
#define F_MSIXADDRHPERR    V_MSIXADDRHPERR(1U)

#define S_MSIXADDRLPERR    3
#define V_MSIXADDRLPERR(x) ((x) << S_MSIXADDRLPERR)
#define F_MSIXADDRLPERR    V_MSIXADDRLPERR(1U)

#define S_MSIDATAPERR    2
#define V_MSIDATAPERR(x) ((x) << S_MSIDATAPERR)
#define F_MSIDATAPERR    V_MSIDATAPERR(1U)

#define S_MSIADDRHPERR    1
#define V_MSIADDRHPERR(x) ((x) << S_MSIADDRHPERR)
#define F_MSIADDRHPERR    V_MSIADDRHPERR(1U)

#define S_MSIADDRLPERR    0
#define V_MSIADDRLPERR(x) ((x) << S_MSIADDRLPERR)
#define F_MSIADDRLPERR    V_MSIADDRLPERR(1U)

#define S_IPGRPPERR    31
#define V_IPGRPPERR(x) ((x) << S_IPGRPPERR)
#define F_IPGRPPERR    V_IPGRPPERR(1U)

#define S_READRSPERR    29
#define V_READRSPERR(x) ((x) << S_READRSPERR)
#define F_READRSPERR    V_READRSPERR(1U)

#define S_TRGT1GRPPERR    28
#define V_TRGT1GRPPERR(x) ((x) << S_TRGT1GRPPERR)
#define F_TRGT1GRPPERR    V_TRGT1GRPPERR(1U)

#define S_IPSOTPERR    27
#define V_IPSOTPERR(x) ((x) << S_IPSOTPERR)
#define F_IPSOTPERR    V_IPSOTPERR(1U)

#define S_IPRETRYPERR    26
#define V_IPRETRYPERR(x) ((x) << S_IPRETRYPERR)
#define F_IPRETRYPERR    V_IPRETRYPERR(1U)

#define S_IPRXDATAGRPPERR    25
#define V_IPRXDATAGRPPERR(x) ((x) << S_IPRXDATAGRPPERR)
#define F_IPRXDATAGRPPERR    V_IPRXDATAGRPPERR(1U)

#define S_IPRXHDRGRPPERR    24
#define V_IPRXHDRGRPPERR(x) ((x) << S_IPRXHDRGRPPERR)
#define F_IPRXHDRGRPPERR    V_IPRXHDRGRPPERR(1U)

#define S_PIOTAGQPERR    23
#define V_PIOTAGQPERR(x) ((x) << S_PIOTAGQPERR)
#define F_PIOTAGQPERR    V_PIOTAGQPERR(1U)

#define S_MAGRPPERR    22
#define V_MAGRPPERR(x) ((x) << S_MAGRPPERR)
#define F_MAGRPPERR    V_MAGRPPERR(1U)

#define S_VFIDPERR    21
#define V_VFIDPERR(x) ((x) << S_VFIDPERR)
#define F_VFIDPERR    V_VFIDPERR(1U)

#define S_HREQRDPERR    17
#define V_HREQRDPERR(x) ((x) << S_HREQRDPERR)
#define F_HREQRDPERR    V_HREQRDPERR(1U)

#define S_HREQWRPERR    16
#define V_HREQWRPERR(x) ((x) << S_HREQWRPERR)
#define F_HREQWRPERR    V_HREQWRPERR(1U)

#define S_DREQRDPERR    14
#define V_DREQRDPERR(x) ((x) << S_DREQRDPERR)
#define F_DREQRDPERR    V_DREQRDPERR(1U)

#define S_DREQWRPERR    13
#define V_DREQWRPERR(x) ((x) << S_DREQWRPERR)
#define F_DREQWRPERR    V_DREQWRPERR(1U)

#define S_CREQRDPERR    11
#define V_CREQRDPERR(x) ((x) << S_CREQRDPERR)
#define F_CREQRDPERR    V_CREQRDPERR(1U)

#define S_MSTTAGQPERR    10
#define V_MSTTAGQPERR(x) ((x) << S_MSTTAGQPERR)
#define F_MSTTAGQPERR    V_MSTTAGQPERR(1U)

#define S_TGTTAGQPERR    9
#define V_TGTTAGQPERR(x) ((x) << S_TGTTAGQPERR)
#define F_TGTTAGQPERR    V_TGTTAGQPERR(1U)

#define S_PIOREQGRPPERR    8
#define V_PIOREQGRPPERR(x) ((x) << S_PIOREQGRPPERR)
#define F_PIOREQGRPPERR    V_PIOREQGRPPERR(1U)

#define S_PIOCPLGRPPERR    7
#define V_PIOCPLGRPPERR(x) ((x) << S_PIOCPLGRPPERR)
#define F_PIOCPLGRPPERR    V_PIOCPLGRPPERR(1U)

#define S_MSIXSTIPERR    2
#define V_MSIXSTIPERR(x) ((x) << S_MSIXSTIPERR)
#define F_MSIXSTIPERR    V_MSIXSTIPERR(1U)

#define S_MSTTIMEOUTPERR    1
#define V_MSTTIMEOUTPERR(x) ((x) << S_MSTTIMEOUTPERR)
#define F_MSTTIMEOUTPERR    V_MSTTIMEOUTPERR(1U)

#define S_MSTGRPPERR    0
#define V_MSTGRPPERR(x) ((x) << S_MSTGRPPERR)
#define F_MSTGRPPERR    V_MSTGRPPERR(1U)

#define A_PCIE_NONFAT_ERR 0x3010

#define S_RDRSPERR    9
#define V_RDRSPERR(x) ((x) << S_RDRSPERR)
#define F_RDRSPERR    V_RDRSPERR(1U)

#define S_VPDRSPERR    8
#define V_VPDRSPERR(x) ((x) << S_VPDRSPERR)
#define F_VPDRSPERR    V_VPDRSPERR(1U)

#define S_POPD    7
#define V_POPD(x) ((x) << S_POPD)
#define F_POPD    V_POPD(1U)

#define S_POPH    6
#define V_POPH(x) ((x) << S_POPH)
#define F_POPH    V_POPH(1U)

#define S_POPC    5
#define V_POPC(x) ((x) << S_POPC)
#define F_POPC    V_POPC(1U)

#define S_MEMREQ    4
#define V_MEMREQ(x) ((x) << S_MEMREQ)
#define F_MEMREQ    V_MEMREQ(1U)

#define S_PIOREQ    3
#define V_PIOREQ(x) ((x) << S_PIOREQ)
#define F_PIOREQ    V_PIOREQ(1U)

#define S_TAGDROP    2
#define V_TAGDROP(x) ((x) << S_TAGDROP)
#define F_TAGDROP    V_TAGDROP(1U)

#define S_TAGCPL    1
#define V_TAGCPL(x) ((x) << S_TAGCPL)
#define F_TAGCPL    V_TAGCPL(1U)

#define S_CFGSNP    0
#define V_CFGSNP(x) ((x) << S_CFGSNP)
#define F_CFGSNP    V_CFGSNP(1U)

#define S_MAREQTIMEOUT    29
#define V_MAREQTIMEOUT(x) ((x) << S_MAREQTIMEOUT)
#define F_MAREQTIMEOUT    V_MAREQTIMEOUT(1U)

#define S_TRGT1BARTYPEERR    28
#define V_TRGT1BARTYPEERR(x) ((x) << S_TRGT1BARTYPEERR)
#define F_TRGT1BARTYPEERR    V_TRGT1BARTYPEERR(1U)

#define S_MAEXTRARSPERR    27
#define V_MAEXTRARSPERR(x) ((x) << S_MAEXTRARSPERR)
#define F_MAEXTRARSPERR    V_MAEXTRARSPERR(1U)

#define S_MARSPTIMEOUT    26
#define V_MARSPTIMEOUT(x) ((x) << S_MARSPTIMEOUT)
#define F_MARSPTIMEOUT    V_MARSPTIMEOUT(1U)

#define S_INTVFALLMSIDISERR    25
#define V_INTVFALLMSIDISERR(x) ((x) << S_INTVFALLMSIDISERR)
#define F_INTVFALLMSIDISERR    V_INTVFALLMSIDISERR(1U)

#define S_INTVFRANGEERR    24
#define V_INTVFRANGEERR(x) ((x) << S_INTVFRANGEERR)
#define F_INTVFRANGEERR    V_INTVFRANGEERR(1U)

#define S_INTPLIRSPERR    23
#define V_INTPLIRSPERR(x) ((x) << S_INTPLIRSPERR)
#define F_INTPLIRSPERR    V_INTPLIRSPERR(1U)

#define S_MEMREQRDTAGERR    22
#define V_MEMREQRDTAGERR(x) ((x) << S_MEMREQRDTAGERR)
#define F_MEMREQRDTAGERR    V_MEMREQRDTAGERR(1U)

#define S_CFGINITDONEERR    21
#define V_CFGINITDONEERR(x) ((x) << S_CFGINITDONEERR)
#define F_CFGINITDONEERR    V_CFGINITDONEERR(1U)

#define S_BAR2TIMEOUT    20
#define V_BAR2TIMEOUT(x) ((x) << S_BAR2TIMEOUT)
#define F_BAR2TIMEOUT    V_BAR2TIMEOUT(1U)

#define S_VPDTIMEOUT    19
#define V_VPDTIMEOUT(x) ((x) << S_VPDTIMEOUT)
#define F_VPDTIMEOUT    V_VPDTIMEOUT(1U)

#define S_MEMRSPRDTAGERR    18
#define V_MEMRSPRDTAGERR(x) ((x) << S_MEMRSPRDTAGERR)
#define F_MEMRSPRDTAGERR    V_MEMRSPRDTAGERR(1U)

#define S_MEMRSPWRTAGERR    17
#define V_MEMRSPWRTAGERR(x) ((x) << S_MEMRSPWRTAGERR)
#define F_MEMRSPWRTAGERR    V_MEMRSPWRTAGERR(1U)

#define S_PIORSPRDTAGERR    16
#define V_PIORSPRDTAGERR(x) ((x) << S_PIORSPRDTAGERR)
#define F_PIORSPRDTAGERR    V_PIORSPRDTAGERR(1U)

#define S_PIORSPWRTAGERR    15
#define V_PIORSPWRTAGERR(x) ((x) << S_PIORSPWRTAGERR)
#define F_PIORSPWRTAGERR    V_PIORSPWRTAGERR(1U)

#define S_DBITIMEOUT    14
#define V_DBITIMEOUT(x) ((x) << S_DBITIMEOUT)
#define F_DBITIMEOUT    V_DBITIMEOUT(1U)

#define S_PIOUNALINDWR    13
#define V_PIOUNALINDWR(x) ((x) << S_PIOUNALINDWR)
#define F_PIOUNALINDWR    V_PIOUNALINDWR(1U)

#define S_BAR2RDERR    12
#define V_BAR2RDERR(x) ((x) << S_BAR2RDERR)
#define F_BAR2RDERR    V_BAR2RDERR(1U)

#define S_MAWREOPERR    11
#define V_MAWREOPERR(x) ((x) << S_MAWREOPERR)
#define F_MAWREOPERR    V_MAWREOPERR(1U)

#define S_MARDEOPERR    10
#define V_MARDEOPERR(x) ((x) << S_MARDEOPERR)
#define F_MARDEOPERR    V_MARDEOPERR(1U)

#define S_BAR2REQ    2
#define V_BAR2REQ(x) ((x) << S_BAR2REQ)
#define F_BAR2REQ    V_BAR2REQ(1U)

#define S_MARSPUE    30
#define V_MARSPUE(x) ((x) << S_MARSPUE)
#define F_MARSPUE    V_MARSPUE(1U)

#define S_KDBEOPERR    7
#define V_KDBEOPERR(x) ((x) << S_KDBEOPERR)
#define F_KDBEOPERR    V_KDBEOPERR(1U)

#define A_PCIE_CFG2 0x3018

#define S_TOTMAXTAG    0
#define M_TOTMAXTAG    0x7U
#define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG)
#define G_TOTMAXTAG(x) (((x) >> S_TOTMAXTAG) & M_TOTMAXTAG)

#define A_PCIE_CFG_SPACE_REQ 0x3060

#define S_ENABLE    30
#define V_ENABLE(x) ((x) << S_ENABLE)
#define F_ENABLE    V_ENABLE(1U)

#define S_AI    29
#define V_AI(x) ((x) << S_AI)
#define F_AI    V_AI(1U)

#define S_LOCALCFG    28
#define V_LOCALCFG(x) ((x) << S_LOCALCFG)
#define F_LOCALCFG    V_LOCALCFG(1U)

#define S_BUS    20
#define M_BUS    0xffU
#define V_BUS(x) ((x) << S_BUS)
#define G_BUS(x) (((x) >> S_BUS) & M_BUS)

#define S_DEVICE    15
#define M_DEVICE    0x1fU
#define V_DEVICE(x) ((x) << S_DEVICE)
#define G_DEVICE(x) (((x) >> S_DEVICE) & M_DEVICE)

#define S_FUNCTION    12
#define M_FUNCTION    0x7U
#define V_FUNCTION(x) ((x) << S_FUNCTION)
#define G_FUNCTION(x) (((x) >> S_FUNCTION) & M_FUNCTION)

#define S_EXTREGISTER    8
#define M_EXTREGISTER    0xfU
#define V_EXTREGISTER(x) ((x) << S_EXTREGISTER)
#define G_EXTREGISTER(x) (((x) >> S_EXTREGISTER) & M_EXTREGISTER)

#define S_REGISTER    0
#define M_REGISTER    0xffU
#define V_REGISTER(x) ((x) << S_REGISTER)
#define G_REGISTER(x) (((x) >> S_REGISTER) & M_REGISTER)

#define S_CS2    28
#define V_CS2(x) ((x) << S_CS2)
#define F_CS2    V_CS2(1U)

#define S_WRBE    24
#define M_WRBE    0xfU
#define V_WRBE(x) ((x) << S_WRBE)
#define G_WRBE(x) (((x) >> S_WRBE) & M_WRBE)

#define S_CFG_SPACE_VFVLD    23
#define V_CFG_SPACE_VFVLD(x) ((x) << S_CFG_SPACE_VFVLD)
#define F_CFG_SPACE_VFVLD    V_CFG_SPACE_VFVLD(1U)

#define S_CFG_SPACE_RVF    16
#define M_CFG_SPACE_RVF    0x7fU
#define V_CFG_SPACE_RVF(x) ((x) << S_CFG_SPACE_RVF)
#define G_CFG_SPACE_RVF(x) (((x) >> S_CFG_SPACE_RVF) & M_CFG_SPACE_RVF)

#define S_CFG_SPACE_PF    12
#define M_CFG_SPACE_PF    0x7U
#define V_CFG_SPACE_PF(x) ((x) << S_CFG_SPACE_PF)
#define G_CFG_SPACE_PF(x) (((x) >> S_CFG_SPACE_PF) & M_CFG_SPACE_PF)

#define S_T6_ENABLE    31
#define V_T6_ENABLE(x) ((x) << S_T6_ENABLE)
#define F_T6_ENABLE    V_T6_ENABLE(1U)

#define S_T6_AI    30
#define V_T6_AI(x) ((x) << S_T6_AI)
#define F_T6_AI    V_T6_AI(1U)

#define S_T6_CS2    29
#define V_T6_CS2(x) ((x) << S_T6_CS2)
#define F_T6_CS2    V_T6_CS2(1U)

#define S_T6_WRBE    25
#define M_T6_WRBE    0xfU
#define V_T6_WRBE(x) ((x) << S_T6_WRBE)
#define G_T6_WRBE(x) (((x) >> S_T6_WRBE) & M_T6_WRBE)

#define S_T6_CFG_SPACE_VFVLD    24
#define V_T6_CFG_SPACE_VFVLD(x) ((x) << S_T6_CFG_SPACE_VFVLD)
#define F_T6_CFG_SPACE_VFVLD    V_T6_CFG_SPACE_VFVLD(1U)

#define S_T6_CFG_SPACE_RVF    16
#define M_T6_CFG_SPACE_RVF    0xffU
#define V_T6_CFG_SPACE_RVF(x) ((x) << S_T6_CFG_SPACE_RVF)
#define G_T6_CFG_SPACE_RVF(x) (((x) >> S_T6_CFG_SPACE_RVF) & M_T6_CFG_SPACE_RVF)

#define A_PCIE_CFG_SPACE_DATA 0x3064
#define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068

#define S_PCIEOFST    10
#define M_PCIEOFST    0x3fffffU
#define V_PCIEOFST(x) ((x) << S_PCIEOFST)
#define G_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)

#define S_BIR    8
#define M_BIR    0x3U
#define V_BIR(x) ((x) << S_BIR)
#define G_BIR(x) (((x) >> S_BIR) & M_BIR)

#define S_WINDOW    0
#define M_WINDOW    0xffU
#define V_WINDOW(x) ((x) << S_WINDOW)
#define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW)

#define A_PCIE_MEM_ACCESS_OFFSET 0x306c

#define S_MEMOFST    7
#define M_MEMOFST    0x1ffffffU
#define V_MEMOFST(x) ((x) << S_MEMOFST)
#define G_MEMOFST(x) (((x) >> S_MEMOFST) & M_MEMOFST)

#define S_PFNUM    0
#define M_PFNUM    0x7U
#define V_PFNUM(x) ((x) << S_PFNUM)
#define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM)

#define A_PCIE_MA_SYNC 0x30b4
#define A_PCIE_FW 0x30b8
#define A_PCIE_FW_PF 0x30bc
#define A_PCIE_CORE_LINK_WIDTH_SPEED_CHANGE 0x580c

#define S_NUM_LANES    8
#define M_NUM_LANES    0x1fU
#define V_NUM_LANES(x) ((x) << S_NUM_LANES)
#define G_NUM_LANES(x) (((x) >> S_NUM_LANES) & M_NUM_LANES)

#define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908

#define S_RNPP    31
#define V_RNPP(x) ((x) << S_RNPP)
#define F_RNPP    V_RNPP(1U)

#define S_RPCP    29
#define V_RPCP(x) ((x) << S_RPCP)
#define F_RPCP    V_RPCP(1U)

#define S_RCIP    27
#define V_RCIP(x) ((x) << S_RCIP)
#define F_RCIP    V_RCIP(1U)

#define S_RCCP    26
#define V_RCCP(x) ((x) << S_RCCP)
#define F_RCCP    V_RCCP(1U)

#define S_RFTP    23
#define V_RFTP(x) ((x) << S_RFTP)
#define F_RFTP    V_RFTP(1U)

#define S_PTRP    20
#define V_PTRP(x) ((x) << S_PTRP)
#define F_PTRP    V_PTRP(1U)

#define A_PCIE_T5_DMA_STAT2 0x5948

#define S_COOKIECNT    24
#define M_COOKIECNT    0xfU
#define V_COOKIECNT(x) ((x) << S_COOKIECNT)
#define G_COOKIECNT(x) (((x) >> S_COOKIECNT) & M_COOKIECNT)

#define S_RDSEQNUMUPDCNT    20
#define M_RDSEQNUMUPDCNT    0xfU
#define V_RDSEQNUMUPDCNT(x) ((x) << S_RDSEQNUMUPDCNT)
#define G_RDSEQNUMUPDCNT(x) (((x) >> S_RDSEQNUMUPDCNT) & M_RDSEQNUMUPDCNT)

#define S_SIREQCNT    16
#define M_SIREQCNT    0xfU
#define V_SIREQCNT(x) ((x) << S_SIREQCNT)
#define G_SIREQCNT(x) (((x) >> S_SIREQCNT) & M_SIREQCNT)

#define S_WREOPMATCHSOP    12
#define V_WREOPMATCHSOP(x) ((x) << S_WREOPMATCHSOP)
#define F_WREOPMATCHSOP    V_WREOPMATCHSOP(1U)

#define S_WRSOPCNT    8
#define M_WRSOPCNT    0xfU
#define V_WRSOPCNT(x) ((x) << S_WRSOPCNT)
#define G_WRSOPCNT(x) (((x) >> S_WRSOPCNT) & M_WRSOPCNT)

#define S_RDSOPCNT    0
#define M_RDSOPCNT    0xffU
#define V_RDSOPCNT(x) ((x) << S_RDSOPCNT)
#define G_RDSOPCNT(x) (((x) >> S_RDSOPCNT) & M_RDSOPCNT)

#define A_PCIE_T5_DMA_STAT3 0x594c

#define S_ATMREQSOPCNT    24
#define M_ATMREQSOPCNT    0xffU
#define V_ATMREQSOPCNT(x) ((x) << S_ATMREQSOPCNT)
#define G_ATMREQSOPCNT(x) (((x) >> S_ATMREQSOPCNT) & M_ATMREQSOPCNT)

#define S_ATMEOPMATCHSOP    17
#define V_ATMEOPMATCHSOP(x) ((x) << S_ATMEOPMATCHSOP)
#define F_ATMEOPMATCHSOP    V_ATMEOPMATCHSOP(1U)

#define S_RSPEOPMATCHSOP    16
#define V_RSPEOPMATCHSOP(x) ((x) << S_RSPEOPMATCHSOP)
#define F_RSPEOPMATCHSOP    V_RSPEOPMATCHSOP(1U)

#define S_RSPERRCNT    8
#define M_RSPERRCNT    0xffU
#define V_RSPERRCNT(x) ((x) << S_RSPERRCNT)
#define G_RSPERRCNT(x) (((x) >> S_RSPERRCNT) & M_RSPERRCNT)

#define S_RSPSOPCNT    0
#define M_RSPSOPCNT    0xffU
#define V_RSPSOPCNT(x) ((x) << S_RSPSOPCNT)
#define G_RSPSOPCNT(x) (((x) >> S_RSPSOPCNT) & M_RSPSOPCNT)

#define A_PCIE_T5_CMD_STAT2 0x5988
#define A_PCIE_T5_CMD_STAT3 0x598c
#define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4

#define S_TPCP    30
#define V_TPCP(x) ((x) << S_TPCP)
#define F_TPCP    V_TPCP(1U)

#define S_TNPP    29
#define V_TNPP(x) ((x) << S_TNPP)
#define F_TNPP    V_TNPP(1U)

#define S_TFTP    28
#define V_TFTP(x) ((x) << S_TFTP)
#define F_TFTP    V_TFTP(1U)

#define S_TCAP    27
#define V_TCAP(x) ((x) << S_TCAP)
#define F_TCAP    V_TCAP(1U)

#define S_TCIP    26
#define V_TCIP(x) ((x) << S_TCIP)
#define F_TCIP    V_TCIP(1U)

#define S_RCAP    25
#define V_RCAP(x) ((x) << S_RCAP)
#define F_RCAP    V_RCAP(1U)

#define S_PLUP    23
#define V_PLUP(x) ((x) << S_PLUP)
#define F_PLUP    V_PLUP(1U)

#define S_PLDN    22
#define V_PLDN(x) ((x) << S_PLDN)
#define F_PLDN    V_PLDN(1U)

#define S_OTDD    21
#define V_OTDD(x) ((x) << S_OTDD)
#define F_OTDD    V_OTDD(1U)

#define S_GTRP    20
#define V_GTRP(x) ((x) << S_GTRP)
#define F_GTRP    V_GTRP(1U)

#define S_RDPE    18
#define V_RDPE(x) ((x) << S_RDPE)
#define F_RDPE    V_RDPE(1U)

#define S_TDCE    17
#define V_TDCE(x) ((x) << S_TDCE)
#define F_TDCE    V_TDCE(1U)

#define S_TDUE    16
#define V_TDUE(x) ((x) << S_TDUE)
#define F_TDUE    V_TDUE(1U)

#define A_PCIE_CORE_ENDPOINT_STATUS 0x59bc

#define S_PTOM    31
#define V_PTOM(x) ((x) << S_PTOM)
#define F_PTOM    V_PTOM(1U)

#define S_ALEA    29
#define V_ALEA(x) ((x) << S_ALEA)
#define F_ALEA    V_ALEA(1U)

#define S_PMC0    23
#define V_PMC0(x) ((x) << S_PMC0)
#define F_PMC0    V_PMC0(1U)

#define S_PMC1    22
#define V_PMC1(x) ((x) << S_PMC1)
#define F_PMC1    V_PMC1(1U)

#define S_PMC2    21
#define V_PMC2(x) ((x) << S_PMC2)
#define F_PMC2    V_PMC2(1U)

#define S_PMC3    20
#define V_PMC3(x) ((x) << S_PMC3)
#define F_PMC3    V_PMC3(1U)

#define S_PMC4    19
#define V_PMC4(x) ((x) << S_PMC4)
#define F_PMC4    V_PMC4(1U)

#define S_PMC5    18
#define V_PMC5(x) ((x) << S_PMC5)
#define F_PMC5    V_PMC5(1U)

#define S_PMC6    17
#define V_PMC6(x) ((x) << S_PMC6)
#define F_PMC6    V_PMC6(1U)

#define S_PMC7    16
#define V_PMC7(x) ((x) << S_PMC7)
#define F_PMC7    V_PMC7(1U)

#define A_PCIE_CHANGESET 0x59fc
#define A_PCIE_REVISION 0x5a00
#define A_PCIE_PDEBUG_INDEX 0x5a04

#define S_PDEBUGSELH    16
#define M_PDEBUGSELH    0x3fU
#define V_PDEBUGSELH(x) ((x) << S_PDEBUGSELH)
#define G_PDEBUGSELH(x) (((x) >> S_PDEBUGSELH) & M_PDEBUGSELH)

#define S_PDEBUGSELL    0
#define M_PDEBUGSELL    0x3fU
#define V_PDEBUGSELL(x) ((x) << S_PDEBUGSELL)
#define G_PDEBUGSELL(x) (((x) >> S_PDEBUGSELL) & M_PDEBUGSELL)

#define S_T6_PDEBUGSELH    16
#define M_T6_PDEBUGSELH    0x7fU
#define V_T6_PDEBUGSELH(x) ((x) << S_T6_PDEBUGSELH)
#define G_T6_PDEBUGSELH(x) (((x) >> S_T6_PDEBUGSELH) & M_T6_PDEBUGSELH)

#define S_T6_PDEBUGSELL    0
#define M_T6_PDEBUGSELL    0x7fU
#define V_T6_PDEBUGSELL(x) ((x) << S_T6_PDEBUGSELL)
#define G_T6_PDEBUGSELL(x) (((x) >> S_T6_PDEBUGSELL) & M_T6_PDEBUGSELL)

#define A_PCIE_PDEBUG_DATA_HIGH 0x5a08
#define A_PCIE_PDEBUG_DATA_LOW 0x5a0c
#define A_PCIE_CDEBUG_INDEX 0x5a10

#define S_CDEBUGSELH    16
#define M_CDEBUGSELH    0xffU
#define V_CDEBUGSELH(x) ((x) << S_CDEBUGSELH)
#define G_CDEBUGSELH(x) (((x) >> S_CDEBUGSELH) & M_CDEBUGSELH)

#define A_PCIE_CDEBUG_DATA_HIGH 0x5a14
#define A_PCIE_DMAW_SOP_CNT 0x5a1c

#define S_CH3    24
#define M_CH3    0xffU
#define V_CH3(x) ((x) << S_CH3)
#define G_CH3(x) (((x) >> S_CH3) & M_CH3)

#define S_CH2    16
#define M_CH2    0xffU
#define V_CH2(x) ((x) << S_CH2)
#define G_CH2(x) (((x) >> S_CH2) & M_CH2)

#define S_CH1    8
#define M_CH1    0xffU
#define V_CH1(x) ((x) << S_CH1)
#define G_CH1(x) (((x) >> S_CH1) & M_CH1)

#define S_CH0    0
#define M_CH0    0xffU
#define V_CH0(x) ((x) << S_CH0)
#define G_CH0(x) (((x) >> S_CH0) & M_CH0)

#define A_PCIE_DMAW_EOP_CNT 0x5a20
#define A_PCIE_DMAR_REQ_CNT 0x5a24
#define A_PCIE_DMAR_RSP_SOP_CNT 0x5a28
#define A_PCIE_DMAR_RSP_EOP_CNT 0x5a2c
#define A_PCIE_DMAI_CNT 0x5a34
#define A_PCIE_CMDR_REQ_CNT 0x5a3c
#define A_PCIE_CMDR_RSP_CNT 0x5a40

#define S_CH1_EOP    24
#define M_CH1_EOP    0xffU
#define V_CH1_EOP(x) ((x) << S_CH1_EOP)
#define G_CH1_EOP(x) (((x) >> S_CH1_EOP) & M_CH1_EOP)

#define S_CH1_SOP    16
#define M_CH1_SOP    0xffU
#define V_CH1_SOP(x) ((x) << S_CH1_SOP)
#define G_CH1_SOP(x) (((x) >> S_CH1_SOP) & M_CH1_SOP)

#define S_CH0_EOP    8
#define M_CH0_EOP    0xffU
#define V_CH0_EOP(x) ((x) << S_CH0_EOP)
#define G_CH0_EOP(x) (((x) >> S_CH0_EOP) & M_CH0_EOP)

#define S_CH0_SOP    0
#define M_CH0_SOP    0xffU
#define V_CH0_SOP(x) ((x) << S_CH0_SOP)
#define G_CH0_SOP(x) (((x) >> S_CH0_SOP) & M_CH0_SOP)

#define A_PCIE_KDOORBELL_GTS_PF_BASE_LEN 0x5c10

#define S_KDB_PF_LEN    24
#define M_KDB_PF_LEN    0x1fU
#define V_KDB_PF_LEN(x) ((x) << S_KDB_PF_LEN)
#define G_KDB_PF_LEN(x) (((x) >> S_KDB_PF_LEN) & M_KDB_PF_LEN)

#define S_KDB_PF_BASEADDR    0
#define M_KDB_PF_BASEADDR    0xfffffU
#define V_KDB_PF_BASEADDR(x) ((x) << S_KDB_PF_BASEADDR)
#define G_KDB_PF_BASEADDR(x) (((x) >> S_KDB_PF_BASEADDR) & M_KDB_PF_BASEADDR)

#define A_PCIE_KDOORBELL_GTS_VF_BASE_LEN 0x5c14

#define S_KDB_VF_LEN    24
#define M_KDB_VF_LEN    0x1fU
#define V_KDB_VF_LEN(x) ((x) << S_KDB_VF_LEN)
#define G_KDB_VF_LEN(x) (((x) >> S_KDB_VF_LEN) & M_KDB_VF_LEN)

#define S_KDB_VF_BASEADDR    0
#define M_KDB_VF_BASEADDR    0xfffffU
#define V_KDB_VF_BASEADDR(x) ((x) << S_KDB_VF_BASEADDR)
#define G_KDB_VF_BASEADDR(x) (((x) >> S_KDB_VF_BASEADDR) & M_KDB_VF_BASEADDR)

#define A_PCIE_KDOORBELL_GTS_VF_OFFSET 0x5c18

#define S_KDB_VF_MODOFST    0
#define M_KDB_VF_MODOFST    0xfffU
#define V_KDB_VF_MODOFST(x) ((x) << S_KDB_VF_MODOFST)
#define G_KDB_VF_MODOFST(x) (((x) >> S_KDB_VF_MODOFST) & M_KDB_VF_MODOFST)

#define A_PCIE_TGT_SKID_FIFO 0x5e94

#define S_HDRFREECNT    16
#define M_HDRFREECNT    0xfffU
#define V_HDRFREECNT(x) ((x) << S_HDRFREECNT)
#define G_HDRFREECNT(x) (((x) >> S_HDRFREECNT) & M_HDRFREECNT)

#define S_DATAFREECNT    0
#define M_DATAFREECNT    0xfffU
#define V_DATAFREECNT(x) ((x) << S_DATAFREECNT)
#define G_DATAFREECNT(x) (((x) >> S_DATAFREECNT) & M_DATAFREECNT)


/* registers for module DBG */
#define DBG_BASE_ADDR 0x6000

#define A_DBG_GPIO_EN 0x6010

#define S_GPIO15_OEN    31
#define V_GPIO15_OEN(x) ((x) << S_GPIO15_OEN)
#define F_GPIO15_OEN    V_GPIO15_OEN(1U)

#define S_GPIO14_OEN    30
#define V_GPIO14_OEN(x) ((x) << S_GPIO14_OEN)
#define F_GPIO14_OEN    V_GPIO14_OEN(1U)

#define S_GPIO13_OEN    29
#define V_GPIO13_OEN(x) ((x) << S_GPIO13_OEN)
#define F_GPIO13_OEN    V_GPIO13_OEN(1U)

#define S_GPIO12_OEN    28
#define V_GPIO12_OEN(x) ((x) << S_GPIO12_OEN)
#define F_GPIO12_OEN    V_GPIO12_OEN(1U)

#define S_GPIO11_OEN    27
#define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN)
#define F_GPIO11_OEN    V_GPIO11_OEN(1U)

#define S_GPIO10_OEN    26
#define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN)
#define F_GPIO10_OEN    V_GPIO10_OEN(1U)

#define S_GPIO9_OEN    25
#define V_GPIO9_OEN(x) ((x) << S_GPIO9_OEN)
#define F_GPIO9_OEN    V_GPIO9_OEN(1U)

#define S_GPIO8_OEN    24
#define V_GPIO8_OEN(x) ((x) << S_GPIO8_OEN)
#define F_GPIO8_OEN    V_GPIO8_OEN(1U)

#define S_GPIO7_OEN    23
#define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN)
#define F_GPIO7_OEN    V_GPIO7_OEN(1U)

#define S_GPIO6_OEN    22
#define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN)
#define F_GPIO6_OEN    V_GPIO6_OEN(1U)

#define S_GPIO5_OEN    21
#define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN)
#define F_GPIO5_OEN    V_GPIO5_OEN(1U)

#define S_GPIO4_OEN    20
#define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN)
#define F_GPIO4_OEN    V_GPIO4_OEN(1U)

#define S_GPIO3_OEN    19
#define V_GPIO3_OEN(x) ((x) << S_GPIO3_OEN)
#define F_GPIO3_OEN    V_GPIO3_OEN(1U)

#define S_GPIO2_OEN    18
#define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN)
#define F_GPIO2_OEN    V_GPIO2_OEN(1U)

#define S_GPIO1_OEN    17
#define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN)
#define F_GPIO1_OEN    V_GPIO1_OEN(1U)

#define S_GPIO0_OEN    16
#define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN)
#define F_GPIO0_OEN    V_GPIO0_OEN(1U)

#define S_GPIO15_OUT_VAL    15
#define V_GPIO15_OUT_VAL(x) ((x) << S_GPIO15_OUT_VAL)
#define F_GPIO15_OUT_VAL    V_GPIO15_OUT_VAL(1U)

#define S_GPIO14_OUT_VAL    14
#define V_GPIO14_OUT_VAL(x) ((x) << S_GPIO14_OUT_VAL)
#define F_GPIO14_OUT_VAL    V_GPIO14_OUT_VAL(1U)

#define S_GPIO13_OUT_VAL    13
#define V_GPIO13_OUT_VAL(x) ((x) << S_GPIO13_OUT_VAL)
#define F_GPIO13_OUT_VAL    V_GPIO13_OUT_VAL(1U)

#define S_GPIO12_OUT_VAL    12
#define V_GPIO12_OUT_VAL(x) ((x) << S_GPIO12_OUT_VAL)
#define F_GPIO12_OUT_VAL    V_GPIO12_OUT_VAL(1U)

#define S_GPIO11_OUT_VAL    11
#define V_GPIO11_OUT_VAL(x) ((x) << S_GPIO11_OUT_VAL)
#define F_GPIO11_OUT_VAL    V_GPIO11_OUT_VAL(1U)

#define S_GPIO10_OUT_VAL    10
#define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL)
#define F_GPIO10_OUT_VAL    V_GPIO10_OUT_VAL(1U)

#define S_GPIO9_OUT_VAL    9
#define V_GPIO9_OUT_VAL(x) ((x) << S_GPIO9_OUT_VAL)
#define F_GPIO9_OUT_VAL    V_GPIO9_OUT_VAL(1U)

#define S_GPIO8_OUT_VAL    8
#define V_GPIO8_OUT_VAL(x) ((x) << S_GPIO8_OUT_VAL)
#define F_GPIO8_OUT_VAL    V_GPIO8_OUT_VAL(1U)

#define S_GPIO7_OUT_VAL    7
#define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL)
#define F_GPIO7_OUT_VAL    V_GPIO7_OUT_VAL(1U)

#define S_GPIO6_OUT_VAL    6
#define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL)
#define F_GPIO6_OUT_VAL    V_GPIO6_OUT_VAL(1U)

#define S_GPIO5_OUT_VAL    5
#define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL)
#define F_GPIO5_OUT_VAL    V_GPIO5_OUT_VAL(1U)

#define S_GPIO4_OUT_VAL    4
#define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL)
#define F_GPIO4_OUT_VAL    V_GPIO4_OUT_VAL(1U)

#define S_GPIO3_OUT_VAL    3
#define V_GPIO3_OUT_VAL(x) ((x) << S_GPIO3_OUT_VAL)
#define F_GPIO3_OUT_VAL    V_GPIO3_OUT_VAL(1U)

#define S_GPIO2_OUT_VAL    2
#define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL)
#define F_GPIO2_OUT_VAL    V_GPIO2_OUT_VAL(1U)

#define S_GPIO1_OUT_VAL    1
#define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL)
#define F_GPIO1_OUT_VAL    V_GPIO1_OUT_VAL(1U)

#define S_GPIO0_OUT_VAL    0
#define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
#define F_GPIO0_OUT_VAL    V_GPIO0_OUT_VAL(1U)

#define A_DBG_STATIC_C_PLL_CONF2 0x60d4

#define S_STATIC_C_PLL_LOCKTUNE    0
#define M_STATIC_C_PLL_LOCKTUNE    0x1fU
#define V_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_STATIC_C_PLL_LOCKTUNE)
#define G_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_STATIC_C_PLL_LOCKTUNE) & M_STATIC_C_PLL_LOCKTUNE)

#define A_DBG_STATIC_C_PLL_CONF3 0x60d8

#define S_STATIC_C_PLL_LOCKSEL    28
#define V_STATIC_C_PLL_LOCKSEL(x) ((x) << S_STATIC_C_PLL_LOCKSEL)
#define F_STATIC_C_PLL_LOCKSEL    V_STATIC_C_PLL_LOCKSEL(1U)

#define S_STATIC_C_PLL_FFTUNE    12
#define M_STATIC_C_PLL_FFTUNE    0xffffU
#define V_STATIC_C_PLL_FFTUNE(x) ((x) << S_STATIC_C_PLL_FFTUNE)
#define G_STATIC_C_PLL_FFTUNE(x) (((x) >> S_STATIC_C_PLL_FFTUNE) & M_STATIC_C_PLL_FFTUNE)

#define A_DBG_STATIC_C_PLL_CONF5 0x60e0

#define S_STATIC_C_PLL_VCVTUNE    22
#define M_STATIC_C_PLL_VCVTUNE    0x7U
#define V_STATIC_C_PLL_VCVTUNE(x) ((x) << S_STATIC_C_PLL_VCVTUNE)
#define G_STATIC_C_PLL_VCVTUNE(x) (((x) >> S_STATIC_C_PLL_VCVTUNE) & M_STATIC_C_PLL_VCVTUNE)

#define S_STATIC_C_PLL_PREDIV_CNF5    8
#define M_STATIC_C_PLL_PREDIV_CNF5    0x1fU
#define V_STATIC_C_PLL_PREDIV_CNF5(x) ((x) << S_STATIC_C_PLL_PREDIV_CNF5)
#define G_STATIC_C_PLL_PREDIV_CNF5(x) (((x) >> S_STATIC_C_PLL_PREDIV_CNF5) & M_STATIC_C_PLL_PREDIV_CNF5)

#define A_DBG_STATIC_U_PLL_CONF2 0x60e8

#define S_STATIC_U_PLL_LOCKTUNE    0
#define M_STATIC_U_PLL_LOCKTUNE    0x1fU
#define V_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_STATIC_U_PLL_LOCKTUNE)
#define G_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_STATIC_U_PLL_LOCKTUNE) & M_STATIC_U_PLL_LOCKTUNE)

#define A_DBG_STATIC_U_PLL_CONF3 0x60ec

#define S_STATIC_U_PLL_LOCKSEL    28
#define V_STATIC_U_PLL_LOCKSEL(x) ((x) << S_STATIC_U_PLL_LOCKSEL)
#define F_STATIC_U_PLL_LOCKSEL    V_STATIC_U_PLL_LOCKSEL(1U)

#define A_DBG_STATIC_KR_PLL_CONF1 0x60f8

#define S_STATIC_KR_PLL_VBOOSTDIV    27
#define M_STATIC_KR_PLL_VBOOSTDIV    0x7U
#define V_STATIC_KR_PLL_VBOOSTDIV(x) ((x) << S_STATIC_KR_PLL_VBOOSTDIV)
#define G_STATIC_KR_PLL_VBOOSTDIV(x) (((x) >> S_STATIC_KR_PLL_VBOOSTDIV) & M_STATIC_KR_PLL_VBOOSTDIV)

#define S_STATIC_KR_PLL_BGOFFSET    11
#define M_STATIC_KR_PLL_BGOFFSET    0xfU
#define V_STATIC_KR_PLL_BGOFFSET(x) ((x) << S_STATIC_KR_PLL_BGOFFSET)
#define G_STATIC_KR_PLL_BGOFFSET(x) (((x) >> S_STATIC_KR_PLL_BGOFFSET) & M_STATIC_KR_PLL_BGOFFSET)

#define A_DBG_STATIC_KX_PLL_CONF1 0x6108

#define S_STATIC_KX_PLL_VBOOSTDIV    27
#define M_STATIC_KX_PLL_VBOOSTDIV    0x7U
#define V_STATIC_KX_PLL_VBOOSTDIV(x) ((x) << S_STATIC_KX_PLL_VBOOSTDIV)
#define G_STATIC_KX_PLL_VBOOSTDIV(x) (((x) >> S_STATIC_KX_PLL_VBOOSTDIV) & M_STATIC_KX_PLL_VBOOSTDIV)

#define S_STATIC_KX_PLL_BGOFFSET    11
#define M_STATIC_KX_PLL_BGOFFSET    0xfU
#define V_STATIC_KX_PLL_BGOFFSET(x) ((x) << S_STATIC_KX_PLL_BGOFFSET)
#define G_STATIC_KX_PLL_BGOFFSET(x) (((x) >> S_STATIC_KX_PLL_BGOFFSET) & M_STATIC_KX_PLL_BGOFFSET)


/* registers for module MC */
#define MC_BASE_ADDR 0x6200

#define A_MC_PAR_CAUSE 0x7510

#define S_ECC_UE_PAR_CAUSE    3
#define V_ECC_UE_PAR_CAUSE(x) ((x) << S_ECC_UE_PAR_CAUSE)
#define F_ECC_UE_PAR_CAUSE    V_ECC_UE_PAR_CAUSE(1U)

#define S_ECC_CE_PAR_CAUSE    2
#define V_ECC_CE_PAR_CAUSE(x) ((x) << S_ECC_CE_PAR_CAUSE)
#define F_ECC_CE_PAR_CAUSE    V_ECC_CE_PAR_CAUSE(1U)

#define S_FIFOR_PAR_CAUSE    1
#define V_FIFOR_PAR_CAUSE(x) ((x) << S_FIFOR_PAR_CAUSE)
#define F_FIFOR_PAR_CAUSE    V_FIFOR_PAR_CAUSE(1U)

#define S_RDATA_FIFOR_PAR_CAUSE    0
#define V_RDATA_FIFOR_PAR_CAUSE(x) ((x) << S_RDATA_FIFOR_PAR_CAUSE)
#define F_RDATA_FIFOR_PAR_CAUSE    V_RDATA_FIFOR_PAR_CAUSE(1U)

#define A_MC_INT_CAUSE 0x7518

#define S_ECC_UE_INT_CAUSE    2
#define V_ECC_UE_INT_CAUSE(x) ((x) << S_ECC_UE_INT_CAUSE)
#define F_ECC_UE_INT_CAUSE    V_ECC_UE_INT_CAUSE(1U)

#define S_ECC_CE_INT_CAUSE    1
#define V_ECC_CE_INT_CAUSE(x) ((x) << S_ECC_CE_INT_CAUSE)
#define F_ECC_CE_INT_CAUSE    V_ECC_CE_INT_CAUSE(1U)

#define S_PERR_INT_CAUSE    0
#define V_PERR_INT_CAUSE(x) ((x) << S_PERR_INT_CAUSE)
#define F_PERR_INT_CAUSE    V_PERR_INT_CAUSE(1U)

#define A_MC_ECC_STATUS 0x751c

#define S_ECC_CECNT    16
#define M_ECC_CECNT    0xffffU
#define V_ECC_CECNT(x) ((x) << S_ECC_CECNT)
#define G_ECC_CECNT(x) (((x) >> S_ECC_CECNT) & M_ECC_CECNT)

#define S_ECC_UECNT    0
#define M_ECC_UECNT    0xffffU
#define V_ECC_UECNT(x) ((x) << S_ECC_UECNT)
#define G_ECC_UECNT(x) (((x) >> S_ECC_UECNT) & M_ECC_UECNT)

#define A_MC_BIST_CMD 0x7600

#define S_START_BIST    31
#define V_START_BIST(x) ((x) << S_START_BIST)
#define F_START_BIST    V_START_BIST(1U)

#define S_BIST_CMD_GAP    8
#define M_BIST_CMD_GAP    0xffU
#define V_BIST_CMD_GAP(x) ((x) << S_BIST_CMD_GAP)
#define G_BIST_CMD_GAP(x) (((x) >> S_BIST_CMD_GAP) & M_BIST_CMD_GAP)

#define S_BIST_OPCODE    0
#define M_BIST_OPCODE    0x3U
#define V_BIST_OPCODE(x) ((x) << S_BIST_OPCODE)
#define G_BIST_OPCODE(x) (((x) >> S_BIST_OPCODE) & M_BIST_OPCODE)

#define A_MC_BIST_CMD_ADDR 0x7604
#define A_MC_BIST_CMD_LEN 0x7608
#define A_MC_BIST_DATA_PATTERN 0x760c

#define S_BIST_DATA_TYPE    0
#define M_BIST_DATA_TYPE    0xfU
#define V_BIST_DATA_TYPE(x) ((x) << S_BIST_DATA_TYPE)
#define G_BIST_DATA_TYPE(x) (((x) >> S_BIST_DATA_TYPE) & M_BIST_DATA_TYPE)

#define A_MC_BIST_STATUS_RDATA 0x7688

/* registers for module MA */
#define MA_BASE_ADDR 0x7700

#define A_MA_EDRAM0_BAR 0x77c0

#define S_EDRAM0_BASE    16
#define M_EDRAM0_BASE    0xfffU
#define V_EDRAM0_BASE(x) ((x) << S_EDRAM0_BASE)
#define G_EDRAM0_BASE(x) (((x) >> S_EDRAM0_BASE) & M_EDRAM0_BASE)

#define S_EDRAM0_SIZE    0
#define M_EDRAM0_SIZE    0xfffU
#define V_EDRAM0_SIZE(x) ((x) << S_EDRAM0_SIZE)
#define G_EDRAM0_SIZE(x) (((x) >> S_EDRAM0_SIZE) & M_EDRAM0_SIZE)

#define A_MA_EDRAM1_BAR 0x77c4

#define S_EDRAM1_BASE    16
#define M_EDRAM1_BASE    0xfffU
#define V_EDRAM1_BASE(x) ((x) << S_EDRAM1_BASE)
#define G_EDRAM1_BASE(x) (((x) >> S_EDRAM1_BASE) & M_EDRAM1_BASE)

#define S_EDRAM1_SIZE    0
#define M_EDRAM1_SIZE    0xfffU
#define V_EDRAM1_SIZE(x) ((x) << S_EDRAM1_SIZE)
#define G_EDRAM1_SIZE(x) (((x) >> S_EDRAM1_SIZE) & M_EDRAM1_SIZE)

#define A_MA_EXT_MEMORY_BAR 0x77c8

#define S_EXT_MEM_BASE    16
#define M_EXT_MEM_BASE    0xfffU
#define V_EXT_MEM_BASE(x) ((x) << S_EXT_MEM_BASE)
#define G_EXT_MEM_BASE(x) (((x) >> S_EXT_MEM_BASE) & M_EXT_MEM_BASE)

#define S_EXT_MEM_SIZE    0
#define M_EXT_MEM_SIZE    0xfffU
#define V_EXT_MEM_SIZE(x) ((x) << S_EXT_MEM_SIZE)
#define G_EXT_MEM_SIZE(x) (((x) >> S_EXT_MEM_SIZE) & M_EXT_MEM_SIZE)

#define A_MA_EXT_MEMORY0_BAR 0x77c8

#define S_EXT_MEM0_BASE    16
#define M_EXT_MEM0_BASE    0xfffU
#define V_EXT_MEM0_BASE(x) ((x) << S_EXT_MEM0_BASE)
#define G_EXT_MEM0_BASE(x) (((x) >> S_EXT_MEM0_BASE) & M_EXT_MEM0_BASE)

#define S_EXT_MEM0_SIZE    0
#define M_EXT_MEM0_SIZE    0xfffU
#define V_EXT_MEM0_SIZE(x) ((x) << S_EXT_MEM0_SIZE)
#define G_EXT_MEM0_SIZE(x) (((x) >> S_EXT_MEM0_SIZE) & M_EXT_MEM0_SIZE)

#define A_MA_TARGET_MEM_ENABLE 0x77d8

#define S_HMA_ENABLE    3
#define V_HMA_ENABLE(x) ((x) << S_HMA_ENABLE)
#define F_HMA_ENABLE    V_HMA_ENABLE(1U)

#define S_EXT_MEM_ENABLE    2
#define V_EXT_MEM_ENABLE(x) ((x) << S_EXT_MEM_ENABLE)
#define F_EXT_MEM_ENABLE    V_EXT_MEM_ENABLE(1U)

#define S_EDRAM1_ENABLE    1
#define V_EDRAM1_ENABLE(x) ((x) << S_EDRAM1_ENABLE)
#define F_EDRAM1_ENABLE    V_EDRAM1_ENABLE(1U)

#define S_EDRAM0_ENABLE    0
#define V_EDRAM0_ENABLE(x) ((x) << S_EDRAM0_ENABLE)
#define F_EDRAM0_ENABLE    V_EDRAM0_ENABLE(1U)

#define S_HMA_MUX    5
#define V_HMA_MUX(x) ((x) << S_HMA_MUX)
#define F_HMA_MUX    V_HMA_MUX(1U)

#define S_EXT_MEM1_ENABLE    4
#define V_EXT_MEM1_ENABLE(x) ((x) << S_EXT_MEM1_ENABLE)
#define F_EXT_MEM1_ENABLE    V_EXT_MEM1_ENABLE(1U)

#define S_EXT_MEM0_ENABLE    2
#define V_EXT_MEM0_ENABLE(x) ((x) << S_EXT_MEM0_ENABLE)
#define F_EXT_MEM0_ENABLE    V_EXT_MEM0_ENABLE(1U)

#define S_MC_SPLIT    6
#define V_MC_SPLIT(x) ((x) << S_MC_SPLIT)
#define F_MC_SPLIT    V_MC_SPLIT(1U)

#define A_MA_INT_CAUSE 0x77e0

#define S_MEM_PERR_INT_CAUSE    1
#define V_MEM_PERR_INT_CAUSE(x) ((x) << S_MEM_PERR_INT_CAUSE)
#define F_MEM_PERR_INT_CAUSE    V_MEM_PERR_INT_CAUSE(1U)

#define S_MEM_WRAP_INT_CAUSE    0
#define V_MEM_WRAP_INT_CAUSE(x) ((x) << S_MEM_WRAP_INT_CAUSE)
#define F_MEM_WRAP_INT_CAUSE    V_MEM_WRAP_INT_CAUSE(1U)

#define A_MA_INT_WRAP_STATUS 0x77e4

#define S_MEM_WRAP_ADDRESS    4
#define M_MEM_WRAP_ADDRESS    0xfffffffU
#define V_MEM_WRAP_ADDRESS(x) ((x) << S_MEM_WRAP_ADDRESS)
#define G_MEM_WRAP_ADDRESS(x) (((x) >> S_MEM_WRAP_ADDRESS) & M_MEM_WRAP_ADDRESS)

#define S_MEM_WRAP_CLIENT_NUM    0
#define M_MEM_WRAP_CLIENT_NUM    0xfU
#define V_MEM_WRAP_CLIENT_NUM(x) ((x) << S_MEM_WRAP_CLIENT_NUM)
#define G_MEM_WRAP_CLIENT_NUM(x) (((x) >> S_MEM_WRAP_CLIENT_NUM) & M_MEM_WRAP_CLIENT_NUM)

#define A_MA_PARITY_ERROR_STATUS 0x77f4

#define S_TP_DMARBT_PAR_ERROR    31
#define V_TP_DMARBT_PAR_ERROR(x) ((x) << S_TP_DMARBT_PAR_ERROR)
#define F_TP_DMARBT_PAR_ERROR    V_TP_DMARBT_PAR_ERROR(1U)

#define S_LOGIC_FIFO_PAR_ERROR    30
#define V_LOGIC_FIFO_PAR_ERROR(x) ((x) << S_LOGIC_FIFO_PAR_ERROR)
#define F_LOGIC_FIFO_PAR_ERROR    V_LOGIC_FIFO_PAR_ERROR(1U)

#define S_ARB3_PAR_WRQUEUE_ERROR    29
#define V_ARB3_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB3_PAR_WRQUEUE_ERROR)
#define F_ARB3_PAR_WRQUEUE_ERROR    V_ARB3_PAR_WRQUEUE_ERROR(1U)

#define S_ARB2_PAR_WRQUEUE_ERROR    28
#define V_ARB2_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB2_PAR_WRQUEUE_ERROR)
#define F_ARB2_PAR_WRQUEUE_ERROR    V_ARB2_PAR_WRQUEUE_ERROR(1U)

#define S_ARB1_PAR_WRQUEUE_ERROR    27
#define V_ARB1_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB1_PAR_WRQUEUE_ERROR)
#define F_ARB1_PAR_WRQUEUE_ERROR    V_ARB1_PAR_WRQUEUE_ERROR(1U)

#define S_ARB0_PAR_WRQUEUE_ERROR    26
#define V_ARB0_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB0_PAR_WRQUEUE_ERROR)
#define F_ARB0_PAR_WRQUEUE_ERROR    V_ARB0_PAR_WRQUEUE_ERROR(1U)

#define S_ARB3_PAR_RDQUEUE_ERROR    25
#define V_ARB3_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB3_PAR_RDQUEUE_ERROR)
#define F_ARB3_PAR_RDQUEUE_ERROR    V_ARB3_PAR_RDQUEUE_ERROR(1U)

#define S_ARB2_PAR_RDQUEUE_ERROR    24
#define V_ARB2_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB2_PAR_RDQUEUE_ERROR)
#define F_ARB2_PAR_RDQUEUE_ERROR    V_ARB2_PAR_RDQUEUE_ERROR(1U)

#define S_ARB1_PAR_RDQUEUE_ERROR    23
#define V_ARB1_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB1_PAR_RDQUEUE_ERROR)
#define F_ARB1_PAR_RDQUEUE_ERROR    V_ARB1_PAR_RDQUEUE_ERROR(1U)

#define S_ARB0_PAR_RDQUEUE_ERROR    22
#define V_ARB0_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB0_PAR_RDQUEUE_ERROR)
#define F_ARB0_PAR_RDQUEUE_ERROR    V_ARB0_PAR_RDQUEUE_ERROR(1U)

#define S_CL10_PAR_WRQUEUE_ERROR    21
#define V_CL10_PAR_WRQUEUE_ERROR(x) ((x) << S_CL10_PAR_WRQUEUE_ERROR)
#define F_CL10_PAR_WRQUEUE_ERROR    V_CL10_PAR_WRQUEUE_ERROR(1U)

#define S_CL9_PAR_WRQUEUE_ERROR    20
#define V_CL9_PAR_WRQUEUE_ERROR(x) ((x) << S_CL9_PAR_WRQUEUE_ERROR)
#define F_CL9_PAR_WRQUEUE_ERROR    V_CL9_PAR_WRQUEUE_ERROR(1U)

#define S_CL8_PAR_WRQUEUE_ERROR    19
#define V_CL8_PAR_WRQUEUE_ERROR(x) ((x) << S_CL8_PAR_WRQUEUE_ERROR)
#define F_CL8_PAR_WRQUEUE_ERROR    V_CL8_PAR_WRQUEUE_ERROR(1U)

#define S_CL7_PAR_WRQUEUE_ERROR    18
#define V_CL7_PAR_WRQUEUE_ERROR(x) ((x) << S_CL7_PAR_WRQUEUE_ERROR)
#define F_CL7_PAR_WRQUEUE_ERROR    V_CL7_PAR_WRQUEUE_ERROR(1U)

#define S_CL6_PAR_WRQUEUE_ERROR    17
#define V_CL6_PAR_WRQUEUE_ERROR(x) ((x) << S_CL6_PAR_WRQUEUE_ERROR)
#define F_CL6_PAR_WRQUEUE_ERROR    V_CL6_PAR_WRQUEUE_ERROR(1U)

#define S_CL5_PAR_WRQUEUE_ERROR    16
#define V_CL5_PAR_WRQUEUE_ERROR(x) ((x) << S_CL5_PAR_WRQUEUE_ERROR)
#define F_CL5_PAR_WRQUEUE_ERROR    V_CL5_PAR_WRQUEUE_ERROR(1U)

#define S_CL4_PAR_WRQUEUE_ERROR    15
#define V_CL4_PAR_WRQUEUE_ERROR(x) ((x) << S_CL4_PAR_WRQUEUE_ERROR)
#define F_CL4_PAR_WRQUEUE_ERROR    V_CL4_PAR_WRQUEUE_ERROR(1U)

#define S_CL3_PAR_WRQUEUE_ERROR    14
#define V_CL3_PAR_WRQUEUE_ERROR(x) ((x) << S_CL3_PAR_WRQUEUE_ERROR)
#define F_CL3_PAR_WRQUEUE_ERROR    V_CL3_PAR_WRQUEUE_ERROR(1U)

#define S_CL2_PAR_WRQUEUE_ERROR    13
#define V_CL2_PAR_WRQUEUE_ERROR(x) ((x) << S_CL2_PAR_WRQUEUE_ERROR)
#define F_CL2_PAR_WRQUEUE_ERROR    V_CL2_PAR_WRQUEUE_ERROR(1U)

#define S_CL1_PAR_WRQUEUE_ERROR    12
#define V_CL1_PAR_WRQUEUE_ERROR(x) ((x) << S_CL1_PAR_WRQUEUE_ERROR)
#define F_CL1_PAR_WRQUEUE_ERROR    V_CL1_PAR_WRQUEUE_ERROR(1U)

#define S_CL0_PAR_WRQUEUE_ERROR    11
#define V_CL0_PAR_WRQUEUE_ERROR(x) ((x) << S_CL0_PAR_WRQUEUE_ERROR)
#define F_CL0_PAR_WRQUEUE_ERROR    V_CL0_PAR_WRQUEUE_ERROR(1U)

#define S_CL10_PAR_RDQUEUE_ERROR    10
#define V_CL10_PAR_RDQUEUE_ERROR(x) ((x) << S_CL10_PAR_RDQUEUE_ERROR)
#define F_CL10_PAR_RDQUEUE_ERROR    V_CL10_PAR_RDQUEUE_ERROR(1U)

#define S_CL9_PAR_RDQUEUE_ERROR    9
#define V_CL9_PAR_RDQUEUE_ERROR(x) ((x) << S_CL9_PAR_RDQUEUE_ERROR)
#define F_CL9_PAR_RDQUEUE_ERROR    V_CL9_PAR_RDQUEUE_ERROR(1U)

#define S_CL8_PAR_RDQUEUE_ERROR    8
#define V_CL8_PAR_RDQUEUE_ERROR(x) ((x) << S_CL8_PAR_RDQUEUE_ERROR)
#define F_CL8_PAR_RDQUEUE_ERROR    V_CL8_PAR_RDQUEUE_ERROR(1U)

#define S_CL7_PAR_RDQUEUE_ERROR    7
#define V_CL7_PAR_RDQUEUE_ERROR(x) ((x) << S_CL7_PAR_RDQUEUE_ERROR)
#define F_CL7_PAR_RDQUEUE_ERROR    V_CL7_PAR_RDQUEUE_ERROR(1U)

#define S_CL6_PAR_RDQUEUE_ERROR    6
#define V_CL6_PAR_RDQUEUE_ERROR(x) ((x) << S_CL6_PAR_RDQUEUE_ERROR)
#define F_CL6_PAR_RDQUEUE_ERROR    V_CL6_PAR_RDQUEUE_ERROR(1U)

#define S_CL5_PAR_RDQUEUE_ERROR    5
#define V_CL5_PAR_RDQUEUE_ERROR(x) ((x) << S_CL5_PAR_RDQUEUE_ERROR)
#define F_CL5_PAR_RDQUEUE_ERROR    V_CL5_PAR_RDQUEUE_ERROR(1U)

#define S_CL4_PAR_RDQUEUE_ERROR    4
#define V_CL4_PAR_RDQUEUE_ERROR(x) ((x) << S_CL4_PAR_RDQUEUE_ERROR)
#define F_CL4_PAR_RDQUEUE_ERROR    V_CL4_PAR_RDQUEUE_ERROR(1U)

#define S_CL3_PAR_RDQUEUE_ERROR    3
#define V_CL3_PAR_RDQUEUE_ERROR(x) ((x) << S_CL3_PAR_RDQUEUE_ERROR)
#define F_CL3_PAR_RDQUEUE_ERROR    V_CL3_PAR_RDQUEUE_ERROR(1U)

#define S_CL2_PAR_RDQUEUE_ERROR    2
#define V_CL2_PAR_RDQUEUE_ERROR(x) ((x) << S_CL2_PAR_RDQUEUE_ERROR)
#define F_CL2_PAR_RDQUEUE_ERROR    V_CL2_PAR_RDQUEUE_ERROR(1U)

#define S_CL1_PAR_RDQUEUE_ERROR    1
#define V_CL1_PAR_RDQUEUE_ERROR(x) ((x) << S_CL1_PAR_RDQUEUE_ERROR)
#define F_CL1_PAR_RDQUEUE_ERROR    V_CL1_PAR_RDQUEUE_ERROR(1U)

#define S_CL0_PAR_RDQUEUE_ERROR    0
#define V_CL0_PAR_RDQUEUE_ERROR(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR)
#define F_CL0_PAR_RDQUEUE_ERROR    V_CL0_PAR_RDQUEUE_ERROR(1U)

#define A_MA_PARITY_ERROR_STATUS1 0x77f4
#define A_MA_PARITY_ERROR_STATUS2 0x7804

#define S_ARB4_PAR_WRQUEUE_ERROR    1
#define V_ARB4_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR)
#define F_ARB4_PAR_WRQUEUE_ERROR    V_ARB4_PAR_WRQUEUE_ERROR(1U)

#define S_ARB4_PAR_RDQUEUE_ERROR    0
#define V_ARB4_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR)
#define F_ARB4_PAR_RDQUEUE_ERROR    V_ARB4_PAR_RDQUEUE_ERROR(1U)

#define A_MA_EXT_MEMORY1_BAR 0x7808

#define S_EXT_MEM1_BASE    16
#define M_EXT_MEM1_BASE    0xfffU
#define V_EXT_MEM1_BASE(x) ((x) << S_EXT_MEM1_BASE)
#define G_EXT_MEM1_BASE(x) (((x) >> S_EXT_MEM1_BASE) & M_EXT_MEM1_BASE)

#define S_EXT_MEM1_SIZE    0
#define M_EXT_MEM1_SIZE    0xfffU
#define V_EXT_MEM1_SIZE(x) ((x) << S_EXT_MEM1_SIZE)
#define G_EXT_MEM1_SIZE(x) (((x) >> S_EXT_MEM1_SIZE) & M_EXT_MEM1_SIZE)

#define A_MA_LOCAL_DEBUG_CFG 0x78f8

#define S_DEBUG_OR    15
#define V_DEBUG_OR(x) ((x) << S_DEBUG_OR)
#define F_DEBUG_OR    V_DEBUG_OR(1U)

#define S_DEBUG_HI    14
#define V_DEBUG_HI(x) ((x) << S_DEBUG_HI)
#define F_DEBUG_HI    V_DEBUG_HI(1U)

#define S_DEBUG_RPT    13
#define V_DEBUG_RPT(x) ((x) << S_DEBUG_RPT)
#define F_DEBUG_RPT    V_DEBUG_RPT(1U)

#define S_DEBUGPAGE    10
#define M_DEBUGPAGE    0x7U
#define V_DEBUGPAGE(x) ((x) << S_DEBUGPAGE)
#define G_DEBUGPAGE(x) (((x) >> S_DEBUGPAGE) & M_DEBUGPAGE)


/* registers for module EDC_0 */
#define EDC_0_BASE_ADDR 0x7900

#define A_EDC_BIST_CMD 0x7904
#define A_EDC_BIST_CMD_ADDR 0x7908
#define A_EDC_BIST_CMD_LEN 0x790c
#define A_EDC_BIST_DATA_PATTERN 0x7910
#define A_EDC_BIST_STATUS_RDATA 0x7928
#define A_EDC_INT_CAUSE 0x7978

#define S_ECC_UE_PAR    5
#define V_ECC_UE_PAR(x) ((x) << S_ECC_UE_PAR)
#define F_ECC_UE_PAR    V_ECC_UE_PAR(1U)

#define S_ECC_CE_PAR    4
#define V_ECC_CE_PAR(x) ((x) << S_ECC_CE_PAR)
#define F_ECC_CE_PAR    V_ECC_CE_PAR(1U)

#define S_PERR_PAR_CAUSE    3
#define V_PERR_PAR_CAUSE(x) ((x) << S_PERR_PAR_CAUSE)
#define F_PERR_PAR_CAUSE    V_PERR_PAR_CAUSE(1U)

#define A_EDC_ECC_STATUS 0x797c

/* registers for module EDC_1 */
#define EDC_1_BASE_ADDR 0x7980

/* registers for module HMA */
#define HMA_BASE_ADDR 0x7a00

/* registers for module CIM */
#define CIM_BASE_ADDR 0x7b00

#define A_CIM_VF_EXT_MAILBOX_CTRL 0x0

#define S_VFMBGENERIC    4
#define M_VFMBGENERIC    0xfU
#define V_VFMBGENERIC(x) ((x) << S_VFMBGENERIC)
#define G_VFMBGENERIC(x) (((x) >> S_VFMBGENERIC) & M_VFMBGENERIC)

#define A_CIM_VF_EXT_MAILBOX_STATUS 0x4

#define S_MBVFREADY    0
#define V_MBVFREADY(x) ((x) << S_MBVFREADY)
#define F_MBVFREADY    V_MBVFREADY(1U)

#define A_CIM_PF_MAILBOX_DATA 0x240
#define A_CIM_PF_MAILBOX_CTRL 0x280

#define S_MBGENERIC    4
#define M_MBGENERIC    0xfffffffU
#define V_MBGENERIC(x) ((x) << S_MBGENERIC)
#define G_MBGENERIC(x) (((x) >> S_MBGENERIC) & M_MBGENERIC)

#define S_MBMSGVALID    3
#define V_MBMSGVALID(x) ((x) << S_MBMSGVALID)
#define F_MBMSGVALID    V_MBMSGVALID(1U)

#define S_MBINTREQ    2
#define V_MBINTREQ(x) ((x) << S_MBINTREQ)
#define F_MBINTREQ    V_MBINTREQ(1U)

#define S_MBOWNER    0
#define M_MBOWNER    0x3U
#define V_MBOWNER(x) ((x) << S_MBOWNER)
#define G_MBOWNER(x) (((x) >> S_MBOWNER) & M_MBOWNER)

#define A_CIM_PF_HOST_INT_ENABLE 0x288

#define S_MBMSGRDYINTEN    19
#define V_MBMSGRDYINTEN(x) ((x) << S_MBMSGRDYINTEN)
#define F_MBMSGRDYINTEN    V_MBMSGRDYINTEN(1U)

#define A_CIM_PF_HOST_INT_CAUSE 0x28c

#define S_MBMSGRDYINT    19
#define V_MBMSGRDYINT(x) ((x) << S_MBMSGRDYINT)
#define F_MBMSGRDYINT    V_MBMSGRDYINT(1U)

#define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290
#define A_CIM_BOOT_CFG 0x7b00

#define S_BOOTADDR    8
#define M_BOOTADDR    0xffffffU
#define V_BOOTADDR(x) ((x) << S_BOOTADDR)
#define G_BOOTADDR(x) (((x) >> S_BOOTADDR) & M_BOOTADDR)

#define S_UPGEN    2
#define M_UPGEN    0x3fU
#define V_UPGEN(x) ((x) << S_UPGEN)
#define G_UPGEN(x) (((x) >> S_UPGEN) & M_UPGEN)

#define S_BOOTSDRAM    1
#define V_BOOTSDRAM(x) ((x) << S_BOOTSDRAM)
#define F_BOOTSDRAM    V_BOOTSDRAM(1U)

#define S_UPCRST    0
#define V_UPCRST(x) ((x) << S_UPCRST)
#define F_UPCRST    V_UPCRST(1U)

#define A_CIM_SDRAM_BASE_ADDR 0x7b14

#define S_SDRAMBASEADDR    6
#define M_SDRAMBASEADDR    0x3ffffffU
#define V_SDRAMBASEADDR(x) ((x) << S_SDRAMBASEADDR)
#define G_SDRAMBASEADDR(x) (((x) >> S_SDRAMBASEADDR) & M_SDRAMBASEADDR)

#define A_CIM_SDRAM_ADDR_SIZE 0x7b18

#define S_SDRAMADDRSIZE    4
#define M_SDRAMADDRSIZE    0xfffffffU
#define V_SDRAMADDRSIZE(x) ((x) << S_SDRAMADDRSIZE)
#define G_SDRAMADDRSIZE(x) (((x) >> S_SDRAMADDRSIZE) & M_SDRAMADDRSIZE)

#define A_CIM_EXTMEM2_BASE_ADDR 0x7b1c

#define S_EXTMEM2BASEADDR    6
#define M_EXTMEM2BASEADDR    0x3ffffffU
#define V_EXTMEM2BASEADDR(x) ((x) << S_EXTMEM2BASEADDR)
#define G_EXTMEM2BASEADDR(x) (((x) >> S_EXTMEM2BASEADDR) & M_EXTMEM2BASEADDR)

#define A_CIM_EXTMEM2_ADDR_SIZE 0x7b20

#define S_EXTMEM2ADDRSIZE    4
#define M_EXTMEM2ADDRSIZE    0xfffffffU
#define V_EXTMEM2ADDRSIZE(x) ((x) << S_EXTMEM2ADDRSIZE)
#define G_EXTMEM2ADDRSIZE(x) (((x) >> S_EXTMEM2ADDRSIZE) & M_EXTMEM2ADDRSIZE)

#define A_CIM_HOST_INT_CAUSE 0x7b2c

#define S_TIEQOUTPARERRINT    20
#define V_TIEQOUTPARERRINT(x) ((x) << S_TIEQOUTPARERRINT)
#define F_TIEQOUTPARERRINT    V_TIEQOUTPARERRINT(1U)

#define S_TIEQINPARERRINT    19
#define V_TIEQINPARERRINT(x) ((x) << S_TIEQINPARERRINT)
#define F_TIEQINPARERRINT    V_TIEQINPARERRINT(1U)

#define S_MBHOSTPARERR    18
#define V_MBHOSTPARERR(x) ((x) << S_MBHOSTPARERR)
#define F_MBHOSTPARERR    V_MBHOSTPARERR(1U)

#define S_MBUPPARERR    17
#define V_MBUPPARERR(x) ((x) << S_MBUPPARERR)
#define F_MBUPPARERR    V_MBUPPARERR(1U)

#define S_IBQTP0PARERR    16
#define V_IBQTP0PARERR(x) ((x) << S_IBQTP0PARERR)
#define F_IBQTP0PARERR    V_IBQTP0PARERR(1U)

#define S_IBQTP1PARERR    15
#define V_IBQTP1PARERR(x) ((x) << S_IBQTP1PARERR)
#define F_IBQTP1PARERR    V_IBQTP1PARERR(1U)

#define S_IBQULPPARERR    14
#define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR)
#define F_IBQULPPARERR    V_IBQULPPARERR(1U)

#define S_IBQSGELOPARERR    13
#define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR)
#define F_IBQSGELOPARERR    V_IBQSGELOPARERR(1U)

#define S_IBQSGEHIPARERR    12
#define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR)
#define F_IBQSGEHIPARERR    V_IBQSGEHIPARERR(1U)

#define S_IBQNCSIPARERR    11
#define V_IBQNCSIPARERR(x) ((x) << S_IBQNCSIPARERR)
#define F_IBQNCSIPARERR    V_IBQNCSIPARERR(1U)

#define S_OBQULP0PARERR    10
#define V_OBQULP0PARERR(x) ((x) << S_OBQULP0PARERR)
#define F_OBQULP0PARERR    V_OBQULP0PARERR(1U)

#define S_OBQULP1PARERR    9
#define V_OBQULP1PARERR(x) ((x) << S_OBQULP1PARERR)
#define F_OBQULP1PARERR    V_OBQULP1PARERR(1U)

#define S_OBQULP2PARERR    8
#define V_OBQULP2PARERR(x) ((x) << S_OBQULP2PARERR)
#define F_OBQULP2PARERR    V_OBQULP2PARERR(1U)

#define S_OBQULP3PARERR    7
#define V_OBQULP3PARERR(x) ((x) << S_OBQULP3PARERR)
#define F_OBQULP3PARERR    V_OBQULP3PARERR(1U)

#define S_OBQSGEPARERR    6
#define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR)
#define F_OBQSGEPARERR    V_OBQSGEPARERR(1U)

#define S_OBQNCSIPARERR    5
#define V_OBQNCSIPARERR(x) ((x) << S_OBQNCSIPARERR)
#define F_OBQNCSIPARERR    V_OBQNCSIPARERR(1U)

#define S_TIMER1INT    3
#define V_TIMER1INT(x) ((x) << S_TIMER1INT)
#define F_TIMER1INT    V_TIMER1INT(1U)

#define S_TIMER0INT    2
#define V_TIMER0INT(x) ((x) << S_TIMER0INT)
#define F_TIMER0INT    V_TIMER0INT(1U)

#define S_PREFDROPINT    1
#define V_PREFDROPINT(x) ((x) << S_PREFDROPINT)
#define F_PREFDROPINT    V_PREFDROPINT(1U)

#define S_UPACCNONZERO    0
#define V_UPACCNONZERO(x) ((x) << S_UPACCNONZERO)
#define F_UPACCNONZERO    V_UPACCNONZERO(1U)

#define S_MA_CIM_INTFPERR    28
#define V_MA_CIM_INTFPERR(x) ((x) << S_MA_CIM_INTFPERR)
#define F_MA_CIM_INTFPERR    V_MA_CIM_INTFPERR(1U)

#define S_PLCIM_MSTRSPDATAPARERR    27
#define V_PLCIM_MSTRSPDATAPARERR(x) ((x) << S_PLCIM_MSTRSPDATAPARERR)
#define F_PLCIM_MSTRSPDATAPARERR    V_PLCIM_MSTRSPDATAPARERR(1U)

#define S_NCSI2CIMINTFPARERR    26
#define V_NCSI2CIMINTFPARERR(x) ((x) << S_NCSI2CIMINTFPARERR)
#define F_NCSI2CIMINTFPARERR    V_NCSI2CIMINTFPARERR(1U)

#define S_SGE2CIMINTFPARERR    25
#define V_SGE2CIMINTFPARERR(x) ((x) << S_SGE2CIMINTFPARERR)
#define F_SGE2CIMINTFPARERR    V_SGE2CIMINTFPARERR(1U)

#define S_ULP2CIMINTFPARERR    24
#define V_ULP2CIMINTFPARERR(x) ((x) << S_ULP2CIMINTFPARERR)
#define F_ULP2CIMINTFPARERR    V_ULP2CIMINTFPARERR(1U)

#define S_TP2CIMINTFPARERR    23
#define V_TP2CIMINTFPARERR(x) ((x) << S_TP2CIMINTFPARERR)
#define F_TP2CIMINTFPARERR    V_TP2CIMINTFPARERR(1U)

#define S_OBQSGERX1PARERR    22
#define V_OBQSGERX1PARERR(x) ((x) << S_OBQSGERX1PARERR)
#define F_OBQSGERX1PARERR    V_OBQSGERX1PARERR(1U)

#define S_OBQSGERX0PARERR    21
#define V_OBQSGERX0PARERR(x) ((x) << S_OBQSGERX0PARERR)
#define F_OBQSGERX0PARERR    V_OBQSGERX0PARERR(1U)

#define S_PCIE2CIMINTFPARERR    29
#define V_PCIE2CIMINTFPARERR(x) ((x) << S_PCIE2CIMINTFPARERR)
#define F_PCIE2CIMINTFPARERR    V_PCIE2CIMINTFPARERR(1U)

#define S_IBQPCIEPARERR    12
#define V_IBQPCIEPARERR(x) ((x) << S_IBQPCIEPARERR)
#define F_IBQPCIEPARERR    V_IBQPCIEPARERR(1U)

#define A_CIM_HOST_UPACC_INT_CAUSE 0x7b34

#define S_EEPROMWRINT    30
#define V_EEPROMWRINT(x) ((x) << S_EEPROMWRINT)
#define F_EEPROMWRINT    V_EEPROMWRINT(1U)

#define S_TIMEOUTMAINT    29
#define V_TIMEOUTMAINT(x) ((x) << S_TIMEOUTMAINT)
#define F_TIMEOUTMAINT    V_TIMEOUTMAINT(1U)

#define S_TIMEOUTINT    28
#define V_TIMEOUTINT(x) ((x) << S_TIMEOUTINT)
#define F_TIMEOUTINT    V_TIMEOUTINT(1U)

#define S_RSPOVRLOOKUPINT    27
#define V_RSPOVRLOOKUPINT(x) ((x) << S_RSPOVRLOOKUPINT)
#define F_RSPOVRLOOKUPINT    V_RSPOVRLOOKUPINT(1U)

#define S_REQOVRLOOKUPINT    26
#define V_REQOVRLOOKUPINT(x) ((x) << S_REQOVRLOOKUPINT)
#define F_REQOVRLOOKUPINT    V_REQOVRLOOKUPINT(1U)

#define S_BLKWRPLINT    25
#define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT)
#define F_BLKWRPLINT    V_BLKWRPLINT(1U)

#define S_BLKRDPLINT    24
#define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT)
#define F_BLKRDPLINT    V_BLKRDPLINT(1U)

#define S_SGLWRPLINT    23
#define V_SGLWRPLINT(x) ((x) << S_SGLWRPLINT)
#define F_SGLWRPLINT    V_SGLWRPLINT(1U)

#define S_SGLRDPLINT    22
#define V_SGLRDPLINT(x) ((x) << S_SGLRDPLINT)
#define F_SGLRDPLINT    V_SGLRDPLINT(1U)

#define S_BLKWRCTLINT    21
#define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT)
#define F_BLKWRCTLINT    V_BLKWRCTLINT(1U)

#define S_BLKRDCTLINT    20
#define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT)
#define F_BLKRDCTLINT    V_BLKRDCTLINT(1U)

#define S_SGLWRCTLINT    19
#define V_SGLWRCTLINT(x) ((x) << S_SGLWRCTLINT)
#define F_SGLWRCTLINT    V_SGLWRCTLINT(1U)

#define S_SGLRDCTLINT    18
#define V_SGLRDCTLINT(x) ((x) << S_SGLRDCTLINT)
#define F_SGLRDCTLINT    V_SGLRDCTLINT(1U)

#define S_BLKWREEPROMINT    17
#define V_BLKWREEPROMINT(x) ((x) << S_BLKWREEPROMINT)
#define F_BLKWREEPROMINT    V_BLKWREEPROMINT(1U)

#define S_BLKRDEEPROMINT    16
#define V_BLKRDEEPROMINT(x) ((x) << S_BLKRDEEPROMINT)
#define F_BLKRDEEPROMINT    V_BLKRDEEPROMINT(1U)

#define S_SGLWREEPROMINT    15
#define V_SGLWREEPROMINT(x) ((x) << S_SGLWREEPROMINT)
#define F_SGLWREEPROMINT    V_SGLWREEPROMINT(1U)

#define S_SGLRDEEPROMINT    14
#define V_SGLRDEEPROMINT(x) ((x) << S_SGLRDEEPROMINT)
#define F_SGLRDEEPROMINT    V_SGLRDEEPROMINT(1U)

#define S_BLKWRFLASHINT    13
#define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT)
#define F_BLKWRFLASHINT    V_BLKWRFLASHINT(1U)

#define S_BLKRDFLASHINT    12
#define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT)
#define F_BLKRDFLASHINT    V_BLKRDFLASHINT(1U)

#define S_SGLWRFLASHINT    11
#define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT)
#define F_SGLWRFLASHINT    V_SGLWRFLASHINT(1U)

#define S_SGLRDFLASHINT    10
#define V_SGLRDFLASHINT(x) ((x) << S_SGLRDFLASHINT)
#define F_SGLRDFLASHINT    V_SGLRDFLASHINT(1U)

#define S_BLKWRBOOTINT    9
#define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT)
#define F_BLKWRBOOTINT    V_BLKWRBOOTINT(1U)

#define S_BLKRDBOOTINT    8
#define V_BLKRDBOOTINT(x) ((x) << S_BLKRDBOOTINT)
#define F_BLKRDBOOTINT    V_BLKRDBOOTINT(1U)

#define S_SGLWRBOOTINT    7
#define V_SGLWRBOOTINT(x) ((x) << S_SGLWRBOOTINT)
#define F_SGLWRBOOTINT    V_SGLWRBOOTINT(1U)

#define S_SGLRDBOOTINT    6
#define V_SGLRDBOOTINT(x) ((x) << S_SGLRDBOOTINT)
#define F_SGLRDBOOTINT    V_SGLRDBOOTINT(1U)

#define S_ILLWRBEINT    5
#define V_ILLWRBEINT(x) ((x) << S_ILLWRBEINT)
#define F_ILLWRBEINT    V_ILLWRBEINT(1U)

#define S_ILLRDBEINT    4
#define V_ILLRDBEINT(x) ((x) << S_ILLRDBEINT)
#define F_ILLRDBEINT    V_ILLRDBEINT(1U)

#define S_ILLRDINT    3
#define V_ILLRDINT(x) ((x) << S_ILLRDINT)
#define F_ILLRDINT    V_ILLRDINT(1U)

#define S_ILLWRINT    2
#define V_ILLWRINT(x) ((x) << S_ILLWRINT)
#define F_ILLWRINT    V_ILLWRINT(1U)

#define S_ILLTRANSINT    1
#define V_ILLTRANSINT(x) ((x) << S_ILLTRANSINT)
#define F_ILLTRANSINT    V_ILLTRANSINT(1U)

#define S_RSVDSPACEINT    0
#define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
#define F_RSVDSPACEINT    V_RSVDSPACEINT(1U)

#define A_CIM_QUEUE_CONFIG_REF 0x7b48

#define S_OBQSELECT    4
#define V_OBQSELECT(x) ((x) << S_OBQSELECT)
#define F_OBQSELECT    V_OBQSELECT(1U)

#define S_IBQSELECT    3
#define V_IBQSELECT(x) ((x) << S_IBQSELECT)
#define F_IBQSELECT    V_IBQSELECT(1U)

#define S_QUENUMSELECT    0
#define M_QUENUMSELECT    0x7U
#define V_QUENUMSELECT(x) ((x) << S_QUENUMSELECT)
#define G_QUENUMSELECT(x) (((x) >> S_QUENUMSELECT) & M_QUENUMSELECT)

#define A_CIM_QUEUE_CONFIG_CTRL 0x7b4c

#define S_CIMQSIZE    24
#define M_CIMQSIZE    0x3fU
#define V_CIMQSIZE(x) ((x) << S_CIMQSIZE)
#define G_CIMQSIZE(x) (((x) >> S_CIMQSIZE) & M_CIMQSIZE)

#define S_CIMQBASE    16
#define M_CIMQBASE    0x3fU
#define V_CIMQBASE(x) ((x) << S_CIMQBASE)
#define G_CIMQBASE(x) (((x) >> S_CIMQBASE) & M_CIMQBASE)

#define S_CIMQDBG8BEN    9
#define V_CIMQDBG8BEN(x) ((x) << S_CIMQDBG8BEN)
#define F_CIMQDBG8BEN    V_CIMQDBG8BEN(1U)

#define S_QUEFULLTHRSH    0
#define M_QUEFULLTHRSH    0x1ffU
#define V_QUEFULLTHRSH(x) ((x) << S_QUEFULLTHRSH)
#define G_QUEFULLTHRSH(x) (((x) >> S_QUEFULLTHRSH) & M_QUEFULLTHRSH)

#define S_CIMQ1KEN    30
#define V_CIMQ1KEN(x) ((x) << S_CIMQ1KEN)
#define F_CIMQ1KEN    V_CIMQ1KEN(1U)

#define A_CIM_HOST_ACC_CTRL 0x7b50

#define S_HOSTBUSY    17
#define V_HOSTBUSY(x) ((x) << S_HOSTBUSY)
#define F_HOSTBUSY    V_HOSTBUSY(1U)

#define S_HOSTWRITE    16
#define V_HOSTWRITE(x) ((x) << S_HOSTWRITE)
#define F_HOSTWRITE    V_HOSTWRITE(1U)

#define S_HOSTADDR    0
#define M_HOSTADDR    0xffffU
#define V_HOSTADDR(x) ((x) << S_HOSTADDR)
#define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR)

#define A_CIM_HOST_ACC_DATA 0x7b54
#define A_CIM_IBQ_DBG_CFG 0x7b60

#define S_IBQDBGADDR    16
#define M_IBQDBGADDR    0xfffU
#define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR)
#define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR)

#define S_IBQDBGWR    2
#define V_IBQDBGWR(x) ((x) << S_IBQDBGWR)
#define F_IBQDBGWR    V_IBQDBGWR(1U)

#define S_IBQDBGBUSY    1
#define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY)
#define F_IBQDBGBUSY    V_IBQDBGBUSY(1U)

#define S_IBQDBGEN    0
#define V_IBQDBGEN(x) ((x) << S_IBQDBGEN)
#define F_IBQDBGEN    V_IBQDBGEN(1U)

#define A_CIM_OBQ_DBG_CFG 0x7b64

#define S_OBQDBGADDR    16
#define M_OBQDBGADDR    0xfffU
#define V_OBQDBGADDR(x) ((x) << S_OBQDBGADDR)
#define G_OBQDBGADDR(x) (((x) >> S_OBQDBGADDR) & M_OBQDBGADDR)

#define S_OBQDBGWR    2
#define V_OBQDBGWR(x) ((x) << S_OBQDBGWR)
#define F_OBQDBGWR    V_OBQDBGWR(1U)

#define S_OBQDBGBUSY    1
#define V_OBQDBGBUSY(x) ((x) << S_OBQDBGBUSY)
#define F_OBQDBGBUSY    V_OBQDBGBUSY(1U)

#define S_OBQDBGEN    0
#define V_OBQDBGEN(x) ((x) << S_OBQDBGEN)
#define F_OBQDBGEN    V_OBQDBGEN(1U)

#define A_CIM_IBQ_DBG_DATA 0x7b68
#define A_CIM_OBQ_DBG_DATA 0x7b6c
#define A_CIM_DEBUGCFG 0x7b70

#define S_POLADBGRDPTR    23
#define M_POLADBGRDPTR    0x1ffU
#define V_POLADBGRDPTR(x) ((x) << S_POLADBGRDPTR)
#define G_POLADBGRDPTR(x) (((x) >> S_POLADBGRDPTR) & M_POLADBGRDPTR)

#define S_PILADBGRDPTR    14
#define M_PILADBGRDPTR    0x1ffU
#define V_PILADBGRDPTR(x) ((x) << S_PILADBGRDPTR)
#define G_PILADBGRDPTR(x) (((x) >> S_PILADBGRDPTR) & M_PILADBGRDPTR)

#define S_LAMASKTRIG    13
#define V_LAMASKTRIG(x) ((x) << S_LAMASKTRIG)
#define F_LAMASKTRIG    V_LAMASKTRIG(1U)

#define S_LADBGEN    12
#define V_LADBGEN(x) ((x) << S_LADBGEN)
#define F_LADBGEN    V_LADBGEN(1U)

#define S_LAFILLONCE    11
#define V_LAFILLONCE(x) ((x) << S_LAFILLONCE)
#define F_LAFILLONCE    V_LAFILLONCE(1U)

#define S_LAMASKSTOP    10
#define V_LAMASKSTOP(x) ((x) << S_LAMASKSTOP)
#define F_LAMASKSTOP    V_LAMASKSTOP(1U)

#define S_DEBUGSELH    5
#define M_DEBUGSELH    0x1fU
#define V_DEBUGSELH(x) ((x) << S_DEBUGSELH)
#define G_DEBUGSELH(x) (((x) >> S_DEBUGSELH) & M_DEBUGSELH)

#define S_DEBUGSELL    0
#define M_DEBUGSELL    0x1fU
#define V_DEBUGSELL(x) ((x) << S_DEBUGSELL)
#define G_DEBUGSELL(x) (((x) >> S_DEBUGSELL) & M_DEBUGSELL)

#define A_CIM_DEBUGSTS 0x7b74

#define S_LARESET    31
#define V_LARESET(x) ((x) << S_LARESET)
#define F_LARESET    V_LARESET(1U)

#define S_POLADBGWRPTR    16
#define M_POLADBGWRPTR    0x1ffU
#define V_POLADBGWRPTR(x) ((x) << S_POLADBGWRPTR)
#define G_POLADBGWRPTR(x) (((x) >> S_POLADBGWRPTR) & M_POLADBGWRPTR)

#define S_PILADBGWRPTR    0
#define M_PILADBGWRPTR    0x1ffU
#define V_PILADBGWRPTR(x) ((x) << S_PILADBGWRPTR)
#define G_PILADBGWRPTR(x) (((x) >> S_PILADBGWRPTR) & M_PILADBGWRPTR)

#define A_CIM_PO_LA_DEBUGDATA 0x7b78
#define A_CIM_PI_LA_DEBUGDATA 0x7b7c
#define A_CIM_PO_LA_MADEBUGDATA 0x7b80
#define A_CIM_PI_LA_MADEBUGDATA 0x7b84
#define A_CIM_DEBUG_ADDR_ILLEGAL 0x7c0c

#define S_DADDRILLEGAL    2
#define M_DADDRILLEGAL    0x3fffffffU
#define V_DADDRILLEGAL(x) ((x) << S_DADDRILLEGAL)
#define G_DADDRILLEGAL(x) (((x) >> S_DADDRILLEGAL) & M_DADDRILLEGAL)

#define S_DADDRILLEGALTYPE    0
#define M_DADDRILLEGALTYPE    0x3U
#define V_DADDRILLEGALTYPE(x) ((x) << S_DADDRILLEGALTYPE)
#define G_DADDRILLEGALTYPE(x) (((x) >> S_DADDRILLEGALTYPE) & M_DADDRILLEGALTYPE)

#define A_CIM_UP_OPERATION_FREQ 0x7c38

/* registers for module TP */
#define TP_BASE_ADDR 0x7d00

#define A_TP_IN_CONFIG 0x7d00

#define S_NICMODE    14
#define V_NICMODE(x) ((x) << S_NICMODE)
#define F_NICMODE    V_NICMODE(1U)

#define S_ECHECKSUMCHECKTCP    13
#define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP)
#define F_ECHECKSUMCHECKTCP    V_ECHECKSUMCHECKTCP(1U)

#define S_ECHECKSUMCHECKIP    12
#define V_ECHECKSUMCHECKIP(x) ((x) << S_ECHECKSUMCHECKIP)
#define F_ECHECKSUMCHECKIP    V_ECHECKSUMCHECKIP(1U)

#define A_TP_OUT_CONFIG 0x7d04

#define S_IPIDSPLITMODE    16
#define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE)
#define F_IPIDSPLITMODE    V_IPIDSPLITMODE(1U)

#define S_VLANEXTENABLEPORT3    15
#define V_VLANEXTENABLEPORT3(x) ((x) << S_VLANEXTENABLEPORT3)
#define F_VLANEXTENABLEPORT3    V_VLANEXTENABLEPORT3(1U)

#define S_VLANEXTENABLEPORT2    14
#define V_VLANEXTENABLEPORT2(x) ((x) << S_VLANEXTENABLEPORT2)
#define F_VLANEXTENABLEPORT2    V_VLANEXTENABLEPORT2(1U)

#define S_VLANEXTENABLEPORT1    13
#define V_VLANEXTENABLEPORT1(x) ((x) << S_VLANEXTENABLEPORT1)
#define F_VLANEXTENABLEPORT1    V_VLANEXTENABLEPORT1(1U)

#define S_VLANEXTENABLEPORT0    12
#define V_VLANEXTENABLEPORT0(x) ((x) << S_VLANEXTENABLEPORT0)
#define F_VLANEXTENABLEPORT0    V_VLANEXTENABLEPORT0(1U)

#define S_CRXPKTENC    3
#define V_CRXPKTENC(x) ((x) << S_CRXPKTENC)
#define F_CRXPKTENC    V_CRXPKTENC(1U)

#define S_CRXPKTXT    1
#define V_CRXPKTXT(x) ((x) << S_CRXPKTXT)
#define F_CRXPKTXT    V_CRXPKTXT(1U)

#define A_TP_GLOBAL_CONFIG 0x7d08

#define S_SYNCOOKIEPARAMS    26
#define M_SYNCOOKIEPARAMS    0x3fU
#define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS)
#define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS)

#define S_RXFLOWCONTROLDISABLE    25
#define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE)
#define F_RXFLOWCONTROLDISABLE    V_RXFLOWCONTROLDISABLE(1U)

#define S_TXPACINGENABLE    24
#define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE)
#define F_TXPACINGENABLE    V_TXPACINGENABLE(1U)

#define S_ATTACKFILTERENABLE    23
#define V_ATTACKFILTERENABLE(x) ((x) << S_ATTACKFILTERENABLE)
#define F_ATTACKFILTERENABLE    V_ATTACKFILTERENABLE(1U)

#define S_SYNCOOKIENOOPTIONS    22
#define V_SYNCOOKIENOOPTIONS(x) ((x) << S_SYNCOOKIENOOPTIONS)
#define F_SYNCOOKIENOOPTIONS    V_SYNCOOKIENOOPTIONS(1U)

#define S_PROTECTEDMODE    21
#define V_PROTECTEDMODE(x) ((x) << S_PROTECTEDMODE)
#define F_PROTECTEDMODE    V_PROTECTEDMODE(1U)

#define S_PINGDROP    20
#define V_PINGDROP(x) ((x) << S_PINGDROP)
#define F_PINGDROP    V_PINGDROP(1U)

#define S_FRAGMENTDROP    19
#define V_FRAGMENTDROP(x) ((x) << S_FRAGMENTDROP)
#define F_FRAGMENTDROP    V_FRAGMENTDROP(1U)

#define S_FIVETUPLELOOKUP    17
#define M_FIVETUPLELOOKUP    0x3U
#define V_FIVETUPLELOOKUP(x) ((x) << S_FIVETUPLELOOKUP)
#define G_FIVETUPLELOOKUP(x) (((x) >> S_FIVETUPLELOOKUP) & M_FIVETUPLELOOKUP)

#define S_OFDMPSSTATS    16
#define V_OFDMPSSTATS(x) ((x) << S_OFDMPSSTATS)
#define F_OFDMPSSTATS    V_OFDMPSSTATS(1U)

#define S_DONTFRAGMENT    15
#define V_DONTFRAGMENT(x) ((x) << S_DONTFRAGMENT)
#define F_DONTFRAGMENT    V_DONTFRAGMENT(1U)

#define S_IPIDENTSPLIT    14
#define V_IPIDENTSPLIT(x) ((x) << S_IPIDENTSPLIT)
#define F_IPIDENTSPLIT    V_IPIDENTSPLIT(1U)

#define S_IPCHECKSUMOFFLOAD    13
#define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD)
#define F_IPCHECKSUMOFFLOAD    V_IPCHECKSUMOFFLOAD(1U)

#define S_UDPCHECKSUMOFFLOAD    12
#define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD)
#define F_UDPCHECKSUMOFFLOAD    V_UDPCHECKSUMOFFLOAD(1U)

#define S_TCPCHECKSUMOFFLOAD    11
#define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD)
#define F_TCPCHECKSUMOFFLOAD    V_TCPCHECKSUMOFFLOAD(1U)

#define S_RSSLOOPBACKENABLE    10
#define V_RSSLOOPBACKENABLE(x) ((x) << S_RSSLOOPBACKENABLE)
#define F_RSSLOOPBACKENABLE    V_RSSLOOPBACKENABLE(1U)

#define S_TCAMSERVERUSE    8
#define M_TCAMSERVERUSE    0x3U
#define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE)
#define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE)

#define S_IPTTL    0
#define M_IPTTL    0xffU
#define V_IPTTL(x) ((x) << S_IPTTL)
#define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL)

#define S_RSSSYNSTEERENABLE    12
#define V_RSSSYNSTEERENABLE(x) ((x) << S_RSSSYNSTEERENABLE)
#define F_RSSSYNSTEERENABLE    V_RSSSYNSTEERENABLE(1U)

#define S_ISSFROMCPLENABLE    11
#define V_ISSFROMCPLENABLE(x) ((x) << S_ISSFROMCPLENABLE)
#define F_ISSFROMCPLENABLE    V_ISSFROMCPLENABLE(1U)

#define S_ACTIVEFILTERCOUNTS    22
#define V_ACTIVEFILTERCOUNTS(x) ((x) << S_ACTIVEFILTERCOUNTS)
#define F_ACTIVEFILTERCOUNTS    V_ACTIVEFILTERCOUNTS(1U)

#define A_TP_CMM_TCB_BASE 0x7d10
#define A_TP_CMM_MM_BASE 0x7d14
#define A_TP_CMM_TIMER_BASE 0x7d18
#define A_TP_PMM_TX_BASE 0x7d20
#define A_TP_PMM_RX_BASE 0x7d28
#define A_TP_PMM_RX_PAGE_SIZE 0x7d2c
#define A_TP_PMM_RX_MAX_PAGE 0x7d30

#define S_PMRXNUMCHN    31
#define V_PMRXNUMCHN(x) ((x) << S_PMRXNUMCHN)
#define F_PMRXNUMCHN    V_PMRXNUMCHN(1U)

#define S_PMRXMAXPAGE    0
#define M_PMRXMAXPAGE    0x1fffffU
#define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE)
#define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE)

#define A_TP_PMM_TX_PAGE_SIZE 0x7d34
#define A_TP_PMM_TX_MAX_PAGE 0x7d38

#define S_PMTXNUMCHN    30
#define M_PMTXNUMCHN    0x3U
#define V_PMTXNUMCHN(x) ((x) << S_PMTXNUMCHN)
#define G_PMTXNUMCHN(x) (((x) >> S_PMTXNUMCHN) & M_PMTXNUMCHN)

#define S_PMTXMAXPAGE    0
#define M_PMTXMAXPAGE    0x1fffffU
#define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE)
#define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE)

#define A_TP_DACK_CONFIG 0x7d44

#define S_AUTOSTATE3    30
#define M_AUTOSTATE3    0x3U
#define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3)
#define G_AUTOSTATE3(x) (((x) >> S_AUTOSTATE3) & M_AUTOSTATE3)

#define S_AUTOSTATE2    28
#define M_AUTOSTATE2    0x3U
#define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2)
#define G_AUTOSTATE2(x) (((x) >> S_AUTOSTATE2) & M_AUTOSTATE2)

#define S_AUTOSTATE1    26
#define M_AUTOSTATE1    0x3U
#define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1)
#define G_AUTOSTATE1(x) (((x) >> S_AUTOSTATE1) & M_AUTOSTATE1)

#define S_BYTETHRESHOLD    8
#define M_BYTETHRESHOLD    0x3ffffU
#define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD)
#define G_BYTETHRESHOLD(x) (((x) >> S_BYTETHRESHOLD) & M_BYTETHRESHOLD)

#define S_MSSTHRESHOLD    4
#define M_MSSTHRESHOLD    0x7U
#define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD)
#define G_MSSTHRESHOLD(x) (((x) >> S_MSSTHRESHOLD) & M_MSSTHRESHOLD)

#define S_AUTOENABLE    1
#define V_AUTOENABLE(x) ((x) << S_AUTOENABLE)
#define F_AUTOENABLE    V_AUTOENABLE(1U)

#define S_MODE    0
#define V_MODE(x) ((x) << S_MODE)
#define F_MODE    V_MODE(1U)

#define A_TP_PARA_REG0 0x7d60

#define S_DUPACKTHRESH    20
#define M_DUPACKTHRESH    0xfU
#define V_DUPACKTHRESH(x) ((x) << S_DUPACKTHRESH)
#define G_DUPACKTHRESH(x) (((x) >> S_DUPACKTHRESH) & M_DUPACKTHRESH)

#define A_TP_PARA_REG2 0x7d68

#define S_MAXRXDATA    16
#define M_MAXRXDATA    0xffffU
#define V_MAXRXDATA(x) ((x) << S_MAXRXDATA)
#define G_MAXRXDATA(x) (((x) >> S_MAXRXDATA) & M_MAXRXDATA)

#define S_RXCOALESCESIZE    0
#define M_RXCOALESCESIZE    0xffffU
#define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE)
#define G_RXCOALESCESIZE(x) (((x) >> S_RXCOALESCESIZE) & M_RXCOALESCESIZE)

#define A_TP_PARA_REG3 0x7d6c

#define S_TUNNELCNGDROP3    23
#define V_TUNNELCNGDROP3(x) ((x) << S_TUNNELCNGDROP3)
#define F_TUNNELCNGDROP3    V_TUNNELCNGDROP3(1U)

#define S_TUNNELCNGDROP2    22
#define V_TUNNELCNGDROP2(x) ((x) << S_TUNNELCNGDROP2)
#define F_TUNNELCNGDROP2    V_TUNNELCNGDROP2(1U)

#define S_TUNNELCNGDROP1    21
#define V_TUNNELCNGDROP1(x) ((x) << S_TUNNELCNGDROP1)
#define F_TUNNELCNGDROP1    V_TUNNELCNGDROP1(1U)

#define S_TUNNELCNGDROP0    20
#define V_TUNNELCNGDROP0(x) ((x) << S_TUNNELCNGDROP0)
#define F_TUNNELCNGDROP0    V_TUNNELCNGDROP0(1U)

#define S_RXURGTUNNEL    6
#define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL)
#define F_RXURGTUNNEL    V_RXURGTUNNEL(1U)

#define A_TP_PARA_REG5 0x7d74

#define S_INDICATESIZE    16
#define M_INDICATESIZE    0xffffU
#define V_INDICATESIZE(x) ((x) << S_INDICATESIZE)
#define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE)

#define S_REARMDDPOFFSET    4
#define V_REARMDDPOFFSET(x) ((x) << S_REARMDDPOFFSET)
#define F_REARMDDPOFFSET    V_REARMDDPOFFSET(1U)

#define S_RESETDDPOFFSET    3
#define V_RESETDDPOFFSET(x) ((x) << S_RESETDDPOFFSET)
#define F_RESETDDPOFFSET    V_RESETDDPOFFSET(1U)

#define A_TP_TIMER_RESOLUTION 0x7d90

#define S_TIMERRESOLUTION    16
#define M_TIMERRESOLUTION    0xffU
#define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
#define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION)

#define S_TIMESTAMPRESOLUTION    8
#define M_TIMESTAMPRESOLUTION    0xffU
#define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION)
#define G_TIMESTAMPRESOLUTION(x) (((x) >> S_TIMESTAMPRESOLUTION) & M_TIMESTAMPRESOLUTION)

#define S_DELAYEDACKRESOLUTION    0
#define M_DELAYEDACKRESOLUTION    0xffU
#define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
#define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION)

#define A_TP_MSL 0x7d94

#define S_MSL    0
#define M_MSL    0x3fffffffU
#define V_MSL(x) ((x) << S_MSL)
#define G_MSL(x) (((x) >> S_MSL) & M_MSL)

#define A_TP_RXT_MIN 0x7d98

#define S_RXTMIN    0
#define M_RXTMIN    0x3fffffffU
#define V_RXTMIN(x) ((x) << S_RXTMIN)
#define G_RXTMIN(x) (((x) >> S_RXTMIN) & M_RXTMIN)

#define A_TP_RXT_MAX 0x7d9c

#define S_RXTMAX    0
#define M_RXTMAX    0x3fffffffU
#define V_RXTMAX(x) ((x) << S_RXTMAX)
#define G_RXTMAX(x) (((x) >> S_RXTMAX) & M_RXTMAX)

#define A_TP_PERS_MIN 0x7da0

#define S_PERSMIN    0
#define M_PERSMIN    0x3fffffffU
#define V_PERSMIN(x) ((x) << S_PERSMIN)
#define G_PERSMIN(x) (((x) >> S_PERSMIN) & M_PERSMIN)

#define A_TP_PERS_MAX 0x7da4

#define S_PERSMAX    0
#define M_PERSMAX    0x3fffffffU
#define V_PERSMAX(x) ((x) << S_PERSMAX)
#define G_PERSMAX(x) (((x) >> S_PERSMAX) & M_PERSMAX)

#define A_TP_KEEP_IDLE 0x7da8

#define S_KEEPALIVEIDLE    0
#define M_KEEPALIVEIDLE    0x3fffffffU
#define V_KEEPALIVEIDLE(x) ((x) << S_KEEPALIVEIDLE)
#define G_KEEPALIVEIDLE(x) (((x) >> S_KEEPALIVEIDLE) & M_KEEPALIVEIDLE)

#define A_TP_KEEP_INTVL 0x7dac

#define S_KEEPALIVEINTVL    0
#define M_KEEPALIVEINTVL    0x3fffffffU
#define V_KEEPALIVEINTVL(x) ((x) << S_KEEPALIVEINTVL)
#define G_KEEPALIVEINTVL(x) (((x) >> S_KEEPALIVEINTVL) & M_KEEPALIVEINTVL)

#define A_TP_INIT_SRTT 0x7db0

#define S_MAXRTT    16
#define M_MAXRTT    0xffffU
#define V_MAXRTT(x) ((x) << S_MAXRTT)
#define G_MAXRTT(x) (((x) >> S_MAXRTT) & M_MAXRTT)

#define S_INITSRTT    0
#define M_INITSRTT    0xffffU
#define V_INITSRTT(x) ((x) << S_INITSRTT)
#define G_INITSRTT(x) (((x) >> S_INITSRTT) & M_INITSRTT)

#define A_TP_DACK_TIMER 0x7db4

#define S_DACKTIME    0
#define M_DACKTIME    0xfffU
#define V_DACKTIME(x) ((x) << S_DACKTIME)
#define G_DACKTIME(x) (((x) >> S_DACKTIME) & M_DACKTIME)

#define A_TP_FINWAIT2_TIMER 0x7db8

#define S_FINWAIT2TIME    0
#define M_FINWAIT2TIME    0x3fffffffU
#define V_FINWAIT2TIME(x) ((x) << S_FINWAIT2TIME)
#define G_FINWAIT2TIME(x) (((x) >> S_FINWAIT2TIME) & M_FINWAIT2TIME)

#define A_TP_SHIFT_CNT 0x7dc0

#define S_SYNSHIFTMAX    24
#define M_SYNSHIFTMAX    0xffU
#define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX)
#define G_SYNSHIFTMAX(x) (((x) >> S_SYNSHIFTMAX) & M_SYNSHIFTMAX)

#define S_RXTSHIFTMAXR1    20
#define M_RXTSHIFTMAXR1    0xfU
#define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1)
#define G_RXTSHIFTMAXR1(x) (((x) >> S_RXTSHIFTMAXR1) & M_RXTSHIFTMAXR1)

#define S_RXTSHIFTMAXR2    16
#define M_RXTSHIFTMAXR2    0xfU
#define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2)
#define G_RXTSHIFTMAXR2(x) (((x) >> S_RXTSHIFTMAXR2) & M_RXTSHIFTMAXR2)

#define S_PERSHIFTBACKOFFMAX    12
#define M_PERSHIFTBACKOFFMAX    0xfU
#define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX)
#define G_PERSHIFTBACKOFFMAX(x) (((x) >> S_PERSHIFTBACKOFFMAX) & M_PERSHIFTBACKOFFMAX)

#define S_PERSHIFTMAX    8
#define M_PERSHIFTMAX    0xfU
#define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX)
#define G_PERSHIFTMAX(x) (((x) >> S_PERSHIFTMAX) & M_PERSHIFTMAX)

#define S_KEEPALIVEMAXR1    4
#define M_KEEPALIVEMAXR1    0xfU
#define V_KEEPALIVEMAXR1(x) ((x) << S_KEEPALIVEMAXR1)
#define G_KEEPALIVEMAXR1(x) (((x) >> S_KEEPALIVEMAXR1) & M_KEEPALIVEMAXR1)

#define S_KEEPALIVEMAXR2    0
#define M_KEEPALIVEMAXR2    0xfU
#define V_KEEPALIVEMAXR2(x) ((x) << S_KEEPALIVEMAXR2)
#define G_KEEPALIVEMAXR2(x) (((x) >> S_KEEPALIVEMAXR2) & M_KEEPALIVEMAXR2)

#define S_T6_SYNSHIFTMAX    24
#define M_T6_SYNSHIFTMAX    0xfU
#define V_T6_SYNSHIFTMAX(x) ((x) << S_T6_SYNSHIFTMAX)
#define G_T6_SYNSHIFTMAX(x) (((x) >> S_T6_SYNSHIFTMAX) & M_T6_SYNSHIFTMAX)

#define A_TP_TIME_LO 0x7dc8
#define A_TP_TIME_HI 0x7dcc
#define A_TP_PACE_TABLE 0x7dd8
#define A_TP_CCTRL_TABLE 0x7ddc

#define S_ROWINDEX    16
#define M_ROWINDEX    0xffffU
#define V_ROWINDEX(x) ((x) << S_ROWINDEX)
#define G_ROWINDEX(x) (((x) >> S_ROWINDEX) & M_ROWINDEX)

#define S_ROWVALUE    0
#define M_ROWVALUE    0xffffU
#define V_ROWVALUE(x) ((x) << S_ROWVALUE)
#define G_ROWVALUE(x) (((x) >> S_ROWVALUE) & M_ROWVALUE)

#define A_TP_MTU_TABLE 0x7de4

#define S_MTUINDEX    24
#define M_MTUINDEX    0xffU
#define V_MTUINDEX(x) ((x) << S_MTUINDEX)
#define G_MTUINDEX(x) (((x) >> S_MTUINDEX) & M_MTUINDEX)

#define S_MTUWIDTH    16
#define M_MTUWIDTH    0xfU
#define V_MTUWIDTH(x) ((x) << S_MTUWIDTH)
#define G_MTUWIDTH(x) (((x) >> S_MTUWIDTH) & M_MTUWIDTH)

#define S_MTUVALUE    0
#define M_MTUVALUE    0x3fffU
#define V_MTUVALUE(x) ((x) << S_MTUVALUE)
#define G_MTUVALUE(x) (((x) >> S_MTUVALUE) & M_MTUVALUE)

#define A_TP_RSS_LKP_TABLE 0x7dec

#define S_LKPTBLROWVLD    31
#define V_LKPTBLROWVLD(x) ((x) << S_LKPTBLROWVLD)
#define F_LKPTBLROWVLD    V_LKPTBLROWVLD(1U)

#define S_LKPTBLROWIDX    20
#define M_LKPTBLROWIDX    0x3ffU
#define V_LKPTBLROWIDX(x) ((x) << S_LKPTBLROWIDX)
#define G_LKPTBLROWIDX(x) (((x) >> S_LKPTBLROWIDX) & M_LKPTBLROWIDX)

#define S_LKPTBLQUEUE1    10
#define M_LKPTBLQUEUE1    0x3ffU
#define V_LKPTBLQUEUE1(x) ((x) << S_LKPTBLQUEUE1)
#define G_LKPTBLQUEUE1(x) (((x) >> S_LKPTBLQUEUE1) & M_LKPTBLQUEUE1)

#define S_LKPTBLQUEUE0    0
#define M_LKPTBLQUEUE0    0x3ffU
#define V_LKPTBLQUEUE0(x) ((x) << S_LKPTBLQUEUE0)
#define G_LKPTBLQUEUE0(x) (((x) >> S_LKPTBLQUEUE0) & M_LKPTBLQUEUE0)

#define S_T6_LKPTBLROWIDX    20
#define M_T6_LKPTBLROWIDX    0x7ffU
#define V_T6_LKPTBLROWIDX(x) ((x) << S_T6_LKPTBLROWIDX)
#define G_T6_LKPTBLROWIDX(x) (((x) >> S_T6_LKPTBLROWIDX) & M_T6_LKPTBLROWIDX)

#define A_TP_RSS_CONFIG 0x7df0

#define S_TNL4TUPENIPV6    31
#define V_TNL4TUPENIPV6(x) ((x) << S_TNL4TUPENIPV6)
#define F_TNL4TUPENIPV6    V_TNL4TUPENIPV6(1U)

#define S_TNL2TUPENIPV6    30
#define V_TNL2TUPENIPV6(x) ((x) << S_TNL2TUPENIPV6)
#define F_TNL2TUPENIPV6    V_TNL2TUPENIPV6(1U)

#define S_TNL4TUPENIPV4    29
#define V_TNL4TUPENIPV4(x) ((x) << S_TNL4TUPENIPV4)
#define F_TNL4TUPENIPV4    V_TNL4TUPENIPV4(1U)

#define S_TNL2TUPENIPV4    28
#define V_TNL2TUPENIPV4(x) ((x) << S_TNL2TUPENIPV4)
#define F_TNL2TUPENIPV4    V_TNL2TUPENIPV4(1U)

#define S_TNLTCPSEL    27
#define V_TNLTCPSEL(x) ((x) << S_TNLTCPSEL)
#define F_TNLTCPSEL    V_TNLTCPSEL(1U)

#define S_TNLIP6SEL    26
#define V_TNLIP6SEL(x) ((x) << S_TNLIP6SEL)
#define F_TNLIP6SEL    V_TNLIP6SEL(1U)

#define S_TNLVRTSEL    25
#define V_TNLVRTSEL(x) ((x) << S_TNLVRTSEL)
#define F_TNLVRTSEL    V_TNLVRTSEL(1U)

#define S_TNLMAPEN    24
#define V_TNLMAPEN(x) ((x) << S_TNLMAPEN)
#define F_TNLMAPEN    V_TNLMAPEN(1U)

#define S_OFDHASHSAVE    19
#define V_OFDHASHSAVE(x) ((x) << S_OFDHASHSAVE)
#define F_OFDHASHSAVE    V_OFDHASHSAVE(1U)

#define S_OFDVRTSEL    18
#define V_OFDVRTSEL(x) ((x) << S_OFDVRTSEL)
#define F_OFDVRTSEL    V_OFDVRTSEL(1U)

#define S_OFDMAPEN    17
#define V_OFDMAPEN(x) ((x) << S_OFDMAPEN)
#define F_OFDMAPEN    V_OFDMAPEN(1U)

#define S_OFDLKPEN    16
#define V_OFDLKPEN(x) ((x) << S_OFDLKPEN)
#define F_OFDLKPEN    V_OFDLKPEN(1U)

#define S_SYN4TUPENIPV6    15
#define V_SYN4TUPENIPV6(x) ((x) << S_SYN4TUPENIPV6)
#define F_SYN4TUPENIPV6    V_SYN4TUPENIPV6(1U)

#define S_SYN2TUPENIPV6    14
#define V_SYN2TUPENIPV6(x) ((x) << S_SYN2TUPENIPV6)
#define F_SYN2TUPENIPV6    V_SYN2TUPENIPV6(1U)

#define S_SYN4TUPENIPV4    13
#define V_SYN4TUPENIPV4(x) ((x) << S_SYN4TUPENIPV4)
#define F_SYN4TUPENIPV4    V_SYN4TUPENIPV4(1U)

#define S_SYN2TUPENIPV4    12
#define V_SYN2TUPENIPV4(x) ((x) << S_SYN2TUPENIPV4)
#define F_SYN2TUPENIPV4    V_SYN2TUPENIPV4(1U)

#define S_SYNIP6SEL    11
#define V_SYNIP6SEL(x) ((x) << S_SYNIP6SEL)
#define F_SYNIP6SEL    V_SYNIP6SEL(1U)

#define S_SYNVRTSEL    10
#define V_SYNVRTSEL(x) ((x) << S_SYNVRTSEL)
#define F_SYNVRTSEL    V_SYNVRTSEL(1U)

#define S_SYNMAPEN    9
#define V_SYNMAPEN(x) ((x) << S_SYNMAPEN)
#define F_SYNMAPEN    V_SYNMAPEN(1U)

#define S_SYNLKPEN    8
#define V_SYNLKPEN(x) ((x) << S_SYNLKPEN)
#define F_SYNLKPEN    V_SYNLKPEN(1U)

#define S_CHANNELENABLE    7
#define V_CHANNELENABLE(x) ((x) << S_CHANNELENABLE)
#define F_CHANNELENABLE    V_CHANNELENABLE(1U)

#define S_PORTENABLE    6
#define V_PORTENABLE(x) ((x) << S_PORTENABLE)
#define F_PORTENABLE    V_PORTENABLE(1U)

#define S_TNLALLLOOKUP    5
#define V_TNLALLLOOKUP(x) ((x) << S_TNLALLLOOKUP)
#define F_TNLALLLOOKUP    V_TNLALLLOOKUP(1U)

#define S_VIRTENABLE    4
#define V_VIRTENABLE(x) ((x) << S_VIRTENABLE)
#define F_VIRTENABLE    V_VIRTENABLE(1U)

#define S_CONGESTIONENABLE    3
#define V_CONGESTIONENABLE(x) ((x) << S_CONGESTIONENABLE)
#define F_CONGESTIONENABLE    V_CONGESTIONENABLE(1U)

#define S_HASHTOEPLITZ    2
#define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ)
#define F_HASHTOEPLITZ    V_HASHTOEPLITZ(1U)

#define S_UDPENABLE    1
#define V_UDPENABLE(x) ((x) << S_UDPENABLE)
#define F_UDPENABLE    V_UDPENABLE(1U)

#define S_DISABLE    0
#define V_DISABLE(x) ((x) << S_DISABLE)
#define F_DISABLE    V_DISABLE(1U)

#define S_TNLFCOEMODE    23
#define V_TNLFCOEMODE(x) ((x) << S_TNLFCOEMODE)
#define F_TNLFCOEMODE    V_TNLFCOEMODE(1U)

#define S_TNLFCOEEN    21
#define V_TNLFCOEEN(x) ((x) << S_TNLFCOEEN)
#define F_TNLFCOEEN    V_TNLFCOEEN(1U)

#define S_HASHXOR    20
#define V_HASHXOR(x) ((x) << S_HASHXOR)
#define F_HASHXOR    V_HASHXOR(1U)

#define S_TNLFCOESID    22
#define V_TNLFCOESID(x) ((x) << S_TNLFCOESID)
#define F_TNLFCOESID    V_TNLFCOESID(1U)

#define A_TP_RSS_CONFIG_TNL 0x7df4

#define S_MASKSIZE    28
#define M_MASKSIZE    0xfU
#define V_MASKSIZE(x) ((x) << S_MASKSIZE)
#define G_MASKSIZE(x) (((x) >> S_MASKSIZE) & M_MASKSIZE)

#define S_MASKFILTER    16
#define M_MASKFILTER    0x7ffU
#define V_MASKFILTER(x) ((x) << S_MASKFILTER)
#define G_MASKFILTER(x) (((x) >> S_MASKFILTER) & M_MASKFILTER)

#define S_USEWIRECH    0
#define V_USEWIRECH(x) ((x) << S_USEWIRECH)
#define F_USEWIRECH    V_USEWIRECH(1U)

#define S_HASHALL    2
#define V_HASHALL(x) ((x) << S_HASHALL)
#define F_HASHALL    V_HASHALL(1U)

#define S_HASHETH    1
#define V_HASHETH(x) ((x) << S_HASHETH)
#define F_HASHETH    V_HASHETH(1U)

#define A_TP_RSS_CONFIG_OFD 0x7df8

#define S_RRCPLMAPEN    20
#define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN)
#define F_RRCPLMAPEN    V_RRCPLMAPEN(1U)

#define S_RRCPLQUEWIDTH    16
#define M_RRCPLQUEWIDTH    0xfU
#define V_RRCPLQUEWIDTH(x) ((x) << S_RRCPLQUEWIDTH)
#define G_RRCPLQUEWIDTH(x) (((x) >> S_RRCPLQUEWIDTH) & M_RRCPLQUEWIDTH)

#define S_FRMWRQUEMASK    12
#define M_FRMWRQUEMASK    0xfU
#define V_FRMWRQUEMASK(x) ((x) << S_FRMWRQUEMASK)
#define G_FRMWRQUEMASK(x) (((x) >> S_FRMWRQUEMASK) & M_FRMWRQUEMASK)

#define A_TP_RSS_CONFIG_SYN 0x7dfc
#define A_TP_RSS_CONFIG_VRT 0x7e00

#define S_VFRDRG    25
#define V_VFRDRG(x) ((x) << S_VFRDRG)
#define F_VFRDRG    V_VFRDRG(1U)

#define S_VFRDEN    24
#define V_VFRDEN(x) ((x) << S_VFRDEN)
#define F_VFRDEN    V_VFRDEN(1U)

#define S_VFPERREN    23
#define V_VFPERREN(x) ((x) << S_VFPERREN)
#define F_VFPERREN    V_VFPERREN(1U)

#define S_KEYPERREN    22
#define V_KEYPERREN(x) ((x) << S_KEYPERREN)
#define F_KEYPERREN    V_KEYPERREN(1U)

#define S_DISABLEVLAN    21
#define V_DISABLEVLAN(x) ((x) << S_DISABLEVLAN)
#define F_DISABLEVLAN    V_DISABLEVLAN(1U)

#define S_ENABLEUP0    20
#define V_ENABLEUP0(x) ((x) << S_ENABLEUP0)
#define F_ENABLEUP0    V_ENABLEUP0(1U)

#define S_HASHDELAY    16
#define M_HASHDELAY    0xfU
#define V_HASHDELAY(x) ((x) << S_HASHDELAY)
#define G_HASHDELAY(x) (((x) >> S_HASHDELAY) & M_HASHDELAY)

#define S_VFWRADDR    8
#define M_VFWRADDR    0x7fU
#define V_VFWRADDR(x) ((x) << S_VFWRADDR)
#define G_VFWRADDR(x) (((x) >> S_VFWRADDR) & M_VFWRADDR)

#define S_KEYMODE    6
#define M_KEYMODE    0x3U
#define V_KEYMODE(x) ((x) << S_KEYMODE)
#define G_KEYMODE(x) (((x) >> S_KEYMODE) & M_KEYMODE)

#define S_VFWREN    5
#define V_VFWREN(x) ((x) << S_VFWREN)
#define F_VFWREN    V_VFWREN(1U)

#define S_KEYWREN    4
#define V_KEYWREN(x) ((x) << S_KEYWREN)
#define F_KEYWREN    V_KEYWREN(1U)

#define S_KEYWRADDR    0
#define M_KEYWRADDR    0xfU
#define V_KEYWRADDR(x) ((x) << S_KEYWRADDR)
#define G_KEYWRADDR(x) (((x) >> S_KEYWRADDR) & M_KEYWRADDR)

#define S_VFVLANEN    21
#define V_VFVLANEN(x) ((x) << S_VFVLANEN)
#define F_VFVLANEN    V_VFVLANEN(1U)

#define S_VFFWEN    20
#define V_VFFWEN(x) ((x) << S_VFFWEN)
#define F_VFFWEN    V_VFFWEN(1U)

#define S_KEYWRADDRX    30
#define M_KEYWRADDRX    0x3U
#define V_KEYWRADDRX(x) ((x) << S_KEYWRADDRX)
#define G_KEYWRADDRX(x) (((x) >> S_KEYWRADDRX) & M_KEYWRADDRX)

#define S_KEYEXTEND    26
#define V_KEYEXTEND(x) ((x) << S_KEYEXTEND)
#define F_KEYEXTEND    V_KEYEXTEND(1U)

#define S_T6_VFWRADDR    8
#define M_T6_VFWRADDR    0xffU
#define V_T6_VFWRADDR(x) ((x) << S_T6_VFWRADDR)
#define G_T6_VFWRADDR(x) (((x) >> S_T6_VFWRADDR) & M_T6_VFWRADDR)

#define A_TP_RSS_CONFIG_CNG 0x7e04

#define S_CHNCOUNT3    31
#define V_CHNCOUNT3(x) ((x) << S_CHNCOUNT3)
#define F_CHNCOUNT3    V_CHNCOUNT3(1U)

#define S_CHNCOUNT2    30
#define V_CHNCOUNT2(x) ((x) << S_CHNCOUNT2)
#define F_CHNCOUNT2    V_CHNCOUNT2(1U)

#define S_CHNCOUNT1    29
#define V_CHNCOUNT1(x) ((x) << S_CHNCOUNT1)
#define F_CHNCOUNT1    V_CHNCOUNT1(1U)

#define S_CHNCOUNT0    28
#define V_CHNCOUNT0(x) ((x) << S_CHNCOUNT0)
#define F_CHNCOUNT0    V_CHNCOUNT0(1U)

#define S_CHNUNDFLOW3    27
#define V_CHNUNDFLOW3(x) ((x) << S_CHNUNDFLOW3)
#define F_CHNUNDFLOW3    V_CHNUNDFLOW3(1U)

#define S_CHNUNDFLOW2    26
#define V_CHNUNDFLOW2(x) ((x) << S_CHNUNDFLOW2)
#define F_CHNUNDFLOW2    V_CHNUNDFLOW2(1U)

#define S_CHNUNDFLOW1    25
#define V_CHNUNDFLOW1(x) ((x) << S_CHNUNDFLOW1)
#define F_CHNUNDFLOW1    V_CHNUNDFLOW1(1U)

#define S_CHNUNDFLOW0    24
#define V_CHNUNDFLOW0(x) ((x) << S_CHNUNDFLOW0)
#define F_CHNUNDFLOW0    V_CHNUNDFLOW0(1U)

#define S_CHNOVRFLOW3    23
#define V_CHNOVRFLOW3(x) ((x) << S_CHNOVRFLOW3)
#define F_CHNOVRFLOW3    V_CHNOVRFLOW3(1U)

#define S_CHNOVRFLOW2    22
#define V_CHNOVRFLOW2(x) ((x) << S_CHNOVRFLOW2)
#define F_CHNOVRFLOW2    V_CHNOVRFLOW2(1U)

#define S_CHNOVRFLOW1    21
#define V_CHNOVRFLOW1(x) ((x) << S_CHNOVRFLOW1)
#define F_CHNOVRFLOW1    V_CHNOVRFLOW1(1U)

#define S_CHNOVRFLOW0    20
#define V_CHNOVRFLOW0(x) ((x) << S_CHNOVRFLOW0)
#define F_CHNOVRFLOW0    V_CHNOVRFLOW0(1U)

#define S_RSTCHN3    19
#define V_RSTCHN3(x) ((x) << S_RSTCHN3)
#define F_RSTCHN3    V_RSTCHN3(1U)

#define S_RSTCHN2    18
#define V_RSTCHN2(x) ((x) << S_RSTCHN2)
#define F_RSTCHN2    V_RSTCHN2(1U)

#define S_RSTCHN1    17
#define V_RSTCHN1(x) ((x) << S_RSTCHN1)
#define F_RSTCHN1    V_RSTCHN1(1U)

#define S_RSTCHN0    16
#define V_RSTCHN0(x) ((x) << S_RSTCHN0)
#define F_RSTCHN0    V_RSTCHN0(1U)

#define S_UPDVLD    15
#define V_UPDVLD(x) ((x) << S_UPDVLD)
#define F_UPDVLD    V_UPDVLD(1U)

#define S_XOFF    14
#define V_XOFF(x) ((x) << S_XOFF)
#define F_XOFF    V_XOFF(1U)

#define S_UPDCHN3    13
#define V_UPDCHN3(x) ((x) << S_UPDCHN3)
#define F_UPDCHN3    V_UPDCHN3(1U)

#define S_UPDCHN2    12
#define V_UPDCHN2(x) ((x) << S_UPDCHN2)
#define F_UPDCHN2    V_UPDCHN2(1U)

#define S_UPDCHN1    11
#define V_UPDCHN1(x) ((x) << S_UPDCHN1)
#define F_UPDCHN1    V_UPDCHN1(1U)

#define S_UPDCHN0    10
#define V_UPDCHN0(x) ((x) << S_UPDCHN0)
#define F_UPDCHN0    V_UPDCHN0(1U)

#define S_QUEUE    0
#define M_QUEUE    0x3ffU
#define V_QUEUE(x) ((x) << S_QUEUE)
#define G_QUEUE(x) (((x) >> S_QUEUE) & M_QUEUE)

#define A_TP_TM_PIO_ADDR 0x7e18
#define A_TP_TM_PIO_DATA 0x7e1c
#define A_TP_MOD_CONFIG 0x7e24

#define S_RXCHANNELWEIGHT1    24
#define M_RXCHANNELWEIGHT1    0xffU
#define V_RXCHANNELWEIGHT1(x) ((x) << S_RXCHANNELWEIGHT1)
#define G_RXCHANNELWEIGHT1(x) (((x) >> S_RXCHANNELWEIGHT1) & M_RXCHANNELWEIGHT1)

#define S_RXCHANNELWEIGHT0    16
#define M_RXCHANNELWEIGHT0    0xffU
#define V_RXCHANNELWEIGHT0(x) ((x) << S_RXCHANNELWEIGHT0)
#define G_RXCHANNELWEIGHT0(x) (((x) >> S_RXCHANNELWEIGHT0) & M_RXCHANNELWEIGHT0)

#define S_TIMERMODE    8
#define M_TIMERMODE    0xffU
#define V_TIMERMODE(x) ((x) << S_TIMERMODE)
#define G_TIMERMODE(x) (((x) >> S_TIMERMODE) & M_TIMERMODE)

#define S_TXCHANNELXOFFEN    0
#define M_TXCHANNELXOFFEN    0xfU
#define V_TXCHANNELXOFFEN(x) ((x) << S_TXCHANNELXOFFEN)
#define G_TXCHANNELXOFFEN(x) (((x) >> S_TXCHANNELXOFFEN) & M_TXCHANNELXOFFEN)

#define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28

#define S_RX_MOD_WEIGHT    24
#define M_RX_MOD_WEIGHT    0xffU
#define V_RX_MOD_WEIGHT(x) ((x) << S_RX_MOD_WEIGHT)
#define G_RX_MOD_WEIGHT(x) (((x) >> S_RX_MOD_WEIGHT) & M_RX_MOD_WEIGHT)

#define S_TX_MOD_WEIGHT    16
#define M_TX_MOD_WEIGHT    0xffU
#define V_TX_MOD_WEIGHT(x) ((x) << S_TX_MOD_WEIGHT)
#define G_TX_MOD_WEIGHT(x) (((x) >> S_TX_MOD_WEIGHT) & M_TX_MOD_WEIGHT)

#define S_TX_MOD_QUEUE_REQ_MAP    0
#define M_TX_MOD_QUEUE_REQ_MAP    0xffffU
#define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
#define G_TX_MOD_QUEUE_REQ_MAP(x) (((x) >> S_TX_MOD_QUEUE_REQ_MAP) & M_TX_MOD_QUEUE_REQ_MAP)

#define A_TP_TX_MOD_QUEUE_WEIGHT1 0x7e2c

#define S_TX_MODQ_WEIGHT7    24
#define M_TX_MODQ_WEIGHT7    0xffU
#define V_TX_MODQ_WEIGHT7(x) ((x) << S_TX_MODQ_WEIGHT7)
#define G_TX_MODQ_WEIGHT7(x) (((x) >> S_TX_MODQ_WEIGHT7) & M_TX_MODQ_WEIGHT7)

#define S_TX_MODQ_WEIGHT6    16
#define M_TX_MODQ_WEIGHT6    0xffU
#define V_TX_MODQ_WEIGHT6(x) ((x) << S_TX_MODQ_WEIGHT6)
#define G_TX_MODQ_WEIGHT6(x) (((x) >> S_TX_MODQ_WEIGHT6) & M_TX_MODQ_WEIGHT6)

#define S_TX_MODQ_WEIGHT5    8
#define M_TX_MODQ_WEIGHT5    0xffU
#define V_TX_MODQ_WEIGHT5(x) ((x) << S_TX_MODQ_WEIGHT5)
#define G_TX_MODQ_WEIGHT5(x) (((x) >> S_TX_MODQ_WEIGHT5) & M_TX_MODQ_WEIGHT5)

#define S_TX_MODQ_WEIGHT4    0
#define M_TX_MODQ_WEIGHT4    0xffU
#define V_TX_MODQ_WEIGHT4(x) ((x) << S_TX_MODQ_WEIGHT4)
#define G_TX_MODQ_WEIGHT4(x) (((x) >> S_TX_MODQ_WEIGHT4) & M_TX_MODQ_WEIGHT4)

#define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30

#define S_TX_MODQ_WEIGHT3    24
#define M_TX_MODQ_WEIGHT3    0xffU
#define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3)
#define G_TX_MODQ_WEIGHT3(x) (((x) >> S_TX_MODQ_WEIGHT3) & M_TX_MODQ_WEIGHT3)

#define S_TX_MODQ_WEIGHT2    16
#define M_TX_MODQ_WEIGHT2    0xffU
#define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2)
#define G_TX_MODQ_WEIGHT2(x) (((x) >> S_TX_MODQ_WEIGHT2) & M_TX_MODQ_WEIGHT2)

#define S_TX_MODQ_WEIGHT1    8
#define M_TX_MODQ_WEIGHT1    0xffU
#define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1)
#define G_TX_MODQ_WEIGHT1(x) (((x) >> S_TX_MODQ_WEIGHT1) & M_TX_MODQ_WEIGHT1)

#define S_TX_MODQ_WEIGHT0    0
#define M_TX_MODQ_WEIGHT0    0xffU
#define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0)
#define G_TX_MODQ_WEIGHT0(x) (((x) >> S_TX_MODQ_WEIGHT0) & M_TX_MODQ_WEIGHT0)

#define A_TP_PIO_ADDR 0x7e40
#define A_TP_PIO_DATA 0x7e44
#define A_TP_MIB_INDEX 0x7e50
#define A_TP_MIB_DATA 0x7e54
#define A_TP_CMM_MM_RX_FLST_BASE 0x7e60
#define A_TP_CMM_MM_TX_FLST_BASE 0x7e64
#define A_TP_CMM_MM_PS_FLST_BASE 0x7e68
#define A_TP_CMM_MM_MAX_PSTRUCT 0x7e6c

#define S_CMMAXPSTRUCT    0
#define M_CMMAXPSTRUCT    0x1fffffU
#define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT)
#define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT)

#define A_TP_INT_ENABLE 0x7e70

#define S_FLMTXFLSTEMPTY    30
#define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY)
#define F_FLMTXFLSTEMPTY    V_FLMTXFLSTEMPTY(1U)

#define A_TP_INT_CAUSE 0x7e74
#define A_TP_PER_ENABLE 0x7e78
#define A_TP_TX_ORATE 0x7ebc

#define S_OFDRATE3    24
#define M_OFDRATE3    0xffU
#define V_OFDRATE3(x) ((x) << S_OFDRATE3)
#define G_OFDRATE3(x) (((x) >> S_OFDRATE3) & M_OFDRATE3)

#define S_OFDRATE2    16
#define M_OFDRATE2    0xffU
#define V_OFDRATE2(x) ((x) << S_OFDRATE2)
#define G_OFDRATE2(x) (((x) >> S_OFDRATE2) & M_OFDRATE2)

#define S_OFDRATE1    8
#define M_OFDRATE1    0xffU
#define V_OFDRATE1(x) ((x) << S_OFDRATE1)
#define G_OFDRATE1(x) (((x) >> S_OFDRATE1) & M_OFDRATE1)

#define S_OFDRATE0    0
#define M_OFDRATE0    0xffU
#define V_OFDRATE0(x) ((x) << S_OFDRATE0)
#define G_OFDRATE0(x) (((x) >> S_OFDRATE0) & M_OFDRATE0)

#define A_TP_TX_TRATE 0x7ed0

#define S_TNLRATE3    24
#define M_TNLRATE3    0xffU
#define V_TNLRATE3(x) ((x) << S_TNLRATE3)
#define G_TNLRATE3(x) (((x) >> S_TNLRATE3) & M_TNLRATE3)

#define S_TNLRATE2    16
#define M_TNLRATE2    0xffU
#define V_TNLRATE2(x) ((x) << S_TNLRATE2)
#define G_TNLRATE2(x) (((x) >> S_TNLRATE2) & M_TNLRATE2)

#define S_TNLRATE1    8
#define M_TNLRATE1    0xffU
#define V_TNLRATE1(x) ((x) << S_TNLRATE1)
#define G_TNLRATE1(x) (((x) >> S_TNLRATE1) & M_TNLRATE1)

#define S_TNLRATE0    0
#define M_TNLRATE0    0xffU
#define V_TNLRATE0(x) ((x) << S_TNLRATE0)
#define G_TNLRATE0(x) (((x) >> S_TNLRATE0) & M_TNLRATE0)

#define A_TP_DBG_LA_CONFIG 0x7ed4

#define S_DBGLAOPCENABLE    24
#define M_DBGLAOPCENABLE    0xffU
#define V_DBGLAOPCENABLE(x) ((x) << S_DBGLAOPCENABLE)
#define G_DBGLAOPCENABLE(x) (((x) >> S_DBGLAOPCENABLE) & M_DBGLAOPCENABLE)

#define S_DBGLAWHLF    23
#define V_DBGLAWHLF(x) ((x) << S_DBGLAWHLF)
#define F_DBGLAWHLF    V_DBGLAWHLF(1U)

#define S_DBGLAWPTR    16
#define M_DBGLAWPTR    0x7fU
#define V_DBGLAWPTR(x) ((x) << S_DBGLAWPTR)
#define G_DBGLAWPTR(x) (((x) >> S_DBGLAWPTR) & M_DBGLAWPTR)

#define S_DBGLAMODE    14
#define M_DBGLAMODE    0x3U
#define V_DBGLAMODE(x) ((x) << S_DBGLAMODE)
#define G_DBGLAMODE(x) (((x) >> S_DBGLAMODE) & M_DBGLAMODE)

#define S_DBGLAFATALFREEZE    13
#define V_DBGLAFATALFREEZE(x) ((x) << S_DBGLAFATALFREEZE)
#define F_DBGLAFATALFREEZE    V_DBGLAFATALFREEZE(1U)

#define S_DBGLAENABLE    12
#define V_DBGLAENABLE(x) ((x) << S_DBGLAENABLE)
#define F_DBGLAENABLE    V_DBGLAENABLE(1U)

#define S_DBGLARPTR    0
#define M_DBGLARPTR    0x7fU
#define V_DBGLARPTR(x) ((x) << S_DBGLARPTR)
#define G_DBGLARPTR(x) (((x) >> S_DBGLARPTR) & M_DBGLARPTR)

#define A_TP_DBG_LA_DATAL 0x7ed8
#define A_TP_DBG_LA_DATAH 0x7edc
#define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3

#define S_TXTIMERSEPQ1    16
#define M_TXTIMERSEPQ1    0xffffU
#define V_TXTIMERSEPQ1(x) ((x) << S_TXTIMERSEPQ1)
#define G_TXTIMERSEPQ1(x) (((x) >> S_TXTIMERSEPQ1) & M_TXTIMERSEPQ1)

#define S_TXTIMERSEPQ0    0
#define M_TXTIMERSEPQ0    0xffffU
#define V_TXTIMERSEPQ0(x) ((x) << S_TXTIMERSEPQ0)
#define G_TXTIMERSEPQ0(x) (((x) >> S_TXTIMERSEPQ0) & M_TXTIMERSEPQ0)

#define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8

#define S_TXRATEINCQ1    24
#define M_TXRATEINCQ1    0xffU
#define V_TXRATEINCQ1(x) ((x) << S_TXRATEINCQ1)
#define G_TXRATEINCQ1(x) (((x) >> S_TXRATEINCQ1) & M_TXRATEINCQ1)

#define S_TXRATETCKQ1    16
#define M_TXRATETCKQ1    0xffU
#define V_TXRATETCKQ1(x) ((x) << S_TXRATETCKQ1)
#define G_TXRATETCKQ1(x) (((x) >> S_TXRATETCKQ1) & M_TXRATETCKQ1)

#define S_TXRATEINCQ0    8
#define M_TXRATEINCQ0    0xffU
#define V_TXRATEINCQ0(x) ((x) << S_TXRATEINCQ0)
#define G_TXRATEINCQ0(x) (((x) >> S_TXRATEINCQ0) & M_TXRATEINCQ0)

#define S_TXRATETCKQ0    0
#define M_TXRATETCKQ0    0xffU
#define V_TXRATETCKQ0(x) ((x) << S_TXRATETCKQ0)
#define G_TXRATETCKQ0(x) (((x) >> S_TXRATETCKQ0) & M_TXRATETCKQ0)

#define A_TP_RSS_PF0_CONFIG 0x30

#define S_MAPENABLE    31
#define V_MAPENABLE(x) ((x) << S_MAPENABLE)
#define F_MAPENABLE    V_MAPENABLE(1U)

#define S_CHNENABLE    30
#define V_CHNENABLE(x) ((x) << S_CHNENABLE)
#define F_CHNENABLE    V_CHNENABLE(1U)

#define S_PRTENABLE    29
#define V_PRTENABLE(x) ((x) << S_PRTENABLE)
#define F_PRTENABLE    V_PRTENABLE(1U)

#define S_UDPFOURTUPEN    28
#define V_UDPFOURTUPEN(x) ((x) << S_UDPFOURTUPEN)
#define F_UDPFOURTUPEN    V_UDPFOURTUPEN(1U)

#define S_IP6FOURTUPEN    27
#define V_IP6FOURTUPEN(x) ((x) << S_IP6FOURTUPEN)
#define F_IP6FOURTUPEN    V_IP6FOURTUPEN(1U)

#define S_IP6TWOTUPEN    26
#define V_IP6TWOTUPEN(x) ((x) << S_IP6TWOTUPEN)
#define F_IP6TWOTUPEN    V_IP6TWOTUPEN(1U)

#define S_IP4FOURTUPEN    25
#define V_IP4FOURTUPEN(x) ((x) << S_IP4FOURTUPEN)
#define F_IP4FOURTUPEN    V_IP4FOURTUPEN(1U)

#define S_IP4TWOTUPEN    24
#define V_IP4TWOTUPEN(x) ((x) << S_IP4TWOTUPEN)
#define F_IP4TWOTUPEN    V_IP4TWOTUPEN(1U)

#define S_IVFWIDTH    20
#define M_IVFWIDTH    0xfU
#define V_IVFWIDTH(x) ((x) << S_IVFWIDTH)
#define G_IVFWIDTH(x) (((x) >> S_IVFWIDTH) & M_IVFWIDTH)

#define S_CH1DEFAULTQUEUE    10
#define M_CH1DEFAULTQUEUE    0x3ffU
#define V_CH1DEFAULTQUEUE(x) ((x) << S_CH1DEFAULTQUEUE)
#define G_CH1DEFAULTQUEUE(x) (((x) >> S_CH1DEFAULTQUEUE) & M_CH1DEFAULTQUEUE)

#define S_CH0DEFAULTQUEUE    0
#define M_CH0DEFAULTQUEUE    0x3ffU
#define V_CH0DEFAULTQUEUE(x) ((x) << S_CH0DEFAULTQUEUE)
#define G_CH0DEFAULTQUEUE(x) (((x) >> S_CH0DEFAULTQUEUE) & M_CH0DEFAULTQUEUE)

#define S_PRIENABLE    30
#define V_PRIENABLE(x) ((x) << S_PRIENABLE)
#define F_PRIENABLE    V_PRIENABLE(1U)

#define S_T6_CHNENABLE    29
#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
#define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)

#define A_TP_RSS_PF_MAP 0x38

#define S_LKPIDXSIZE    24
#define M_LKPIDXSIZE    0x3U
#define V_LKPIDXSIZE(x) ((x) << S_LKPIDXSIZE)
#define G_LKPIDXSIZE(x) (((x) >> S_LKPIDXSIZE) & M_LKPIDXSIZE)

#define S_PF7LKPIDX    21
#define M_PF7LKPIDX    0x7U
#define V_PF7LKPIDX(x) ((x) << S_PF7LKPIDX)
#define G_PF7LKPIDX(x) (((x) >> S_PF7LKPIDX) & M_PF7LKPIDX)

#define S_PF6LKPIDX    18
#define M_PF6LKPIDX    0x7U
#define V_PF6LKPIDX(x) ((x) << S_PF6LKPIDX)
#define G_PF6LKPIDX(x) (((x) >> S_PF6LKPIDX) & M_PF6LKPIDX)

#define S_PF5LKPIDX    15
#define M_PF5LKPIDX    0x7U
#define V_PF5LKPIDX(x) ((x) << S_PF5LKPIDX)
#define G_PF5LKPIDX(x) (((x) >> S_PF5LKPIDX) & M_PF5LKPIDX)

#define S_PF4LKPIDX    12
#define M_PF4LKPIDX    0x7U
#define V_PF4LKPIDX(x) ((x) << S_PF4LKPIDX)
#define G_PF4LKPIDX(x) (((x) >> S_PF4LKPIDX) & M_PF4LKPIDX)

#define S_PF3LKPIDX    9
#define M_PF3LKPIDX    0x7U
#define V_PF3LKPIDX(x) ((x) << S_PF3LKPIDX)
#define G_PF3LKPIDX(x) (((x) >> S_PF3LKPIDX) & M_PF3LKPIDX)

#define S_PF2LKPIDX    6
#define M_PF2LKPIDX    0x7U
#define V_PF2LKPIDX(x) ((x) << S_PF2LKPIDX)
#define G_PF2LKPIDX(x) (((x) >> S_PF2LKPIDX) & M_PF2LKPIDX)

#define S_PF1LKPIDX    3
#define M_PF1LKPIDX    0x7U
#define V_PF1LKPIDX(x) ((x) << S_PF1LKPIDX)
#define G_PF1LKPIDX(x) (((x) >> S_PF1LKPIDX) & M_PF1LKPIDX)

#define S_PF0LKPIDX    0
#define M_PF0LKPIDX    0x7U
#define V_PF0LKPIDX(x) ((x) << S_PF0LKPIDX)
#define G_PF0LKPIDX(x) (((x) >> S_PF0LKPIDX) & M_PF0LKPIDX)

#define A_TP_RSS_PF_MSK 0x39

#define S_PF7MSKSIZE    28
#define M_PF7MSKSIZE    0xfU
#define V_PF7MSKSIZE(x) ((x) << S_PF7MSKSIZE)
#define G_PF7MSKSIZE(x) (((x) >> S_PF7MSKSIZE) & M_PF7MSKSIZE)

#define S_PF6MSKSIZE    24
#define M_PF6MSKSIZE    0xfU
#define V_PF6MSKSIZE(x) ((x) << S_PF6MSKSIZE)
#define G_PF6MSKSIZE(x) (((x) >> S_PF6MSKSIZE) & M_PF6MSKSIZE)

#define S_PF5MSKSIZE    20
#define M_PF5MSKSIZE    0xfU
#define V_PF5MSKSIZE(x) ((x) << S_PF5MSKSIZE)
#define G_PF5MSKSIZE(x) (((x) >> S_PF5MSKSIZE) & M_PF5MSKSIZE)

#define S_PF4MSKSIZE    16
#define M_PF4MSKSIZE    0xfU
#define V_PF4MSKSIZE(x) ((x) << S_PF4MSKSIZE)
#define G_PF4MSKSIZE(x) (((x) >> S_PF4MSKSIZE) & M_PF4MSKSIZE)

#define S_PF3MSKSIZE    12
#define M_PF3MSKSIZE    0xfU
#define V_PF3MSKSIZE(x) ((x) << S_PF3MSKSIZE)
#define G_PF3MSKSIZE(x) (((x) >> S_PF3MSKSIZE) & M_PF3MSKSIZE)

#define S_PF2MSKSIZE    8
#define M_PF2MSKSIZE    0xfU
#define V_PF2MSKSIZE(x) ((x) << S_PF2MSKSIZE)
#define G_PF2MSKSIZE(x) (((x) >> S_PF2MSKSIZE) & M_PF2MSKSIZE)

#define S_PF1MSKSIZE    4
#define M_PF1MSKSIZE    0xfU
#define V_PF1MSKSIZE(x) ((x) << S_PF1MSKSIZE)
#define G_PF1MSKSIZE(x) (((x) >> S_PF1MSKSIZE) & M_PF1MSKSIZE)

#define S_PF0MSKSIZE    0
#define M_PF0MSKSIZE    0xfU
#define V_PF0MSKSIZE(x) ((x) << S_PF0MSKSIZE)
#define G_PF0MSKSIZE(x) (((x) >> S_PF0MSKSIZE) & M_PF0MSKSIZE)

#define A_TP_RSS_VFL_CONFIG 0x3a
#define A_TP_RSS_VFH_CONFIG 0x3b

#define S_ENABLEUDPHASH    31
#define V_ENABLEUDPHASH(x) ((x) << S_ENABLEUDPHASH)
#define F_ENABLEUDPHASH    V_ENABLEUDPHASH(1U)

#define S_VFUPEN    30
#define V_VFUPEN(x) ((x) << S_VFUPEN)
#define F_VFUPEN    V_VFUPEN(1U)

#define S_VFVLNEX    28
#define V_VFVLNEX(x) ((x) << S_VFVLNEX)
#define F_VFVLNEX    V_VFVLNEX(1U)

#define S_VFPRTEN    27
#define V_VFPRTEN(x) ((x) << S_VFPRTEN)
#define F_VFPRTEN    V_VFPRTEN(1U)

#define S_VFCHNEN    26
#define V_VFCHNEN(x) ((x) << S_VFCHNEN)
#define F_VFCHNEN    V_VFCHNEN(1U)

#define S_DEFAULTQUEUE    16
#define M_DEFAULTQUEUE    0x3ffU
#define V_DEFAULTQUEUE(x) ((x) << S_DEFAULTQUEUE)
#define G_DEFAULTQUEUE(x) (((x) >> S_DEFAULTQUEUE) & M_DEFAULTQUEUE)

#define S_VFLKPIDX    8
#define M_VFLKPIDX    0xffU
#define V_VFLKPIDX(x) ((x) << S_VFLKPIDX)
#define G_VFLKPIDX(x) (((x) >> S_VFLKPIDX) & M_VFLKPIDX)

#define S_VFIP6FOURTUPEN    7
#define V_VFIP6FOURTUPEN(x) ((x) << S_VFIP6FOURTUPEN)
#define F_VFIP6FOURTUPEN    V_VFIP6FOURTUPEN(1U)

#define S_VFIP6TWOTUPEN    6
#define V_VFIP6TWOTUPEN(x) ((x) << S_VFIP6TWOTUPEN)
#define F_VFIP6TWOTUPEN    V_VFIP6TWOTUPEN(1U)

#define S_VFIP4FOURTUPEN    5
#define V_VFIP4FOURTUPEN(x) ((x) << S_VFIP4FOURTUPEN)
#define F_VFIP4FOURTUPEN    V_VFIP4FOURTUPEN(1U)

#define S_VFIP4TWOTUPEN    4
#define V_VFIP4TWOTUPEN(x) ((x) << S_VFIP4TWOTUPEN)
#define F_VFIP4TWOTUPEN    V_VFIP4TWOTUPEN(1U)

#define S_KEYINDEX    0
#define M_KEYINDEX    0xfU
#define V_KEYINDEX(x) ((x) << S_KEYINDEX)
#define G_KEYINDEX(x) (((x) >> S_KEYINDEX) & M_KEYINDEX)

#define A_TP_RSS_SECRET_KEY0 0x40
#define A_TP_DBG_ESIDE_PKT0 0x130

#define S_ETXSOPCNT    28
#define M_ETXSOPCNT    0xfU
#define V_ETXSOPCNT(x) ((x) << S_ETXSOPCNT)
#define G_ETXSOPCNT(x) (((x) >> S_ETXSOPCNT) & M_ETXSOPCNT)

#define S_ETXEOPCNT    24
#define M_ETXEOPCNT    0xfU
#define V_ETXEOPCNT(x) ((x) << S_ETXEOPCNT)
#define G_ETXEOPCNT(x) (((x) >> S_ETXEOPCNT) & M_ETXEOPCNT)

#define S_ETXPLDSOPCNT    20
#define M_ETXPLDSOPCNT    0xfU
#define V_ETXPLDSOPCNT(x) ((x) << S_ETXPLDSOPCNT)
#define G_ETXPLDSOPCNT(x) (((x) >> S_ETXPLDSOPCNT) & M_ETXPLDSOPCNT)

#define S_ETXPLDEOPCNT    16
#define M_ETXPLDEOPCNT    0xfU
#define V_ETXPLDEOPCNT(x) ((x) << S_ETXPLDEOPCNT)
#define G_ETXPLDEOPCNT(x) (((x) >> S_ETXPLDEOPCNT) & M_ETXPLDEOPCNT)

#define S_ERXSOPCNT    12
#define M_ERXSOPCNT    0xfU
#define V_ERXSOPCNT(x) ((x) << S_ERXSOPCNT)
#define G_ERXSOPCNT(x) (((x) >> S_ERXSOPCNT) & M_ERXSOPCNT)

#define S_ERXEOPCNT    8
#define M_ERXEOPCNT    0xfU
#define V_ERXEOPCNT(x) ((x) << S_ERXEOPCNT)
#define G_ERXEOPCNT(x) (((x) >> S_ERXEOPCNT) & M_ERXEOPCNT)

#define S_ERXPLDSOPCNT    4
#define M_ERXPLDSOPCNT    0xfU
#define V_ERXPLDSOPCNT(x) ((x) << S_ERXPLDSOPCNT)
#define G_ERXPLDSOPCNT(x) (((x) >> S_ERXPLDSOPCNT) & M_ERXPLDSOPCNT)

#define S_ERXPLDEOPCNT    0
#define M_ERXPLDEOPCNT    0xfU
#define V_ERXPLDEOPCNT(x) ((x) << S_ERXPLDEOPCNT)
#define G_ERXPLDEOPCNT(x) (((x) >> S_ERXPLDEOPCNT) & M_ERXPLDEOPCNT)

#define A_TP_DBG_ESIDE_PKT1 0x131
#define A_TP_DBG_ESIDE_PKT2 0x132
#define A_TP_DBG_ESIDE_PKT3 0x133
#define A_TP_VLAN_PRI_MAP 0x140

#define S_FRAGMENTATION    9
#define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
#define F_FRAGMENTATION    V_FRAGMENTATION(1U)

#define S_MPSHITTYPE    8
#define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
#define F_MPSHITTYPE    V_MPSHITTYPE(1U)

#define S_MACMATCH    7
#define V_MACMATCH(x) ((x) << S_MACMATCH)
#define F_MACMATCH    V_MACMATCH(1U)

#define S_ETHERTYPE    6
#define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
#define F_ETHERTYPE    V_ETHERTYPE(1U)

#define S_PROTOCOL    5
#define V_PROTOCOL(x) ((x) << S_PROTOCOL)
#define F_PROTOCOL    V_PROTOCOL(1U)

#define S_TOS    4
#define V_TOS(x) ((x) << S_TOS)
#define F_TOS    V_TOS(1U)

#define S_VLAN    3
#define V_VLAN(x) ((x) << S_VLAN)
#define F_VLAN    V_VLAN(1U)

#define S_VNIC_ID    2
#define V_VNIC_ID(x) ((x) << S_VNIC_ID)
#define F_VNIC_ID    V_VNIC_ID(1U)

#define S_PORT    1
#define V_PORT(x) ((x) << S_PORT)
#define F_PORT    V_PORT(1U)

#define S_FCOE    0
#define V_FCOE(x) ((x) << S_FCOE)
#define F_FCOE    V_FCOE(1U)

#define S_FILTERMODE    15
#define V_FILTERMODE(x) ((x) << S_FILTERMODE)
#define F_FILTERMODE    V_FILTERMODE(1U)

#define S_FCOEMASK    14
#define V_FCOEMASK(x) ((x) << S_FCOEMASK)
#define F_FCOEMASK    V_FCOEMASK(1U)

#define S_SRVRSRAM    13
#define V_SRVRSRAM(x) ((x) << S_SRVRSRAM)
#define F_SRVRSRAM    V_SRVRSRAM(1U)

#define A_TP_INGRESS_CONFIG 0x141

#define S_OPAQUE_TYPE    16
#define M_OPAQUE_TYPE    0xffffU
#define V_OPAQUE_TYPE(x) ((x) << S_OPAQUE_TYPE)
#define G_OPAQUE_TYPE(x) (((x) >> S_OPAQUE_TYPE) & M_OPAQUE_TYPE)

#define S_OPAQUE_RM    15
#define V_OPAQUE_RM(x) ((x) << S_OPAQUE_RM)
#define F_OPAQUE_RM    V_OPAQUE_RM(1U)

#define S_OPAQUE_HDR_SIZE    14
#define V_OPAQUE_HDR_SIZE(x) ((x) << S_OPAQUE_HDR_SIZE)
#define F_OPAQUE_HDR_SIZE    V_OPAQUE_HDR_SIZE(1U)

#define S_OPAQUE_RM_MAC_IN_MAC    13
#define V_OPAQUE_RM_MAC_IN_MAC(x) ((x) << S_OPAQUE_RM_MAC_IN_MAC)
#define F_OPAQUE_RM_MAC_IN_MAC    V_OPAQUE_RM_MAC_IN_MAC(1U)

#define S_FCOE_TARGET    12
#define V_FCOE_TARGET(x) ((x) << S_FCOE_TARGET)
#define F_FCOE_TARGET    V_FCOE_TARGET(1U)

#define S_VNIC    11
#define V_VNIC(x) ((x) << S_VNIC)
#define F_VNIC    V_VNIC(1U)

#define S_CSUM_HAS_PSEUDO_HDR    10
#define V_CSUM_HAS_PSEUDO_HDR(x) ((x) << S_CSUM_HAS_PSEUDO_HDR)
#define F_CSUM_HAS_PSEUDO_HDR    V_CSUM_HAS_PSEUDO_HDR(1U)

#define S_RM_OVLAN    9
#define V_RM_OVLAN(x) ((x) << S_RM_OVLAN)
#define F_RM_OVLAN    V_RM_OVLAN(1U)

#define S_LOOKUPEVERYPKT    8
#define V_LOOKUPEVERYPKT(x) ((x) << S_LOOKUPEVERYPKT)
#define F_LOOKUPEVERYPKT    V_LOOKUPEVERYPKT(1U)

#define S_IPV6_EXT_HDR_SKIP    0
#define M_IPV6_EXT_HDR_SKIP    0xffU
#define V_IPV6_EXT_HDR_SKIP(x) ((x) << S_IPV6_EXT_HDR_SKIP)
#define G_IPV6_EXT_HDR_SKIP(x) (((x) >> S_IPV6_EXT_HDR_SKIP) & M_IPV6_EXT_HDR_SKIP)

#define S_FRAG_LEN_MOD8_COMPAT    12
#define V_FRAG_LEN_MOD8_COMPAT(x) ((x) << S_FRAG_LEN_MOD8_COMPAT)
#define F_FRAG_LEN_MOD8_COMPAT    V_FRAG_LEN_MOD8_COMPAT(1U)

#define S_USE_ENC_IDX    13
#define V_USE_ENC_IDX(x) ((x) << S_USE_ENC_IDX)
#define F_USE_ENC_IDX    V_USE_ENC_IDX(1U)

#define A_TP_ESIDE_CONFIG 0x160

#define S_VNI_EN    26
#define V_VNI_EN(x) ((x) << S_VNI_EN)
#define F_VNI_EN    V_VNI_EN(1U)

#define S_ENC_RX_EN    25
#define V_ENC_RX_EN(x) ((x) << S_ENC_RX_EN)
#define F_ENC_RX_EN    V_ENC_RX_EN(1U)

#define S_TNL_LKP_INNER_SEL    24
#define V_TNL_LKP_INNER_SEL(x) ((x) << S_TNL_LKP_INNER_SEL)
#define F_TNL_LKP_INNER_SEL    V_TNL_LKP_INNER_SEL(1U)

#define S_ROCEV2UDPPORT    0
#define M_ROCEV2UDPPORT    0xffffU
#define V_ROCEV2UDPPORT(x) ((x) << S_ROCEV2UDPPORT)
#define G_ROCEV2UDPPORT(x) (((x) >> S_ROCEV2UDPPORT) & M_ROCEV2UDPPORT)

#define A_TP_DBG_CSIDE_RX0 0x230

#define S_CRXSOPCNT    28
#define M_CRXSOPCNT    0xfU
#define V_CRXSOPCNT(x) ((x) << S_CRXSOPCNT)
#define G_CRXSOPCNT(x) (((x) >> S_CRXSOPCNT) & M_CRXSOPCNT)

#define S_CRXEOPCNT    24
#define M_CRXEOPCNT    0xfU
#define V_CRXEOPCNT(x) ((x) << S_CRXEOPCNT)
#define G_CRXEOPCNT(x) (((x) >> S_CRXEOPCNT) & M_CRXEOPCNT)

#define S_CRXPLDSOPCNT    20
#define M_CRXPLDSOPCNT    0xfU
#define V_CRXPLDSOPCNT(x) ((x) << S_CRXPLDSOPCNT)
#define G_CRXPLDSOPCNT(x) (((x) >> S_CRXPLDSOPCNT) & M_CRXPLDSOPCNT)

#define S_CRXPLDEOPCNT    16
#define M_CRXPLDEOPCNT    0xfU
#define V_CRXPLDEOPCNT(x) ((x) << S_CRXPLDEOPCNT)
#define G_CRXPLDEOPCNT(x) (((x) >> S_CRXPLDEOPCNT) & M_CRXPLDEOPCNT)

#define S_CRXARBSOPCNT    12
#define M_CRXARBSOPCNT    0xfU
#define V_CRXARBSOPCNT(x) ((x) << S_CRXARBSOPCNT)
#define G_CRXARBSOPCNT(x) (((x) >> S_CRXARBSOPCNT) & M_CRXARBSOPCNT)

#define S_CRXARBEOPCNT    8
#define M_CRXARBEOPCNT    0xfU
#define V_CRXARBEOPCNT(x) ((x) << S_CRXARBEOPCNT)
#define G_CRXARBEOPCNT(x) (((x) >> S_CRXARBEOPCNT) & M_CRXARBEOPCNT)

#define S_CRXCPLSOPCNT    4
#define M_CRXCPLSOPCNT    0xfU
#define V_CRXCPLSOPCNT(x) ((x) << S_CRXCPLSOPCNT)
#define G_CRXCPLSOPCNT(x) (((x) >> S_CRXCPLSOPCNT) & M_CRXCPLSOPCNT)

#define S_CRXCPLEOPCNT    0
#define M_CRXCPLEOPCNT    0xfU
#define V_CRXCPLEOPCNT(x) ((x) << S_CRXCPLEOPCNT)
#define G_CRXCPLEOPCNT(x) (((x) >> S_CRXCPLEOPCNT) & M_CRXCPLEOPCNT)

#define A_TP_DBG_CSIDE_RX1 0x231
#define A_TP_DBG_CSIDE_RX2 0x232
#define A_TP_DBG_CSIDE_RX3 0x233
#define A_TP_DBG_CSIDE_TX0 0x234

#define S_TXSOPCNT    28
#define M_TXSOPCNT    0xfU
#define V_TXSOPCNT(x) ((x) << S_TXSOPCNT)
#define G_TXSOPCNT(x) (((x) >> S_TXSOPCNT) & M_TXSOPCNT)

#define S_TXEOPCNT    24
#define M_TXEOPCNT    0xfU
#define V_TXEOPCNT(x) ((x) << S_TXEOPCNT)
#define G_TXEOPCNT(x) (((x) >> S_TXEOPCNT) & M_TXEOPCNT)

#define S_TXPLDSOPCNT    20
#define M_TXPLDSOPCNT    0xfU
#define V_TXPLDSOPCNT(x) ((x) << S_TXPLDSOPCNT)
#define G_TXPLDSOPCNT(x) (((x) >> S_TXPLDSOPCNT) & M_TXPLDSOPCNT)

#define S_TXPLDEOPCNT    16
#define M_TXPLDEOPCNT    0xfU
#define V_TXPLDEOPCNT(x) ((x) << S_TXPLDEOPCNT)
#define G_TXPLDEOPCNT(x) (((x) >> S_TXPLDEOPCNT) & M_TXPLDEOPCNT)

#define S_TXARBSOPCNT    12
#define M_TXARBSOPCNT    0xfU
#define V_TXARBSOPCNT(x) ((x) << S_TXARBSOPCNT)
#define G_TXARBSOPCNT(x) (((x) >> S_TXARBSOPCNT) & M_TXARBSOPCNT)

#define S_TXARBEOPCNT    8
#define M_TXARBEOPCNT    0xfU
#define V_TXARBEOPCNT(x) ((x) << S_TXARBEOPCNT)
#define G_TXARBEOPCNT(x) (((x) >> S_TXARBEOPCNT) & M_TXARBEOPCNT)

#define S_TXCPLSOPCNT    4
#define M_TXCPLSOPCNT    0xfU
#define V_TXCPLSOPCNT(x) ((x) << S_TXCPLSOPCNT)
#define G_TXCPLSOPCNT(x) (((x) >> S_TXCPLSOPCNT) & M_TXCPLSOPCNT)

#define S_TXCPLEOPCNT    0
#define M_TXCPLEOPCNT    0xfU
#define V_TXCPLEOPCNT(x) ((x) << S_TXCPLEOPCNT)
#define G_TXCPLEOPCNT(x) (((x) >> S_TXCPLEOPCNT) & M_TXCPLEOPCNT)

#define A_TP_DBG_CSIDE_TX1 0x235
#define A_TP_DBG_CSIDE_TX2 0x236
#define A_TP_DBG_CSIDE_TX3 0x237
#define A_TP_MIB_MAC_IN_ERR_0 0x0
#define A_TP_MIB_MAC_IN_ERR_1 0x1
#define A_TP_MIB_MAC_IN_ERR_2 0x2
#define A_TP_MIB_MAC_IN_ERR_3 0x3
#define A_TP_MIB_HDR_IN_ERR_0 0x4
#define A_TP_MIB_HDR_IN_ERR_1 0x5
#define A_TP_MIB_HDR_IN_ERR_2 0x6
#define A_TP_MIB_HDR_IN_ERR_3 0x7
#define A_TP_MIB_TCP_IN_ERR_0 0x8
#define A_TP_MIB_TCP_IN_ERR_1 0x9
#define A_TP_MIB_TCP_IN_ERR_2 0xa
#define A_TP_MIB_TCP_IN_ERR_3 0xb
#define A_TP_MIB_TCP_OUT_RST 0xc
#define A_TP_MIB_TCP_IN_SEG_HI 0x10
#define A_TP_MIB_TCP_IN_SEG_LO 0x11
#define A_TP_MIB_TCP_OUT_SEG_HI 0x12
#define A_TP_MIB_TCP_OUT_SEG_LO 0x13
#define A_TP_MIB_TCP_RXT_SEG_HI 0x14
#define A_TP_MIB_TCP_RXT_SEG_LO 0x15
#define A_TP_MIB_TNL_CNG_DROP_0 0x18
#define A_TP_MIB_TNL_CNG_DROP_1 0x19
#define A_TP_MIB_TNL_CNG_DROP_2 0x1a
#define A_TP_MIB_TNL_CNG_DROP_3 0x1b
#define A_TP_MIB_OFD_CHN_DROP_0 0x1c
#define A_TP_MIB_OFD_CHN_DROP_1 0x1d
#define A_TP_MIB_OFD_CHN_DROP_2 0x1e
#define A_TP_MIB_OFD_CHN_DROP_3 0x1f
#define A_TP_MIB_TNL_OUT_PKT_0 0x20
#define A_TP_MIB_TNL_OUT_PKT_1 0x21
#define A_TP_MIB_TNL_OUT_PKT_2 0x22
#define A_TP_MIB_TNL_OUT_PKT_3 0x23
#define A_TP_MIB_TNL_IN_PKT_0 0x24
#define A_TP_MIB_TNL_IN_PKT_1 0x25
#define A_TP_MIB_TNL_IN_PKT_2 0x26
#define A_TP_MIB_TNL_IN_PKT_3 0x27
#define A_TP_MIB_TCP_V6IN_ERR_0 0x28
#define A_TP_MIB_TCP_V6IN_ERR_1 0x29
#define A_TP_MIB_TCP_V6IN_ERR_2 0x2a
#define A_TP_MIB_TCP_V6IN_ERR_3 0x2b
#define A_TP_MIB_TCP_V6OUT_RST 0x2c
#define A_TP_MIB_TCP_V6IN_SEG_HI 0x30
#define A_TP_MIB_TCP_V6IN_SEG_LO 0x31
#define A_TP_MIB_TCP_V6OUT_SEG_HI 0x32
#define A_TP_MIB_TCP_V6OUT_SEG_LO 0x33
#define A_TP_MIB_TCP_V6RXT_SEG_HI 0x34
#define A_TP_MIB_TCP_V6RXT_SEG_LO 0x35
#define A_TP_MIB_OFD_ARP_DROP 0x36
#define A_TP_MIB_OFD_DFR_DROP 0x37
#define A_TP_MIB_CPL_IN_REQ_0 0x38
#define A_TP_MIB_CPL_IN_REQ_1 0x39
#define A_TP_MIB_CPL_IN_REQ_2 0x3a
#define A_TP_MIB_CPL_IN_REQ_3 0x3b
#define A_TP_MIB_CPL_OUT_RSP_0 0x3c
#define A_TP_MIB_CPL_OUT_RSP_1 0x3d
#define A_TP_MIB_CPL_OUT_RSP_2 0x3e
#define A_TP_MIB_CPL_OUT_RSP_3 0x3f
#define A_TP_MIB_TNL_LPBK_0 0x40
#define A_TP_MIB_TNL_LPBK_1 0x41
#define A_TP_MIB_TNL_LPBK_2 0x42
#define A_TP_MIB_TNL_LPBK_3 0x43
#define A_TP_MIB_TNL_DROP_0 0x44
#define A_TP_MIB_TNL_DROP_1 0x45
#define A_TP_MIB_TNL_DROP_2 0x46
#define A_TP_MIB_TNL_DROP_3 0x47
#define A_TP_MIB_FCOE_DDP_0 0x48
#define A_TP_MIB_FCOE_DDP_1 0x49
#define A_TP_MIB_FCOE_DDP_2 0x4a
#define A_TP_MIB_FCOE_DDP_3 0x4b
#define A_TP_MIB_FCOE_DROP_0 0x4c
#define A_TP_MIB_FCOE_DROP_1 0x4d
#define A_TP_MIB_FCOE_DROP_2 0x4e
#define A_TP_MIB_FCOE_DROP_3 0x4f
#define A_TP_MIB_FCOE_BYTE_0_HI 0x50
#define A_TP_MIB_FCOE_BYTE_0_LO 0x51
#define A_TP_MIB_FCOE_BYTE_1_HI 0x52
#define A_TP_MIB_FCOE_BYTE_1_LO 0x53
#define A_TP_MIB_FCOE_BYTE_2_HI 0x54
#define A_TP_MIB_FCOE_BYTE_2_LO 0x55
#define A_TP_MIB_FCOE_BYTE_3_HI 0x56
#define A_TP_MIB_FCOE_BYTE_3_LO 0x57
#define A_TP_MIB_OFD_VLN_DROP_0 0x58
#define A_TP_MIB_OFD_VLN_DROP_1 0x59
#define A_TP_MIB_OFD_VLN_DROP_2 0x5a
#define A_TP_MIB_OFD_VLN_DROP_3 0x5b
#define A_TP_MIB_USM_PKTS 0x5c
#define A_TP_MIB_USM_DROP 0x5d
#define A_TP_MIB_USM_BYTES_HI 0x5e
#define A_TP_MIB_USM_BYTES_LO 0x5f
#define A_TP_MIB_TID_DEL 0x60
#define A_TP_MIB_TID_INV 0x61
#define A_TP_MIB_TID_ACT 0x62
#define A_TP_MIB_TID_PAS 0x63
#define A_TP_MIB_RQE_DFR_PKT 0x64
#define A_TP_MIB_RQE_DFR_MOD 0x65
#define A_TP_MIB_CPL_OUT_ERR_0 0x68
#define A_TP_MIB_CPL_OUT_ERR_1 0x69
#define A_TP_MIB_CPL_OUT_ERR_2 0x6a
#define A_TP_MIB_CPL_OUT_ERR_3 0x6b
#define A_TP_MIB_ENG_LINE_0 0x6c
#define A_TP_MIB_ENG_LINE_1 0x6d
#define A_TP_MIB_ENG_LINE_2 0x6e
#define A_TP_MIB_ENG_LINE_3 0x6f
#define A_TP_MIB_TNL_ERR_0 0x70
#define A_TP_MIB_TNL_ERR_1 0x71
#define A_TP_MIB_TNL_ERR_2 0x72
#define A_TP_MIB_TNL_ERR_3 0x73

/* registers for module ULP_TX */
#define ULP_TX_BASE_ADDR 0x8dc0

#define A_ULP_TX_INT_CAUSE 0x8dcc

#define S_PBL_BOUND_ERR_CH3    31
#define V_PBL_BOUND_ERR_CH3(x) ((x) << S_PBL_BOUND_ERR_CH3)
#define F_PBL_BOUND_ERR_CH3    V_PBL_BOUND_ERR_CH3(1U)

#define S_PBL_BOUND_ERR_CH2    30
#define V_PBL_BOUND_ERR_CH2(x) ((x) << S_PBL_BOUND_ERR_CH2)
#define F_PBL_BOUND_ERR_CH2    V_PBL_BOUND_ERR_CH2(1U)

#define S_PBL_BOUND_ERR_CH1    29
#define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1)
#define F_PBL_BOUND_ERR_CH1    V_PBL_BOUND_ERR_CH1(1U)

#define S_PBL_BOUND_ERR_CH0    28
#define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0)
#define F_PBL_BOUND_ERR_CH0    V_PBL_BOUND_ERR_CH0(1U)

#define S_SGE2ULP_FIFO_PERR_SET3    27
#define V_SGE2ULP_FIFO_PERR_SET3(x) ((x) << S_SGE2ULP_FIFO_PERR_SET3)
#define F_SGE2ULP_FIFO_PERR_SET3    V_SGE2ULP_FIFO_PERR_SET3(1U)

#define S_SGE2ULP_FIFO_PERR_SET2    26
#define V_SGE2ULP_FIFO_PERR_SET2(x) ((x) << S_SGE2ULP_FIFO_PERR_SET2)
#define F_SGE2ULP_FIFO_PERR_SET2    V_SGE2ULP_FIFO_PERR_SET2(1U)

#define S_SGE2ULP_FIFO_PERR_SET1    25
#define V_SGE2ULP_FIFO_PERR_SET1(x) ((x) << S_SGE2ULP_FIFO_PERR_SET1)
#define F_SGE2ULP_FIFO_PERR_SET1    V_SGE2ULP_FIFO_PERR_SET1(1U)

#define S_SGE2ULP_FIFO_PERR_SET0    24
#define V_SGE2ULP_FIFO_PERR_SET0(x) ((x) << S_SGE2ULP_FIFO_PERR_SET0)
#define F_SGE2ULP_FIFO_PERR_SET0    V_SGE2ULP_FIFO_PERR_SET0(1U)

#define S_CIM2ULP_FIFO_PERR_SET3    23
#define V_CIM2ULP_FIFO_PERR_SET3(x) ((x) << S_CIM2ULP_FIFO_PERR_SET3)
#define F_CIM2ULP_FIFO_PERR_SET3    V_CIM2ULP_FIFO_PERR_SET3(1U)

#define S_CIM2ULP_FIFO_PERR_SET2    22
#define V_CIM2ULP_FIFO_PERR_SET2(x) ((x) << S_CIM2ULP_FIFO_PERR_SET2)
#define F_CIM2ULP_FIFO_PERR_SET2    V_CIM2ULP_FIFO_PERR_SET2(1U)

#define S_CIM2ULP_FIFO_PERR_SET1    21
#define V_CIM2ULP_FIFO_PERR_SET1(x) ((x) << S_CIM2ULP_FIFO_PERR_SET1)
#define F_CIM2ULP_FIFO_PERR_SET1    V_CIM2ULP_FIFO_PERR_SET1(1U)

#define S_CIM2ULP_FIFO_PERR_SET0    20
#define V_CIM2ULP_FIFO_PERR_SET0(x) ((x) << S_CIM2ULP_FIFO_PERR_SET0)
#define F_CIM2ULP_FIFO_PERR_SET0    V_CIM2ULP_FIFO_PERR_SET0(1U)

#define S_CQE_FIFO_PERR_SET3    19
#define V_CQE_FIFO_PERR_SET3(x) ((x) << S_CQE_FIFO_PERR_SET3)
#define F_CQE_FIFO_PERR_SET3    V_CQE_FIFO_PERR_SET3(1U)

#define S_CQE_FIFO_PERR_SET2    18
#define V_CQE_FIFO_PERR_SET2(x) ((x) << S_CQE_FIFO_PERR_SET2)
#define F_CQE_FIFO_PERR_SET2    V_CQE_FIFO_PERR_SET2(1U)

#define S_CQE_FIFO_PERR_SET1    17
#define V_CQE_FIFO_PERR_SET1(x) ((x) << S_CQE_FIFO_PERR_SET1)
#define F_CQE_FIFO_PERR_SET1    V_CQE_FIFO_PERR_SET1(1U)

#define S_CQE_FIFO_PERR_SET0    16
#define V_CQE_FIFO_PERR_SET0(x) ((x) << S_CQE_FIFO_PERR_SET0)
#define F_CQE_FIFO_PERR_SET0    V_CQE_FIFO_PERR_SET0(1U)

#define S_PBL_FIFO_PERR_SET3    15
#define V_PBL_FIFO_PERR_SET3(x) ((x) << S_PBL_FIFO_PERR_SET3)
#define F_PBL_FIFO_PERR_SET3    V_PBL_FIFO_PERR_SET3(1U)

#define S_PBL_FIFO_PERR_SET2    14
#define V_PBL_FIFO_PERR_SET2(x) ((x) << S_PBL_FIFO_PERR_SET2)
#define F_PBL_FIFO_PERR_SET2    V_PBL_FIFO_PERR_SET2(1U)

#define S_PBL_FIFO_PERR_SET1    13
#define V_PBL_FIFO_PERR_SET1(x) ((x) << S_PBL_FIFO_PERR_SET1)
#define F_PBL_FIFO_PERR_SET1    V_PBL_FIFO_PERR_SET1(1U)

#define S_PBL_FIFO_PERR_SET0    12
#define V_PBL_FIFO_PERR_SET0(x) ((x) << S_PBL_FIFO_PERR_SET0)
#define F_PBL_FIFO_PERR_SET0    V_PBL_FIFO_PERR_SET0(1U)

#define S_CMD_FIFO_PERR_SET3    11
#define V_CMD_FIFO_PERR_SET3(x) ((x) << S_CMD_FIFO_PERR_SET3)
#define F_CMD_FIFO_PERR_SET3    V_CMD_FIFO_PERR_SET3(1U)

#define S_CMD_FIFO_PERR_SET2    10
#define V_CMD_FIFO_PERR_SET2(x) ((x) << S_CMD_FIFO_PERR_SET2)
#define F_CMD_FIFO_PERR_SET2    V_CMD_FIFO_PERR_SET2(1U)

#define S_CMD_FIFO_PERR_SET1    9
#define V_CMD_FIFO_PERR_SET1(x) ((x) << S_CMD_FIFO_PERR_SET1)
#define F_CMD_FIFO_PERR_SET1    V_CMD_FIFO_PERR_SET1(1U)

#define S_CMD_FIFO_PERR_SET0    8
#define V_CMD_FIFO_PERR_SET0(x) ((x) << S_CMD_FIFO_PERR_SET0)
#define F_CMD_FIFO_PERR_SET0    V_CMD_FIFO_PERR_SET0(1U)

#define S_LSO_HDR_SRAM_PERR_SET3    7
#define V_LSO_HDR_SRAM_PERR_SET3(x) ((x) << S_LSO_HDR_SRAM_PERR_SET3)
#define F_LSO_HDR_SRAM_PERR_SET3    V_LSO_HDR_SRAM_PERR_SET3(1U)

#define S_LSO_HDR_SRAM_PERR_SET2    6
#define V_LSO_HDR_SRAM_PERR_SET2(x) ((x) << S_LSO_HDR_SRAM_PERR_SET2)
#define F_LSO_HDR_SRAM_PERR_SET2    V_LSO_HDR_SRAM_PERR_SET2(1U)

#define S_LSO_HDR_SRAM_PERR_SET1    5
#define V_LSO_HDR_SRAM_PERR_SET1(x) ((x) << S_LSO_HDR_SRAM_PERR_SET1)
#define F_LSO_HDR_SRAM_PERR_SET1    V_LSO_HDR_SRAM_PERR_SET1(1U)

#define S_LSO_HDR_SRAM_PERR_SET0    4
#define V_LSO_HDR_SRAM_PERR_SET0(x) ((x) << S_LSO_HDR_SRAM_PERR_SET0)
#define F_LSO_HDR_SRAM_PERR_SET0    V_LSO_HDR_SRAM_PERR_SET0(1U)

#define S_IMM_DATA_PERR_SET_CH3    3
#define V_IMM_DATA_PERR_SET_CH3(x) ((x) << S_IMM_DATA_PERR_SET_CH3)
#define F_IMM_DATA_PERR_SET_CH3    V_IMM_DATA_PERR_SET_CH3(1U)

#define S_IMM_DATA_PERR_SET_CH2    2
#define V_IMM_DATA_PERR_SET_CH2(x) ((x) << S_IMM_DATA_PERR_SET_CH2)
#define F_IMM_DATA_PERR_SET_CH2    V_IMM_DATA_PERR_SET_CH2(1U)

#define S_IMM_DATA_PERR_SET_CH1    1
#define V_IMM_DATA_PERR_SET_CH1(x) ((x) << S_IMM_DATA_PERR_SET_CH1)
#define F_IMM_DATA_PERR_SET_CH1    V_IMM_DATA_PERR_SET_CH1(1U)

#define S_IMM_DATA_PERR_SET_CH0    0
#define V_IMM_DATA_PERR_SET_CH0(x) ((x) << S_IMM_DATA_PERR_SET_CH0)
#define F_IMM_DATA_PERR_SET_CH0    V_IMM_DATA_PERR_SET_CH0(1U)

#define A_ULP_TX_TPT_LLIMIT 0x8dd4
#define A_ULP_TX_TPT_ULIMIT 0x8dd8
#define A_ULP_TX_PBL_LLIMIT 0x8ddc
#define A_ULP_TX_PBL_ULIMIT 0x8de0
#define A_ULP_TX_ERR_TABLE_BASE 0x8e04
#define A_ULP_TX_ULP2TP_BIST_CMD 0x8e30
#define A_ULP_TX_ULP2TP_BIST_ERROR_CNT 0x8e34
#define A_ULP_TX_FPGA_CMD_CTRL 0x8e38
#define A_ULP_TX_FPGA_CMD_0 0x8e3c
#define A_ULP_TX_FPGA_CMD_1 0x8e40
#define A_ULP_TX_FPGA_CMD_2 0x8e44
#define A_ULP_TX_FPGA_CMD_3 0x8e48
#define A_ULP_TX_FPGA_CMD_4 0x8e4c
#define A_ULP_TX_FPGA_CMD_5 0x8e50
#define A_ULP_TX_FPGA_CMD_6 0x8e54
#define A_ULP_TX_FPGA_CMD_7 0x8e58
#define A_ULP_TX_FPGA_CMD_8 0x8e5c
#define A_ULP_TX_FPGA_CMD_9 0x8e60
#define A_ULP_TX_FPGA_CMD_10 0x8e64
#define A_ULP_TX_FPGA_CMD_11 0x8e68
#define A_ULP_TX_FPGA_CMD_12 0x8e6c
#define A_ULP_TX_FPGA_CMD_13 0x8e70
#define A_ULP_TX_FPGA_CMD_14 0x8e74
#define A_ULP_TX_FPGA_CMD_15 0x8e78
#define A_ULP_TX_INT_CAUSE_2 0x8e80

#define S_SMARBT2ULP_DATA_PERR_SET    12
#define V_SMARBT2ULP_DATA_PERR_SET(x) ((x) << S_SMARBT2ULP_DATA_PERR_SET)
#define F_SMARBT2ULP_DATA_PERR_SET    V_SMARBT2ULP_DATA_PERR_SET(1U)

#define S_ULP2TP_DATA_PERR_SET    11
#define V_ULP2TP_DATA_PERR_SET(x) ((x) << S_ULP2TP_DATA_PERR_SET)
#define F_ULP2TP_DATA_PERR_SET    V_ULP2TP_DATA_PERR_SET(1U)

#define S_MA2ULP_DATA_PERR_SET    10
#define V_MA2ULP_DATA_PERR_SET(x) ((x) << S_MA2ULP_DATA_PERR_SET)
#define F_MA2ULP_DATA_PERR_SET    V_MA2ULP_DATA_PERR_SET(1U)

#define S_SGE2ULP_DATA_PERR_SET    9
#define V_SGE2ULP_DATA_PERR_SET(x) ((x) << S_SGE2ULP_DATA_PERR_SET)
#define F_SGE2ULP_DATA_PERR_SET    V_SGE2ULP_DATA_PERR_SET(1U)

#define S_CIM2ULP_DATA_PERR_SET    8
#define V_CIM2ULP_DATA_PERR_SET(x) ((x) << S_CIM2ULP_DATA_PERR_SET)
#define F_CIM2ULP_DATA_PERR_SET    V_CIM2ULP_DATA_PERR_SET(1U)

#define S_FSO_HDR_SRAM_PERR_SET3    7
#define V_FSO_HDR_SRAM_PERR_SET3(x) ((x) << S_FSO_HDR_SRAM_PERR_SET3)
#define F_FSO_HDR_SRAM_PERR_SET3    V_FSO_HDR_SRAM_PERR_SET3(1U)

#define S_FSO_HDR_SRAM_PERR_SET2    6
#define V_FSO_HDR_SRAM_PERR_SET2(x) ((x) << S_FSO_HDR_SRAM_PERR_SET2)
#define F_FSO_HDR_SRAM_PERR_SET2    V_FSO_HDR_SRAM_PERR_SET2(1U)

#define S_FSO_HDR_SRAM_PERR_SET1    5
#define V_FSO_HDR_SRAM_PERR_SET1(x) ((x) << S_FSO_HDR_SRAM_PERR_SET1)
#define F_FSO_HDR_SRAM_PERR_SET1    V_FSO_HDR_SRAM_PERR_SET1(1U)

#define S_FSO_HDR_SRAM_PERR_SET0    4
#define V_FSO_HDR_SRAM_PERR_SET0(x) ((x) << S_FSO_HDR_SRAM_PERR_SET0)
#define F_FSO_HDR_SRAM_PERR_SET0    V_FSO_HDR_SRAM_PERR_SET0(1U)

#define S_T10_PI_SRAM_PERR_SET3    3
#define V_T10_PI_SRAM_PERR_SET3(x) ((x) << S_T10_PI_SRAM_PERR_SET3)
#define F_T10_PI_SRAM_PERR_SET3    V_T10_PI_SRAM_PERR_SET3(1U)

#define S_T10_PI_SRAM_PERR_SET2    2
#define V_T10_PI_SRAM_PERR_SET2(x) ((x) << S_T10_PI_SRAM_PERR_SET2)
#define F_T10_PI_SRAM_PERR_SET2    V_T10_PI_SRAM_PERR_SET2(1U)

#define S_T10_PI_SRAM_PERR_SET1    1
#define V_T10_PI_SRAM_PERR_SET1(x) ((x) << S_T10_PI_SRAM_PERR_SET1)
#define F_T10_PI_SRAM_PERR_SET1    V_T10_PI_SRAM_PERR_SET1(1U)

#define S_T10_PI_SRAM_PERR_SET0    0
#define V_T10_PI_SRAM_PERR_SET0(x) ((x) << S_T10_PI_SRAM_PERR_SET0)
#define F_T10_PI_SRAM_PERR_SET0    V_T10_PI_SRAM_PERR_SET0(1U)

#define S_EDMA_IN_FIFO_PERR_SET3    31
#define V_EDMA_IN_FIFO_PERR_SET3(x) ((x) << S_EDMA_IN_FIFO_PERR_SET3)
#define F_EDMA_IN_FIFO_PERR_SET3    V_EDMA_IN_FIFO_PERR_SET3(1U)

#define S_EDMA_IN_FIFO_PERR_SET2    30
#define V_EDMA_IN_FIFO_PERR_SET2(x) ((x) << S_EDMA_IN_FIFO_PERR_SET2)
#define F_EDMA_IN_FIFO_PERR_SET2    V_EDMA_IN_FIFO_PERR_SET2(1U)

#define S_EDMA_IN_FIFO_PERR_SET1    29
#define V_EDMA_IN_FIFO_PERR_SET1(x) ((x) << S_EDMA_IN_FIFO_PERR_SET1)
#define F_EDMA_IN_FIFO_PERR_SET1    V_EDMA_IN_FIFO_PERR_SET1(1U)

#define S_EDMA_IN_FIFO_PERR_SET0    28
#define V_EDMA_IN_FIFO_PERR_SET0(x) ((x) << S_EDMA_IN_FIFO_PERR_SET0)
#define F_EDMA_IN_FIFO_PERR_SET0    V_EDMA_IN_FIFO_PERR_SET0(1U)

#define S_ALIGN_CTL_FIFO_PERR_SET3    27
#define V_ALIGN_CTL_FIFO_PERR_SET3(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET3)
#define F_ALIGN_CTL_FIFO_PERR_SET3    V_ALIGN_CTL_FIFO_PERR_SET3(1U)

#define S_ALIGN_CTL_FIFO_PERR_SET2    26
#define V_ALIGN_CTL_FIFO_PERR_SET2(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET2)
#define F_ALIGN_CTL_FIFO_PERR_SET2    V_ALIGN_CTL_FIFO_PERR_SET2(1U)

#define S_ALIGN_CTL_FIFO_PERR_SET1    25
#define V_ALIGN_CTL_FIFO_PERR_SET1(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET1)
#define F_ALIGN_CTL_FIFO_PERR_SET1    V_ALIGN_CTL_FIFO_PERR_SET1(1U)

#define S_ALIGN_CTL_FIFO_PERR_SET0    24
#define V_ALIGN_CTL_FIFO_PERR_SET0(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET0)
#define F_ALIGN_CTL_FIFO_PERR_SET0    V_ALIGN_CTL_FIFO_PERR_SET0(1U)

#define S_SGE_FIFO_PERR_SET3    23
#define V_SGE_FIFO_PERR_SET3(x) ((x) << S_SGE_FIFO_PERR_SET3)
#define F_SGE_FIFO_PERR_SET3    V_SGE_FIFO_PERR_SET3(1U)

#define S_SGE_FIFO_PERR_SET2    22
#define V_SGE_FIFO_PERR_SET2(x) ((x) << S_SGE_FIFO_PERR_SET2)
#define F_SGE_FIFO_PERR_SET2    V_SGE_FIFO_PERR_SET2(1U)

#define S_SGE_FIFO_PERR_SET1    21
#define V_SGE_FIFO_PERR_SET1(x) ((x) << S_SGE_FIFO_PERR_SET1)
#define F_SGE_FIFO_PERR_SET1    V_SGE_FIFO_PERR_SET1(1U)

#define S_SGE_FIFO_PERR_SET0    20
#define V_SGE_FIFO_PERR_SET0(x) ((x) << S_SGE_FIFO_PERR_SET0)
#define F_SGE_FIFO_PERR_SET0    V_SGE_FIFO_PERR_SET0(1U)

#define S_STAG_FIFO_PERR_SET3    19
#define V_STAG_FIFO_PERR_SET3(x) ((x) << S_STAG_FIFO_PERR_SET3)
#define F_STAG_FIFO_PERR_SET3    V_STAG_FIFO_PERR_SET3(1U)

#define S_STAG_FIFO_PERR_SET2    18
#define V_STAG_FIFO_PERR_SET2(x) ((x) << S_STAG_FIFO_PERR_SET2)
#define F_STAG_FIFO_PERR_SET2    V_STAG_FIFO_PERR_SET2(1U)

#define S_STAG_FIFO_PERR_SET1    17
#define V_STAG_FIFO_PERR_SET1(x) ((x) << S_STAG_FIFO_PERR_SET1)
#define F_STAG_FIFO_PERR_SET1    V_STAG_FIFO_PERR_SET1(1U)

#define S_STAG_FIFO_PERR_SET0    16
#define V_STAG_FIFO_PERR_SET0(x) ((x) << S_STAG_FIFO_PERR_SET0)
#define F_STAG_FIFO_PERR_SET0    V_STAG_FIFO_PERR_SET0(1U)

#define S_MAP_FIFO_PERR_SET3    15
#define V_MAP_FIFO_PERR_SET3(x) ((x) << S_MAP_FIFO_PERR_SET3)
#define F_MAP_FIFO_PERR_SET3    V_MAP_FIFO_PERR_SET3(1U)

#define S_MAP_FIFO_PERR_SET2    14
#define V_MAP_FIFO_PERR_SET2(x) ((x) << S_MAP_FIFO_PERR_SET2)
#define F_MAP_FIFO_PERR_SET2    V_MAP_FIFO_PERR_SET2(1U)

#define S_MAP_FIFO_PERR_SET1    13
#define V_MAP_FIFO_PERR_SET1(x) ((x) << S_MAP_FIFO_PERR_SET1)
#define F_MAP_FIFO_PERR_SET1    V_MAP_FIFO_PERR_SET1(1U)

#define S_MAP_FIFO_PERR_SET0    12
#define V_MAP_FIFO_PERR_SET0(x) ((x) << S_MAP_FIFO_PERR_SET0)
#define F_MAP_FIFO_PERR_SET0    V_MAP_FIFO_PERR_SET0(1U)

#define S_DMA_FIFO_PERR_SET3    11
#define V_DMA_FIFO_PERR_SET3(x) ((x) << S_DMA_FIFO_PERR_SET3)
#define F_DMA_FIFO_PERR_SET3    V_DMA_FIFO_PERR_SET3(1U)

#define S_DMA_FIFO_PERR_SET2    10
#define V_DMA_FIFO_PERR_SET2(x) ((x) << S_DMA_FIFO_PERR_SET2)
#define F_DMA_FIFO_PERR_SET2    V_DMA_FIFO_PERR_SET2(1U)

#define S_DMA_FIFO_PERR_SET1    9
#define V_DMA_FIFO_PERR_SET1(x) ((x) << S_DMA_FIFO_PERR_SET1)
#define F_DMA_FIFO_PERR_SET1    V_DMA_FIFO_PERR_SET1(1U)

#define S_DMA_FIFO_PERR_SET0    8
#define V_DMA_FIFO_PERR_SET0(x) ((x) << S_DMA_FIFO_PERR_SET0)
#define F_DMA_FIFO_PERR_SET0    V_DMA_FIFO_PERR_SET0(1U)

#define A_ULP_TX_SE_CNT_CH0 0x8ea8

#define S_SOP_CNT_ULP2TP    28
#define M_SOP_CNT_ULP2TP    0xfU
#define V_SOP_CNT_ULP2TP(x) ((x) << S_SOP_CNT_ULP2TP)
#define G_SOP_CNT_ULP2TP(x) (((x) >> S_SOP_CNT_ULP2TP) & M_SOP_CNT_ULP2TP)

#define S_EOP_CNT_ULP2TP    24
#define M_EOP_CNT_ULP2TP    0xfU
#define V_EOP_CNT_ULP2TP(x) ((x) << S_EOP_CNT_ULP2TP)
#define G_EOP_CNT_ULP2TP(x) (((x) >> S_EOP_CNT_ULP2TP) & M_EOP_CNT_ULP2TP)

#define S_SOP_CNT_LSO_IN    20
#define M_SOP_CNT_LSO_IN    0xfU
#define V_SOP_CNT_LSO_IN(x) ((x) << S_SOP_CNT_LSO_IN)
#define G_SOP_CNT_LSO_IN(x) (((x) >> S_SOP_CNT_LSO_IN) & M_SOP_CNT_LSO_IN)

#define S_EOP_CNT_LSO_IN    16
#define M_EOP_CNT_LSO_IN    0xfU
#define V_EOP_CNT_LSO_IN(x) ((x) << S_EOP_CNT_LSO_IN)
#define G_EOP_CNT_LSO_IN(x) (((x) >> S_EOP_CNT_LSO_IN) & M_EOP_CNT_LSO_IN)

#define S_SOP_CNT_ALG_IN    12
#define M_SOP_CNT_ALG_IN    0xfU
#define V_SOP_CNT_ALG_IN(x) ((x) << S_SOP_CNT_ALG_IN)
#define G_SOP_CNT_ALG_IN(x) (((x) >> S_SOP_CNT_ALG_IN) & M_SOP_CNT_ALG_IN)

#define S_EOP_CNT_ALG_IN    8
#define M_EOP_CNT_ALG_IN    0xfU
#define V_EOP_CNT_ALG_IN(x) ((x) << S_EOP_CNT_ALG_IN)
#define G_EOP_CNT_ALG_IN(x) (((x) >> S_EOP_CNT_ALG_IN) & M_EOP_CNT_ALG_IN)

#define S_SOP_CNT_CIM2ULP    4
#define M_SOP_CNT_CIM2ULP    0xfU
#define V_SOP_CNT_CIM2ULP(x) ((x) << S_SOP_CNT_CIM2ULP)
#define G_SOP_CNT_CIM2ULP(x) (((x) >> S_SOP_CNT_CIM2ULP) & M_SOP_CNT_CIM2ULP)

#define S_EOP_CNT_CIM2ULP    0
#define M_EOP_CNT_CIM2ULP    0xfU
#define V_EOP_CNT_CIM2ULP(x) ((x) << S_EOP_CNT_CIM2ULP)
#define G_EOP_CNT_CIM2ULP(x) (((x) >> S_EOP_CNT_CIM2ULP) & M_EOP_CNT_CIM2ULP)

#define A_ULP_TX_T5_SE_CNT_CH0 0x8ea8
#define A_ULP_TX_SE_CNT_CH1 0x8eac
#define A_ULP_TX_T5_SE_CNT_CH1 0x8eac
#define A_ULP_TX_SE_CNT_CH2 0x8eb0
#define A_ULP_TX_T5_SE_CNT_CH2 0x8eb0
#define A_ULP_TX_SE_CNT_CH3 0x8eb4
#define A_ULP_TX_T5_SE_CNT_CH3 0x8eb4
#define A_ULP_TX_CSU_REVISION 0x8ebc
#define A_ULP_TX_LA_RDPTR_0 0x8ec0
#define A_ULP_TX_LA_RDDATA_0 0x8ec4
#define A_ULP_TX_LA_WRPTR_0 0x8ec8
#define A_ULP_TX_LA_RESERVED_0 0x8ecc
#define A_ULP_TX_LA_RDPTR_1 0x8ed0
#define A_ULP_TX_LA_RDDATA_1 0x8ed4
#define A_ULP_TX_LA_WRPTR_1 0x8ed8
#define A_ULP_TX_LA_RESERVED_1 0x8edc
#define A_ULP_TX_LA_RDPTR_2 0x8ee0
#define A_ULP_TX_LA_RDDATA_2 0x8ee4
#define A_ULP_TX_LA_WRPTR_2 0x8ee8
#define A_ULP_TX_LA_RESERVED_2 0x8eec
#define A_ULP_TX_LA_RDPTR_3 0x8ef0
#define A_ULP_TX_LA_RDDATA_3 0x8ef4
#define A_ULP_TX_LA_WRPTR_3 0x8ef8
#define A_ULP_TX_LA_RESERVED_3 0x8efc
#define A_ULP_TX_LA_RDPTR_4 0x8f00
#define A_ULP_TX_LA_RDDATA_4 0x8f04
#define A_ULP_TX_LA_WRPTR_4 0x8f08
#define A_ULP_TX_LA_RESERVED_4 0x8f0c
#define A_ULP_TX_LA_RDPTR_5 0x8f10
#define A_ULP_TX_LA_RDDATA_5 0x8f14
#define A_ULP_TX_LA_WRPTR_5 0x8f18
#define A_ULP_TX_LA_RESERVED_5 0x8f1c
#define A_ULP_TX_LA_RDPTR_6 0x8f20
#define A_ULP_TX_LA_RDDATA_6 0x8f24
#define A_ULP_TX_LA_WRPTR_6 0x8f28
#define A_ULP_TX_LA_RESERVED_6 0x8f2c
#define A_ULP_TX_LA_RDPTR_7 0x8f30
#define A_ULP_TX_LA_RDDATA_7 0x8f34
#define A_ULP_TX_LA_WRPTR_7 0x8f38
#define A_ULP_TX_LA_RESERVED_7 0x8f3c
#define A_ULP_TX_LA_RDPTR_8 0x8f40
#define A_ULP_TX_LA_RDDATA_8 0x8f44
#define A_ULP_TX_LA_WRPTR_8 0x8f48
#define A_ULP_TX_LA_RESERVED_8 0x8f4c
#define A_ULP_TX_LA_RDPTR_9 0x8f50
#define A_ULP_TX_LA_RDDATA_9 0x8f54
#define A_ULP_TX_LA_WRPTR_9 0x8f58
#define A_ULP_TX_LA_RESERVED_9 0x8f5c
#define A_ULP_TX_LA_RDPTR_10 0x8f60
#define A_ULP_TX_LA_RDDATA_10 0x8f64
#define A_ULP_TX_LA_WRPTR_10 0x8f68
#define A_ULP_TX_LA_RESERVED_10 0x8f6c

/* registers for module PM_RX */
#define PM_RX_BASE_ADDR 0x8fc0

#define A_PM_RX_STAT_CONFIG 0x8fc8
#define A_PM_RX_STAT_COUNT 0x8fcc
#define A_PM_RX_STAT_LSB 0x8fd0
#define A_PM_RX_DBG_CTRL 0x8fd0

#define S_OSPIWRBUSY_T5    21
#define M_OSPIWRBUSY_T5    0x3U
#define V_OSPIWRBUSY_T5(x) ((x) << S_OSPIWRBUSY_T5)
#define G_OSPIWRBUSY_T5(x) (((x) >> S_OSPIWRBUSY_T5) & M_OSPIWRBUSY_T5)

#define S_ISPIWRBUSY    17
#define M_ISPIWRBUSY    0xfU
#define V_ISPIWRBUSY(x) ((x) << S_ISPIWRBUSY)
#define G_ISPIWRBUSY(x) (((x) >> S_ISPIWRBUSY) & M_ISPIWRBUSY)

#define S_PMDBGADDR    0
#define M_PMDBGADDR    0x1ffffU
#define V_PMDBGADDR(x) ((x) << S_PMDBGADDR)
#define G_PMDBGADDR(x) (((x) >> S_PMDBGADDR) & M_PMDBGADDR)

#define A_PM_RX_STAT_MSB 0x8fd4
#define A_PM_RX_DBG_DATA 0x8fd4
#define A_PM_RX_INT_CAUSE 0x8fdc

#define S_ZERO_E_CMD_ERROR    22
#define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR)
#define F_ZERO_E_CMD_ERROR    V_ZERO_E_CMD_ERROR(1U)

#define S_IESPI0_FIFO2X_RX_FRAMING_ERROR    21
#define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
#define F_IESPI0_FIFO2X_RX_FRAMING_ERROR    V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U)

#define S_IESPI1_FIFO2X_RX_FRAMING_ERROR    20
#define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
#define F_IESPI1_FIFO2X_RX_FRAMING_ERROR    V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U)

#define S_IESPI2_FIFO2X_RX_FRAMING_ERROR    19
#define V_IESPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_FIFO2X_RX_FRAMING_ERROR)
#define F_IESPI2_FIFO2X_RX_FRAMING_ERROR    V_IESPI2_FIFO2X_RX_FRAMING_ERROR(1U)

#define S_IESPI3_FIFO2X_RX_FRAMING_ERROR    18
#define V_IESPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_FIFO2X_RX_FRAMING_ERROR)
#define F_IESPI3_FIFO2X_RX_FRAMING_ERROR    V_IESPI3_FIFO2X_RX_FRAMING_ERROR(1U)

#define S_IESPI0_RX_FRAMING_ERROR    17
#define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR)
#define F_IESPI0_RX_FRAMING_ERROR    V_IESPI0_RX_FRAMING_ERROR(1U)

#define S_IESPI1_RX_FRAMING_ERROR    16
#define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR)
#define F_IESPI1_RX_FRAMING_ERROR    V_IESPI1_RX_FRAMING_ERROR(1U)

#define S_IESPI2_RX_FRAMING_ERROR    15
#define V_IESPI2_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_RX_FRAMING_ERROR)
#define F_IESPI2_RX_FRAMING_ERROR    V_IESPI2_RX_FRAMING_ERROR(1U)

#define S_IESPI3_RX_FRAMING_ERROR    14
#define V_IESPI3_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_RX_FRAMING_ERROR)
#define F_IESPI3_RX_FRAMING_ERROR    V_IESPI3_RX_FRAMING_ERROR(1U)

#define S_IESPI0_TX_FRAMING_ERROR    13
#define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR)
#define F_IESPI0_TX_FRAMING_ERROR    V_IESPI0_TX_FRAMING_ERROR(1U)

#define S_IESPI1_TX_FRAMING_ERROR    12
#define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR)
#define F_IESPI1_TX_FRAMING_ERROR    V_IESPI1_TX_FRAMING_ERROR(1U)

#define S_IESPI2_TX_FRAMING_ERROR    11
#define V_IESPI2_TX_FRAMING_ERROR(x) ((x) << S_IESPI2_TX_FRAMING_ERROR)
#define F_IESPI2_TX_FRAMING_ERROR    V_IESPI2_TX_FRAMING_ERROR(1U)

#define S_IESPI3_TX_FRAMING_ERROR    10
#define V_IESPI3_TX_FRAMING_ERROR(x) ((x) << S_IESPI3_TX_FRAMING_ERROR)
#define F_IESPI3_TX_FRAMING_ERROR    V_IESPI3_TX_FRAMING_ERROR(1U)

#define S_OCSPI0_RX_FRAMING_ERROR    9
#define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR)
#define F_OCSPI0_RX_FRAMING_ERROR    V_OCSPI0_RX_FRAMING_ERROR(1U)

#define S_OCSPI1_RX_FRAMING_ERROR    8
#define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR)
#define F_OCSPI1_RX_FRAMING_ERROR    V_OCSPI1_RX_FRAMING_ERROR(1U)

#define S_OCSPI0_TX_FRAMING_ERROR    7
#define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR)
#define F_OCSPI0_TX_FRAMING_ERROR    V_OCSPI0_TX_FRAMING_ERROR(1U)

#define S_OCSPI1_TX_FRAMING_ERROR    6
#define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR)
#define F_OCSPI1_TX_FRAMING_ERROR    V_OCSPI1_TX_FRAMING_ERROR(1U)

#define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    5
#define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
#define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U)

#define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    4
#define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
#define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U)

#define S_OCSPI_PAR_ERROR    3
#define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR)
#define F_OCSPI_PAR_ERROR    V_OCSPI_PAR_ERROR(1U)

#define S_DB_OPTIONS_PAR_ERROR    2
#define V_DB_OPTIONS_PAR_ERROR(x) ((x) << S_DB_OPTIONS_PAR_ERROR)
#define F_DB_OPTIONS_PAR_ERROR    V_DB_OPTIONS_PAR_ERROR(1U)

#define S_IESPI_PAR_ERROR    1
#define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR)
#define F_IESPI_PAR_ERROR    V_IESPI_PAR_ERROR(1U)

#define S_E_PCMD_PAR_ERROR    0
#define V_E_PCMD_PAR_ERROR(x) ((x) << S_E_PCMD_PAR_ERROR)
#define F_E_PCMD_PAR_ERROR    V_E_PCMD_PAR_ERROR(1U)

#define S_OSPI_OVERFLOW1    28
#define V_OSPI_OVERFLOW1(x) ((x) << S_OSPI_OVERFLOW1)
#define F_OSPI_OVERFLOW1    V_OSPI_OVERFLOW1(1U)

#define S_OSPI_OVERFLOW0    27
#define V_OSPI_OVERFLOW0(x) ((x) << S_OSPI_OVERFLOW0)
#define F_OSPI_OVERFLOW0    V_OSPI_OVERFLOW0(1U)

#define S_MA_INTF_SDC_ERR    26
#define V_MA_INTF_SDC_ERR(x) ((x) << S_MA_INTF_SDC_ERR)
#define F_MA_INTF_SDC_ERR    V_MA_INTF_SDC_ERR(1U)

#define S_BUNDLE_LEN_PARERR    25
#define V_BUNDLE_LEN_PARERR(x) ((x) << S_BUNDLE_LEN_PARERR)
#define F_BUNDLE_LEN_PARERR    V_BUNDLE_LEN_PARERR(1U)

#define S_BUNDLE_LEN_OVFL    24
#define V_BUNDLE_LEN_OVFL(x) ((x) << S_BUNDLE_LEN_OVFL)
#define F_BUNDLE_LEN_OVFL    V_BUNDLE_LEN_OVFL(1U)

#define S_SDC_ERR    23
#define V_SDC_ERR(x) ((x) << S_SDC_ERR)
#define F_SDC_ERR    V_SDC_ERR(1U)

#define A_PM_RX_DBG_STAT_MSB 0x10013
#define A_PM_RX_DBG_STAT_LSB 0x10014

/* registers for module PM_TX */
#define PM_TX_BASE_ADDR 0x8fe0

#define A_PM_TX_STAT_CONFIG 0x8fe8
#define A_PM_TX_STAT_COUNT 0x8fec
#define A_PM_TX_STAT_LSB 0x8ff0
#define A_PM_TX_DBG_CTRL 0x8ff0

#define S_OSPIWRBUSY    21
#define M_OSPIWRBUSY    0xfU
#define V_OSPIWRBUSY(x) ((x) << S_OSPIWRBUSY)
#define G_OSPIWRBUSY(x) (((x) >> S_OSPIWRBUSY) & M_OSPIWRBUSY)

#define A_PM_TX_STAT_MSB 0x8ff4
#define A_PM_TX_DBG_DATA 0x8ff4
#define A_PM_TX_INT_CAUSE 0x8ffc

#define S_PCMD_LEN_OVFL0    31
#define V_PCMD_LEN_OVFL0(x) ((x) << S_PCMD_LEN_OVFL0)
#define F_PCMD_LEN_OVFL0    V_PCMD_LEN_OVFL0(1U)

#define S_PCMD_LEN_OVFL1    30
#define V_PCMD_LEN_OVFL1(x) ((x) << S_PCMD_LEN_OVFL1)
#define F_PCMD_LEN_OVFL1    V_PCMD_LEN_OVFL1(1U)

#define S_PCMD_LEN_OVFL2    29
#define V_PCMD_LEN_OVFL2(x) ((x) << S_PCMD_LEN_OVFL2)
#define F_PCMD_LEN_OVFL2    V_PCMD_LEN_OVFL2(1U)

#define S_ZERO_C_CMD_ERROR    28
#define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
#define F_ZERO_C_CMD_ERROR    V_ZERO_C_CMD_ERROR(1U)

#define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR    27
#define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
#define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR    V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)

#define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR    26
#define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
#define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR    V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)

#define S_ICSPI2_FIFO2X_RX_FRAMING_ERROR    25
#define V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_FIFO2X_RX_FRAMING_ERROR)
#define F_ICSPI2_FIFO2X_RX_FRAMING_ERROR    V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(1U)

#define S_ICSPI3_FIFO2X_RX_FRAMING_ERROR    24
#define V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_FIFO2X_RX_FRAMING_ERROR)
#define F_ICSPI3_FIFO2X_RX_FRAMING_ERROR    V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(1U)

#define S_ICSPI0_RX_FRAMING_ERROR    23
#define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR)
#define F_ICSPI0_RX_FRAMING_ERROR    V_ICSPI0_RX_FRAMING_ERROR(1U)

#define S_ICSPI1_RX_FRAMING_ERROR    22
#define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR)
#define F_ICSPI1_RX_FRAMING_ERROR    V_ICSPI1_RX_FRAMING_ERROR(1U)

#define S_ICSPI2_RX_FRAMING_ERROR    21
#define V_ICSPI2_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_RX_FRAMING_ERROR)
#define F_ICSPI2_RX_FRAMING_ERROR    V_ICSPI2_RX_FRAMING_ERROR(1U)

#define S_ICSPI3_RX_FRAMING_ERROR    20
#define V_ICSPI3_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_RX_FRAMING_ERROR)
#define F_ICSPI3_RX_FRAMING_ERROR    V_ICSPI3_RX_FRAMING_ERROR(1U)

#define S_ICSPI0_TX_FRAMING_ERROR    19
#define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR)
#define F_ICSPI0_TX_FRAMING_ERROR    V_ICSPI0_TX_FRAMING_ERROR(1U)

#define S_ICSPI1_TX_FRAMING_ERROR    18
#define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR)
#define F_ICSPI1_TX_FRAMING_ERROR    V_ICSPI1_TX_FRAMING_ERROR(1U)

#define S_ICSPI2_TX_FRAMING_ERROR    17
#define V_ICSPI2_TX_FRAMING_ERROR(x) ((x) << S_ICSPI2_TX_FRAMING_ERROR)
#define F_ICSPI2_TX_FRAMING_ERROR    V_ICSPI2_TX_FRAMING_ERROR(1U)

#define S_ICSPI3_TX_FRAMING_ERROR    16
#define V_ICSPI3_TX_FRAMING_ERROR(x) ((x) << S_ICSPI3_TX_FRAMING_ERROR)
#define F_ICSPI3_TX_FRAMING_ERROR    V_ICSPI3_TX_FRAMING_ERROR(1U)

#define S_OESPI0_RX_FRAMING_ERROR    15
#define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR)
#define F_OESPI0_RX_FRAMING_ERROR    V_OESPI0_RX_FRAMING_ERROR(1U)

#define S_OESPI1_RX_FRAMING_ERROR    14
#define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR)
#define F_OESPI1_RX_FRAMING_ERROR    V_OESPI1_RX_FRAMING_ERROR(1U)

#define S_OESPI2_RX_FRAMING_ERROR    13
#define V_OESPI2_RX_FRAMING_ERROR(x) ((x) << S_OESPI2_RX_FRAMING_ERROR)
#define F_OESPI2_RX_FRAMING_ERROR    V_OESPI2_RX_FRAMING_ERROR(1U)

#define S_OESPI3_RX_FRAMING_ERROR    12
#define V_OESPI3_RX_FRAMING_ERROR(x) ((x) << S_OESPI3_RX_FRAMING_ERROR)
#define F_OESPI3_RX_FRAMING_ERROR    V_OESPI3_RX_FRAMING_ERROR(1U)

#define S_OESPI0_TX_FRAMING_ERROR    11
#define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR)
#define F_OESPI0_TX_FRAMING_ERROR    V_OESPI0_TX_FRAMING_ERROR(1U)

#define S_OESPI1_TX_FRAMING_ERROR    10
#define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR)
#define F_OESPI1_TX_FRAMING_ERROR    V_OESPI1_TX_FRAMING_ERROR(1U)

#define S_OESPI2_TX_FRAMING_ERROR    9
#define V_OESPI2_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_TX_FRAMING_ERROR)
#define F_OESPI2_TX_FRAMING_ERROR    V_OESPI2_TX_FRAMING_ERROR(1U)

#define S_OESPI3_TX_FRAMING_ERROR    8
#define V_OESPI3_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_TX_FRAMING_ERROR)
#define F_OESPI3_TX_FRAMING_ERROR    V_OESPI3_TX_FRAMING_ERROR(1U)

#define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR    7
#define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
#define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR    V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)

#define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR    6
#define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
#define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR    V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)

#define S_OESPI2_OFIFO2X_TX_FRAMING_ERROR    5
#define V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_OFIFO2X_TX_FRAMING_ERROR)
#define F_OESPI2_OFIFO2X_TX_FRAMING_ERROR    V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(1U)

#define S_OESPI3_OFIFO2X_TX_FRAMING_ERROR    4
#define V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_OFIFO2X_TX_FRAMING_ERROR)
#define F_OESPI3_OFIFO2X_TX_FRAMING_ERROR    V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(1U)

#define S_OESPI_PAR_ERROR    3
#define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR)
#define F_OESPI_PAR_ERROR    V_OESPI_PAR_ERROR(1U)

#define S_ICSPI_PAR_ERROR    1
#define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR)
#define F_ICSPI_PAR_ERROR    V_ICSPI_PAR_ERROR(1U)

#define S_C_PCMD_PAR_ERROR    0
#define V_C_PCMD_PAR_ERROR(x) ((x) << S_C_PCMD_PAR_ERROR)
#define F_C_PCMD_PAR_ERROR    V_C_PCMD_PAR_ERROR(1U)

#define S_OSPI_OR_BUNDLE_LEN_PAR_ERR    3
#define V_OSPI_OR_BUNDLE_LEN_PAR_ERR(x) ((x) << S_OSPI_OR_BUNDLE_LEN_PAR_ERR)
#define F_OSPI_OR_BUNDLE_LEN_PAR_ERR    V_OSPI_OR_BUNDLE_LEN_PAR_ERR(1U)

#define A_PM_TX_DBG_STAT_MSB 0x1001a
#define A_PM_TX_DBG_STAT_LSB 0x1001b

/* registers for module MPS */
#define MPS_BASE_ADDR 0x9000

#define A_MPS_VF_CTL 0x0
#define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L 0x80
#define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_H 0x84
#define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_L 0x88
#define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_H 0x8c
#define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_L 0x90
#define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_H 0x94
#define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_L 0x98
#define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_H 0x9c
#define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_L 0xa0
#define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_H 0xa4
#define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_L 0xa8
#define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_H 0xac
#define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_L 0xb0
#define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_H 0xb4
#define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_L 0xb8
#define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_H 0xbc
#define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_L 0xc0
#define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_H 0xc4
#define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_L 0xc8
#define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_H 0xcc
#define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_L 0xd0
#define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_H 0xd4
#define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_L 0xd8
#define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_H 0xdc
#define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_L 0xe0
#define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_H 0xe4
#define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_L 0xe8
#define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_H 0xec
#define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_L 0xf0
#define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_H 0xf4
#define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_L 0xf8
#define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H 0xfc
#define A_MPS_PORT_CLS_HASH_SRAM 0x200

#define S_VALID    20
#define V_VALID(x) ((x) << S_VALID)
#define F_VALID    V_VALID(1U)

#define S_HASHPORTMAP    16
#define M_HASHPORTMAP    0xfU
#define V_HASHPORTMAP(x) ((x) << S_HASHPORTMAP)
#define G_HASHPORTMAP(x) (((x) >> S_HASHPORTMAP) & M_HASHPORTMAP)

#define S_MULTILISTEN    15
#define V_MULTILISTEN(x) ((x) << S_MULTILISTEN)
#define F_MULTILISTEN    V_MULTILISTEN(1U)

#define S_PRIORITY    12
#define M_PRIORITY    0x7U
#define V_PRIORITY(x) ((x) << S_PRIORITY)
#define G_PRIORITY(x) (((x) >> S_PRIORITY) & M_PRIORITY)

#define S_REPLICATE    11
#define V_REPLICATE(x) ((x) << S_REPLICATE)
#define F_REPLICATE    V_REPLICATE(1U)

#define S_PF    8
#define M_PF    0x7U
#define V_PF(x) ((x) << S_PF)
#define G_PF(x) (((x) >> S_PF) & M_PF)

#define S_VF_VALID    7
#define V_VF_VALID(x) ((x) << S_VF_VALID)
#define F_VF_VALID    V_VF_VALID(1U)

#define S_VF    0
#define M_VF    0x7fU
#define V_VF(x) ((x) << S_VF)
#define G_VF(x) (((x) >> S_VF) & M_VF)

#define S_DISENCAPOUTERRPLCT    23
#define V_DISENCAPOUTERRPLCT(x) ((x) << S_DISENCAPOUTERRPLCT)
#define F_DISENCAPOUTERRPLCT    V_DISENCAPOUTERRPLCT(1U)

#define S_DISENCAP    22
#define V_DISENCAP(x) ((x) << S_DISENCAP)
#define F_DISENCAP    V_DISENCAP(1U)

#define S_T6_VALID    21
#define V_T6_VALID(x) ((x) << S_T6_VALID)
#define F_T6_VALID    V_T6_VALID(1U)

#define S_T6_HASHPORTMAP    17
#define M_T6_HASHPORTMAP    0xfU
#define V_T6_HASHPORTMAP(x) ((x) << S_T6_HASHPORTMAP)
#define G_T6_HASHPORTMAP(x) (((x) >> S_T6_HASHPORTMAP) & M_T6_HASHPORTMAP)

#define S_T6_MULTILISTEN    16
#define V_T6_MULTILISTEN(x) ((x) << S_T6_MULTILISTEN)
#define F_T6_MULTILISTEN    V_T6_MULTILISTEN(1U)

#define S_T6_PRIORITY    13
#define M_T6_PRIORITY    0x7U
#define V_T6_PRIORITY(x) ((x) << S_T6_PRIORITY)
#define G_T6_PRIORITY(x) (((x) >> S_T6_PRIORITY) & M_T6_PRIORITY)

#define S_T6_REPLICATE    12
#define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE)
#define F_T6_REPLICATE    V_T6_REPLICATE(1U)

#define S_T6_PF    9
#define M_T6_PF    0x7U
#define V_T6_PF(x) ((x) << S_T6_PF)
#define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF)

#define S_T6_VF_VALID    8
#define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID)
#define F_T6_VF_VALID    V_T6_VF_VALID(1U)

#define S_T6_VF    0
#define M_T6_VF    0xffU
#define V_T6_VF(x) ((x) << S_T6_VF)
#define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF)

#define A_MPS_PF_CTL 0x2c0

#define S_TXEN    1
#define V_TXEN(x) ((x) << S_TXEN)
#define F_TXEN    V_TXEN(1U)

#define S_RXEN    0
#define V_RXEN(x) ((x) << S_RXEN)
#define F_RXEN    V_RXEN(1U)

#define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
#define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
#define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
#define A_MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
#define A_MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
#define A_MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
#define A_MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
#define A_MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
#define A_MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
#define A_MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
#define A_MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
#define A_MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
#define A_MPS_PORT_STAT_TX_PORT_64B_L 0x430
#define A_MPS_PORT_STAT_TX_PORT_64B_H 0x434
#define A_MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
#define A_MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
#define A_MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
#define A_MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
#define A_MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
#define A_MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
#define A_MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
#define A_MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
#define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
#define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
#define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
#define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
#define A_MPS_PORT_STAT_TX_PORT_DROP_L 0x468
#define A_MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
#define A_MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
#define A_MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
#define A_MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
#define A_MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
#define A_MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
#define A_MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
#define A_MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
#define A_MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
#define A_MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
#define A_MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
#define A_MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
#define A_MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
#define A_MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
#define A_MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
#define A_MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
#define A_MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
#define A_MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
#define A_MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
#define A_MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
#define A_MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
#define A_MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
#define A_MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
#define A_MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
#define A_MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
#define A_MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
#define A_MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
#define A_MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
#define A_MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
#define A_MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
#define A_MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
#define A_MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
#define A_MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
#define A_MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
#define A_MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
#define A_MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
#define A_MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
#define A_MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
#define A_MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
#define A_MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
#define A_MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
#define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
#define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
#define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
#define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c
#define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
#define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
#define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
#define A_MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
#define A_MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
#define A_MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
#define A_MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
#define A_MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
#define A_MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
#define A_MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
#define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
#define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
#define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
#define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
#define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
#define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
#define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
#define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
#define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
#define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
#define A_MPS_PORT_STAT_RX_PORT_64B_L 0x590
#define A_MPS_PORT_STAT_RX_PORT_64B_H 0x594
#define A_MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
#define A_MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
#define A_MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
#define A_MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
#define A_MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
#define A_MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
#define A_MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
#define A_MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
#define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
#define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
#define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
#define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
#define A_MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
#define A_MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
#define A_MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
#define A_MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
#define A_MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
#define A_MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
#define A_MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
#define A_MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
#define A_MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
#define A_MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
#define A_MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
#define A_MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
#define A_MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
#define A_MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
#define A_MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
#define A_MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
#define A_MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
#define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
#define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
#define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
#define A_MPS_CMN_CTL 0x9000

#define S_DETECT8023    3
#define V_DETECT8023(x) ((x) << S_DETECT8023)
#define F_DETECT8023    V_DETECT8023(1U)

#define S_VFDIRECTACCESS    2
#define V_VFDIRECTACCESS(x) ((x) << S_VFDIRECTACCESS)
#define F_VFDIRECTACCESS    V_VFDIRECTACCESS(1U)

#define S_NUMPORTS    0
#define M_NUMPORTS    0x3U
#define V_NUMPORTS(x) ((x) << S_NUMPORTS)
#define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS)

#define S_LPBKCRDTCTRL    4
#define V_LPBKCRDTCTRL(x) ((x) << S_LPBKCRDTCTRL)
#define F_LPBKCRDTCTRL    V_LPBKCRDTCTRL(1U)

#define A_MPS_INT_CAUSE 0x9008

#define S_STATINT    5
#define V_STATINT(x) ((x) << S_STATINT)
#define F_STATINT    V_STATINT(1U)

#define S_TXINT    4
#define V_TXINT(x) ((x) << S_TXINT)
#define F_TXINT    V_TXINT(1U)

#define S_RXINT    3
#define V_RXINT(x) ((x) << S_RXINT)
#define F_RXINT    V_RXINT(1U)

#define S_TRCINT    2
#define V_TRCINT(x) ((x) << S_TRCINT)
#define F_TRCINT    V_TRCINT(1U)

#define S_CLSINT    1
#define V_CLSINT(x) ((x) << S_CLSINT)
#define F_CLSINT    V_CLSINT(1U)

#define S_PLINT    0
#define V_PLINT(x) ((x) << S_PLINT)
#define F_PLINT    V_PLINT(1U)

#define A_MPS_TX_INT_CAUSE 0x9408

#define S_PORTERR    16
#define V_PORTERR(x) ((x) << S_PORTERR)
#define F_PORTERR    V_PORTERR(1U)

#define S_FRMERR    15
#define V_FRMERR(x) ((x) << S_FRMERR)
#define F_FRMERR    V_FRMERR(1U)

#define S_SECNTERR    14
#define V_SECNTERR(x) ((x) << S_SECNTERR)
#define F_SECNTERR    V_SECNTERR(1U)

#define S_BUBBLE    13
#define V_BUBBLE(x) ((x) << S_BUBBLE)
#define F_BUBBLE    V_BUBBLE(1U)

#define S_TXDESCFIFO    9
#define M_TXDESCFIFO    0xfU
#define V_TXDESCFIFO(x) ((x) << S_TXDESCFIFO)
#define G_TXDESCFIFO(x) (((x) >> S_TXDESCFIFO) & M_TXDESCFIFO)

#define S_TXDATAFIFO    5
#define M_TXDATAFIFO    0xfU
#define V_TXDATAFIFO(x) ((x) << S_TXDATAFIFO)
#define G_TXDATAFIFO(x) (((x) >> S_TXDATAFIFO) & M_TXDATAFIFO)

#define S_NCSIFIFO    4
#define V_NCSIFIFO(x) ((x) << S_NCSIFIFO)
#define F_NCSIFIFO    V_NCSIFIFO(1U)

#define S_TPFIFO    0
#define M_TPFIFO    0xfU
#define V_TPFIFO(x) ((x) << S_TPFIFO)
#define G_TPFIFO(x) (((x) >> S_TPFIFO) & M_TPFIFO)

#define A_MPS_TX_SE_CNT_TP01 0x9418
#define A_MPS_TX_SE_CNT_TP23 0x941c
#define A_MPS_TX_SE_CNT_MAC01 0x9420
#define A_MPS_TX_SE_CNT_MAC23 0x9424
#define A_MPS_STAT_CTL 0x9600

#define S_COUNTPAUSESTATRX    4
#define V_COUNTPAUSESTATRX(x) ((x) << S_COUNTPAUSESTATRX)
#define F_COUNTPAUSESTATRX    V_COUNTPAUSESTATRX(1U)

#define S_COUNTPAUSESTATTX    2
#define V_COUNTPAUSESTATTX(x) ((x) << S_COUNTPAUSESTATTX)
#define F_COUNTPAUSESTATTX    V_COUNTPAUSESTATTX(1U)

#define S_STATSTOPCTRL    10
#define V_STATSTOPCTRL(x) ((x) << S_STATSTOPCTRL)
#define F_STATSTOPCTRL    V_STATSTOPCTRL(1U)

#define S_STOPSTAT    9
#define V_STOPSTAT(x) ((x) << S_STOPSTAT)
#define F_STOPSTAT    V_STOPSTAT(1U)

#define S_STATWRITECTRL    8
#define V_STATWRITECTRL(x) ((x) << S_STATWRITECTRL)
#define F_STATWRITECTRL    V_STATWRITECTRL(1U)

#define S_COUNTLBPF    7
#define V_COUNTLBPF(x) ((x) << S_COUNTLBPF)
#define F_COUNTLBPF    V_COUNTLBPF(1U)

#define S_COUNTLBVF    6
#define V_COUNTLBVF(x) ((x) << S_COUNTLBVF)
#define F_COUNTLBVF    V_COUNTLBVF(1U)

#define S_COUNTPAUSEMCRX    5
#define V_COUNTPAUSEMCRX(x) ((x) << S_COUNTPAUSEMCRX)
#define F_COUNTPAUSEMCRX    V_COUNTPAUSEMCRX(1U)

#define S_COUNTPAUSEMCTX    3
#define V_COUNTPAUSEMCTX(x) ((x) << S_COUNTPAUSEMCTX)
#define F_COUNTPAUSEMCTX    V_COUNTPAUSEMCTX(1U)

#define A_MPS_STAT_INT_CAUSE 0x960c

#define S_PLREADSYNCERR    0
#define V_PLREADSYNCERR(x) ((x) << S_PLREADSYNCERR)
#define F_PLREADSYNCERR    V_PLREADSYNCERR(1U)

#define A_MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614

#define S_RXBG    20
#define V_RXBG(x) ((x) << S_RXBG)
#define F_RXBG    V_RXBG(1U)

#define S_RXVF    18
#define M_RXVF    0x3U
#define V_RXVF(x) ((x) << S_RXVF)
#define G_RXVF(x) (((x) >> S_RXVF) & M_RXVF)

#define S_TXVF    16
#define M_TXVF    0x3U
#define V_TXVF(x) ((x) << S_TXVF)
#define G_TXVF(x) (((x) >> S_TXVF) & M_TXVF)

#define S_RXPF    13
#define M_RXPF    0x7U
#define V_RXPF(x) ((x) << S_RXPF)
#define G_RXPF(x) (((x) >> S_RXPF) & M_RXPF)

#define S_TXPF    11
#define M_TXPF    0x3U
#define V_TXPF(x) ((x) << S_TXPF)
#define G_TXPF(x) (((x) >> S_TXPF) & M_TXPF)

#define S_RXPORT    7
#define M_RXPORT    0xfU
#define V_RXPORT(x) ((x) << S_RXPORT)
#define G_RXPORT(x) (((x) >> S_RXPORT) & M_RXPORT)

#define S_LBPORT    4
#define M_LBPORT    0x7U
#define V_LBPORT(x) ((x) << S_LBPORT)
#define G_LBPORT(x) (((x) >> S_LBPORT) & M_LBPORT)

#define S_TXPORT    0
#define M_TXPORT    0xfU
#define V_TXPORT(x) ((x) << S_TXPORT)
#define G_TXPORT(x) (((x) >> S_TXPORT) & M_TXPORT)

#define S_T5_RXBG    27
#define M_T5_RXBG    0x3U
#define V_T5_RXBG(x) ((x) << S_T5_RXBG)
#define G_T5_RXBG(x) (((x) >> S_T5_RXBG) & M_T5_RXBG)

#define S_T5_RXPF    22
#define M_T5_RXPF    0x1fU
#define V_T5_RXPF(x) ((x) << S_T5_RXPF)
#define G_T5_RXPF(x) (((x) >> S_T5_RXPF) & M_T5_RXPF)

#define S_T5_TXPF    18
#define M_T5_TXPF    0xfU
#define V_T5_TXPF(x) ((x) << S_T5_TXPF)
#define G_T5_TXPF(x) (((x) >> S_T5_TXPF) & M_T5_TXPF)

#define S_T5_RXPORT    11
#define M_T5_RXPORT    0x7fU
#define V_T5_RXPORT(x) ((x) << S_T5_RXPORT)
#define G_T5_RXPORT(x) (((x) >> S_T5_RXPORT) & M_T5_RXPORT)

#define S_T5_LBPORT    6
#define M_T5_LBPORT    0x1fU
#define V_T5_LBPORT(x) ((x) << S_T5_LBPORT)
#define G_T5_LBPORT(x) (((x) >> S_T5_LBPORT) & M_T5_LBPORT)

#define S_T5_TXPORT    0
#define M_T5_TXPORT    0x3fU
#define V_T5_TXPORT(x) ((x) << S_T5_TXPORT)
#define G_T5_TXPORT(x) (((x) >> S_T5_TXPORT) & M_T5_TXPORT)

#define A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620

#define S_TX    12
#define M_TX    0xffU
#define V_TX(x) ((x) << S_TX)
#define G_TX(x) (((x) >> S_TX) & M_TX)

#define S_TXPAUSEFIFO    8
#define M_TXPAUSEFIFO    0xfU
#define V_TXPAUSEFIFO(x) ((x) << S_TXPAUSEFIFO)
#define G_TXPAUSEFIFO(x) (((x) >> S_TXPAUSEFIFO) & M_TXPAUSEFIFO)

#define S_DROP    0
#define M_DROP    0xffU
#define V_DROP(x) ((x) << S_DROP)
#define G_DROP(x) (((x) >> S_DROP) & M_DROP)

#define S_TXCH    20
#define M_TXCH    0xfU
#define V_TXCH(x) ((x) << S_TXCH)
#define G_TXCH(x) (((x) >> S_TXCH) & M_TXCH)

#define A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c

#define S_PAUSEFIFO    20
#define M_PAUSEFIFO    0xfU
#define V_PAUSEFIFO(x) ((x) << S_PAUSEFIFO)
#define G_PAUSEFIFO(x) (((x) >> S_PAUSEFIFO) & M_PAUSEFIFO)

#define S_LPBK    16
#define M_LPBK    0xfU
#define V_LPBK(x) ((x) << S_LPBK)
#define G_LPBK(x) (((x) >> S_LPBK) & M_LPBK)

#define S_NQ    8
#define M_NQ    0xffU
#define V_NQ(x) ((x) << S_NQ)
#define G_NQ(x) (((x) >> S_NQ) & M_NQ)

#define S_PV    4
#define M_PV    0xfU
#define V_PV(x) ((x) << S_PV)
#define G_PV(x) (((x) >> S_PV) & M_PV)

#define S_MAC    0
#define M_MAC    0xfU
#define V_MAC(x) ((x) << S_MAC)
#define G_MAC(x) (((x) >> S_MAC) & M_MAC)

#define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
#define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
#define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
#define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
#define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
#define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
#define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
#define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
#define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
#define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
#define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
#define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
#define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
#define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
#define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
#define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
#define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
#define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
#define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
#define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
#define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
#define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
#define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
#define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
#define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
#define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
#define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
#define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
#define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
#define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
#define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
#define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
#define A_MPS_STAT_PERR_INT_CAUSE_SRAM1 0x96c4

#define S_T5_RXVF    5
#define M_T5_RXVF    0x7U
#define V_T5_RXVF(x) ((x) << S_T5_RXVF)
#define G_T5_RXVF(x) (((x) >> S_T5_RXVF) & M_T5_RXVF)

#define S_T5_TXVF    0
#define M_T5_TXVF    0x1fU
#define V_T5_TXVF(x) ((x) << S_T5_TXVF)
#define G_T5_TXVF(x) (((x) >> S_T5_TXVF) & M_T5_TXVF)

#define A_MPS_TRC_CFG 0x9800

#define S_TRCFIFOEMPTY    4
#define V_TRCFIFOEMPTY(x) ((x) << S_TRCFIFOEMPTY)
#define F_TRCFIFOEMPTY    V_TRCFIFOEMPTY(1U)

#define S_TRCIGNOREDROPINPUT    3
#define V_TRCIGNOREDROPINPUT(x) ((x) << S_TRCIGNOREDROPINPUT)
#define F_TRCIGNOREDROPINPUT    V_TRCIGNOREDROPINPUT(1U)

#define S_TRCKEEPDUPLICATES    2
#define V_TRCKEEPDUPLICATES(x) ((x) << S_TRCKEEPDUPLICATES)
#define F_TRCKEEPDUPLICATES    V_TRCKEEPDUPLICATES(1U)

#define S_TRCEN    1
#define V_TRCEN(x) ((x) << S_TRCEN)
#define F_TRCEN    V_TRCEN(1U)

#define S_TRCMULTIFILTER    0
#define V_TRCMULTIFILTER(x) ((x) << S_TRCMULTIFILTER)
#define F_TRCMULTIFILTER    V_TRCMULTIFILTER(1U)

#define S_TRCMULTIRSSFILTER    5
#define V_TRCMULTIRSSFILTER(x) ((x) << S_TRCMULTIRSSFILTER)
#define F_TRCMULTIRSSFILTER    V_TRCMULTIRSSFILTER(1U)

#define A_MPS_TRC_RSS_CONTROL 0x9808

#define S_RSSCONTROL    16
#define M_RSSCONTROL    0xffU
#define V_RSSCONTROL(x) ((x) << S_RSSCONTROL)
#define G_RSSCONTROL(x) (((x) >> S_RSSCONTROL) & M_RSSCONTROL)

#define S_QUEUENUMBER    0
#define M_QUEUENUMBER    0xffffU
#define V_QUEUENUMBER(x) ((x) << S_QUEUENUMBER)
#define G_QUEUENUMBER(x) (((x) >> S_QUEUENUMBER) & M_QUEUENUMBER)

#define A_MPS_TRC_FILTER_MATCH_CTL_A 0x9810

#define S_TFINVERTMATCH    24
#define V_TFINVERTMATCH(x) ((x) << S_TFINVERTMATCH)
#define F_TFINVERTMATCH    V_TFINVERTMATCH(1U)

#define S_TFPKTTOOLARGE    23
#define V_TFPKTTOOLARGE(x) ((x) << S_TFPKTTOOLARGE)
#define F_TFPKTTOOLARGE    V_TFPKTTOOLARGE(1U)

#define S_TFEN    22
#define V_TFEN(x) ((x) << S_TFEN)
#define F_TFEN    V_TFEN(1U)

#define S_TFPORT    18
#define M_TFPORT    0xfU
#define V_TFPORT(x) ((x) << S_TFPORT)
#define G_TFPORT(x) (((x) >> S_TFPORT) & M_TFPORT)

#define S_TFDROP    17
#define V_TFDROP(x) ((x) << S_TFDROP)
#define F_TFDROP    V_TFDROP(1U)

#define S_TFSOPEOPERR    16
#define V_TFSOPEOPERR(x) ((x) << S_TFSOPEOPERR)
#define F_TFSOPEOPERR    V_TFSOPEOPERR(1U)

#define S_TFLENGTH    8
#define M_TFLENGTH    0x1fU
#define V_TFLENGTH(x) ((x) << S_TFLENGTH)
#define G_TFLENGTH(x) (((x) >> S_TFLENGTH) & M_TFLENGTH)

#define S_TFOFFSET    0
#define M_TFOFFSET    0x1fU
#define V_TFOFFSET(x) ((x) << S_TFOFFSET)
#define G_TFOFFSET(x) (((x) >> S_TFOFFSET) & M_TFOFFSET)

#define S_TFINSERTACTLEN    27
#define V_TFINSERTACTLEN(x) ((x) << S_TFINSERTACTLEN)
#define F_TFINSERTACTLEN    V_TFINSERTACTLEN(1U)

#define S_TFINSERTTIMER    26
#define V_TFINSERTTIMER(x) ((x) << S_TFINSERTTIMER)
#define F_TFINSERTTIMER    V_TFINSERTTIMER(1U)

#define S_T5_TFINVERTMATCH    25
#define V_T5_TFINVERTMATCH(x) ((x) << S_T5_TFINVERTMATCH)
#define F_T5_TFINVERTMATCH    V_T5_TFINVERTMATCH(1U)

#define S_T5_TFPKTTOOLARGE    24
#define V_T5_TFPKTTOOLARGE(x) ((x) << S_T5_TFPKTTOOLARGE)
#define F_T5_TFPKTTOOLARGE    V_T5_TFPKTTOOLARGE(1U)

#define S_T5_TFEN    23
#define V_T5_TFEN(x) ((x) << S_T5_TFEN)
#define F_T5_TFEN    V_T5_TFEN(1U)

#define S_T5_TFPORT    18
#define M_T5_TFPORT    0x1fU
#define V_T5_TFPORT(x) ((x) << S_T5_TFPORT)
#define G_T5_TFPORT(x) (((x) >> S_T5_TFPORT) & M_T5_TFPORT)

#define A_MPS_TRC_FILTER_MATCH_CTL_B 0x9820

#define S_TFMINPKTSIZE    16
#define M_TFMINPKTSIZE    0x1ffU
#define V_TFMINPKTSIZE(x) ((x) << S_TFMINPKTSIZE)
#define G_TFMINPKTSIZE(x) (((x) >> S_TFMINPKTSIZE) & M_TFMINPKTSIZE)

#define S_TFCAPTUREMAX    0
#define M_TFCAPTUREMAX    0x3fffU
#define V_TFCAPTUREMAX(x) ((x) << S_TFCAPTUREMAX)
#define G_TFCAPTUREMAX(x) (((x) >> S_TFCAPTUREMAX) & M_TFCAPTUREMAX)

#define A_MPS_TRC_INT_CAUSE 0x985c

#define S_TRCPLERRENB    9
#define V_TRCPLERRENB(x) ((x) << S_TRCPLERRENB)
#define F_TRCPLERRENB    V_TRCPLERRENB(1U)

#define S_MISCPERR    8
#define V_MISCPERR(x) ((x) << S_MISCPERR)
#define F_MISCPERR    V_MISCPERR(1U)

#define S_PKTFIFO    4
#define M_PKTFIFO    0xfU
#define V_PKTFIFO(x) ((x) << S_PKTFIFO)
#define G_PKTFIFO(x) (((x) >> S_PKTFIFO) & M_PKTFIFO)

#define S_FILTMEM    0
#define M_FILTMEM    0xfU
#define V_FILTMEM(x) ((x) << S_FILTMEM)
#define G_FILTMEM(x) (((x) >> S_FILTMEM) & M_FILTMEM)

#define A_MPS_TRC_FILTER0_MATCH 0x9c00
#define A_MPS_TRC_FILTER0_DONT_CARE 0x9c80
#define A_MPS_TRC_FILTER1_MATCH 0x9d00
#define A_MPS_T5_TRC_RSS_CONTROL 0xa00c
#define A_MPS_CLS_PERR_ENABLE 0xd020

#define S_HASHSRAM    2
#define V_HASHSRAM(x) ((x) << S_HASHSRAM)
#define F_HASHSRAM    V_HASHSRAM(1U)

#define S_MATCHTCAM    1
#define V_MATCHTCAM(x) ((x) << S_MATCHTCAM)
#define F_MATCHTCAM    V_MATCHTCAM(1U)

#define S_MATCHSRAM    0
#define V_MATCHSRAM(x) ((x) << S_MATCHSRAM)
#define F_MATCHSRAM    V_MATCHSRAM(1U)

#define A_MPS_CLS_INT_ENABLE 0xd024

#define S_PLERRENB    3
#define V_PLERRENB(x) ((x) << S_PLERRENB)
#define F_PLERRENB    V_PLERRENB(1U)

#define A_MPS_CLS_INT_CAUSE 0xd028
#define A_MPS_CLS_SRAM_L 0xe000

#define S_MULTILISTEN3    28
#define V_MULTILISTEN3(x) ((x) << S_MULTILISTEN3)
#define F_MULTILISTEN3    V_MULTILISTEN3(1U)

#define S_MULTILISTEN2    27
#define V_MULTILISTEN2(x) ((x) << S_MULTILISTEN2)
#define F_MULTILISTEN2    V_MULTILISTEN2(1U)

#define S_MULTILISTEN1    26
#define V_MULTILISTEN1(x) ((x) << S_MULTILISTEN1)
#define F_MULTILISTEN1    V_MULTILISTEN1(1U)

#define S_MULTILISTEN0    25
#define V_MULTILISTEN0(x) ((x) << S_MULTILISTEN0)
#define F_MULTILISTEN0    V_MULTILISTEN0(1U)

#define S_SRAM_PRIO3    22
#define M_SRAM_PRIO3    0x7U
#define V_SRAM_PRIO3(x) ((x) << S_SRAM_PRIO3)
#define G_SRAM_PRIO3(x) (((x) >> S_SRAM_PRIO3) & M_SRAM_PRIO3)

#define S_SRAM_PRIO2    19
#define M_SRAM_PRIO2    0x7U
#define V_SRAM_PRIO2(x) ((x) << S_SRAM_PRIO2)
#define G_SRAM_PRIO2(x) (((x) >> S_SRAM_PRIO2) & M_SRAM_PRIO2)

#define S_SRAM_PRIO1    16
#define M_SRAM_PRIO1    0x7U
#define V_SRAM_PRIO1(x) ((x) << S_SRAM_PRIO1)
#define G_SRAM_PRIO1(x) (((x) >> S_SRAM_PRIO1) & M_SRAM_PRIO1)

#define S_SRAM_PRIO0    13
#define M_SRAM_PRIO0    0x7U
#define V_SRAM_PRIO0(x) ((x) << S_SRAM_PRIO0)
#define G_SRAM_PRIO0(x) (((x) >> S_SRAM_PRIO0) & M_SRAM_PRIO0)

#define S_SRAM_VLD    12
#define V_SRAM_VLD(x) ((x) << S_SRAM_VLD)
#define F_SRAM_VLD    V_SRAM_VLD(1U)

#define A_MPS_T5_CLS_SRAM_L 0xe000

#define S_T6_DISENCAPOUTERRPLCT    31
#define V_T6_DISENCAPOUTERRPLCT(x) ((x) << S_T6_DISENCAPOUTERRPLCT)
#define F_T6_DISENCAPOUTERRPLCT    V_T6_DISENCAPOUTERRPLCT(1U)

#define S_T6_DISENCAP    30
#define V_T6_DISENCAP(x) ((x) << S_T6_DISENCAP)
#define F_T6_DISENCAP    V_T6_DISENCAP(1U)

#define S_T6_MULTILISTEN3    29
#define V_T6_MULTILISTEN3(x) ((x) << S_T6_MULTILISTEN3)
#define F_T6_MULTILISTEN3    V_T6_MULTILISTEN3(1U)

#define S_T6_MULTILISTEN2    28
#define V_T6_MULTILISTEN2(x) ((x) << S_T6_MULTILISTEN2)
#define F_T6_MULTILISTEN2    V_T6_MULTILISTEN2(1U)

#define S_T6_MULTILISTEN1    27
#define V_T6_MULTILISTEN1(x) ((x) << S_T6_MULTILISTEN1)
#define F_T6_MULTILISTEN1    V_T6_MULTILISTEN1(1U)

#define S_T6_MULTILISTEN0    26
#define V_T6_MULTILISTEN0(x) ((x) << S_T6_MULTILISTEN0)
#define F_T6_MULTILISTEN0    V_T6_MULTILISTEN0(1U)

#define S_T6_SRAM_PRIO3    23
#define M_T6_SRAM_PRIO3    0x7U
#define V_T6_SRAM_PRIO3(x) ((x) << S_T6_SRAM_PRIO3)
#define G_T6_SRAM_PRIO3(x) (((x) >> S_T6_SRAM_PRIO3) & M_T6_SRAM_PRIO3)

#define S_T6_SRAM_PRIO2    20
#define M_T6_SRAM_PRIO2    0x7U
#define V_T6_SRAM_PRIO2(x) ((x) << S_T6_SRAM_PRIO2)
#define G_T6_SRAM_PRIO2(x) (((x) >> S_T6_SRAM_PRIO2) & M_T6_SRAM_PRIO2)

#define S_T6_SRAM_PRIO1    17
#define M_T6_SRAM_PRIO1    0x7U
#define V_T6_SRAM_PRIO1(x) ((x) << S_T6_SRAM_PRIO1)
#define G_T6_SRAM_PRIO1(x) (((x) >> S_T6_SRAM_PRIO1) & M_T6_SRAM_PRIO1)

#define S_T6_SRAM_PRIO0    14
#define M_T6_SRAM_PRIO0    0x7U
#define V_T6_SRAM_PRIO0(x) ((x) << S_T6_SRAM_PRIO0)
#define G_T6_SRAM_PRIO0(x) (((x) >> S_T6_SRAM_PRIO0) & M_T6_SRAM_PRIO0)

#define S_T6_SRAM_VLD    13
#define V_T6_SRAM_VLD(x) ((x) << S_T6_SRAM_VLD)
#define F_T6_SRAM_VLD    V_T6_SRAM_VLD(1U)

#define S_T6_REPLICATE    12
#define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE)
#define F_T6_REPLICATE    V_T6_REPLICATE(1U)

#define S_T6_PF    9
#define M_T6_PF    0x7U
#define V_T6_PF(x) ((x) << S_T6_PF)
#define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF)

#define S_T6_VF_VALID    8
#define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID)
#define F_T6_VF_VALID    V_T6_VF_VALID(1U)

#define S_T6_VF    0
#define M_T6_VF    0xffU
#define V_T6_VF(x) ((x) << S_T6_VF)
#define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF)

#define A_MPS_CLS_SRAM_H 0xe004

#define S_MACPARITY1    9
#define V_MACPARITY1(x) ((x) << S_MACPARITY1)
#define F_MACPARITY1    V_MACPARITY1(1U)

#define S_MACPARITY0    8
#define V_MACPARITY0(x) ((x) << S_MACPARITY0)
#define F_MACPARITY0    V_MACPARITY0(1U)

#define S_MACPARITYMASKSIZE    4
#define M_MACPARITYMASKSIZE    0xfU
#define V_MACPARITYMASKSIZE(x) ((x) << S_MACPARITYMASKSIZE)
#define G_MACPARITYMASKSIZE(x) (((x) >> S_MACPARITYMASKSIZE) & M_MACPARITYMASKSIZE)

#define S_PORTMAP    0
#define M_PORTMAP    0xfU
#define V_PORTMAP(x) ((x) << S_PORTMAP)
#define G_PORTMAP(x) (((x) >> S_PORTMAP) & M_PORTMAP)

#define A_MPS_T5_CLS_SRAM_H 0xe004

#define S_MACPARITY2    10
#define V_MACPARITY2(x) ((x) << S_MACPARITY2)
#define F_MACPARITY2    V_MACPARITY2(1U)

#define A_MPS_CLS_TCAM_Y_L 0xf000
#define A_MPS_CLS_TCAM_DATA0 0xf000
#define A_MPS_CLS_TCAM_DATA1 0xf004

#define S_VIDL    16
#define M_VIDL    0xffffU
#define V_VIDL(x) ((x) << S_VIDL)
#define G_VIDL(x) (((x) >> S_VIDL) & M_VIDL)

#define S_DMACH    0
#define M_DMACH    0xffffU
#define V_DMACH(x) ((x) << S_DMACH)
#define G_DMACH(x) (((x) >> S_DMACH) & M_DMACH)

#define A_MPS_CLS_TCAM_X_L 0xf008
#define A_MPS_CLS_TCAM_DATA2_CTL 0xf008

#define S_CTLCMDTYPE    31
#define V_CTLCMDTYPE(x) ((x) << S_CTLCMDTYPE)
#define F_CTLCMDTYPE    V_CTLCMDTYPE(1U)

#define S_CTLREQID    30
#define V_CTLREQID(x) ((x) << S_CTLREQID)
#define F_CTLREQID    V_CTLREQID(1U)

#define S_CTLTCAMSEL    25
#define V_CTLTCAMSEL(x) ((x) << S_CTLTCAMSEL)
#define F_CTLTCAMSEL    V_CTLTCAMSEL(1U)

#define S_CTLTCAMINDEX    17
#define M_CTLTCAMINDEX    0xffU
#define V_CTLTCAMINDEX(x) ((x) << S_CTLTCAMINDEX)
#define G_CTLTCAMINDEX(x) (((x) >> S_CTLTCAMINDEX) & M_CTLTCAMINDEX)

#define S_CTLXYBITSEL    16
#define V_CTLXYBITSEL(x) ((x) << S_CTLXYBITSEL)
#define F_CTLXYBITSEL    V_CTLXYBITSEL(1U)

#define S_DATAPORTNUM    12
#define M_DATAPORTNUM    0xfU
#define V_DATAPORTNUM(x) ((x) << S_DATAPORTNUM)
#define G_DATAPORTNUM(x) (((x) >> S_DATAPORTNUM) & M_DATAPORTNUM)

#define S_DATALKPTYPE    10
#define M_DATALKPTYPE    0x3U
#define V_DATALKPTYPE(x) ((x) << S_DATALKPTYPE)
#define G_DATALKPTYPE(x) (((x) >> S_DATALKPTYPE) & M_DATALKPTYPE)

#define S_DATADIPHIT    8
#define V_DATADIPHIT(x) ((x) << S_DATADIPHIT)
#define F_DATADIPHIT    V_DATADIPHIT(1U)

#define S_DATAVIDH2    7
#define V_DATAVIDH2(x) ((x) << S_DATAVIDH2)
#define F_DATAVIDH2    V_DATAVIDH2(1U)

#define S_DATAVIDH1    0
#define M_DATAVIDH1    0x7fU
#define V_DATAVIDH1(x) ((x) << S_DATAVIDH1)
#define G_DATAVIDH1(x) (((x) >> S_DATAVIDH1) & M_DATAVIDH1)

#define A_MPS_CLS_TCAM_RDATA0_REQ_ID0 0xf010
#define A_MPS_CLS_TCAM_RDATA1_REQ_ID0 0xf014
#define A_MPS_CLS_TCAM_RDATA2_REQ_ID0 0xf018
#define A_MPS_CLS_TCAM_RDATA0_REQ_ID1 0xf020
#define A_MPS_CLS_TCAM_RDATA1_REQ_ID1 0xf024
#define A_MPS_CLS_TCAM_RDATA2_REQ_ID1 0xf028
#define A_MPS_RX_PG_RSV0 0x11010

#define S_CLR_INTR    31
#define V_CLR_INTR(x) ((x) << S_CLR_INTR)
#define F_CLR_INTR    V_CLR_INTR(1U)

#define S_SET_INTR    30
#define V_SET_INTR(x) ((x) << S_SET_INTR)
#define F_SET_INTR    V_SET_INTR(1U)

#define S_USED    16
#define M_USED    0x7ffU
#define V_USED(x) ((x) << S_USED)
#define G_USED(x) (((x) >> S_USED) & M_USED)

#define S_ALLOC    0
#define M_ALLOC    0x7ffU
#define V_ALLOC(x) ((x) << S_ALLOC)
#define G_ALLOC(x) (((x) >> S_ALLOC) & M_ALLOC)

#define S_T5_USED    16
#define M_T5_USED    0xfffU
#define V_T5_USED(x) ((x) << S_T5_USED)
#define G_T5_USED(x) (((x) >> S_T5_USED) & M_T5_USED)

#define S_T5_ALLOC    0
#define M_T5_ALLOC    0xfffU
#define V_T5_ALLOC(x) ((x) << S_T5_ALLOC)
#define G_T5_ALLOC(x) (((x) >> S_T5_ALLOC) & M_T5_ALLOC)

#define A_MPS_RX_PG_RSV1 0x11014
#define A_MPS_RX_PG_RSV2 0x11018
#define A_MPS_RX_PG_RSV3 0x1101c
#define A_MPS_RX_PG_RSV4 0x11020
#define A_MPS_RX_PG_RSV5 0x11024
#define A_MPS_RX_PG_RSV6 0x11028
#define A_MPS_RX_PG_RSV7 0x1102c
#define A_MPS_RX_PERR_INT_CAUSE 0x11074

#define S_FF    23
#define V_FF(x) ((x) << S_FF)
#define F_FF    V_FF(1U)

#define S_PGMO    22
#define V_PGMO(x) ((x) << S_PGMO)
#define F_PGMO    V_PGMO(1U)

#define S_PGME    21
#define V_PGME(x) ((x) << S_PGME)
#define F_PGME    V_PGME(1U)

#define S_CHMN    20
#define V_CHMN(x) ((x) << S_CHMN)
#define F_CHMN    V_CHMN(1U)

#define S_RPLC    19
#define V_RPLC(x) ((x) << S_RPLC)
#define F_RPLC    V_RPLC(1U)

#define S_ATRB    18
#define V_ATRB(x) ((x) << S_ATRB)
#define F_ATRB    V_ATRB(1U)

#define S_PSMX    17
#define V_PSMX(x) ((x) << S_PSMX)
#define F_PSMX    V_PSMX(1U)

#define S_PGLL    16
#define V_PGLL(x) ((x) << S_PGLL)
#define F_PGLL    V_PGLL(1U)

#define S_PGFL    15
#define V_PGFL(x) ((x) << S_PGFL)
#define F_PGFL    V_PGFL(1U)

#define S_PKTQ    14
#define V_PKTQ(x) ((x) << S_PKTQ)
#define F_PKTQ    V_PKTQ(1U)

#define S_PKFL    13
#define V_PKFL(x) ((x) << S_PKFL)
#define F_PKFL    V_PKFL(1U)

#define S_PPM3    12
#define V_PPM3(x) ((x) << S_PPM3)
#define F_PPM3    V_PPM3(1U)

#define S_PPM2    11
#define V_PPM2(x) ((x) << S_PPM2)
#define F_PPM2    V_PPM2(1U)

#define S_PPM1    10
#define V_PPM1(x) ((x) << S_PPM1)
#define F_PPM1    V_PPM1(1U)

#define S_PPM0    9
#define V_PPM0(x) ((x) << S_PPM0)
#define F_PPM0    V_PPM0(1U)

#define S_SPMX    8
#define V_SPMX(x) ((x) << S_SPMX)
#define F_SPMX    V_SPMX(1U)

#define S_CDL3    7
#define V_CDL3(x) ((x) << S_CDL3)
#define F_CDL3    V_CDL3(1U)

#define S_CDL2    6
#define V_CDL2(x) ((x) << S_CDL2)
#define F_CDL2    V_CDL2(1U)

#define S_CDL1    5
#define V_CDL1(x) ((x) << S_CDL1)
#define F_CDL1    V_CDL1(1U)

#define S_CDL0    4
#define V_CDL0(x) ((x) << S_CDL0)
#define F_CDL0    V_CDL0(1U)

#define S_CDM3    3
#define V_CDM3(x) ((x) << S_CDM3)
#define F_CDM3    V_CDM3(1U)

#define S_CDM2    2
#define V_CDM2(x) ((x) << S_CDM2)
#define F_CDM2    V_CDM2(1U)

#define S_CDM1    1
#define V_CDM1(x) ((x) << S_CDM1)
#define F_CDM1    V_CDM1(1U)

#define S_CDM0    0
#define V_CDM0(x) ((x) << S_CDM0)
#define F_CDM0    V_CDM0(1U)

#define A_MPS_RX_SE_CNT_IN0 0x11148

#define S_SOP_CNT_PM    24
#define M_SOP_CNT_PM    0xffU
#define V_SOP_CNT_PM(x) ((x) << S_SOP_CNT_PM)
#define G_SOP_CNT_PM(x) (((x) >> S_SOP_CNT_PM) & M_SOP_CNT_PM)

#define S_EOP_CNT_PM    16
#define M_EOP_CNT_PM    0xffU
#define V_EOP_CNT_PM(x) ((x) << S_EOP_CNT_PM)
#define G_EOP_CNT_PM(x) (((x) >> S_EOP_CNT_PM) & M_EOP_CNT_PM)

#define S_SOP_CNT_IN    8
#define M_SOP_CNT_IN    0xffU
#define V_SOP_CNT_IN(x) ((x) << S_SOP_CNT_IN)
#define G_SOP_CNT_IN(x) (((x) >> S_SOP_CNT_IN) & M_SOP_CNT_IN)

#define S_EOP_CNT_IN    0
#define M_EOP_CNT_IN    0xffU
#define V_EOP_CNT_IN(x) ((x) << S_EOP_CNT_IN)
#define G_EOP_CNT_IN(x) (((x) >> S_EOP_CNT_IN) & M_EOP_CNT_IN)

#define A_MPS_RX_SE_CNT_IN1 0x1114c
#define A_MPS_RX_SE_CNT_IN2 0x11150
#define A_MPS_RX_SE_CNT_IN3 0x11154
#define A_MPS_RX_SE_CNT_IN4 0x11158
#define A_MPS_RX_SE_CNT_IN5 0x1115c
#define A_MPS_RX_SE_CNT_IN6 0x11160
#define A_MPS_RX_SE_CNT_IN7 0x11164
#define A_MPS_RX_SE_CNT_OUT01 0x11168

#define S_SOP_CNT_1    24
#define M_SOP_CNT_1    0xffU
#define V_SOP_CNT_1(x) ((x) << S_SOP_CNT_1)
#define G_SOP_CNT_1(x) (((x) >> S_SOP_CNT_1) & M_SOP_CNT_1)

#define S_EOP_CNT_1    16
#define M_EOP_CNT_1    0xffU
#define V_EOP_CNT_1(x) ((x) << S_EOP_CNT_1)
#define G_EOP_CNT_1(x) (((x) >> S_EOP_CNT_1) & M_EOP_CNT_1)

#define S_SOP_CNT_0    8
#define M_SOP_CNT_0    0xffU
#define V_SOP_CNT_0(x) ((x) << S_SOP_CNT_0)
#define G_SOP_CNT_0(x) (((x) >> S_SOP_CNT_0) & M_SOP_CNT_0)

#define S_EOP_CNT_0    0
#define M_EOP_CNT_0    0xffU
#define V_EOP_CNT_0(x) ((x) << S_EOP_CNT_0)
#define G_EOP_CNT_0(x) (((x) >> S_EOP_CNT_0) & M_EOP_CNT_0)

#define A_MPS_RX_SE_CNT_OUT23 0x1116c

#define S_SOP_CNT_3    24
#define M_SOP_CNT_3    0xffU
#define V_SOP_CNT_3(x) ((x) << S_SOP_CNT_3)
#define G_SOP_CNT_3(x) (((x) >> S_SOP_CNT_3) & M_SOP_CNT_3)

#define S_EOP_CNT_3    16
#define M_EOP_CNT_3    0xffU
#define V_EOP_CNT_3(x) ((x) << S_EOP_CNT_3)
#define G_EOP_CNT_3(x) (((x) >> S_EOP_CNT_3) & M_EOP_CNT_3)

#define S_SOP_CNT_2    8
#define M_SOP_CNT_2    0xffU
#define V_SOP_CNT_2(x) ((x) << S_SOP_CNT_2)
#define G_SOP_CNT_2(x) (((x) >> S_SOP_CNT_2) & M_SOP_CNT_2)

#define S_EOP_CNT_2    0
#define M_EOP_CNT_2    0xffU
#define V_EOP_CNT_2(x) ((x) << S_EOP_CNT_2)
#define G_EOP_CNT_2(x) (((x) >> S_EOP_CNT_2) & M_EOP_CNT_2)

#define A_MPS_RX_CLS_DROP_CNT0 0x11180

#define S_LPBK_CNT0    16
#define M_LPBK_CNT0    0xffffU
#define V_LPBK_CNT0(x) ((x) << S_LPBK_CNT0)
#define G_LPBK_CNT0(x) (((x) >> S_LPBK_CNT0) & M_LPBK_CNT0)

#define S_MAC_CNT0    0
#define M_MAC_CNT0    0xffffU
#define V_MAC_CNT0(x) ((x) << S_MAC_CNT0)
#define G_MAC_CNT0(x) (((x) >> S_MAC_CNT0) & M_MAC_CNT0)

#define A_MPS_RX_CLS_DROP_CNT1 0x11184

#define S_LPBK_CNT1    16
#define M_LPBK_CNT1    0xffffU
#define V_LPBK_CNT1(x) ((x) << S_LPBK_CNT1)
#define G_LPBK_CNT1(x) (((x) >> S_LPBK_CNT1) & M_LPBK_CNT1)

#define S_MAC_CNT1    0
#define M_MAC_CNT1    0xffffU
#define V_MAC_CNT1(x) ((x) << S_MAC_CNT1)
#define G_MAC_CNT1(x) (((x) >> S_MAC_CNT1) & M_MAC_CNT1)

#define A_MPS_RX_CLS_DROP_CNT2 0x11188

#define S_LPBK_CNT2    16
#define M_LPBK_CNT2    0xffffU
#define V_LPBK_CNT2(x) ((x) << S_LPBK_CNT2)
#define G_LPBK_CNT2(x) (((x) >> S_LPBK_CNT2) & M_LPBK_CNT2)

#define S_MAC_CNT2    0
#define M_MAC_CNT2    0xffffU
#define V_MAC_CNT2(x) ((x) << S_MAC_CNT2)
#define G_MAC_CNT2(x) (((x) >> S_MAC_CNT2) & M_MAC_CNT2)

#define A_MPS_RX_CLS_DROP_CNT3 0x1118c

#define S_LPBK_CNT3    16
#define M_LPBK_CNT3    0xffffU
#define V_LPBK_CNT3(x) ((x) << S_LPBK_CNT3)
#define G_LPBK_CNT3(x) (((x) >> S_LPBK_CNT3) & M_LPBK_CNT3)

#define S_MAC_CNT3    0
#define M_MAC_CNT3    0xffffU
#define V_MAC_CNT3(x) ((x) << S_MAC_CNT3)
#define G_MAC_CNT3(x) (((x) >> S_MAC_CNT3) & M_MAC_CNT3)

#define A_MPS_RX_MAC_CLS_DROP_CNT0 0x111e4
#define A_MPS_RX_MAC_CLS_DROP_CNT1 0x111e8
#define A_MPS_RX_MAC_CLS_DROP_CNT2 0x111ec
#define A_MPS_RX_MAC_CLS_DROP_CNT3 0x111f0
#define A_MPS_RX_LPBK_CLS_DROP_CNT0 0x111f4
#define A_MPS_RX_LPBK_CLS_DROP_CNT1 0x111f8
#define A_MPS_RX_LPBK_CLS_DROP_CNT2 0x111fc
#define A_MPS_RX_LPBK_CLS_DROP_CNT3 0x11200
#define A_MPS_RX_MAC_BG_PG_CNT0 0x11208

#define S_MAC_USED    16
#define M_MAC_USED    0x7ffU
#define V_MAC_USED(x) ((x) << S_MAC_USED)
#define G_MAC_USED(x) (((x) >> S_MAC_USED) & M_MAC_USED)

#define S_MAC_ALLOC    0
#define M_MAC_ALLOC    0x7ffU
#define V_MAC_ALLOC(x) ((x) << S_MAC_ALLOC)
#define G_MAC_ALLOC(x) (((x) >> S_MAC_ALLOC) & M_MAC_ALLOC)

#define A_MPS_RX_MAC_BG_PG_CNT1 0x1120c
#define A_MPS_RX_MAC_BG_PG_CNT2 0x11210
#define A_MPS_RX_MAC_BG_PG_CNT3 0x11214
#define A_MPS_RX_LPBK_BG_PG_CNT0 0x11218

#define S_LPBK_USED    16
#define M_LPBK_USED    0x7ffU
#define V_LPBK_USED(x) ((x) << S_LPBK_USED)
#define G_LPBK_USED(x) (((x) >> S_LPBK_USED) & M_LPBK_USED)

#define S_LPBK_ALLOC    0
#define M_LPBK_ALLOC    0x7ffU
#define V_LPBK_ALLOC(x) ((x) << S_LPBK_ALLOC)
#define G_LPBK_ALLOC(x) (((x) >> S_LPBK_ALLOC) & M_LPBK_ALLOC)

#define A_MPS_RX_LPBK_BG_PG_CNT1 0x1121c
#define A_MPS_RX_GRE_PROT_TYPE 0x11230

#define S_NVGRE_EN    9
#define V_NVGRE_EN(x) ((x) << S_NVGRE_EN)
#define F_NVGRE_EN    V_NVGRE_EN(1U)

#define S_GRE_EN    8
#define V_GRE_EN(x) ((x) << S_GRE_EN)
#define F_GRE_EN    V_GRE_EN(1U)

#define S_GRE    0
#define M_GRE    0xffU
#define V_GRE(x) ((x) << S_GRE)
#define G_GRE(x) (((x) >> S_GRE) & M_GRE)

#define A_MPS_RX_VXLAN_TYPE 0x11234

#define S_VXLAN_EN    16
#define V_VXLAN_EN(x) ((x) << S_VXLAN_EN)
#define F_VXLAN_EN    V_VXLAN_EN(1U)

#define S_VXLAN    0
#define M_VXLAN    0xffffU
#define V_VXLAN(x) ((x) << S_VXLAN)
#define G_VXLAN(x) (((x) >> S_VXLAN) & M_VXLAN)

#define A_MPS_RX_GENEVE_TYPE 0x11238

#define S_GENEVE_EN    16
#define V_GENEVE_EN(x) ((x) << S_GENEVE_EN)
#define F_GENEVE_EN    V_GENEVE_EN(1U)

#define S_GENEVE    0
#define M_GENEVE    0xffffU
#define V_GENEVE(x) ((x) << S_GENEVE)
#define G_GENEVE(x) (((x) >> S_GENEVE) & M_GENEVE)

#define A_MPS_RX_ENCAP_NVGRE 0x11240

#define S_ETYPE_EN    16
#define V_ETYPE_EN(x) ((x) << S_ETYPE_EN)
#define F_ETYPE_EN    V_ETYPE_EN(1U)

#define S_ETYPE    0
#define M_ETYPE    0xffffU
#define V_ETYPE(x) ((x) << S_ETYPE)
#define G_ETYPE(x) (((x) >> S_ETYPE) & M_ETYPE)

#define A_MPS_RX_ENCAP_GENEVE 0x11244

/* registers for module CPL_SWITCH */
#define CPL_SWITCH_BASE_ADDR 0x19040

#define A_CPL_INTR_ENABLE 0x19050

#define S_CIM_OP_MAP_PERR    5
#define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR)
#define F_CIM_OP_MAP_PERR    V_CIM_OP_MAP_PERR(1U)

#define S_CIM_OVFL_ERROR    4
#define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)
#define F_CIM_OVFL_ERROR    V_CIM_OVFL_ERROR(1U)

#define S_TP_FRAMING_ERROR    3
#define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR)
#define F_TP_FRAMING_ERROR    V_TP_FRAMING_ERROR(1U)

#define S_SGE_FRAMING_ERROR    2
#define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR)
#define F_SGE_FRAMING_ERROR    V_SGE_FRAMING_ERROR(1U)

#define S_CIM_FRAMING_ERROR    1
#define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR)
#define F_CIM_FRAMING_ERROR    V_CIM_FRAMING_ERROR(1U)

#define S_ZERO_SWITCH_ERROR    0
#define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
#define F_ZERO_SWITCH_ERROR    V_ZERO_SWITCH_ERROR(1U)

#define S_PERR_CPL_128TO128_1    7
#define V_PERR_CPL_128TO128_1(x) ((x) << S_PERR_CPL_128TO128_1)
#define F_PERR_CPL_128TO128_1    V_PERR_CPL_128TO128_1(1U)

#define S_PERR_CPL_128TO128_0    6
#define V_PERR_CPL_128TO128_0(x) ((x) << S_PERR_CPL_128TO128_0)
#define F_PERR_CPL_128TO128_0    V_PERR_CPL_128TO128_0(1U)

#define A_CPL_INTR_CAUSE 0x19054

/* registers for module SMB */
#define SMB_BASE_ADDR 0x19060

#define A_SMB_INT_ENABLE 0x1908c

#define S_MSTTXFIFOPAREN    21
#define V_MSTTXFIFOPAREN(x) ((x) << S_MSTTXFIFOPAREN)
#define F_MSTTXFIFOPAREN    V_MSTTXFIFOPAREN(1U)

#define S_MSTRXFIFOPAREN    20
#define V_MSTRXFIFOPAREN(x) ((x) << S_MSTRXFIFOPAREN)
#define F_MSTRXFIFOPAREN    V_MSTRXFIFOPAREN(1U)

#define S_SLVFIFOPAREN    19
#define V_SLVFIFOPAREN(x) ((x) << S_SLVFIFOPAREN)
#define F_SLVFIFOPAREN    V_SLVFIFOPAREN(1U)

#define A_SMB_INT_CAUSE 0x19090

#define S_MSTTXFIFOPARINT    21
#define V_MSTTXFIFOPARINT(x) ((x) << S_MSTTXFIFOPARINT)
#define F_MSTTXFIFOPARINT    V_MSTTXFIFOPARINT(1U)

#define S_MSTRXFIFOPARINT    20
#define V_MSTRXFIFOPARINT(x) ((x) << S_MSTRXFIFOPARINT)
#define F_MSTRXFIFOPARINT    V_MSTRXFIFOPARINT(1U)

#define S_SLVFIFOPARINT    19
#define V_SLVFIFOPARINT(x) ((x) << S_SLVFIFOPARINT)
#define F_SLVFIFOPARINT    V_SLVFIFOPARINT(1U)


/* registers for module I2CM */
#define I2CM_BASE_ADDR 0x190f0

#define A_I2CM_CFG 0x190f0

#define S_I2C_CLKDIV16B    0
#define M_I2C_CLKDIV16B    0xffffU
#define V_I2C_CLKDIV16B(x) ((x) << S_I2C_CLKDIV16B)
#define G_I2C_CLKDIV16B(x) (((x) >> S_I2C_CLKDIV16B) & M_I2C_CLKDIV16B)


/* registers for module MI */
#define MI_BASE_ADDR 0x19100


/* registers for module UART */
#define UART_BASE_ADDR 0x19110


/* registers for module PMU */
#define PMU_BASE_ADDR 0x19120


/* registers for module ULP_RX */
#define ULP_RX_BASE_ADDR 0x19150

#define A_ULP_RX_CTL 0x19150

#define S_PCMD1THRESHOLD    24
#define M_PCMD1THRESHOLD    0xffU
#define V_PCMD1THRESHOLD(x) ((x) << S_PCMD1THRESHOLD)
#define G_PCMD1THRESHOLD(x) (((x) >> S_PCMD1THRESHOLD) & M_PCMD1THRESHOLD)

#define S_PCMD0THRESHOLD    16
#define M_PCMD0THRESHOLD    0xffU
#define V_PCMD0THRESHOLD(x) ((x) << S_PCMD0THRESHOLD)
#define G_PCMD0THRESHOLD(x) (((x) >> S_PCMD0THRESHOLD) & M_PCMD0THRESHOLD)

#define S_DISABLE_0B_STAG_ERR    14
#define V_DISABLE_0B_STAG_ERR(x) ((x) << S_DISABLE_0B_STAG_ERR)
#define F_DISABLE_0B_STAG_ERR    V_DISABLE_0B_STAG_ERR(1U)

#define S_RDMA_0B_WR_OPCODE    10
#define M_RDMA_0B_WR_OPCODE    0xfU
#define V_RDMA_0B_WR_OPCODE(x) ((x) << S_RDMA_0B_WR_OPCODE)
#define G_RDMA_0B_WR_OPCODE(x) (((x) >> S_RDMA_0B_WR_OPCODE) & M_RDMA_0B_WR_OPCODE)

#define S_RDMA_0B_WR_PASS    9
#define V_RDMA_0B_WR_PASS(x) ((x) << S_RDMA_0B_WR_PASS)
#define F_RDMA_0B_WR_PASS    V_RDMA_0B_WR_PASS(1U)

#define S_STAG_RQE    8
#define V_STAG_RQE(x) ((x) << S_STAG_RQE)
#define F_STAG_RQE    V_STAG_RQE(1U)

#define S_RDMA_STATE_EN    7
#define V_RDMA_STATE_EN(x) ((x) << S_RDMA_STATE_EN)
#define F_RDMA_STATE_EN    V_RDMA_STATE_EN(1U)

#define S_CRC1_EN    6
#define V_CRC1_EN(x) ((x) << S_CRC1_EN)
#define F_CRC1_EN    V_CRC1_EN(1U)

#define S_RDMA_0B_WR_CQE    5
#define V_RDMA_0B_WR_CQE(x) ((x) << S_RDMA_0B_WR_CQE)
#define F_RDMA_0B_WR_CQE    V_RDMA_0B_WR_CQE(1U)

#define S_PCIE_ATRB_EN    4
#define V_PCIE_ATRB_EN(x) ((x) << S_PCIE_ATRB_EN)
#define F_PCIE_ATRB_EN    V_PCIE_ATRB_EN(1U)

#define S_RDMA_PERMISSIVE_MODE    3
#define V_RDMA_PERMISSIVE_MODE(x) ((x) << S_RDMA_PERMISSIVE_MODE)
#define F_RDMA_PERMISSIVE_MODE    V_RDMA_PERMISSIVE_MODE(1U)

#define S_PAGEPODME    2
#define V_PAGEPODME(x) ((x) << S_PAGEPODME)
#define F_PAGEPODME    V_PAGEPODME(1U)

#define S_ISCSITAGTCB    1
#define V_ISCSITAGTCB(x) ((x) << S_ISCSITAGTCB)
#define F_ISCSITAGTCB    V_ISCSITAGTCB(1U)

#define S_TDDPTAGTCB    0
#define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB)
#define F_TDDPTAGTCB    V_TDDPTAGTCB(1U)

#define A_ULP_RX_INT_CAUSE 0x19158

#define S_CAUSE_CTX_1    24
#define V_CAUSE_CTX_1(x) ((x) << S_CAUSE_CTX_1)
#define F_CAUSE_CTX_1    V_CAUSE_CTX_1(1U)

#define S_CAUSE_CTX_0    23
#define V_CAUSE_CTX_0(x) ((x) << S_CAUSE_CTX_0)
#define F_CAUSE_CTX_0    V_CAUSE_CTX_0(1U)

#define S_CAUSE_FF    22
#define V_CAUSE_FF(x) ((x) << S_CAUSE_FF)
#define F_CAUSE_FF    V_CAUSE_FF(1U)

#define S_CAUSE_APF_1    21
#define V_CAUSE_APF_1(x) ((x) << S_CAUSE_APF_1)
#define F_CAUSE_APF_1    V_CAUSE_APF_1(1U)

#define S_CAUSE_APF_0    20
#define V_CAUSE_APF_0(x) ((x) << S_CAUSE_APF_0)
#define F_CAUSE_APF_0    V_CAUSE_APF_0(1U)

#define S_CAUSE_AF_1    19
#define V_CAUSE_AF_1(x) ((x) << S_CAUSE_AF_1)
#define F_CAUSE_AF_1    V_CAUSE_AF_1(1U)

#define S_CAUSE_AF_0    18
#define V_CAUSE_AF_0(x) ((x) << S_CAUSE_AF_0)
#define F_CAUSE_AF_0    V_CAUSE_AF_0(1U)

#define S_CAUSE_DDPDF_1    17
#define V_CAUSE_DDPDF_1(x) ((x) << S_CAUSE_DDPDF_1)
#define F_CAUSE_DDPDF_1    V_CAUSE_DDPDF_1(1U)

#define S_CAUSE_DDPMF_1    16
#define V_CAUSE_DDPMF_1(x) ((x) << S_CAUSE_DDPMF_1)
#define F_CAUSE_DDPMF_1    V_CAUSE_DDPMF_1(1U)

#define S_CAUSE_MEMRF_1    15
#define V_CAUSE_MEMRF_1(x) ((x) << S_CAUSE_MEMRF_1)
#define F_CAUSE_MEMRF_1    V_CAUSE_MEMRF_1(1U)

#define S_CAUSE_PRSDF_1    14
#define V_CAUSE_PRSDF_1(x) ((x) << S_CAUSE_PRSDF_1)
#define F_CAUSE_PRSDF_1    V_CAUSE_PRSDF_1(1U)

#define S_CAUSE_DDPDF_0    13
#define V_CAUSE_DDPDF_0(x) ((x) << S_CAUSE_DDPDF_0)
#define F_CAUSE_DDPDF_0    V_CAUSE_DDPDF_0(1U)

#define S_CAUSE_DDPMF_0    12
#define V_CAUSE_DDPMF_0(x) ((x) << S_CAUSE_DDPMF_0)
#define F_CAUSE_DDPMF_0    V_CAUSE_DDPMF_0(1U)

#define S_CAUSE_MEMRF_0    11
#define V_CAUSE_MEMRF_0(x) ((x) << S_CAUSE_MEMRF_0)
#define F_CAUSE_MEMRF_0    V_CAUSE_MEMRF_0(1U)

#define S_CAUSE_PRSDF_0    10
#define V_CAUSE_PRSDF_0(x) ((x) << S_CAUSE_PRSDF_0)
#define F_CAUSE_PRSDF_0    V_CAUSE_PRSDF_0(1U)

#define S_CAUSE_PCMDF_1    9
#define V_CAUSE_PCMDF_1(x) ((x) << S_CAUSE_PCMDF_1)
#define F_CAUSE_PCMDF_1    V_CAUSE_PCMDF_1(1U)

#define S_CAUSE_TPTCF_1    8
#define V_CAUSE_TPTCF_1(x) ((x) << S_CAUSE_TPTCF_1)
#define F_CAUSE_TPTCF_1    V_CAUSE_TPTCF_1(1U)

#define S_CAUSE_DDPCF_1    7
#define V_CAUSE_DDPCF_1(x) ((x) << S_CAUSE_DDPCF_1)
#define F_CAUSE_DDPCF_1    V_CAUSE_DDPCF_1(1U)

#define S_CAUSE_MPARF_1    6
#define V_CAUSE_MPARF_1(x) ((x) << S_CAUSE_MPARF_1)
#define F_CAUSE_MPARF_1    V_CAUSE_MPARF_1(1U)

#define S_CAUSE_MPARC_1    5
#define V_CAUSE_MPARC_1(x) ((x) << S_CAUSE_MPARC_1)
#define F_CAUSE_MPARC_1    V_CAUSE_MPARC_1(1U)

#define S_CAUSE_PCMDF_0    4
#define V_CAUSE_PCMDF_0(x) ((x) << S_CAUSE_PCMDF_0)
#define F_CAUSE_PCMDF_0    V_CAUSE_PCMDF_0(1U)

#define S_CAUSE_TPTCF_0    3
#define V_CAUSE_TPTCF_0(x) ((x) << S_CAUSE_TPTCF_0)
#define F_CAUSE_TPTCF_0    V_CAUSE_TPTCF_0(1U)

#define S_CAUSE_DDPCF_0    2
#define V_CAUSE_DDPCF_0(x) ((x) << S_CAUSE_DDPCF_0)
#define F_CAUSE_DDPCF_0    V_CAUSE_DDPCF_0(1U)

#define S_CAUSE_MPARF_0    1
#define V_CAUSE_MPARF_0(x) ((x) << S_CAUSE_MPARF_0)
#define F_CAUSE_MPARF_0    V_CAUSE_MPARF_0(1U)

#define S_CAUSE_MPARC_0    0
#define V_CAUSE_MPARC_0(x) ((x) << S_CAUSE_MPARC_0)
#define F_CAUSE_MPARC_0    V_CAUSE_MPARC_0(1U)

#define S_SE_CNT_MISMATCH_1    26
#define V_SE_CNT_MISMATCH_1(x) ((x) << S_SE_CNT_MISMATCH_1)
#define F_SE_CNT_MISMATCH_1    V_SE_CNT_MISMATCH_1(1U)

#define S_SE_CNT_MISMATCH_0    25
#define V_SE_CNT_MISMATCH_0(x) ((x) << S_SE_CNT_MISMATCH_0)
#define F_SE_CNT_MISMATCH_0    V_SE_CNT_MISMATCH_0(1U)

#define A_ULP_RX_ISCSI_LLIMIT 0x1915c

#define S_ISCSILLIMIT    6
#define M_ISCSILLIMIT    0x3ffffffU
#define V_ISCSILLIMIT(x) ((x) << S_ISCSILLIMIT)
#define G_ISCSILLIMIT(x) (((x) >> S_ISCSILLIMIT) & M_ISCSILLIMIT)

#define A_ULP_RX_ISCSI_ULIMIT 0x19160

#define S_ISCSIULIMIT    6
#define M_ISCSIULIMIT    0x3ffffffU
#define V_ISCSIULIMIT(x) ((x) << S_ISCSIULIMIT)
#define G_ISCSIULIMIT(x) (((x) >> S_ISCSIULIMIT) & M_ISCSIULIMIT)

#define A_ULP_RX_ISCSI_TAGMASK 0x19164

#define S_ISCSITAGMASK    6
#define M_ISCSITAGMASK    0x3ffffffU
#define V_ISCSITAGMASK(x) ((x) << S_ISCSITAGMASK)
#define G_ISCSITAGMASK(x) (((x) >> S_ISCSITAGMASK) & M_ISCSITAGMASK)

#define A_ULP_RX_ISCSI_PSZ 0x19168

#define S_HPZ3    24
#define M_HPZ3    0xfU
#define V_HPZ3(x) ((x) << S_HPZ3)
#define G_HPZ3(x) (((x) >> S_HPZ3) & M_HPZ3)

#define S_HPZ2    16
#define M_HPZ2    0xfU
#define V_HPZ2(x) ((x) << S_HPZ2)
#define G_HPZ2(x) (((x) >> S_HPZ2) & M_HPZ2)

#define S_HPZ1    8
#define M_HPZ1    0xfU
#define V_HPZ1(x) ((x) << S_HPZ1)
#define G_HPZ1(x) (((x) >> S_HPZ1) & M_HPZ1)

#define S_HPZ0    0
#define M_HPZ0    0xfU
#define V_HPZ0(x) ((x) << S_HPZ0)
#define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)

#define A_ULP_RX_TDDP_LLIMIT 0x1916c

#define S_TDDPLLIMIT    6
#define M_TDDPLLIMIT    0x3ffffffU
#define V_TDDPLLIMIT(x) ((x) << S_TDDPLLIMIT)
#define G_TDDPLLIMIT(x) (((x) >> S_TDDPLLIMIT) & M_TDDPLLIMIT)

#define A_ULP_RX_TDDP_ULIMIT 0x19170

#define S_TDDPULIMIT    6
#define M_TDDPULIMIT    0x3ffffffU
#define V_TDDPULIMIT(x) ((x) << S_TDDPULIMIT)
#define G_TDDPULIMIT(x) (((x) >> S_TDDPULIMIT) & M_TDDPULIMIT)

#define A_ULP_RX_TDDP_TAGMASK 0x19174

#define S_TDDPTAGMASK    6
#define M_TDDPTAGMASK    0x3ffffffU
#define V_TDDPTAGMASK(x) ((x) << S_TDDPTAGMASK)
#define G_TDDPTAGMASK(x) (((x) >> S_TDDPTAGMASK) & M_TDDPTAGMASK)

#define A_ULP_RX_TDDP_PSZ 0x19178
#define A_ULP_RX_STAG_LLIMIT 0x1917c
#define A_ULP_RX_STAG_ULIMIT 0x19180
#define A_ULP_RX_RQ_LLIMIT 0x19184
#define A_ULP_RX_RQ_ULIMIT 0x19188
#define A_ULP_RX_PBL_LLIMIT 0x1918c
#define A_ULP_RX_PBL_ULIMIT 0x19190
#define A_ULP_RX_CTX_BASE 0x19194
#define A_ULP_RX_RQUDP_LLIMIT 0x191a4
#define A_ULP_RX_RQUDP_ULIMIT 0x191a8
#define A_ULP_RX_SE_CNT_CH0 0x191d8

#define S_SOP_CNT_OUT0    28
#define M_SOP_CNT_OUT0    0xfU
#define V_SOP_CNT_OUT0(x) ((x) << S_SOP_CNT_OUT0)
#define G_SOP_CNT_OUT0(x) (((x) >> S_SOP_CNT_OUT0) & M_SOP_CNT_OUT0)

#define S_EOP_CNT_OUT0    24
#define M_EOP_CNT_OUT0    0xfU
#define V_EOP_CNT_OUT0(x) ((x) << S_EOP_CNT_OUT0)
#define G_EOP_CNT_OUT0(x) (((x) >> S_EOP_CNT_OUT0) & M_EOP_CNT_OUT0)

#define S_SOP_CNT_AL0    20
#define M_SOP_CNT_AL0    0xfU
#define V_SOP_CNT_AL0(x) ((x) << S_SOP_CNT_AL0)
#define G_SOP_CNT_AL0(x) (((x) >> S_SOP_CNT_AL0) & M_SOP_CNT_AL0)

#define S_EOP_CNT_AL0    16
#define M_EOP_CNT_AL0    0xfU
#define V_EOP_CNT_AL0(x) ((x) << S_EOP_CNT_AL0)
#define G_EOP_CNT_AL0(x) (((x) >> S_EOP_CNT_AL0) & M_EOP_CNT_AL0)

#define S_SOP_CNT_MR0    12
#define M_SOP_CNT_MR0    0xfU
#define V_SOP_CNT_MR0(x) ((x) << S_SOP_CNT_MR0)
#define G_SOP_CNT_MR0(x) (((x) >> S_SOP_CNT_MR0) & M_SOP_CNT_MR0)

#define S_EOP_CNT_MR0    8
#define M_EOP_CNT_MR0    0xfU
#define V_EOP_CNT_MR0(x) ((x) << S_EOP_CNT_MR0)
#define G_EOP_CNT_MR0(x) (((x) >> S_EOP_CNT_MR0) & M_EOP_CNT_MR0)

#define S_SOP_CNT_IN0    4
#define M_SOP_CNT_IN0    0xfU
#define V_SOP_CNT_IN0(x) ((x) << S_SOP_CNT_IN0)
#define G_SOP_CNT_IN0(x) (((x) >> S_SOP_CNT_IN0) & M_SOP_CNT_IN0)

#define S_EOP_CNT_IN0    0
#define M_EOP_CNT_IN0    0xfU
#define V_EOP_CNT_IN0(x) ((x) << S_EOP_CNT_IN0)
#define G_EOP_CNT_IN0(x) (((x) >> S_EOP_CNT_IN0) & M_EOP_CNT_IN0)

#define A_ULP_RX_SE_CNT_CH1 0x191dc

#define S_SOP_CNT_OUT1    28
#define M_SOP_CNT_OUT1    0xfU
#define V_SOP_CNT_OUT1(x) ((x) << S_SOP_CNT_OUT1)
#define G_SOP_CNT_OUT1(x) (((x) >> S_SOP_CNT_OUT1) & M_SOP_CNT_OUT1)

#define S_EOP_CNT_OUT1    24
#define M_EOP_CNT_OUT1    0xfU
#define V_EOP_CNT_OUT1(x) ((x) << S_EOP_CNT_OUT1)
#define G_EOP_CNT_OUT1(x) (((x) >> S_EOP_CNT_OUT1) & M_EOP_CNT_OUT1)

#define S_SOP_CNT_AL1    20
#define M_SOP_CNT_AL1    0xfU
#define V_SOP_CNT_AL1(x) ((x) << S_SOP_CNT_AL1)
#define G_SOP_CNT_AL1(x) (((x) >> S_SOP_CNT_AL1) & M_SOP_CNT_AL1)

#define S_EOP_CNT_AL1    16
#define M_EOP_CNT_AL1    0xfU
#define V_EOP_CNT_AL1(x) ((x) << S_EOP_CNT_AL1)
#define G_EOP_CNT_AL1(x) (((x) >> S_EOP_CNT_AL1) & M_EOP_CNT_AL1)

#define S_SOP_CNT_MR1    12
#define M_SOP_CNT_MR1    0xfU
#define V_SOP_CNT_MR1(x) ((x) << S_SOP_CNT_MR1)
#define G_SOP_CNT_MR1(x) (((x) >> S_SOP_CNT_MR1) & M_SOP_CNT_MR1)

#define S_EOP_CNT_MR1    8
#define M_EOP_CNT_MR1    0xfU
#define V_EOP_CNT_MR1(x) ((x) << S_EOP_CNT_MR1)
#define G_EOP_CNT_MR1(x) (((x) >> S_EOP_CNT_MR1) & M_EOP_CNT_MR1)

#define S_SOP_CNT_IN1    4
#define M_SOP_CNT_IN1    0xfU
#define V_SOP_CNT_IN1(x) ((x) << S_SOP_CNT_IN1)
#define G_SOP_CNT_IN1(x) (((x) >> S_SOP_CNT_IN1) & M_SOP_CNT_IN1)

#define S_EOP_CNT_IN1    0
#define M_EOP_CNT_IN1    0xfU
#define V_EOP_CNT_IN1(x) ((x) << S_EOP_CNT_IN1)
#define G_EOP_CNT_IN1(x) (((x) >> S_EOP_CNT_IN1) & M_EOP_CNT_IN1)

#define A_ULP_RX_LA_CTL 0x1923c

#define S_TRC_SEL    0
#define V_TRC_SEL(x) ((x) << S_TRC_SEL)
#define F_TRC_SEL    V_TRC_SEL(1U)

#define A_ULP_RX_LA_RDPTR 0x19240

#define S_RD_PTR    0
#define M_RD_PTR    0x1ffU
#define V_RD_PTR(x) ((x) << S_RD_PTR)
#define G_RD_PTR(x) (((x) >> S_RD_PTR) & M_RD_PTR)

#define A_ULP_RX_LA_RDDATA 0x19244
#define A_ULP_RX_LA_WRPTR 0x19248

#define S_WR_PTR    0
#define M_WR_PTR    0x1ffU
#define V_WR_PTR(x) ((x) << S_WR_PTR)
#define G_WR_PTR(x) (((x) >> S_WR_PTR) & M_WR_PTR)

#define A_ULP_RX_LA_RESERVED 0x1924c
#define A_ULP_RX_INT_CAUSE_2 0x19270

#define S_ULPRX2MA_INTFPERR    8
#define V_ULPRX2MA_INTFPERR(x) ((x) << S_ULPRX2MA_INTFPERR)
#define F_ULPRX2MA_INTFPERR    V_ULPRX2MA_INTFPERR(1U)

#define S_ALN_SDC_ERR_1    7
#define V_ALN_SDC_ERR_1(x) ((x) << S_ALN_SDC_ERR_1)
#define F_ALN_SDC_ERR_1    V_ALN_SDC_ERR_1(1U)

#define S_ALN_SDC_ERR_0    6
#define V_ALN_SDC_ERR_0(x) ((x) << S_ALN_SDC_ERR_0)
#define F_ALN_SDC_ERR_0    V_ALN_SDC_ERR_0(1U)

#define S_PF_UNTAGGED_TPT_1    5
#define V_PF_UNTAGGED_TPT_1(x) ((x) << S_PF_UNTAGGED_TPT_1)
#define F_PF_UNTAGGED_TPT_1    V_PF_UNTAGGED_TPT_1(1U)

#define S_PF_UNTAGGED_TPT_0    4
#define V_PF_UNTAGGED_TPT_0(x) ((x) << S_PF_UNTAGGED_TPT_0)
#define F_PF_UNTAGGED_TPT_0    V_PF_UNTAGGED_TPT_0(1U)

#define S_PF_PBL_1    3
#define V_PF_PBL_1(x) ((x) << S_PF_PBL_1)
#define F_PF_PBL_1    V_PF_PBL_1(1U)

#define S_PF_PBL_0    2
#define V_PF_PBL_0(x) ((x) << S_PF_PBL_0)
#define F_PF_PBL_0    V_PF_PBL_0(1U)

#define S_DDP_HINT_1    1
#define V_DDP_HINT_1(x) ((x) << S_DDP_HINT_1)
#define F_DDP_HINT_1    V_DDP_HINT_1(1U)

#define S_DDP_HINT_0    0
#define V_DDP_HINT_0(x) ((x) << S_DDP_HINT_0)
#define F_DDP_HINT_0    V_DDP_HINT_0(1U)

#define A_ULP_RX_TLS_PP_LLIMIT 0x192a4

#define S_TLSPPLLIMIT    6
#define M_TLSPPLLIMIT    0x3ffffffU
#define V_TLSPPLLIMIT(x) ((x) << S_TLSPPLLIMIT)
#define G_TLSPPLLIMIT(x) (((x) >> S_TLSPPLLIMIT) & M_TLSPPLLIMIT)

#define A_ULP_RX_TLS_PP_ULIMIT 0x192a8

#define S_TLSPPULIMIT    6
#define M_TLSPPULIMIT    0x3ffffffU
#define V_TLSPPULIMIT(x) ((x) << S_TLSPPULIMIT)
#define G_TLSPPULIMIT(x) (((x) >> S_TLSPPULIMIT) & M_TLSPPULIMIT)

#define A_ULP_RX_TLS_KEY_LLIMIT 0x192ac

#define S_TLSKEYLLIMIT    8
#define M_TLSKEYLLIMIT    0xffffffU
#define V_TLSKEYLLIMIT(x) ((x) << S_TLSKEYLLIMIT)
#define G_TLSKEYLLIMIT(x) (((x) >> S_TLSKEYLLIMIT) & M_TLSKEYLLIMIT)

#define A_ULP_RX_TLS_KEY_ULIMIT 0x192b0

#define S_TLSKEYULIMIT    8
#define M_TLSKEYULIMIT    0xffffffU
#define V_TLSKEYULIMIT(x) ((x) << S_TLSKEYULIMIT)
#define G_TLSKEYULIMIT(x) (((x) >> S_TLSKEYULIMIT) & M_TLSKEYULIMIT)


/* registers for module SF */
#define SF_BASE_ADDR 0x193f8

#define A_SF_DATA 0x193f8
#define A_SF_OP 0x193fc

#define S_SF_LOCK    4
#define V_SF_LOCK(x) ((x) << S_SF_LOCK)
#define F_SF_LOCK    V_SF_LOCK(1U)

#define S_CONT    3
#define V_CONT(x) ((x) << S_CONT)
#define F_CONT    V_CONT(1U)

#define S_BYTECNT    1
#define M_BYTECNT    0x3U
#define V_BYTECNT(x) ((x) << S_BYTECNT)
#define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)

#define S_OP    0
#define V_OP(x) ((x) << S_OP)
#define F_OP    V_OP(1U)

/* registers for module PL */
#define PL_BASE_ADDR 0x19400

#define A_PL_VF_WHOAMI 0x0

#define S_PORTXMAP    24
#define M_PORTXMAP    0x7U
#define V_PORTXMAP(x) ((x) << S_PORTXMAP)
#define G_PORTXMAP(x) (((x) >> S_PORTXMAP) & M_PORTXMAP)

#define S_SOURCEBUS    16
#define M_SOURCEBUS    0x3U
#define V_SOURCEBUS(x) ((x) << S_SOURCEBUS)
#define G_SOURCEBUS(x) (((x) >> S_SOURCEBUS) & M_SOURCEBUS)

#define S_SOURCEPF    8
#define M_SOURCEPF    0x7U
#define V_SOURCEPF(x) ((x) << S_SOURCEPF)
#define G_SOURCEPF(x) (((x) >> S_SOURCEPF) & M_SOURCEPF)

#define S_ISVF    7
#define V_ISVF(x) ((x) << S_ISVF)
#define F_ISVF    V_ISVF(1U)

#define S_VFID    0
#define M_VFID    0x7fU
#define V_VFID(x) ((x) << S_VFID)
#define G_VFID(x) (((x) >> S_VFID) & M_VFID)

#define S_T6_SOURCEPF    9
#define M_T6_SOURCEPF    0x7U
#define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF)
#define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF)

#define S_T6_ISVF    8
#define V_T6_ISVF(x) ((x) << S_T6_ISVF)
#define F_T6_ISVF    V_T6_ISVF(1U)

#define S_T6_VFID    0
#define M_T6_VFID    0xffU
#define V_T6_VFID(x) ((x) << S_T6_VFID)
#define G_T6_VFID(x) (((x) >> S_T6_VFID) & M_T6_VFID)

#define A_PL_VF_REV 0x4

#define S_CHIPID    4
#define M_CHIPID    0xfU
#define V_CHIPID(x) ((x) << S_CHIPID)
#define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID)

#define A_PL_VF_REVISION 0x8
#define A_PL_PF_INT_CAUSE 0x3c0
#define A_PL_PF_INT_ENABLE 0x3c4

#define S_PFSW    3
#define V_PFSW(x) ((x) << S_PFSW)
#define F_PFSW    V_PFSW(1U)

#define S_PFSGE    2
#define V_PFSGE(x) ((x) << S_PFSGE)
#define F_PFSGE    V_PFSGE(1U)

#define S_PFCIM    1
#define V_PFCIM(x) ((x) << S_PFCIM)
#define F_PFCIM    V_PFCIM(1U)

#define S_PFMPS    0
#define V_PFMPS(x) ((x) << S_PFMPS)
#define F_PFMPS    V_PFMPS(1U)

#define A_PL_PF_CTL 0x3c8

#define S_SWINT    0
#define V_SWINT(x) ((x) << S_SWINT)
#define F_SWINT    V_SWINT(1U)

#define A_PL_WHOAMI 0x19400

#define S_T6_SOURCEPF    9
#define M_T6_SOURCEPF    0x7U
#define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF)
#define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF)

#define S_T6_ISVF    8
#define V_T6_ISVF(x) ((x) << S_T6_ISVF)
#define F_T6_ISVF    V_T6_ISVF(1U)

#define S_T6_VFID    0
#define M_T6_VFID    0xffU
#define V_T6_VFID(x) ((x) << S_T6_VFID)
#define G_T6_VFID(x) (((x) >> S_T6_VFID) & M_T6_VFID)

#define A_PL_INT_CAUSE 0x1940c

#define S_MC1    31
#define V_MC1(x) ((x) << S_MC1)
#define F_MC1    V_MC1(1U)

#define S_MAC3    12
#define V_MAC3(x) ((x) << S_MAC3)
#define F_MAC3    V_MAC3(1U)

#define S_MAC2    11
#define V_MAC2(x) ((x) << S_MAC2)
#define F_MAC2    V_MAC2(1U)

#define S_FLR    30
#define V_FLR(x) ((x) << S_FLR)
#define F_FLR    V_FLR(1U)

#define S_SW_CIM    29
#define V_SW_CIM(x) ((x) << S_SW_CIM)
#define F_SW_CIM    V_SW_CIM(1U)

#define S_UART    28
#define V_UART(x) ((x) << S_UART)
#define F_UART    V_UART(1U)

#define S_ULP_TX    27
#define V_ULP_TX(x) ((x) << S_ULP_TX)
#define F_ULP_TX    V_ULP_TX(1U)

#define S_SGE    26
#define V_SGE(x) ((x) << S_SGE)
#define F_SGE    V_SGE(1U)

#define S_HMA    25
#define V_HMA(x) ((x) << S_HMA)
#define F_HMA    V_HMA(1U)

#define S_CPL_SWITCH    24
#define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH)
#define F_CPL_SWITCH    V_CPL_SWITCH(1U)

#define S_ULP_RX    23
#define V_ULP_RX(x) ((x) << S_ULP_RX)
#define F_ULP_RX    V_ULP_RX(1U)

#define S_PM_RX    22
#define V_PM_RX(x) ((x) << S_PM_RX)
#define F_PM_RX    V_PM_RX(1U)

#define S_PM_TX    21
#define V_PM_TX(x) ((x) << S_PM_TX)
#define F_PM_TX    V_PM_TX(1U)

#define S_MA    20
#define V_MA(x) ((x) << S_MA)
#define F_MA    V_MA(1U)

#define S_TP    19
#define V_TP(x) ((x) << S_TP)
#define F_TP    V_TP(1U)

#define S_LE    18
#define V_LE(x) ((x) << S_LE)
#define F_LE    V_LE(1U)

#define S_EDC1    17
#define V_EDC1(x) ((x) << S_EDC1)
#define F_EDC1    V_EDC1(1U)

#define S_EDC0    16
#define V_EDC0(x) ((x) << S_EDC0)
#define F_EDC0    V_EDC0(1U)

#define S_MC0    15
#define V_MC0(x) ((x) << S_MC0)
#define F_MC0    V_MC0(1U)

#define S_PCIE    14
#define V_PCIE(x) ((x) << S_PCIE)
#define F_PCIE    V_PCIE(1U)

#define S_PMU    13
#define V_PMU(x) ((x) << S_PMU)
#define F_PMU    V_PMU(1U)

#define S_MAC1    10
#define V_MAC1(x) ((x) << S_MAC1)
#define F_MAC1    V_MAC1(1U)

#define S_MAC0    9
#define V_MAC0(x) ((x) << S_MAC0)
#define F_MAC0    V_MAC0(1U)

#define S_SMB    8
#define V_SMB(x) ((x) << S_SMB)
#define F_SMB    V_SMB(1U)

#define S_PL    6
#define V_PL(x) ((x) << S_PL)
#define F_PL    V_PL(1U)

#define S_NCSI    5
#define V_NCSI(x) ((x) << S_NCSI)
#define F_NCSI    V_NCSI(1U)

#define S_MPS    4
#define V_MPS(x) ((x) << S_MPS)
#define F_MPS    V_MPS(1U)

#define S_MI    3
#define V_MI(x) ((x) << S_MI)
#define F_MI    V_MI(1U)

#define S_DBG    2
#define V_DBG(x) ((x) << S_DBG)
#define F_DBG    V_DBG(1U)

#define S_I2CM    1
#define V_I2CM(x) ((x) << S_I2CM)
#define F_I2CM    V_I2CM(1U)

#define S_CIM    0
#define V_CIM(x) ((x) << S_CIM)
#define F_CIM    V_CIM(1U)

#define A_PL_INT_ENABLE 0x19410

#define S_SF    7
#define V_SF(x) ((x) << S_SF)
#define F_SF    V_SF(1U)

#define A_PL_INT_MAP0 0x19414

#define S_MAPNCSI    16
#define M_MAPNCSI    0x1ffU
#define V_MAPNCSI(x) ((x) << S_MAPNCSI)
#define G_MAPNCSI(x) (((x) >> S_MAPNCSI) & M_MAPNCSI)

#define S_MAPDEFAULT    0
#define M_MAPDEFAULT    0x1ffU
#define V_MAPDEFAULT(x) ((x) << S_MAPDEFAULT)
#define G_MAPDEFAULT(x) (((x) >> S_MAPDEFAULT) & M_MAPDEFAULT)

#define A_PL_RST 0x19428

#define S_FATALPERREN    3
#define V_FATALPERREN(x) ((x) << S_FATALPERREN)
#define F_FATALPERREN    V_FATALPERREN(1U)

#define S_SWINTCIM    2
#define V_SWINTCIM(x) ((x) << S_SWINTCIM)
#define F_SWINTCIM    V_SWINTCIM(1U)

#define S_PIORST    1
#define V_PIORST(x) ((x) << S_PIORST)
#define F_PIORST    V_PIORST(1U)

#define S_PIORSTMODE    0
#define V_PIORSTMODE(x) ((x) << S_PIORSTMODE)
#define F_PIORSTMODE    V_PIORSTMODE(1U)

#define S_AUTOPCIEPAUSE    4
#define V_AUTOPCIEPAUSE(x) ((x) << S_AUTOPCIEPAUSE)
#define F_AUTOPCIEPAUSE    V_AUTOPCIEPAUSE(1U)

#define A_PL_PL_INT_CAUSE 0x19430

#define S_PF_ENABLEERR    5
#define V_PF_ENABLEERR(x) ((x) << S_PF_ENABLEERR)
#define F_PF_ENABLEERR    V_PF_ENABLEERR(1U)

#define S_FATALPERR    4
#define V_FATALPERR(x) ((x) << S_FATALPERR)
#define F_FATALPERR    V_FATALPERR(1U)

#define S_INVALIDACCESS    3
#define V_INVALIDACCESS(x) ((x) << S_INVALIDACCESS)
#define F_INVALIDACCESS    V_INVALIDACCESS(1U)

#define S_TIMEOUT    2
#define V_TIMEOUT(x) ((x) << S_TIMEOUT)
#define F_TIMEOUT    V_TIMEOUT(1U)

#define S_PLERR    1
#define V_PLERR(x) ((x) << S_PLERR)
#define F_PLERR    V_PLERR(1U)

#define S_PERRVFID    0
#define V_PERRVFID(x) ((x) << S_PERRVFID)
#define F_PERRVFID    V_PERRVFID(1U)

#define S_PL_BUSPERR    6
#define V_PL_BUSPERR(x) ((x) << S_PL_BUSPERR)
#define F_PL_BUSPERR    V_PL_BUSPERR(1U)

#define A_PL_PL_INT_ENABLE 0x19434
#define A_PL_PL_PERR_ENABLE 0x19438
#define A_PL_REV 0x1943c

#define S_REV    0
#define M_REV    0xfU
#define V_REV(x) ((x) << S_REV)
#define G_REV(x) (((x) >> S_REV) & M_REV)

#define A_PL_TIMEOUT_STATUS1 0x194f8

#define S_PL_TORID    0
#define M_PL_TORID    0xffffU
#define V_PL_TORID(x) ((x) << S_PL_TORID)
#define G_PL_TORID(x) (((x) >> S_PL_TORID) & M_PL_TORID)

#define S_PL_TOVFID    0
#define M_PL_TOVFID    0xffU
#define V_PL_TOVFID(x) ((x) << S_PL_TOVFID)
#define G_PL_TOVFID(x) (((x) >> S_PL_TOVFID) & M_PL_TOVFID)

#define S_T6_PL_TOVFID    0
#define M_T6_PL_TOVFID    0x1ffU
#define V_T6_PL_TOVFID(x) ((x) << S_T6_PL_TOVFID)
#define G_T6_PL_TOVFID(x) (((x) >> S_T6_PL_TOVFID) & M_T6_PL_TOVFID)


/* registers for module LE */
#define LE_BASE_ADDR 0x19c00

#define A_LE_DB_CONFIG 0x19c04

#define S_TCAMCMDOVLAPEN    21
#define V_TCAMCMDOVLAPEN(x) ((x) << S_TCAMCMDOVLAPEN)
#define F_TCAMCMDOVLAPEN    V_TCAMCMDOVLAPEN(1U)

#define S_HASHEN    20
#define V_HASHEN(x) ((x) << S_HASHEN)
#define F_HASHEN    V_HASHEN(1U)

#define S_ASBOTHSRCHEN    18
#define V_ASBOTHSRCHEN(x) ((x) << S_ASBOTHSRCHEN)
#define F_ASBOTHSRCHEN    V_ASBOTHSRCHEN(1U)

#define S_ASLIPCOMPEN    17
#define V_ASLIPCOMPEN(x) ((x) << S_ASLIPCOMPEN)
#define F_ASLIPCOMPEN    V_ASLIPCOMPEN(1U)

#define S_BUILD    16
#define V_BUILD(x) ((x) << S_BUILD)
#define F_BUILD    V_BUILD(1U)

#define S_FILTEREN    11
#define V_FILTEREN(x) ((x) << S_FILTEREN)
#define F_FILTEREN    V_FILTEREN(1U)

#define S_SYNMODE    7
#define M_SYNMODE    0x3U
#define V_SYNMODE(x) ((x) << S_SYNMODE)
#define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE)

#define S_LEBUSEN    5
#define V_LEBUSEN(x) ((x) << S_LEBUSEN)
#define F_LEBUSEN    V_LEBUSEN(1U)

#define S_ELOOKDUMEN    4
#define V_ELOOKDUMEN(x) ((x) << S_ELOOKDUMEN)
#define F_ELOOKDUMEN    V_ELOOKDUMEN(1U)

#define S_IPV4ONLYEN    3
#define V_IPV4ONLYEN(x) ((x) << S_IPV4ONLYEN)
#define F_IPV4ONLYEN    V_IPV4ONLYEN(1U)

#define S_MOSTCMDOEN    2
#define V_MOSTCMDOEN(x) ((x) << S_MOSTCMDOEN)
#define F_MOSTCMDOEN    V_MOSTCMDOEN(1U)

#define S_DELACTSYNOEN    1
#define V_DELACTSYNOEN(x) ((x) << S_DELACTSYNOEN)
#define F_DELACTSYNOEN    V_DELACTSYNOEN(1U)

#define S_CMDOVERLAPDIS    0
#define V_CMDOVERLAPDIS(x) ((x) << S_CMDOVERLAPDIS)
#define F_CMDOVERLAPDIS    V_CMDOVERLAPDIS(1U)

#define S_MASKCMDOLAPDIS    26
#define V_MASKCMDOLAPDIS(x) ((x) << S_MASKCMDOLAPDIS)
#define F_MASKCMDOLAPDIS    V_MASKCMDOLAPDIS(1U)

#define S_IPV4HASHSIZEEN    25
#define V_IPV4HASHSIZEEN(x) ((x) << S_IPV4HASHSIZEEN)
#define F_IPV4HASHSIZEEN    V_IPV4HASHSIZEEN(1U)

#define S_PROTOCOLMASKEN    24
#define V_PROTOCOLMASKEN(x) ((x) << S_PROTOCOLMASKEN)
#define F_PROTOCOLMASKEN    V_PROTOCOLMASKEN(1U)

#define S_TUPLESIZEEN    23
#define V_TUPLESIZEEN(x) ((x) << S_TUPLESIZEEN)
#define F_TUPLESIZEEN    V_TUPLESIZEEN(1U)

#define S_SRVRSRAMEN    22
#define V_SRVRSRAMEN(x) ((x) << S_SRVRSRAMEN)
#define F_SRVRSRAMEN    V_SRVRSRAMEN(1U)

#define S_ASBOTHSRCHENPR    19
#define V_ASBOTHSRCHENPR(x) ((x) << S_ASBOTHSRCHENPR)
#define F_ASBOTHSRCHENPR    V_ASBOTHSRCHENPR(1U)

#define S_POCLIPTID0    15
#define V_POCLIPTID0(x) ((x) << S_POCLIPTID0)
#define F_POCLIPTID0    V_POCLIPTID0(1U)

#define S_TCAMARBOFF    14
#define V_TCAMARBOFF(x) ((x) << S_TCAMARBOFF)
#define F_TCAMARBOFF    V_TCAMARBOFF(1U)

#define S_ACCNTFULLEN    13
#define V_ACCNTFULLEN(x) ((x) << S_ACCNTFULLEN)
#define F_ACCNTFULLEN    V_ACCNTFULLEN(1U)

#define S_FILTERRWNOCLIP    12
#define V_FILTERRWNOCLIP(x) ((x) << S_FILTERRWNOCLIP)
#define F_FILTERRWNOCLIP    V_FILTERRWNOCLIP(1U)

#define S_CRCHASH    10
#define V_CRCHASH(x) ((x) << S_CRCHASH)
#define F_CRCHASH    V_CRCHASH(1U)

#define S_COMPTID    9
#define V_COMPTID(x) ((x) << S_COMPTID)
#define F_COMPTID    V_COMPTID(1U)

#define S_SINGLETHREAD    6
#define V_SINGLETHREAD(x) ((x) << S_SINGLETHREAD)
#define F_SINGLETHREAD    V_SINGLETHREAD(1U)

#define S_CHK_FUL_TUP_ZERO    27
#define V_CHK_FUL_TUP_ZERO(x) ((x) << S_CHK_FUL_TUP_ZERO)
#define F_CHK_FUL_TUP_ZERO    V_CHK_FUL_TUP_ZERO(1U)

#define S_PRI_HASH    26
#define V_PRI_HASH(x) ((x) << S_PRI_HASH)
#define F_PRI_HASH    V_PRI_HASH(1U)

#define S_EXTN_HASH_IPV4    25
#define V_EXTN_HASH_IPV4(x) ((x) << S_EXTN_HASH_IPV4)
#define F_EXTN_HASH_IPV4    V_EXTN_HASH_IPV4(1U)

#define S_ASLIPCOMPEN_IPV4    18
#define V_ASLIPCOMPEN_IPV4(x) ((x) << S_ASLIPCOMPEN_IPV4)
#define F_ASLIPCOMPEN_IPV4    V_ASLIPCOMPEN_IPV4(1U)

#define S_IGNR_TUP_ZERO    9
#define V_IGNR_TUP_ZERO(x) ((x) << S_IGNR_TUP_ZERO)
#define F_IGNR_TUP_ZERO    V_IGNR_TUP_ZERO(1U)

#define S_IGNR_LIP_ZERO    8
#define V_IGNR_LIP_ZERO(x) ((x) << S_IGNR_LIP_ZERO)
#define F_IGNR_LIP_ZERO    V_IGNR_LIP_ZERO(1U)

#define S_CLCAM_INIT_BUSY    7
#define V_CLCAM_INIT_BUSY(x) ((x) << S_CLCAM_INIT_BUSY)
#define F_CLCAM_INIT_BUSY    V_CLCAM_INIT_BUSY(1U)

#define S_CLCAM_INIT    6
#define V_CLCAM_INIT(x) ((x) << S_CLCAM_INIT)
#define F_CLCAM_INIT    V_CLCAM_INIT(1U)

#define S_MTCAM_INIT_BUSY    5
#define V_MTCAM_INIT_BUSY(x) ((x) << S_MTCAM_INIT_BUSY)
#define F_MTCAM_INIT_BUSY    V_MTCAM_INIT_BUSY(1U)

#define S_MTCAM_INIT    4
#define V_MTCAM_INIT(x) ((x) << S_MTCAM_INIT)
#define F_MTCAM_INIT    V_MTCAM_INIT(1U)

#define S_REGION_EN    0
#define M_REGION_EN    0xfU
#define V_REGION_EN(x) ((x) << S_REGION_EN)
#define G_REGION_EN(x) (((x) >> S_REGION_EN) & M_REGION_EN)

#define A_LE_DB_ROUTING_TABLE_INDEX 0x19c10

#define S_RTINDX    7
#define M_RTINDX    0x3fU
#define V_RTINDX(x) ((x) << S_RTINDX)
#define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX)

#define A_LE_DB_ACTIVE_TABLE_START_INDEX 0x19c10

#define S_ATINDX    0
#define M_ATINDX    0xfffffU
#define V_ATINDX(x) ((x) << S_ATINDX)
#define G_ATINDX(x) (((x) >> S_ATINDX) & M_ATINDX)

#define A_LE_DB_FILTER_TABLE_INDEX 0x19c14

#define S_FTINDX    7
#define M_FTINDX    0x3fU
#define V_FTINDX(x) ((x) << S_FTINDX)
#define G_FTINDX(x) (((x) >> S_FTINDX) & M_FTINDX)

#define A_LE_DB_NORM_FILT_TABLE_START_INDEX 0x19c14

#define S_NFTINDX    0
#define M_NFTINDX    0xfffffU
#define V_NFTINDX(x) ((x) << S_NFTINDX)
#define G_NFTINDX(x) (((x) >> S_NFTINDX) & M_NFTINDX)

#define A_LE_DB_SERVER_INDEX 0x19c18

#define S_SRINDX    7
#define M_SRINDX    0x3fU
#define V_SRINDX(x) ((x) << S_SRINDX)
#define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX)

#define A_LE_DB_SRVR_START_INDEX 0x19c18

#define S_T6_SRINDX    0
#define M_T6_SRINDX    0xfffffU
#define V_T6_SRINDX(x) ((x) << S_T6_SRINDX)
#define G_T6_SRINDX(x) (((x) >> S_T6_SRINDX) & M_T6_SRINDX)

#define A_LE_DB_CLIP_TABLE_INDEX 0x19c1c

#define S_CLIPTINDX    7
#define M_CLIPTINDX    0x3fU
#define V_CLIPTINDX(x) ((x) << S_CLIPTINDX)
#define G_CLIPTINDX(x) (((x) >> S_CLIPTINDX) & M_CLIPTINDX)

#define A_LE_DB_HPRI_FILT_TABLE_START_INDEX 0x19c1c

#define S_HFTINDX    0
#define M_HFTINDX    0xfffffU
#define V_HFTINDX(x) ((x) << S_HFTINDX)
#define G_HFTINDX(x) (((x) >> S_HFTINDX) & M_HFTINDX)

#define A_LE_DB_ACT_CNT_IPV4 0x19c20

#define S_ACTCNTIPV4    0
#define M_ACTCNTIPV4    0xfffffU
#define V_ACTCNTIPV4(x) ((x) << S_ACTCNTIPV4)
#define G_ACTCNTIPV4(x) (((x) >> S_ACTCNTIPV4) & M_ACTCNTIPV4)

#define A_LE_DB_ACT_CNT_IPV6 0x19c24

#define S_ACTCNTIPV6    0
#define M_ACTCNTIPV6    0xfffffU
#define V_ACTCNTIPV6(x) ((x) << S_ACTCNTIPV6)
#define G_ACTCNTIPV6(x) (((x) >> S_ACTCNTIPV6) & M_ACTCNTIPV6)

#define A_LE_DB_HASH_CONFIG 0x19c28

#define S_HASHTIDSIZE    16
#define M_HASHTIDSIZE    0x3fU
#define V_HASHTIDSIZE(x) ((x) << S_HASHTIDSIZE)
#define G_HASHTIDSIZE(x) (((x) >> S_HASHTIDSIZE) & M_HASHTIDSIZE)

#define S_HASHSIZE    0
#define M_HASHSIZE    0x3fU
#define V_HASHSIZE(x) ((x) << S_HASHSIZE)
#define G_HASHSIZE(x) (((x) >> S_HASHSIZE) & M_HASHSIZE)

#define A_LE_DB_HASH_TID_BASE 0x19c30
#define A_LE_DB_HASH_TBL_BASE_ADDR 0x19c30

#define S_HASHTBLADDR    4
#define M_HASHTBLADDR    0xfffffffU
#define V_HASHTBLADDR(x) ((x) << S_HASHTBLADDR)
#define G_HASHTBLADDR(x) (((x) >> S_HASHTBLADDR) & M_HASHTBLADDR)

#define A_LE_DB_INT_ENABLE 0x19c38

#define S_CLIPSUBERR    29
#define V_CLIPSUBERR(x) ((x) << S_CLIPSUBERR)
#define F_CLIPSUBERR    V_CLIPSUBERR(1U)

#define S_CLCAMFIFOERR    28
#define V_CLCAMFIFOERR(x) ((x) << S_CLCAMFIFOERR)
#define F_CLCAMFIFOERR    V_CLCAMFIFOERR(1U)

#define S_HASHTBLMEMCRCERR    27
#define V_HASHTBLMEMCRCERR(x) ((x) << S_HASHTBLMEMCRCERR)
#define F_HASHTBLMEMCRCERR    V_HASHTBLMEMCRCERR(1U)

#define S_CTCAMINVLDENT    26
#define V_CTCAMINVLDENT(x) ((x) << S_CTCAMINVLDENT)
#define F_CTCAMINVLDENT    V_CTCAMINVLDENT(1U)

#define S_TCAMINVLDENT    25
#define V_TCAMINVLDENT(x) ((x) << S_TCAMINVLDENT)
#define F_TCAMINVLDENT    V_TCAMINVLDENT(1U)

#define S_TOTCNTERR    24
#define V_TOTCNTERR(x) ((x) << S_TOTCNTERR)
#define F_TOTCNTERR    V_TOTCNTERR(1U)

#define S_CMDPRSRINTERR    23
#define V_CMDPRSRINTERR(x) ((x) << S_CMDPRSRINTERR)
#define F_CMDPRSRINTERR    V_CMDPRSRINTERR(1U)

#define S_CMDTIDERR    22
#define V_CMDTIDERR(x) ((x) << S_CMDTIDERR)
#define F_CMDTIDERR    V_CMDTIDERR(1U)

#define S_T6_ACTRGNFULL    21
#define V_T6_ACTRGNFULL(x) ((x) << S_T6_ACTRGNFULL)
#define F_T6_ACTRGNFULL    V_T6_ACTRGNFULL(1U)

#define S_T6_ACTCNTIPV6TZERO    20
#define V_T6_ACTCNTIPV6TZERO(x) ((x) << S_T6_ACTCNTIPV6TZERO)
#define F_T6_ACTCNTIPV6TZERO    V_T6_ACTCNTIPV6TZERO(1U)

#define S_T6_ACTCNTIPV4TZERO    19
#define V_T6_ACTCNTIPV4TZERO(x) ((x) << S_T6_ACTCNTIPV4TZERO)
#define F_T6_ACTCNTIPV4TZERO    V_T6_ACTCNTIPV4TZERO(1U)

#define S_T6_ACTCNTIPV6ZERO    18
#define V_T6_ACTCNTIPV6ZERO(x) ((x) << S_T6_ACTCNTIPV6ZERO)
#define F_T6_ACTCNTIPV6ZERO    V_T6_ACTCNTIPV6ZERO(1U)

#define S_T6_ACTCNTIPV4ZERO    17
#define V_T6_ACTCNTIPV4ZERO(x) ((x) << S_T6_ACTCNTIPV4ZERO)
#define F_T6_ACTCNTIPV4ZERO    V_T6_ACTCNTIPV4ZERO(1U)

#define S_MAIFWRINTPERR    16
#define V_MAIFWRINTPERR(x) ((x) << S_MAIFWRINTPERR)
#define F_MAIFWRINTPERR    V_MAIFWRINTPERR(1U)

#define S_HASHTBLMEMACCERR    15
#define V_HASHTBLMEMACCERR(x) ((x) << S_HASHTBLMEMACCERR)
#define F_HASHTBLMEMACCERR    V_HASHTBLMEMACCERR(1U)

#define S_TCAMCRCERR    14
#define V_TCAMCRCERR(x) ((x) << S_TCAMCRCERR)
#define F_TCAMCRCERR    V_TCAMCRCERR(1U)

#define S_TCAMINTPERR    13
#define V_TCAMINTPERR(x) ((x) << S_TCAMINTPERR)
#define F_TCAMINTPERR    V_TCAMINTPERR(1U)

#define S_VFSRAMPERR    12
#define V_VFSRAMPERR(x) ((x) << S_VFSRAMPERR)
#define F_VFSRAMPERR    V_VFSRAMPERR(1U)

#define S_SRVSRAMPERR    11
#define V_SRVSRAMPERR(x) ((x) << S_SRVSRAMPERR)
#define F_SRVSRAMPERR    V_SRVSRAMPERR(1U)

#define S_SSRAMINTPERR    10
#define V_SSRAMINTPERR(x) ((x) << S_SSRAMINTPERR)
#define F_SSRAMINTPERR    V_SSRAMINTPERR(1U)

#define S_CLCAMINTPERR    9
#define V_CLCAMINTPERR(x) ((x) << S_CLCAMINTPERR)
#define F_CLCAMINTPERR    V_CLCAMINTPERR(1U)

#define S_CLCAMCRCPARERR    8
#define V_CLCAMCRCPARERR(x) ((x) << S_CLCAMCRCPARERR)
#define F_CLCAMCRCPARERR    V_CLCAMCRCPARERR(1U)

#define S_HASHTBLACCFAIL    7
#define V_HASHTBLACCFAIL(x) ((x) << S_HASHTBLACCFAIL)
#define F_HASHTBLACCFAIL    V_HASHTBLACCFAIL(1U)

#define S_TCAMACCFAIL    6
#define V_TCAMACCFAIL(x) ((x) << S_TCAMACCFAIL)
#define F_TCAMACCFAIL    V_TCAMACCFAIL(1U)

#define S_SRVSRAMACCFAIL    5
#define V_SRVSRAMACCFAIL(x) ((x) << S_SRVSRAMACCFAIL)
#define F_SRVSRAMACCFAIL    V_SRVSRAMACCFAIL(1U)

#define S_CLIPTCAMACCFAIL    4
#define V_CLIPTCAMACCFAIL(x) ((x) << S_CLIPTCAMACCFAIL)
#define F_CLIPTCAMACCFAIL    V_CLIPTCAMACCFAIL(1U)

#define S_T6_UNKNOWNCMD    3
#define V_T6_UNKNOWNCMD(x) ((x) << S_T6_UNKNOWNCMD)
#define F_T6_UNKNOWNCMD    V_T6_UNKNOWNCMD(1U)

#define S_T6_LIP0    2
#define V_T6_LIP0(x) ((x) << S_T6_LIP0)
#define F_T6_LIP0    V_T6_LIP0(1U)

#define S_T6_LIPMISS    1
#define V_T6_LIPMISS(x) ((x) << S_T6_LIPMISS)
#define F_T6_LIPMISS    V_T6_LIPMISS(1U)

#define S_PIPELINEERR    0
#define V_PIPELINEERR(x) ((x) << S_PIPELINEERR)
#define F_PIPELINEERR    V_PIPELINEERR(1U)

#define A_LE_DB_INT_CAUSE 0x19c3c

#define S_REQQPARERR    16
#define V_REQQPARERR(x) ((x) << S_REQQPARERR)
#define F_REQQPARERR    V_REQQPARERR(1U)

#define S_UNKNOWNCMD    15
#define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD)
#define F_UNKNOWNCMD    V_UNKNOWNCMD(1U)

#define S_DROPFILTERHIT    13
#define V_DROPFILTERHIT(x) ((x) << S_DROPFILTERHIT)
#define F_DROPFILTERHIT    V_DROPFILTERHIT(1U)

#define S_FILTERHIT    12
#define V_FILTERHIT(x) ((x) << S_FILTERHIT)
#define F_FILTERHIT    V_FILTERHIT(1U)

#define S_SYNCOOKIEOFF    11
#define V_SYNCOOKIEOFF(x) ((x) << S_SYNCOOKIEOFF)
#define F_SYNCOOKIEOFF    V_SYNCOOKIEOFF(1U)

#define S_SYNCOOKIEBAD    10
#define V_SYNCOOKIEBAD(x) ((x) << S_SYNCOOKIEBAD)
#define F_SYNCOOKIEBAD    V_SYNCOOKIEBAD(1U)

#define S_SYNCOOKIE    9
#define V_SYNCOOKIE(x) ((x) << S_SYNCOOKIE)
#define F_SYNCOOKIE    V_SYNCOOKIE(1U)

#define S_NFASRCHFAIL    8
#define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL)
#define F_NFASRCHFAIL    V_NFASRCHFAIL(1U)

#define S_ACTRGNFULL    7
#define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL)
#define F_ACTRGNFULL    V_ACTRGNFULL(1U)

#define S_PARITYERR    6
#define V_PARITYERR(x) ((x) << S_PARITYERR)
#define F_PARITYERR    V_PARITYERR(1U)

#define S_LIPMISS    5
#define V_LIPMISS(x) ((x) << S_LIPMISS)
#define F_LIPMISS    V_LIPMISS(1U)

#define S_LIP0    4
#define V_LIP0(x) ((x) << S_LIP0)
#define F_LIP0    V_LIP0(1U)

#define S_MISS    3
#define V_MISS(x) ((x) << S_MISS)
#define F_MISS    V_MISS(1U)

#define S_ROUTINGHIT    2
#define V_ROUTINGHIT(x) ((x) << S_ROUTINGHIT)
#define F_ROUTINGHIT    V_ROUTINGHIT(1U)

#define S_ACTIVEHIT    1
#define V_ACTIVEHIT(x) ((x) << S_ACTIVEHIT)
#define F_ACTIVEHIT    V_ACTIVEHIT(1U)

#define S_SERVERHIT    0
#define V_SERVERHIT(x) ((x) << S_SERVERHIT)
#define F_SERVERHIT    V_SERVERHIT(1U)

#define S_ACTCNTIPV6TZERO    21
#define V_ACTCNTIPV6TZERO(x) ((x) << S_ACTCNTIPV6TZERO)
#define F_ACTCNTIPV6TZERO    V_ACTCNTIPV6TZERO(1U)

#define S_ACTCNTIPV4TZERO    20
#define V_ACTCNTIPV4TZERO(x) ((x) << S_ACTCNTIPV4TZERO)
#define F_ACTCNTIPV4TZERO    V_ACTCNTIPV4TZERO(1U)

#define S_ACTCNTIPV6ZERO    19
#define V_ACTCNTIPV6ZERO(x) ((x) << S_ACTCNTIPV6ZERO)
#define F_ACTCNTIPV6ZERO    V_ACTCNTIPV6ZERO(1U)

#define S_ACTCNTIPV4ZERO    18
#define V_ACTCNTIPV4ZERO(x) ((x) << S_ACTCNTIPV4ZERO)
#define F_ACTCNTIPV4ZERO    V_ACTCNTIPV4ZERO(1U)

#define S_MARSPPARERR    17
#define V_MARSPPARERR(x) ((x) << S_MARSPPARERR)
#define F_MARSPPARERR    V_MARSPPARERR(1U)

#define S_VFPARERR    14
#define V_VFPARERR(x) ((x) << S_VFPARERR)
#define F_VFPARERR    V_VFPARERR(1U)

#define S_T6_ACTRGNFULL    21
#define V_T6_ACTRGNFULL(x) ((x) << S_T6_ACTRGNFULL)
#define F_T6_ACTRGNFULL    V_T6_ACTRGNFULL(1U)

#define S_T6_ACTCNTIPV6TZERO    20
#define V_T6_ACTCNTIPV6TZERO(x) ((x) << S_T6_ACTCNTIPV6TZERO)
#define F_T6_ACTCNTIPV6TZERO    V_T6_ACTCNTIPV6TZERO(1U)

#define S_T6_ACTCNTIPV4TZERO    19
#define V_T6_ACTCNTIPV4TZERO(x) ((x) << S_T6_ACTCNTIPV4TZERO)
#define F_T6_ACTCNTIPV4TZERO    V_T6_ACTCNTIPV4TZERO(1U)

#define S_T6_ACTCNTIPV6ZERO    18
#define V_T6_ACTCNTIPV6ZERO(x) ((x) << S_T6_ACTCNTIPV6ZERO)
#define F_T6_ACTCNTIPV6ZERO    V_T6_ACTCNTIPV6ZERO(1U)

#define S_T6_ACTCNTIPV4ZERO    17
#define V_T6_ACTCNTIPV4ZERO(x) ((x) << S_T6_ACTCNTIPV4ZERO)
#define F_T6_ACTCNTIPV4ZERO    V_T6_ACTCNTIPV4ZERO(1U)

#define S_T6_UNKNOWNCMD    3
#define V_T6_UNKNOWNCMD(x) ((x) << S_T6_UNKNOWNCMD)
#define F_T6_UNKNOWNCMD    V_T6_UNKNOWNCMD(1U)

#define S_T6_LIP0    2
#define V_T6_LIP0(x) ((x) << S_T6_LIP0)
#define F_T6_LIP0    V_T6_LIP0(1U)

#define S_T6_LIPMISS    1
#define V_T6_LIPMISS(x) ((x) << S_T6_LIPMISS)
#define F_T6_LIPMISS    V_T6_LIPMISS(1U)

#define A_LE_DB_RSP_CODE_0 0x19c74

#define S_SUCCESS    25
#define M_SUCCESS    0x1fU
#define V_SUCCESS(x) ((x) << S_SUCCESS)
#define G_SUCCESS(x) (((x) >> S_SUCCESS) & M_SUCCESS)

#define S_TCAM_ACTV_SUCC    20
#define M_TCAM_ACTV_SUCC    0x1fU
#define V_TCAM_ACTV_SUCC(x) ((x) << S_TCAM_ACTV_SUCC)
#define G_TCAM_ACTV_SUCC(x) (((x) >> S_TCAM_ACTV_SUCC) & M_TCAM_ACTV_SUCC)

#define S_HASH_ACTV_SUCC    15
#define M_HASH_ACTV_SUCC    0x1fU
#define V_HASH_ACTV_SUCC(x) ((x) << S_HASH_ACTV_SUCC)
#define G_HASH_ACTV_SUCC(x) (((x) >> S_HASH_ACTV_SUCC) & M_HASH_ACTV_SUCC)

#define S_TCAM_SRVR_HIT    10
#define M_TCAM_SRVR_HIT    0x1fU
#define V_TCAM_SRVR_HIT(x) ((x) << S_TCAM_SRVR_HIT)
#define G_TCAM_SRVR_HIT(x) (((x) >> S_TCAM_SRVR_HIT) & M_TCAM_SRVR_HIT)

#define S_SRAM_SRVR_HIT    5
#define M_SRAM_SRVR_HIT    0x1fU
#define V_SRAM_SRVR_HIT(x) ((x) << S_SRAM_SRVR_HIT)
#define G_SRAM_SRVR_HIT(x) (((x) >> S_SRAM_SRVR_HIT) & M_SRAM_SRVR_HIT)

#define S_TCAM_ACTV_HIT    0
#define M_TCAM_ACTV_HIT    0x1fU
#define V_TCAM_ACTV_HIT(x) ((x) << S_TCAM_ACTV_HIT)
#define G_TCAM_ACTV_HIT(x) (((x) >> S_TCAM_ACTV_HIT) & M_TCAM_ACTV_HIT)

#define A_LE_DB_RSP_CODE_1 0x19c78

#define S_HASH_ACTV_HIT    25
#define M_HASH_ACTV_HIT    0x1fU
#define V_HASH_ACTV_HIT(x) ((x) << S_HASH_ACTV_HIT)
#define G_HASH_ACTV_HIT(x) (((x) >> S_HASH_ACTV_HIT) & M_HASH_ACTV_HIT)

#define S_T6_MISS    20
#define M_T6_MISS    0x1fU
#define V_T6_MISS(x) ((x) << S_T6_MISS)
#define G_T6_MISS(x) (((x) >> S_T6_MISS) & M_T6_MISS)

#define S_NORM_FILT_HIT    15
#define M_NORM_FILT_HIT    0x1fU
#define V_NORM_FILT_HIT(x) ((x) << S_NORM_FILT_HIT)
#define G_NORM_FILT_HIT(x) (((x) >> S_NORM_FILT_HIT) & M_NORM_FILT_HIT)

#define S_HPRI_FILT_HIT    10
#define M_HPRI_FILT_HIT    0x1fU
#define V_HPRI_FILT_HIT(x) ((x) << S_HPRI_FILT_HIT)
#define G_HPRI_FILT_HIT(x) (((x) >> S_HPRI_FILT_HIT) & M_HPRI_FILT_HIT)

#define S_ACTV_OPEN_ERR    5
#define M_ACTV_OPEN_ERR    0x1fU
#define V_ACTV_OPEN_ERR(x) ((x) << S_ACTV_OPEN_ERR)
#define G_ACTV_OPEN_ERR(x) (((x) >> S_ACTV_OPEN_ERR) & M_ACTV_OPEN_ERR)

#define S_ACTV_FULL_ERR    0
#define M_ACTV_FULL_ERR    0x1fU
#define V_ACTV_FULL_ERR(x) ((x) << S_ACTV_FULL_ERR)
#define G_ACTV_FULL_ERR(x) (((x) >> S_ACTV_FULL_ERR) & M_ACTV_FULL_ERR)

#define A_LE_DB_ACT_CNT_IPV4_TCAM 0x19c94
#define A_LE_DB_ACT_CNT_IPV6_TCAM 0x19c98
#define A_LE_ACT_CNT_THRSH 0x19c9c

#define S_ACT_CNT_THRSH    0
#define M_ACT_CNT_THRSH    0x1fffffU
#define V_ACT_CNT_THRSH(x) ((x) << S_ACT_CNT_THRSH)
#define G_ACT_CNT_THRSH(x) (((x) >> S_ACT_CNT_THRSH) & M_ACT_CNT_THRSH)

#define A_LE_DB_REQ_RSP_CNT 0x19ce4

#define S_RSPCNTLE    16
#define M_RSPCNTLE    0xffffU
#define V_RSPCNTLE(x) ((x) << S_RSPCNTLE)
#define G_RSPCNTLE(x) (((x) >> S_RSPCNTLE) & M_RSPCNTLE)

#define S_REQCNTLE    0
#define M_REQCNTLE    0xffffU
#define V_REQCNTLE(x) ((x) << S_REQCNTLE)
#define G_REQCNTLE(x) (((x) >> S_REQCNTLE) & M_REQCNTLE)

#define A_LE_DB_DBGI_CONFIG 0x19cf0

#define S_DBGICMDPERR    31
#define V_DBGICMDPERR(x) ((x) << S_DBGICMDPERR)
#define F_DBGICMDPERR    V_DBGICMDPERR(1U)

#define S_DBGICMDRANGE    22
#define M_DBGICMDRANGE    0x7U
#define V_DBGICMDRANGE(x) ((x) << S_DBGICMDRANGE)
#define G_DBGICMDRANGE(x) (((x) >> S_DBGICMDRANGE) & M_DBGICMDRANGE)

#define S_DBGICMDMSKTYPE    21
#define V_DBGICMDMSKTYPE(x) ((x) << S_DBGICMDMSKTYPE)
#define F_DBGICMDMSKTYPE    V_DBGICMDMSKTYPE(1U)

#define S_DBGICMDSEARCH    20
#define V_DBGICMDSEARCH(x) ((x) << S_DBGICMDSEARCH)
#define F_DBGICMDSEARCH    V_DBGICMDSEARCH(1U)

#define S_DBGICMDREAD    19
#define V_DBGICMDREAD(x) ((x) << S_DBGICMDREAD)
#define F_DBGICMDREAD    V_DBGICMDREAD(1U)

#define S_DBGICMDLEARN    18
#define V_DBGICMDLEARN(x) ((x) << S_DBGICMDLEARN)
#define F_DBGICMDLEARN    V_DBGICMDLEARN(1U)

#define S_DBGICMDERASE    17
#define V_DBGICMDERASE(x) ((x) << S_DBGICMDERASE)
#define F_DBGICMDERASE    V_DBGICMDERASE(1U)

#define S_DBGICMDIPV6    16
#define V_DBGICMDIPV6(x) ((x) << S_DBGICMDIPV6)
#define F_DBGICMDIPV6    V_DBGICMDIPV6(1U)

#define S_DBGICMDTYPE    13
#define M_DBGICMDTYPE    0x7U
#define V_DBGICMDTYPE(x) ((x) << S_DBGICMDTYPE)
#define G_DBGICMDTYPE(x) (((x) >> S_DBGICMDTYPE) & M_DBGICMDTYPE)

#define S_DBGICMDACKERR    12
#define V_DBGICMDACKERR(x) ((x) << S_DBGICMDACKERR)
#define F_DBGICMDACKERR    V_DBGICMDACKERR(1U)

#define S_DBGICMDBUSY    3
#define V_DBGICMDBUSY(x) ((x) << S_DBGICMDBUSY)
#define F_DBGICMDBUSY    V_DBGICMDBUSY(1U)

#define S_DBGICMDSTRT    2
#define V_DBGICMDSTRT(x) ((x) << S_DBGICMDSTRT)
#define F_DBGICMDSTRT    V_DBGICMDSTRT(1U)

#define S_DBGICMDMODE    0
#define M_DBGICMDMODE    0x3U
#define V_DBGICMDMODE(x) ((x) << S_DBGICMDMODE)
#define G_DBGICMDMODE(x) (((x) >> S_DBGICMDMODE) & M_DBGICMDMODE)

#define A_LE_DB_DBGI_REQ_TCAM_CMD 0x19cf4

#define S_DBGICMD    20
#define M_DBGICMD    0xfU
#define V_DBGICMD(x) ((x) << S_DBGICMD)
#define G_DBGICMD(x) (((x) >> S_DBGICMD) & M_DBGICMD)

#define S_DBGITINDEX    0
#define M_DBGITINDEX    0xfffffU
#define V_DBGITINDEX(x) ((x) << S_DBGITINDEX)
#define G_DBGITINDEX(x) (((x) >> S_DBGITINDEX) & M_DBGITINDEX)

#define A_LE_DB_DBGI_REQ_CMD 0x19cf4

#define S_DBGITID    0
#define M_DBGITID    0xfffffU
#define V_DBGITID(x) ((x) << S_DBGITID)
#define G_DBGITID(x) (((x) >> S_DBGITID) & M_DBGITID)

#define A_LE_PERR_ENABLE 0x19cf8

#define S_BKCHKPERIOD    22
#define M_BKCHKPERIOD    0x3ffU
#define V_BKCHKPERIOD(x) ((x) << S_BKCHKPERIOD)
#define G_BKCHKPERIOD(x) (((x) >> S_BKCHKPERIOD) & M_BKCHKPERIOD)

#define S_TCAMBKCHKEN    21
#define V_TCAMBKCHKEN(x) ((x) << S_TCAMBKCHKEN)
#define F_TCAMBKCHKEN    V_TCAMBKCHKEN(1U)

#define S_T6_CLCAMFIFOERR    2
#define V_T6_CLCAMFIFOERR(x) ((x) << S_T6_CLCAMFIFOERR)
#define F_T6_CLCAMFIFOERR    V_T6_CLCAMFIFOERR(1U)

#define S_T6_HASHTBLMEMCRCERR    1
#define V_T6_HASHTBLMEMCRCERR(x) ((x) << S_T6_HASHTBLMEMCRCERR)
#define F_T6_HASHTBLMEMCRCERR    V_T6_HASHTBLMEMCRCERR(1U)

#define A_LE_DB_DBGI_REQ_DATA 0x19d00
#define A_LE_DB_DBGI_REQ_MASK 0x19d50
#define A_LE_DB_DBGI_RSP_STATUS 0x19d94

#define S_DBGIRSPINDEX    12
#define M_DBGIRSPINDEX    0xfffffU
#define V_DBGIRSPINDEX(x) ((x) << S_DBGIRSPINDEX)
#define G_DBGIRSPINDEX(x) (((x) >> S_DBGIRSPINDEX) & M_DBGIRSPINDEX)

#define S_DBGIRSPMSG    8
#define M_DBGIRSPMSG    0xfU
#define V_DBGIRSPMSG(x) ((x) << S_DBGIRSPMSG)
#define G_DBGIRSPMSG(x) (((x) >> S_DBGIRSPMSG) & M_DBGIRSPMSG)

#define S_DBGIRSPMSGVLD    7
#define V_DBGIRSPMSGVLD(x) ((x) << S_DBGIRSPMSGVLD)
#define F_DBGIRSPMSGVLD    V_DBGIRSPMSGVLD(1U)

#define S_DBGIRSPMHIT    2
#define V_DBGIRSPMHIT(x) ((x) << S_DBGIRSPMHIT)
#define F_DBGIRSPMHIT    V_DBGIRSPMHIT(1U)

#define S_DBGIRSPHIT    1
#define V_DBGIRSPHIT(x) ((x) << S_DBGIRSPHIT)
#define F_DBGIRSPHIT    V_DBGIRSPHIT(1U)

#define S_DBGIRSPVALID    0
#define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
#define F_DBGIRSPVALID    V_DBGIRSPVALID(1U)

#define S_DBGIRSPTID    12
#define M_DBGIRSPTID    0xfffffU
#define V_DBGIRSPTID(x) ((x) << S_DBGIRSPTID)
#define G_DBGIRSPTID(x) (((x) >> S_DBGIRSPTID) & M_DBGIRSPTID)

#define S_DBGIRSPLEARN    2
#define V_DBGIRSPLEARN(x) ((x) << S_DBGIRSPLEARN)
#define F_DBGIRSPLEARN    V_DBGIRSPLEARN(1U)

#define A_LE_DBG_SEL 0x19d98
#define A_LE_DB_DBGI_RSP_DATA 0x19da0
#define A_LE_DB_TCAM_TID_BASE 0x19df0

#define S_TCAM_TID_BASE    0
#define M_TCAM_TID_BASE    0xfffffU
#define V_TCAM_TID_BASE(x) ((x) << S_TCAM_TID_BASE)
#define G_TCAM_TID_BASE(x) (((x) >> S_TCAM_TID_BASE) & M_TCAM_TID_BASE)

#define A_LE_DB_CLCAM_TID_BASE 0x19df4

#define S_CLCAM_TID_BASE    0
#define M_CLCAM_TID_BASE    0xfffffU
#define V_CLCAM_TID_BASE(x) ((x) << S_CLCAM_TID_BASE)
#define G_CLCAM_TID_BASE(x) (((x) >> S_CLCAM_TID_BASE) & M_CLCAM_TID_BASE)

#define A_LE_DB_TID_HASHBASE 0x19df8

#define S_HASHBASE_ADDR    2
#define M_HASHBASE_ADDR    0xfffffU
#define V_HASHBASE_ADDR(x) ((x) << S_HASHBASE_ADDR)
#define G_HASHBASE_ADDR(x) (((x) >> S_HASHBASE_ADDR) & M_HASHBASE_ADDR)

#define A_T6_LE_DB_HASH_TID_BASE 0x19df8

#define S_HASH_TID_BASE    0
#define M_HASH_TID_BASE    0xfffffU
#define V_HASH_TID_BASE(x) ((x) << S_HASH_TID_BASE)
#define G_HASH_TID_BASE(x) (((x) >> S_HASH_TID_BASE) & M_HASH_TID_BASE)

#define A_LE_DB_SSRAM_TID_BASE 0x19dfc

#define S_SSRAM_TID_BASE    0
#define M_SSRAM_TID_BASE    0xfffffU
#define V_SSRAM_TID_BASE(x) ((x) << S_SSRAM_TID_BASE)
#define G_SSRAM_TID_BASE(x) (((x) >> S_SSRAM_TID_BASE) & M_SSRAM_TID_BASE)

#define A_LE_DEBUG_LA_CONFIG 0x19f20
#define A_LE_REQ_DEBUG_LA_DATA 0x19f24
#define A_LE_REQ_DEBUG_LA_WRPTR 0x19f28
#define A_LE_RSP_DEBUG_LA_DATA 0x19f2c
#define A_LE_RSP_DEBUG_LA_WRPTR 0x19f30
#define A_LE_DEBUG_LA_SELECTOR 0x19f34
#define A_LE_SRVR_SRAM_INIT 0x19f34

#define S_SRVRSRAMBASE    2
#define M_SRVRSRAMBASE    0xfffffU
#define V_SRVRSRAMBASE(x) ((x) << S_SRVRSRAMBASE)
#define G_SRVRSRAMBASE(x) (((x) >> S_SRVRSRAMBASE) & M_SRVRSRAMBASE)

#define S_SRVRINITBUSY    1
#define V_SRVRINITBUSY(x) ((x) << S_SRVRINITBUSY)
#define F_SRVRINITBUSY    V_SRVRINITBUSY(1U)

#define S_SRVRINIT    0
#define V_SRVRINIT(x) ((x) << S_SRVRINIT)
#define F_SRVRINIT    V_SRVRINIT(1U)

#define A_LE_DEBUG_LA_CAPTURED_DATA 0x19f38
#define A_LE_MA_DEBUG_LA_DATA 0x19f3c
#define A_LE_RSP_DEBUG_LA_HASH_WRPTR 0x19f40
#define A_LE_HASH_DEBUG_LA_DATA 0x19f44
#define A_LE_RSP_DEBUG_LA_TCAM_WRPTR 0x19f48
#define A_LE_TCAM_DEBUG_LA_DATA 0x19f4c
#define A_LE_DEBUG_LA_CONFIGT5 0x19fd0
#define A_LE_REQ_DEBUG_LA_DATAT5 0x19fd4
#define A_LE_REQ_DEBUG_LA_WRPTRT5 0x19fd8
#define A_LE_RSP_DEBUG_LA_DATAT5 0x19fdc
#define A_LE_RSP_DEBUG_LA_WRPTRT5 0x19fe0
#define A_LE_DEBUG_LA_SEL_DATA 0x19fe4

/* registers for module NCSI */
#define NCSI_BASE_ADDR 0x1a000

#define A_NCSI_LA_RESERVED 0x1a0cc
#define A_NCSI_INT_ENABLE 0x1a0d4

#define S_CIM_DM_PRTY_ERR    8
#define V_CIM_DM_PRTY_ERR(x) ((x) << S_CIM_DM_PRTY_ERR)
#define F_CIM_DM_PRTY_ERR    V_CIM_DM_PRTY_ERR(1U)

#define S_MPS_DM_PRTY_ERR    7
#define V_MPS_DM_PRTY_ERR(x) ((x) << S_MPS_DM_PRTY_ERR)
#define F_MPS_DM_PRTY_ERR    V_MPS_DM_PRTY_ERR(1U)

#define S_TOKEN    6
#define V_TOKEN(x) ((x) << S_TOKEN)
#define F_TOKEN    V_TOKEN(1U)

#define S_ARB_DONE    5
#define V_ARB_DONE(x) ((x) << S_ARB_DONE)
#define F_ARB_DONE    V_ARB_DONE(1U)

#define S_ARB_STARTED    4
#define V_ARB_STARTED(x) ((x) << S_ARB_STARTED)
#define F_ARB_STARTED    V_ARB_STARTED(1U)

#define S_WOL    3
#define V_WOL(x) ((x) << S_WOL)
#define F_WOL    V_WOL(1U)

#define S_MACINT    2
#define V_MACINT(x) ((x) << S_MACINT)
#define F_MACINT    V_MACINT(1U)

#define S_TXFIFO_PRTY_ERR    1
#define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR)
#define F_TXFIFO_PRTY_ERR    V_TXFIFO_PRTY_ERR(1U)

#define S_RXFIFO_PRTY_ERR    0
#define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
#define F_RXFIFO_PRTY_ERR    V_RXFIFO_PRTY_ERR(1U)

#define A_NCSI_INT_CAUSE 0x1a0d8
#define A_NCSI_PERR_ENABLE 0x1a0f8

/* registers for module XGMAC */
#define XGMAC_BASE_ADDR 0x0

#define A_XGMAC_PORT_CFG 0x1000

#define S_SIGNAL_DET    14
#define V_SIGNAL_DET(x) ((x) << S_SIGNAL_DET)
#define F_SIGNAL_DET    V_SIGNAL_DET(1U)

#define A_XGMAC_PORT_INT_CAUSE 0x10dc

#define S_EXT_LOS    28
#define V_EXT_LOS(x) ((x) << S_EXT_LOS)
#define F_EXT_LOS    V_EXT_LOS(1U)

#define S_INCMPTBL_LINK    27
#define V_INCMPTBL_LINK(x) ((x) << S_INCMPTBL_LINK)
#define F_INCMPTBL_LINK    V_INCMPTBL_LINK(1U)

#define S_PATDETWAKE    26
#define V_PATDETWAKE(x) ((x) << S_PATDETWAKE)
#define F_PATDETWAKE    V_PATDETWAKE(1U)

#define S_MAGICWAKE    25
#define V_MAGICWAKE(x) ((x) << S_MAGICWAKE)
#define F_MAGICWAKE    V_MAGICWAKE(1U)

#define S_SIGDETCHG    24
#define V_SIGDETCHG(x) ((x) << S_SIGDETCHG)
#define F_SIGDETCHG    V_SIGDETCHG(1U)

#define S_PCSR_FEC_CORR    23
#define V_PCSR_FEC_CORR(x) ((x) << S_PCSR_FEC_CORR)
#define F_PCSR_FEC_CORR    V_PCSR_FEC_CORR(1U)

#define S_AE_TRAIN_LOCAL    22
#define V_AE_TRAIN_LOCAL(x) ((x) << S_AE_TRAIN_LOCAL)
#define F_AE_TRAIN_LOCAL    V_AE_TRAIN_LOCAL(1U)

#define S_HSSPLL_LOCK    21
#define V_HSSPLL_LOCK(x) ((x) << S_HSSPLL_LOCK)
#define F_HSSPLL_LOCK    V_HSSPLL_LOCK(1U)

#define S_HSSPRT_READY    20
#define V_HSSPRT_READY(x) ((x) << S_HSSPRT_READY)
#define F_HSSPRT_READY    V_HSSPRT_READY(1U)

#define S_AUTONEG_DONE    19
#define V_AUTONEG_DONE(x) ((x) << S_AUTONEG_DONE)
#define F_AUTONEG_DONE    V_AUTONEG_DONE(1U)

#define S_PCSR_HI_BER    18
#define V_PCSR_HI_BER(x) ((x) << S_PCSR_HI_BER)
#define F_PCSR_HI_BER    V_PCSR_HI_BER(1U)

#define S_PCSR_FEC_ERROR    17
#define V_PCSR_FEC_ERROR(x) ((x) << S_PCSR_FEC_ERROR)
#define F_PCSR_FEC_ERROR    V_PCSR_FEC_ERROR(1U)

#define S_PCSR_LINK_FAIL    16
#define V_PCSR_LINK_FAIL(x) ((x) << S_PCSR_LINK_FAIL)
#define F_PCSR_LINK_FAIL    V_PCSR_LINK_FAIL(1U)

#define S_XAUI_DEC_ERROR    15
#define V_XAUI_DEC_ERROR(x) ((x) << S_XAUI_DEC_ERROR)
#define F_XAUI_DEC_ERROR    V_XAUI_DEC_ERROR(1U)

#define S_XAUI_LINK_FAIL    14
#define V_XAUI_LINK_FAIL(x) ((x) << S_XAUI_LINK_FAIL)
#define F_XAUI_LINK_FAIL    V_XAUI_LINK_FAIL(1U)

#define S_PCS_CTC_ERROR    13
#define V_PCS_CTC_ERROR(x) ((x) << S_PCS_CTC_ERROR)
#define F_PCS_CTC_ERROR    V_PCS_CTC_ERROR(1U)

#define S_PCS_LINK_GOOD    12
#define V_PCS_LINK_GOOD(x) ((x) << S_PCS_LINK_GOOD)
#define F_PCS_LINK_GOOD    V_PCS_LINK_GOOD(1U)

#define S_PCS_LINK_FAIL    11
#define V_PCS_LINK_FAIL(x) ((x) << S_PCS_LINK_FAIL)
#define F_PCS_LINK_FAIL    V_PCS_LINK_FAIL(1U)

#define S_RXFIFOOVERFLOW    10
#define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW)
#define F_RXFIFOOVERFLOW    V_RXFIFOOVERFLOW(1U)

#define S_HSSPRBSERR    9
#define V_HSSPRBSERR(x) ((x) << S_HSSPRBSERR)
#define F_HSSPRBSERR    V_HSSPRBSERR(1U)

#define S_HSSEYEQUAL    8
#define V_HSSEYEQUAL(x) ((x) << S_HSSEYEQUAL)
#define F_HSSEYEQUAL    V_HSSEYEQUAL(1U)

#define S_REMOTEFAULT    7
#define V_REMOTEFAULT(x) ((x) << S_REMOTEFAULT)
#define F_REMOTEFAULT    V_REMOTEFAULT(1U)

#define S_LOCALFAULT    6
#define V_LOCALFAULT(x) ((x) << S_LOCALFAULT)
#define F_LOCALFAULT    V_LOCALFAULT(1U)

#define S_MAC_LINK_DOWN    5
#define V_MAC_LINK_DOWN(x) ((x) << S_MAC_LINK_DOWN)
#define F_MAC_LINK_DOWN    V_MAC_LINK_DOWN(1U)

#define S_MAC_LINK_UP    4
#define V_MAC_LINK_UP(x) ((x) << S_MAC_LINK_UP)
#define F_MAC_LINK_UP    V_MAC_LINK_UP(1U)

#define S_BEAN_INT    3
#define V_BEAN_INT(x) ((x) << S_BEAN_INT)
#define F_BEAN_INT    V_BEAN_INT(1U)

#define S_XGM_INT    2
#define V_XGM_INT(x) ((x) << S_XGM_INT)
#define F_XGM_INT    V_XGM_INT(1U)


/* registers for module UP */
#define UP_BASE_ADDR 0x0

#define A_UP_IBQ_0_RDADDR 0x10

#define S_QUEID    13
#define M_QUEID    0x7ffffU
#define V_QUEID(x) ((x) << S_QUEID)
#define G_QUEID(x) (((x) >> S_QUEID) & M_QUEID)

#define S_IBQRDADDR    0
#define M_IBQRDADDR    0x1fffU
#define V_IBQRDADDR(x) ((x) << S_IBQRDADDR)
#define G_IBQRDADDR(x) (((x) >> S_IBQRDADDR) & M_IBQRDADDR)

#define A_UP_IBQ_0_WRADDR 0x14

#define S_IBQWRADDR    0
#define M_IBQWRADDR    0x1fffU
#define V_IBQWRADDR(x) ((x) << S_IBQWRADDR)
#define G_IBQWRADDR(x) (((x) >> S_IBQWRADDR) & M_IBQWRADDR)

#define A_UP_IBQ_0_STATUS 0x18

#define S_QUEERRFRAME    31
#define V_QUEERRFRAME(x) ((x) << S_QUEERRFRAME)
#define F_QUEERRFRAME    V_QUEERRFRAME(1U)

#define S_QUEREMFLITS    0
#define M_QUEREMFLITS    0x7ffU
#define V_QUEREMFLITS(x) ((x) << S_QUEREMFLITS)
#define G_QUEREMFLITS(x) (((x) >> S_QUEREMFLITS) & M_QUEREMFLITS)

#define A_UP_IBQ_0_PKTCNT 0x1c

#define S_QUEEOPCNT    16
#define M_QUEEOPCNT    0xfffU
#define V_QUEEOPCNT(x) ((x) << S_QUEEOPCNT)
#define G_QUEEOPCNT(x) (((x) >> S_QUEEOPCNT) & M_QUEEOPCNT)

#define S_QUESOPCNT    0
#define M_QUESOPCNT    0xfffU
#define V_QUESOPCNT(x) ((x) << S_QUESOPCNT)
#define G_QUESOPCNT(x) (((x) >> S_QUESOPCNT) & M_QUESOPCNT)

#define A_UP_OBQ_0_RDADDR 0x70

#define S_OBQID    15
#define M_OBQID    0x1ffffU
#define V_OBQID(x) ((x) << S_OBQID)
#define G_OBQID(x) (((x) >> S_OBQID) & M_OBQID)

#define S_QUERDADDR    0
#define M_QUERDADDR    0x7fffU
#define V_QUERDADDR(x) ((x) << S_QUERDADDR)
#define G_QUERDADDR(x) (((x) >> S_QUERDADDR) & M_QUERDADDR)

#define A_UP_OBQ_0_REALADDR 0x104

#define S_QUEMEMADDR    3
#define M_QUEMEMADDR    0x7ffU
#define V_QUEMEMADDR(x) ((x) << S_QUEMEMADDR)
#define G_QUEMEMADDR(x) (((x) >> S_QUEMEMADDR) & M_QUEMEMADDR)

#define A_UP_UP_DBG_LA_CFG 0x140

#define S_UPDBGLACAPTBUB    31
#define V_UPDBGLACAPTBUB(x) ((x) << S_UPDBGLACAPTBUB)
#define F_UPDBGLACAPTBUB    V_UPDBGLACAPTBUB(1U)

#define S_UPDBGLACAPTPCONLY    30
#define V_UPDBGLACAPTPCONLY(x) ((x) << S_UPDBGLACAPTPCONLY)
#define F_UPDBGLACAPTPCONLY    V_UPDBGLACAPTPCONLY(1U)

#define S_UPDBGLAMASKSTOP    29
#define V_UPDBGLAMASKSTOP(x) ((x) << S_UPDBGLAMASKSTOP)
#define F_UPDBGLAMASKSTOP    V_UPDBGLAMASKSTOP(1U)

#define S_UPDBGLAMASKTRIG    28
#define V_UPDBGLAMASKTRIG(x) ((x) << S_UPDBGLAMASKTRIG)
#define F_UPDBGLAMASKTRIG    V_UPDBGLAMASKTRIG(1U)

#define S_UPDBGLAWRPTR    16
#define M_UPDBGLAWRPTR    0xfffU
#define V_UPDBGLAWRPTR(x) ((x) << S_UPDBGLAWRPTR)
#define G_UPDBGLAWRPTR(x) (((x) >> S_UPDBGLAWRPTR) & M_UPDBGLAWRPTR)

#define S_UPDBGLARDPTR    2
#define M_UPDBGLARDPTR    0xfffU
#define V_UPDBGLARDPTR(x) ((x) << S_UPDBGLARDPTR)
#define G_UPDBGLARDPTR(x) (((x) >> S_UPDBGLARDPTR) & M_UPDBGLARDPTR)

#define S_UPDBGLARDEN    1
#define V_UPDBGLARDEN(x) ((x) << S_UPDBGLARDEN)
#define F_UPDBGLARDEN    V_UPDBGLARDEN(1U)

#define S_UPDBGLAEN    0
#define V_UPDBGLAEN(x) ((x) << S_UPDBGLAEN)
#define F_UPDBGLAEN    V_UPDBGLAEN(1U)

#define S_UPDBGLABUSY    14
#define V_UPDBGLABUSY(x) ((x) << S_UPDBGLABUSY)
#define F_UPDBGLABUSY    V_UPDBGLABUSY(1U)

#define A_UP_UP_DBG_LA_DATA 0x144
#define A_UP_IBQ_0_SHADOW_RDADDR 0x280
#define A_UP_IBQ_0_SHADOW_WRADDR 0x284
#define A_UP_IBQ_0_SHADOW_STATUS 0x288
#define A_UP_IBQ_0_SHADOW_PKTCNT 0x28c
#define A_UP_IBQ_1_SHADOW_RDADDR 0x290
#define A_UP_IBQ_1_SHADOW_WRADDR 0x294
#define A_UP_IBQ_1_SHADOW_STATUS 0x298
#define A_UP_IBQ_1_SHADOW_PKTCNT 0x29c
#define A_UP_IBQ_2_SHADOW_RDADDR 0x2a0
#define A_UP_IBQ_2_SHADOW_WRADDR 0x2a4
#define A_UP_IBQ_2_SHADOW_STATUS 0x2a8
#define A_UP_IBQ_2_SHADOW_PKTCNT 0x2ac
#define A_UP_IBQ_3_SHADOW_RDADDR 0x2b0
#define A_UP_IBQ_3_SHADOW_WRADDR 0x2b4
#define A_UP_IBQ_3_SHADOW_STATUS 0x2b8
#define A_UP_IBQ_3_SHADOW_PKTCNT 0x2bc
#define A_UP_IBQ_4_SHADOW_RDADDR 0x2c0
#define A_UP_IBQ_4_SHADOW_WRADDR 0x2c4
#define A_UP_IBQ_4_SHADOW_STATUS 0x2c8
#define A_UP_IBQ_4_SHADOW_PKTCNT 0x2cc
#define A_UP_IBQ_5_SHADOW_RDADDR 0x2d0
#define A_UP_IBQ_5_SHADOW_WRADDR 0x2d4
#define A_UP_IBQ_5_SHADOW_STATUS 0x2d8
#define A_UP_IBQ_5_SHADOW_PKTCNT 0x2dc
#define A_UP_OBQ_0_SHADOW_RDADDR 0x2e0
#define A_UP_OBQ_0_SHADOW_WRADDR 0x2e4

#define S_QUEWRADDR    0
#define M_QUEWRADDR    0x7fffU
#define V_QUEWRADDR(x) ((x) << S_QUEWRADDR)
#define G_QUEWRADDR(x) (((x) >> S_QUEWRADDR) & M_QUEWRADDR)

#define A_UP_OBQ_0_SHADOW_STATUS 0x2e8
#define A_UP_OBQ_0_SHADOW_PKTCNT 0x2ec
#define A_UP_OBQ_1_SHADOW_RDADDR 0x2f0
#define A_UP_OBQ_1_SHADOW_WRADDR 0x2f4
#define A_UP_OBQ_1_SHADOW_STATUS 0x2f8
#define A_UP_OBQ_1_SHADOW_PKTCNT 0x2fc
#define A_UP_OBQ_2_SHADOW_RDADDR 0x300
#define A_UP_OBQ_2_SHADOW_WRADDR 0x304
#define A_UP_OBQ_2_SHADOW_STATUS 0x308
#define A_UP_OBQ_2_SHADOW_PKTCNT 0x30c
#define A_UP_OBQ_3_SHADOW_RDADDR 0x310
#define A_UP_OBQ_3_SHADOW_WRADDR 0x314
#define A_UP_OBQ_3_SHADOW_STATUS 0x318
#define A_UP_OBQ_3_SHADOW_PKTCNT 0x31c
#define A_UP_OBQ_4_SHADOW_RDADDR 0x320
#define A_UP_OBQ_4_SHADOW_WRADDR 0x324
#define A_UP_OBQ_4_SHADOW_STATUS 0x328
#define A_UP_OBQ_4_SHADOW_PKTCNT 0x32c
#define A_UP_OBQ_5_SHADOW_RDADDR 0x330
#define A_UP_OBQ_5_SHADOW_WRADDR 0x334
#define A_UP_OBQ_5_SHADOW_STATUS 0x338
#define A_UP_OBQ_5_SHADOW_PKTCNT 0x33c
#define A_UP_OBQ_6_SHADOW_RDADDR 0x340
#define A_UP_OBQ_6_SHADOW_WRADDR 0x344
#define A_UP_OBQ_6_SHADOW_STATUS 0x348
#define A_UP_OBQ_6_SHADOW_PKTCNT 0x34c
#define A_UP_OBQ_7_SHADOW_RDADDR 0x350
#define A_UP_OBQ_7_SHADOW_WRADDR 0x354
#define A_UP_OBQ_7_SHADOW_STATUS 0x358
#define A_UP_OBQ_7_SHADOW_PKTCNT 0x35c
#define A_UP_IBQ_0_SHADOW_CONFIG 0x360

#define S_QUESIZE    26
#define M_QUESIZE    0x3fU
#define V_QUESIZE(x) ((x) << S_QUESIZE)
#define G_QUESIZE(x) (((x) >> S_QUESIZE) & M_QUESIZE)

#define S_QUEBASE    8
#define M_QUEBASE    0x3fU
#define V_QUEBASE(x) ((x) << S_QUEBASE)
#define G_QUEBASE(x) (((x) >> S_QUEBASE) & M_QUEBASE)

#define S_QUEDBG8BEN    7
#define V_QUEDBG8BEN(x) ((x) << S_QUEDBG8BEN)
#define F_QUEDBG8BEN    V_QUEDBG8BEN(1U)

#define S_QUEBAREADDR    0
#define V_QUEBAREADDR(x) ((x) << S_QUEBAREADDR)
#define F_QUEBAREADDR    V_QUEBAREADDR(1U)

#define A_UP_IBQ_0_SHADOW_REALADDR 0x364

#define S_QUERDADDRWRAP    31
#define V_QUERDADDRWRAP(x) ((x) << S_QUERDADDRWRAP)
#define F_QUERDADDRWRAP    V_QUERDADDRWRAP(1U)

#define S_QUEWRADDRWRAP    30
#define V_QUEWRADDRWRAP(x) ((x) << S_QUEWRADDRWRAP)
#define F_QUEWRADDRWRAP    V_QUEWRADDRWRAP(1U)

#define A_UP_IBQ_1_SHADOW_CONFIG 0x368
#define A_UP_IBQ_1_SHADOW_REALADDR 0x36c
#define A_UP_IBQ_2_SHADOW_CONFIG 0x370
#define A_UP_IBQ_2_SHADOW_REALADDR 0x374
#define A_UP_IBQ_3_SHADOW_CONFIG 0x378
#define A_UP_IBQ_3_SHADOW_REALADDR 0x37c
#define A_UP_IBQ_4_SHADOW_CONFIG 0x380
#define A_UP_IBQ_4_SHADOW_REALADDR 0x384
#define A_UP_IBQ_5_SHADOW_CONFIG 0x388
#define A_UP_IBQ_5_SHADOW_REALADDR 0x38c
#define A_UP_OBQ_0_SHADOW_CONFIG 0x390
#define A_UP_OBQ_0_SHADOW_REALADDR 0x394
#define A_UP_OBQ_1_SHADOW_CONFIG 0x398
#define A_UP_OBQ_1_SHADOW_REALADDR 0x39c
#define A_UP_OBQ_2_SHADOW_CONFIG 0x3a0
#define A_UP_OBQ_2_SHADOW_REALADDR 0x3a4
#define A_UP_OBQ_3_SHADOW_CONFIG 0x3a8
#define A_UP_OBQ_3_SHADOW_REALADDR 0x3ac
#define A_UP_OBQ_4_SHADOW_CONFIG 0x3b0
#define A_UP_OBQ_4_SHADOW_REALADDR 0x3b4
#define A_UP_OBQ_5_SHADOW_CONFIG 0x3b8
#define A_UP_OBQ_5_SHADOW_REALADDR 0x3bc
#define A_UP_OBQ_6_SHADOW_CONFIG 0x3c0
#define A_UP_OBQ_6_SHADOW_REALADDR 0x3c4
#define A_UP_OBQ_7_SHADOW_CONFIG 0x3c8
#define A_UP_OBQ_7_SHADOW_REALADDR 0x3cc

/* registers for module CIM_CTL */
#define CIM_CTL_BASE_ADDR 0x0


/* registers for module MAC */
#define MAC_BASE_ADDR 0x0

#define A_MAC_PORT_CFG 0x800

#define S_MAC_CLK_SEL    29
#define M_MAC_CLK_SEL    0x7U
#define V_MAC_CLK_SEL(x) ((x) << S_MAC_CLK_SEL)
#define G_MAC_CLK_SEL(x) (((x) >> S_MAC_CLK_SEL) & M_MAC_CLK_SEL)

#define S_SINKTX    27
#define V_SINKTX(x) ((x) << S_SINKTX)
#define F_SINKTX    V_SINKTX(1U)

#define S_SINKTXONLINKDOWN    26
#define V_SINKTXONLINKDOWN(x) ((x) << S_SINKTXONLINKDOWN)
#define F_SINKTXONLINKDOWN    V_SINKTXONLINKDOWN(1U)

#define S_LOOPNOFWD    24
#define V_LOOPNOFWD(x) ((x) << S_LOOPNOFWD)
#define F_LOOPNOFWD    V_LOOPNOFWD(1U)

#define S_SMUX_RX_LOOP    19
#define V_SMUX_RX_LOOP(x) ((x) << S_SMUX_RX_LOOP)
#define F_SMUX_RX_LOOP    V_SMUX_RX_LOOP(1U)

#define S_RX_LANE_SWAP    18
#define V_RX_LANE_SWAP(x) ((x) << S_RX_LANE_SWAP)
#define F_RX_LANE_SWAP    V_RX_LANE_SWAP(1U)

#define S_TX_LANE_SWAP    17
#define V_TX_LANE_SWAP(x) ((x) << S_TX_LANE_SWAP)
#define F_TX_LANE_SWAP    V_TX_LANE_SWAP(1U)

#define S_SMUXTXSEL    9
#define V_SMUXTXSEL(x) ((x) << S_SMUXTXSEL)
#define F_SMUXTXSEL    V_SMUXTXSEL(1U)

#define S_SMUXRXSEL    8
#define V_SMUXRXSEL(x) ((x) << S_SMUXRXSEL)
#define F_SMUXRXSEL    V_SMUXRXSEL(1U)

#define S_PORTSPEED    4
#define M_PORTSPEED    0x3U
#define V_PORTSPEED(x) ((x) << S_PORTSPEED)
#define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED)

#define S_RX_BYTE_SWAP    3
#define V_RX_BYTE_SWAP(x) ((x) << S_RX_BYTE_SWAP)
#define F_RX_BYTE_SWAP    V_RX_BYTE_SWAP(1U)

#define S_TX_BYTE_SWAP    2
#define V_TX_BYTE_SWAP(x) ((x) << S_TX_BYTE_SWAP)
#define F_TX_BYTE_SWAP    V_TX_BYTE_SWAP(1U)

#define S_PORT_SEL    0
#define V_PORT_SEL(x) ((x) << S_PORT_SEL)
#define F_PORT_SEL    V_PORT_SEL(1U)

#define S_ENA_ERR_RSP    28
#define V_ENA_ERR_RSP(x) ((x) << S_ENA_ERR_RSP)
#define F_ENA_ERR_RSP    V_ENA_ERR_RSP(1U)

#define S_DEBUG_CLR    25
#define V_DEBUG_CLR(x) ((x) << S_DEBUG_CLR)
#define F_DEBUG_CLR    V_DEBUG_CLR(1U)

#define S_PLL_SEL    23
#define V_PLL_SEL(x) ((x) << S_PLL_SEL)
#define F_PLL_SEL    V_PLL_SEL(1U)

#define S_PORT_MAP    20
#define M_PORT_MAP    0x7U
#define V_PORT_MAP(x) ((x) << S_PORT_MAP)
#define G_PORT_MAP(x) (((x) >> S_PORT_MAP) & M_PORT_MAP)

#define S_AEC_PAT_DATA    15
#define V_AEC_PAT_DATA(x) ((x) << S_AEC_PAT_DATA)
#define F_AEC_PAT_DATA    V_AEC_PAT_DATA(1U)

#define S_MACCLK_SEL    13
#define V_MACCLK_SEL(x) ((x) << S_MACCLK_SEL)
#define F_MACCLK_SEL    V_MACCLK_SEL(1U)

#define S_XGMII_SEL    12
#define V_XGMII_SEL(x) ((x) << S_XGMII_SEL)
#define F_XGMII_SEL    V_XGMII_SEL(1U)

#define S_DEBUG_PORT_SEL    10
#define M_DEBUG_PORT_SEL    0x3U
#define V_DEBUG_PORT_SEL(x) ((x) << S_DEBUG_PORT_SEL)
#define G_DEBUG_PORT_SEL(x) (((x) >> S_DEBUG_PORT_SEL) & M_DEBUG_PORT_SEL)

#define S_ENABLE_25G    7
#define V_ENABLE_25G(x) ((x) << S_ENABLE_25G)
#define F_ENABLE_25G    V_ENABLE_25G(1U)

#define S_ENABLE_50G    6
#define V_ENABLE_50G(x) ((x) << S_ENABLE_50G)
#define F_ENABLE_50G    V_ENABLE_50G(1U)

#define S_DEBUG_TX_RX_SEL    1
#define V_DEBUG_TX_RX_SEL(x) ((x) << S_DEBUG_TX_RX_SEL)
#define F_DEBUG_TX_RX_SEL    V_DEBUG_TX_RX_SEL(1U)

#define A_MAC_PORT_RESET_CTRL 0x804

#define S_TWGDSK_HSSC16B    31
#define V_TWGDSK_HSSC16B(x) ((x) << S_TWGDSK_HSSC16B)
#define F_TWGDSK_HSSC16B    V_TWGDSK_HSSC16B(1U)

#define S_EEE_RESET    30
#define V_EEE_RESET(x) ((x) << S_EEE_RESET)
#define F_EEE_RESET    V_EEE_RESET(1U)

#define S_PTP_TIMER    29
#define V_PTP_TIMER(x) ((x) << S_PTP_TIMER)
#define F_PTP_TIMER    V_PTP_TIMER(1U)

#define S_MTIPREFRESET    28
#define V_MTIPREFRESET(x) ((x) << S_MTIPREFRESET)
#define F_MTIPREFRESET    V_MTIPREFRESET(1U)

#define S_MAC100G40G_RESET    27
#define V_MAC100G40G_RESET(x) ((x) << S_MAC100G40G_RESET)
#define F_MAC100G40G_RESET    V_MAC100G40G_RESET(1U)

#define S_MAC10G1G_RESET    26
#define V_MAC10G1G_RESET(x) ((x) << S_MAC10G1G_RESET)
#define F_MAC10G1G_RESET    V_MAC10G1G_RESET(1U)

#define S_MTIPREGRESET    25
#define V_MTIPREGRESET(x) ((x) << S_MTIPREGRESET)
#define F_MTIPREGRESET    V_MTIPREGRESET(1U)

#define S_PCS1G_RESET    24
#define V_PCS1G_RESET(x) ((x) << S_PCS1G_RESET)
#define F_PCS1G_RESET    V_PCS1G_RESET(1U)

#define S_AEC3RESET    23
#define V_AEC3RESET(x) ((x) << S_AEC3RESET)
#define F_AEC3RESET    V_AEC3RESET(1U)

#define S_AEC2RESET    22
#define V_AEC2RESET(x) ((x) << S_AEC2RESET)
#define F_AEC2RESET    V_AEC2RESET(1U)

#define S_AEC1RESET    21
#define V_AEC1RESET(x) ((x) << S_AEC1RESET)
#define F_AEC1RESET    V_AEC1RESET(1U)

#define S_AEC0RESET    20
#define V_AEC0RESET(x) ((x) << S_AEC0RESET)
#define F_AEC0RESET    V_AEC0RESET(1U)

#define S_AET3RESET    19
#define V_AET3RESET(x) ((x) << S_AET3RESET)
#define F_AET3RESET    V_AET3RESET(1U)

#define S_AET2RESET    18
#define V_AET2RESET(x) ((x) << S_AET2RESET)
#define F_AET2RESET    V_AET2RESET(1U)

#define S_AET1RESET    17
#define V_AET1RESET(x) ((x) << S_AET1RESET)
#define F_AET1RESET    V_AET1RESET(1U)

#define S_AET0RESET    16
#define V_AET0RESET(x) ((x) << S_AET0RESET)
#define F_AET0RESET    V_AET0RESET(1U)

#define S_PCS10G_RESET    15
#define V_PCS10G_RESET(x) ((x) << S_PCS10G_RESET)
#define F_PCS10G_RESET    V_PCS10G_RESET(1U)

#define S_PCS40G_RESET    14
#define V_PCS40G_RESET(x) ((x) << S_PCS40G_RESET)
#define F_PCS40G_RESET    V_PCS40G_RESET(1U)

#define S_PCS100G_RESET    13
#define V_PCS100G_RESET(x) ((x) << S_PCS100G_RESET)
#define F_PCS100G_RESET    V_PCS100G_RESET(1U)

#define S_TXIF_RESET    12
#define V_TXIF_RESET(x) ((x) << S_TXIF_RESET)
#define F_TXIF_RESET    V_TXIF_RESET(1U)

#define S_RXIF_RESET    11
#define V_RXIF_RESET(x) ((x) << S_RXIF_RESET)
#define F_RXIF_RESET    V_RXIF_RESET(1U)

#define S_AUXEXT_RESET    10
#define V_AUXEXT_RESET(x) ((x) << S_AUXEXT_RESET)
#define F_AUXEXT_RESET    V_AUXEXT_RESET(1U)

#define S_MTIPSD3TXRST    9
#define V_MTIPSD3TXRST(x) ((x) << S_MTIPSD3TXRST)
#define F_MTIPSD3TXRST    V_MTIPSD3TXRST(1U)

#define S_MTIPSD2TXRST    8
#define V_MTIPSD2TXRST(x) ((x) << S_MTIPSD2TXRST)
#define F_MTIPSD2TXRST    V_MTIPSD2TXRST(1U)

#define S_MTIPSD1TXRST    7
#define V_MTIPSD1TXRST(x) ((x) << S_MTIPSD1TXRST)
#define F_MTIPSD1TXRST    V_MTIPSD1TXRST(1U)

#define S_MTIPSD0TXRST    6
#define V_MTIPSD0TXRST(x) ((x) << S_MTIPSD0TXRST)
#define F_MTIPSD0TXRST    V_MTIPSD0TXRST(1U)

#define S_MTIPSD3RXRST    5
#define V_MTIPSD3RXRST(x) ((x) << S_MTIPSD3RXRST)
#define F_MTIPSD3RXRST    V_MTIPSD3RXRST(1U)

#define S_MTIPSD2RXRST    4
#define V_MTIPSD2RXRST(x) ((x) << S_MTIPSD2RXRST)
#define F_MTIPSD2RXRST    V_MTIPSD2RXRST(1U)

#define S_MTIPSD1RXRST    3
#define V_MTIPSD1RXRST(x) ((x) << S_MTIPSD1RXRST)
#define F_MTIPSD1RXRST    V_MTIPSD1RXRST(1U)

#define S_WOL_RESET    2
#define V_WOL_RESET(x) ((x) << S_WOL_RESET)
#define F_WOL_RESET    V_WOL_RESET(1U)

#define S_MTIPSD0RXRST    1
#define V_MTIPSD0RXRST(x) ((x) << S_MTIPSD0RXRST)
#define F_MTIPSD0RXRST    V_MTIPSD0RXRST(1U)

#define S_HSS_RESET    0
#define V_HSS_RESET(x) ((x) << S_HSS_RESET)
#define F_HSS_RESET    V_HSS_RESET(1U)

#define A_MAC_PORT_PKT_COUNT 0x81c

#define S_TX_SOP_COUNT    24
#define M_TX_SOP_COUNT    0xffU
#define V_TX_SOP_COUNT(x) ((x) << S_TX_SOP_COUNT)
#define G_TX_SOP_COUNT(x) (((x) >> S_TX_SOP_COUNT) & M_TX_SOP_COUNT)

#define S_TX_EOP_COUNT    16
#define M_TX_EOP_COUNT    0xffU
#define V_TX_EOP_COUNT(x) ((x) << S_TX_EOP_COUNT)
#define G_TX_EOP_COUNT(x) (((x) >> S_TX_EOP_COUNT) & M_TX_EOP_COUNT)

#define S_RX_SOP_COUNT    8
#define M_RX_SOP_COUNT    0xffU
#define V_RX_SOP_COUNT(x) ((x) << S_RX_SOP_COUNT)
#define G_RX_SOP_COUNT(x) (((x) >> S_RX_SOP_COUNT) & M_RX_SOP_COUNT)

#define S_RX_EOP_COUNT    0
#define M_RX_EOP_COUNT    0xffU
#define V_RX_EOP_COUNT(x) ((x) << S_RX_EOP_COUNT)
#define G_RX_EOP_COUNT(x) (((x) >> S_RX_EOP_COUNT) & M_RX_EOP_COUNT)

#define A_MAC_PORT_MTIP_RESET_CTRL 0x82c

#define S_AN_RESET_SD_TX_CLK    31
#define V_AN_RESET_SD_TX_CLK(x) ((x) << S_AN_RESET_SD_TX_CLK)
#define F_AN_RESET_SD_TX_CLK    V_AN_RESET_SD_TX_CLK(1U)

#define S_AN_RESET_SD_RX_CLK    30
#define V_AN_RESET_SD_RX_CLK(x) ((x) << S_AN_RESET_SD_RX_CLK)
#define F_AN_RESET_SD_RX_CLK    V_AN_RESET_SD_RX_CLK(1U)

#define S_SGMII_RESET_TX_CLK    29
#define V_SGMII_RESET_TX_CLK(x) ((x) << S_SGMII_RESET_TX_CLK)
#define F_SGMII_RESET_TX_CLK    V_SGMII_RESET_TX_CLK(1U)

#define S_SGMII_RESET_RX_CLK    28
#define V_SGMII_RESET_RX_CLK(x) ((x) << S_SGMII_RESET_RX_CLK)
#define F_SGMII_RESET_RX_CLK    V_SGMII_RESET_RX_CLK(1U)

#define S_SGMII_RESET_REF_CLK    27
#define V_SGMII_RESET_REF_CLK(x) ((x) << S_SGMII_RESET_REF_CLK)
#define F_SGMII_RESET_REF_CLK    V_SGMII_RESET_REF_CLK(1U)

#define S_PCS10G_RESET_XFI_RXCLK    26
#define V_PCS10G_RESET_XFI_RXCLK(x) ((x) << S_PCS10G_RESET_XFI_RXCLK)
#define F_PCS10G_RESET_XFI_RXCLK    V_PCS10G_RESET_XFI_RXCLK(1U)

#define S_PCS10G_RESET_XFI_TXCLK    25
#define V_PCS10G_RESET_XFI_TXCLK(x) ((x) << S_PCS10G_RESET_XFI_TXCLK)
#define F_PCS10G_RESET_XFI_TXCLK    V_PCS10G_RESET_XFI_TXCLK(1U)

#define S_PCS10G_RESET_SD_TX_CLK    24
#define V_PCS10G_RESET_SD_TX_CLK(x) ((x) << S_PCS10G_RESET_SD_TX_CLK)
#define F_PCS10G_RESET_SD_TX_CLK    V_PCS10G_RESET_SD_TX_CLK(1U)

#define S_PCS10G_RESET_SD_RX_CLK    23
#define V_PCS10G_RESET_SD_RX_CLK(x) ((x) << S_PCS10G_RESET_SD_RX_CLK)
#define F_PCS10G_RESET_SD_RX_CLK    V_PCS10G_RESET_SD_RX_CLK(1U)

#define S_PCS40G_RESET_RXCLK    22
#define V_PCS40G_RESET_RXCLK(x) ((x) << S_PCS40G_RESET_RXCLK)
#define F_PCS40G_RESET_RXCLK    V_PCS40G_RESET_RXCLK(1U)

#define S_PCS40G_RESET_SD_TX_CLK    21
#define V_PCS40G_RESET_SD_TX_CLK(x) ((x) << S_PCS40G_RESET_SD_TX_CLK)
#define F_PCS40G_RESET_SD_TX_CLK    V_PCS40G_RESET_SD_TX_CLK(1U)

#define S_PCS40G_RESET_SD0_RX_CLK    20
#define V_PCS40G_RESET_SD0_RX_CLK(x) ((x) << S_PCS40G_RESET_SD0_RX_CLK)
#define F_PCS40G_RESET_SD0_RX_CLK    V_PCS40G_RESET_SD0_RX_CLK(1U)

#define S_PCS40G_RESET_SD1_RX_CLK    19
#define V_PCS40G_RESET_SD1_RX_CLK(x) ((x) << S_PCS40G_RESET_SD1_RX_CLK)
#define F_PCS40G_RESET_SD1_RX_CLK    V_PCS40G_RESET_SD1_RX_CLK(1U)

#define S_PCS40G_RESET_SD2_RX_CLK    18
#define V_PCS40G_RESET_SD2_RX_CLK(x) ((x) << S_PCS40G_RESET_SD2_RX_CLK)
#define F_PCS40G_RESET_SD2_RX_CLK    V_PCS40G_RESET_SD2_RX_CLK(1U)

#define S_PCS40G_RESET_SD3_RX_CLK    17
#define V_PCS40G_RESET_SD3_RX_CLK(x) ((x) << S_PCS40G_RESET_SD3_RX_CLK)
#define F_PCS40G_RESET_SD3_RX_CLK    V_PCS40G_RESET_SD3_RX_CLK(1U)

#define S_PCS100G_RESET_CGMII_RXCLK    16
#define V_PCS100G_RESET_CGMII_RXCLK(x) ((x) << S_PCS100G_RESET_CGMII_RXCLK)
#define F_PCS100G_RESET_CGMII_RXCLK    V_PCS100G_RESET_CGMII_RXCLK(1U)

#define S_PCS100G_RESET_CGMII_TXCLK    15
#define V_PCS100G_RESET_CGMII_TXCLK(x) ((x) << S_PCS100G_RESET_CGMII_TXCLK)
#define F_PCS100G_RESET_CGMII_TXCLK    V_PCS100G_RESET_CGMII_TXCLK(1U)

#define S_PCS100G_RESET_TX_CLK    14
#define V_PCS100G_RESET_TX_CLK(x) ((x) << S_PCS100G_RESET_TX_CLK)
#define F_PCS100G_RESET_TX_CLK    V_PCS100G_RESET_TX_CLK(1U)

#define S_PCS100G_RESET_SD0_RX_CLK    13
#define V_PCS100G_RESET_SD0_RX_CLK(x) ((x) << S_PCS100G_RESET_SD0_RX_CLK)
#define F_PCS100G_RESET_SD0_RX_CLK    V_PCS100G_RESET_SD0_RX_CLK(1U)

#define S_PCS100G_RESET_SD1_RX_CLK    12
#define V_PCS100G_RESET_SD1_RX_CLK(x) ((x) << S_PCS100G_RESET_SD1_RX_CLK)
#define F_PCS100G_RESET_SD1_RX_CLK    V_PCS100G_RESET_SD1_RX_CLK(1U)

#define S_PCS100G_RESET_SD2_RX_CLK    11
#define V_PCS100G_RESET_SD2_RX_CLK(x) ((x) << S_PCS100G_RESET_SD2_RX_CLK)
#define F_PCS100G_RESET_SD2_RX_CLK    V_PCS100G_RESET_SD2_RX_CLK(1U)

#define S_PCS100G_RESET_SD3_RX_CLK    10
#define V_PCS100G_RESET_SD3_RX_CLK(x) ((x) << S_PCS100G_RESET_SD3_RX_CLK)
#define F_PCS100G_RESET_SD3_RX_CLK    V_PCS100G_RESET_SD3_RX_CLK(1U)

#define S_MAC40G100G_RESET_TXCLK    9
#define V_MAC40G100G_RESET_TXCLK(x) ((x) << S_MAC40G100G_RESET_TXCLK)
#define F_MAC40G100G_RESET_TXCLK    V_MAC40G100G_RESET_TXCLK(1U)

#define S_MAC40G100G_RESET_RXCLK    8
#define V_MAC40G100G_RESET_RXCLK(x) ((x) << S_MAC40G100G_RESET_RXCLK)
#define F_MAC40G100G_RESET_RXCLK    V_MAC40G100G_RESET_RXCLK(1U)

#define S_MAC40G100G_RESET_FF_TX_CLK    7
#define V_MAC40G100G_RESET_FF_TX_CLK(x) ((x) << S_MAC40G100G_RESET_FF_TX_CLK)
#define F_MAC40G100G_RESET_FF_TX_CLK    V_MAC40G100G_RESET_FF_TX_CLK(1U)

#define S_MAC40G100G_RESET_FF_RX_CLK    6
#define V_MAC40G100G_RESET_FF_RX_CLK(x) ((x) << S_MAC40G100G_RESET_FF_RX_CLK)
#define F_MAC40G100G_RESET_FF_RX_CLK    V_MAC40G100G_RESET_FF_RX_CLK(1U)

#define S_MAC40G100G_RESET_TS_CLK    5
#define V_MAC40G100G_RESET_TS_CLK(x) ((x) << S_MAC40G100G_RESET_TS_CLK)
#define F_MAC40G100G_RESET_TS_CLK    V_MAC40G100G_RESET_TS_CLK(1U)

#define S_MAC1G10G_RESET_RXCLK    4
#define V_MAC1G10G_RESET_RXCLK(x) ((x) << S_MAC1G10G_RESET_RXCLK)
#define F_MAC1G10G_RESET_RXCLK    V_MAC1G10G_RESET_RXCLK(1U)

#define S_MAC1G10G_RESET_TXCLK    3
#define V_MAC1G10G_RESET_TXCLK(x) ((x) << S_MAC1G10G_RESET_TXCLK)
#define F_MAC1G10G_RESET_TXCLK    V_MAC1G10G_RESET_TXCLK(1U)

#define S_MAC1G10G_RESET_FF_RX_CLK    2
#define V_MAC1G10G_RESET_FF_RX_CLK(x) ((x) << S_MAC1G10G_RESET_FF_RX_CLK)
#define F_MAC1G10G_RESET_FF_RX_CLK    V_MAC1G10G_RESET_FF_RX_CLK(1U)

#define S_MAC1G10G_RESET_FF_TX_CLK    1
#define V_MAC1G10G_RESET_FF_TX_CLK(x) ((x) << S_MAC1G10G_RESET_FF_TX_CLK)
#define F_MAC1G10G_RESET_FF_TX_CLK    V_MAC1G10G_RESET_FF_TX_CLK(1U)

#define S_XGMII_CLK_RESET    0
#define V_XGMII_CLK_RESET(x) ((x) << S_XGMII_CLK_RESET)
#define F_XGMII_CLK_RESET    V_XGMII_CLK_RESET(1U)

#define A_MAC_PORT_MTIP_GATE_CTRL 0x830

#define S_AN_GATE_SD_TX_CLK    31
#define V_AN_GATE_SD_TX_CLK(x) ((x) << S_AN_GATE_SD_TX_CLK)
#define F_AN_GATE_SD_TX_CLK    V_AN_GATE_SD_TX_CLK(1U)

#define S_AN_GATE_SD_RX_CLK    30
#define V_AN_GATE_SD_RX_CLK(x) ((x) << S_AN_GATE_SD_RX_CLK)
#define F_AN_GATE_SD_RX_CLK    V_AN_GATE_SD_RX_CLK(1U)

#define S_SGMII_GATE_TX_CLK    29
#define V_SGMII_GATE_TX_CLK(x) ((x) << S_SGMII_GATE_TX_CLK)
#define F_SGMII_GATE_TX_CLK    V_SGMII_GATE_TX_CLK(1U)

#define S_SGMII_GATE_RX_CLK    28
#define V_SGMII_GATE_RX_CLK(x) ((x) << S_SGMII_GATE_RX_CLK)
#define F_SGMII_GATE_RX_CLK    V_SGMII_GATE_RX_CLK(1U)

#define S_SGMII_GATE_REF_CLK    27
#define V_SGMII_GATE_REF_CLK(x) ((x) << S_SGMII_GATE_REF_CLK)
#define F_SGMII_GATE_REF_CLK    V_SGMII_GATE_REF_CLK(1U)

#define S_PCS10G_GATE_XFI_RXCLK    26
#define V_PCS10G_GATE_XFI_RXCLK(x) ((x) << S_PCS10G_GATE_XFI_RXCLK)
#define F_PCS10G_GATE_XFI_RXCLK    V_PCS10G_GATE_XFI_RXCLK(1U)

#define S_PCS10G_GATE_XFI_TXCLK    25
#define V_PCS10G_GATE_XFI_TXCLK(x) ((x) << S_PCS10G_GATE_XFI_TXCLK)
#define F_PCS10G_GATE_XFI_TXCLK    V_PCS10G_GATE_XFI_TXCLK(1U)

#define S_PCS10G_GATE_SD_TX_CLK    24
#define V_PCS10G_GATE_SD_TX_CLK(x) ((x) << S_PCS10G_GATE_SD_TX_CLK)
#define F_PCS10G_GATE_SD_TX_CLK    V_PCS10G_GATE_SD_TX_CLK(1U)

#define S_PCS10G_GATE_SD_RX_CLK    23
#define V_PCS10G_GATE_SD_RX_CLK(x) ((x) << S_PCS10G_GATE_SD_RX_CLK)
#define F_PCS10G_GATE_SD_RX_CLK    V_PCS10G_GATE_SD_RX_CLK(1U)

#define S_PCS40G_GATE_RXCLK    22
#define V_PCS40G_GATE_RXCLK(x) ((x) << S_PCS40G_GATE_RXCLK)
#define F_PCS40G_GATE_RXCLK    V_PCS40G_GATE_RXCLK(1U)

#define S_PCS40G_GATE_SD_TX_CLK    21
#define V_PCS40G_GATE_SD_TX_CLK(x) ((x) << S_PCS40G_GATE_SD_TX_CLK)
#define F_PCS40G_GATE_SD_TX_CLK    V_PCS40G_GATE_SD_TX_CLK(1U)

#define S_PCS40G_GATE_SD_RX_CLK    20
#define V_PCS40G_GATE_SD_RX_CLK(x) ((x) << S_PCS40G_GATE_SD_RX_CLK)
#define F_PCS40G_GATE_SD_RX_CLK    V_PCS40G_GATE_SD_RX_CLK(1U)

#define S_PCS100G_GATE_CGMII_RXCLK    19
#define V_PCS100G_GATE_CGMII_RXCLK(x) ((x) << S_PCS100G_GATE_CGMII_RXCLK)
#define F_PCS100G_GATE_CGMII_RXCLK    V_PCS100G_GATE_CGMII_RXCLK(1U)

#define S_PCS100G_GATE_CGMII_TXCLK    18
#define V_PCS100G_GATE_CGMII_TXCLK(x) ((x) << S_PCS100G_GATE_CGMII_TXCLK)
#define F_PCS100G_GATE_CGMII_TXCLK    V_PCS100G_GATE_CGMII_TXCLK(1U)

#define S_PCS100G_GATE_TX_CLK    17
#define V_PCS100G_GATE_TX_CLK(x) ((x) << S_PCS100G_GATE_TX_CLK)
#define F_PCS100G_GATE_TX_CLK    V_PCS100G_GATE_TX_CLK(1U)

#define S_PCS100G_GATE_SD_RX_CLK    16
#define V_PCS100G_GATE_SD_RX_CLK(x) ((x) << S_PCS100G_GATE_SD_RX_CLK)
#define F_PCS100G_GATE_SD_RX_CLK    V_PCS100G_GATE_SD_RX_CLK(1U)

#define S_MAC40G100G_GATE_TXCLK    15
#define V_MAC40G100G_GATE_TXCLK(x) ((x) << S_MAC40G100G_GATE_TXCLK)
#define F_MAC40G100G_GATE_TXCLK    V_MAC40G100G_GATE_TXCLK(1U)

#define S_MAC40G100G_GATE_RXCLK    14
#define V_MAC40G100G_GATE_RXCLK(x) ((x) << S_MAC40G100G_GATE_RXCLK)
#define F_MAC40G100G_GATE_RXCLK    V_MAC40G100G_GATE_RXCLK(1U)

#define S_MAC40G100G_GATE_FF_TX_CLK    13
#define V_MAC40G100G_GATE_FF_TX_CLK(x) ((x) << S_MAC40G100G_GATE_FF_TX_CLK)
#define F_MAC40G100G_GATE_FF_TX_CLK    V_MAC40G100G_GATE_FF_TX_CLK(1U)

#define S_MAC40G100G_GATE_FF_RX_CLK    12
#define V_MAC40G100G_GATE_FF_RX_CLK(x) ((x) << S_MAC40G100G_GATE_FF_RX_CLK)
#define F_MAC40G100G_GATE_FF_RX_CLK    V_MAC40G100G_GATE_FF_RX_CLK(1U)

#define S_MAC40G100G_TS_CLK    11
#define V_MAC40G100G_TS_CLK(x) ((x) << S_MAC40G100G_TS_CLK)
#define F_MAC40G100G_TS_CLK    V_MAC40G100G_TS_CLK(1U)

#define S_MAC1G10G_GATE_RXCLK    10
#define V_MAC1G10G_GATE_RXCLK(x) ((x) << S_MAC1G10G_GATE_RXCLK)
#define F_MAC1G10G_GATE_RXCLK    V_MAC1G10G_GATE_RXCLK(1U)

#define S_MAC1G10G_GATE_TXCLK    9
#define V_MAC1G10G_GATE_TXCLK(x) ((x) << S_MAC1G10G_GATE_TXCLK)
#define F_MAC1G10G_GATE_TXCLK    V_MAC1G10G_GATE_TXCLK(1U)

#define S_MAC1G10G_GATE_FF_RX_CLK    8
#define V_MAC1G10G_GATE_FF_RX_CLK(x) ((x) << S_MAC1G10G_GATE_FF_RX_CLK)
#define F_MAC1G10G_GATE_FF_RX_CLK    V_MAC1G10G_GATE_FF_RX_CLK(1U)

#define S_MAC1G10G_GATE_FF_TX_CLK    7
#define V_MAC1G10G_GATE_FF_TX_CLK(x) ((x) << S_MAC1G10G_GATE_FF_TX_CLK)
#define F_MAC1G10G_GATE_FF_TX_CLK    V_MAC1G10G_GATE_FF_TX_CLK(1U)

#define S_AEC_RX    6
#define V_AEC_RX(x) ((x) << S_AEC_RX)
#define F_AEC_RX    V_AEC_RX(1U)

#define S_AEC_TX    5
#define V_AEC_TX(x) ((x) << S_AEC_TX)
#define F_AEC_TX    V_AEC_TX(1U)

#define S_PCS100G_CLK_ENABLE    4
#define V_PCS100G_CLK_ENABLE(x) ((x) << S_PCS100G_CLK_ENABLE)
#define F_PCS100G_CLK_ENABLE    V_PCS100G_CLK_ENABLE(1U)

#define S_PCS40G_CLK_ENABLE    3
#define V_PCS40G_CLK_ENABLE(x) ((x) << S_PCS40G_CLK_ENABLE)
#define F_PCS40G_CLK_ENABLE    V_PCS40G_CLK_ENABLE(1U)

#define S_PCS10G_CLK_ENABLE    2
#define V_PCS10G_CLK_ENABLE(x) ((x) << S_PCS10G_CLK_ENABLE)
#define F_PCS10G_CLK_ENABLE    V_PCS10G_CLK_ENABLE(1U)

#define S_PCS1G_CLK_ENABLE    1
#define V_PCS1G_CLK_ENABLE(x) ((x) << S_PCS1G_CLK_ENABLE)
#define F_PCS1G_CLK_ENABLE    V_PCS1G_CLK_ENABLE(1U)

#define S_AN_CLK_ENABLE    0
#define V_AN_CLK_ENABLE(x) ((x) << S_AN_CLK_ENABLE)
#define F_AN_CLK_ENABLE    V_AN_CLK_ENABLE(1U)

#define A_MAC_PORT_PERR_INT_CAUSE_100G 0x888

#define S_PERR_RX_FEC100G_DLY    29
#define V_PERR_RX_FEC100G_DLY(x) ((x) << S_PERR_RX_FEC100G_DLY)
#define F_PERR_RX_FEC100G_DLY    V_PERR_RX_FEC100G_DLY(1U)

#define S_PERR_RX_FEC100G    28
#define V_PERR_RX_FEC100G(x) ((x) << S_PERR_RX_FEC100G)
#define F_PERR_RX_FEC100G    V_PERR_RX_FEC100G(1U)

#define S_PERR_RX3_FEC100G_DK    27
#define V_PERR_RX3_FEC100G_DK(x) ((x) << S_PERR_RX3_FEC100G_DK)
#define F_PERR_RX3_FEC100G_DK    V_PERR_RX3_FEC100G_DK(1U)

#define S_PERR_RX2_FEC100G_DK    26
#define V_PERR_RX2_FEC100G_DK(x) ((x) << S_PERR_RX2_FEC100G_DK)
#define F_PERR_RX2_FEC100G_DK    V_PERR_RX2_FEC100G_DK(1U)

#define S_PERR_RX1_FEC100G_DK    25
#define V_PERR_RX1_FEC100G_DK(x) ((x) << S_PERR_RX1_FEC100G_DK)
#define F_PERR_RX1_FEC100G_DK    V_PERR_RX1_FEC100G_DK(1U)

#define S_PERR_RX0_FEC100G_DK    24
#define V_PERR_RX0_FEC100G_DK(x) ((x) << S_PERR_RX0_FEC100G_DK)
#define F_PERR_RX0_FEC100G_DK    V_PERR_RX0_FEC100G_DK(1U)

#define S_PERR_TX3_PCS100G    23
#define V_PERR_TX3_PCS100G(x) ((x) << S_PERR_TX3_PCS100G)
#define F_PERR_TX3_PCS100G    V_PERR_TX3_PCS100G(1U)

#define S_PERR_TX2_PCS100G    22
#define V_PERR_TX2_PCS100G(x) ((x) << S_PERR_TX2_PCS100G)
#define F_PERR_TX2_PCS100G    V_PERR_TX2_PCS100G(1U)

#define S_PERR_TX1_PCS100G    21
#define V_PERR_TX1_PCS100G(x) ((x) << S_PERR_TX1_PCS100G)
#define F_PERR_TX1_PCS100G    V_PERR_TX1_PCS100G(1U)

#define S_PERR_TX0_PCS100G    20
#define V_PERR_TX0_PCS100G(x) ((x) << S_PERR_TX0_PCS100G)
#define F_PERR_TX0_PCS100G    V_PERR_TX0_PCS100G(1U)

#define S_PERR_RX19_PCS100G    19
#define V_PERR_RX19_PCS100G(x) ((x) << S_PERR_RX19_PCS100G)
#define F_PERR_RX19_PCS100G    V_PERR_RX19_PCS100G(1U)

#define S_PERR_RX18_PCS100G    18
#define V_PERR_RX18_PCS100G(x) ((x) << S_PERR_RX18_PCS100G)
#define F_PERR_RX18_PCS100G    V_PERR_RX18_PCS100G(1U)

#define S_PERR_RX17_PCS100G    17
#define V_PERR_RX17_PCS100G(x) ((x) << S_PERR_RX17_PCS100G)
#define F_PERR_RX17_PCS100G    V_PERR_RX17_PCS100G(1U)

#define S_PERR_RX16_PCS100G    16
#define V_PERR_RX16_PCS100G(x) ((x) << S_PERR_RX16_PCS100G)
#define F_PERR_RX16_PCS100G    V_PERR_RX16_PCS100G(1U)

#define S_PERR_RX15_PCS100G    15
#define V_PERR_RX15_PCS100G(x) ((x) << S_PERR_RX15_PCS100G)
#define F_PERR_RX15_PCS100G    V_PERR_RX15_PCS100G(1U)

#define S_PERR_RX14_PCS100G    14
#define V_PERR_RX14_PCS100G(x) ((x) << S_PERR_RX14_PCS100G)
#define F_PERR_RX14_PCS100G    V_PERR_RX14_PCS100G(1U)

#define S_PERR_RX13_PCS100G    13
#define V_PERR_RX13_PCS100G(x) ((x) << S_PERR_RX13_PCS100G)
#define F_PERR_RX13_PCS100G    V_PERR_RX13_PCS100G(1U)

#define S_PERR_RX12_PCS100G    12
#define V_PERR_RX12_PCS100G(x) ((x) << S_PERR_RX12_PCS100G)
#define F_PERR_RX12_PCS100G    V_PERR_RX12_PCS100G(1U)

#define S_PERR_RX11_PCS100G    11
#define V_PERR_RX11_PCS100G(x) ((x) << S_PERR_RX11_PCS100G)
#define F_PERR_RX11_PCS100G    V_PERR_RX11_PCS100G(1U)

#define S_PERR_RX10_PCS100G    10
#define V_PERR_RX10_PCS100G(x) ((x) << S_PERR_RX10_PCS100G)
#define F_PERR_RX10_PCS100G    V_PERR_RX10_PCS100G(1U)

#define S_PERR_RX9_PCS100G    9
#define V_PERR_RX9_PCS100G(x) ((x) << S_PERR_RX9_PCS100G)
#define F_PERR_RX9_PCS100G    V_PERR_RX9_PCS100G(1U)

#define S_PERR_RX8_PCS100G    8
#define V_PERR_RX8_PCS100G(x) ((x) << S_PERR_RX8_PCS100G)
#define F_PERR_RX8_PCS100G    V_PERR_RX8_PCS100G(1U)

#define S_PERR_RX7_PCS100G    7
#define V_PERR_RX7_PCS100G(x) ((x) << S_PERR_RX7_PCS100G)
#define F_PERR_RX7_PCS100G    V_PERR_RX7_PCS100G(1U)

#define S_PERR_RX6_PCS100G    6
#define V_PERR_RX6_PCS100G(x) ((x) << S_PERR_RX6_PCS100G)
#define F_PERR_RX6_PCS100G    V_PERR_RX6_PCS100G(1U)

#define S_PERR_RX5_PCS100G    5
#define V_PERR_RX5_PCS100G(x) ((x) << S_PERR_RX5_PCS100G)
#define F_PERR_RX5_PCS100G    V_PERR_RX5_PCS100G(1U)

#define S_PERR_RX4_PCS100G    4
#define V_PERR_RX4_PCS100G(x) ((x) << S_PERR_RX4_PCS100G)
#define F_PERR_RX4_PCS100G    V_PERR_RX4_PCS100G(1U)

#define S_PERR_RX3_PCS100G    3
#define V_PERR_RX3_PCS100G(x) ((x) << S_PERR_RX3_PCS100G)
#define F_PERR_RX3_PCS100G    V_PERR_RX3_PCS100G(1U)

#define S_PERR_RX2_PCS100G    2
#define V_PERR_RX2_PCS100G(x) ((x) << S_PERR_RX2_PCS100G)
#define F_PERR_RX2_PCS100G    V_PERR_RX2_PCS100G(1U)

#define S_PERR_RX1_PCS100G    1
#define V_PERR_RX1_PCS100G(x) ((x) << S_PERR_RX1_PCS100G)
#define F_PERR_RX1_PCS100G    V_PERR_RX1_PCS100G(1U)

#define S_PERR_RX0_PCS100G    0
#define V_PERR_RX0_PCS100G(x) ((x) << S_PERR_RX0_PCS100G)
#define F_PERR_RX0_PCS100G    V_PERR_RX0_PCS100G(1U)

#define A_MAC_PORT_INT_CAUSE 0x8dc

#define S_TX_TS_AVAIL    29
#define V_TX_TS_AVAIL(x) ((x) << S_TX_TS_AVAIL)
#define F_TX_TS_AVAIL    V_TX_TS_AVAIL(1U)

#define S_AN_PAGE_RCVD    2
#define V_AN_PAGE_RCVD(x) ((x) << S_AN_PAGE_RCVD)
#define F_AN_PAGE_RCVD    V_AN_PAGE_RCVD(1U)

#define A_MAC_PORT_PERR_INT_CAUSE 0x8e4

#define S_PERR_PKT_RAM    24
#define V_PERR_PKT_RAM(x) ((x) << S_PERR_PKT_RAM)
#define F_PERR_PKT_RAM    V_PERR_PKT_RAM(1U)

#define S_PERR_MASK_RAM    23
#define V_PERR_MASK_RAM(x) ((x) << S_PERR_MASK_RAM)
#define F_PERR_MASK_RAM    V_PERR_MASK_RAM(1U)

#define S_PERR_CRC_RAM    22
#define V_PERR_CRC_RAM(x) ((x) << S_PERR_CRC_RAM)
#define F_PERR_CRC_RAM    V_PERR_CRC_RAM(1U)

#define S_RX_DFF_SEG0    21
#define V_RX_DFF_SEG0(x) ((x) << S_RX_DFF_SEG0)
#define F_RX_DFF_SEG0    V_RX_DFF_SEG0(1U)

#define S_RX_SFF_SEG0    20
#define V_RX_SFF_SEG0(x) ((x) << S_RX_SFF_SEG0)
#define F_RX_SFF_SEG0    V_RX_SFF_SEG0(1U)

#define S_RX_DFF_MAC10    19
#define V_RX_DFF_MAC10(x) ((x) << S_RX_DFF_MAC10)
#define F_RX_DFF_MAC10    V_RX_DFF_MAC10(1U)

#define S_RX_SFF_MAC10    18
#define V_RX_SFF_MAC10(x) ((x) << S_RX_SFF_MAC10)
#define F_RX_SFF_MAC10    V_RX_SFF_MAC10(1U)

#define S_TX_DFF_SEG0    17
#define V_TX_DFF_SEG0(x) ((x) << S_TX_DFF_SEG0)
#define F_TX_DFF_SEG0    V_TX_DFF_SEG0(1U)

#define S_TX_SFF_SEG0    16
#define V_TX_SFF_SEG0(x) ((x) << S_TX_SFF_SEG0)
#define F_TX_SFF_SEG0    V_TX_SFF_SEG0(1U)

#define S_TX_DFF_MAC10    15
#define V_TX_DFF_MAC10(x) ((x) << S_TX_DFF_MAC10)
#define F_TX_DFF_MAC10    V_TX_DFF_MAC10(1U)

#define S_TX_SFF_MAC10    14
#define V_TX_SFF_MAC10(x) ((x) << S_TX_SFF_MAC10)
#define F_TX_SFF_MAC10    V_TX_SFF_MAC10(1U)

#define S_RX_STATS    13
#define V_RX_STATS(x) ((x) << S_RX_STATS)
#define F_RX_STATS    V_RX_STATS(1U)

#define S_TX_STATS    12
#define V_TX_STATS(x) ((x) << S_TX_STATS)
#define F_TX_STATS    V_TX_STATS(1U)

#define S_PERR3_RX_MIX    11
#define V_PERR3_RX_MIX(x) ((x) << S_PERR3_RX_MIX)
#define F_PERR3_RX_MIX    V_PERR3_RX_MIX(1U)

#define S_PERR3_RX_SD    10
#define V_PERR3_RX_SD(x) ((x) << S_PERR3_RX_SD)
#define F_PERR3_RX_SD    V_PERR3_RX_SD(1U)

#define S_PERR3_TX    9
#define V_PERR3_TX(x) ((x) << S_PERR3_TX)
#define F_PERR3_TX    V_PERR3_TX(1U)

#define S_PERR2_RX_MIX    8
#define V_PERR2_RX_MIX(x) ((x) << S_PERR2_RX_MIX)
#define F_PERR2_RX_MIX    V_PERR2_RX_MIX(1U)

#define S_PERR2_RX_SD    7
#define V_PERR2_RX_SD(x) ((x) << S_PERR2_RX_SD)
#define F_PERR2_RX_SD    V_PERR2_RX_SD(1U)

#define S_PERR2_TX    6
#define V_PERR2_TX(x) ((x) << S_PERR2_TX)
#define F_PERR2_TX    V_PERR2_TX(1U)

#define S_PERR1_RX_MIX    5
#define V_PERR1_RX_MIX(x) ((x) << S_PERR1_RX_MIX)
#define F_PERR1_RX_MIX    V_PERR1_RX_MIX(1U)

#define S_PERR1_RX_SD    4
#define V_PERR1_RX_SD(x) ((x) << S_PERR1_RX_SD)
#define F_PERR1_RX_SD    V_PERR1_RX_SD(1U)

#define S_PERR1_TX    3
#define V_PERR1_TX(x) ((x) << S_PERR1_TX)
#define F_PERR1_TX    V_PERR1_TX(1U)

#define S_PERR0_RX_MIX    2
#define V_PERR0_RX_MIX(x) ((x) << S_PERR0_RX_MIX)
#define F_PERR0_RX_MIX    V_PERR0_RX_MIX(1U)

#define S_PERR0_RX_SD    1
#define V_PERR0_RX_SD(x) ((x) << S_PERR0_RX_SD)
#define F_PERR0_RX_SD    V_PERR0_RX_SD(1U)

#define S_PERR0_TX    0
#define V_PERR0_TX(x) ((x) << S_PERR0_TX)
#define F_PERR0_TX    V_PERR0_TX(1U)

#define S_T6_PERR_PKT_RAM    31
#define V_T6_PERR_PKT_RAM(x) ((x) << S_T6_PERR_PKT_RAM)
#define F_T6_PERR_PKT_RAM    V_T6_PERR_PKT_RAM(1U)

#define S_T6_PERR_MASK_RAM    30
#define V_T6_PERR_MASK_RAM(x) ((x) << S_T6_PERR_MASK_RAM)
#define F_T6_PERR_MASK_RAM    V_T6_PERR_MASK_RAM(1U)

#define S_T6_PERR_CRC_RAM    29
#define V_T6_PERR_CRC_RAM(x) ((x) << S_T6_PERR_CRC_RAM)
#define F_T6_PERR_CRC_RAM    V_T6_PERR_CRC_RAM(1U)

#define S_RX_MAC40G    28
#define V_RX_MAC40G(x) ((x) << S_RX_MAC40G)
#define F_RX_MAC40G    V_RX_MAC40G(1U)

#define S_TX_MAC40G    27
#define V_TX_MAC40G(x) ((x) << S_TX_MAC40G)
#define F_TX_MAC40G    V_TX_MAC40G(1U)

#define S_RX_ST_MAC40G    26
#define V_RX_ST_MAC40G(x) ((x) << S_RX_ST_MAC40G)
#define F_RX_ST_MAC40G    V_RX_ST_MAC40G(1U)

#define S_TX_ST_MAC40G    25
#define V_TX_ST_MAC40G(x) ((x) << S_TX_ST_MAC40G)
#define F_TX_ST_MAC40G    V_TX_ST_MAC40G(1U)

#define S_TX_MAC1G10G    24
#define V_TX_MAC1G10G(x) ((x) << S_TX_MAC1G10G)
#define F_TX_MAC1G10G    V_TX_MAC1G10G(1U)

#define S_RX_MAC1G10G    23
#define V_RX_MAC1G10G(x) ((x) << S_RX_MAC1G10G)
#define F_RX_MAC1G10G    V_RX_MAC1G10G(1U)

#define S_RX_STATUS_MAC1G10G    22
#define V_RX_STATUS_MAC1G10G(x) ((x) << S_RX_STATUS_MAC1G10G)
#define F_RX_STATUS_MAC1G10G    V_RX_STATUS_MAC1G10G(1U)

#define S_RX_ST_MAC1G10G    21
#define V_RX_ST_MAC1G10G(x) ((x) << S_RX_ST_MAC1G10G)
#define F_RX_ST_MAC1G10G    V_RX_ST_MAC1G10G(1U)

#define S_TX_ST_MAC1G10G    20
#define V_TX_ST_MAC1G10G(x) ((x) << S_TX_ST_MAC1G10G)
#define F_TX_ST_MAC1G10G    V_TX_ST_MAC1G10G(1U)

#define S_PERR_TX0_PCS40G    19
#define V_PERR_TX0_PCS40G(x) ((x) << S_PERR_TX0_PCS40G)
#define F_PERR_TX0_PCS40G    V_PERR_TX0_PCS40G(1U)

#define S_PERR_TX1_PCS40G    18
#define V_PERR_TX1_PCS40G(x) ((x) << S_PERR_TX1_PCS40G)
#define F_PERR_TX1_PCS40G    V_PERR_TX1_PCS40G(1U)

#define S_PERR_TX2_PCS40G    17
#define V_PERR_TX2_PCS40G(x) ((x) << S_PERR_TX2_PCS40G)
#define F_PERR_TX2_PCS40G    V_PERR_TX2_PCS40G(1U)

#define S_PERR_TX3_PCS40G    16
#define V_PERR_TX3_PCS40G(x) ((x) << S_PERR_TX3_PCS40G)
#define F_PERR_TX3_PCS40G    V_PERR_TX3_PCS40G(1U)

#define S_PERR_TX0_FEC40G    15
#define V_PERR_TX0_FEC40G(x) ((x) << S_PERR_TX0_FEC40G)
#define F_PERR_TX0_FEC40G    V_PERR_TX0_FEC40G(1U)

#define S_PERR_TX1_FEC40G    14
#define V_PERR_TX1_FEC40G(x) ((x) << S_PERR_TX1_FEC40G)
#define F_PERR_TX1_FEC40G    V_PERR_TX1_FEC40G(1U)

#define S_PERR_TX2_FEC40G    13
#define V_PERR_TX2_FEC40G(x) ((x) << S_PERR_TX2_FEC40G)
#define F_PERR_TX2_FEC40G    V_PERR_TX2_FEC40G(1U)

#define S_PERR_TX3_FEC40G    12
#define V_PERR_TX3_FEC40G(x) ((x) << S_PERR_TX3_FEC40G)
#define F_PERR_TX3_FEC40G    V_PERR_TX3_FEC40G(1U)

#define S_PERR_RX0_PCS40G    11
#define V_PERR_RX0_PCS40G(x) ((x) << S_PERR_RX0_PCS40G)
#define F_PERR_RX0_PCS40G    V_PERR_RX0_PCS40G(1U)

#define S_PERR_RX1_PCS40G    10
#define V_PERR_RX1_PCS40G(x) ((x) << S_PERR_RX1_PCS40G)
#define F_PERR_RX1_PCS40G    V_PERR_RX1_PCS40G(1U)

#define S_PERR_RX2_PCS40G    9
#define V_PERR_RX2_PCS40G(x) ((x) << S_PERR_RX2_PCS40G)
#define F_PERR_RX2_PCS40G    V_PERR_RX2_PCS40G(1U)

#define S_PERR_RX3_PCS40G    8
#define V_PERR_RX3_PCS40G(x) ((x) << S_PERR_RX3_PCS40G)
#define F_PERR_RX3_PCS40G    V_PERR_RX3_PCS40G(1U)

#define S_PERR_RX0_FEC40G    7
#define V_PERR_RX0_FEC40G(x) ((x) << S_PERR_RX0_FEC40G)
#define F_PERR_RX0_FEC40G    V_PERR_RX0_FEC40G(1U)

#define S_PERR_RX1_FEC40G    6
#define V_PERR_RX1_FEC40G(x) ((x) << S_PERR_RX1_FEC40G)
#define F_PERR_RX1_FEC40G    V_PERR_RX1_FEC40G(1U)

#define S_PERR_RX2_FEC40G    5
#define V_PERR_RX2_FEC40G(x) ((x) << S_PERR_RX2_FEC40G)
#define F_PERR_RX2_FEC40G    V_PERR_RX2_FEC40G(1U)

#define S_PERR_RX3_FEC40G    4
#define V_PERR_RX3_FEC40G(x) ((x) << S_PERR_RX3_FEC40G)
#define F_PERR_RX3_FEC40G    V_PERR_RX3_FEC40G(1U)

#define S_PERR_RX_PCS10G_LPBK    3
#define V_PERR_RX_PCS10G_LPBK(x) ((x) << S_PERR_RX_PCS10G_LPBK)
#define F_PERR_RX_PCS10G_LPBK    V_PERR_RX_PCS10G_LPBK(1U)

#define S_PERR_RX_PCS10G    2
#define V_PERR_RX_PCS10G(x) ((x) << S_PERR_RX_PCS10G)
#define F_PERR_RX_PCS10G    V_PERR_RX_PCS10G(1U)

#define S_PERR_RX_PCS1G    1
#define V_PERR_RX_PCS1G(x) ((x) << S_PERR_RX_PCS1G)
#define F_PERR_RX_PCS1G    V_PERR_RX_PCS1G(1U)

#define S_PERR_TX_PCS1G    0
#define V_PERR_TX_PCS1G(x) ((x) << S_PERR_TX_PCS1G)
#define F_PERR_TX_PCS1G    V_PERR_TX_PCS1G(1U)

#define A_MAC_PORT_TX_TS_VAL_LO 0x928
#define A_MAC_PORT_TX_TS_VAL_HI 0x92c
#define A_MAC_PORT_AFRAMESTRANSMITTEDOK 0xa80
#define A_MAC_PORT_AFRAMESTRANSMITTEDOKHI 0xa84
#define A_MAC_PORT_AFRAMESRECEIVEDOK 0xa88
#define A_MAC_PORT_AFRAMESRECEIVEDOKHI 0xa8c
#define A_MAC_PORT_MTIP_1G10G_RX_FRAMESOK 0xe20
#define A_MAC_PORT_MTIP_1G10G_RX_FRAMESOKHI 0xe24
#define A_MAC_PORT_MTIP_1G10G_TX_FRAMESOKHI 0xf24
#define A_MAC_PORT_MTIP_1G10G_TX_CRCERRORS 0xf28

/* registers for module MC_0 */
#define MC_0_BASE_ADDR 0x40000

#define A_MC_P_PAR_CAUSE 0x41310
#define A_MC_P_INT_CAUSE 0x41318
#define A_MC_P_ECC_STATUS 0x4131c
#define A_MC_P_BIST_CMD 0x41400

#define S_BURST_LEN    16
#define M_BURST_LEN    0x3U
#define V_BURST_LEN(x) ((x) << S_BURST_LEN)
#define G_BURST_LEN(x) (((x) >> S_BURST_LEN) & M_BURST_LEN)

#define A_MC_P_BIST_CMD_ADDR 0x41404
#define A_MC_P_BIST_CMD_LEN 0x41408
#define A_MC_P_BIST_DATA_PATTERN 0x4140c
#define A_MC_P_BIST_STATUS_RDATA 0x41488
#define A_MC_DDRPHY_DP18_WRCLK_AUX_CNTL 0x4407c
#define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE 0x45860
#define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 0x458a0
#define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 0x458a4
#define A_MC_DDRPHY_APB_MTSTAT_REG0 0x47828

/* registers for module MC_1 */
#define MC_1_BASE_ADDR 0x48000

/* registers for module EDC_T50 */
#define EDC_T50_BASE_ADDR 0x50000

#define A_EDC_H_BIST_CMD 0x50004
#define A_EDC_H_BIST_CMD_ADDR 0x50008
#define A_EDC_H_BIST_CMD_LEN 0x5000c
#define A_EDC_H_BIST_DATA_PATTERN 0x50010
#define A_EDC_H_BIST_STATUS_RDATA 0x50028
#define A_EDC_H_INT_CAUSE 0x50078

#define S_ECC_UE_INT0_CAUSE    5
#define V_ECC_UE_INT0_CAUSE(x) ((x) << S_ECC_UE_INT0_CAUSE)
#define F_ECC_UE_INT0_CAUSE    V_ECC_UE_INT0_CAUSE(1U)

#define S_ECC_CE_INT0_CAUSE    4
#define V_ECC_CE_INT0_CAUSE(x) ((x) << S_ECC_CE_INT0_CAUSE)
#define F_ECC_CE_INT0_CAUSE    V_ECC_CE_INT0_CAUSE(1U)

#define S_PERR_INT0_CAUSE    3
#define V_PERR_INT0_CAUSE(x) ((x) << S_PERR_INT0_CAUSE)
#define F_PERR_INT0_CAUSE    V_PERR_INT0_CAUSE(1U)

#define A_EDC_H_ECC_STATUS 0x5007c
#define A_EDC_H_ECC_ERR_ADDR 0x50084
#define A_EDC_H_ECC_ERR_DATA_RDATA 0x50090

/* registers for module EDC_T51 */
#define EDC_T51_BASE_ADDR 0x50800

/* registers for module HMA_T5 */
#define HMA_T5_BASE_ADDR 0x51000


/* registers for module EDC_T60 */
#define EDC_T60_BASE_ADDR 0x50000

#define S_ECC_ADDR    0
#define M_ECC_ADDR    0x7fffffU
#define V_ECC_ADDR(x) ((x) << S_ECC_ADDR)
#define G_ECC_ADDR(x) (((x) >> S_ECC_ADDR) & M_ECC_ADDR)


/* registers for module EDC_T61 */
#define EDC_T61_BASE_ADDR 0x50800

/* registers for module HMA_T6 */
#define HMA_T6_BASE_ADDR 0x51000

#define A_HMA_LOCAL_DEBUG_CFG 0x51320