1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* This file is automatically generated --- changes will be lost */ 13 /* Generation Date : Thu Feb 16 10:13:37 IST 2017 */ 14 /* Directory name: t4_reg.txt, Changeset: */ 15 /* Directory name: t5_reg.txt, Changeset: 6939:9fe6306ea018 */ 16 /* Directory name: t6_reg.txt, Changeset: 4259:6bffc83b6848 */ 17 18 #define MYPF_BASE 0x1b000 19 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) 20 21 #define PF0_BASE 0x1e000 22 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr)) 23 24 #define PF1_BASE 0x1e400 25 #define PF1_REG(reg_addr) (PF1_BASE + (reg_addr)) 26 27 #define PF2_BASE 0x1e800 28 #define PF2_REG(reg_addr) (PF2_BASE + (reg_addr)) 29 30 #define PF3_BASE 0x1ec00 31 #define PF3_REG(reg_addr) (PF3_BASE + (reg_addr)) 32 33 #define PF4_BASE 0x1f000 34 #define PF4_REG(reg_addr) (PF4_BASE + (reg_addr)) 35 36 #define PF5_BASE 0x1f400 37 #define PF5_REG(reg_addr) (PF5_BASE + (reg_addr)) 38 39 #define PF6_BASE 0x1f800 40 #define PF6_REG(reg_addr) (PF6_BASE + (reg_addr)) 41 42 #define PF7_BASE 0x1fc00 43 #define PF7_REG(reg_addr) (PF7_BASE + (reg_addr)) 44 45 #define PF_STRIDE 0x400 46 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE) 47 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg)) 48 49 #define VF_SGE_BASE 0x0 50 #define VF_SGE_REG(reg_addr) (VF_SGE_BASE + (reg_addr)) 51 52 #define VF_MPS_BASE 0x100 53 #define VF_MPS_REG(reg_addr) (VF_MPS_BASE + (reg_addr)) 54 55 #define VF_PL_BASE 0x200 56 #define VF_PL_REG(reg_addr) (VF_PL_BASE + (reg_addr)) 57 58 #define VF_MBDATA_BASE 0x240 59 #define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr)) 60 61 #define VF_CIM_BASE 0x300 62 #define VF_CIM_REG(reg_addr) (VF_CIM_BASE + (reg_addr)) 63 64 #define MYPORT_BASE 0x1c000 65 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) 66 67 #define PORT0_BASE 0x20000 68 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr)) 69 70 #define PORT1_BASE 0x22000 71 #define PORT1_REG(reg_addr) (PORT1_BASE + (reg_addr)) 72 73 #define PORT2_BASE 0x24000 74 #define PORT2_REG(reg_addr) (PORT2_BASE + (reg_addr)) 75 76 #define PORT3_BASE 0x26000 77 #define PORT3_REG(reg_addr) (PORT3_BASE + (reg_addr)) 78 79 #define PORT_STRIDE 0x2000 80 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) 81 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg)) 82 83 #define SGE_QUEUE_BASE_MAP_HIGH(idx) (A_SGE_QUEUE_BASE_MAP_HIGH + (idx) * 8) 84 #define NUM_SGE_QUEUE_BASE_MAP_HIGH_INSTANCES 136 85 86 #define SGE_QUEUE_BASE_MAP_LOW(idx) (A_SGE_QUEUE_BASE_MAP_LOW + (idx) * 8) 87 #define NUM_SGE_QUEUE_BASE_MAP_LOW_INSTANCES 136 88 89 #define PCIE_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 90 #define NUM_PCIE_DMA_INSTANCES 4 91 92 #define PCIE_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 93 #define NUM_PCIE_CMD_INSTANCES 2 94 95 #define PCIE_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 96 #define NUM_PCIE_HMA_INSTANCES 1 97 98 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 99 #define NUM_PCIE_MEM_ACCESS_INSTANCES 8 100 101 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 102 #define NUM_PCIE_MAILBOX_INSTANCES 1 103 104 #define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 105 #define NUM_PCIE_FW_INSTANCES 8 106 107 #define PCIE_FUNC_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 108 #define NUM_PCIE_FUNC_INSTANCES 256 109 110 #define PCIE_FID(idx) (A_PCIE_FID + (idx) * 4) 111 #define NUM_PCIE_FID_INSTANCES 2048 112 113 #define PCIE_DMA_BUF_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 114 #define NUM_PCIE_DMA_BUF_INSTANCES 4 115 116 #define MC_DDR3PHYDATX8_REG(reg_addr, idx) ((reg_addr) + (idx) * 256) 117 #define NUM_MC_DDR3PHYDATX8_INSTANCES 9 118 119 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 120 #define NUM_MC_BIST_STATUS_INSTANCES 18 121 122 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 123 #define NUM_EDC_BIST_STATUS_INSTANCES 18 124 125 #define CIM_PF_MAILBOX_DATA(idx) (A_CIM_PF_MAILBOX_DATA + (idx) * 4) 126 #define NUM_CIM_PF_MAILBOX_DATA_INSTANCES 16 127 128 #define MPS_TRC_FILTER_MATCH_CTL_A(idx) (A_MPS_TRC_FILTER_MATCH_CTL_A + (idx) * 4) 129 #define NUM_MPS_TRC_FILTER_MATCH_CTL_A_INSTANCES 4 130 131 #define MPS_TRC_FILTER_MATCH_CTL_B(idx) (A_MPS_TRC_FILTER_MATCH_CTL_B + (idx) * 4) 132 #define NUM_MPS_TRC_FILTER_MATCH_CTL_B_INSTANCES 4 133 134 #define MPS_TRC_FILTER_RUNT_CTL(idx) (A_MPS_TRC_FILTER_RUNT_CTL + (idx) * 4) 135 #define NUM_MPS_TRC_FILTER_RUNT_CTL_INSTANCES 4 136 137 #define MPS_TRC_FILTER_DROP(idx) (A_MPS_TRC_FILTER_DROP + (idx) * 4) 138 #define NUM_MPS_TRC_FILTER_DROP_INSTANCES 4 139 140 #define MPS_TRC_FILTER0_MATCH(idx) (A_MPS_TRC_FILTER0_MATCH + (idx) * 4) 141 #define NUM_MPS_TRC_FILTER0_MATCH_INSTANCES 28 142 143 #define MPS_TRC_FILTER0_DONT_CARE(idx) (A_MPS_TRC_FILTER0_DONT_CARE + (idx) * 4) 144 #define NUM_MPS_TRC_FILTER0_DONT_CARE_INSTANCES 28 145 146 #define MPS_TRC_FILTER1_MATCH(idx) (A_MPS_TRC_FILTER1_MATCH + (idx) * 4) 147 #define NUM_MPS_TRC_FILTER1_MATCH_INSTANCES 28 148 149 #define MPS_TRC_FILTER1_DONT_CARE(idx) (A_MPS_TRC_FILTER1_DONT_CARE + (idx) * 4) 150 #define NUM_MPS_TRC_FILTER1_DONT_CARE_INSTANCES 28 151 152 #define MPS_TRC_FILTER2_MATCH(idx) (A_MPS_TRC_FILTER2_MATCH + (idx) * 4) 153 #define NUM_MPS_TRC_FILTER2_MATCH_INSTANCES 28 154 155 #define MPS_TRC_FILTER2_DONT_CARE(idx) (A_MPS_TRC_FILTER2_DONT_CARE + (idx) * 4) 156 #define NUM_MPS_TRC_FILTER2_DONT_CARE_INSTANCES 28 157 158 #define MPS_TRC_FILTER3_MATCH(idx) (A_MPS_TRC_FILTER3_MATCH + (idx) * 4) 159 #define NUM_MPS_TRC_FILTER3_MATCH_INSTANCES 28 160 161 #define MPS_TRC_FILTER3_DONT_CARE(idx) (A_MPS_TRC_FILTER3_DONT_CARE + (idx) * 4) 162 #define NUM_MPS_TRC_FILTER3_DONT_CARE_INSTANCES 28 163 164 #define MPS_PORT_CLS_HASH_SRAM(idx) (A_MPS_PORT_CLS_HASH_SRAM + (idx) * 4) 165 #define NUM_MPS_PORT_CLS_HASH_SRAM_INSTANCES 65 166 167 #define MPS_CLS_VLAN_TABLE(idx) (A_MPS_CLS_VLAN_TABLE + (idx) * 4) 168 #define NUM_MPS_CLS_VLAN_TABLE_INSTANCES 9 169 170 #define MPS_CLS_SRAM_L(idx) (A_MPS_CLS_SRAM_L + (idx) * 8) 171 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336 172 173 #define MPS_CLS_SRAM_H(idx) (A_MPS_CLS_SRAM_H + (idx) * 8) 174 #define NUM_MPS_CLS_SRAM_H_INSTANCES 336 175 176 #define MPS_CLS_TCAM_Y_L(idx) (A_MPS_CLS_TCAM_Y_L + (idx) * 16) 177 #define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512 178 179 #define MPS_CLS_TCAM_Y_H(idx) (A_MPS_CLS_TCAM_Y_H + (idx) * 16) 180 #define NUM_MPS_CLS_TCAM_Y_H_INSTANCES 512 181 182 #define MPS_CLS_TCAM_X_L(idx) (A_MPS_CLS_TCAM_X_L + (idx) * 16) 183 #define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512 184 185 #define MPS_CLS_TCAM_X_H(idx) (A_MPS_CLS_TCAM_X_H + (idx) * 16) 186 #define NUM_MPS_CLS_TCAM_X_H_INSTANCES 512 187 188 #define PL_SEMAPHORE_LOCK(idx) (A_PL_SEMAPHORE_LOCK + (idx) * 4) 189 #define NUM_PL_SEMAPHORE_LOCK_INSTANCES 8 190 191 #define PL_VF_SLICE_L(idx) (A_PL_VF_SLICE_L + (idx) * 8) 192 #define NUM_PL_VF_SLICE_L_INSTANCES 8 193 194 #define PL_VF_SLICE_H(idx) (A_PL_VF_SLICE_H + (idx) * 8) 195 #define NUM_PL_VF_SLICE_H_INSTANCES 8 196 197 #define PL_FLR_VF_STATUS(idx) (A_PL_FLR_VF_STATUS + (idx) * 4) 198 #define NUM_PL_FLR_VF_STATUS_INSTANCES 4 199 200 #define PL_VFID_MAP(idx) (A_PL_VFID_MAP + (idx) * 4) 201 #define NUM_PL_VFID_MAP_INSTANCES 256 202 203 #define LE_DB_MASK_IPV4(idx) (A_LE_DB_MASK_IPV4 + (idx) * 4) 204 #define NUM_LE_DB_MASK_IPV4_INSTANCES 17 205 206 #define LE_DB_MASK_IPV6(idx) (A_LE_DB_MASK_IPV6 + (idx) * 4) 207 #define NUM_LE_DB_MASK_IPV6_INSTANCES 17 208 209 #define LE_DB_DBGI_REQ_DATA(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4) 210 #define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 17 211 212 #define LE_DB_DBGI_REQ_MASK(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4) 213 #define NUM_LE_DB_DBGI_REQ_MASK_INSTANCES 17 214 215 #define LE_DB_DBGI_RSP_DATA(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4) 216 #define NUM_LE_DB_DBGI_RSP_DATA_INSTANCES 17 217 218 #define LE_DB_ACTIVE_MASK_IPV4(idx) (A_LE_DB_ACTIVE_MASK_IPV4 + (idx) * 4) 219 #define NUM_LE_DB_ACTIVE_MASK_IPV4_INSTANCES 17 220 221 #define LE_DB_ACTIVE_MASK_IPV6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4) 222 #define NUM_LE_DB_ACTIVE_MASK_IPV6_INSTANCES 17 223 224 #define LE_HASH_MASK_GEN_IPV4(idx) (A_LE_HASH_MASK_GEN_IPV4 + (idx) * 4) 225 #define NUM_LE_HASH_MASK_GEN_IPV4_INSTANCES 4 226 227 #define LE_HASH_MASK_GEN_IPV6(idx) (A_LE_HASH_MASK_GEN_IPV6 + (idx) * 4) 228 #define NUM_LE_HASH_MASK_GEN_IPV6_INSTANCES 12 229 230 #define LE_HASH_MASK_CMP_IPV4(idx) (A_LE_HASH_MASK_CMP_IPV4 + (idx) * 4) 231 #define NUM_LE_HASH_MASK_CMP_IPV4_INSTANCES 4 232 233 #define LE_HASH_MASK_CMP_IPV6(idx) (A_LE_HASH_MASK_CMP_IPV6 + (idx) * 4) 234 #define NUM_LE_HASH_MASK_CMP_IPV6_INSTANCES 12 235 236 #define UP_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) 237 #define NUM_UP_TSCH_CHANNEL_INSTANCES 4 238 239 #define CIM_CTL_MAILBOX_VF_STATUS(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4) 240 #define NUM_CIM_CTL_MAILBOX_VF_STATUS_INSTANCES 4 241 242 #define CIM_CTL_MAILBOX_VFN_CTL(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 16) 243 #define NUM_CIM_CTL_MAILBOX_VFN_CTL_INSTANCES 128 244 245 #define CIM_CTL_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 288) 246 #define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 4 247 248 #define CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) 249 #define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16 250 251 #define T5_MYPORT_BASE 0x2c000 252 #define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr)) 253 254 #define T5_PORT0_BASE 0x30000 255 #define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr)) 256 257 #define T5_PORT1_BASE 0x34000 258 #define T5_PORT1_REG(reg_addr) (T5_PORT1_BASE + (reg_addr)) 259 260 #define T5_PORT2_BASE 0x38000 261 #define T5_PORT2_REG(reg_addr) (T5_PORT2_BASE + (reg_addr)) 262 263 #define T5_PORT3_BASE 0x3c000 264 #define T5_PORT3_REG(reg_addr) (T5_PORT3_BASE + (reg_addr)) 265 266 #define T5_PORT_STRIDE 0x4000 267 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE) 268 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg)) 269 270 #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR) 271 #define MC_REG(reg, idx) (reg + MC_STRIDE * idx) 272 273 #define PCIE_PF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 274 #define NUM_PCIE_PF_INT_INSTANCES 8 275 276 #define PCIE_VF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 277 #define NUM_PCIE_VF_INT_INSTANCES 128 278 279 #define PCIE_FID_VFID(idx) (A_PCIE_FID_VFID + (idx) * 4) 280 #define NUM_PCIE_FID_VFID_INSTANCES 2048 281 282 #define PCIE_COOKIE_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 283 #define NUM_PCIE_COOKIE_INSTANCES 8 284 285 #define PCIE_T5_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) 286 #define NUM_PCIE_T5_DMA_INSTANCES 4 287 288 #define PCIE_T5_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) 289 #define NUM_PCIE_T5_CMD_INSTANCES 3 290 291 #define PCIE_T5_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) 292 #define NUM_PCIE_T5_HMA_INSTANCES 1 293 294 #define PCIE_PHY_PRESET_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 295 #define NUM_PCIE_PHY_PRESET_INSTANCES 11 296 297 #define MPS_T5_CLS_SRAM_L(idx) (A_MPS_T5_CLS_SRAM_L + (idx) * 8) 298 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512 299 300 #define MPS_T5_CLS_SRAM_H(idx) (A_MPS_T5_CLS_SRAM_H + (idx) * 8) 301 #define NUM_MPS_T5_CLS_SRAM_H_INSTANCES 512 302 303 #define LE_T5_DB_MASK_IPV4(idx) (A_LE_T5_DB_MASK_IPV4 + (idx) * 4) 304 #define NUM_LE_T5_DB_MASK_IPV4_INSTANCES 5 305 306 #define LE_T5_DB_ACTIVE_MASK_IPV4(idx) (A_LE_T5_DB_ACTIVE_MASK_IPV4 + (idx) * 4) 307 #define NUM_LE_T5_DB_ACTIVE_MASK_IPV4_INSTANCES 5 308 309 #define LE_HASH_MASK_GEN_IPV4T5(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4) 310 #define NUM_LE_HASH_MASK_GEN_IPV4T5_INSTANCES 5 311 312 #define LE_HASH_MASK_GEN_IPV6T5(idx) (A_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4) 313 #define NUM_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 12 314 315 #define LE_HASH_MASK_CMP_IPV4T5(idx) (A_LE_HASH_MASK_CMP_IPV4T5 + (idx) * 4) 316 #define NUM_LE_HASH_MASK_CMP_IPV4T5_INSTANCES 5 317 318 #define LE_HASH_MASK_CMP_IPV6T5(idx) (A_LE_HASH_MASK_CMP_IPV6T5 + (idx) * 4) 319 #define NUM_LE_HASH_MASK_CMP_IPV6T5_INSTANCES 12 320 321 #define LE_DB_SECOND_ACTIVE_MASK_IPV4(idx) (A_LE_DB_SECOND_ACTIVE_MASK_IPV4 + (idx) * 4) 322 #define NUM_LE_DB_SECOND_ACTIVE_MASK_IPV4_INSTANCES 5 323 324 #define LE_DB_SECOND_GEN_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4) 325 #define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_INSTANCES 5 326 327 #define LE_DB_SECOND_CMP_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 + (idx) * 4) 328 #define NUM_LE_DB_SECOND_CMP_HASH_MASK_IPV4_INSTANCES 5 329 330 #define MC_ADR_REG(reg_addr, idx) ((reg_addr) + (idx) * 512) 331 #define NUM_MC_ADR_INSTANCES 2 332 333 #define MC_DDRPHY_DP18_REG(reg_addr, idx) ((reg_addr) + (idx) * 512) 334 #define NUM_MC_DDRPHY_DP18_INSTANCES 5 335 336 #define MC_CE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 337 #define NUM_MC_CE_ERR_DATA_INSTANCES 8 338 339 #define MC_CE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 340 #define NUM_MC_CE_COR_DATA_INSTANCES 8 341 342 #define MC_UE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 343 #define NUM_MC_UE_ERR_DATA_INSTANCES 8 344 345 #define MC_UE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 346 #define NUM_MC_UE_COR_DATA_INSTANCES 8 347 348 #define MC_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 349 #define NUM_MC_P_BIST_STATUS_INSTANCES 18 350 351 #define EDC_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 352 #define NUM_EDC_H_BIST_STATUS_INSTANCES 18 353 354 #define EDC_H_ECC_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 355 #define NUM_EDC_H_ECC_ERR_DATA_INSTANCES 16 356 357 #define SGE_DEBUG1_DBP_THREAD(idx) (A_SGE_DEBUG1_DBP_THREAD + (idx) * 4) 358 #define NUM_SGE_DEBUG1_DBP_THREAD_INSTANCES 4 359 360 #define SGE_DEBUG0_DBP_THREAD(idx) (A_SGE_DEBUG0_DBP_THREAD + (idx) * 4) 361 #define NUM_SGE_DEBUG0_DBP_THREAD_INSTANCES 5 362 363 #define SGE_WC_EGRS_BAR2_OFF_PF(idx) (A_SGE_WC_EGRS_BAR2_OFF_PF + (idx) * 4) 364 #define NUM_SGE_WC_EGRS_BAR2_OFF_PF_INSTANCES 8 365 366 #define SGE_WC_EGRS_BAR2_OFF_VF(idx) (A_SGE_WC_EGRS_BAR2_OFF_VF + (idx) * 4) 367 #define NUM_SGE_WC_EGRS_BAR2_OFF_VF_INSTANCES 8 368 369 #define PCIE_T6_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) 370 #define NUM_PCIE_T6_DMA_INSTANCES 2 371 372 #define PCIE_T6_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) 373 #define NUM_PCIE_T6_CMD_INSTANCES 1 374 375 #define PCIE_VF_256_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 376 #define NUM_PCIE_VF_256_INT_INSTANCES 128 377 378 #define MPS_CLS_REQUEST_TRACE_MAC_DA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_L + (idx) * 32) 379 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_DA_L_INSTANCES 8 380 381 #define MPS_CLS_REQUEST_TRACE_MAC_DA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_H + (idx) * 32) 382 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_DA_H_INSTANCES 8 383 384 #define MPS_CLS_REQUEST_TRACE_MAC_SA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_L + (idx) * 32) 385 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_SA_L_INSTANCES 8 386 387 #define MPS_CLS_REQUEST_TRACE_MAC_SA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_H + (idx) * 32) 388 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_SA_H_INSTANCES 8 389 390 #define MPS_CLS_REQUEST_TRACE_PORT_VLAN(idx) (A_MPS_CLS_REQUEST_TRACE_PORT_VLAN + (idx) * 32) 391 #define NUM_MPS_CLS_REQUEST_TRACE_PORT_VLAN_INSTANCES 8 392 393 #define MPS_CLS_REQUEST_TRACE_ENCAP(idx) (A_MPS_CLS_REQUEST_TRACE_ENCAP + (idx) * 32) 394 #define NUM_MPS_CLS_REQUEST_TRACE_ENCAP_INSTANCES 8 395 396 #define MPS_CLS_RESULT_TRACE(idx) (A_MPS_CLS_RESULT_TRACE + (idx) * 4) 397 #define NUM_MPS_CLS_RESULT_TRACE_INSTANCES 8 398 399 #define MPS_CLS_DIPIPV4_ID_TABLE(idx) (A_MPS_CLS_DIPIPV4_ID_TABLE + (idx) * 8) 400 #define NUM_MPS_CLS_DIPIPV4_ID_TABLE_INSTANCES 4 401 402 #define MPS_CLS_DIPIPV4_MASK_TABLE(idx) (A_MPS_CLS_DIPIPV4_MASK_TABLE + (idx) * 8) 403 #define NUM_MPS_CLS_DIPIPV4_MASK_TABLE_INSTANCES 4 404 405 #define MPS_CLS_DIPIPV6ID_0_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_0_TABLE + (idx) * 32) 406 #define NUM_MPS_CLS_DIPIPV6ID_0_TABLE_INSTANCES 2 407 408 #define MPS_CLS_DIPIPV6ID_1_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_1_TABLE + (idx) * 32) 409 #define NUM_MPS_CLS_DIPIPV6ID_1_TABLE_INSTANCES 2 410 411 #define MPS_CLS_DIPIPV6ID_2_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_2_TABLE + (idx) * 32) 412 #define NUM_MPS_CLS_DIPIPV6ID_2_TABLE_INSTANCES 2 413 414 #define MPS_CLS_DIPIPV6ID_3_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_3_TABLE + (idx) * 32) 415 #define NUM_MPS_CLS_DIPIPV6ID_3_TABLE_INSTANCES 2 416 417 #define MPS_CLS_DIPIPV6MASK_0_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_0_TABLE + (idx) * 32) 418 #define NUM_MPS_CLS_DIPIPV6MASK_0_TABLE_INSTANCES 2 419 420 #define MPS_CLS_DIPIPV6MASK_1_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_1_TABLE + (idx) * 32) 421 #define NUM_MPS_CLS_DIPIPV6MASK_1_TABLE_INSTANCES 2 422 423 #define MPS_CLS_DIPIPV6MASK_2_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_2_TABLE + (idx) * 32) 424 #define NUM_MPS_CLS_DIPIPV6MASK_2_TABLE_INSTANCES 2 425 426 #define MPS_CLS_DIPIPV6MASK_3_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_3_TABLE + (idx) * 32) 427 #define NUM_MPS_CLS_DIPIPV6MASK_3_TABLE_INSTANCES 2 428 429 #define MPS_RX_HASH_LKP_TABLE(idx) (A_MPS_RX_HASH_LKP_TABLE + (idx) * 4) 430 #define NUM_MPS_RX_HASH_LKP_TABLE_INSTANCES 4 431 432 #define LE_DB_DBG_MATCH_DATA_MASK(idx) (A_LE_DB_DBG_MATCH_DATA_MASK + (idx) * 4) 433 #define NUM_LE_DB_DBG_MATCH_DATA_MASK_INSTANCES 8 434 435 #define LE_DB_DBG_MATCH_DATA(idx) (A_LE_DB_DBG_MATCH_DATA + (idx) * 4) 436 #define NUM_LE_DB_DBG_MATCH_DATA_INSTANCES 8 437 438 #define LE_DB_DBGI_REQ_DATA_T6(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4) 439 #define NUM_LE_DB_DBGI_REQ_DATA_T6_INSTANCES 11 440 441 #define LE_DB_DBGI_REQ_MASK_T6(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4) 442 #define NUM_LE_DB_DBGI_REQ_MASK_T6_INSTANCES 11 443 444 #define LE_DB_DBGI_RSP_DATA_T6(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4) 445 #define NUM_LE_DB_DBGI_RSP_DATA_T6_INSTANCES 11 446 447 #define LE_DB_ACTIVE_MASK_IPV6_T6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4) 448 #define NUM_LE_DB_ACTIVE_MASK_IPV6_T6_INSTANCES 8 449 450 #define LE_HASH_MASK_GEN_IPV4T6(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4) 451 #define NUM_LE_HASH_MASK_GEN_IPV4T6_INSTANCES 8 452 453 #define T6_LE_HASH_MASK_GEN_IPV6T5(idx) (A_T6_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4) 454 #define NUM_T6_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 8 455 456 #define LE_DB_PSV_FILTER_MASK_TUP_IPV4(idx) (A_LE_DB_PSV_FILTER_MASK_TUP_IPV4 + (idx) * 4) 457 #define NUM_LE_DB_PSV_FILTER_MASK_TUP_IPV4_INSTANCES 3 458 459 #define LE_DB_PSV_FILTER_MASK_FLT_IPV4(idx) (A_LE_DB_PSV_FILTER_MASK_FLT_IPV4 + (idx) * 4) 460 #define NUM_LE_DB_PSV_FILTER_MASK_FLT_IPV4_INSTANCES 2 461 462 #define LE_DB_PSV_FILTER_MASK_TUP_IPV6(idx) (A_LE_DB_PSV_FILTER_MASK_TUP_IPV6 + (idx) * 4) 463 #define NUM_LE_DB_PSV_FILTER_MASK_TUP_IPV6_INSTANCES 9 464 465 #define LE_DB_PSV_FILTER_MASK_FLT_IPV6(idx) (A_LE_DB_PSV_FILTER_MASK_FLT_IPV6 + (idx) * 4) 466 #define NUM_LE_DB_PSV_FILTER_MASK_FLT_IPV6_INSTANCES 2 467 468 #define LE_DB_SECOND_GEN_HASH_MASK_IPV4_T6(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4) 469 #define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_T6_INSTANCES 8 470 471 #define MC_DDRPHY_DP18_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 512) 472 #define NUM_MC_DDRPHY_DP18_T6_INSTANCES 9 473 474 #define MC_CE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 475 #define NUM_MC_CE_ERR_DATA_T6_INSTANCES 16 476 477 #define MC_UE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 478 #define NUM_MC_UE_ERR_DATA_T6_INSTANCES 16 479 480 #define CIM_CTL_MAILBOX_VF_STATUS_T6(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4) 481 #define NUM_CIM_CTL_MAILBOX_VF_STATUS_T6_INSTANCES 8 482 483 #define CIM_CTL_MAILBOX_VFN_CTL_T6(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 4) 484 #define NUM_CIM_CTL_MAILBOX_VFN_CTL_T6_INSTANCES 256 485 486 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR) 487 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx) 488 489 #define EDC_T5_STRIDE (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 490 #define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx) 491 492 /* registers for module SGE */ 493 #define SGE_BASE_ADDR 0x1000 494 495 #define A_SGE_PF_KDOORBELL 0x0 496 497 #define S_QID 15 498 #define M_QID 0x1ffffU 499 #define V_QID(x) ((x) << S_QID) 500 #define G_QID(x) (((x) >> S_QID) & M_QID) 501 502 #define S_DBPRIO 14 503 #define V_DBPRIO(x) ((x) << S_DBPRIO) 504 #define F_DBPRIO V_DBPRIO(1U) 505 506 #define S_PIDX 0 507 #define M_PIDX 0x3fffU 508 #define V_PIDX(x) ((x) << S_PIDX) 509 #define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX) 510 511 #define A_SGE_VF_KDOORBELL 0x0 512 513 #define S_DBTYPE 13 514 #define V_DBTYPE(x) ((x) << S_DBTYPE) 515 #define F_DBTYPE V_DBTYPE(1U) 516 517 #define S_PIDX_T5 0 518 #define M_PIDX_T5 0x1fffU 519 #define V_PIDX_T5(x) ((x) << S_PIDX_T5) 520 #define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5) 521 522 #define S_SYNC_T6 14 523 #define V_SYNC_T6(x) ((x) << S_SYNC_T6) 524 #define F_SYNC_T6 V_SYNC_T6(1U) 525 526 #define A_SGE_PF_GTS 0x4 527 528 #define S_INGRESSQID 16 529 #define M_INGRESSQID 0xffffU 530 #define V_INGRESSQID(x) ((x) << S_INGRESSQID) 531 #define G_INGRESSQID(x) (((x) >> S_INGRESSQID) & M_INGRESSQID) 532 533 #define S_TIMERREG 13 534 #define M_TIMERREG 0x7U 535 #define V_TIMERREG(x) ((x) << S_TIMERREG) 536 #define G_TIMERREG(x) (((x) >> S_TIMERREG) & M_TIMERREG) 537 538 #define S_SEINTARM 12 539 #define V_SEINTARM(x) ((x) << S_SEINTARM) 540 #define F_SEINTARM V_SEINTARM(1U) 541 542 #define S_CIDXINC 0 543 #define M_CIDXINC 0xfffU 544 #define V_CIDXINC(x) ((x) << S_CIDXINC) 545 #define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC) 546 547 #define A_SGE_VF_GTS 0x4 548 #define A_SGE_PF_KTIMESTAMP_LO 0x8 549 #define A_SGE_VF_KTIMESTAMP_LO 0x8 550 #define A_SGE_PF_KTIMESTAMP_HI 0xc 551 552 #define S_TSTAMPVAL 0 553 #define M_TSTAMPVAL 0xfffffffU 554 #define V_TSTAMPVAL(x) ((x) << S_TSTAMPVAL) 555 #define G_TSTAMPVAL(x) (((x) >> S_TSTAMPVAL) & M_TSTAMPVAL) 556 557 #define A_SGE_VF_KTIMESTAMP_HI 0xc 558 #define A_SGE_CONTROL 0x1008 559 560 #define S_FLSPLITMODE 20 561 #define M_FLSPLITMODE 0x3U 562 #define V_FLSPLITMODE(x) ((x) << S_FLSPLITMODE) 563 #define G_FLSPLITMODE(x) (((x) >> S_FLSPLITMODE) & M_FLSPLITMODE) 564 565 #define S_RXPKTCPLMODE 18 566 #define V_RXPKTCPLMODE(x) ((x) << S_RXPKTCPLMODE) 567 #define F_RXPKTCPLMODE V_RXPKTCPLMODE(1U) 568 569 #define S_EGRSTATUSPAGESIZE 17 570 #define V_EGRSTATUSPAGESIZE(x) ((x) << S_EGRSTATUSPAGESIZE) 571 #define F_EGRSTATUSPAGESIZE V_EGRSTATUSPAGESIZE(1U) 572 573 #define S_PKTSHIFT 10 574 #define M_PKTSHIFT 0x7U 575 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT) 576 #define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT) 577 578 #define S_INGPADBOUNDARY 4 579 #define M_INGPADBOUNDARY 0x7U 580 #define V_INGPADBOUNDARY(x) ((x) << S_INGPADBOUNDARY) 581 #define G_INGPADBOUNDARY(x) (((x) >> S_INGPADBOUNDARY) & M_INGPADBOUNDARY) 582 583 #define S_GLOBALENABLE 0 584 #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE) 585 #define F_GLOBALENABLE V_GLOBALENABLE(1U) 586 587 #define S_IGRALLCPLTOFL 31 588 #define V_IGRALLCPLTOFL(x) ((x) << S_IGRALLCPLTOFL) 589 #define F_IGRALLCPLTOFL V_IGRALLCPLTOFL(1U) 590 591 #define S_FLSPLITMIN 22 592 #define M_FLSPLITMIN 0x1ffU 593 #define V_FLSPLITMIN(x) ((x) << S_FLSPLITMIN) 594 #define G_FLSPLITMIN(x) (((x) >> S_FLSPLITMIN) & M_FLSPLITMIN) 595 596 #define S_INGHINTENABLE1 15 597 #define V_INGHINTENABLE1(x) ((x) << S_INGHINTENABLE1) 598 #define F_INGHINTENABLE1 V_INGHINTENABLE1(1U) 599 600 #define S_INGHINTENABLE0 14 601 #define V_INGHINTENABLE0(x) ((x) << S_INGHINTENABLE0) 602 #define F_INGHINTENABLE0 V_INGHINTENABLE0(1U) 603 604 #define S_INGINTCOMPAREIDX 13 605 #define V_INGINTCOMPAREIDX(x) ((x) << S_INGINTCOMPAREIDX) 606 #define F_INGINTCOMPAREIDX V_INGINTCOMPAREIDX(1U) 607 608 #define S_INGPCIEBOUNDARY 7 609 #define M_INGPCIEBOUNDARY 0x7U 610 #define V_INGPCIEBOUNDARY(x) ((x) << S_INGPCIEBOUNDARY) 611 #define G_INGPCIEBOUNDARY(x) (((x) >> S_INGPCIEBOUNDARY) & M_INGPCIEBOUNDARY) 612 613 #define A_SGE_HOST_PAGE_SIZE 0x100c 614 615 #define S_HOSTPAGESIZEPF7 28 616 #define M_HOSTPAGESIZEPF7 0xfU 617 #define V_HOSTPAGESIZEPF7(x) ((x) << S_HOSTPAGESIZEPF7) 618 #define G_HOSTPAGESIZEPF7(x) (((x) >> S_HOSTPAGESIZEPF7) & M_HOSTPAGESIZEPF7) 619 620 #define S_HOSTPAGESIZEPF6 24 621 #define M_HOSTPAGESIZEPF6 0xfU 622 #define V_HOSTPAGESIZEPF6(x) ((x) << S_HOSTPAGESIZEPF6) 623 #define G_HOSTPAGESIZEPF6(x) (((x) >> S_HOSTPAGESIZEPF6) & M_HOSTPAGESIZEPF6) 624 625 #define S_HOSTPAGESIZEPF5 20 626 #define M_HOSTPAGESIZEPF5 0xfU 627 #define V_HOSTPAGESIZEPF5(x) ((x) << S_HOSTPAGESIZEPF5) 628 #define G_HOSTPAGESIZEPF5(x) (((x) >> S_HOSTPAGESIZEPF5) & M_HOSTPAGESIZEPF5) 629 630 #define S_HOSTPAGESIZEPF4 16 631 #define M_HOSTPAGESIZEPF4 0xfU 632 #define V_HOSTPAGESIZEPF4(x) ((x) << S_HOSTPAGESIZEPF4) 633 #define G_HOSTPAGESIZEPF4(x) (((x) >> S_HOSTPAGESIZEPF4) & M_HOSTPAGESIZEPF4) 634 635 #define S_HOSTPAGESIZEPF3 12 636 #define M_HOSTPAGESIZEPF3 0xfU 637 #define V_HOSTPAGESIZEPF3(x) ((x) << S_HOSTPAGESIZEPF3) 638 #define G_HOSTPAGESIZEPF3(x) (((x) >> S_HOSTPAGESIZEPF3) & M_HOSTPAGESIZEPF3) 639 640 #define S_HOSTPAGESIZEPF2 8 641 #define M_HOSTPAGESIZEPF2 0xfU 642 #define V_HOSTPAGESIZEPF2(x) ((x) << S_HOSTPAGESIZEPF2) 643 #define G_HOSTPAGESIZEPF2(x) (((x) >> S_HOSTPAGESIZEPF2) & M_HOSTPAGESIZEPF2) 644 645 #define S_HOSTPAGESIZEPF1 4 646 #define M_HOSTPAGESIZEPF1 0xfU 647 #define V_HOSTPAGESIZEPF1(x) ((x) << S_HOSTPAGESIZEPF1) 648 #define G_HOSTPAGESIZEPF1(x) (((x) >> S_HOSTPAGESIZEPF1) & M_HOSTPAGESIZEPF1) 649 650 #define S_HOSTPAGESIZEPF0 0 651 #define M_HOSTPAGESIZEPF0 0xfU 652 #define V_HOSTPAGESIZEPF0(x) ((x) << S_HOSTPAGESIZEPF0) 653 #define G_HOSTPAGESIZEPF0(x) (((x) >> S_HOSTPAGESIZEPF0) & M_HOSTPAGESIZEPF0) 654 655 #define A_SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010 656 657 #define S_QUEUESPERPAGEPF7 28 658 #define M_QUEUESPERPAGEPF7 0xfU 659 #define V_QUEUESPERPAGEPF7(x) ((x) << S_QUEUESPERPAGEPF7) 660 #define G_QUEUESPERPAGEPF7(x) (((x) >> S_QUEUESPERPAGEPF7) & M_QUEUESPERPAGEPF7) 661 662 #define S_QUEUESPERPAGEPF6 24 663 #define M_QUEUESPERPAGEPF6 0xfU 664 #define V_QUEUESPERPAGEPF6(x) ((x) << S_QUEUESPERPAGEPF6) 665 #define G_QUEUESPERPAGEPF6(x) (((x) >> S_QUEUESPERPAGEPF6) & M_QUEUESPERPAGEPF6) 666 667 #define S_QUEUESPERPAGEPF5 20 668 #define M_QUEUESPERPAGEPF5 0xfU 669 #define V_QUEUESPERPAGEPF5(x) ((x) << S_QUEUESPERPAGEPF5) 670 #define G_QUEUESPERPAGEPF5(x) (((x) >> S_QUEUESPERPAGEPF5) & M_QUEUESPERPAGEPF5) 671 672 #define S_QUEUESPERPAGEPF4 16 673 #define M_QUEUESPERPAGEPF4 0xfU 674 #define V_QUEUESPERPAGEPF4(x) ((x) << S_QUEUESPERPAGEPF4) 675 #define G_QUEUESPERPAGEPF4(x) (((x) >> S_QUEUESPERPAGEPF4) & M_QUEUESPERPAGEPF4) 676 677 #define S_QUEUESPERPAGEPF3 12 678 #define M_QUEUESPERPAGEPF3 0xfU 679 #define V_QUEUESPERPAGEPF3(x) ((x) << S_QUEUESPERPAGEPF3) 680 #define G_QUEUESPERPAGEPF3(x) (((x) >> S_QUEUESPERPAGEPF3) & M_QUEUESPERPAGEPF3) 681 682 #define S_QUEUESPERPAGEPF2 8 683 #define M_QUEUESPERPAGEPF2 0xfU 684 #define V_QUEUESPERPAGEPF2(x) ((x) << S_QUEUESPERPAGEPF2) 685 #define G_QUEUESPERPAGEPF2(x) (((x) >> S_QUEUESPERPAGEPF2) & M_QUEUESPERPAGEPF2) 686 687 #define S_QUEUESPERPAGEPF1 4 688 #define M_QUEUESPERPAGEPF1 0xfU 689 #define V_QUEUESPERPAGEPF1(x) ((x) << S_QUEUESPERPAGEPF1) 690 #define G_QUEUESPERPAGEPF1(x) (((x) >> S_QUEUESPERPAGEPF1) & M_QUEUESPERPAGEPF1) 691 692 #define S_QUEUESPERPAGEPF0 0 693 #define M_QUEUESPERPAGEPF0 0xfU 694 #define V_QUEUESPERPAGEPF0(x) ((x) << S_QUEUESPERPAGEPF0) 695 #define G_QUEUESPERPAGEPF0(x) (((x) >> S_QUEUESPERPAGEPF0) & M_QUEUESPERPAGEPF0) 696 697 #define A_SGE_EGRESS_QUEUES_PER_PAGE_VF 0x1014 698 699 #define S_QUEUESPERPAGEVFPF7 28 700 #define M_QUEUESPERPAGEVFPF7 0xfU 701 #define V_QUEUESPERPAGEVFPF7(x) ((x) << S_QUEUESPERPAGEVFPF7) 702 #define G_QUEUESPERPAGEVFPF7(x) (((x) >> S_QUEUESPERPAGEVFPF7) & M_QUEUESPERPAGEVFPF7) 703 704 #define S_QUEUESPERPAGEVFPF6 24 705 #define M_QUEUESPERPAGEVFPF6 0xfU 706 #define V_QUEUESPERPAGEVFPF6(x) ((x) << S_QUEUESPERPAGEVFPF6) 707 #define G_QUEUESPERPAGEVFPF6(x) (((x) >> S_QUEUESPERPAGEVFPF6) & M_QUEUESPERPAGEVFPF6) 708 709 #define S_QUEUESPERPAGEVFPF5 20 710 #define M_QUEUESPERPAGEVFPF5 0xfU 711 #define V_QUEUESPERPAGEVFPF5(x) ((x) << S_QUEUESPERPAGEVFPF5) 712 #define G_QUEUESPERPAGEVFPF5(x) (((x) >> S_QUEUESPERPAGEVFPF5) & M_QUEUESPERPAGEVFPF5) 713 714 #define S_QUEUESPERPAGEVFPF4 16 715 #define M_QUEUESPERPAGEVFPF4 0xfU 716 #define V_QUEUESPERPAGEVFPF4(x) ((x) << S_QUEUESPERPAGEVFPF4) 717 #define G_QUEUESPERPAGEVFPF4(x) (((x) >> S_QUEUESPERPAGEVFPF4) & M_QUEUESPERPAGEVFPF4) 718 719 #define S_QUEUESPERPAGEVFPF3 12 720 #define M_QUEUESPERPAGEVFPF3 0xfU 721 #define V_QUEUESPERPAGEVFPF3(x) ((x) << S_QUEUESPERPAGEVFPF3) 722 #define G_QUEUESPERPAGEVFPF3(x) (((x) >> S_QUEUESPERPAGEVFPF3) & M_QUEUESPERPAGEVFPF3) 723 724 #define S_QUEUESPERPAGEVFPF2 8 725 #define M_QUEUESPERPAGEVFPF2 0xfU 726 #define V_QUEUESPERPAGEVFPF2(x) ((x) << S_QUEUESPERPAGEVFPF2) 727 #define G_QUEUESPERPAGEVFPF2(x) (((x) >> S_QUEUESPERPAGEVFPF2) & M_QUEUESPERPAGEVFPF2) 728 729 #define S_QUEUESPERPAGEVFPF1 4 730 #define M_QUEUESPERPAGEVFPF1 0xfU 731 #define V_QUEUESPERPAGEVFPF1(x) ((x) << S_QUEUESPERPAGEVFPF1) 732 #define G_QUEUESPERPAGEVFPF1(x) (((x) >> S_QUEUESPERPAGEVFPF1) & M_QUEUESPERPAGEVFPF1) 733 734 #define S_QUEUESPERPAGEVFPF0 0 735 #define M_QUEUESPERPAGEVFPF0 0xfU 736 #define V_QUEUESPERPAGEVFPF0(x) ((x) << S_QUEUESPERPAGEVFPF0) 737 #define G_QUEUESPERPAGEVFPF0(x) (((x) >> S_QUEUESPERPAGEVFPF0) & M_QUEUESPERPAGEVFPF0) 738 739 #define A_SGE_USER_MODE_LIMITS 0x1018 740 741 #define S_OPCODE_MIN 24 742 #define M_OPCODE_MIN 0xffU 743 #define V_OPCODE_MIN(x) ((x) << S_OPCODE_MIN) 744 #define G_OPCODE_MIN(x) (((x) >> S_OPCODE_MIN) & M_OPCODE_MIN) 745 746 #define S_OPCODE_MAX 16 747 #define M_OPCODE_MAX 0xffU 748 #define V_OPCODE_MAX(x) ((x) << S_OPCODE_MAX) 749 #define G_OPCODE_MAX(x) (((x) >> S_OPCODE_MAX) & M_OPCODE_MAX) 750 751 #define S_LENGTH_MIN 8 752 #define M_LENGTH_MIN 0xffU 753 #define V_LENGTH_MIN(x) ((x) << S_LENGTH_MIN) 754 #define G_LENGTH_MIN(x) (((x) >> S_LENGTH_MIN) & M_LENGTH_MIN) 755 756 #define S_LENGTH_MAX 0 757 #define M_LENGTH_MAX 0xffU 758 #define V_LENGTH_MAX(x) ((x) << S_LENGTH_MAX) 759 #define G_LENGTH_MAX(x) (((x) >> S_LENGTH_MAX) & M_LENGTH_MAX) 760 761 #define A_SGE_WR_ERROR 0x101c 762 763 #define S_WR_ERROR_OPCODE 0 764 #define M_WR_ERROR_OPCODE 0xffU 765 #define V_WR_ERROR_OPCODE(x) ((x) << S_WR_ERROR_OPCODE) 766 #define G_WR_ERROR_OPCODE(x) (((x) >> S_WR_ERROR_OPCODE) & M_WR_ERROR_OPCODE) 767 768 #define A_SGE_INT_CAUSE1 0x1024 769 770 #define S_PERR_FLM_CREDITFIFO 30 771 #define V_PERR_FLM_CREDITFIFO(x) ((x) << S_PERR_FLM_CREDITFIFO) 772 #define F_PERR_FLM_CREDITFIFO V_PERR_FLM_CREDITFIFO(1U) 773 774 #define S_PERR_IMSG_HINT_FIFO 29 775 #define V_PERR_IMSG_HINT_FIFO(x) ((x) << S_PERR_IMSG_HINT_FIFO) 776 #define F_PERR_IMSG_HINT_FIFO V_PERR_IMSG_HINT_FIFO(1U) 777 778 #define S_PERR_MC_PC 28 779 #define V_PERR_MC_PC(x) ((x) << S_PERR_MC_PC) 780 #define F_PERR_MC_PC V_PERR_MC_PC(1U) 781 782 #define S_PERR_MC_IGR_CTXT 27 783 #define V_PERR_MC_IGR_CTXT(x) ((x) << S_PERR_MC_IGR_CTXT) 784 #define F_PERR_MC_IGR_CTXT V_PERR_MC_IGR_CTXT(1U) 785 786 #define S_PERR_MC_EGR_CTXT 26 787 #define V_PERR_MC_EGR_CTXT(x) ((x) << S_PERR_MC_EGR_CTXT) 788 #define F_PERR_MC_EGR_CTXT V_PERR_MC_EGR_CTXT(1U) 789 790 #define S_PERR_MC_FLM 25 791 #define V_PERR_MC_FLM(x) ((x) << S_PERR_MC_FLM) 792 #define F_PERR_MC_FLM V_PERR_MC_FLM(1U) 793 794 #define S_PERR_PC_MCTAG 24 795 #define V_PERR_PC_MCTAG(x) ((x) << S_PERR_PC_MCTAG) 796 #define F_PERR_PC_MCTAG V_PERR_PC_MCTAG(1U) 797 798 #define S_PERR_PC_CHPI_RSP1 23 799 #define V_PERR_PC_CHPI_RSP1(x) ((x) << S_PERR_PC_CHPI_RSP1) 800 #define F_PERR_PC_CHPI_RSP1 V_PERR_PC_CHPI_RSP1(1U) 801 802 #define S_PERR_PC_CHPI_RSP0 22 803 #define V_PERR_PC_CHPI_RSP0(x) ((x) << S_PERR_PC_CHPI_RSP0) 804 #define F_PERR_PC_CHPI_RSP0 V_PERR_PC_CHPI_RSP0(1U) 805 806 #define S_PERR_DBP_PC_RSP_FIFO3 21 807 #define V_PERR_DBP_PC_RSP_FIFO3(x) ((x) << S_PERR_DBP_PC_RSP_FIFO3) 808 #define F_PERR_DBP_PC_RSP_FIFO3 V_PERR_DBP_PC_RSP_FIFO3(1U) 809 810 #define S_PERR_DBP_PC_RSP_FIFO2 20 811 #define V_PERR_DBP_PC_RSP_FIFO2(x) ((x) << S_PERR_DBP_PC_RSP_FIFO2) 812 #define F_PERR_DBP_PC_RSP_FIFO2 V_PERR_DBP_PC_RSP_FIFO2(1U) 813 814 #define S_PERR_DBP_PC_RSP_FIFO1 19 815 #define V_PERR_DBP_PC_RSP_FIFO1(x) ((x) << S_PERR_DBP_PC_RSP_FIFO1) 816 #define F_PERR_DBP_PC_RSP_FIFO1 V_PERR_DBP_PC_RSP_FIFO1(1U) 817 818 #define S_PERR_DBP_PC_RSP_FIFO0 18 819 #define V_PERR_DBP_PC_RSP_FIFO0(x) ((x) << S_PERR_DBP_PC_RSP_FIFO0) 820 #define F_PERR_DBP_PC_RSP_FIFO0 V_PERR_DBP_PC_RSP_FIFO0(1U) 821 822 #define S_PERR_DMARBT 17 823 #define V_PERR_DMARBT(x) ((x) << S_PERR_DMARBT) 824 #define F_PERR_DMARBT V_PERR_DMARBT(1U) 825 826 #define S_PERR_FLM_DBPFIFO 16 827 #define V_PERR_FLM_DBPFIFO(x) ((x) << S_PERR_FLM_DBPFIFO) 828 #define F_PERR_FLM_DBPFIFO V_PERR_FLM_DBPFIFO(1U) 829 830 #define S_PERR_FLM_MCREQ_FIFO 15 831 #define V_PERR_FLM_MCREQ_FIFO(x) ((x) << S_PERR_FLM_MCREQ_FIFO) 832 #define F_PERR_FLM_MCREQ_FIFO V_PERR_FLM_MCREQ_FIFO(1U) 833 834 #define S_PERR_FLM_HINTFIFO 14 835 #define V_PERR_FLM_HINTFIFO(x) ((x) << S_PERR_FLM_HINTFIFO) 836 #define F_PERR_FLM_HINTFIFO V_PERR_FLM_HINTFIFO(1U) 837 838 #define S_PERR_ALIGN_CTL_FIFO3 13 839 #define V_PERR_ALIGN_CTL_FIFO3(x) ((x) << S_PERR_ALIGN_CTL_FIFO3) 840 #define F_PERR_ALIGN_CTL_FIFO3 V_PERR_ALIGN_CTL_FIFO3(1U) 841 842 #define S_PERR_ALIGN_CTL_FIFO2 12 843 #define V_PERR_ALIGN_CTL_FIFO2(x) ((x) << S_PERR_ALIGN_CTL_FIFO2) 844 #define F_PERR_ALIGN_CTL_FIFO2 V_PERR_ALIGN_CTL_FIFO2(1U) 845 846 #define S_PERR_ALIGN_CTL_FIFO1 11 847 #define V_PERR_ALIGN_CTL_FIFO1(x) ((x) << S_PERR_ALIGN_CTL_FIFO1) 848 #define F_PERR_ALIGN_CTL_FIFO1 V_PERR_ALIGN_CTL_FIFO1(1U) 849 850 #define S_PERR_ALIGN_CTL_FIFO0 10 851 #define V_PERR_ALIGN_CTL_FIFO0(x) ((x) << S_PERR_ALIGN_CTL_FIFO0) 852 #define F_PERR_ALIGN_CTL_FIFO0 V_PERR_ALIGN_CTL_FIFO0(1U) 853 854 #define S_PERR_EDMA_FIFO3 9 855 #define V_PERR_EDMA_FIFO3(x) ((x) << S_PERR_EDMA_FIFO3) 856 #define F_PERR_EDMA_FIFO3 V_PERR_EDMA_FIFO3(1U) 857 858 #define S_PERR_EDMA_FIFO2 8 859 #define V_PERR_EDMA_FIFO2(x) ((x) << S_PERR_EDMA_FIFO2) 860 #define F_PERR_EDMA_FIFO2 V_PERR_EDMA_FIFO2(1U) 861 862 #define S_PERR_EDMA_FIFO1 7 863 #define V_PERR_EDMA_FIFO1(x) ((x) << S_PERR_EDMA_FIFO1) 864 #define F_PERR_EDMA_FIFO1 V_PERR_EDMA_FIFO1(1U) 865 866 #define S_PERR_EDMA_FIFO0 6 867 #define V_PERR_EDMA_FIFO0(x) ((x) << S_PERR_EDMA_FIFO0) 868 #define F_PERR_EDMA_FIFO0 V_PERR_EDMA_FIFO0(1U) 869 870 #define S_PERR_PD_FIFO3 5 871 #define V_PERR_PD_FIFO3(x) ((x) << S_PERR_PD_FIFO3) 872 #define F_PERR_PD_FIFO3 V_PERR_PD_FIFO3(1U) 873 874 #define S_PERR_PD_FIFO2 4 875 #define V_PERR_PD_FIFO2(x) ((x) << S_PERR_PD_FIFO2) 876 #define F_PERR_PD_FIFO2 V_PERR_PD_FIFO2(1U) 877 878 #define S_PERR_PD_FIFO1 3 879 #define V_PERR_PD_FIFO1(x) ((x) << S_PERR_PD_FIFO1) 880 #define F_PERR_PD_FIFO1 V_PERR_PD_FIFO1(1U) 881 882 #define S_PERR_PD_FIFO0 2 883 #define V_PERR_PD_FIFO0(x) ((x) << S_PERR_PD_FIFO0) 884 #define F_PERR_PD_FIFO0 V_PERR_PD_FIFO0(1U) 885 886 #define S_PERR_ING_CTXT_MIFRSP 1 887 #define V_PERR_ING_CTXT_MIFRSP(x) ((x) << S_PERR_ING_CTXT_MIFRSP) 888 #define F_PERR_ING_CTXT_MIFRSP V_PERR_ING_CTXT_MIFRSP(1U) 889 890 #define S_PERR_EGR_CTXT_MIFRSP 0 891 #define V_PERR_EGR_CTXT_MIFRSP(x) ((x) << S_PERR_EGR_CTXT_MIFRSP) 892 #define F_PERR_EGR_CTXT_MIFRSP V_PERR_EGR_CTXT_MIFRSP(1U) 893 894 #define S_PERR_PC_CHPI_RSP2 31 895 #define V_PERR_PC_CHPI_RSP2(x) ((x) << S_PERR_PC_CHPI_RSP2) 896 #define F_PERR_PC_CHPI_RSP2 V_PERR_PC_CHPI_RSP2(1U) 897 898 #define S_PERR_PC_RSP 23 899 #define V_PERR_PC_RSP(x) ((x) << S_PERR_PC_RSP) 900 #define F_PERR_PC_RSP V_PERR_PC_RSP(1U) 901 902 #define S_PERR_PC_REQ 22 903 #define V_PERR_PC_REQ(x) ((x) << S_PERR_PC_REQ) 904 #define F_PERR_PC_REQ V_PERR_PC_REQ(1U) 905 906 #define A_SGE_INT_ENABLE1 0x1028 907 #define A_SGE_PERR_ENABLE1 0x102c 908 #define A_SGE_INT_CAUSE2 0x1030 909 910 #define S_PERR_HINT_DELAY_FIFO1 30 911 #define V_PERR_HINT_DELAY_FIFO1(x) ((x) << S_PERR_HINT_DELAY_FIFO1) 912 #define F_PERR_HINT_DELAY_FIFO1 V_PERR_HINT_DELAY_FIFO1(1U) 913 914 #define S_PERR_HINT_DELAY_FIFO0 29 915 #define V_PERR_HINT_DELAY_FIFO0(x) ((x) << S_PERR_HINT_DELAY_FIFO0) 916 #define F_PERR_HINT_DELAY_FIFO0 V_PERR_HINT_DELAY_FIFO0(1U) 917 918 #define S_PERR_IMSG_PD_FIFO 28 919 #define V_PERR_IMSG_PD_FIFO(x) ((x) << S_PERR_IMSG_PD_FIFO) 920 #define F_PERR_IMSG_PD_FIFO V_PERR_IMSG_PD_FIFO(1U) 921 922 #define S_PERR_ULPTX_FIFO1 27 923 #define V_PERR_ULPTX_FIFO1(x) ((x) << S_PERR_ULPTX_FIFO1) 924 #define F_PERR_ULPTX_FIFO1 V_PERR_ULPTX_FIFO1(1U) 925 926 #define S_PERR_ULPTX_FIFO0 26 927 #define V_PERR_ULPTX_FIFO0(x) ((x) << S_PERR_ULPTX_FIFO0) 928 #define F_PERR_ULPTX_FIFO0 V_PERR_ULPTX_FIFO0(1U) 929 930 #define S_PERR_IDMA2IMSG_FIFO1 25 931 #define V_PERR_IDMA2IMSG_FIFO1(x) ((x) << S_PERR_IDMA2IMSG_FIFO1) 932 #define F_PERR_IDMA2IMSG_FIFO1 V_PERR_IDMA2IMSG_FIFO1(1U) 933 934 #define S_PERR_IDMA2IMSG_FIFO0 24 935 #define V_PERR_IDMA2IMSG_FIFO0(x) ((x) << S_PERR_IDMA2IMSG_FIFO0) 936 #define F_PERR_IDMA2IMSG_FIFO0 V_PERR_IDMA2IMSG_FIFO0(1U) 937 938 #define S_PERR_HEADERSPLIT_FIFO1 23 939 #define V_PERR_HEADERSPLIT_FIFO1(x) ((x) << S_PERR_HEADERSPLIT_FIFO1) 940 #define F_PERR_HEADERSPLIT_FIFO1 V_PERR_HEADERSPLIT_FIFO1(1U) 941 942 #define S_PERR_HEADERSPLIT_FIFO0 22 943 #define V_PERR_HEADERSPLIT_FIFO0(x) ((x) << S_PERR_HEADERSPLIT_FIFO0) 944 #define F_PERR_HEADERSPLIT_FIFO0 V_PERR_HEADERSPLIT_FIFO0(1U) 945 946 #define S_PERR_ESWITCH_FIFO3 21 947 #define V_PERR_ESWITCH_FIFO3(x) ((x) << S_PERR_ESWITCH_FIFO3) 948 #define F_PERR_ESWITCH_FIFO3 V_PERR_ESWITCH_FIFO3(1U) 949 950 #define S_PERR_ESWITCH_FIFO2 20 951 #define V_PERR_ESWITCH_FIFO2(x) ((x) << S_PERR_ESWITCH_FIFO2) 952 #define F_PERR_ESWITCH_FIFO2 V_PERR_ESWITCH_FIFO2(1U) 953 954 #define S_PERR_ESWITCH_FIFO1 19 955 #define V_PERR_ESWITCH_FIFO1(x) ((x) << S_PERR_ESWITCH_FIFO1) 956 #define F_PERR_ESWITCH_FIFO1 V_PERR_ESWITCH_FIFO1(1U) 957 958 #define S_PERR_ESWITCH_FIFO0 18 959 #define V_PERR_ESWITCH_FIFO0(x) ((x) << S_PERR_ESWITCH_FIFO0) 960 #define F_PERR_ESWITCH_FIFO0 V_PERR_ESWITCH_FIFO0(1U) 961 962 #define S_PERR_PC_DBP1 17 963 #define V_PERR_PC_DBP1(x) ((x) << S_PERR_PC_DBP1) 964 #define F_PERR_PC_DBP1 V_PERR_PC_DBP1(1U) 965 966 #define S_PERR_PC_DBP0 16 967 #define V_PERR_PC_DBP0(x) ((x) << S_PERR_PC_DBP0) 968 #define F_PERR_PC_DBP0 V_PERR_PC_DBP0(1U) 969 970 #define S_PERR_IMSG_OB_FIFO 15 971 #define V_PERR_IMSG_OB_FIFO(x) ((x) << S_PERR_IMSG_OB_FIFO) 972 #define F_PERR_IMSG_OB_FIFO V_PERR_IMSG_OB_FIFO(1U) 973 974 #define S_PERR_CONM_SRAM 14 975 #define V_PERR_CONM_SRAM(x) ((x) << S_PERR_CONM_SRAM) 976 #define F_PERR_CONM_SRAM V_PERR_CONM_SRAM(1U) 977 978 #define S_PERR_PC_MC_RSP 13 979 #define V_PERR_PC_MC_RSP(x) ((x) << S_PERR_PC_MC_RSP) 980 #define F_PERR_PC_MC_RSP V_PERR_PC_MC_RSP(1U) 981 982 #define S_PERR_ISW_IDMA0_FIFO 12 983 #define V_PERR_ISW_IDMA0_FIFO(x) ((x) << S_PERR_ISW_IDMA0_FIFO) 984 #define F_PERR_ISW_IDMA0_FIFO V_PERR_ISW_IDMA0_FIFO(1U) 985 986 #define S_PERR_ISW_IDMA1_FIFO 11 987 #define V_PERR_ISW_IDMA1_FIFO(x) ((x) << S_PERR_ISW_IDMA1_FIFO) 988 #define F_PERR_ISW_IDMA1_FIFO V_PERR_ISW_IDMA1_FIFO(1U) 989 990 #define S_PERR_ISW_DBP_FIFO 10 991 #define V_PERR_ISW_DBP_FIFO(x) ((x) << S_PERR_ISW_DBP_FIFO) 992 #define F_PERR_ISW_DBP_FIFO V_PERR_ISW_DBP_FIFO(1U) 993 994 #define S_PERR_ISW_GTS_FIFO 9 995 #define V_PERR_ISW_GTS_FIFO(x) ((x) << S_PERR_ISW_GTS_FIFO) 996 #define F_PERR_ISW_GTS_FIFO V_PERR_ISW_GTS_FIFO(1U) 997 998 #define S_PERR_ITP_EVR 8 999 #define V_PERR_ITP_EVR(x) ((x) << S_PERR_ITP_EVR) 1000 #define F_PERR_ITP_EVR V_PERR_ITP_EVR(1U) 1001 1002 #define S_PERR_FLM_CNTXMEM 7 1003 #define V_PERR_FLM_CNTXMEM(x) ((x) << S_PERR_FLM_CNTXMEM) 1004 #define F_PERR_FLM_CNTXMEM V_PERR_FLM_CNTXMEM(1U) 1005 1006 #define S_PERR_FLM_L1CACHE 6 1007 #define V_PERR_FLM_L1CACHE(x) ((x) << S_PERR_FLM_L1CACHE) 1008 #define F_PERR_FLM_L1CACHE V_PERR_FLM_L1CACHE(1U) 1009 1010 #define S_PERR_DBP_HINT_FIFO 5 1011 #define V_PERR_DBP_HINT_FIFO(x) ((x) << S_PERR_DBP_HINT_FIFO) 1012 #define F_PERR_DBP_HINT_FIFO V_PERR_DBP_HINT_FIFO(1U) 1013 1014 #define S_PERR_DBP_HP_FIFO 4 1015 #define V_PERR_DBP_HP_FIFO(x) ((x) << S_PERR_DBP_HP_FIFO) 1016 #define F_PERR_DBP_HP_FIFO V_PERR_DBP_HP_FIFO(1U) 1017 1018 #define S_PERR_DBP_LP_FIFO 3 1019 #define V_PERR_DBP_LP_FIFO(x) ((x) << S_PERR_DBP_LP_FIFO) 1020 #define F_PERR_DBP_LP_FIFO V_PERR_DBP_LP_FIFO(1U) 1021 1022 #define S_PERR_ING_CTXT_CACHE 2 1023 #define V_PERR_ING_CTXT_CACHE(x) ((x) << S_PERR_ING_CTXT_CACHE) 1024 #define F_PERR_ING_CTXT_CACHE V_PERR_ING_CTXT_CACHE(1U) 1025 1026 #define S_PERR_EGR_CTXT_CACHE 1 1027 #define V_PERR_EGR_CTXT_CACHE(x) ((x) << S_PERR_EGR_CTXT_CACHE) 1028 #define F_PERR_EGR_CTXT_CACHE V_PERR_EGR_CTXT_CACHE(1U) 1029 1030 #define S_PERR_BASE_SIZE 0 1031 #define V_PERR_BASE_SIZE(x) ((x) << S_PERR_BASE_SIZE) 1032 #define F_PERR_BASE_SIZE V_PERR_BASE_SIZE(1U) 1033 1034 #define S_PERR_DBP_HINT_FL_FIFO 24 1035 #define V_PERR_DBP_HINT_FL_FIFO(x) ((x) << S_PERR_DBP_HINT_FL_FIFO) 1036 #define F_PERR_DBP_HINT_FL_FIFO V_PERR_DBP_HINT_FL_FIFO(1U) 1037 1038 #define S_PERR_EGR_DBP_TX_COAL 23 1039 #define V_PERR_EGR_DBP_TX_COAL(x) ((x) << S_PERR_EGR_DBP_TX_COAL) 1040 #define F_PERR_EGR_DBP_TX_COAL V_PERR_EGR_DBP_TX_COAL(1U) 1041 1042 #define S_PERR_DBP_FL_FIFO 22 1043 #define V_PERR_DBP_FL_FIFO(x) ((x) << S_PERR_DBP_FL_FIFO) 1044 #define F_PERR_DBP_FL_FIFO V_PERR_DBP_FL_FIFO(1U) 1045 1046 #define S_PERR_PC_DBP2 15 1047 #define V_PERR_PC_DBP2(x) ((x) << S_PERR_PC_DBP2) 1048 #define F_PERR_PC_DBP2 V_PERR_PC_DBP2(1U) 1049 1050 #define S_DEQ_LL_PERR 21 1051 #define V_DEQ_LL_PERR(x) ((x) << S_DEQ_LL_PERR) 1052 #define F_DEQ_LL_PERR V_DEQ_LL_PERR(1U) 1053 1054 #define S_ENQ_PERR 20 1055 #define V_ENQ_PERR(x) ((x) << S_ENQ_PERR) 1056 #define F_ENQ_PERR V_ENQ_PERR(1U) 1057 1058 #define S_DEQ_OUT_PERR 19 1059 #define V_DEQ_OUT_PERR(x) ((x) << S_DEQ_OUT_PERR) 1060 #define F_DEQ_OUT_PERR V_DEQ_OUT_PERR(1U) 1061 1062 #define S_BUF_PERR 18 1063 #define V_BUF_PERR(x) ((x) << S_BUF_PERR) 1064 #define F_BUF_PERR V_BUF_PERR(1U) 1065 1066 #define S_PERR_DB_FIFO 3 1067 #define V_PERR_DB_FIFO(x) ((x) << S_PERR_DB_FIFO) 1068 #define F_PERR_DB_FIFO V_PERR_DB_FIFO(1U) 1069 1070 #define A_SGE_INT_ENABLE2 0x1034 1071 #define A_SGE_PERR_ENABLE2 0x1038 1072 #define A_SGE_INT_CAUSE3 0x103c 1073 1074 #define S_ERR_FLM_DBP 31 1075 #define V_ERR_FLM_DBP(x) ((x) << S_ERR_FLM_DBP) 1076 #define F_ERR_FLM_DBP V_ERR_FLM_DBP(1U) 1077 1078 #define S_ERR_FLM_IDMA1 30 1079 #define V_ERR_FLM_IDMA1(x) ((x) << S_ERR_FLM_IDMA1) 1080 #define F_ERR_FLM_IDMA1 V_ERR_FLM_IDMA1(1U) 1081 1082 #define S_ERR_FLM_IDMA0 29 1083 #define V_ERR_FLM_IDMA0(x) ((x) << S_ERR_FLM_IDMA0) 1084 #define F_ERR_FLM_IDMA0 V_ERR_FLM_IDMA0(1U) 1085 1086 #define S_ERR_FLM_HINT 28 1087 #define V_ERR_FLM_HINT(x) ((x) << S_ERR_FLM_HINT) 1088 #define F_ERR_FLM_HINT V_ERR_FLM_HINT(1U) 1089 1090 #define S_ERR_PCIE_ERROR3 27 1091 #define V_ERR_PCIE_ERROR3(x) ((x) << S_ERR_PCIE_ERROR3) 1092 #define F_ERR_PCIE_ERROR3 V_ERR_PCIE_ERROR3(1U) 1093 1094 #define S_ERR_PCIE_ERROR2 26 1095 #define V_ERR_PCIE_ERROR2(x) ((x) << S_ERR_PCIE_ERROR2) 1096 #define F_ERR_PCIE_ERROR2 V_ERR_PCIE_ERROR2(1U) 1097 1098 #define S_ERR_PCIE_ERROR1 25 1099 #define V_ERR_PCIE_ERROR1(x) ((x) << S_ERR_PCIE_ERROR1) 1100 #define F_ERR_PCIE_ERROR1 V_ERR_PCIE_ERROR1(1U) 1101 1102 #define S_ERR_PCIE_ERROR0 24 1103 #define V_ERR_PCIE_ERROR0(x) ((x) << S_ERR_PCIE_ERROR0) 1104 #define F_ERR_PCIE_ERROR0 V_ERR_PCIE_ERROR0(1U) 1105 1106 #define S_ERR_TIMER_ABOVE_MAX_QID 23 1107 #define V_ERR_TIMER_ABOVE_MAX_QID(x) ((x) << S_ERR_TIMER_ABOVE_MAX_QID) 1108 #define F_ERR_TIMER_ABOVE_MAX_QID V_ERR_TIMER_ABOVE_MAX_QID(1U) 1109 1110 #define S_ERR_CPL_EXCEED_IQE_SIZE 22 1111 #define V_ERR_CPL_EXCEED_IQE_SIZE(x) ((x) << S_ERR_CPL_EXCEED_IQE_SIZE) 1112 #define F_ERR_CPL_EXCEED_IQE_SIZE V_ERR_CPL_EXCEED_IQE_SIZE(1U) 1113 1114 #define S_ERR_INVALID_CIDX_INC 21 1115 #define V_ERR_INVALID_CIDX_INC(x) ((x) << S_ERR_INVALID_CIDX_INC) 1116 #define F_ERR_INVALID_CIDX_INC V_ERR_INVALID_CIDX_INC(1U) 1117 1118 #define S_ERR_ITP_TIME_PAUSED 20 1119 #define V_ERR_ITP_TIME_PAUSED(x) ((x) << S_ERR_ITP_TIME_PAUSED) 1120 #define F_ERR_ITP_TIME_PAUSED V_ERR_ITP_TIME_PAUSED(1U) 1121 1122 #define S_ERR_CPL_OPCODE_0 19 1123 #define V_ERR_CPL_OPCODE_0(x) ((x) << S_ERR_CPL_OPCODE_0) 1124 #define F_ERR_CPL_OPCODE_0 V_ERR_CPL_OPCODE_0(1U) 1125 1126 #define S_ERR_DROPPED_DB 18 1127 #define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB) 1128 #define F_ERR_DROPPED_DB V_ERR_DROPPED_DB(1U) 1129 1130 #define S_ERR_DATA_CPL_ON_HIGH_QID1 17 1131 #define V_ERR_DATA_CPL_ON_HIGH_QID1(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID1) 1132 #define F_ERR_DATA_CPL_ON_HIGH_QID1 V_ERR_DATA_CPL_ON_HIGH_QID1(1U) 1133 1134 #define S_ERR_DATA_CPL_ON_HIGH_QID0 16 1135 #define V_ERR_DATA_CPL_ON_HIGH_QID0(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID0) 1136 #define F_ERR_DATA_CPL_ON_HIGH_QID0 V_ERR_DATA_CPL_ON_HIGH_QID0(1U) 1137 1138 #define S_ERR_BAD_DB_PIDX3 15 1139 #define V_ERR_BAD_DB_PIDX3(x) ((x) << S_ERR_BAD_DB_PIDX3) 1140 #define F_ERR_BAD_DB_PIDX3 V_ERR_BAD_DB_PIDX3(1U) 1141 1142 #define S_ERR_BAD_DB_PIDX2 14 1143 #define V_ERR_BAD_DB_PIDX2(x) ((x) << S_ERR_BAD_DB_PIDX2) 1144 #define F_ERR_BAD_DB_PIDX2 V_ERR_BAD_DB_PIDX2(1U) 1145 1146 #define S_ERR_BAD_DB_PIDX1 13 1147 #define V_ERR_BAD_DB_PIDX1(x) ((x) << S_ERR_BAD_DB_PIDX1) 1148 #define F_ERR_BAD_DB_PIDX1 V_ERR_BAD_DB_PIDX1(1U) 1149 1150 #define S_ERR_BAD_DB_PIDX0 12 1151 #define V_ERR_BAD_DB_PIDX0(x) ((x) << S_ERR_BAD_DB_PIDX0) 1152 #define F_ERR_BAD_DB_PIDX0 V_ERR_BAD_DB_PIDX0(1U) 1153 1154 #define S_ERR_ING_PCIE_CHAN 11 1155 #define V_ERR_ING_PCIE_CHAN(x) ((x) << S_ERR_ING_PCIE_CHAN) 1156 #define F_ERR_ING_PCIE_CHAN V_ERR_ING_PCIE_CHAN(1U) 1157 1158 #define S_ERR_ING_CTXT_PRIO 10 1159 #define V_ERR_ING_CTXT_PRIO(x) ((x) << S_ERR_ING_CTXT_PRIO) 1160 #define F_ERR_ING_CTXT_PRIO V_ERR_ING_CTXT_PRIO(1U) 1161 1162 #define S_ERR_EGR_CTXT_PRIO 9 1163 #define V_ERR_EGR_CTXT_PRIO(x) ((x) << S_ERR_EGR_CTXT_PRIO) 1164 #define F_ERR_EGR_CTXT_PRIO V_ERR_EGR_CTXT_PRIO(1U) 1165 1166 #define S_DBFIFO_HP_INT 8 1167 #define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT) 1168 #define F_DBFIFO_HP_INT V_DBFIFO_HP_INT(1U) 1169 1170 #define S_DBFIFO_LP_INT 7 1171 #define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT) 1172 #define F_DBFIFO_LP_INT V_DBFIFO_LP_INT(1U) 1173 1174 #define S_REG_ADDRESS_ERR 6 1175 #define V_REG_ADDRESS_ERR(x) ((x) << S_REG_ADDRESS_ERR) 1176 #define F_REG_ADDRESS_ERR V_REG_ADDRESS_ERR(1U) 1177 1178 #define S_INGRESS_SIZE_ERR 5 1179 #define V_INGRESS_SIZE_ERR(x) ((x) << S_INGRESS_SIZE_ERR) 1180 #define F_INGRESS_SIZE_ERR V_INGRESS_SIZE_ERR(1U) 1181 1182 #define S_EGRESS_SIZE_ERR 4 1183 #define V_EGRESS_SIZE_ERR(x) ((x) << S_EGRESS_SIZE_ERR) 1184 #define F_EGRESS_SIZE_ERR V_EGRESS_SIZE_ERR(1U) 1185 1186 #define S_ERR_INV_CTXT3 3 1187 #define V_ERR_INV_CTXT3(x) ((x) << S_ERR_INV_CTXT3) 1188 #define F_ERR_INV_CTXT3 V_ERR_INV_CTXT3(1U) 1189 1190 #define S_ERR_INV_CTXT2 2 1191 #define V_ERR_INV_CTXT2(x) ((x) << S_ERR_INV_CTXT2) 1192 #define F_ERR_INV_CTXT2 V_ERR_INV_CTXT2(1U) 1193 1194 #define S_ERR_INV_CTXT1 1 1195 #define V_ERR_INV_CTXT1(x) ((x) << S_ERR_INV_CTXT1) 1196 #define F_ERR_INV_CTXT1 V_ERR_INV_CTXT1(1U) 1197 1198 #define S_ERR_INV_CTXT0 0 1199 #define V_ERR_INV_CTXT0(x) ((x) << S_ERR_INV_CTXT0) 1200 #define F_ERR_INV_CTXT0 V_ERR_INV_CTXT0(1U) 1201 1202 #define S_DBP_TBUF_FULL 8 1203 #define V_DBP_TBUF_FULL(x) ((x) << S_DBP_TBUF_FULL) 1204 #define F_DBP_TBUF_FULL V_DBP_TBUF_FULL(1U) 1205 1206 #define S_FATAL_WRE_LEN 7 1207 #define V_FATAL_WRE_LEN(x) ((x) << S_FATAL_WRE_LEN) 1208 #define F_FATAL_WRE_LEN V_FATAL_WRE_LEN(1U) 1209 1210 #define A_SGE_INT_ENABLE3 0x1040 1211 #define A_SGE_FL_BUFFER_SIZE0 0x1044 1212 1213 #define S_SIZE 4 1214 #define M_SIZE 0xfffffffU 1215 #define V_SIZE(x) ((x) << S_SIZE) 1216 #define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE) 1217 1218 #define S_T6_SIZE 4 1219 #define M_T6_SIZE 0xfffffU 1220 #define V_T6_SIZE(x) ((x) << S_T6_SIZE) 1221 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) 1222 1223 #define A_SGE_FL_BUFFER_SIZE1 0x1048 1224 1225 #define S_T6_SIZE 4 1226 #define M_T6_SIZE 0xfffffU 1227 #define V_T6_SIZE(x) ((x) << S_T6_SIZE) 1228 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) 1229 1230 #define A_SGE_FL_BUFFER_SIZE2 0x104c 1231 1232 #define S_T6_SIZE 4 1233 #define M_T6_SIZE 0xfffffU 1234 #define V_T6_SIZE(x) ((x) << S_T6_SIZE) 1235 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) 1236 1237 #define A_SGE_FL_BUFFER_SIZE3 0x1050 1238 1239 #define S_T6_SIZE 4 1240 #define M_T6_SIZE 0xfffffU 1241 #define V_T6_SIZE(x) ((x) << S_T6_SIZE) 1242 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) 1243 1244 #define A_SGE_FL_BUFFER_SIZE4 0x1054 1245 1246 #define S_T6_SIZE 4 1247 #define M_T6_SIZE 0xfffffU 1248 #define V_T6_SIZE(x) ((x) << S_T6_SIZE) 1249 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) 1250 1251 #define A_SGE_FL_BUFFER_SIZE5 0x1058 1252 1253 #define S_T6_SIZE 4 1254 #define M_T6_SIZE 0xfffffU 1255 #define V_T6_SIZE(x) ((x) << S_T6_SIZE) 1256 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) 1257 1258 #define A_SGE_FL_BUFFER_SIZE6 0x105c 1259 1260 #define S_T6_SIZE 4 1261 #define M_T6_SIZE 0xfffffU 1262 #define V_T6_SIZE(x) ((x) << S_T6_SIZE) 1263 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) 1264 1265 #define A_SGE_FL_BUFFER_SIZE7 0x1060 1266 1267 #define S_T6_SIZE 4 1268 #define M_T6_SIZE 0xfffffU 1269 #define V_T6_SIZE(x) ((x) << S_T6_SIZE) 1270 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) 1271 1272 #define A_SGE_FL_BUFFER_SIZE8 0x1064 1273 1274 #define S_T6_SIZE 4 1275 #define M_T6_SIZE 0xfffffU 1276 #define V_T6_SIZE(x) ((x) << S_T6_SIZE) 1277 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) 1278 1279 #define A_SGE_FL_BUFFER_SIZE9 0x1068 1280 1281 #define S_T6_SIZE 4 1282 #define M_T6_SIZE 0xfffffU 1283 #define V_T6_SIZE(x) ((x) << S_T6_SIZE) 1284 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) 1285 1286 #define A_SGE_FL_BUFFER_SIZE10 0x106c 1287 1288 #define S_T6_SIZE 4 1289 #define M_T6_SIZE 0xfffffU 1290 #define V_T6_SIZE(x) ((x) << S_T6_SIZE) 1291 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) 1292 1293 #define A_SGE_FL_BUFFER_SIZE11 0x1070 1294 1295 #define S_T6_SIZE 4 1296 #define M_T6_SIZE 0xfffffU 1297 #define V_T6_SIZE(x) ((x) << S_T6_SIZE) 1298 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) 1299 1300 #define A_SGE_FL_BUFFER_SIZE12 0x1074 1301 1302 #define S_T6_SIZE 4 1303 #define M_T6_SIZE 0xfffffU 1304 #define V_T6_SIZE(x) ((x) << S_T6_SIZE) 1305 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) 1306 1307 #define A_SGE_FL_BUFFER_SIZE13 0x1078 1308 1309 #define S_T6_SIZE 4 1310 #define M_T6_SIZE 0xfffffU 1311 #define V_T6_SIZE(x) ((x) << S_T6_SIZE) 1312 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) 1313 1314 #define A_SGE_FL_BUFFER_SIZE14 0x107c 1315 1316 #define S_T6_SIZE 4 1317 #define M_T6_SIZE 0xfffffU 1318 #define V_T6_SIZE(x) ((x) << S_T6_SIZE) 1319 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) 1320 1321 #define A_SGE_FL_BUFFER_SIZE15 0x1080 1322 1323 #define S_T6_SIZE 4 1324 #define M_T6_SIZE 0xfffffU 1325 #define V_T6_SIZE(x) ((x) << S_T6_SIZE) 1326 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) 1327 1328 #define A_SGE_DBQ_CTXT_BADDR 0x1084 1329 1330 #define S_BASEADDR 3 1331 #define M_BASEADDR 0x1fffffffU 1332 #define V_BASEADDR(x) ((x) << S_BASEADDR) 1333 #define G_BASEADDR(x) (((x) >> S_BASEADDR) & M_BASEADDR) 1334 1335 #define A_SGE_IMSG_CTXT_BADDR 0x1088 1336 #define A_SGE_FLM_CACHE_BADDR 0x108c 1337 #define A_SGE_FLM_CFG 0x1090 1338 1339 #define S_OPMODE 26 1340 #define M_OPMODE 0x3fU 1341 #define V_OPMODE(x) ((x) << S_OPMODE) 1342 #define G_OPMODE(x) (((x) >> S_OPMODE) & M_OPMODE) 1343 1344 #define S_NULLPTR 20 1345 #define M_NULLPTR 0xfU 1346 #define V_NULLPTR(x) ((x) << S_NULLPTR) 1347 #define G_NULLPTR(x) (((x) >> S_NULLPTR) & M_NULLPTR) 1348 1349 #define S_NULLPTREN 19 1350 #define V_NULLPTREN(x) ((x) << S_NULLPTREN) 1351 #define F_NULLPTREN V_NULLPTREN(1U) 1352 1353 #define S_NOHDR 18 1354 #define V_NOHDR(x) ((x) << S_NOHDR) 1355 #define F_NOHDR V_NOHDR(1U) 1356 1357 #define S_CACHEPTRCNT 16 1358 #define M_CACHEPTRCNT 0x3U 1359 #define V_CACHEPTRCNT(x) ((x) << S_CACHEPTRCNT) 1360 #define G_CACHEPTRCNT(x) (((x) >> S_CACHEPTRCNT) & M_CACHEPTRCNT) 1361 1362 #define S_EDRAMPTRCNT 14 1363 #define M_EDRAMPTRCNT 0x3U 1364 #define V_EDRAMPTRCNT(x) ((x) << S_EDRAMPTRCNT) 1365 #define G_EDRAMPTRCNT(x) (((x) >> S_EDRAMPTRCNT) & M_EDRAMPTRCNT) 1366 1367 #define S_HDRSTARTFLQ 11 1368 #define M_HDRSTARTFLQ 0x7U 1369 #define V_HDRSTARTFLQ(x) ((x) << S_HDRSTARTFLQ) 1370 #define G_HDRSTARTFLQ(x) (((x) >> S_HDRSTARTFLQ) & M_HDRSTARTFLQ) 1371 1372 #define S_FETCHTHRESH 6 1373 #define M_FETCHTHRESH 0x1fU 1374 #define V_FETCHTHRESH(x) ((x) << S_FETCHTHRESH) 1375 #define G_FETCHTHRESH(x) (((x) >> S_FETCHTHRESH) & M_FETCHTHRESH) 1376 1377 #define S_CREDITCNT 4 1378 #define M_CREDITCNT 0x3U 1379 #define V_CREDITCNT(x) ((x) << S_CREDITCNT) 1380 #define G_CREDITCNT(x) (((x) >> S_CREDITCNT) & M_CREDITCNT) 1381 1382 #define S_CREDITCNTPACKING 2 1383 #define M_CREDITCNTPACKING 0x3U 1384 #define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING) 1385 #define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING) 1386 1387 #define S_NOEDRAM 0 1388 #define V_NOEDRAM(x) ((x) << S_NOEDRAM) 1389 #define F_NOEDRAM V_NOEDRAM(1U) 1390 1391 #define A_SGE_CONM_CTRL 0x1094 1392 1393 #define S_EGRTHRESHOLD 8 1394 #define M_EGRTHRESHOLD 0x3fU 1395 #define V_EGRTHRESHOLD(x) ((x) << S_EGRTHRESHOLD) 1396 #define G_EGRTHRESHOLD(x) (((x) >> S_EGRTHRESHOLD) & M_EGRTHRESHOLD) 1397 1398 #define S_EGRTHRESHOLDPACKING 14 1399 #define M_EGRTHRESHOLDPACKING 0x3fU 1400 #define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING) 1401 #define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & M_EGRTHRESHOLDPACKING) 1402 1403 #define S_T6_EGRTHRESHOLDPACKING 16 1404 #define M_T6_EGRTHRESHOLDPACKING 0xffU 1405 #define V_T6_EGRTHRESHOLDPACKING(x) ((x) << S_T6_EGRTHRESHOLDPACKING) 1406 #define G_T6_EGRTHRESHOLDPACKING(x) (((x) >> S_T6_EGRTHRESHOLDPACKING) & M_T6_EGRTHRESHOLDPACKING) 1407 1408 #define S_T6_EGRTHRESHOLD 8 1409 #define M_T6_EGRTHRESHOLD 0xffU 1410 #define V_T6_EGRTHRESHOLD(x) ((x) << S_T6_EGRTHRESHOLD) 1411 #define G_T6_EGRTHRESHOLD(x) (((x) >> S_T6_EGRTHRESHOLD) & M_T6_EGRTHRESHOLD) 1412 1413 #define S_INGTHRESHOLD 2 1414 #define M_INGTHRESHOLD 0x3fU 1415 #define V_INGTHRESHOLD(x) ((x) << S_INGTHRESHOLD) 1416 #define G_INGTHRESHOLD(x) (((x) >> S_INGTHRESHOLD) & M_INGTHRESHOLD) 1417 1418 #define A_SGE_TIMESTAMP_LO 0x1098 1419 #define A_SGE_TIMESTAMP_HI 0x109c 1420 1421 #define S_TSOP 28 1422 #define M_TSOP 0x3U 1423 #define V_TSOP(x) ((x) << S_TSOP) 1424 #define G_TSOP(x) (((x) >> S_TSOP) & M_TSOP) 1425 1426 #define S_TSVAL 0 1427 #define M_TSVAL 0xfffffffU 1428 #define V_TSVAL(x) ((x) << S_TSVAL) 1429 #define G_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL) 1430 1431 #define A_SGE_INGRESS_RX_THRESHOLD 0x10a0 1432 1433 #define S_THRESHOLD_0 24 1434 #define M_THRESHOLD_0 0x3fU 1435 #define V_THRESHOLD_0(x) ((x) << S_THRESHOLD_0) 1436 #define G_THRESHOLD_0(x) (((x) >> S_THRESHOLD_0) & M_THRESHOLD_0) 1437 1438 #define S_THRESHOLD_1 16 1439 #define M_THRESHOLD_1 0x3fU 1440 #define V_THRESHOLD_1(x) ((x) << S_THRESHOLD_1) 1441 #define G_THRESHOLD_1(x) (((x) >> S_THRESHOLD_1) & M_THRESHOLD_1) 1442 1443 #define S_THRESHOLD_2 8 1444 #define M_THRESHOLD_2 0x3fU 1445 #define V_THRESHOLD_2(x) ((x) << S_THRESHOLD_2) 1446 #define G_THRESHOLD_2(x) (((x) >> S_THRESHOLD_2) & M_THRESHOLD_2) 1447 1448 #define S_THRESHOLD_3 0 1449 #define M_THRESHOLD_3 0x3fU 1450 #define V_THRESHOLD_3(x) ((x) << S_THRESHOLD_3) 1451 #define G_THRESHOLD_3(x) (((x) >> S_THRESHOLD_3) & M_THRESHOLD_3) 1452 1453 #define A_SGE_DBFIFO_STATUS 0x10a4 1454 1455 #define S_HP_INT_THRESH 28 1456 #define M_HP_INT_THRESH 0xfU 1457 #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH) 1458 #define G_HP_INT_THRESH(x) (((x) >> S_HP_INT_THRESH) & M_HP_INT_THRESH) 1459 1460 #define S_HP_COUNT 16 1461 #define M_HP_COUNT 0x7ffU 1462 #define V_HP_COUNT(x) ((x) << S_HP_COUNT) 1463 #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT) 1464 1465 #define S_LP_INT_THRESH 12 1466 #define M_LP_INT_THRESH 0xfU 1467 #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH) 1468 #define G_LP_INT_THRESH(x) (((x) >> S_LP_INT_THRESH) & M_LP_INT_THRESH) 1469 1470 #define S_LP_COUNT 0 1471 #define M_LP_COUNT 0x7ffU 1472 #define V_LP_COUNT(x) ((x) << S_LP_COUNT) 1473 #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT) 1474 1475 #define S_BAR2VALID 31 1476 #define V_BAR2VALID(x) ((x) << S_BAR2VALID) 1477 #define F_BAR2VALID V_BAR2VALID(1U) 1478 1479 #define S_BAR2FULL 30 1480 #define V_BAR2FULL(x) ((x) << S_BAR2FULL) 1481 #define F_BAR2FULL V_BAR2FULL(1U) 1482 1483 #define S_LP_INT_THRESH_T5 18 1484 #define M_LP_INT_THRESH_T5 0xfffU 1485 #define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5) 1486 #define G_LP_INT_THRESH_T5(x) (((x) >> S_LP_INT_THRESH_T5) & M_LP_INT_THRESH_T5) 1487 1488 #define S_LP_COUNT_T5 0 1489 #define M_LP_COUNT_T5 0x3ffffU 1490 #define V_LP_COUNT_T5(x) ((x) << S_LP_COUNT_T5) 1491 #define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT_T5) & M_LP_COUNT_T5) 1492 1493 #define S_VFIFO_CNT 15 1494 #define M_VFIFO_CNT 0x1ffffU 1495 #define V_VFIFO_CNT(x) ((x) << S_VFIFO_CNT) 1496 #define G_VFIFO_CNT(x) (((x) >> S_VFIFO_CNT) & M_VFIFO_CNT) 1497 1498 #define S_COAL_CTL_FIFO_CNT 8 1499 #define M_COAL_CTL_FIFO_CNT 0x3fU 1500 #define V_COAL_CTL_FIFO_CNT(x) ((x) << S_COAL_CTL_FIFO_CNT) 1501 #define G_COAL_CTL_FIFO_CNT(x) (((x) >> S_COAL_CTL_FIFO_CNT) & M_COAL_CTL_FIFO_CNT) 1502 1503 #define S_MERGE_FIFO_CNT 0 1504 #define M_MERGE_FIFO_CNT 0x3fU 1505 #define V_MERGE_FIFO_CNT(x) ((x) << S_MERGE_FIFO_CNT) 1506 #define G_MERGE_FIFO_CNT(x) (((x) >> S_MERGE_FIFO_CNT) & M_MERGE_FIFO_CNT) 1507 1508 #define A_SGE_DOORBELL_CONTROL 0x10a8 1509 1510 #define S_HINTDEPTHCTL 27 1511 #define M_HINTDEPTHCTL 0x1fU 1512 #define V_HINTDEPTHCTL(x) ((x) << S_HINTDEPTHCTL) 1513 #define G_HINTDEPTHCTL(x) (((x) >> S_HINTDEPTHCTL) & M_HINTDEPTHCTL) 1514 1515 #define S_NOCOALESCE 26 1516 #define V_NOCOALESCE(x) ((x) << S_NOCOALESCE) 1517 #define F_NOCOALESCE V_NOCOALESCE(1U) 1518 1519 #define S_HP_WEIGHT 24 1520 #define M_HP_WEIGHT 0x3U 1521 #define V_HP_WEIGHT(x) ((x) << S_HP_WEIGHT) 1522 #define G_HP_WEIGHT(x) (((x) >> S_HP_WEIGHT) & M_HP_WEIGHT) 1523 1524 #define S_HP_DISABLE 23 1525 #define V_HP_DISABLE(x) ((x) << S_HP_DISABLE) 1526 #define F_HP_DISABLE V_HP_DISABLE(1U) 1527 1528 #define S_FORCEUSERDBTOLP 22 1529 #define V_FORCEUSERDBTOLP(x) ((x) << S_FORCEUSERDBTOLP) 1530 #define F_FORCEUSERDBTOLP V_FORCEUSERDBTOLP(1U) 1531 1532 #define S_FORCEVFPF0DBTOLP 21 1533 #define V_FORCEVFPF0DBTOLP(x) ((x) << S_FORCEVFPF0DBTOLP) 1534 #define F_FORCEVFPF0DBTOLP V_FORCEVFPF0DBTOLP(1U) 1535 1536 #define S_FORCEVFPF1DBTOLP 20 1537 #define V_FORCEVFPF1DBTOLP(x) ((x) << S_FORCEVFPF1DBTOLP) 1538 #define F_FORCEVFPF1DBTOLP V_FORCEVFPF1DBTOLP(1U) 1539 1540 #define S_FORCEVFPF2DBTOLP 19 1541 #define V_FORCEVFPF2DBTOLP(x) ((x) << S_FORCEVFPF2DBTOLP) 1542 #define F_FORCEVFPF2DBTOLP V_FORCEVFPF2DBTOLP(1U) 1543 1544 #define S_FORCEVFPF3DBTOLP 18 1545 #define V_FORCEVFPF3DBTOLP(x) ((x) << S_FORCEVFPF3DBTOLP) 1546 #define F_FORCEVFPF3DBTOLP V_FORCEVFPF3DBTOLP(1U) 1547 1548 #define S_FORCEVFPF4DBTOLP 17 1549 #define V_FORCEVFPF4DBTOLP(x) ((x) << S_FORCEVFPF4DBTOLP) 1550 #define F_FORCEVFPF4DBTOLP V_FORCEVFPF4DBTOLP(1U) 1551 1552 #define S_FORCEVFPF5DBTOLP 16 1553 #define V_FORCEVFPF5DBTOLP(x) ((x) << S_FORCEVFPF5DBTOLP) 1554 #define F_FORCEVFPF5DBTOLP V_FORCEVFPF5DBTOLP(1U) 1555 1556 #define S_FORCEVFPF6DBTOLP 15 1557 #define V_FORCEVFPF6DBTOLP(x) ((x) << S_FORCEVFPF6DBTOLP) 1558 #define F_FORCEVFPF6DBTOLP V_FORCEVFPF6DBTOLP(1U) 1559 1560 #define S_FORCEVFPF7DBTOLP 14 1561 #define V_FORCEVFPF7DBTOLP(x) ((x) << S_FORCEVFPF7DBTOLP) 1562 #define F_FORCEVFPF7DBTOLP V_FORCEVFPF7DBTOLP(1U) 1563 1564 #define S_ENABLE_DROP 13 1565 #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP) 1566 #define F_ENABLE_DROP V_ENABLE_DROP(1U) 1567 1568 #define S_DROP_TIMEOUT 1 1569 #define M_DROP_TIMEOUT 0xfffU 1570 #define V_DROP_TIMEOUT(x) ((x) << S_DROP_TIMEOUT) 1571 #define G_DROP_TIMEOUT(x) (((x) >> S_DROP_TIMEOUT) & M_DROP_TIMEOUT) 1572 1573 #define S_DROPPED_DB 0 1574 #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB) 1575 #define F_DROPPED_DB V_DROPPED_DB(1U) 1576 1577 #define S_T6_DROP_TIMEOUT 7 1578 #define M_T6_DROP_TIMEOUT 0x3fU 1579 #define V_T6_DROP_TIMEOUT(x) ((x) << S_T6_DROP_TIMEOUT) 1580 #define G_T6_DROP_TIMEOUT(x) (((x) >> S_T6_DROP_TIMEOUT) & M_T6_DROP_TIMEOUT) 1581 1582 #define S_INVONDBSYNC 6 1583 #define V_INVONDBSYNC(x) ((x) << S_INVONDBSYNC) 1584 #define F_INVONDBSYNC V_INVONDBSYNC(1U) 1585 1586 #define S_INVONGTSSYNC 5 1587 #define V_INVONGTSSYNC(x) ((x) << S_INVONGTSSYNC) 1588 #define F_INVONGTSSYNC V_INVONGTSSYNC(1U) 1589 1590 #define S_DB_DBG_EN 4 1591 #define V_DB_DBG_EN(x) ((x) << S_DB_DBG_EN) 1592 #define F_DB_DBG_EN V_DB_DBG_EN(1U) 1593 1594 #define S_GTS_DBG_TIMER_REG 1 1595 #define M_GTS_DBG_TIMER_REG 0x7U 1596 #define V_GTS_DBG_TIMER_REG(x) ((x) << S_GTS_DBG_TIMER_REG) 1597 #define G_GTS_DBG_TIMER_REG(x) (((x) >> S_GTS_DBG_TIMER_REG) & M_GTS_DBG_TIMER_REG) 1598 1599 #define S_GTS_DBG_EN 0 1600 #define V_GTS_DBG_EN(x) ((x) << S_GTS_DBG_EN) 1601 #define F_GTS_DBG_EN V_GTS_DBG_EN(1U) 1602 1603 #define A_SGE_DOORBELL_THROTTLE_CONTROL 0x10b0 1604 1605 #define S_BAR2THROTTLECOUNT 16 1606 #define M_BAR2THROTTLECOUNT 0xffU 1607 #define V_BAR2THROTTLECOUNT(x) ((x) << S_BAR2THROTTLECOUNT) 1608 #define G_BAR2THROTTLECOUNT(x) (((x) >> S_BAR2THROTTLECOUNT) & M_BAR2THROTTLECOUNT) 1609 1610 #define S_CLRCOALESCEDISABLE 15 1611 #define V_CLRCOALESCEDISABLE(x) ((x) << S_CLRCOALESCEDISABLE) 1612 #define F_CLRCOALESCEDISABLE V_CLRCOALESCEDISABLE(1U) 1613 1614 #define S_OPENBAR2GATEONCE 14 1615 #define V_OPENBAR2GATEONCE(x) ((x) << S_OPENBAR2GATEONCE) 1616 #define F_OPENBAR2GATEONCE V_OPENBAR2GATEONCE(1U) 1617 1618 #define S_FORCEOPENBAR2GATE 13 1619 #define V_FORCEOPENBAR2GATE(x) ((x) << S_FORCEOPENBAR2GATE) 1620 #define F_FORCEOPENBAR2GATE V_FORCEOPENBAR2GATE(1U) 1621 1622 #define A_SGE_ITP_CONTROL 0x10b4 1623 1624 #define S_TSCALE 28 1625 #define M_TSCALE 0xfU 1626 #define V_TSCALE(x) ((x) << S_TSCALE) 1627 #define G_TSCALE(x) (((x) >> S_TSCALE) & M_TSCALE) 1628 1629 #define S_CRITICAL_TIME 10 1630 #define M_CRITICAL_TIME 0x7fffU 1631 #define V_CRITICAL_TIME(x) ((x) << S_CRITICAL_TIME) 1632 #define G_CRITICAL_TIME(x) (((x) >> S_CRITICAL_TIME) & M_CRITICAL_TIME) 1633 1634 #define S_LL_EMPTY 4 1635 #define M_LL_EMPTY 0x3fU 1636 #define V_LL_EMPTY(x) ((x) << S_LL_EMPTY) 1637 #define G_LL_EMPTY(x) (((x) >> S_LL_EMPTY) & M_LL_EMPTY) 1638 1639 #define S_LL_READ_WAIT_DISABLE 0 1640 #define V_LL_READ_WAIT_DISABLE(x) ((x) << S_LL_READ_WAIT_DISABLE) 1641 #define F_LL_READ_WAIT_DISABLE V_LL_READ_WAIT_DISABLE(1U) 1642 1643 #define A_SGE_TIMER_VALUE_0_AND_1 0x10b8 1644 1645 #define S_TIMERVALUE0 16 1646 #define M_TIMERVALUE0 0xffffU 1647 #define V_TIMERVALUE0(x) ((x) << S_TIMERVALUE0) 1648 #define G_TIMERVALUE0(x) (((x) >> S_TIMERVALUE0) & M_TIMERVALUE0) 1649 1650 #define S_TIMERVALUE1 0 1651 #define M_TIMERVALUE1 0xffffU 1652 #define V_TIMERVALUE1(x) ((x) << S_TIMERVALUE1) 1653 #define G_TIMERVALUE1(x) (((x) >> S_TIMERVALUE1) & M_TIMERVALUE1) 1654 1655 #define A_SGE_TIMER_VALUE_2_AND_3 0x10bc 1656 1657 #define S_TIMERVALUE2 16 1658 #define M_TIMERVALUE2 0xffffU 1659 #define V_TIMERVALUE2(x) ((x) << S_TIMERVALUE2) 1660 #define G_TIMERVALUE2(x) (((x) >> S_TIMERVALUE2) & M_TIMERVALUE2) 1661 1662 #define S_TIMERVALUE3 0 1663 #define M_TIMERVALUE3 0xffffU 1664 #define V_TIMERVALUE3(x) ((x) << S_TIMERVALUE3) 1665 #define G_TIMERVALUE3(x) (((x) >> S_TIMERVALUE3) & M_TIMERVALUE3) 1666 1667 #define A_SGE_TIMER_VALUE_4_AND_5 0x10c0 1668 1669 #define S_TIMERVALUE4 16 1670 #define M_TIMERVALUE4 0xffffU 1671 #define V_TIMERVALUE4(x) ((x) << S_TIMERVALUE4) 1672 #define G_TIMERVALUE4(x) (((x) >> S_TIMERVALUE4) & M_TIMERVALUE4) 1673 1674 #define S_TIMERVALUE5 0 1675 #define M_TIMERVALUE5 0xffffU 1676 #define V_TIMERVALUE5(x) ((x) << S_TIMERVALUE5) 1677 #define G_TIMERVALUE5(x) (((x) >> S_TIMERVALUE5) & M_TIMERVALUE5) 1678 1679 #define A_SGE_GK_CONTROL 0x10c4 1680 1681 #define S_EN_FLM_FIFTH 29 1682 #define V_EN_FLM_FIFTH(x) ((x) << S_EN_FLM_FIFTH) 1683 #define F_EN_FLM_FIFTH V_EN_FLM_FIFTH(1U) 1684 1685 #define S_FL_PROG_THRESH 20 1686 #define M_FL_PROG_THRESH 0x1ffU 1687 #define V_FL_PROG_THRESH(x) ((x) << S_FL_PROG_THRESH) 1688 #define G_FL_PROG_THRESH(x) (((x) >> S_FL_PROG_THRESH) & M_FL_PROG_THRESH) 1689 1690 #define S_COAL_ALL_THREAD 19 1691 #define V_COAL_ALL_THREAD(x) ((x) << S_COAL_ALL_THREAD) 1692 #define F_COAL_ALL_THREAD V_COAL_ALL_THREAD(1U) 1693 1694 #define S_EN_PSHB 18 1695 #define V_EN_PSHB(x) ((x) << S_EN_PSHB) 1696 #define F_EN_PSHB V_EN_PSHB(1U) 1697 1698 #define S_EN_DB_FIFTH 17 1699 #define V_EN_DB_FIFTH(x) ((x) << S_EN_DB_FIFTH) 1700 #define F_EN_DB_FIFTH V_EN_DB_FIFTH(1U) 1701 1702 #define S_DB_PROG_THRESH 8 1703 #define M_DB_PROG_THRESH 0x1ffU 1704 #define V_DB_PROG_THRESH(x) ((x) << S_DB_PROG_THRESH) 1705 #define G_DB_PROG_THRESH(x) (((x) >> S_DB_PROG_THRESH) & M_DB_PROG_THRESH) 1706 1707 #define S_100NS_TIMER 0 1708 #define M_100NS_TIMER 0xffU 1709 #define V_100NS_TIMER(x) ((x) << S_100NS_TIMER) 1710 #define G_100NS_TIMER(x) (((x) >> S_100NS_TIMER) & M_100NS_TIMER) 1711 1712 #define A_SGE_GK_CONTROL2 0x10c8 1713 1714 #define S_DBQ_TIMER_TICK 16 1715 #define M_DBQ_TIMER_TICK 0xffffU 1716 #define V_DBQ_TIMER_TICK(x) ((x) << S_DBQ_TIMER_TICK) 1717 #define G_DBQ_TIMER_TICK(x) (((x) >> S_DBQ_TIMER_TICK) & M_DBQ_TIMER_TICK) 1718 1719 #define S_FL_MERGE_CNT_THRESH 8 1720 #define M_FL_MERGE_CNT_THRESH 0xfU 1721 #define V_FL_MERGE_CNT_THRESH(x) ((x) << S_FL_MERGE_CNT_THRESH) 1722 #define G_FL_MERGE_CNT_THRESH(x) (((x) >> S_FL_MERGE_CNT_THRESH) & M_FL_MERGE_CNT_THRESH) 1723 1724 #define S_MERGE_CNT_THRESH 0 1725 #define M_MERGE_CNT_THRESH 0x3fU 1726 #define V_MERGE_CNT_THRESH(x) ((x) << S_MERGE_CNT_THRESH) 1727 #define G_MERGE_CNT_THRESH(x) (((x) >> S_MERGE_CNT_THRESH) & M_MERGE_CNT_THRESH) 1728 1729 #define A_SGE_DEBUG_INDEX 0x10cc 1730 #define A_SGE_DEBUG_DATA_HIGH 0x10d0 1731 #define A_SGE_DEBUG_DATA_LOW 0x10d4 1732 #define A_SGE_INT_CAUSE4 0x10dc 1733 1734 #define S_ERR_BAD_UPFL_INC_CREDIT3 8 1735 #define V_ERR_BAD_UPFL_INC_CREDIT3(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT3) 1736 #define F_ERR_BAD_UPFL_INC_CREDIT3 V_ERR_BAD_UPFL_INC_CREDIT3(1U) 1737 1738 #define S_ERR_BAD_UPFL_INC_CREDIT2 7 1739 #define V_ERR_BAD_UPFL_INC_CREDIT2(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT2) 1740 #define F_ERR_BAD_UPFL_INC_CREDIT2 V_ERR_BAD_UPFL_INC_CREDIT2(1U) 1741 1742 #define S_ERR_BAD_UPFL_INC_CREDIT1 6 1743 #define V_ERR_BAD_UPFL_INC_CREDIT1(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT1) 1744 #define F_ERR_BAD_UPFL_INC_CREDIT1 V_ERR_BAD_UPFL_INC_CREDIT1(1U) 1745 1746 #define S_ERR_BAD_UPFL_INC_CREDIT0 5 1747 #define V_ERR_BAD_UPFL_INC_CREDIT0(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT0) 1748 #define F_ERR_BAD_UPFL_INC_CREDIT0 V_ERR_BAD_UPFL_INC_CREDIT0(1U) 1749 1750 #define S_ERR_PHYSADDR_LEN0_IDMA1 4 1751 #define V_ERR_PHYSADDR_LEN0_IDMA1(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA1) 1752 #define F_ERR_PHYSADDR_LEN0_IDMA1 V_ERR_PHYSADDR_LEN0_IDMA1(1U) 1753 1754 #define S_ERR_PHYSADDR_LEN0_IDMA0 3 1755 #define V_ERR_PHYSADDR_LEN0_IDMA0(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA0) 1756 #define F_ERR_PHYSADDR_LEN0_IDMA0 V_ERR_PHYSADDR_LEN0_IDMA0(1U) 1757 1758 #define S_ERR_FLM_INVALID_PKT_DROP1 2 1759 #define V_ERR_FLM_INVALID_PKT_DROP1(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP1) 1760 #define F_ERR_FLM_INVALID_PKT_DROP1 V_ERR_FLM_INVALID_PKT_DROP1(1U) 1761 1762 #define S_ERR_FLM_INVALID_PKT_DROP0 1 1763 #define V_ERR_FLM_INVALID_PKT_DROP0(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP0) 1764 #define F_ERR_FLM_INVALID_PKT_DROP0 V_ERR_FLM_INVALID_PKT_DROP0(1U) 1765 1766 #define S_ERR_UNEXPECTED_TIMER 0 1767 #define V_ERR_UNEXPECTED_TIMER(x) ((x) << S_ERR_UNEXPECTED_TIMER) 1768 #define F_ERR_UNEXPECTED_TIMER V_ERR_UNEXPECTED_TIMER(1U) 1769 1770 #define S_BAR2_EGRESS_LEN_OR_ADDR_ERR 29 1771 #define V_BAR2_EGRESS_LEN_OR_ADDR_ERR(x) ((x) << S_BAR2_EGRESS_LEN_OR_ADDR_ERR) 1772 #define F_BAR2_EGRESS_LEN_OR_ADDR_ERR V_BAR2_EGRESS_LEN_OR_ADDR_ERR(1U) 1773 1774 #define S_ERR_CPL_EXCEED_MAX_IQE_SIZE1 28 1775 #define V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE1) 1776 #define F_ERR_CPL_EXCEED_MAX_IQE_SIZE1 V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(1U) 1777 1778 #define S_ERR_CPL_EXCEED_MAX_IQE_SIZE0 27 1779 #define V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE0) 1780 #define F_ERR_CPL_EXCEED_MAX_IQE_SIZE0 V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(1U) 1781 1782 #define S_ERR_WR_LEN_TOO_LARGE3 26 1783 #define V_ERR_WR_LEN_TOO_LARGE3(x) ((x) << S_ERR_WR_LEN_TOO_LARGE3) 1784 #define F_ERR_WR_LEN_TOO_LARGE3 V_ERR_WR_LEN_TOO_LARGE3(1U) 1785 1786 #define S_ERR_WR_LEN_TOO_LARGE2 25 1787 #define V_ERR_WR_LEN_TOO_LARGE2(x) ((x) << S_ERR_WR_LEN_TOO_LARGE2) 1788 #define F_ERR_WR_LEN_TOO_LARGE2 V_ERR_WR_LEN_TOO_LARGE2(1U) 1789 1790 #define S_ERR_WR_LEN_TOO_LARGE1 24 1791 #define V_ERR_WR_LEN_TOO_LARGE1(x) ((x) << S_ERR_WR_LEN_TOO_LARGE1) 1792 #define F_ERR_WR_LEN_TOO_LARGE1 V_ERR_WR_LEN_TOO_LARGE1(1U) 1793 1794 #define S_ERR_WR_LEN_TOO_LARGE0 23 1795 #define V_ERR_WR_LEN_TOO_LARGE0(x) ((x) << S_ERR_WR_LEN_TOO_LARGE0) 1796 #define F_ERR_WR_LEN_TOO_LARGE0 V_ERR_WR_LEN_TOO_LARGE0(1U) 1797 1798 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL3 22 1799 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL3) 1800 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL3 V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(1U) 1801 1802 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL2 21 1803 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL2) 1804 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL2 V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(1U) 1805 1806 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL1 20 1807 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL1) 1808 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL1 V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(1U) 1809 1810 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL0 19 1811 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL0) 1812 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL0 V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(1U) 1813 1814 #define S_COAL_WITH_HP_DISABLE_ERR 18 1815 #define V_COAL_WITH_HP_DISABLE_ERR(x) ((x) << S_COAL_WITH_HP_DISABLE_ERR) 1816 #define F_COAL_WITH_HP_DISABLE_ERR V_COAL_WITH_HP_DISABLE_ERR(1U) 1817 1818 #define S_BAR2_EGRESS_COAL0_ERR 17 1819 #define V_BAR2_EGRESS_COAL0_ERR(x) ((x) << S_BAR2_EGRESS_COAL0_ERR) 1820 #define F_BAR2_EGRESS_COAL0_ERR V_BAR2_EGRESS_COAL0_ERR(1U) 1821 1822 #define S_BAR2_EGRESS_SIZE_ERR 16 1823 #define V_BAR2_EGRESS_SIZE_ERR(x) ((x) << S_BAR2_EGRESS_SIZE_ERR) 1824 #define F_BAR2_EGRESS_SIZE_ERR V_BAR2_EGRESS_SIZE_ERR(1U) 1825 1826 #define S_FLM_PC_RSP_ERR 15 1827 #define V_FLM_PC_RSP_ERR(x) ((x) << S_FLM_PC_RSP_ERR) 1828 #define F_FLM_PC_RSP_ERR V_FLM_PC_RSP_ERR(1U) 1829 1830 #define S_DBFIFO_HP_INT_LOW 14 1831 #define V_DBFIFO_HP_INT_LOW(x) ((x) << S_DBFIFO_HP_INT_LOW) 1832 #define F_DBFIFO_HP_INT_LOW V_DBFIFO_HP_INT_LOW(1U) 1833 1834 #define S_DBFIFO_LP_INT_LOW 13 1835 #define V_DBFIFO_LP_INT_LOW(x) ((x) << S_DBFIFO_LP_INT_LOW) 1836 #define F_DBFIFO_LP_INT_LOW V_DBFIFO_LP_INT_LOW(1U) 1837 1838 #define S_DBFIFO_FL_INT_LOW 12 1839 #define V_DBFIFO_FL_INT_LOW(x) ((x) << S_DBFIFO_FL_INT_LOW) 1840 #define F_DBFIFO_FL_INT_LOW V_DBFIFO_FL_INT_LOW(1U) 1841 1842 #define S_DBFIFO_FL_INT 11 1843 #define V_DBFIFO_FL_INT(x) ((x) << S_DBFIFO_FL_INT) 1844 #define F_DBFIFO_FL_INT V_DBFIFO_FL_INT(1U) 1845 1846 #define S_ERR_RX_CPL_PACKET_SIZE1 10 1847 #define V_ERR_RX_CPL_PACKET_SIZE1(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE1) 1848 #define F_ERR_RX_CPL_PACKET_SIZE1 V_ERR_RX_CPL_PACKET_SIZE1(1U) 1849 1850 #define S_ERR_RX_CPL_PACKET_SIZE0 9 1851 #define V_ERR_RX_CPL_PACKET_SIZE0(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE0) 1852 #define F_ERR_RX_CPL_PACKET_SIZE0 V_ERR_RX_CPL_PACKET_SIZE0(1U) 1853 1854 #define S_ERR_ISHIFT_UR1 31 1855 #define V_ERR_ISHIFT_UR1(x) ((x) << S_ERR_ISHIFT_UR1) 1856 #define F_ERR_ISHIFT_UR1 V_ERR_ISHIFT_UR1(1U) 1857 1858 #define S_ERR_ISHIFT_UR0 30 1859 #define V_ERR_ISHIFT_UR0(x) ((x) << S_ERR_ISHIFT_UR0) 1860 #define F_ERR_ISHIFT_UR0 V_ERR_ISHIFT_UR0(1U) 1861 1862 #define S_ERR_TH3_MAX_FETCH 14 1863 #define V_ERR_TH3_MAX_FETCH(x) ((x) << S_ERR_TH3_MAX_FETCH) 1864 #define F_ERR_TH3_MAX_FETCH V_ERR_TH3_MAX_FETCH(1U) 1865 1866 #define S_ERR_TH2_MAX_FETCH 13 1867 #define V_ERR_TH2_MAX_FETCH(x) ((x) << S_ERR_TH2_MAX_FETCH) 1868 #define F_ERR_TH2_MAX_FETCH V_ERR_TH2_MAX_FETCH(1U) 1869 1870 #define S_ERR_TH1_MAX_FETCH 12 1871 #define V_ERR_TH1_MAX_FETCH(x) ((x) << S_ERR_TH1_MAX_FETCH) 1872 #define F_ERR_TH1_MAX_FETCH V_ERR_TH1_MAX_FETCH(1U) 1873 1874 #define S_ERR_TH0_MAX_FETCH 11 1875 #define V_ERR_TH0_MAX_FETCH(x) ((x) << S_ERR_TH0_MAX_FETCH) 1876 #define F_ERR_TH0_MAX_FETCH V_ERR_TH0_MAX_FETCH(1U) 1877 1878 #define A_SGE_INT_ENABLE4 0x10e0 1879 #define A_SGE_STAT_TOTAL 0x10e4 1880 #define A_SGE_STAT_MATCH 0x10e8 1881 #define A_SGE_STAT_CFG 0x10ec 1882 1883 #define S_STATMODE 2 1884 #define M_STATMODE 0x3U 1885 #define V_STATMODE(x) ((x) << S_STATMODE) 1886 #define G_STATMODE(x) (((x) >> S_STATMODE) & M_STATMODE) 1887 1888 #define S_STATSOURCE 0 1889 #define M_STATSOURCE 0x3U 1890 #define V_STATSOURCE(x) ((x) << S_STATSOURCE) 1891 #define G_STATSOURCE(x) (((x) >> S_STATSOURCE) & M_STATSOURCE) 1892 1893 #define S_STATSOURCE_T5 9 1894 #define M_STATSOURCE_T5 0xfU 1895 #define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5) 1896 #define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5) 1897 1898 #define S_ITPOPMODE 8 1899 #define V_ITPOPMODE(x) ((x) << S_ITPOPMODE) 1900 #define F_ITPOPMODE V_ITPOPMODE(1U) 1901 1902 #define S_EGRCTXTOPMODE 6 1903 #define M_EGRCTXTOPMODE 0x3U 1904 #define V_EGRCTXTOPMODE(x) ((x) << S_EGRCTXTOPMODE) 1905 #define G_EGRCTXTOPMODE(x) (((x) >> S_EGRCTXTOPMODE) & M_EGRCTXTOPMODE) 1906 1907 #define S_INGCTXTOPMODE 4 1908 #define M_INGCTXTOPMODE 0x3U 1909 #define V_INGCTXTOPMODE(x) ((x) << S_INGCTXTOPMODE) 1910 #define G_INGCTXTOPMODE(x) (((x) >> S_INGCTXTOPMODE) & M_INGCTXTOPMODE) 1911 1912 #define S_T6_STATMODE 0 1913 #define M_T6_STATMODE 0xfU 1914 #define V_T6_STATMODE(x) ((x) << S_T6_STATMODE) 1915 #define G_T6_STATMODE(x) (((x) >> S_T6_STATMODE) & M_T6_STATMODE) 1916 1917 #define A_SGE_HINT_CFG 0x10f0 1918 1919 #define S_UPCUTOFFTHRESHLP 12 1920 #define M_UPCUTOFFTHRESHLP 0x7ffU 1921 #define V_UPCUTOFFTHRESHLP(x) ((x) << S_UPCUTOFFTHRESHLP) 1922 #define G_UPCUTOFFTHRESHLP(x) (((x) >> S_UPCUTOFFTHRESHLP) & M_UPCUTOFFTHRESHLP) 1923 1924 #define S_HINTSALLOWEDNOHDR 6 1925 #define M_HINTSALLOWEDNOHDR 0x3fU 1926 #define V_HINTSALLOWEDNOHDR(x) ((x) << S_HINTSALLOWEDNOHDR) 1927 #define G_HINTSALLOWEDNOHDR(x) (((x) >> S_HINTSALLOWEDNOHDR) & M_HINTSALLOWEDNOHDR) 1928 1929 #define S_HINTSALLOWEDHDR 0 1930 #define M_HINTSALLOWEDHDR 0x3fU 1931 #define V_HINTSALLOWEDHDR(x) ((x) << S_HINTSALLOWEDHDR) 1932 #define G_HINTSALLOWEDHDR(x) (((x) >> S_HINTSALLOWEDHDR) & M_HINTSALLOWEDHDR) 1933 1934 #define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4 1935 #define A_SGE_INGRESS_QUEUES_PER_PAGE_VF 0x10f8 1936 #define A_SGE_ERROR_STATS 0x1100 1937 1938 #define S_UNCAPTURED_ERROR 18 1939 #define V_UNCAPTURED_ERROR(x) ((x) << S_UNCAPTURED_ERROR) 1940 #define F_UNCAPTURED_ERROR V_UNCAPTURED_ERROR(1U) 1941 1942 #define S_ERROR_QID_VALID 17 1943 #define V_ERROR_QID_VALID(x) ((x) << S_ERROR_QID_VALID) 1944 #define F_ERROR_QID_VALID V_ERROR_QID_VALID(1U) 1945 1946 #define S_ERROR_QID 0 1947 #define M_ERROR_QID 0x1ffffU 1948 #define V_ERROR_QID(x) ((x) << S_ERROR_QID) 1949 #define G_ERROR_QID(x) (((x) >> S_ERROR_QID) & M_ERROR_QID) 1950 1951 #define S_CAUSE_REGISTER 24 1952 #define M_CAUSE_REGISTER 0x7U 1953 #define V_CAUSE_REGISTER(x) ((x) << S_CAUSE_REGISTER) 1954 #define G_CAUSE_REGISTER(x) (((x) >> S_CAUSE_REGISTER) & M_CAUSE_REGISTER) 1955 1956 #define S_CAUSE_BIT 19 1957 #define M_CAUSE_BIT 0x1fU 1958 #define V_CAUSE_BIT(x) ((x) << S_CAUSE_BIT) 1959 #define G_CAUSE_BIT(x) (((x) >> S_CAUSE_BIT) & M_CAUSE_BIT) 1960 1961 #define A_SGE_IDMA0_DROP_CNT 0x1104 1962 #define A_SGE_IDMA1_DROP_CNT 0x1108 1963 #define A_SGE_INT_CAUSE5 0x110c 1964 1965 #define S_ERR_T_RXCRC 31 1966 #define V_ERR_T_RXCRC(x) ((x) << S_ERR_T_RXCRC) 1967 #define F_ERR_T_RXCRC V_ERR_T_RXCRC(1U) 1968 1969 #define S_PERR_MC_RSPDATA 30 1970 #define V_PERR_MC_RSPDATA(x) ((x) << S_PERR_MC_RSPDATA) 1971 #define F_PERR_MC_RSPDATA V_PERR_MC_RSPDATA(1U) 1972 1973 #define S_PERR_PC_RSPDATA 29 1974 #define V_PERR_PC_RSPDATA(x) ((x) << S_PERR_PC_RSPDATA) 1975 #define F_PERR_PC_RSPDATA V_PERR_PC_RSPDATA(1U) 1976 1977 #define S_PERR_PD_RDRSPDATA 28 1978 #define V_PERR_PD_RDRSPDATA(x) ((x) << S_PERR_PD_RDRSPDATA) 1979 #define F_PERR_PD_RDRSPDATA V_PERR_PD_RDRSPDATA(1U) 1980 1981 #define S_PERR_U_RXDATA 27 1982 #define V_PERR_U_RXDATA(x) ((x) << S_PERR_U_RXDATA) 1983 #define F_PERR_U_RXDATA V_PERR_U_RXDATA(1U) 1984 1985 #define S_PERR_UD_RXDATA 26 1986 #define V_PERR_UD_RXDATA(x) ((x) << S_PERR_UD_RXDATA) 1987 #define F_PERR_UD_RXDATA V_PERR_UD_RXDATA(1U) 1988 1989 #define S_PERR_UP_DATA 25 1990 #define V_PERR_UP_DATA(x) ((x) << S_PERR_UP_DATA) 1991 #define F_PERR_UP_DATA V_PERR_UP_DATA(1U) 1992 1993 #define S_PERR_CIM2SGE_RXDATA 24 1994 #define V_PERR_CIM2SGE_RXDATA(x) ((x) << S_PERR_CIM2SGE_RXDATA) 1995 #define F_PERR_CIM2SGE_RXDATA V_PERR_CIM2SGE_RXDATA(1U) 1996 1997 #define S_PERR_HINT_DELAY_FIFO1_T5 23 1998 #define V_PERR_HINT_DELAY_FIFO1_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO1_T5) 1999 #define F_PERR_HINT_DELAY_FIFO1_T5 V_PERR_HINT_DELAY_FIFO1_T5(1U) 2000 2001 #define S_PERR_HINT_DELAY_FIFO0_T5 22 2002 #define V_PERR_HINT_DELAY_FIFO0_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO0_T5) 2003 #define F_PERR_HINT_DELAY_FIFO0_T5 V_PERR_HINT_DELAY_FIFO0_T5(1U) 2004 2005 #define S_PERR_IMSG_PD_FIFO_T5 21 2006 #define V_PERR_IMSG_PD_FIFO_T5(x) ((x) << S_PERR_IMSG_PD_FIFO_T5) 2007 #define F_PERR_IMSG_PD_FIFO_T5 V_PERR_IMSG_PD_FIFO_T5(1U) 2008 2009 #define S_PERR_ULPTX_FIFO1_T5 20 2010 #define V_PERR_ULPTX_FIFO1_T5(x) ((x) << S_PERR_ULPTX_FIFO1_T5) 2011 #define F_PERR_ULPTX_FIFO1_T5 V_PERR_ULPTX_FIFO1_T5(1U) 2012 2013 #define S_PERR_ULPTX_FIFO0_T5 19 2014 #define V_PERR_ULPTX_FIFO0_T5(x) ((x) << S_PERR_ULPTX_FIFO0_T5) 2015 #define F_PERR_ULPTX_FIFO0_T5 V_PERR_ULPTX_FIFO0_T5(1U) 2016 2017 #define S_PERR_IDMA2IMSG_FIFO1_T5 18 2018 #define V_PERR_IDMA2IMSG_FIFO1_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO1_T5) 2019 #define F_PERR_IDMA2IMSG_FIFO1_T5 V_PERR_IDMA2IMSG_FIFO1_T5(1U) 2020 2021 #define S_PERR_IDMA2IMSG_FIFO0_T5 17 2022 #define V_PERR_IDMA2IMSG_FIFO0_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO0_T5) 2023 #define F_PERR_IDMA2IMSG_FIFO0_T5 V_PERR_IDMA2IMSG_FIFO0_T5(1U) 2024 2025 #define S_PERR_POINTER_DATA_FIFO0 16 2026 #define V_PERR_POINTER_DATA_FIFO0(x) ((x) << S_PERR_POINTER_DATA_FIFO0) 2027 #define F_PERR_POINTER_DATA_FIFO0 V_PERR_POINTER_DATA_FIFO0(1U) 2028 2029 #define S_PERR_POINTER_DATA_FIFO1 15 2030 #define V_PERR_POINTER_DATA_FIFO1(x) ((x) << S_PERR_POINTER_DATA_FIFO1) 2031 #define F_PERR_POINTER_DATA_FIFO1 V_PERR_POINTER_DATA_FIFO1(1U) 2032 2033 #define S_PERR_POINTER_HDR_FIFO0 14 2034 #define V_PERR_POINTER_HDR_FIFO0(x) ((x) << S_PERR_POINTER_HDR_FIFO0) 2035 #define F_PERR_POINTER_HDR_FIFO0 V_PERR_POINTER_HDR_FIFO0(1U) 2036 2037 #define S_PERR_POINTER_HDR_FIFO1 13 2038 #define V_PERR_POINTER_HDR_FIFO1(x) ((x) << S_PERR_POINTER_HDR_FIFO1) 2039 #define F_PERR_POINTER_HDR_FIFO1 V_PERR_POINTER_HDR_FIFO1(1U) 2040 2041 #define S_PERR_PAYLOAD_FIFO0 12 2042 #define V_PERR_PAYLOAD_FIFO0(x) ((x) << S_PERR_PAYLOAD_FIFO0) 2043 #define F_PERR_PAYLOAD_FIFO0 V_PERR_PAYLOAD_FIFO0(1U) 2044 2045 #define S_PERR_PAYLOAD_FIFO1 11 2046 #define V_PERR_PAYLOAD_FIFO1(x) ((x) << S_PERR_PAYLOAD_FIFO1) 2047 #define F_PERR_PAYLOAD_FIFO1 V_PERR_PAYLOAD_FIFO1(1U) 2048 2049 #define S_PERR_EDMA_INPUT_FIFO3 10 2050 #define V_PERR_EDMA_INPUT_FIFO3(x) ((x) << S_PERR_EDMA_INPUT_FIFO3) 2051 #define F_PERR_EDMA_INPUT_FIFO3 V_PERR_EDMA_INPUT_FIFO3(1U) 2052 2053 #define S_PERR_EDMA_INPUT_FIFO2 9 2054 #define V_PERR_EDMA_INPUT_FIFO2(x) ((x) << S_PERR_EDMA_INPUT_FIFO2) 2055 #define F_PERR_EDMA_INPUT_FIFO2 V_PERR_EDMA_INPUT_FIFO2(1U) 2056 2057 #define S_PERR_EDMA_INPUT_FIFO1 8 2058 #define V_PERR_EDMA_INPUT_FIFO1(x) ((x) << S_PERR_EDMA_INPUT_FIFO1) 2059 #define F_PERR_EDMA_INPUT_FIFO1 V_PERR_EDMA_INPUT_FIFO1(1U) 2060 2061 #define S_PERR_EDMA_INPUT_FIFO0 7 2062 #define V_PERR_EDMA_INPUT_FIFO0(x) ((x) << S_PERR_EDMA_INPUT_FIFO0) 2063 #define F_PERR_EDMA_INPUT_FIFO0 V_PERR_EDMA_INPUT_FIFO0(1U) 2064 2065 #define S_PERR_MGT_BAR2_FIFO 6 2066 #define V_PERR_MGT_BAR2_FIFO(x) ((x) << S_PERR_MGT_BAR2_FIFO) 2067 #define F_PERR_MGT_BAR2_FIFO V_PERR_MGT_BAR2_FIFO(1U) 2068 2069 #define S_PERR_HEADERSPLIT_FIFO1_T5 5 2070 #define V_PERR_HEADERSPLIT_FIFO1_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO1_T5) 2071 #define F_PERR_HEADERSPLIT_FIFO1_T5 V_PERR_HEADERSPLIT_FIFO1_T5(1U) 2072 2073 #define S_PERR_HEADERSPLIT_FIFO0_T5 4 2074 #define V_PERR_HEADERSPLIT_FIFO0_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO0_T5) 2075 #define F_PERR_HEADERSPLIT_FIFO0_T5 V_PERR_HEADERSPLIT_FIFO0_T5(1U) 2076 2077 #define S_PERR_CIM_FIFO1 3 2078 #define V_PERR_CIM_FIFO1(x) ((x) << S_PERR_CIM_FIFO1) 2079 #define F_PERR_CIM_FIFO1 V_PERR_CIM_FIFO1(1U) 2080 2081 #define S_PERR_CIM_FIFO0 2 2082 #define V_PERR_CIM_FIFO0(x) ((x) << S_PERR_CIM_FIFO0) 2083 #define F_PERR_CIM_FIFO0 V_PERR_CIM_FIFO0(1U) 2084 2085 #define S_PERR_IDMA_SWITCH_OUTPUT_FIFO1 1 2086 #define V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO1) 2087 #define F_PERR_IDMA_SWITCH_OUTPUT_FIFO1 V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(1U) 2088 2089 #define S_PERR_IDMA_SWITCH_OUTPUT_FIFO0 0 2090 #define V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO0) 2091 #define F_PERR_IDMA_SWITCH_OUTPUT_FIFO0 V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(1U) 2092 2093 #define A_SGE_INT_ENABLE5 0x1110 2094 #define A_SGE_PERR_ENABLE5 0x1114 2095 #define A_SGE_DBFIFO_STATUS2 0x1118 2096 2097 #define S_FL_INT_THRESH 24 2098 #define M_FL_INT_THRESH 0xfU 2099 #define V_FL_INT_THRESH(x) ((x) << S_FL_INT_THRESH) 2100 #define G_FL_INT_THRESH(x) (((x) >> S_FL_INT_THRESH) & M_FL_INT_THRESH) 2101 2102 #define S_FL_COUNT 14 2103 #define M_FL_COUNT 0x3ffU 2104 #define V_FL_COUNT(x) ((x) << S_FL_COUNT) 2105 #define G_FL_COUNT(x) (((x) >> S_FL_COUNT) & M_FL_COUNT) 2106 2107 #define S_HP_INT_THRESH_T5 10 2108 #define M_HP_INT_THRESH_T5 0xfU 2109 #define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5) 2110 #define G_HP_INT_THRESH_T5(x) (((x) >> S_HP_INT_THRESH_T5) & M_HP_INT_THRESH_T5) 2111 2112 #define S_HP_COUNT_T5 0 2113 #define M_HP_COUNT_T5 0x3ffU 2114 #define V_HP_COUNT_T5(x) ((x) << S_HP_COUNT_T5) 2115 #define G_HP_COUNT_T5(x) (((x) >> S_HP_COUNT_T5) & M_HP_COUNT_T5) 2116 2117 #define A_SGE_FETCH_BURST_MAX_0_AND_1 0x111c 2118 2119 #define S_FETCHBURSTMAX0 16 2120 #define M_FETCHBURSTMAX0 0x3ffU 2121 #define V_FETCHBURSTMAX0(x) ((x) << S_FETCHBURSTMAX0) 2122 #define G_FETCHBURSTMAX0(x) (((x) >> S_FETCHBURSTMAX0) & M_FETCHBURSTMAX0) 2123 2124 #define S_FETCHBURSTMAX1 0 2125 #define M_FETCHBURSTMAX1 0x3ffU 2126 #define V_FETCHBURSTMAX1(x) ((x) << S_FETCHBURSTMAX1) 2127 #define G_FETCHBURSTMAX1(x) (((x) >> S_FETCHBURSTMAX1) & M_FETCHBURSTMAX1) 2128 2129 #define A_SGE_FETCH_BURST_MAX_2_AND_3 0x1120 2130 2131 #define S_FETCHBURSTMAX2 16 2132 #define M_FETCHBURSTMAX2 0x3ffU 2133 #define V_FETCHBURSTMAX2(x) ((x) << S_FETCHBURSTMAX2) 2134 #define G_FETCHBURSTMAX2(x) (((x) >> S_FETCHBURSTMAX2) & M_FETCHBURSTMAX2) 2135 2136 #define S_FETCHBURSTMAX3 0 2137 #define M_FETCHBURSTMAX3 0x3ffU 2138 #define V_FETCHBURSTMAX3(x) ((x) << S_FETCHBURSTMAX3) 2139 #define G_FETCHBURSTMAX3(x) (((x) >> S_FETCHBURSTMAX3) & M_FETCHBURSTMAX3) 2140 2141 #define A_SGE_CONTROL2 0x1124 2142 2143 #define S_INGPACKBOUNDARY 16 2144 #define M_INGPACKBOUNDARY 0x7U 2145 #define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY) 2146 #define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY) 2147 2148 #define S_VFIFO_ENABLE 10 2149 #define V_VFIFO_ENABLE(x) ((x) << S_VFIFO_ENABLE) 2150 #define F_VFIFO_ENABLE V_VFIFO_ENABLE(1U) 2151 2152 #define S_FLM_RESCHEDULE_MODE 9 2153 #define V_FLM_RESCHEDULE_MODE(x) ((x) << S_FLM_RESCHEDULE_MODE) 2154 #define F_FLM_RESCHEDULE_MODE V_FLM_RESCHEDULE_MODE(1U) 2155 2156 #define S_HINTDEPTHCTLFL 4 2157 #define M_HINTDEPTHCTLFL 0x1fU 2158 #define V_HINTDEPTHCTLFL(x) ((x) << S_HINTDEPTHCTLFL) 2159 #define G_HINTDEPTHCTLFL(x) (((x) >> S_HINTDEPTHCTLFL) & M_HINTDEPTHCTLFL) 2160 2161 #define S_FORCE_ORDERING 3 2162 #define V_FORCE_ORDERING(x) ((x) << S_FORCE_ORDERING) 2163 #define F_FORCE_ORDERING V_FORCE_ORDERING(1U) 2164 2165 #define S_TX_COALESCE_SIZE 2 2166 #define V_TX_COALESCE_SIZE(x) ((x) << S_TX_COALESCE_SIZE) 2167 #define F_TX_COALESCE_SIZE V_TX_COALESCE_SIZE(1U) 2168 2169 #define S_COAL_STRICT_CIM_PRI 1 2170 #define V_COAL_STRICT_CIM_PRI(x) ((x) << S_COAL_STRICT_CIM_PRI) 2171 #define F_COAL_STRICT_CIM_PRI V_COAL_STRICT_CIM_PRI(1U) 2172 2173 #define S_TX_COALESCE_PRI 0 2174 #define V_TX_COALESCE_PRI(x) ((x) << S_TX_COALESCE_PRI) 2175 #define F_TX_COALESCE_PRI V_TX_COALESCE_PRI(1U) 2176 2177 #define S_UPFLCUTOFFDIS 21 2178 #define V_UPFLCUTOFFDIS(x) ((x) << S_UPFLCUTOFFDIS) 2179 #define F_UPFLCUTOFFDIS V_UPFLCUTOFFDIS(1U) 2180 2181 #define S_RXCPLSIZEAUTOCORRECT 20 2182 #define V_RXCPLSIZEAUTOCORRECT(x) ((x) << S_RXCPLSIZEAUTOCORRECT) 2183 #define F_RXCPLSIZEAUTOCORRECT V_RXCPLSIZEAUTOCORRECT(1U) 2184 2185 #define S_IDMAARBROUNDROBIN 19 2186 #define V_IDMAARBROUNDROBIN(x) ((x) << S_IDMAARBROUNDROBIN) 2187 #define F_IDMAARBROUNDROBIN V_IDMAARBROUNDROBIN(1U) 2188 2189 #define S_CGEN_EGRESS_CONTEXT 15 2190 #define V_CGEN_EGRESS_CONTEXT(x) ((x) << S_CGEN_EGRESS_CONTEXT) 2191 #define F_CGEN_EGRESS_CONTEXT V_CGEN_EGRESS_CONTEXT(1U) 2192 2193 #define S_CGEN_INGRESS_CONTEXT 14 2194 #define V_CGEN_INGRESS_CONTEXT(x) ((x) << S_CGEN_INGRESS_CONTEXT) 2195 #define F_CGEN_INGRESS_CONTEXT V_CGEN_INGRESS_CONTEXT(1U) 2196 2197 #define S_CGEN_IDMA 13 2198 #define V_CGEN_IDMA(x) ((x) << S_CGEN_IDMA) 2199 #define F_CGEN_IDMA V_CGEN_IDMA(1U) 2200 2201 #define S_CGEN_DBP 12 2202 #define V_CGEN_DBP(x) ((x) << S_CGEN_DBP) 2203 #define F_CGEN_DBP V_CGEN_DBP(1U) 2204 2205 #define S_CGEN_EDMA 11 2206 #define V_CGEN_EDMA(x) ((x) << S_CGEN_EDMA) 2207 #define F_CGEN_EDMA V_CGEN_EDMA(1U) 2208 2209 #define A_SGE_INT_CAUSE6 0x1128 2210 2211 #define S_ERR_DB_SYNC 21 2212 #define V_ERR_DB_SYNC(x) ((x) << S_ERR_DB_SYNC) 2213 #define F_ERR_DB_SYNC V_ERR_DB_SYNC(1U) 2214 2215 #define S_ERR_GTS_SYNC 20 2216 #define V_ERR_GTS_SYNC(x) ((x) << S_ERR_GTS_SYNC) 2217 #define F_ERR_GTS_SYNC V_ERR_GTS_SYNC(1U) 2218 2219 #define S_FATAL_LARGE_COAL 19 2220 #define V_FATAL_LARGE_COAL(x) ((x) << S_FATAL_LARGE_COAL) 2221 #define F_FATAL_LARGE_COAL V_FATAL_LARGE_COAL(1U) 2222 2223 #define S_PL_BAR2_FRM_ERR 18 2224 #define V_PL_BAR2_FRM_ERR(x) ((x) << S_PL_BAR2_FRM_ERR) 2225 #define F_PL_BAR2_FRM_ERR V_PL_BAR2_FRM_ERR(1U) 2226 2227 #define S_SILENT_DROP_TX_COAL 17 2228 #define V_SILENT_DROP_TX_COAL(x) ((x) << S_SILENT_DROP_TX_COAL) 2229 #define F_SILENT_DROP_TX_COAL V_SILENT_DROP_TX_COAL(1U) 2230 2231 #define S_ERR_INV_CTXT4 16 2232 #define V_ERR_INV_CTXT4(x) ((x) << S_ERR_INV_CTXT4) 2233 #define F_ERR_INV_CTXT4 V_ERR_INV_CTXT4(1U) 2234 2235 #define S_ERR_BAD_DB_PIDX4 15 2236 #define V_ERR_BAD_DB_PIDX4(x) ((x) << S_ERR_BAD_DB_PIDX4) 2237 #define F_ERR_BAD_DB_PIDX4 V_ERR_BAD_DB_PIDX4(1U) 2238 2239 #define S_ERR_BAD_UPFL_INC_CREDIT4 14 2240 #define V_ERR_BAD_UPFL_INC_CREDIT4(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT4) 2241 #define F_ERR_BAD_UPFL_INC_CREDIT4 V_ERR_BAD_UPFL_INC_CREDIT4(1U) 2242 2243 #define S_ERR_PC_RSP_LEN3 11 2244 #define V_ERR_PC_RSP_LEN3(x) ((x) << S_ERR_PC_RSP_LEN3) 2245 #define F_ERR_PC_RSP_LEN3 V_ERR_PC_RSP_LEN3(1U) 2246 2247 #define S_ERR_PC_RSP_LEN2 10 2248 #define V_ERR_PC_RSP_LEN2(x) ((x) << S_ERR_PC_RSP_LEN2) 2249 #define F_ERR_PC_RSP_LEN2 V_ERR_PC_RSP_LEN2(1U) 2250 2251 #define S_ERR_PC_RSP_LEN1 9 2252 #define V_ERR_PC_RSP_LEN1(x) ((x) << S_ERR_PC_RSP_LEN1) 2253 #define F_ERR_PC_RSP_LEN1 V_ERR_PC_RSP_LEN1(1U) 2254 2255 #define S_ERR_PC_RSP_LEN0 8 2256 #define V_ERR_PC_RSP_LEN0(x) ((x) << S_ERR_PC_RSP_LEN0) 2257 #define F_ERR_PC_RSP_LEN0 V_ERR_PC_RSP_LEN0(1U) 2258 2259 #define S_FATAL_ENQ2LL_VLD 7 2260 #define V_FATAL_ENQ2LL_VLD(x) ((x) << S_FATAL_ENQ2LL_VLD) 2261 #define F_FATAL_ENQ2LL_VLD V_FATAL_ENQ2LL_VLD(1U) 2262 2263 #define S_FATAL_LL_EMPTY 6 2264 #define V_FATAL_LL_EMPTY(x) ((x) << S_FATAL_LL_EMPTY) 2265 #define F_FATAL_LL_EMPTY V_FATAL_LL_EMPTY(1U) 2266 2267 #define S_FATAL_OFF_WDENQ 5 2268 #define V_FATAL_OFF_WDENQ(x) ((x) << S_FATAL_OFF_WDENQ) 2269 #define F_FATAL_OFF_WDENQ V_FATAL_OFF_WDENQ(1U) 2270 2271 #define S_FATAL_DEQ_DRDY 3 2272 #define M_FATAL_DEQ_DRDY 0x3U 2273 #define V_FATAL_DEQ_DRDY(x) ((x) << S_FATAL_DEQ_DRDY) 2274 #define G_FATAL_DEQ_DRDY(x) (((x) >> S_FATAL_DEQ_DRDY) & M_FATAL_DEQ_DRDY) 2275 2276 #define S_FATAL_OUTP_DRDY 1 2277 #define M_FATAL_OUTP_DRDY 0x3U 2278 #define V_FATAL_OUTP_DRDY(x) ((x) << S_FATAL_OUTP_DRDY) 2279 #define G_FATAL_OUTP_DRDY(x) (((x) >> S_FATAL_OUTP_DRDY) & M_FATAL_OUTP_DRDY) 2280 2281 #define S_FATAL_DEQ 0 2282 #define V_FATAL_DEQ(x) ((x) << S_FATAL_DEQ) 2283 #define F_FATAL_DEQ V_FATAL_DEQ(1U) 2284 2285 #define A_SGE_INT_ENABLE6 0x112c 2286 2287 #define S_FATAL_TAG_MISMATCH 13 2288 #define V_FATAL_TAG_MISMATCH(x) ((x) << S_FATAL_TAG_MISMATCH) 2289 #define F_FATAL_TAG_MISMATCH V_FATAL_TAG_MISMATCH(1U) 2290 2291 #define S_FATAL_ENQ_CTL_RDY 12 2292 #define V_FATAL_ENQ_CTL_RDY(x) ((x) << S_FATAL_ENQ_CTL_RDY) 2293 #define F_FATAL_ENQ_CTL_RDY V_FATAL_ENQ_CTL_RDY(1U) 2294 2295 #define A_SGE_DBVFIFO_BADDR 0x1138 2296 #define A_SGE_DBVFIFO_SIZE 0x113c 2297 2298 #define S_DBVFIFO_SIZE 6 2299 #define M_DBVFIFO_SIZE 0xfffU 2300 #define V_DBVFIFO_SIZE(x) ((x) << S_DBVFIFO_SIZE) 2301 #define G_DBVFIFO_SIZE(x) (((x) >> S_DBVFIFO_SIZE) & M_DBVFIFO_SIZE) 2302 2303 #define S_T6_DBVFIFO_SIZE 0 2304 #define M_T6_DBVFIFO_SIZE 0x1fffU 2305 #define V_T6_DBVFIFO_SIZE(x) ((x) << S_T6_DBVFIFO_SIZE) 2306 #define G_T6_DBVFIFO_SIZE(x) (((x) >> S_T6_DBVFIFO_SIZE) & M_T6_DBVFIFO_SIZE) 2307 2308 #define A_SGE_DBFIFO_STATUS3 0x1140 2309 2310 #define S_LP_PTRS_EQUAL 21 2311 #define V_LP_PTRS_EQUAL(x) ((x) << S_LP_PTRS_EQUAL) 2312 #define F_LP_PTRS_EQUAL V_LP_PTRS_EQUAL(1U) 2313 2314 #define S_LP_SNAPHOT 20 2315 #define V_LP_SNAPHOT(x) ((x) << S_LP_SNAPHOT) 2316 #define F_LP_SNAPHOT V_LP_SNAPHOT(1U) 2317 2318 #define S_FL_INT_THRESH_LOW 16 2319 #define M_FL_INT_THRESH_LOW 0xfU 2320 #define V_FL_INT_THRESH_LOW(x) ((x) << S_FL_INT_THRESH_LOW) 2321 #define G_FL_INT_THRESH_LOW(x) (((x) >> S_FL_INT_THRESH_LOW) & M_FL_INT_THRESH_LOW) 2322 2323 #define S_HP_INT_THRESH_LOW 12 2324 #define M_HP_INT_THRESH_LOW 0xfU 2325 #define V_HP_INT_THRESH_LOW(x) ((x) << S_HP_INT_THRESH_LOW) 2326 #define G_HP_INT_THRESH_LOW(x) (((x) >> S_HP_INT_THRESH_LOW) & M_HP_INT_THRESH_LOW) 2327 2328 #define S_LP_INT_THRESH_LOW 0 2329 #define M_LP_INT_THRESH_LOW 0xfffU 2330 #define V_LP_INT_THRESH_LOW(x) ((x) << S_LP_INT_THRESH_LOW) 2331 #define G_LP_INT_THRESH_LOW(x) (((x) >> S_LP_INT_THRESH_LOW) & M_LP_INT_THRESH_LOW) 2332 2333 #define A_SGE_CHANGESET 0x1144 2334 #define A_SGE_PC_RSP_ERROR 0x1148 2335 #define A_SGE_TBUF_CONTROL 0x114c 2336 2337 #define S_DBPTBUFRSV1 9 2338 #define M_DBPTBUFRSV1 0x1ffU 2339 #define V_DBPTBUFRSV1(x) ((x) << S_DBPTBUFRSV1) 2340 #define G_DBPTBUFRSV1(x) (((x) >> S_DBPTBUFRSV1) & M_DBPTBUFRSV1) 2341 2342 #define S_DBPTBUFRSV0 0 2343 #define M_DBPTBUFRSV0 0x1ffU 2344 #define V_DBPTBUFRSV0(x) ((x) << S_DBPTBUFRSV0) 2345 #define G_DBPTBUFRSV0(x) (((x) >> S_DBPTBUFRSV0) & M_DBPTBUFRSV0) 2346 2347 #define A_SGE_PC0_REQ_BIST_CMD 0x1180 2348 #define A_SGE_PC0_REQ_BIST_ERROR_CNT 0x1184 2349 #define A_SGE_PC1_REQ_BIST_CMD 0x1190 2350 #define A_SGE_PC1_REQ_BIST_ERROR_CNT 0x1194 2351 #define A_SGE_PC0_RSP_BIST_CMD 0x11a0 2352 #define A_SGE_PC0_RSP_BIST_ERROR_CNT 0x11a4 2353 #define A_SGE_PC1_RSP_BIST_CMD 0x11b0 2354 #define A_SGE_PC1_RSP_BIST_ERROR_CNT 0x11b4 2355 #define A_SGE_CTXT_CMD 0x11fc 2356 2357 #define S_BUSY 31 2358 #define V_BUSY(x) ((x) << S_BUSY) 2359 #define F_BUSY V_BUSY(1U) 2360 2361 #define S_CTXTOP 28 2362 #define M_CTXTOP 0x3U 2363 #define V_CTXTOP(x) ((x) << S_CTXTOP) 2364 #define G_CTXTOP(x) (((x) >> S_CTXTOP) & M_CTXTOP) 2365 2366 #define S_CTXTTYPE 24 2367 #define M_CTXTTYPE 0x3U 2368 #define V_CTXTTYPE(x) ((x) << S_CTXTTYPE) 2369 #define G_CTXTTYPE(x) (((x) >> S_CTXTTYPE) & M_CTXTTYPE) 2370 2371 #define S_CTXTQID 0 2372 #define M_CTXTQID 0x1ffffU 2373 #define V_CTXTQID(x) ((x) << S_CTXTQID) 2374 #define G_CTXTQID(x) (((x) >> S_CTXTQID) & M_CTXTQID) 2375 2376 #define A_SGE_CTXT_DATA0 0x1200 2377 #define A_SGE_CTXT_DATA1 0x1204 2378 #define A_SGE_CTXT_DATA2 0x1208 2379 #define A_SGE_CTXT_DATA3 0x120c 2380 #define A_SGE_CTXT_DATA4 0x1210 2381 #define A_SGE_CTXT_DATA5 0x1214 2382 #define A_SGE_CTXT_DATA6 0x1218 2383 #define A_SGE_CTXT_DATA7 0x121c 2384 #define A_SGE_CTXT_MASK0 0x1220 2385 #define A_SGE_CTXT_MASK1 0x1224 2386 #define A_SGE_CTXT_MASK2 0x1228 2387 #define A_SGE_CTXT_MASK3 0x122c 2388 #define A_SGE_CTXT_MASK4 0x1230 2389 #define A_SGE_CTXT_MASK5 0x1234 2390 #define A_SGE_CTXT_MASK6 0x1238 2391 #define A_SGE_CTXT_MASK7 0x123c 2392 #define A_SGE_QBASE_MAP0 0x1240 2393 2394 #define S_EGRESS0_SIZE 24 2395 #define M_EGRESS0_SIZE 0x1fU 2396 #define V_EGRESS0_SIZE(x) ((x) << S_EGRESS0_SIZE) 2397 #define G_EGRESS0_SIZE(x) (((x) >> S_EGRESS0_SIZE) & M_EGRESS0_SIZE) 2398 2399 #define S_EGRESS1_SIZE 16 2400 #define M_EGRESS1_SIZE 0x1fU 2401 #define V_EGRESS1_SIZE(x) ((x) << S_EGRESS1_SIZE) 2402 #define G_EGRESS1_SIZE(x) (((x) >> S_EGRESS1_SIZE) & M_EGRESS1_SIZE) 2403 2404 #define S_INGRESS0_SIZE 8 2405 #define M_INGRESS0_SIZE 0x1fU 2406 #define V_INGRESS0_SIZE(x) ((x) << S_INGRESS0_SIZE) 2407 #define G_INGRESS0_SIZE(x) (((x) >> S_INGRESS0_SIZE) & M_INGRESS0_SIZE) 2408 2409 #define S_INGRESS1_SIZE 0 2410 #define M_INGRESS1_SIZE 0x1fU 2411 #define V_INGRESS1_SIZE(x) ((x) << S_INGRESS1_SIZE) 2412 #define G_INGRESS1_SIZE(x) (((x) >> S_INGRESS1_SIZE) & M_INGRESS1_SIZE) 2413 2414 #define A_SGE_QBASE_MAP1 0x1244 2415 2416 #define S_EGRESS0_BASE 0 2417 #define M_EGRESS0_BASE 0x1ffffU 2418 #define V_EGRESS0_BASE(x) ((x) << S_EGRESS0_BASE) 2419 #define G_EGRESS0_BASE(x) (((x) >> S_EGRESS0_BASE) & M_EGRESS0_BASE) 2420 2421 #define A_SGE_QBASE_MAP2 0x1248 2422 2423 #define S_EGRESS1_BASE 0 2424 #define M_EGRESS1_BASE 0x1ffffU 2425 #define V_EGRESS1_BASE(x) ((x) << S_EGRESS1_BASE) 2426 #define G_EGRESS1_BASE(x) (((x) >> S_EGRESS1_BASE) & M_EGRESS1_BASE) 2427 2428 #define A_SGE_QBASE_MAP3 0x124c 2429 2430 #define S_INGRESS1_BASE_256VF 16 2431 #define M_INGRESS1_BASE_256VF 0xffffU 2432 #define V_INGRESS1_BASE_256VF(x) ((x) << S_INGRESS1_BASE_256VF) 2433 #define G_INGRESS1_BASE_256VF(x) (((x) >> S_INGRESS1_BASE_256VF) & M_INGRESS1_BASE_256VF) 2434 2435 #define S_INGRESS0_BASE 0 2436 #define M_INGRESS0_BASE 0xffffU 2437 #define V_INGRESS0_BASE(x) ((x) << S_INGRESS0_BASE) 2438 #define G_INGRESS0_BASE(x) (((x) >> S_INGRESS0_BASE) & M_INGRESS0_BASE) 2439 2440 #define A_SGE_QBASE_INDEX 0x1250 2441 2442 #define S_QIDX 0 2443 #define M_QIDX 0x1ffU 2444 #define V_QIDX(x) ((x) << S_QIDX) 2445 #define G_QIDX(x) (((x) >> S_QIDX) & M_QIDX) 2446 2447 #define A_SGE_CONM_CTRL2 0x1254 2448 2449 #define S_FLMTHRESHPACK 8 2450 #define M_FLMTHRESHPACK 0x7fU 2451 #define V_FLMTHRESHPACK(x) ((x) << S_FLMTHRESHPACK) 2452 #define G_FLMTHRESHPACK(x) (((x) >> S_FLMTHRESHPACK) & M_FLMTHRESHPACK) 2453 2454 #define S_FLMTHRESH 0 2455 #define M_FLMTHRESH 0x7fU 2456 #define V_FLMTHRESH(x) ((x) << S_FLMTHRESH) 2457 #define G_FLMTHRESH(x) (((x) >> S_FLMTHRESH) & M_FLMTHRESH) 2458 2459 #define A_SGE_DEBUG_CONM 0x1258 2460 2461 #define S_MPS_CH_CNG 16 2462 #define M_MPS_CH_CNG 0xffffU 2463 #define V_MPS_CH_CNG(x) ((x) << S_MPS_CH_CNG) 2464 #define G_MPS_CH_CNG(x) (((x) >> S_MPS_CH_CNG) & M_MPS_CH_CNG) 2465 2466 #define S_TP_CH_CNG 14 2467 #define M_TP_CH_CNG 0x3U 2468 #define V_TP_CH_CNG(x) ((x) << S_TP_CH_CNG) 2469 #define G_TP_CH_CNG(x) (((x) >> S_TP_CH_CNG) & M_TP_CH_CNG) 2470 2471 #define S_ST_CONG 12 2472 #define M_ST_CONG 0x3U 2473 #define V_ST_CONG(x) ((x) << S_ST_CONG) 2474 #define G_ST_CONG(x) (((x) >> S_ST_CONG) & M_ST_CONG) 2475 2476 #define S_LAST_XOFF 10 2477 #define V_LAST_XOFF(x) ((x) << S_LAST_XOFF) 2478 #define F_LAST_XOFF V_LAST_XOFF(1U) 2479 2480 #define S_LAST_QID 0 2481 #define M_LAST_QID 0x3ffU 2482 #define V_LAST_QID(x) ((x) << S_LAST_QID) 2483 #define G_LAST_QID(x) (((x) >> S_LAST_QID) & M_LAST_QID) 2484 2485 #define A_SGE_DBG_QUEUE_STAT0_CTRL 0x125c 2486 2487 #define S_IMSG_GTS_SEL 18 2488 #define V_IMSG_GTS_SEL(x) ((x) << S_IMSG_GTS_SEL) 2489 #define F_IMSG_GTS_SEL V_IMSG_GTS_SEL(1U) 2490 2491 #define S_MGT_SEL 17 2492 #define V_MGT_SEL(x) ((x) << S_MGT_SEL) 2493 #define F_MGT_SEL V_MGT_SEL(1U) 2494 2495 #define S_DB_GTS_QID 0 2496 #define M_DB_GTS_QID 0x1ffffU 2497 #define V_DB_GTS_QID(x) ((x) << S_DB_GTS_QID) 2498 #define G_DB_GTS_QID(x) (((x) >> S_DB_GTS_QID) & M_DB_GTS_QID) 2499 2500 #define A_SGE_DBG_QUEUE_STAT1_CTRL 0x1260 2501 #define A_SGE_DBG_QUEUE_STAT0 0x1264 2502 #define A_SGE_DBG_QUEUE_STAT1 0x1268 2503 #define A_SGE_DBG_BAR2_PKT_CNT 0x126c 2504 #define A_SGE_DBG_DB_PKT_CNT 0x1270 2505 #define A_SGE_DBG_GTS_PKT_CNT 0x1274 2506 #define A_SGE_DEBUG_DATA_HIGH_INDEX_0 0x1280 2507 2508 #define S_CIM_WM 24 2509 #define M_CIM_WM 0x3U 2510 #define V_CIM_WM(x) ((x) << S_CIM_WM) 2511 #define G_CIM_WM(x) (((x) >> S_CIM_WM) & M_CIM_WM) 2512 2513 #define S_DEBUG_UP_SOP_CNT 20 2514 #define M_DEBUG_UP_SOP_CNT 0xfU 2515 #define V_DEBUG_UP_SOP_CNT(x) ((x) << S_DEBUG_UP_SOP_CNT) 2516 #define G_DEBUG_UP_SOP_CNT(x) (((x) >> S_DEBUG_UP_SOP_CNT) & M_DEBUG_UP_SOP_CNT) 2517 2518 #define S_DEBUG_UP_EOP_CNT 16 2519 #define M_DEBUG_UP_EOP_CNT 0xfU 2520 #define V_DEBUG_UP_EOP_CNT(x) ((x) << S_DEBUG_UP_EOP_CNT) 2521 #define G_DEBUG_UP_EOP_CNT(x) (((x) >> S_DEBUG_UP_EOP_CNT) & M_DEBUG_UP_EOP_CNT) 2522 2523 #define S_DEBUG_CIM_SOP1_CNT 12 2524 #define M_DEBUG_CIM_SOP1_CNT 0xfU 2525 #define V_DEBUG_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CIM_SOP1_CNT) 2526 #define G_DEBUG_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CIM_SOP1_CNT) & M_DEBUG_CIM_SOP1_CNT) 2527 2528 #define S_DEBUG_CIM_EOP1_CNT 8 2529 #define M_DEBUG_CIM_EOP1_CNT 0xfU 2530 #define V_DEBUG_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CIM_EOP1_CNT) 2531 #define G_DEBUG_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CIM_EOP1_CNT) & M_DEBUG_CIM_EOP1_CNT) 2532 2533 #define S_DEBUG_CIM_SOP0_CNT 4 2534 #define M_DEBUG_CIM_SOP0_CNT 0xfU 2535 #define V_DEBUG_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CIM_SOP0_CNT) 2536 #define G_DEBUG_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CIM_SOP0_CNT) & M_DEBUG_CIM_SOP0_CNT) 2537 2538 #define S_DEBUG_CIM_EOP0_CNT 0 2539 #define M_DEBUG_CIM_EOP0_CNT 0xfU 2540 #define V_DEBUG_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CIM_EOP0_CNT) 2541 #define G_DEBUG_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CIM_EOP0_CNT) & M_DEBUG_CIM_EOP0_CNT) 2542 2543 #define S_DEBUG_BAR2_SOP_CNT 28 2544 #define M_DEBUG_BAR2_SOP_CNT 0xfU 2545 #define V_DEBUG_BAR2_SOP_CNT(x) ((x) << S_DEBUG_BAR2_SOP_CNT) 2546 #define G_DEBUG_BAR2_SOP_CNT(x) (((x) >> S_DEBUG_BAR2_SOP_CNT) & M_DEBUG_BAR2_SOP_CNT) 2547 2548 #define S_DEBUG_BAR2_EOP_CNT 24 2549 #define M_DEBUG_BAR2_EOP_CNT 0xfU 2550 #define V_DEBUG_BAR2_EOP_CNT(x) ((x) << S_DEBUG_BAR2_EOP_CNT) 2551 #define G_DEBUG_BAR2_EOP_CNT(x) (((x) >> S_DEBUG_BAR2_EOP_CNT) & M_DEBUG_BAR2_EOP_CNT) 2552 2553 #define A_SGE_DEBUG_DATA_HIGH_INDEX_1 0x1284 2554 2555 #define S_DEBUG_T_RX_SOP1_CNT 28 2556 #define M_DEBUG_T_RX_SOP1_CNT 0xfU 2557 #define V_DEBUG_T_RX_SOP1_CNT(x) ((x) << S_DEBUG_T_RX_SOP1_CNT) 2558 #define G_DEBUG_T_RX_SOP1_CNT(x) (((x) >> S_DEBUG_T_RX_SOP1_CNT) & M_DEBUG_T_RX_SOP1_CNT) 2559 2560 #define S_DEBUG_T_RX_EOP1_CNT 24 2561 #define M_DEBUG_T_RX_EOP1_CNT 0xfU 2562 #define V_DEBUG_T_RX_EOP1_CNT(x) ((x) << S_DEBUG_T_RX_EOP1_CNT) 2563 #define G_DEBUG_T_RX_EOP1_CNT(x) (((x) >> S_DEBUG_T_RX_EOP1_CNT) & M_DEBUG_T_RX_EOP1_CNT) 2564 2565 #define S_DEBUG_T_RX_SOP0_CNT 20 2566 #define M_DEBUG_T_RX_SOP0_CNT 0xfU 2567 #define V_DEBUG_T_RX_SOP0_CNT(x) ((x) << S_DEBUG_T_RX_SOP0_CNT) 2568 #define G_DEBUG_T_RX_SOP0_CNT(x) (((x) >> S_DEBUG_T_RX_SOP0_CNT) & M_DEBUG_T_RX_SOP0_CNT) 2569 2570 #define S_DEBUG_T_RX_EOP0_CNT 16 2571 #define M_DEBUG_T_RX_EOP0_CNT 0xfU 2572 #define V_DEBUG_T_RX_EOP0_CNT(x) ((x) << S_DEBUG_T_RX_EOP0_CNT) 2573 #define G_DEBUG_T_RX_EOP0_CNT(x) (((x) >> S_DEBUG_T_RX_EOP0_CNT) & M_DEBUG_T_RX_EOP0_CNT) 2574 2575 #define S_DEBUG_U_RX_SOP1_CNT 12 2576 #define M_DEBUG_U_RX_SOP1_CNT 0xfU 2577 #define V_DEBUG_U_RX_SOP1_CNT(x) ((x) << S_DEBUG_U_RX_SOP1_CNT) 2578 #define G_DEBUG_U_RX_SOP1_CNT(x) (((x) >> S_DEBUG_U_RX_SOP1_CNT) & M_DEBUG_U_RX_SOP1_CNT) 2579 2580 #define S_DEBUG_U_RX_EOP1_CNT 8 2581 #define M_DEBUG_U_RX_EOP1_CNT 0xfU 2582 #define V_DEBUG_U_RX_EOP1_CNT(x) ((x) << S_DEBUG_U_RX_EOP1_CNT) 2583 #define G_DEBUG_U_RX_EOP1_CNT(x) (((x) >> S_DEBUG_U_RX_EOP1_CNT) & M_DEBUG_U_RX_EOP1_CNT) 2584 2585 #define S_DEBUG_U_RX_SOP0_CNT 4 2586 #define M_DEBUG_U_RX_SOP0_CNT 0xfU 2587 #define V_DEBUG_U_RX_SOP0_CNT(x) ((x) << S_DEBUG_U_RX_SOP0_CNT) 2588 #define G_DEBUG_U_RX_SOP0_CNT(x) (((x) >> S_DEBUG_U_RX_SOP0_CNT) & M_DEBUG_U_RX_SOP0_CNT) 2589 2590 #define S_DEBUG_U_RX_EOP0_CNT 0 2591 #define M_DEBUG_U_RX_EOP0_CNT 0xfU 2592 #define V_DEBUG_U_RX_EOP0_CNT(x) ((x) << S_DEBUG_U_RX_EOP0_CNT) 2593 #define G_DEBUG_U_RX_EOP0_CNT(x) (((x) >> S_DEBUG_U_RX_EOP0_CNT) & M_DEBUG_U_RX_EOP0_CNT) 2594 2595 #define A_SGE_DEBUG_DATA_HIGH_INDEX_2 0x1288 2596 2597 #define S_DEBUG_UD_RX_SOP3_CNT 28 2598 #define M_DEBUG_UD_RX_SOP3_CNT 0xfU 2599 #define V_DEBUG_UD_RX_SOP3_CNT(x) ((x) << S_DEBUG_UD_RX_SOP3_CNT) 2600 #define G_DEBUG_UD_RX_SOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP3_CNT) & M_DEBUG_UD_RX_SOP3_CNT) 2601 2602 #define S_DEBUG_UD_RX_EOP3_CNT 24 2603 #define M_DEBUG_UD_RX_EOP3_CNT 0xfU 2604 #define V_DEBUG_UD_RX_EOP3_CNT(x) ((x) << S_DEBUG_UD_RX_EOP3_CNT) 2605 #define G_DEBUG_UD_RX_EOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP3_CNT) & M_DEBUG_UD_RX_EOP3_CNT) 2606 2607 #define S_DEBUG_UD_RX_SOP2_CNT 20 2608 #define M_DEBUG_UD_RX_SOP2_CNT 0xfU 2609 #define V_DEBUG_UD_RX_SOP2_CNT(x) ((x) << S_DEBUG_UD_RX_SOP2_CNT) 2610 #define G_DEBUG_UD_RX_SOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP2_CNT) & M_DEBUG_UD_RX_SOP2_CNT) 2611 2612 #define S_DEBUG_UD_RX_EOP2_CNT 16 2613 #define M_DEBUG_UD_RX_EOP2_CNT 0xfU 2614 #define V_DEBUG_UD_RX_EOP2_CNT(x) ((x) << S_DEBUG_UD_RX_EOP2_CNT) 2615 #define G_DEBUG_UD_RX_EOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP2_CNT) & M_DEBUG_UD_RX_EOP2_CNT) 2616 2617 #define S_DEBUG_UD_RX_SOP1_CNT 12 2618 #define M_DEBUG_UD_RX_SOP1_CNT 0xfU 2619 #define V_DEBUG_UD_RX_SOP1_CNT(x) ((x) << S_DEBUG_UD_RX_SOP1_CNT) 2620 #define G_DEBUG_UD_RX_SOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP1_CNT) & M_DEBUG_UD_RX_SOP1_CNT) 2621 2622 #define S_DEBUG_UD_RX_EOP1_CNT 8 2623 #define M_DEBUG_UD_RX_EOP1_CNT 0xfU 2624 #define V_DEBUG_UD_RX_EOP1_CNT(x) ((x) << S_DEBUG_UD_RX_EOP1_CNT) 2625 #define G_DEBUG_UD_RX_EOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP1_CNT) & M_DEBUG_UD_RX_EOP1_CNT) 2626 2627 #define S_DEBUG_UD_RX_SOP0_CNT 4 2628 #define M_DEBUG_UD_RX_SOP0_CNT 0xfU 2629 #define V_DEBUG_UD_RX_SOP0_CNT(x) ((x) << S_DEBUG_UD_RX_SOP0_CNT) 2630 #define G_DEBUG_UD_RX_SOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP0_CNT) & M_DEBUG_UD_RX_SOP0_CNT) 2631 2632 #define S_DEBUG_UD_RX_EOP0_CNT 0 2633 #define M_DEBUG_UD_RX_EOP0_CNT 0xfU 2634 #define V_DEBUG_UD_RX_EOP0_CNT(x) ((x) << S_DEBUG_UD_RX_EOP0_CNT) 2635 #define G_DEBUG_UD_RX_EOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP0_CNT) & M_DEBUG_UD_RX_EOP0_CNT) 2636 2637 #define S_DBG_TBUF_USED1 9 2638 #define M_DBG_TBUF_USED1 0x1ffU 2639 #define V_DBG_TBUF_USED1(x) ((x) << S_DBG_TBUF_USED1) 2640 #define G_DBG_TBUF_USED1(x) (((x) >> S_DBG_TBUF_USED1) & M_DBG_TBUF_USED1) 2641 2642 #define S_DBG_TBUF_USED0 0 2643 #define M_DBG_TBUF_USED0 0x1ffU 2644 #define V_DBG_TBUF_USED0(x) ((x) << S_DBG_TBUF_USED0) 2645 #define G_DBG_TBUF_USED0(x) (((x) >> S_DBG_TBUF_USED0) & M_DBG_TBUF_USED0) 2646 2647 #define A_SGE_DEBUG_DATA_HIGH_INDEX_3 0x128c 2648 2649 #define S_DEBUG_U_TX_SOP3_CNT 28 2650 #define M_DEBUG_U_TX_SOP3_CNT 0xfU 2651 #define V_DEBUG_U_TX_SOP3_CNT(x) ((x) << S_DEBUG_U_TX_SOP3_CNT) 2652 #define G_DEBUG_U_TX_SOP3_CNT(x) (((x) >> S_DEBUG_U_TX_SOP3_CNT) & M_DEBUG_U_TX_SOP3_CNT) 2653 2654 #define S_DEBUG_U_TX_EOP3_CNT 24 2655 #define M_DEBUG_U_TX_EOP3_CNT 0xfU 2656 #define V_DEBUG_U_TX_EOP3_CNT(x) ((x) << S_DEBUG_U_TX_EOP3_CNT) 2657 #define G_DEBUG_U_TX_EOP3_CNT(x) (((x) >> S_DEBUG_U_TX_EOP3_CNT) & M_DEBUG_U_TX_EOP3_CNT) 2658 2659 #define S_DEBUG_U_TX_SOP2_CNT 20 2660 #define M_DEBUG_U_TX_SOP2_CNT 0xfU 2661 #define V_DEBUG_U_TX_SOP2_CNT(x) ((x) << S_DEBUG_U_TX_SOP2_CNT) 2662 #define G_DEBUG_U_TX_SOP2_CNT(x) (((x) >> S_DEBUG_U_TX_SOP2_CNT) & M_DEBUG_U_TX_SOP2_CNT) 2663 2664 #define S_DEBUG_U_TX_EOP2_CNT 16 2665 #define M_DEBUG_U_TX_EOP2_CNT 0xfU 2666 #define V_DEBUG_U_TX_EOP2_CNT(x) ((x) << S_DEBUG_U_TX_EOP2_CNT) 2667 #define G_DEBUG_U_TX_EOP2_CNT(x) (((x) >> S_DEBUG_U_TX_EOP2_CNT) & M_DEBUG_U_TX_EOP2_CNT) 2668 2669 #define S_DEBUG_U_TX_SOP1_CNT 12 2670 #define M_DEBUG_U_TX_SOP1_CNT 0xfU 2671 #define V_DEBUG_U_TX_SOP1_CNT(x) ((x) << S_DEBUG_U_TX_SOP1_CNT) 2672 #define G_DEBUG_U_TX_SOP1_CNT(x) (((x) >> S_DEBUG_U_TX_SOP1_CNT) & M_DEBUG_U_TX_SOP1_CNT) 2673 2674 #define S_DEBUG_U_TX_EOP1_CNT 8 2675 #define M_DEBUG_U_TX_EOP1_CNT 0xfU 2676 #define V_DEBUG_U_TX_EOP1_CNT(x) ((x) << S_DEBUG_U_TX_EOP1_CNT) 2677 #define G_DEBUG_U_TX_EOP1_CNT(x) (((x) >> S_DEBUG_U_TX_EOP1_CNT) & M_DEBUG_U_TX_EOP1_CNT) 2678 2679 #define S_DEBUG_U_TX_SOP0_CNT 4 2680 #define M_DEBUG_U_TX_SOP0_CNT 0xfU 2681 #define V_DEBUG_U_TX_SOP0_CNT(x) ((x) << S_DEBUG_U_TX_SOP0_CNT) 2682 #define G_DEBUG_U_TX_SOP0_CNT(x) (((x) >> S_DEBUG_U_TX_SOP0_CNT) & M_DEBUG_U_TX_SOP0_CNT) 2683 2684 #define S_DEBUG_U_TX_EOP0_CNT 0 2685 #define M_DEBUG_U_TX_EOP0_CNT 0xfU 2686 #define V_DEBUG_U_TX_EOP0_CNT(x) ((x) << S_DEBUG_U_TX_EOP0_CNT) 2687 #define G_DEBUG_U_TX_EOP0_CNT(x) (((x) >> S_DEBUG_U_TX_EOP0_CNT) & M_DEBUG_U_TX_EOP0_CNT) 2688 2689 #define A_SGE_DEBUG1_DBP_THREAD 0x128c 2690 2691 #define S_WR_DEQ_CNT 12 2692 #define M_WR_DEQ_CNT 0xfU 2693 #define V_WR_DEQ_CNT(x) ((x) << S_WR_DEQ_CNT) 2694 #define G_WR_DEQ_CNT(x) (((x) >> S_WR_DEQ_CNT) & M_WR_DEQ_CNT) 2695 2696 #define S_WR_ENQ_CNT 8 2697 #define M_WR_ENQ_CNT 0xfU 2698 #define V_WR_ENQ_CNT(x) ((x) << S_WR_ENQ_CNT) 2699 #define G_WR_ENQ_CNT(x) (((x) >> S_WR_ENQ_CNT) & M_WR_ENQ_CNT) 2700 2701 #define S_FL_DEQ_CNT 4 2702 #define M_FL_DEQ_CNT 0xfU 2703 #define V_FL_DEQ_CNT(x) ((x) << S_FL_DEQ_CNT) 2704 #define G_FL_DEQ_CNT(x) (((x) >> S_FL_DEQ_CNT) & M_FL_DEQ_CNT) 2705 2706 #define S_FL_ENQ_CNT 0 2707 #define M_FL_ENQ_CNT 0xfU 2708 #define V_FL_ENQ_CNT(x) ((x) << S_FL_ENQ_CNT) 2709 #define G_FL_ENQ_CNT(x) (((x) >> S_FL_ENQ_CNT) & M_FL_ENQ_CNT) 2710 2711 #define A_SGE_DEBUG_DATA_HIGH_INDEX_4 0x1290 2712 2713 #define S_DEBUG_PC_RSP_SOP1_CNT 28 2714 #define M_DEBUG_PC_RSP_SOP1_CNT 0xfU 2715 #define V_DEBUG_PC_RSP_SOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP1_CNT) 2716 #define G_DEBUG_PC_RSP_SOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP1_CNT) & M_DEBUG_PC_RSP_SOP1_CNT) 2717 2718 #define S_DEBUG_PC_RSP_EOP1_CNT 24 2719 #define M_DEBUG_PC_RSP_EOP1_CNT 0xfU 2720 #define V_DEBUG_PC_RSP_EOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP1_CNT) 2721 #define G_DEBUG_PC_RSP_EOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP1_CNT) & M_DEBUG_PC_RSP_EOP1_CNT) 2722 2723 #define S_DEBUG_PC_RSP_SOP0_CNT 20 2724 #define M_DEBUG_PC_RSP_SOP0_CNT 0xfU 2725 #define V_DEBUG_PC_RSP_SOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP0_CNT) 2726 #define G_DEBUG_PC_RSP_SOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP0_CNT) & M_DEBUG_PC_RSP_SOP0_CNT) 2727 2728 #define S_DEBUG_PC_RSP_EOP0_CNT 16 2729 #define M_DEBUG_PC_RSP_EOP0_CNT 0xfU 2730 #define V_DEBUG_PC_RSP_EOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP0_CNT) 2731 #define G_DEBUG_PC_RSP_EOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP0_CNT) & M_DEBUG_PC_RSP_EOP0_CNT) 2732 2733 #define S_DEBUG_PC_REQ_SOP1_CNT 12 2734 #define M_DEBUG_PC_REQ_SOP1_CNT 0xfU 2735 #define V_DEBUG_PC_REQ_SOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP1_CNT) 2736 #define G_DEBUG_PC_REQ_SOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP1_CNT) & M_DEBUG_PC_REQ_SOP1_CNT) 2737 2738 #define S_DEBUG_PC_REQ_EOP1_CNT 8 2739 #define M_DEBUG_PC_REQ_EOP1_CNT 0xfU 2740 #define V_DEBUG_PC_REQ_EOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP1_CNT) 2741 #define G_DEBUG_PC_REQ_EOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP1_CNT) & M_DEBUG_PC_REQ_EOP1_CNT) 2742 2743 #define S_DEBUG_PC_REQ_SOP0_CNT 4 2744 #define M_DEBUG_PC_REQ_SOP0_CNT 0xfU 2745 #define V_DEBUG_PC_REQ_SOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP0_CNT) 2746 #define G_DEBUG_PC_REQ_SOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP0_CNT) & M_DEBUG_PC_REQ_SOP0_CNT) 2747 2748 #define S_DEBUG_PC_REQ_EOP0_CNT 0 2749 #define M_DEBUG_PC_REQ_EOP0_CNT 0xfU 2750 #define V_DEBUG_PC_REQ_EOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP0_CNT) 2751 #define G_DEBUG_PC_REQ_EOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP0_CNT) & M_DEBUG_PC_REQ_EOP0_CNT) 2752 2753 #define A_SGE_DEBUG_DATA_HIGH_INDEX_5 0x1294 2754 2755 #define S_DEBUG_PD_RDREQ_SOP3_CNT 28 2756 #define M_DEBUG_PD_RDREQ_SOP3_CNT 0xfU 2757 #define V_DEBUG_PD_RDREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP3_CNT) 2758 #define G_DEBUG_PD_RDREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP3_CNT) & M_DEBUG_PD_RDREQ_SOP3_CNT) 2759 2760 #define S_DEBUG_PD_RDREQ_EOP3_CNT 24 2761 #define M_DEBUG_PD_RDREQ_EOP3_CNT 0xfU 2762 #define V_DEBUG_PD_RDREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP3_CNT) 2763 #define G_DEBUG_PD_RDREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP3_CNT) & M_DEBUG_PD_RDREQ_EOP3_CNT) 2764 2765 #define S_DEBUG_PD_RDREQ_SOP2_CNT 20 2766 #define M_DEBUG_PD_RDREQ_SOP2_CNT 0xfU 2767 #define V_DEBUG_PD_RDREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP2_CNT) 2768 #define G_DEBUG_PD_RDREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP2_CNT) & M_DEBUG_PD_RDREQ_SOP2_CNT) 2769 2770 #define S_DEBUG_PD_RDREQ_EOP2_CNT 16 2771 #define M_DEBUG_PD_RDREQ_EOP2_CNT 0xfU 2772 #define V_DEBUG_PD_RDREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP2_CNT) 2773 #define G_DEBUG_PD_RDREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP2_CNT) & M_DEBUG_PD_RDREQ_EOP2_CNT) 2774 2775 #define S_DEBUG_PD_RDREQ_SOP1_CNT 12 2776 #define M_DEBUG_PD_RDREQ_SOP1_CNT 0xfU 2777 #define V_DEBUG_PD_RDREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP1_CNT) 2778 #define G_DEBUG_PD_RDREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP1_CNT) & M_DEBUG_PD_RDREQ_SOP1_CNT) 2779 2780 #define S_DEBUG_PD_RDREQ_EOP1_CNT 8 2781 #define M_DEBUG_PD_RDREQ_EOP1_CNT 0xfU 2782 #define V_DEBUG_PD_RDREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP1_CNT) 2783 #define G_DEBUG_PD_RDREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP1_CNT) & M_DEBUG_PD_RDREQ_EOP1_CNT) 2784 2785 #define S_DEBUG_PD_RDREQ_SOP0_CNT 4 2786 #define M_DEBUG_PD_RDREQ_SOP0_CNT 0xfU 2787 #define V_DEBUG_PD_RDREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP0_CNT) 2788 #define G_DEBUG_PD_RDREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP0_CNT) & M_DEBUG_PD_RDREQ_SOP0_CNT) 2789 2790 #define S_DEBUG_PD_RDREQ_EOP0_CNT 0 2791 #define M_DEBUG_PD_RDREQ_EOP0_CNT 0xfU 2792 #define V_DEBUG_PD_RDREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP0_CNT) 2793 #define G_DEBUG_PD_RDREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP0_CNT) & M_DEBUG_PD_RDREQ_EOP0_CNT) 2794 2795 #define A_SGE_DEBUG_DATA_HIGH_INDEX_6 0x1298 2796 2797 #define S_DEBUG_PD_RDRSP_SOP3_CNT 28 2798 #define M_DEBUG_PD_RDRSP_SOP3_CNT 0xfU 2799 #define V_DEBUG_PD_RDRSP_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP3_CNT) 2800 #define G_DEBUG_PD_RDRSP_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP3_CNT) & M_DEBUG_PD_RDRSP_SOP3_CNT) 2801 2802 #define S_DEBUG_PD_RDRSP_EOP3_CNT 24 2803 #define M_DEBUG_PD_RDRSP_EOP3_CNT 0xfU 2804 #define V_DEBUG_PD_RDRSP_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP3_CNT) 2805 #define G_DEBUG_PD_RDRSP_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP3_CNT) & M_DEBUG_PD_RDRSP_EOP3_CNT) 2806 2807 #define S_DEBUG_PD_RDRSP_SOP2_CNT 20 2808 #define M_DEBUG_PD_RDRSP_SOP2_CNT 0xfU 2809 #define V_DEBUG_PD_RDRSP_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP2_CNT) 2810 #define G_DEBUG_PD_RDRSP_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP2_CNT) & M_DEBUG_PD_RDRSP_SOP2_CNT) 2811 2812 #define S_DEBUG_PD_RDRSP_EOP2_CNT 16 2813 #define M_DEBUG_PD_RDRSP_EOP2_CNT 0xfU 2814 #define V_DEBUG_PD_RDRSP_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP2_CNT) 2815 #define G_DEBUG_PD_RDRSP_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP2_CNT) & M_DEBUG_PD_RDRSP_EOP2_CNT) 2816 2817 #define S_DEBUG_PD_RDRSP_SOP1_CNT 12 2818 #define M_DEBUG_PD_RDRSP_SOP1_CNT 0xfU 2819 #define V_DEBUG_PD_RDRSP_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP1_CNT) 2820 #define G_DEBUG_PD_RDRSP_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP1_CNT) & M_DEBUG_PD_RDRSP_SOP1_CNT) 2821 2822 #define S_DEBUG_PD_RDRSP_EOP1_CNT 8 2823 #define M_DEBUG_PD_RDRSP_EOP1_CNT 0xfU 2824 #define V_DEBUG_PD_RDRSP_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP1_CNT) 2825 #define G_DEBUG_PD_RDRSP_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP1_CNT) & M_DEBUG_PD_RDRSP_EOP1_CNT) 2826 2827 #define S_DEBUG_PD_RDRSP_SOP0_CNT 4 2828 #define M_DEBUG_PD_RDRSP_SOP0_CNT 0xfU 2829 #define V_DEBUG_PD_RDRSP_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP0_CNT) 2830 #define G_DEBUG_PD_RDRSP_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP0_CNT) & M_DEBUG_PD_RDRSP_SOP0_CNT) 2831 2832 #define S_DEBUG_PD_RDRSP_EOP0_CNT 0 2833 #define M_DEBUG_PD_RDRSP_EOP0_CNT 0xfU 2834 #define V_DEBUG_PD_RDRSP_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP0_CNT) 2835 #define G_DEBUG_PD_RDRSP_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP0_CNT) & M_DEBUG_PD_RDRSP_EOP0_CNT) 2836 2837 #define A_SGE_DEBUG_DATA_HIGH_INDEX_7 0x129c 2838 2839 #define S_DEBUG_PD_WRREQ_SOP3_CNT 28 2840 #define M_DEBUG_PD_WRREQ_SOP3_CNT 0xfU 2841 #define V_DEBUG_PD_WRREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP3_CNT) 2842 #define G_DEBUG_PD_WRREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP3_CNT) & M_DEBUG_PD_WRREQ_SOP3_CNT) 2843 2844 #define S_DEBUG_PD_WRREQ_EOP3_CNT 24 2845 #define M_DEBUG_PD_WRREQ_EOP3_CNT 0xfU 2846 #define V_DEBUG_PD_WRREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP3_CNT) 2847 #define G_DEBUG_PD_WRREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP3_CNT) & M_DEBUG_PD_WRREQ_EOP3_CNT) 2848 2849 #define S_DEBUG_PD_WRREQ_SOP2_CNT 20 2850 #define M_DEBUG_PD_WRREQ_SOP2_CNT 0xfU 2851 #define V_DEBUG_PD_WRREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP2_CNT) 2852 #define G_DEBUG_PD_WRREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP2_CNT) & M_DEBUG_PD_WRREQ_SOP2_CNT) 2853 2854 #define S_DEBUG_PD_WRREQ_EOP2_CNT 16 2855 #define M_DEBUG_PD_WRREQ_EOP2_CNT 0xfU 2856 #define V_DEBUG_PD_WRREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP2_CNT) 2857 #define G_DEBUG_PD_WRREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP2_CNT) & M_DEBUG_PD_WRREQ_EOP2_CNT) 2858 2859 #define S_DEBUG_PD_WRREQ_SOP1_CNT 12 2860 #define M_DEBUG_PD_WRREQ_SOP1_CNT 0xfU 2861 #define V_DEBUG_PD_WRREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP1_CNT) 2862 #define G_DEBUG_PD_WRREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP1_CNT) & M_DEBUG_PD_WRREQ_SOP1_CNT) 2863 2864 #define S_DEBUG_PD_WRREQ_EOP1_CNT 8 2865 #define M_DEBUG_PD_WRREQ_EOP1_CNT 0xfU 2866 #define V_DEBUG_PD_WRREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP1_CNT) 2867 #define G_DEBUG_PD_WRREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP1_CNT) & M_DEBUG_PD_WRREQ_EOP1_CNT) 2868 2869 #define S_DEBUG_PD_WRREQ_SOP0_CNT 4 2870 #define M_DEBUG_PD_WRREQ_SOP0_CNT 0xfU 2871 #define V_DEBUG_PD_WRREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP0_CNT) 2872 #define G_DEBUG_PD_WRREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP0_CNT) & M_DEBUG_PD_WRREQ_SOP0_CNT) 2873 2874 #define S_DEBUG_PD_WRREQ_EOP0_CNT 0 2875 #define M_DEBUG_PD_WRREQ_EOP0_CNT 0xfU 2876 #define V_DEBUG_PD_WRREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP0_CNT) 2877 #define G_DEBUG_PD_WRREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP0_CNT) & M_DEBUG_PD_WRREQ_EOP0_CNT) 2878 2879 #define S_DEBUG_PC_RSP_SOP_CNT 28 2880 #define M_DEBUG_PC_RSP_SOP_CNT 0xfU 2881 #define V_DEBUG_PC_RSP_SOP_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP_CNT) 2882 #define G_DEBUG_PC_RSP_SOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP_CNT) & M_DEBUG_PC_RSP_SOP_CNT) 2883 2884 #define S_DEBUG_PC_RSP_EOP_CNT 24 2885 #define M_DEBUG_PC_RSP_EOP_CNT 0xfU 2886 #define V_DEBUG_PC_RSP_EOP_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP_CNT) 2887 #define G_DEBUG_PC_RSP_EOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP_CNT) & M_DEBUG_PC_RSP_EOP_CNT) 2888 2889 #define S_DEBUG_PC_REQ_SOP_CNT 20 2890 #define M_DEBUG_PC_REQ_SOP_CNT 0xfU 2891 #define V_DEBUG_PC_REQ_SOP_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP_CNT) 2892 #define G_DEBUG_PC_REQ_SOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP_CNT) & M_DEBUG_PC_REQ_SOP_CNT) 2893 2894 #define S_DEBUG_PC_REQ_EOP_CNT 16 2895 #define M_DEBUG_PC_REQ_EOP_CNT 0xfU 2896 #define V_DEBUG_PC_REQ_EOP_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP_CNT) 2897 #define G_DEBUG_PC_REQ_EOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP_CNT) & M_DEBUG_PC_REQ_EOP_CNT) 2898 2899 #define A_SGE_DEBUG_DATA_HIGH_INDEX_8 0x12a0 2900 2901 #define S_GLOBALENABLE_OFF 29 2902 #define V_GLOBALENABLE_OFF(x) ((x) << S_GLOBALENABLE_OFF) 2903 #define F_GLOBALENABLE_OFF V_GLOBALENABLE_OFF(1U) 2904 2905 #define S_DEBUG_CIM2SGE_RXAFULL_D 27 2906 #define M_DEBUG_CIM2SGE_RXAFULL_D 0x3U 2907 #define V_DEBUG_CIM2SGE_RXAFULL_D(x) ((x) << S_DEBUG_CIM2SGE_RXAFULL_D) 2908 #define G_DEBUG_CIM2SGE_RXAFULL_D(x) (((x) >> S_DEBUG_CIM2SGE_RXAFULL_D) & M_DEBUG_CIM2SGE_RXAFULL_D) 2909 2910 #define S_DEBUG_CPLSW_CIM_TXAFULL_D 25 2911 #define M_DEBUG_CPLSW_CIM_TXAFULL_D 0x3U 2912 #define V_DEBUG_CPLSW_CIM_TXAFULL_D(x) ((x) << S_DEBUG_CPLSW_CIM_TXAFULL_D) 2913 #define G_DEBUG_CPLSW_CIM_TXAFULL_D(x) (((x) >> S_DEBUG_CPLSW_CIM_TXAFULL_D) & M_DEBUG_CPLSW_CIM_TXAFULL_D) 2914 2915 #define S_DEBUG_UP_FULL 24 2916 #define V_DEBUG_UP_FULL(x) ((x) << S_DEBUG_UP_FULL) 2917 #define F_DEBUG_UP_FULL V_DEBUG_UP_FULL(1U) 2918 2919 #define S_DEBUG_M_RD_REQ_OUTSTANDING_PC 23 2920 #define V_DEBUG_M_RD_REQ_OUTSTANDING_PC(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_PC) 2921 #define F_DEBUG_M_RD_REQ_OUTSTANDING_PC V_DEBUG_M_RD_REQ_OUTSTANDING_PC(1U) 2922 2923 #define S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO 22 2924 #define V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO) 2925 #define F_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(1U) 2926 2927 #define S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG 21 2928 #define V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG) 2929 #define F_DEBUG_M_RD_REQ_OUTSTANDING_IMSG V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(1U) 2930 2931 #define S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB 20 2932 #define V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB) 2933 #define F_DEBUG_M_RD_REQ_OUTSTANDING_CMARB V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(1U) 2934 2935 #define S_DEBUG_M_RD_REQ_OUTSTANDING_FLM 19 2936 #define V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_FLM) 2937 #define F_DEBUG_M_RD_REQ_OUTSTANDING_FLM V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(1U) 2938 2939 #define S_DEBUG_M_REQVLD 18 2940 #define V_DEBUG_M_REQVLD(x) ((x) << S_DEBUG_M_REQVLD) 2941 #define F_DEBUG_M_REQVLD V_DEBUG_M_REQVLD(1U) 2942 2943 #define S_DEBUG_M_REQRDY 17 2944 #define V_DEBUG_M_REQRDY(x) ((x) << S_DEBUG_M_REQRDY) 2945 #define F_DEBUG_M_REQRDY V_DEBUG_M_REQRDY(1U) 2946 2947 #define S_DEBUG_M_RSPVLD 16 2948 #define V_DEBUG_M_RSPVLD(x) ((x) << S_DEBUG_M_RSPVLD) 2949 #define F_DEBUG_M_RSPVLD V_DEBUG_M_RSPVLD(1U) 2950 2951 #define S_DEBUG_PD_WRREQ_INT3_CNT 12 2952 #define M_DEBUG_PD_WRREQ_INT3_CNT 0xfU 2953 #define V_DEBUG_PD_WRREQ_INT3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT3_CNT) 2954 #define G_DEBUG_PD_WRREQ_INT3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT3_CNT) & M_DEBUG_PD_WRREQ_INT3_CNT) 2955 2956 #define S_DEBUG_PD_WRREQ_INT2_CNT 8 2957 #define M_DEBUG_PD_WRREQ_INT2_CNT 0xfU 2958 #define V_DEBUG_PD_WRREQ_INT2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT2_CNT) 2959 #define G_DEBUG_PD_WRREQ_INT2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT2_CNT) & M_DEBUG_PD_WRREQ_INT2_CNT) 2960 2961 #define S_DEBUG_PD_WRREQ_INT1_CNT 4 2962 #define M_DEBUG_PD_WRREQ_INT1_CNT 0xfU 2963 #define V_DEBUG_PD_WRREQ_INT1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT1_CNT) 2964 #define G_DEBUG_PD_WRREQ_INT1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT1_CNT) & M_DEBUG_PD_WRREQ_INT1_CNT) 2965 2966 #define S_DEBUG_PD_WRREQ_INT0_CNT 0 2967 #define M_DEBUG_PD_WRREQ_INT0_CNT 0xfU 2968 #define V_DEBUG_PD_WRREQ_INT0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT0_CNT) 2969 #define G_DEBUG_PD_WRREQ_INT0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT0_CNT) & M_DEBUG_PD_WRREQ_INT0_CNT) 2970 2971 #define S_DEBUG_PL_BAR2_REQVLD 31 2972 #define V_DEBUG_PL_BAR2_REQVLD(x) ((x) << S_DEBUG_PL_BAR2_REQVLD) 2973 #define F_DEBUG_PL_BAR2_REQVLD V_DEBUG_PL_BAR2_REQVLD(1U) 2974 2975 #define S_DEBUG_PL_BAR2_REQFULL 30 2976 #define V_DEBUG_PL_BAR2_REQFULL(x) ((x) << S_DEBUG_PL_BAR2_REQFULL) 2977 #define F_DEBUG_PL_BAR2_REQFULL V_DEBUG_PL_BAR2_REQFULL(1U) 2978 2979 #define A_SGE_DEBUG_DATA_HIGH_INDEX_9 0x12a4 2980 2981 #define S_DEBUG_CPLSW_TP_RX_SOP1_CNT 28 2982 #define M_DEBUG_CPLSW_TP_RX_SOP1_CNT 0xfU 2983 #define V_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP1_CNT) 2984 #define G_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP1_CNT) & M_DEBUG_CPLSW_TP_RX_SOP1_CNT) 2985 2986 #define S_DEBUG_CPLSW_TP_RX_EOP1_CNT 24 2987 #define M_DEBUG_CPLSW_TP_RX_EOP1_CNT 0xfU 2988 #define V_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP1_CNT) 2989 #define G_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP1_CNT) & M_DEBUG_CPLSW_TP_RX_EOP1_CNT) 2990 2991 #define S_DEBUG_CPLSW_TP_RX_SOP0_CNT 20 2992 #define M_DEBUG_CPLSW_TP_RX_SOP0_CNT 0xfU 2993 #define V_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP0_CNT) 2994 #define G_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP0_CNT) & M_DEBUG_CPLSW_TP_RX_SOP0_CNT) 2995 2996 #define S_DEBUG_CPLSW_TP_RX_EOP0_CNT 16 2997 #define M_DEBUG_CPLSW_TP_RX_EOP0_CNT 0xfU 2998 #define V_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP0_CNT) 2999 #define G_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP0_CNT) & M_DEBUG_CPLSW_TP_RX_EOP0_CNT) 3000 3001 #define S_DEBUG_CPLSW_CIM_SOP1_CNT 12 3002 #define M_DEBUG_CPLSW_CIM_SOP1_CNT 0xfU 3003 #define V_DEBUG_CPLSW_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP1_CNT) 3004 #define G_DEBUG_CPLSW_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP1_CNT) & M_DEBUG_CPLSW_CIM_SOP1_CNT) 3005 3006 #define S_DEBUG_CPLSW_CIM_EOP1_CNT 8 3007 #define M_DEBUG_CPLSW_CIM_EOP1_CNT 0xfU 3008 #define V_DEBUG_CPLSW_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP1_CNT) 3009 #define G_DEBUG_CPLSW_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP1_CNT) & M_DEBUG_CPLSW_CIM_EOP1_CNT) 3010 3011 #define S_DEBUG_CPLSW_CIM_SOP0_CNT 4 3012 #define M_DEBUG_CPLSW_CIM_SOP0_CNT 0xfU 3013 #define V_DEBUG_CPLSW_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP0_CNT) 3014 #define G_DEBUG_CPLSW_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP0_CNT) & M_DEBUG_CPLSW_CIM_SOP0_CNT) 3015 3016 #define S_DEBUG_CPLSW_CIM_EOP0_CNT 0 3017 #define M_DEBUG_CPLSW_CIM_EOP0_CNT 0xfU 3018 #define V_DEBUG_CPLSW_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP0_CNT) 3019 #define G_DEBUG_CPLSW_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP0_CNT) & M_DEBUG_CPLSW_CIM_EOP0_CNT) 3020 3021 #define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8 3022 3023 #define S_DEBUG_T_RXAFULL_D 30 3024 #define M_DEBUG_T_RXAFULL_D 0x3U 3025 #define V_DEBUG_T_RXAFULL_D(x) ((x) << S_DEBUG_T_RXAFULL_D) 3026 #define G_DEBUG_T_RXAFULL_D(x) (((x) >> S_DEBUG_T_RXAFULL_D) & M_DEBUG_T_RXAFULL_D) 3027 3028 #define S_DEBUG_PD_RDRSPAFULL_D 26 3029 #define M_DEBUG_PD_RDRSPAFULL_D 0xfU 3030 #define V_DEBUG_PD_RDRSPAFULL_D(x) ((x) << S_DEBUG_PD_RDRSPAFULL_D) 3031 #define G_DEBUG_PD_RDRSPAFULL_D(x) (((x) >> S_DEBUG_PD_RDRSPAFULL_D) & M_DEBUG_PD_RDRSPAFULL_D) 3032 3033 #define S_DEBUG_PD_RDREQAFULL_D 22 3034 #define M_DEBUG_PD_RDREQAFULL_D 0xfU 3035 #define V_DEBUG_PD_RDREQAFULL_D(x) ((x) << S_DEBUG_PD_RDREQAFULL_D) 3036 #define G_DEBUG_PD_RDREQAFULL_D(x) (((x) >> S_DEBUG_PD_RDREQAFULL_D) & M_DEBUG_PD_RDREQAFULL_D) 3037 3038 #define S_DEBUG_PD_WRREQAFULL_D 18 3039 #define M_DEBUG_PD_WRREQAFULL_D 0xfU 3040 #define V_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_DEBUG_PD_WRREQAFULL_D) 3041 #define G_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_DEBUG_PD_WRREQAFULL_D) & M_DEBUG_PD_WRREQAFULL_D) 3042 3043 #define S_DEBUG_PC_RSPAFULL_D 15 3044 #define M_DEBUG_PC_RSPAFULL_D 0x7U 3045 #define V_DEBUG_PC_RSPAFULL_D(x) ((x) << S_DEBUG_PC_RSPAFULL_D) 3046 #define G_DEBUG_PC_RSPAFULL_D(x) (((x) >> S_DEBUG_PC_RSPAFULL_D) & M_DEBUG_PC_RSPAFULL_D) 3047 3048 #define S_DEBUG_PC_REQAFULL_D 12 3049 #define M_DEBUG_PC_REQAFULL_D 0x7U 3050 #define V_DEBUG_PC_REQAFULL_D(x) ((x) << S_DEBUG_PC_REQAFULL_D) 3051 #define G_DEBUG_PC_REQAFULL_D(x) (((x) >> S_DEBUG_PC_REQAFULL_D) & M_DEBUG_PC_REQAFULL_D) 3052 3053 #define S_DEBUG_U_TXAFULL_D 8 3054 #define M_DEBUG_U_TXAFULL_D 0xfU 3055 #define V_DEBUG_U_TXAFULL_D(x) ((x) << S_DEBUG_U_TXAFULL_D) 3056 #define G_DEBUG_U_TXAFULL_D(x) (((x) >> S_DEBUG_U_TXAFULL_D) & M_DEBUG_U_TXAFULL_D) 3057 3058 #define S_DEBUG_UD_RXAFULL_D 4 3059 #define M_DEBUG_UD_RXAFULL_D 0xfU 3060 #define V_DEBUG_UD_RXAFULL_D(x) ((x) << S_DEBUG_UD_RXAFULL_D) 3061 #define G_DEBUG_UD_RXAFULL_D(x) (((x) >> S_DEBUG_UD_RXAFULL_D) & M_DEBUG_UD_RXAFULL_D) 3062 3063 #define S_DEBUG_U_RXAFULL_D 2 3064 #define M_DEBUG_U_RXAFULL_D 0x3U 3065 #define V_DEBUG_U_RXAFULL_D(x) ((x) << S_DEBUG_U_RXAFULL_D) 3066 #define G_DEBUG_U_RXAFULL_D(x) (((x) >> S_DEBUG_U_RXAFULL_D) & M_DEBUG_U_RXAFULL_D) 3067 3068 #define S_DEBUG_CIM_AFULL_D 0 3069 #define M_DEBUG_CIM_AFULL_D 0x3U 3070 #define V_DEBUG_CIM_AFULL_D(x) ((x) << S_DEBUG_CIM_AFULL_D) 3071 #define G_DEBUG_CIM_AFULL_D(x) (((x) >> S_DEBUG_CIM_AFULL_D) & M_DEBUG_CIM_AFULL_D) 3072 3073 #define S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING 28 3074 #define M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING 0xfU 3075 #define V_DEBUG_IDMA1_S_CPL_FLIT_REMAINING(x) ((x) << S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING) 3076 #define G_DEBUG_IDMA1_S_CPL_FLIT_REMAINING(x) (((x) >> S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING) & M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING) 3077 3078 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY 27 3079 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY) 3080 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY(1U) 3081 3082 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS 26 3083 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS) 3084 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS(1U) 3085 3086 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL 25 3087 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL) 3088 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL(1U) 3089 3090 #define S_DEBUG_IDMA1_IDMA2IMSG_FULL 24 3091 #define V_DEBUG_IDMA1_IDMA2IMSG_FULL(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_FULL) 3092 #define F_DEBUG_IDMA1_IDMA2IMSG_FULL V_DEBUG_IDMA1_IDMA2IMSG_FULL(1U) 3093 3094 #define S_DEBUG_IDMA1_IDMA2IMSG_EOP 23 3095 #define V_DEBUG_IDMA1_IDMA2IMSG_EOP(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_EOP) 3096 #define F_DEBUG_IDMA1_IDMA2IMSG_EOP V_DEBUG_IDMA1_IDMA2IMSG_EOP(1U) 3097 3098 #define S_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY 22 3099 #define V_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY) 3100 #define F_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY V_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY(1U) 3101 3102 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY 21 3103 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY) 3104 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY V_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY(1U) 3105 3106 #define S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING 17 3107 #define M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING 0xfU 3108 #define V_DEBUG_IDMA0_S_CPL_FLIT_REMAINING(x) ((x) << S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING) 3109 #define G_DEBUG_IDMA0_S_CPL_FLIT_REMAINING(x) (((x) >> S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING) & M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING) 3110 3111 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY 16 3112 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY) 3113 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY(1U) 3114 3115 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS 15 3116 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS) 3117 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS(1U) 3118 3119 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL 14 3120 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL) 3121 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL(1U) 3122 3123 #define S_DEBUG_IDMA0_IDMA2IMSG_FULL 13 3124 #define V_DEBUG_IDMA0_IDMA2IMSG_FULL(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_FULL) 3125 #define F_DEBUG_IDMA0_IDMA2IMSG_FULL V_DEBUG_IDMA0_IDMA2IMSG_FULL(1U) 3126 3127 #define S_DEBUG_IDMA0_IDMA2IMSG_EOP 12 3128 #define V_DEBUG_IDMA0_IDMA2IMSG_EOP(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_EOP) 3129 #define F_DEBUG_IDMA0_IDMA2IMSG_EOP V_DEBUG_IDMA0_IDMA2IMSG_EOP(1U) 3130 3131 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY 11 3132 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY) 3133 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY V_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY(1U) 3134 3135 #define S_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY 10 3136 #define V_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY) 3137 #define F_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY V_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY(1U) 3138 3139 #define S_T6_DEBUG_T_RXAFULL_D 8 3140 #define M_T6_DEBUG_T_RXAFULL_D 0x3U 3141 #define V_T6_DEBUG_T_RXAFULL_D(x) ((x) << S_T6_DEBUG_T_RXAFULL_D) 3142 #define G_T6_DEBUG_T_RXAFULL_D(x) (((x) >> S_T6_DEBUG_T_RXAFULL_D) & M_T6_DEBUG_T_RXAFULL_D) 3143 3144 #define S_T6_DEBUG_PD_WRREQAFULL_D 6 3145 #define M_T6_DEBUG_PD_WRREQAFULL_D 0x3U 3146 #define V_T6_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_T6_DEBUG_PD_WRREQAFULL_D) 3147 #define G_T6_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_T6_DEBUG_PD_WRREQAFULL_D) & M_T6_DEBUG_PD_WRREQAFULL_D) 3148 3149 #define S_T6_DEBUG_PC_RSPAFULL_D 5 3150 #define V_T6_DEBUG_PC_RSPAFULL_D(x) ((x) << S_T6_DEBUG_PC_RSPAFULL_D) 3151 #define F_T6_DEBUG_PC_RSPAFULL_D V_T6_DEBUG_PC_RSPAFULL_D(1U) 3152 3153 #define S_T6_DEBUG_PC_REQAFULL_D 4 3154 #define V_T6_DEBUG_PC_REQAFULL_D(x) ((x) << S_T6_DEBUG_PC_REQAFULL_D) 3155 #define F_T6_DEBUG_PC_REQAFULL_D V_T6_DEBUG_PC_REQAFULL_D(1U) 3156 3157 #define S_T6_DEBUG_CIM_AFULL_D 0 3158 #define V_T6_DEBUG_CIM_AFULL_D(x) ((x) << S_T6_DEBUG_CIM_AFULL_D) 3159 #define F_T6_DEBUG_CIM_AFULL_D V_T6_DEBUG_CIM_AFULL_D(1U) 3160 3161 #define A_SGE_DEBUG_DATA_HIGH_INDEX_11 0x12ac 3162 3163 #define S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE 24 3164 #define V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE) 3165 #define F_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(1U) 3166 3167 #define S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE 23 3168 #define V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE) 3169 #define F_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(1U) 3170 3171 #define S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE 22 3172 #define V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE) 3173 #define F_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(1U) 3174 3175 #define S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE 21 3176 #define V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE) 3177 #define F_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(1U) 3178 3179 #define S_DEBUG_ST_FLM_IDMA1_CACHE 19 3180 #define M_DEBUG_ST_FLM_IDMA1_CACHE 0x3U 3181 #define V_DEBUG_ST_FLM_IDMA1_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CACHE) 3182 #define G_DEBUG_ST_FLM_IDMA1_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CACHE) & M_DEBUG_ST_FLM_IDMA1_CACHE) 3183 3184 #define S_DEBUG_ST_FLM_IDMA1_CTXT 16 3185 #define M_DEBUG_ST_FLM_IDMA1_CTXT 0x7U 3186 #define V_DEBUG_ST_FLM_IDMA1_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CTXT) 3187 #define G_DEBUG_ST_FLM_IDMA1_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CTXT) & M_DEBUG_ST_FLM_IDMA1_CTXT) 3188 3189 #define S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE 8 3190 #define V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE) 3191 #define F_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(1U) 3192 3193 #define S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE 7 3194 #define V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE) 3195 #define F_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(1U) 3196 3197 #define S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE 6 3198 #define V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE) 3199 #define F_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(1U) 3200 3201 #define S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE 5 3202 #define V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE) 3203 #define F_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(1U) 3204 3205 #define S_DEBUG_ST_FLM_IDMA0_CACHE 3 3206 #define M_DEBUG_ST_FLM_IDMA0_CACHE 0x3U 3207 #define V_DEBUG_ST_FLM_IDMA0_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CACHE) 3208 #define G_DEBUG_ST_FLM_IDMA0_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CACHE) & M_DEBUG_ST_FLM_IDMA0_CACHE) 3209 3210 #define S_DEBUG_ST_FLM_IDMA0_CTXT 0 3211 #define M_DEBUG_ST_FLM_IDMA0_CTXT 0x7U 3212 #define V_DEBUG_ST_FLM_IDMA0_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CTXT) 3213 #define G_DEBUG_ST_FLM_IDMA0_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CTXT) & M_DEBUG_ST_FLM_IDMA0_CTXT) 3214 3215 #define A_SGE_DEBUG_DATA_HIGH_INDEX_12 0x12b0 3216 3217 #define S_DEBUG_CPLSW_SOP1_CNT 28 3218 #define M_DEBUG_CPLSW_SOP1_CNT 0xfU 3219 #define V_DEBUG_CPLSW_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_SOP1_CNT) 3220 #define G_DEBUG_CPLSW_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP1_CNT) & M_DEBUG_CPLSW_SOP1_CNT) 3221 3222 #define S_DEBUG_CPLSW_EOP1_CNT 24 3223 #define M_DEBUG_CPLSW_EOP1_CNT 0xfU 3224 #define V_DEBUG_CPLSW_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_EOP1_CNT) 3225 #define G_DEBUG_CPLSW_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP1_CNT) & M_DEBUG_CPLSW_EOP1_CNT) 3226 3227 #define S_DEBUG_CPLSW_SOP0_CNT 20 3228 #define M_DEBUG_CPLSW_SOP0_CNT 0xfU 3229 #define V_DEBUG_CPLSW_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_SOP0_CNT) 3230 #define G_DEBUG_CPLSW_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP0_CNT) & M_DEBUG_CPLSW_SOP0_CNT) 3231 3232 #define S_DEBUG_CPLSW_EOP0_CNT 16 3233 #define M_DEBUG_CPLSW_EOP0_CNT 0xfU 3234 #define V_DEBUG_CPLSW_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_EOP0_CNT) 3235 #define G_DEBUG_CPLSW_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP0_CNT) & M_DEBUG_CPLSW_EOP0_CNT) 3236 3237 #define S_DEBUG_PC_RSP_SOP2_CNT 12 3238 #define M_DEBUG_PC_RSP_SOP2_CNT 0xfU 3239 #define V_DEBUG_PC_RSP_SOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP2_CNT) 3240 #define G_DEBUG_PC_RSP_SOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP2_CNT) & M_DEBUG_PC_RSP_SOP2_CNT) 3241 3242 #define S_DEBUG_PC_RSP_EOP2_CNT 8 3243 #define M_DEBUG_PC_RSP_EOP2_CNT 0xfU 3244 #define V_DEBUG_PC_RSP_EOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP2_CNT) 3245 #define G_DEBUG_PC_RSP_EOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP2_CNT) & M_DEBUG_PC_RSP_EOP2_CNT) 3246 3247 #define S_DEBUG_PC_REQ_SOP2_CNT 4 3248 #define M_DEBUG_PC_REQ_SOP2_CNT 0xfU 3249 #define V_DEBUG_PC_REQ_SOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP2_CNT) 3250 #define G_DEBUG_PC_REQ_SOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP2_CNT) & M_DEBUG_PC_REQ_SOP2_CNT) 3251 3252 #define S_DEBUG_PC_REQ_EOP2_CNT 0 3253 #define M_DEBUG_PC_REQ_EOP2_CNT 0xfU 3254 #define V_DEBUG_PC_REQ_EOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP2_CNT) 3255 #define G_DEBUG_PC_REQ_EOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP2_CNT) & M_DEBUG_PC_REQ_EOP2_CNT) 3256 3257 #define S_DEBUG_IDMA1_ISHIFT_TX_SIZE 8 3258 #define M_DEBUG_IDMA1_ISHIFT_TX_SIZE 0x7fU 3259 #define V_DEBUG_IDMA1_ISHIFT_TX_SIZE(x) ((x) << S_DEBUG_IDMA1_ISHIFT_TX_SIZE) 3260 #define G_DEBUG_IDMA1_ISHIFT_TX_SIZE(x) (((x) >> S_DEBUG_IDMA1_ISHIFT_TX_SIZE) & M_DEBUG_IDMA1_ISHIFT_TX_SIZE) 3261 3262 #define S_DEBUG_IDMA0_ISHIFT_TX_SIZE 0 3263 #define M_DEBUG_IDMA0_ISHIFT_TX_SIZE 0x7fU 3264 #define V_DEBUG_IDMA0_ISHIFT_TX_SIZE(x) ((x) << S_DEBUG_IDMA0_ISHIFT_TX_SIZE) 3265 #define G_DEBUG_IDMA0_ISHIFT_TX_SIZE(x) (((x) >> S_DEBUG_IDMA0_ISHIFT_TX_SIZE) & M_DEBUG_IDMA0_ISHIFT_TX_SIZE) 3266 3267 #define A_SGE_DEBUG_DATA_HIGH_INDEX_13 0x12b4 3268 #define A_SGE_DEBUG_DATA_HIGH_INDEX_14 0x12b8 3269 #define A_SGE_DEBUG_DATA_HIGH_INDEX_15 0x12bc 3270 #define A_SGE_DEBUG_DATA_LOW_INDEX_0 0x12c0 3271 3272 #define S_DEBUG_ST_IDMA1_FLM_REQ 29 3273 #define M_DEBUG_ST_IDMA1_FLM_REQ 0x7U 3274 #define V_DEBUG_ST_IDMA1_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA1_FLM_REQ) 3275 #define G_DEBUG_ST_IDMA1_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA1_FLM_REQ) & M_DEBUG_ST_IDMA1_FLM_REQ) 3276 3277 #define S_DEBUG_ST_IDMA0_FLM_REQ 26 3278 #define M_DEBUG_ST_IDMA0_FLM_REQ 0x7U 3279 #define V_DEBUG_ST_IDMA0_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA0_FLM_REQ) 3280 #define G_DEBUG_ST_IDMA0_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA0_FLM_REQ) & M_DEBUG_ST_IDMA0_FLM_REQ) 3281 3282 #define S_DEBUG_ST_IMSG_CTXT 23 3283 #define M_DEBUG_ST_IMSG_CTXT 0x7U 3284 #define V_DEBUG_ST_IMSG_CTXT(x) ((x) << S_DEBUG_ST_IMSG_CTXT) 3285 #define G_DEBUG_ST_IMSG_CTXT(x) (((x) >> S_DEBUG_ST_IMSG_CTXT) & M_DEBUG_ST_IMSG_CTXT) 3286 3287 #define S_DEBUG_ST_IMSG 18 3288 #define M_DEBUG_ST_IMSG 0x1fU 3289 #define V_DEBUG_ST_IMSG(x) ((x) << S_DEBUG_ST_IMSG) 3290 #define G_DEBUG_ST_IMSG(x) (((x) >> S_DEBUG_ST_IMSG) & M_DEBUG_ST_IMSG) 3291 3292 #define S_DEBUG_ST_IDMA1_IALN 16 3293 #define M_DEBUG_ST_IDMA1_IALN 0x3U 3294 #define V_DEBUG_ST_IDMA1_IALN(x) ((x) << S_DEBUG_ST_IDMA1_IALN) 3295 #define G_DEBUG_ST_IDMA1_IALN(x) (((x) >> S_DEBUG_ST_IDMA1_IALN) & M_DEBUG_ST_IDMA1_IALN) 3296 3297 #define S_DEBUG_ST_IDMA1_IDMA_SM 9 3298 #define M_DEBUG_ST_IDMA1_IDMA_SM 0x3fU 3299 #define V_DEBUG_ST_IDMA1_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA1_IDMA_SM) 3300 #define G_DEBUG_ST_IDMA1_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA1_IDMA_SM) & M_DEBUG_ST_IDMA1_IDMA_SM) 3301 3302 #define S_DEBUG_ST_IDMA0_IALN 7 3303 #define M_DEBUG_ST_IDMA0_IALN 0x3U 3304 #define V_DEBUG_ST_IDMA0_IALN(x) ((x) << S_DEBUG_ST_IDMA0_IALN) 3305 #define G_DEBUG_ST_IDMA0_IALN(x) (((x) >> S_DEBUG_ST_IDMA0_IALN) & M_DEBUG_ST_IDMA0_IALN) 3306 3307 #define S_DEBUG_ST_IDMA0_IDMA_SM 0 3308 #define M_DEBUG_ST_IDMA0_IDMA_SM 0x3fU 3309 #define V_DEBUG_ST_IDMA0_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA0_IDMA_SM) 3310 #define G_DEBUG_ST_IDMA0_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA0_IDMA_SM) & M_DEBUG_ST_IDMA0_IDMA_SM) 3311 3312 #define A_SGE_DEBUG_DATA_LOW_INDEX_1 0x12c4 3313 3314 #define S_DEBUG_ITP_EMPTY 12 3315 #define M_DEBUG_ITP_EMPTY 0x3fU 3316 #define V_DEBUG_ITP_EMPTY(x) ((x) << S_DEBUG_ITP_EMPTY) 3317 #define G_DEBUG_ITP_EMPTY(x) (((x) >> S_DEBUG_ITP_EMPTY) & M_DEBUG_ITP_EMPTY) 3318 3319 #define S_DEBUG_ITP_EXPIRED 6 3320 #define M_DEBUG_ITP_EXPIRED 0x3fU 3321 #define V_DEBUG_ITP_EXPIRED(x) ((x) << S_DEBUG_ITP_EXPIRED) 3322 #define G_DEBUG_ITP_EXPIRED(x) (((x) >> S_DEBUG_ITP_EXPIRED) & M_DEBUG_ITP_EXPIRED) 3323 3324 #define S_DEBUG_ITP_PAUSE 5 3325 #define V_DEBUG_ITP_PAUSE(x) ((x) << S_DEBUG_ITP_PAUSE) 3326 #define F_DEBUG_ITP_PAUSE V_DEBUG_ITP_PAUSE(1U) 3327 3328 #define S_DEBUG_ITP_DEL_DONE 4 3329 #define V_DEBUG_ITP_DEL_DONE(x) ((x) << S_DEBUG_ITP_DEL_DONE) 3330 #define F_DEBUG_ITP_DEL_DONE V_DEBUG_ITP_DEL_DONE(1U) 3331 3332 #define S_DEBUG_ITP_ADD_DONE 3 3333 #define V_DEBUG_ITP_ADD_DONE(x) ((x) << S_DEBUG_ITP_ADD_DONE) 3334 #define F_DEBUG_ITP_ADD_DONE V_DEBUG_ITP_ADD_DONE(1U) 3335 3336 #define S_DEBUG_ITP_EVR_STATE 0 3337 #define M_DEBUG_ITP_EVR_STATE 0x7U 3338 #define V_DEBUG_ITP_EVR_STATE(x) ((x) << S_DEBUG_ITP_EVR_STATE) 3339 #define G_DEBUG_ITP_EVR_STATE(x) (((x) >> S_DEBUG_ITP_EVR_STATE) & M_DEBUG_ITP_EVR_STATE) 3340 3341 #define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8 3342 3343 #define S_DEBUG_ST_DBP_THREAD2_CIMFL 25 3344 #define M_DEBUG_ST_DBP_THREAD2_CIMFL 0x1fU 3345 #define V_DEBUG_ST_DBP_THREAD2_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD2_CIMFL) 3346 #define G_DEBUG_ST_DBP_THREAD2_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_CIMFL) & M_DEBUG_ST_DBP_THREAD2_CIMFL) 3347 3348 #define S_DEBUG_ST_DBP_THREAD2_MAIN 20 3349 #define M_DEBUG_ST_DBP_THREAD2_MAIN 0x1fU 3350 #define V_DEBUG_ST_DBP_THREAD2_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD2_MAIN) 3351 #define G_DEBUG_ST_DBP_THREAD2_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_MAIN) & M_DEBUG_ST_DBP_THREAD2_MAIN) 3352 3353 #define S_DEBUG_ST_DBP_THREAD1_CIMFL 15 3354 #define M_DEBUG_ST_DBP_THREAD1_CIMFL 0x1fU 3355 #define V_DEBUG_ST_DBP_THREAD1_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD1_CIMFL) 3356 #define G_DEBUG_ST_DBP_THREAD1_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_CIMFL) & M_DEBUG_ST_DBP_THREAD1_CIMFL) 3357 3358 #define S_DEBUG_ST_DBP_THREAD1_MAIN 10 3359 #define M_DEBUG_ST_DBP_THREAD1_MAIN 0x1fU 3360 #define V_DEBUG_ST_DBP_THREAD1_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD1_MAIN) 3361 #define G_DEBUG_ST_DBP_THREAD1_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_MAIN) & M_DEBUG_ST_DBP_THREAD1_MAIN) 3362 3363 #define S_DEBUG_ST_DBP_THREAD0_CIMFL 5 3364 #define M_DEBUG_ST_DBP_THREAD0_CIMFL 0x1fU 3365 #define V_DEBUG_ST_DBP_THREAD0_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD0_CIMFL) 3366 #define G_DEBUG_ST_DBP_THREAD0_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_CIMFL) & M_DEBUG_ST_DBP_THREAD0_CIMFL) 3367 3368 #define S_DEBUG_ST_DBP_THREAD0_MAIN 0 3369 #define M_DEBUG_ST_DBP_THREAD0_MAIN 0x1fU 3370 #define V_DEBUG_ST_DBP_THREAD0_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD0_MAIN) 3371 #define G_DEBUG_ST_DBP_THREAD0_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_MAIN) & M_DEBUG_ST_DBP_THREAD0_MAIN) 3372 3373 #define S_T6_DEBUG_ST_DBP_UPCP_MAIN 14 3374 #define M_T6_DEBUG_ST_DBP_UPCP_MAIN 0x7U 3375 #define V_T6_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_T6_DEBUG_ST_DBP_UPCP_MAIN) 3376 #define G_T6_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_T6_DEBUG_ST_DBP_UPCP_MAIN) & M_T6_DEBUG_ST_DBP_UPCP_MAIN) 3377 3378 #define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc 3379 3380 #define S_DEBUG_ST_DBP_UPCP_MAIN 14 3381 #define M_DEBUG_ST_DBP_UPCP_MAIN 0x1fU 3382 #define V_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_DEBUG_ST_DBP_UPCP_MAIN) 3383 #define G_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_DEBUG_ST_DBP_UPCP_MAIN) & M_DEBUG_ST_DBP_UPCP_MAIN) 3384 3385 #define S_DEBUG_ST_DBP_DBFIFO_MAIN 13 3386 #define V_DEBUG_ST_DBP_DBFIFO_MAIN(x) ((x) << S_DEBUG_ST_DBP_DBFIFO_MAIN) 3387 #define F_DEBUG_ST_DBP_DBFIFO_MAIN V_DEBUG_ST_DBP_DBFIFO_MAIN(1U) 3388 3389 #define S_DEBUG_ST_DBP_CTXT 10 3390 #define M_DEBUG_ST_DBP_CTXT 0x7U 3391 #define V_DEBUG_ST_DBP_CTXT(x) ((x) << S_DEBUG_ST_DBP_CTXT) 3392 #define G_DEBUG_ST_DBP_CTXT(x) (((x) >> S_DEBUG_ST_DBP_CTXT) & M_DEBUG_ST_DBP_CTXT) 3393 3394 #define S_DEBUG_ST_DBP_THREAD3_CIMFL 5 3395 #define M_DEBUG_ST_DBP_THREAD3_CIMFL 0x1fU 3396 #define V_DEBUG_ST_DBP_THREAD3_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD3_CIMFL) 3397 #define G_DEBUG_ST_DBP_THREAD3_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_CIMFL) & M_DEBUG_ST_DBP_THREAD3_CIMFL) 3398 3399 #define S_DEBUG_ST_DBP_THREAD3_MAIN 0 3400 #define M_DEBUG_ST_DBP_THREAD3_MAIN 0x1fU 3401 #define V_DEBUG_ST_DBP_THREAD3_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD3_MAIN) 3402 #define G_DEBUG_ST_DBP_THREAD3_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_MAIN) & M_DEBUG_ST_DBP_THREAD3_MAIN) 3403 3404 #define A_SGE_DEBUG_DATA_LOW_INDEX_4 0x12d0 3405 3406 #define S_DEBUG_ST_EDMA3_ALIGN_SUB 29 3407 #define M_DEBUG_ST_EDMA3_ALIGN_SUB 0x7U 3408 #define V_DEBUG_ST_EDMA3_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN_SUB) 3409 #define G_DEBUG_ST_EDMA3_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN_SUB) & M_DEBUG_ST_EDMA3_ALIGN_SUB) 3410 3411 #define S_DEBUG_ST_EDMA3_ALIGN 27 3412 #define M_DEBUG_ST_EDMA3_ALIGN 0x3U 3413 #define V_DEBUG_ST_EDMA3_ALIGN(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN) 3414 #define G_DEBUG_ST_EDMA3_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN) & M_DEBUG_ST_EDMA3_ALIGN) 3415 3416 #define S_DEBUG_ST_EDMA3_REQ 24 3417 #define M_DEBUG_ST_EDMA3_REQ 0x7U 3418 #define V_DEBUG_ST_EDMA3_REQ(x) ((x) << S_DEBUG_ST_EDMA3_REQ) 3419 #define G_DEBUG_ST_EDMA3_REQ(x) (((x) >> S_DEBUG_ST_EDMA3_REQ) & M_DEBUG_ST_EDMA3_REQ) 3420 3421 #define S_DEBUG_ST_EDMA2_ALIGN_SUB 21 3422 #define M_DEBUG_ST_EDMA2_ALIGN_SUB 0x7U 3423 #define V_DEBUG_ST_EDMA2_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN_SUB) 3424 #define G_DEBUG_ST_EDMA2_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN_SUB) & M_DEBUG_ST_EDMA2_ALIGN_SUB) 3425 3426 #define S_DEBUG_ST_EDMA2_ALIGN 19 3427 #define M_DEBUG_ST_EDMA2_ALIGN 0x3U 3428 #define V_DEBUG_ST_EDMA2_ALIGN(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN) 3429 #define G_DEBUG_ST_EDMA2_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN) & M_DEBUG_ST_EDMA2_ALIGN) 3430 3431 #define S_DEBUG_ST_EDMA2_REQ 16 3432 #define M_DEBUG_ST_EDMA2_REQ 0x7U 3433 #define V_DEBUG_ST_EDMA2_REQ(x) ((x) << S_DEBUG_ST_EDMA2_REQ) 3434 #define G_DEBUG_ST_EDMA2_REQ(x) (((x) >> S_DEBUG_ST_EDMA2_REQ) & M_DEBUG_ST_EDMA2_REQ) 3435 3436 #define S_DEBUG_ST_EDMA1_ALIGN_SUB 13 3437 #define M_DEBUG_ST_EDMA1_ALIGN_SUB 0x7U 3438 #define V_DEBUG_ST_EDMA1_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN_SUB) 3439 #define G_DEBUG_ST_EDMA1_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN_SUB) & M_DEBUG_ST_EDMA1_ALIGN_SUB) 3440 3441 #define S_DEBUG_ST_EDMA1_ALIGN 11 3442 #define M_DEBUG_ST_EDMA1_ALIGN 0x3U 3443 #define V_DEBUG_ST_EDMA1_ALIGN(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN) 3444 #define G_DEBUG_ST_EDMA1_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN) & M_DEBUG_ST_EDMA1_ALIGN) 3445 3446 #define S_DEBUG_ST_EDMA1_REQ 8 3447 #define M_DEBUG_ST_EDMA1_REQ 0x7U 3448 #define V_DEBUG_ST_EDMA1_REQ(x) ((x) << S_DEBUG_ST_EDMA1_REQ) 3449 #define G_DEBUG_ST_EDMA1_REQ(x) (((x) >> S_DEBUG_ST_EDMA1_REQ) & M_DEBUG_ST_EDMA1_REQ) 3450 3451 #define S_DEBUG_ST_EDMA0_ALIGN_SUB 5 3452 #define M_DEBUG_ST_EDMA0_ALIGN_SUB 0x7U 3453 #define V_DEBUG_ST_EDMA0_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN_SUB) 3454 #define G_DEBUG_ST_EDMA0_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN_SUB) & M_DEBUG_ST_EDMA0_ALIGN_SUB) 3455 3456 #define S_DEBUG_ST_EDMA0_ALIGN 3 3457 #define M_DEBUG_ST_EDMA0_ALIGN 0x3U 3458 #define V_DEBUG_ST_EDMA0_ALIGN(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN) 3459 #define G_DEBUG_ST_EDMA0_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN) & M_DEBUG_ST_EDMA0_ALIGN) 3460 3461 #define S_DEBUG_ST_EDMA0_REQ 0 3462 #define M_DEBUG_ST_EDMA0_REQ 0x7U 3463 #define V_DEBUG_ST_EDMA0_REQ(x) ((x) << S_DEBUG_ST_EDMA0_REQ) 3464 #define G_DEBUG_ST_EDMA0_REQ(x) (((x) >> S_DEBUG_ST_EDMA0_REQ) & M_DEBUG_ST_EDMA0_REQ) 3465 3466 #define A_SGE_DEBUG_DATA_LOW_INDEX_5 0x12d4 3467 3468 #define S_DEBUG_ST_FLM_DBPTR 30 3469 #define M_DEBUG_ST_FLM_DBPTR 0x3U 3470 #define V_DEBUG_ST_FLM_DBPTR(x) ((x) << S_DEBUG_ST_FLM_DBPTR) 3471 #define G_DEBUG_ST_FLM_DBPTR(x) (((x) >> S_DEBUG_ST_FLM_DBPTR) & M_DEBUG_ST_FLM_DBPTR) 3472 3473 #define S_DEBUG_FLM_CACHE_LOCKED_COUNT 23 3474 #define M_DEBUG_FLM_CACHE_LOCKED_COUNT 0x7fU 3475 #define V_DEBUG_FLM_CACHE_LOCKED_COUNT(x) ((x) << S_DEBUG_FLM_CACHE_LOCKED_COUNT) 3476 #define G_DEBUG_FLM_CACHE_LOCKED_COUNT(x) (((x) >> S_DEBUG_FLM_CACHE_LOCKED_COUNT) & M_DEBUG_FLM_CACHE_LOCKED_COUNT) 3477 3478 #define S_DEBUG_FLM_CACHE_AGENT 20 3479 #define M_DEBUG_FLM_CACHE_AGENT 0x7U 3480 #define V_DEBUG_FLM_CACHE_AGENT(x) ((x) << S_DEBUG_FLM_CACHE_AGENT) 3481 #define G_DEBUG_FLM_CACHE_AGENT(x) (((x) >> S_DEBUG_FLM_CACHE_AGENT) & M_DEBUG_FLM_CACHE_AGENT) 3482 3483 #define S_DEBUG_ST_FLM_CACHE 16 3484 #define M_DEBUG_ST_FLM_CACHE 0xfU 3485 #define V_DEBUG_ST_FLM_CACHE(x) ((x) << S_DEBUG_ST_FLM_CACHE) 3486 #define G_DEBUG_ST_FLM_CACHE(x) (((x) >> S_DEBUG_ST_FLM_CACHE) & M_DEBUG_ST_FLM_CACHE) 3487 3488 #define S_DEBUG_FLM_DBPTR_CIDX_STALL 12 3489 #define V_DEBUG_FLM_DBPTR_CIDX_STALL(x) ((x) << S_DEBUG_FLM_DBPTR_CIDX_STALL) 3490 #define F_DEBUG_FLM_DBPTR_CIDX_STALL V_DEBUG_FLM_DBPTR_CIDX_STALL(1U) 3491 3492 #define S_DEBUG_FLM_DBPTR_QID 0 3493 #define M_DEBUG_FLM_DBPTR_QID 0xfffU 3494 #define V_DEBUG_FLM_DBPTR_QID(x) ((x) << S_DEBUG_FLM_DBPTR_QID) 3495 #define G_DEBUG_FLM_DBPTR_QID(x) (((x) >> S_DEBUG_FLM_DBPTR_QID) & M_DEBUG_FLM_DBPTR_QID) 3496 3497 #define A_SGE_DEBUG0_DBP_THREAD 0x12d4 3498 3499 #define S_THREAD_ST_MAIN 25 3500 #define M_THREAD_ST_MAIN 0x3fU 3501 #define V_THREAD_ST_MAIN(x) ((x) << S_THREAD_ST_MAIN) 3502 #define G_THREAD_ST_MAIN(x) (((x) >> S_THREAD_ST_MAIN) & M_THREAD_ST_MAIN) 3503 3504 #define S_THREAD_ST_CIMFL 21 3505 #define M_THREAD_ST_CIMFL 0xfU 3506 #define V_THREAD_ST_CIMFL(x) ((x) << S_THREAD_ST_CIMFL) 3507 #define G_THREAD_ST_CIMFL(x) (((x) >> S_THREAD_ST_CIMFL) & M_THREAD_ST_CIMFL) 3508 3509 #define S_THREAD_CMDOP 17 3510 #define M_THREAD_CMDOP 0xfU 3511 #define V_THREAD_CMDOP(x) ((x) << S_THREAD_CMDOP) 3512 #define G_THREAD_CMDOP(x) (((x) >> S_THREAD_CMDOP) & M_THREAD_CMDOP) 3513 3514 #define S_THREAD_QID 0 3515 #define M_THREAD_QID 0x1ffffU 3516 #define V_THREAD_QID(x) ((x) << S_THREAD_QID) 3517 #define G_THREAD_QID(x) (((x) >> S_THREAD_QID) & M_THREAD_QID) 3518 3519 #define A_SGE_DEBUG_DATA_LOW_INDEX_6 0x12d8 3520 3521 #define S_DEBUG_DBP_THREAD0_QID 0 3522 #define M_DEBUG_DBP_THREAD0_QID 0x1ffffU 3523 #define V_DEBUG_DBP_THREAD0_QID(x) ((x) << S_DEBUG_DBP_THREAD0_QID) 3524 #define G_DEBUG_DBP_THREAD0_QID(x) (((x) >> S_DEBUG_DBP_THREAD0_QID) & M_DEBUG_DBP_THREAD0_QID) 3525 3526 #define A_SGE_DEBUG_DATA_LOW_INDEX_7 0x12dc 3527 3528 #define S_DEBUG_DBP_THREAD1_QID 0 3529 #define M_DEBUG_DBP_THREAD1_QID 0x1ffffU 3530 #define V_DEBUG_DBP_THREAD1_QID(x) ((x) << S_DEBUG_DBP_THREAD1_QID) 3531 #define G_DEBUG_DBP_THREAD1_QID(x) (((x) >> S_DEBUG_DBP_THREAD1_QID) & M_DEBUG_DBP_THREAD1_QID) 3532 3533 #define A_SGE_DEBUG_DATA_LOW_INDEX_8 0x12e0 3534 3535 #define S_DEBUG_DBP_THREAD2_QID 0 3536 #define M_DEBUG_DBP_THREAD2_QID 0x1ffffU 3537 #define V_DEBUG_DBP_THREAD2_QID(x) ((x) << S_DEBUG_DBP_THREAD2_QID) 3538 #define G_DEBUG_DBP_THREAD2_QID(x) (((x) >> S_DEBUG_DBP_THREAD2_QID) & M_DEBUG_DBP_THREAD2_QID) 3539 3540 #define A_SGE_DEBUG_DATA_LOW_INDEX_9 0x12e4 3541 3542 #define S_DEBUG_DBP_THREAD3_QID 0 3543 #define M_DEBUG_DBP_THREAD3_QID 0x1ffffU 3544 #define V_DEBUG_DBP_THREAD3_QID(x) ((x) << S_DEBUG_DBP_THREAD3_QID) 3545 #define G_DEBUG_DBP_THREAD3_QID(x) (((x) >> S_DEBUG_DBP_THREAD3_QID) & M_DEBUG_DBP_THREAD3_QID) 3546 3547 #define A_SGE_DEBUG_DATA_LOW_INDEX_10 0x12e8 3548 3549 #define S_DEBUG_IMSG_CPL 16 3550 #define M_DEBUG_IMSG_CPL 0xffU 3551 #define V_DEBUG_IMSG_CPL(x) ((x) << S_DEBUG_IMSG_CPL) 3552 #define G_DEBUG_IMSG_CPL(x) (((x) >> S_DEBUG_IMSG_CPL) & M_DEBUG_IMSG_CPL) 3553 3554 #define S_DEBUG_IMSG_QID 0 3555 #define M_DEBUG_IMSG_QID 0xffffU 3556 #define V_DEBUG_IMSG_QID(x) ((x) << S_DEBUG_IMSG_QID) 3557 #define G_DEBUG_IMSG_QID(x) (((x) >> S_DEBUG_IMSG_QID) & M_DEBUG_IMSG_QID) 3558 3559 #define A_SGE_DEBUG_DATA_LOW_INDEX_11 0x12ec 3560 3561 #define S_DEBUG_IDMA1_QID 16 3562 #define M_DEBUG_IDMA1_QID 0xffffU 3563 #define V_DEBUG_IDMA1_QID(x) ((x) << S_DEBUG_IDMA1_QID) 3564 #define G_DEBUG_IDMA1_QID(x) (((x) >> S_DEBUG_IDMA1_QID) & M_DEBUG_IDMA1_QID) 3565 3566 #define S_DEBUG_IDMA0_QID 0 3567 #define M_DEBUG_IDMA0_QID 0xffffU 3568 #define V_DEBUG_IDMA0_QID(x) ((x) << S_DEBUG_IDMA0_QID) 3569 #define G_DEBUG_IDMA0_QID(x) (((x) >> S_DEBUG_IDMA0_QID) & M_DEBUG_IDMA0_QID) 3570 3571 #define A_SGE_DEBUG_DATA_LOW_INDEX_12 0x12f0 3572 3573 #define S_DEBUG_IDMA1_FLM_REQ_QID 16 3574 #define M_DEBUG_IDMA1_FLM_REQ_QID 0xffffU 3575 #define V_DEBUG_IDMA1_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA1_FLM_REQ_QID) 3576 #define G_DEBUG_IDMA1_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA1_FLM_REQ_QID) & M_DEBUG_IDMA1_FLM_REQ_QID) 3577 3578 #define S_DEBUG_IDMA0_FLM_REQ_QID 0 3579 #define M_DEBUG_IDMA0_FLM_REQ_QID 0xffffU 3580 #define V_DEBUG_IDMA0_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA0_FLM_REQ_QID) 3581 #define G_DEBUG_IDMA0_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA0_FLM_REQ_QID) & M_DEBUG_IDMA0_FLM_REQ_QID) 3582 3583 #define A_SGE_DEBUG_DATA_LOW_INDEX_13 0x12f4 3584 #define A_SGE_DEBUG_DATA_LOW_INDEX_14 0x12f8 3585 #define A_SGE_DEBUG_DATA_LOW_INDEX_15 0x12fc 3586 #define A_SGE_WC_EGRS_BAR2_OFF_PF 0x1300 3587 3588 #define S_PFIQSPERPAGE 28 3589 #define M_PFIQSPERPAGE 0xfU 3590 #define V_PFIQSPERPAGE(x) ((x) << S_PFIQSPERPAGE) 3591 #define G_PFIQSPERPAGE(x) (((x) >> S_PFIQSPERPAGE) & M_PFIQSPERPAGE) 3592 3593 #define S_PFEQSPERPAGE 24 3594 #define M_PFEQSPERPAGE 0xfU 3595 #define V_PFEQSPERPAGE(x) ((x) << S_PFEQSPERPAGE) 3596 #define G_PFEQSPERPAGE(x) (((x) >> S_PFEQSPERPAGE) & M_PFEQSPERPAGE) 3597 3598 #define S_PFWCQSPERPAGE 20 3599 #define M_PFWCQSPERPAGE 0xfU 3600 #define V_PFWCQSPERPAGE(x) ((x) << S_PFWCQSPERPAGE) 3601 #define G_PFWCQSPERPAGE(x) (((x) >> S_PFWCQSPERPAGE) & M_PFWCQSPERPAGE) 3602 3603 #define S_PFWCOFFEN 19 3604 #define V_PFWCOFFEN(x) ((x) << S_PFWCOFFEN) 3605 #define F_PFWCOFFEN V_PFWCOFFEN(1U) 3606 3607 #define S_PFMAXWCSIZE 17 3608 #define M_PFMAXWCSIZE 0x3U 3609 #define V_PFMAXWCSIZE(x) ((x) << S_PFMAXWCSIZE) 3610 #define G_PFMAXWCSIZE(x) (((x) >> S_PFMAXWCSIZE) & M_PFMAXWCSIZE) 3611 3612 #define S_PFWCOFFSET 0 3613 #define M_PFWCOFFSET 0x1ffffU 3614 #define V_PFWCOFFSET(x) ((x) << S_PFWCOFFSET) 3615 #define G_PFWCOFFSET(x) (((x) >> S_PFWCOFFSET) & M_PFWCOFFSET) 3616 3617 #define A_SGE_WC_EGRS_BAR2_OFF_VF 0x1320 3618 3619 #define S_VFIQSPERPAGE 28 3620 #define M_VFIQSPERPAGE 0xfU 3621 #define V_VFIQSPERPAGE(x) ((x) << S_VFIQSPERPAGE) 3622 #define G_VFIQSPERPAGE(x) (((x) >> S_VFIQSPERPAGE) & M_VFIQSPERPAGE) 3623 3624 #define S_VFEQSPERPAGE 24 3625 #define M_VFEQSPERPAGE 0xfU 3626 #define V_VFEQSPERPAGE(x) ((x) << S_VFEQSPERPAGE) 3627 #define G_VFEQSPERPAGE(x) (((x) >> S_VFEQSPERPAGE) & M_VFEQSPERPAGE) 3628 3629 #define S_VFWCQSPERPAGE 20 3630 #define M_VFWCQSPERPAGE 0xfU 3631 #define V_VFWCQSPERPAGE(x) ((x) << S_VFWCQSPERPAGE) 3632 #define G_VFWCQSPERPAGE(x) (((x) >> S_VFWCQSPERPAGE) & M_VFWCQSPERPAGE) 3633 3634 #define S_VFWCOFFEN 19 3635 #define V_VFWCOFFEN(x) ((x) << S_VFWCOFFEN) 3636 #define F_VFWCOFFEN V_VFWCOFFEN(1U) 3637 3638 #define S_VFMAXWCSIZE 17 3639 #define M_VFMAXWCSIZE 0x3U 3640 #define V_VFMAXWCSIZE(x) ((x) << S_VFMAXWCSIZE) 3641 #define G_VFMAXWCSIZE(x) (((x) >> S_VFMAXWCSIZE) & M_VFMAXWCSIZE) 3642 3643 #define S_VFWCOFFSET 0 3644 #define M_VFWCOFFSET 0x1ffffU 3645 #define V_VFWCOFFSET(x) ((x) << S_VFWCOFFSET) 3646 #define G_VFWCOFFSET(x) (((x) >> S_VFWCOFFSET) & M_VFWCOFFSET) 3647 3648 #define A_SGE_LA_RDPTR_0 0x1800 3649 #define A_SGE_LA_RDDATA_0 0x1804 3650 #define A_SGE_LA_WRPTR_0 0x1808 3651 #define A_SGE_LA_RESERVED_0 0x180c 3652 #define A_SGE_LA_RDPTR_1 0x1810 3653 #define A_SGE_LA_RDDATA_1 0x1814 3654 #define A_SGE_LA_WRPTR_1 0x1818 3655 #define A_SGE_LA_RESERVED_1 0x181c 3656 #define A_SGE_LA_RDPTR_2 0x1820 3657 #define A_SGE_LA_RDDATA_2 0x1824 3658 #define A_SGE_LA_WRPTR_2 0x1828 3659 #define A_SGE_LA_RESERVED_2 0x182c 3660 #define A_SGE_LA_RDPTR_3 0x1830 3661 #define A_SGE_LA_RDDATA_3 0x1834 3662 #define A_SGE_LA_WRPTR_3 0x1838 3663 #define A_SGE_LA_RESERVED_3 0x183c 3664 #define A_SGE_LA_RDPTR_4 0x1840 3665 #define A_SGE_LA_RDDATA_4 0x1844 3666 #define A_SGE_LA_WRPTR_4 0x1848 3667 #define A_SGE_LA_RESERVED_4 0x184c 3668 #define A_SGE_LA_RDPTR_5 0x1850 3669 #define A_SGE_LA_RDDATA_5 0x1854 3670 #define A_SGE_LA_WRPTR_5 0x1858 3671 #define A_SGE_LA_RESERVED_5 0x185c 3672 #define A_SGE_LA_RDPTR_6 0x1860 3673 #define A_SGE_LA_RDDATA_6 0x1864 3674 #define A_SGE_LA_WRPTR_6 0x1868 3675 #define A_SGE_LA_RESERVED_6 0x186c 3676 #define A_SGE_LA_RDPTR_7 0x1870 3677 #define A_SGE_LA_RDDATA_7 0x1874 3678 #define A_SGE_LA_WRPTR_7 0x1878 3679 #define A_SGE_LA_RESERVED_7 0x187c 3680 #define A_SGE_LA_RDPTR_8 0x1880 3681 #define A_SGE_LA_RDDATA_8 0x1884 3682 #define A_SGE_LA_WRPTR_8 0x1888 3683 #define A_SGE_LA_RESERVED_8 0x188c 3684 #define A_SGE_LA_RDPTR_9 0x1890 3685 #define A_SGE_LA_RDDATA_9 0x1894 3686 #define A_SGE_LA_WRPTR_9 0x1898 3687 #define A_SGE_LA_RESERVED_9 0x189c 3688 #define A_SGE_LA_RDPTR_10 0x18a0 3689 #define A_SGE_LA_RDDATA_10 0x18a4 3690 #define A_SGE_LA_WRPTR_10 0x18a8 3691 #define A_SGE_LA_RESERVED_10 0x18ac 3692 #define A_SGE_LA_RDPTR_11 0x18b0 3693 #define A_SGE_LA_RDDATA_11 0x18b4 3694 #define A_SGE_LA_WRPTR_11 0x18b8 3695 #define A_SGE_LA_RESERVED_11 0x18bc 3696 #define A_SGE_LA_RDPTR_12 0x18c0 3697 #define A_SGE_LA_RDDATA_12 0x18c4 3698 #define A_SGE_LA_WRPTR_12 0x18c8 3699 #define A_SGE_LA_RESERVED_12 0x18cc 3700 #define A_SGE_LA_RDPTR_13 0x18d0 3701 #define A_SGE_LA_RDDATA_13 0x18d4 3702 #define A_SGE_LA_WRPTR_13 0x18d8 3703 #define A_SGE_LA_RESERVED_13 0x18dc 3704 #define A_SGE_LA_RDPTR_14 0x18e0 3705 #define A_SGE_LA_RDDATA_14 0x18e4 3706 #define A_SGE_LA_WRPTR_14 0x18e8 3707 #define A_SGE_LA_RESERVED_14 0x18ec 3708 #define A_SGE_LA_RDPTR_15 0x18f0 3709 #define A_SGE_LA_RDDATA_15 0x18f4 3710 #define A_SGE_LA_WRPTR_15 0x18f8 3711 #define A_SGE_LA_RESERVED_15 0x18fc 3712 3713 /* registers for module PCIE */ 3714 #define PCIE_BASE_ADDR 0x3000 3715 3716 #define A_PCIE_PF_CFG 0x40 3717 3718 #define S_AIVEC 4 3719 #define M_AIVEC 0x3ffU 3720 #define V_AIVEC(x) ((x) << S_AIVEC) 3721 #define G_AIVEC(x) (((x) >> S_AIVEC) & M_AIVEC) 3722 3723 #define A_PCIE_PF_CLI 0x44 3724 #define A_PCIE_PF_EXPROM_OFST 0x4c 3725 3726 #define S_OFFSET 10 3727 #define M_OFFSET 0x3fffU 3728 #define V_OFFSET(x) ((x) << S_OFFSET) 3729 #define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET) 3730 3731 #define A_PCIE_INT_CAUSE 0x3004 3732 3733 #define S_NONFATALERR 30 3734 #define V_NONFATALERR(x) ((x) << S_NONFATALERR) 3735 #define F_NONFATALERR V_NONFATALERR(1U) 3736 3737 #define S_UNXSPLCPLERR 29 3738 #define V_UNXSPLCPLERR(x) ((x) << S_UNXSPLCPLERR) 3739 #define F_UNXSPLCPLERR V_UNXSPLCPLERR(1U) 3740 3741 #define S_PCIEPINT 28 3742 #define V_PCIEPINT(x) ((x) << S_PCIEPINT) 3743 #define F_PCIEPINT V_PCIEPINT(1U) 3744 3745 #define S_PCIESINT 27 3746 #define V_PCIESINT(x) ((x) << S_PCIESINT) 3747 #define F_PCIESINT V_PCIESINT(1U) 3748 3749 #define S_RPLPERR 26 3750 #define V_RPLPERR(x) ((x) << S_RPLPERR) 3751 #define F_RPLPERR V_RPLPERR(1U) 3752 3753 #define S_RXWRPERR 25 3754 #define V_RXWRPERR(x) ((x) << S_RXWRPERR) 3755 #define F_RXWRPERR V_RXWRPERR(1U) 3756 3757 #define S_RXCPLPERR 24 3758 #define V_RXCPLPERR(x) ((x) << S_RXCPLPERR) 3759 #define F_RXCPLPERR V_RXCPLPERR(1U) 3760 3761 #define S_PIOTAGPERR 23 3762 #define V_PIOTAGPERR(x) ((x) << S_PIOTAGPERR) 3763 #define F_PIOTAGPERR V_PIOTAGPERR(1U) 3764 3765 #define S_MATAGPERR 22 3766 #define V_MATAGPERR(x) ((x) << S_MATAGPERR) 3767 #define F_MATAGPERR V_MATAGPERR(1U) 3768 3769 #define S_INTXCLRPERR 21 3770 #define V_INTXCLRPERR(x) ((x) << S_INTXCLRPERR) 3771 #define F_INTXCLRPERR V_INTXCLRPERR(1U) 3772 3773 #define S_FIDPERR 20 3774 #define V_FIDPERR(x) ((x) << S_FIDPERR) 3775 #define F_FIDPERR V_FIDPERR(1U) 3776 3777 #define S_CFGSNPPERR 19 3778 #define V_CFGSNPPERR(x) ((x) << S_CFGSNPPERR) 3779 #define F_CFGSNPPERR V_CFGSNPPERR(1U) 3780 3781 #define S_HRSPPERR 18 3782 #define V_HRSPPERR(x) ((x) << S_HRSPPERR) 3783 #define F_HRSPPERR V_HRSPPERR(1U) 3784 3785 #define S_HREQPERR 17 3786 #define V_HREQPERR(x) ((x) << S_HREQPERR) 3787 #define F_HREQPERR V_HREQPERR(1U) 3788 3789 #define S_HCNTPERR 16 3790 #define V_HCNTPERR(x) ((x) << S_HCNTPERR) 3791 #define F_HCNTPERR V_HCNTPERR(1U) 3792 3793 #define S_DRSPPERR 15 3794 #define V_DRSPPERR(x) ((x) << S_DRSPPERR) 3795 #define F_DRSPPERR V_DRSPPERR(1U) 3796 3797 #define S_DREQPERR 14 3798 #define V_DREQPERR(x) ((x) << S_DREQPERR) 3799 #define F_DREQPERR V_DREQPERR(1U) 3800 3801 #define S_DCNTPERR 13 3802 #define V_DCNTPERR(x) ((x) << S_DCNTPERR) 3803 #define F_DCNTPERR V_DCNTPERR(1U) 3804 3805 #define S_CRSPPERR 12 3806 #define V_CRSPPERR(x) ((x) << S_CRSPPERR) 3807 #define F_CRSPPERR V_CRSPPERR(1U) 3808 3809 #define S_CREQPERR 11 3810 #define V_CREQPERR(x) ((x) << S_CREQPERR) 3811 #define F_CREQPERR V_CREQPERR(1U) 3812 3813 #define S_CCNTPERR 10 3814 #define V_CCNTPERR(x) ((x) << S_CCNTPERR) 3815 #define F_CCNTPERR V_CCNTPERR(1U) 3816 3817 #define S_TARTAGPERR 9 3818 #define V_TARTAGPERR(x) ((x) << S_TARTAGPERR) 3819 #define F_TARTAGPERR V_TARTAGPERR(1U) 3820 3821 #define S_PIOREQPERR 8 3822 #define V_PIOREQPERR(x) ((x) << S_PIOREQPERR) 3823 #define F_PIOREQPERR V_PIOREQPERR(1U) 3824 3825 #define S_PIOCPLPERR 7 3826 #define V_PIOCPLPERR(x) ((x) << S_PIOCPLPERR) 3827 #define F_PIOCPLPERR V_PIOCPLPERR(1U) 3828 3829 #define S_MSIXDIPERR 6 3830 #define V_MSIXDIPERR(x) ((x) << S_MSIXDIPERR) 3831 #define F_MSIXDIPERR V_MSIXDIPERR(1U) 3832 3833 #define S_MSIXDATAPERR 5 3834 #define V_MSIXDATAPERR(x) ((x) << S_MSIXDATAPERR) 3835 #define F_MSIXDATAPERR V_MSIXDATAPERR(1U) 3836 3837 #define S_MSIXADDRHPERR 4 3838 #define V_MSIXADDRHPERR(x) ((x) << S_MSIXADDRHPERR) 3839 #define F_MSIXADDRHPERR V_MSIXADDRHPERR(1U) 3840 3841 #define S_MSIXADDRLPERR 3 3842 #define V_MSIXADDRLPERR(x) ((x) << S_MSIXADDRLPERR) 3843 #define F_MSIXADDRLPERR V_MSIXADDRLPERR(1U) 3844 3845 #define S_MSIDATAPERR 2 3846 #define V_MSIDATAPERR(x) ((x) << S_MSIDATAPERR) 3847 #define F_MSIDATAPERR V_MSIDATAPERR(1U) 3848 3849 #define S_MSIADDRHPERR 1 3850 #define V_MSIADDRHPERR(x) ((x) << S_MSIADDRHPERR) 3851 #define F_MSIADDRHPERR V_MSIADDRHPERR(1U) 3852 3853 #define S_MSIADDRLPERR 0 3854 #define V_MSIADDRLPERR(x) ((x) << S_MSIADDRLPERR) 3855 #define F_MSIADDRLPERR V_MSIADDRLPERR(1U) 3856 3857 #define S_IPGRPPERR 31 3858 #define V_IPGRPPERR(x) ((x) << S_IPGRPPERR) 3859 #define F_IPGRPPERR V_IPGRPPERR(1U) 3860 3861 #define S_READRSPERR 29 3862 #define V_READRSPERR(x) ((x) << S_READRSPERR) 3863 #define F_READRSPERR V_READRSPERR(1U) 3864 3865 #define S_TRGT1GRPPERR 28 3866 #define V_TRGT1GRPPERR(x) ((x) << S_TRGT1GRPPERR) 3867 #define F_TRGT1GRPPERR V_TRGT1GRPPERR(1U) 3868 3869 #define S_IPSOTPERR 27 3870 #define V_IPSOTPERR(x) ((x) << S_IPSOTPERR) 3871 #define F_IPSOTPERR V_IPSOTPERR(1U) 3872 3873 #define S_IPRETRYPERR 26 3874 #define V_IPRETRYPERR(x) ((x) << S_IPRETRYPERR) 3875 #define F_IPRETRYPERR V_IPRETRYPERR(1U) 3876 3877 #define S_IPRXDATAGRPPERR 25 3878 #define V_IPRXDATAGRPPERR(x) ((x) << S_IPRXDATAGRPPERR) 3879 #define F_IPRXDATAGRPPERR V_IPRXDATAGRPPERR(1U) 3880 3881 #define S_IPRXHDRGRPPERR 24 3882 #define V_IPRXHDRGRPPERR(x) ((x) << S_IPRXHDRGRPPERR) 3883 #define F_IPRXHDRGRPPERR V_IPRXHDRGRPPERR(1U) 3884 3885 #define S_PIOTAGQPERR 23 3886 #define V_PIOTAGQPERR(x) ((x) << S_PIOTAGQPERR) 3887 #define F_PIOTAGQPERR V_PIOTAGQPERR(1U) 3888 3889 #define S_MAGRPPERR 22 3890 #define V_MAGRPPERR(x) ((x) << S_MAGRPPERR) 3891 #define F_MAGRPPERR V_MAGRPPERR(1U) 3892 3893 #define S_VFIDPERR 21 3894 #define V_VFIDPERR(x) ((x) << S_VFIDPERR) 3895 #define F_VFIDPERR V_VFIDPERR(1U) 3896 3897 #define S_HREQRDPERR 17 3898 #define V_HREQRDPERR(x) ((x) << S_HREQRDPERR) 3899 #define F_HREQRDPERR V_HREQRDPERR(1U) 3900 3901 #define S_HREQWRPERR 16 3902 #define V_HREQWRPERR(x) ((x) << S_HREQWRPERR) 3903 #define F_HREQWRPERR V_HREQWRPERR(1U) 3904 3905 #define S_DREQRDPERR 14 3906 #define V_DREQRDPERR(x) ((x) << S_DREQRDPERR) 3907 #define F_DREQRDPERR V_DREQRDPERR(1U) 3908 3909 #define S_DREQWRPERR 13 3910 #define V_DREQWRPERR(x) ((x) << S_DREQWRPERR) 3911 #define F_DREQWRPERR V_DREQWRPERR(1U) 3912 3913 #define S_CREQRDPERR 11 3914 #define V_CREQRDPERR(x) ((x) << S_CREQRDPERR) 3915 #define F_CREQRDPERR V_CREQRDPERR(1U) 3916 3917 #define S_MSTTAGQPERR 10 3918 #define V_MSTTAGQPERR(x) ((x) << S_MSTTAGQPERR) 3919 #define F_MSTTAGQPERR V_MSTTAGQPERR(1U) 3920 3921 #define S_TGTTAGQPERR 9 3922 #define V_TGTTAGQPERR(x) ((x) << S_TGTTAGQPERR) 3923 #define F_TGTTAGQPERR V_TGTTAGQPERR(1U) 3924 3925 #define S_PIOREQGRPPERR 8 3926 #define V_PIOREQGRPPERR(x) ((x) << S_PIOREQGRPPERR) 3927 #define F_PIOREQGRPPERR V_PIOREQGRPPERR(1U) 3928 3929 #define S_PIOCPLGRPPERR 7 3930 #define V_PIOCPLGRPPERR(x) ((x) << S_PIOCPLGRPPERR) 3931 #define F_PIOCPLGRPPERR V_PIOCPLGRPPERR(1U) 3932 3933 #define S_MSIXSTIPERR 2 3934 #define V_MSIXSTIPERR(x) ((x) << S_MSIXSTIPERR) 3935 #define F_MSIXSTIPERR V_MSIXSTIPERR(1U) 3936 3937 #define S_MSTTIMEOUTPERR 1 3938 #define V_MSTTIMEOUTPERR(x) ((x) << S_MSTTIMEOUTPERR) 3939 #define F_MSTTIMEOUTPERR V_MSTTIMEOUTPERR(1U) 3940 3941 #define S_MSTGRPPERR 0 3942 #define V_MSTGRPPERR(x) ((x) << S_MSTGRPPERR) 3943 #define F_MSTGRPPERR V_MSTGRPPERR(1U) 3944 3945 #define A_PCIE_NONFAT_ERR 0x3010 3946 3947 #define S_RDRSPERR 9 3948 #define V_RDRSPERR(x) ((x) << S_RDRSPERR) 3949 #define F_RDRSPERR V_RDRSPERR(1U) 3950 3951 #define S_VPDRSPERR 8 3952 #define V_VPDRSPERR(x) ((x) << S_VPDRSPERR) 3953 #define F_VPDRSPERR V_VPDRSPERR(1U) 3954 3955 #define S_POPD 7 3956 #define V_POPD(x) ((x) << S_POPD) 3957 #define F_POPD V_POPD(1U) 3958 3959 #define S_POPH 6 3960 #define V_POPH(x) ((x) << S_POPH) 3961 #define F_POPH V_POPH(1U) 3962 3963 #define S_POPC 5 3964 #define V_POPC(x) ((x) << S_POPC) 3965 #define F_POPC V_POPC(1U) 3966 3967 #define S_MEMREQ 4 3968 #define V_MEMREQ(x) ((x) << S_MEMREQ) 3969 #define F_MEMREQ V_MEMREQ(1U) 3970 3971 #define S_PIOREQ 3 3972 #define V_PIOREQ(x) ((x) << S_PIOREQ) 3973 #define F_PIOREQ V_PIOREQ(1U) 3974 3975 #define S_TAGDROP 2 3976 #define V_TAGDROP(x) ((x) << S_TAGDROP) 3977 #define F_TAGDROP V_TAGDROP(1U) 3978 3979 #define S_TAGCPL 1 3980 #define V_TAGCPL(x) ((x) << S_TAGCPL) 3981 #define F_TAGCPL V_TAGCPL(1U) 3982 3983 #define S_CFGSNP 0 3984 #define V_CFGSNP(x) ((x) << S_CFGSNP) 3985 #define F_CFGSNP V_CFGSNP(1U) 3986 3987 #define S_MAREQTIMEOUT 29 3988 #define V_MAREQTIMEOUT(x) ((x) << S_MAREQTIMEOUT) 3989 #define F_MAREQTIMEOUT V_MAREQTIMEOUT(1U) 3990 3991 #define S_TRGT1BARTYPEERR 28 3992 #define V_TRGT1BARTYPEERR(x) ((x) << S_TRGT1BARTYPEERR) 3993 #define F_TRGT1BARTYPEERR V_TRGT1BARTYPEERR(1U) 3994 3995 #define S_MAEXTRARSPERR 27 3996 #define V_MAEXTRARSPERR(x) ((x) << S_MAEXTRARSPERR) 3997 #define F_MAEXTRARSPERR V_MAEXTRARSPERR(1U) 3998 3999 #define S_MARSPTIMEOUT 26 4000 #define V_MARSPTIMEOUT(x) ((x) << S_MARSPTIMEOUT) 4001 #define F_MARSPTIMEOUT V_MARSPTIMEOUT(1U) 4002 4003 #define S_INTVFALLMSIDISERR 25 4004 #define V_INTVFALLMSIDISERR(x) ((x) << S_INTVFALLMSIDISERR) 4005 #define F_INTVFALLMSIDISERR V_INTVFALLMSIDISERR(1U) 4006 4007 #define S_INTVFRANGEERR 24 4008 #define V_INTVFRANGEERR(x) ((x) << S_INTVFRANGEERR) 4009 #define F_INTVFRANGEERR V_INTVFRANGEERR(1U) 4010 4011 #define S_INTPLIRSPERR 23 4012 #define V_INTPLIRSPERR(x) ((x) << S_INTPLIRSPERR) 4013 #define F_INTPLIRSPERR V_INTPLIRSPERR(1U) 4014 4015 #define S_MEMREQRDTAGERR 22 4016 #define V_MEMREQRDTAGERR(x) ((x) << S_MEMREQRDTAGERR) 4017 #define F_MEMREQRDTAGERR V_MEMREQRDTAGERR(1U) 4018 4019 #define S_CFGINITDONEERR 21 4020 #define V_CFGINITDONEERR(x) ((x) << S_CFGINITDONEERR) 4021 #define F_CFGINITDONEERR V_CFGINITDONEERR(1U) 4022 4023 #define S_BAR2TIMEOUT 20 4024 #define V_BAR2TIMEOUT(x) ((x) << S_BAR2TIMEOUT) 4025 #define F_BAR2TIMEOUT V_BAR2TIMEOUT(1U) 4026 4027 #define S_VPDTIMEOUT 19 4028 #define V_VPDTIMEOUT(x) ((x) << S_VPDTIMEOUT) 4029 #define F_VPDTIMEOUT V_VPDTIMEOUT(1U) 4030 4031 #define S_MEMRSPRDTAGERR 18 4032 #define V_MEMRSPRDTAGERR(x) ((x) << S_MEMRSPRDTAGERR) 4033 #define F_MEMRSPRDTAGERR V_MEMRSPRDTAGERR(1U) 4034 4035 #define S_MEMRSPWRTAGERR 17 4036 #define V_MEMRSPWRTAGERR(x) ((x) << S_MEMRSPWRTAGERR) 4037 #define F_MEMRSPWRTAGERR V_MEMRSPWRTAGERR(1U) 4038 4039 #define S_PIORSPRDTAGERR 16 4040 #define V_PIORSPRDTAGERR(x) ((x) << S_PIORSPRDTAGERR) 4041 #define F_PIORSPRDTAGERR V_PIORSPRDTAGERR(1U) 4042 4043 #define S_PIORSPWRTAGERR 15 4044 #define V_PIORSPWRTAGERR(x) ((x) << S_PIORSPWRTAGERR) 4045 #define F_PIORSPWRTAGERR V_PIORSPWRTAGERR(1U) 4046 4047 #define S_DBITIMEOUT 14 4048 #define V_DBITIMEOUT(x) ((x) << S_DBITIMEOUT) 4049 #define F_DBITIMEOUT V_DBITIMEOUT(1U) 4050 4051 #define S_PIOUNALINDWR 13 4052 #define V_PIOUNALINDWR(x) ((x) << S_PIOUNALINDWR) 4053 #define F_PIOUNALINDWR V_PIOUNALINDWR(1U) 4054 4055 #define S_BAR2RDERR 12 4056 #define V_BAR2RDERR(x) ((x) << S_BAR2RDERR) 4057 #define F_BAR2RDERR V_BAR2RDERR(1U) 4058 4059 #define S_MAWREOPERR 11 4060 #define V_MAWREOPERR(x) ((x) << S_MAWREOPERR) 4061 #define F_MAWREOPERR V_MAWREOPERR(1U) 4062 4063 #define S_MARDEOPERR 10 4064 #define V_MARDEOPERR(x) ((x) << S_MARDEOPERR) 4065 #define F_MARDEOPERR V_MARDEOPERR(1U) 4066 4067 #define S_BAR2REQ 2 4068 #define V_BAR2REQ(x) ((x) << S_BAR2REQ) 4069 #define F_BAR2REQ V_BAR2REQ(1U) 4070 4071 #define S_MARSPUE 30 4072 #define V_MARSPUE(x) ((x) << S_MARSPUE) 4073 #define F_MARSPUE V_MARSPUE(1U) 4074 4075 #define S_KDBEOPERR 7 4076 #define V_KDBEOPERR(x) ((x) << S_KDBEOPERR) 4077 #define F_KDBEOPERR V_KDBEOPERR(1U) 4078 4079 #define A_PCIE_CFG2 0x3018 4080 4081 #define S_TOTMAXTAG 0 4082 #define M_TOTMAXTAG 0x7U 4083 #define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG) 4084 #define G_TOTMAXTAG(x) (((x) >> S_TOTMAXTAG) & M_TOTMAXTAG) 4085 4086 #define A_PCIE_CFG_SPACE_REQ 0x3060 4087 4088 #define S_ENABLE 30 4089 #define V_ENABLE(x) ((x) << S_ENABLE) 4090 #define F_ENABLE V_ENABLE(1U) 4091 4092 #define S_AI 29 4093 #define V_AI(x) ((x) << S_AI) 4094 #define F_AI V_AI(1U) 4095 4096 #define S_LOCALCFG 28 4097 #define V_LOCALCFG(x) ((x) << S_LOCALCFG) 4098 #define F_LOCALCFG V_LOCALCFG(1U) 4099 4100 #define S_BUS 20 4101 #define M_BUS 0xffU 4102 #define V_BUS(x) ((x) << S_BUS) 4103 #define G_BUS(x) (((x) >> S_BUS) & M_BUS) 4104 4105 #define S_DEVICE 15 4106 #define M_DEVICE 0x1fU 4107 #define V_DEVICE(x) ((x) << S_DEVICE) 4108 #define G_DEVICE(x) (((x) >> S_DEVICE) & M_DEVICE) 4109 4110 #define S_FUNCTION 12 4111 #define M_FUNCTION 0x7U 4112 #define V_FUNCTION(x) ((x) << S_FUNCTION) 4113 #define G_FUNCTION(x) (((x) >> S_FUNCTION) & M_FUNCTION) 4114 4115 #define S_EXTREGISTER 8 4116 #define M_EXTREGISTER 0xfU 4117 #define V_EXTREGISTER(x) ((x) << S_EXTREGISTER) 4118 #define G_EXTREGISTER(x) (((x) >> S_EXTREGISTER) & M_EXTREGISTER) 4119 4120 #define S_REGISTER 0 4121 #define M_REGISTER 0xffU 4122 #define V_REGISTER(x) ((x) << S_REGISTER) 4123 #define G_REGISTER(x) (((x) >> S_REGISTER) & M_REGISTER) 4124 4125 #define S_CS2 28 4126 #define V_CS2(x) ((x) << S_CS2) 4127 #define F_CS2 V_CS2(1U) 4128 4129 #define S_WRBE 24 4130 #define M_WRBE 0xfU 4131 #define V_WRBE(x) ((x) << S_WRBE) 4132 #define G_WRBE(x) (((x) >> S_WRBE) & M_WRBE) 4133 4134 #define S_CFG_SPACE_VFVLD 23 4135 #define V_CFG_SPACE_VFVLD(x) ((x) << S_CFG_SPACE_VFVLD) 4136 #define F_CFG_SPACE_VFVLD V_CFG_SPACE_VFVLD(1U) 4137 4138 #define S_CFG_SPACE_RVF 16 4139 #define M_CFG_SPACE_RVF 0x7fU 4140 #define V_CFG_SPACE_RVF(x) ((x) << S_CFG_SPACE_RVF) 4141 #define G_CFG_SPACE_RVF(x) (((x) >> S_CFG_SPACE_RVF) & M_CFG_SPACE_RVF) 4142 4143 #define S_CFG_SPACE_PF 12 4144 #define M_CFG_SPACE_PF 0x7U 4145 #define V_CFG_SPACE_PF(x) ((x) << S_CFG_SPACE_PF) 4146 #define G_CFG_SPACE_PF(x) (((x) >> S_CFG_SPACE_PF) & M_CFG_SPACE_PF) 4147 4148 #define S_T6_ENABLE 31 4149 #define V_T6_ENABLE(x) ((x) << S_T6_ENABLE) 4150 #define F_T6_ENABLE V_T6_ENABLE(1U) 4151 4152 #define S_T6_AI 30 4153 #define V_T6_AI(x) ((x) << S_T6_AI) 4154 #define F_T6_AI V_T6_AI(1U) 4155 4156 #define S_T6_CS2 29 4157 #define V_T6_CS2(x) ((x) << S_T6_CS2) 4158 #define F_T6_CS2 V_T6_CS2(1U) 4159 4160 #define S_T6_WRBE 25 4161 #define M_T6_WRBE 0xfU 4162 #define V_T6_WRBE(x) ((x) << S_T6_WRBE) 4163 #define G_T6_WRBE(x) (((x) >> S_T6_WRBE) & M_T6_WRBE) 4164 4165 #define S_T6_CFG_SPACE_VFVLD 24 4166 #define V_T6_CFG_SPACE_VFVLD(x) ((x) << S_T6_CFG_SPACE_VFVLD) 4167 #define F_T6_CFG_SPACE_VFVLD V_T6_CFG_SPACE_VFVLD(1U) 4168 4169 #define S_T6_CFG_SPACE_RVF 16 4170 #define M_T6_CFG_SPACE_RVF 0xffU 4171 #define V_T6_CFG_SPACE_RVF(x) ((x) << S_T6_CFG_SPACE_RVF) 4172 #define G_T6_CFG_SPACE_RVF(x) (((x) >> S_T6_CFG_SPACE_RVF) & M_T6_CFG_SPACE_RVF) 4173 4174 #define A_PCIE_CFG_SPACE_DATA 0x3064 4175 #define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068 4176 4177 #define S_PCIEOFST 10 4178 #define M_PCIEOFST 0x3fffffU 4179 #define V_PCIEOFST(x) ((x) << S_PCIEOFST) 4180 #define G_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST) 4181 4182 #define S_BIR 8 4183 #define M_BIR 0x3U 4184 #define V_BIR(x) ((x) << S_BIR) 4185 #define G_BIR(x) (((x) >> S_BIR) & M_BIR) 4186 4187 #define S_WINDOW 0 4188 #define M_WINDOW 0xffU 4189 #define V_WINDOW(x) ((x) << S_WINDOW) 4190 #define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW) 4191 4192 #define A_PCIE_MEM_ACCESS_OFFSET 0x306c 4193 4194 #define S_MEMOFST 7 4195 #define M_MEMOFST 0x1ffffffU 4196 #define V_MEMOFST(x) ((x) << S_MEMOFST) 4197 #define G_MEMOFST(x) (((x) >> S_MEMOFST) & M_MEMOFST) 4198 4199 #define S_PFNUM 0 4200 #define M_PFNUM 0x7U 4201 #define V_PFNUM(x) ((x) << S_PFNUM) 4202 #define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM) 4203 4204 #define A_PCIE_MA_SYNC 0x30b4 4205 #define A_PCIE_FW 0x30b8 4206 #define A_PCIE_FW_PF 0x30bc 4207 #define A_PCIE_CORE_LINK_WIDTH_SPEED_CHANGE 0x580c 4208 4209 #define S_NUM_LANES 8 4210 #define M_NUM_LANES 0x1fU 4211 #define V_NUM_LANES(x) ((x) << S_NUM_LANES) 4212 #define G_NUM_LANES(x) (((x) >> S_NUM_LANES) & M_NUM_LANES) 4213 4214 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908 4215 4216 #define S_RNPP 31 4217 #define V_RNPP(x) ((x) << S_RNPP) 4218 #define F_RNPP V_RNPP(1U) 4219 4220 #define S_RPCP 29 4221 #define V_RPCP(x) ((x) << S_RPCP) 4222 #define F_RPCP V_RPCP(1U) 4223 4224 #define S_RCIP 27 4225 #define V_RCIP(x) ((x) << S_RCIP) 4226 #define F_RCIP V_RCIP(1U) 4227 4228 #define S_RCCP 26 4229 #define V_RCCP(x) ((x) << S_RCCP) 4230 #define F_RCCP V_RCCP(1U) 4231 4232 #define S_RFTP 23 4233 #define V_RFTP(x) ((x) << S_RFTP) 4234 #define F_RFTP V_RFTP(1U) 4235 4236 #define S_PTRP 20 4237 #define V_PTRP(x) ((x) << S_PTRP) 4238 #define F_PTRP V_PTRP(1U) 4239 4240 #define A_PCIE_T5_DMA_STAT2 0x5948 4241 4242 #define S_COOKIECNT 24 4243 #define M_COOKIECNT 0xfU 4244 #define V_COOKIECNT(x) ((x) << S_COOKIECNT) 4245 #define G_COOKIECNT(x) (((x) >> S_COOKIECNT) & M_COOKIECNT) 4246 4247 #define S_RDSEQNUMUPDCNT 20 4248 #define M_RDSEQNUMUPDCNT 0xfU 4249 #define V_RDSEQNUMUPDCNT(x) ((x) << S_RDSEQNUMUPDCNT) 4250 #define G_RDSEQNUMUPDCNT(x) (((x) >> S_RDSEQNUMUPDCNT) & M_RDSEQNUMUPDCNT) 4251 4252 #define S_SIREQCNT 16 4253 #define M_SIREQCNT 0xfU 4254 #define V_SIREQCNT(x) ((x) << S_SIREQCNT) 4255 #define G_SIREQCNT(x) (((x) >> S_SIREQCNT) & M_SIREQCNT) 4256 4257 #define S_WREOPMATCHSOP 12 4258 #define V_WREOPMATCHSOP(x) ((x) << S_WREOPMATCHSOP) 4259 #define F_WREOPMATCHSOP V_WREOPMATCHSOP(1U) 4260 4261 #define S_WRSOPCNT 8 4262 #define M_WRSOPCNT 0xfU 4263 #define V_WRSOPCNT(x) ((x) << S_WRSOPCNT) 4264 #define G_WRSOPCNT(x) (((x) >> S_WRSOPCNT) & M_WRSOPCNT) 4265 4266 #define S_RDSOPCNT 0 4267 #define M_RDSOPCNT 0xffU 4268 #define V_RDSOPCNT(x) ((x) << S_RDSOPCNT) 4269 #define G_RDSOPCNT(x) (((x) >> S_RDSOPCNT) & M_RDSOPCNT) 4270 4271 #define A_PCIE_T5_DMA_STAT3 0x594c 4272 4273 #define S_ATMREQSOPCNT 24 4274 #define M_ATMREQSOPCNT 0xffU 4275 #define V_ATMREQSOPCNT(x) ((x) << S_ATMREQSOPCNT) 4276 #define G_ATMREQSOPCNT(x) (((x) >> S_ATMREQSOPCNT) & M_ATMREQSOPCNT) 4277 4278 #define S_ATMEOPMATCHSOP 17 4279 #define V_ATMEOPMATCHSOP(x) ((x) << S_ATMEOPMATCHSOP) 4280 #define F_ATMEOPMATCHSOP V_ATMEOPMATCHSOP(1U) 4281 4282 #define S_RSPEOPMATCHSOP 16 4283 #define V_RSPEOPMATCHSOP(x) ((x) << S_RSPEOPMATCHSOP) 4284 #define F_RSPEOPMATCHSOP V_RSPEOPMATCHSOP(1U) 4285 4286 #define S_RSPERRCNT 8 4287 #define M_RSPERRCNT 0xffU 4288 #define V_RSPERRCNT(x) ((x) << S_RSPERRCNT) 4289 #define G_RSPERRCNT(x) (((x) >> S_RSPERRCNT) & M_RSPERRCNT) 4290 4291 #define S_RSPSOPCNT 0 4292 #define M_RSPSOPCNT 0xffU 4293 #define V_RSPSOPCNT(x) ((x) << S_RSPSOPCNT) 4294 #define G_RSPSOPCNT(x) (((x) >> S_RSPSOPCNT) & M_RSPSOPCNT) 4295 4296 #define A_PCIE_T5_CMD_STAT2 0x5988 4297 #define A_PCIE_T5_CMD_STAT3 0x598c 4298 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4 4299 4300 #define S_TPCP 30 4301 #define V_TPCP(x) ((x) << S_TPCP) 4302 #define F_TPCP V_TPCP(1U) 4303 4304 #define S_TNPP 29 4305 #define V_TNPP(x) ((x) << S_TNPP) 4306 #define F_TNPP V_TNPP(1U) 4307 4308 #define S_TFTP 28 4309 #define V_TFTP(x) ((x) << S_TFTP) 4310 #define F_TFTP V_TFTP(1U) 4311 4312 #define S_TCAP 27 4313 #define V_TCAP(x) ((x) << S_TCAP) 4314 #define F_TCAP V_TCAP(1U) 4315 4316 #define S_TCIP 26 4317 #define V_TCIP(x) ((x) << S_TCIP) 4318 #define F_TCIP V_TCIP(1U) 4319 4320 #define S_RCAP 25 4321 #define V_RCAP(x) ((x) << S_RCAP) 4322 #define F_RCAP V_RCAP(1U) 4323 4324 #define S_PLUP 23 4325 #define V_PLUP(x) ((x) << S_PLUP) 4326 #define F_PLUP V_PLUP(1U) 4327 4328 #define S_PLDN 22 4329 #define V_PLDN(x) ((x) << S_PLDN) 4330 #define F_PLDN V_PLDN(1U) 4331 4332 #define S_OTDD 21 4333 #define V_OTDD(x) ((x) << S_OTDD) 4334 #define F_OTDD V_OTDD(1U) 4335 4336 #define S_GTRP 20 4337 #define V_GTRP(x) ((x) << S_GTRP) 4338 #define F_GTRP V_GTRP(1U) 4339 4340 #define S_RDPE 18 4341 #define V_RDPE(x) ((x) << S_RDPE) 4342 #define F_RDPE V_RDPE(1U) 4343 4344 #define S_TDCE 17 4345 #define V_TDCE(x) ((x) << S_TDCE) 4346 #define F_TDCE V_TDCE(1U) 4347 4348 #define S_TDUE 16 4349 #define V_TDUE(x) ((x) << S_TDUE) 4350 #define F_TDUE V_TDUE(1U) 4351 4352 #define A_PCIE_CORE_ENDPOINT_STATUS 0x59bc 4353 4354 #define S_PTOM 31 4355 #define V_PTOM(x) ((x) << S_PTOM) 4356 #define F_PTOM V_PTOM(1U) 4357 4358 #define S_ALEA 29 4359 #define V_ALEA(x) ((x) << S_ALEA) 4360 #define F_ALEA V_ALEA(1U) 4361 4362 #define S_PMC0 23 4363 #define V_PMC0(x) ((x) << S_PMC0) 4364 #define F_PMC0 V_PMC0(1U) 4365 4366 #define S_PMC1 22 4367 #define V_PMC1(x) ((x) << S_PMC1) 4368 #define F_PMC1 V_PMC1(1U) 4369 4370 #define S_PMC2 21 4371 #define V_PMC2(x) ((x) << S_PMC2) 4372 #define F_PMC2 V_PMC2(1U) 4373 4374 #define S_PMC3 20 4375 #define V_PMC3(x) ((x) << S_PMC3) 4376 #define F_PMC3 V_PMC3(1U) 4377 4378 #define S_PMC4 19 4379 #define V_PMC4(x) ((x) << S_PMC4) 4380 #define F_PMC4 V_PMC4(1U) 4381 4382 #define S_PMC5 18 4383 #define V_PMC5(x) ((x) << S_PMC5) 4384 #define F_PMC5 V_PMC5(1U) 4385 4386 #define S_PMC6 17 4387 #define V_PMC6(x) ((x) << S_PMC6) 4388 #define F_PMC6 V_PMC6(1U) 4389 4390 #define S_PMC7 16 4391 #define V_PMC7(x) ((x) << S_PMC7) 4392 #define F_PMC7 V_PMC7(1U) 4393 4394 #define A_PCIE_CHANGESET 0x59fc 4395 #define A_PCIE_REVISION 0x5a00 4396 #define A_PCIE_PDEBUG_INDEX 0x5a04 4397 4398 #define S_PDEBUGSELH 16 4399 #define M_PDEBUGSELH 0x3fU 4400 #define V_PDEBUGSELH(x) ((x) << S_PDEBUGSELH) 4401 #define G_PDEBUGSELH(x) (((x) >> S_PDEBUGSELH) & M_PDEBUGSELH) 4402 4403 #define S_PDEBUGSELL 0 4404 #define M_PDEBUGSELL 0x3fU 4405 #define V_PDEBUGSELL(x) ((x) << S_PDEBUGSELL) 4406 #define G_PDEBUGSELL(x) (((x) >> S_PDEBUGSELL) & M_PDEBUGSELL) 4407 4408 #define S_T6_PDEBUGSELH 16 4409 #define M_T6_PDEBUGSELH 0x7fU 4410 #define V_T6_PDEBUGSELH(x) ((x) << S_T6_PDEBUGSELH) 4411 #define G_T6_PDEBUGSELH(x) (((x) >> S_T6_PDEBUGSELH) & M_T6_PDEBUGSELH) 4412 4413 #define S_T6_PDEBUGSELL 0 4414 #define M_T6_PDEBUGSELL 0x7fU 4415 #define V_T6_PDEBUGSELL(x) ((x) << S_T6_PDEBUGSELL) 4416 #define G_T6_PDEBUGSELL(x) (((x) >> S_T6_PDEBUGSELL) & M_T6_PDEBUGSELL) 4417 4418 #define A_PCIE_PDEBUG_DATA_HIGH 0x5a08 4419 #define A_PCIE_PDEBUG_DATA_LOW 0x5a0c 4420 #define A_PCIE_CDEBUG_INDEX 0x5a10 4421 4422 #define S_CDEBUGSELH 16 4423 #define M_CDEBUGSELH 0xffU 4424 #define V_CDEBUGSELH(x) ((x) << S_CDEBUGSELH) 4425 #define G_CDEBUGSELH(x) (((x) >> S_CDEBUGSELH) & M_CDEBUGSELH) 4426 4427 #define A_PCIE_CDEBUG_DATA_HIGH 0x5a14 4428 #define A_PCIE_DMAW_SOP_CNT 0x5a1c 4429 4430 #define S_CH3 24 4431 #define M_CH3 0xffU 4432 #define V_CH3(x) ((x) << S_CH3) 4433 #define G_CH3(x) (((x) >> S_CH3) & M_CH3) 4434 4435 #define S_CH2 16 4436 #define M_CH2 0xffU 4437 #define V_CH2(x) ((x) << S_CH2) 4438 #define G_CH2(x) (((x) >> S_CH2) & M_CH2) 4439 4440 #define S_CH1 8 4441 #define M_CH1 0xffU 4442 #define V_CH1(x) ((x) << S_CH1) 4443 #define G_CH1(x) (((x) >> S_CH1) & M_CH1) 4444 4445 #define S_CH0 0 4446 #define M_CH0 0xffU 4447 #define V_CH0(x) ((x) << S_CH0) 4448 #define G_CH0(x) (((x) >> S_CH0) & M_CH0) 4449 4450 #define A_PCIE_DMAW_EOP_CNT 0x5a20 4451 #define A_PCIE_DMAR_REQ_CNT 0x5a24 4452 #define A_PCIE_DMAR_RSP_SOP_CNT 0x5a28 4453 #define A_PCIE_DMAR_RSP_EOP_CNT 0x5a2c 4454 #define A_PCIE_DMAI_CNT 0x5a34 4455 #define A_PCIE_CMDR_REQ_CNT 0x5a3c 4456 #define A_PCIE_CMDR_RSP_CNT 0x5a40 4457 4458 #define S_CH1_EOP 24 4459 #define M_CH1_EOP 0xffU 4460 #define V_CH1_EOP(x) ((x) << S_CH1_EOP) 4461 #define G_CH1_EOP(x) (((x) >> S_CH1_EOP) & M_CH1_EOP) 4462 4463 #define S_CH1_SOP 16 4464 #define M_CH1_SOP 0xffU 4465 #define V_CH1_SOP(x) ((x) << S_CH1_SOP) 4466 #define G_CH1_SOP(x) (((x) >> S_CH1_SOP) & M_CH1_SOP) 4467 4468 #define S_CH0_EOP 8 4469 #define M_CH0_EOP 0xffU 4470 #define V_CH0_EOP(x) ((x) << S_CH0_EOP) 4471 #define G_CH0_EOP(x) (((x) >> S_CH0_EOP) & M_CH0_EOP) 4472 4473 #define S_CH0_SOP 0 4474 #define M_CH0_SOP 0xffU 4475 #define V_CH0_SOP(x) ((x) << S_CH0_SOP) 4476 #define G_CH0_SOP(x) (((x) >> S_CH0_SOP) & M_CH0_SOP) 4477 4478 #define A_PCIE_KDOORBELL_GTS_PF_BASE_LEN 0x5c10 4479 4480 #define S_KDB_PF_LEN 24 4481 #define M_KDB_PF_LEN 0x1fU 4482 #define V_KDB_PF_LEN(x) ((x) << S_KDB_PF_LEN) 4483 #define G_KDB_PF_LEN(x) (((x) >> S_KDB_PF_LEN) & M_KDB_PF_LEN) 4484 4485 #define S_KDB_PF_BASEADDR 0 4486 #define M_KDB_PF_BASEADDR 0xfffffU 4487 #define V_KDB_PF_BASEADDR(x) ((x) << S_KDB_PF_BASEADDR) 4488 #define G_KDB_PF_BASEADDR(x) (((x) >> S_KDB_PF_BASEADDR) & M_KDB_PF_BASEADDR) 4489 4490 #define A_PCIE_KDOORBELL_GTS_VF_BASE_LEN 0x5c14 4491 4492 #define S_KDB_VF_LEN 24 4493 #define M_KDB_VF_LEN 0x1fU 4494 #define V_KDB_VF_LEN(x) ((x) << S_KDB_VF_LEN) 4495 #define G_KDB_VF_LEN(x) (((x) >> S_KDB_VF_LEN) & M_KDB_VF_LEN) 4496 4497 #define S_KDB_VF_BASEADDR 0 4498 #define M_KDB_VF_BASEADDR 0xfffffU 4499 #define V_KDB_VF_BASEADDR(x) ((x) << S_KDB_VF_BASEADDR) 4500 #define G_KDB_VF_BASEADDR(x) (((x) >> S_KDB_VF_BASEADDR) & M_KDB_VF_BASEADDR) 4501 4502 #define A_PCIE_KDOORBELL_GTS_VF_OFFSET 0x5c18 4503 4504 #define S_KDB_VF_MODOFST 0 4505 #define M_KDB_VF_MODOFST 0xfffU 4506 #define V_KDB_VF_MODOFST(x) ((x) << S_KDB_VF_MODOFST) 4507 #define G_KDB_VF_MODOFST(x) (((x) >> S_KDB_VF_MODOFST) & M_KDB_VF_MODOFST) 4508 4509 #define A_PCIE_TGT_SKID_FIFO 0x5e94 4510 4511 #define S_HDRFREECNT 16 4512 #define M_HDRFREECNT 0xfffU 4513 #define V_HDRFREECNT(x) ((x) << S_HDRFREECNT) 4514 #define G_HDRFREECNT(x) (((x) >> S_HDRFREECNT) & M_HDRFREECNT) 4515 4516 #define S_DATAFREECNT 0 4517 #define M_DATAFREECNT 0xfffU 4518 #define V_DATAFREECNT(x) ((x) << S_DATAFREECNT) 4519 #define G_DATAFREECNT(x) (((x) >> S_DATAFREECNT) & M_DATAFREECNT) 4520 4521 4522 /* registers for module DBG */ 4523 #define DBG_BASE_ADDR 0x6000 4524 4525 #define A_DBG_GPIO_EN 0x6010 4526 4527 #define S_GPIO15_OEN 31 4528 #define V_GPIO15_OEN(x) ((x) << S_GPIO15_OEN) 4529 #define F_GPIO15_OEN V_GPIO15_OEN(1U) 4530 4531 #define S_GPIO14_OEN 30 4532 #define V_GPIO14_OEN(x) ((x) << S_GPIO14_OEN) 4533 #define F_GPIO14_OEN V_GPIO14_OEN(1U) 4534 4535 #define S_GPIO13_OEN 29 4536 #define V_GPIO13_OEN(x) ((x) << S_GPIO13_OEN) 4537 #define F_GPIO13_OEN V_GPIO13_OEN(1U) 4538 4539 #define S_GPIO12_OEN 28 4540 #define V_GPIO12_OEN(x) ((x) << S_GPIO12_OEN) 4541 #define F_GPIO12_OEN V_GPIO12_OEN(1U) 4542 4543 #define S_GPIO11_OEN 27 4544 #define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN) 4545 #define F_GPIO11_OEN V_GPIO11_OEN(1U) 4546 4547 #define S_GPIO10_OEN 26 4548 #define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN) 4549 #define F_GPIO10_OEN V_GPIO10_OEN(1U) 4550 4551 #define S_GPIO9_OEN 25 4552 #define V_GPIO9_OEN(x) ((x) << S_GPIO9_OEN) 4553 #define F_GPIO9_OEN V_GPIO9_OEN(1U) 4554 4555 #define S_GPIO8_OEN 24 4556 #define V_GPIO8_OEN(x) ((x) << S_GPIO8_OEN) 4557 #define F_GPIO8_OEN V_GPIO8_OEN(1U) 4558 4559 #define S_GPIO7_OEN 23 4560 #define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN) 4561 #define F_GPIO7_OEN V_GPIO7_OEN(1U) 4562 4563 #define S_GPIO6_OEN 22 4564 #define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN) 4565 #define F_GPIO6_OEN V_GPIO6_OEN(1U) 4566 4567 #define S_GPIO5_OEN 21 4568 #define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN) 4569 #define F_GPIO5_OEN V_GPIO5_OEN(1U) 4570 4571 #define S_GPIO4_OEN 20 4572 #define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN) 4573 #define F_GPIO4_OEN V_GPIO4_OEN(1U) 4574 4575 #define S_GPIO3_OEN 19 4576 #define V_GPIO3_OEN(x) ((x) << S_GPIO3_OEN) 4577 #define F_GPIO3_OEN V_GPIO3_OEN(1U) 4578 4579 #define S_GPIO2_OEN 18 4580 #define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN) 4581 #define F_GPIO2_OEN V_GPIO2_OEN(1U) 4582 4583 #define S_GPIO1_OEN 17 4584 #define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN) 4585 #define F_GPIO1_OEN V_GPIO1_OEN(1U) 4586 4587 #define S_GPIO0_OEN 16 4588 #define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN) 4589 #define F_GPIO0_OEN V_GPIO0_OEN(1U) 4590 4591 #define S_GPIO15_OUT_VAL 15 4592 #define V_GPIO15_OUT_VAL(x) ((x) << S_GPIO15_OUT_VAL) 4593 #define F_GPIO15_OUT_VAL V_GPIO15_OUT_VAL(1U) 4594 4595 #define S_GPIO14_OUT_VAL 14 4596 #define V_GPIO14_OUT_VAL(x) ((x) << S_GPIO14_OUT_VAL) 4597 #define F_GPIO14_OUT_VAL V_GPIO14_OUT_VAL(1U) 4598 4599 #define S_GPIO13_OUT_VAL 13 4600 #define V_GPIO13_OUT_VAL(x) ((x) << S_GPIO13_OUT_VAL) 4601 #define F_GPIO13_OUT_VAL V_GPIO13_OUT_VAL(1U) 4602 4603 #define S_GPIO12_OUT_VAL 12 4604 #define V_GPIO12_OUT_VAL(x) ((x) << S_GPIO12_OUT_VAL) 4605 #define F_GPIO12_OUT_VAL V_GPIO12_OUT_VAL(1U) 4606 4607 #define S_GPIO11_OUT_VAL 11 4608 #define V_GPIO11_OUT_VAL(x) ((x) << S_GPIO11_OUT_VAL) 4609 #define F_GPIO11_OUT_VAL V_GPIO11_OUT_VAL(1U) 4610 4611 #define S_GPIO10_OUT_VAL 10 4612 #define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL) 4613 #define F_GPIO10_OUT_VAL V_GPIO10_OUT_VAL(1U) 4614 4615 #define S_GPIO9_OUT_VAL 9 4616 #define V_GPIO9_OUT_VAL(x) ((x) << S_GPIO9_OUT_VAL) 4617 #define F_GPIO9_OUT_VAL V_GPIO9_OUT_VAL(1U) 4618 4619 #define S_GPIO8_OUT_VAL 8 4620 #define V_GPIO8_OUT_VAL(x) ((x) << S_GPIO8_OUT_VAL) 4621 #define F_GPIO8_OUT_VAL V_GPIO8_OUT_VAL(1U) 4622 4623 #define S_GPIO7_OUT_VAL 7 4624 #define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL) 4625 #define F_GPIO7_OUT_VAL V_GPIO7_OUT_VAL(1U) 4626 4627 #define S_GPIO6_OUT_VAL 6 4628 #define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL) 4629 #define F_GPIO6_OUT_VAL V_GPIO6_OUT_VAL(1U) 4630 4631 #define S_GPIO5_OUT_VAL 5 4632 #define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL) 4633 #define F_GPIO5_OUT_VAL V_GPIO5_OUT_VAL(1U) 4634 4635 #define S_GPIO4_OUT_VAL 4 4636 #define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL) 4637 #define F_GPIO4_OUT_VAL V_GPIO4_OUT_VAL(1U) 4638 4639 #define S_GPIO3_OUT_VAL 3 4640 #define V_GPIO3_OUT_VAL(x) ((x) << S_GPIO3_OUT_VAL) 4641 #define F_GPIO3_OUT_VAL V_GPIO3_OUT_VAL(1U) 4642 4643 #define S_GPIO2_OUT_VAL 2 4644 #define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL) 4645 #define F_GPIO2_OUT_VAL V_GPIO2_OUT_VAL(1U) 4646 4647 #define S_GPIO1_OUT_VAL 1 4648 #define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL) 4649 #define F_GPIO1_OUT_VAL V_GPIO1_OUT_VAL(1U) 4650 4651 #define S_GPIO0_OUT_VAL 0 4652 #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL) 4653 #define F_GPIO0_OUT_VAL V_GPIO0_OUT_VAL(1U) 4654 4655 #define A_DBG_STATIC_C_PLL_CONF2 0x60d4 4656 4657 #define S_STATIC_C_PLL_LOCKTUNE 0 4658 #define M_STATIC_C_PLL_LOCKTUNE 0x1fU 4659 #define V_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_STATIC_C_PLL_LOCKTUNE) 4660 #define G_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_STATIC_C_PLL_LOCKTUNE) & M_STATIC_C_PLL_LOCKTUNE) 4661 4662 #define A_DBG_STATIC_C_PLL_CONF3 0x60d8 4663 4664 #define S_STATIC_C_PLL_LOCKSEL 28 4665 #define V_STATIC_C_PLL_LOCKSEL(x) ((x) << S_STATIC_C_PLL_LOCKSEL) 4666 #define F_STATIC_C_PLL_LOCKSEL V_STATIC_C_PLL_LOCKSEL(1U) 4667 4668 #define S_STATIC_C_PLL_FFTUNE 12 4669 #define M_STATIC_C_PLL_FFTUNE 0xffffU 4670 #define V_STATIC_C_PLL_FFTUNE(x) ((x) << S_STATIC_C_PLL_FFTUNE) 4671 #define G_STATIC_C_PLL_FFTUNE(x) (((x) >> S_STATIC_C_PLL_FFTUNE) & M_STATIC_C_PLL_FFTUNE) 4672 4673 #define A_DBG_STATIC_C_PLL_CONF5 0x60e0 4674 4675 #define S_STATIC_C_PLL_VCVTUNE 22 4676 #define M_STATIC_C_PLL_VCVTUNE 0x7U 4677 #define V_STATIC_C_PLL_VCVTUNE(x) ((x) << S_STATIC_C_PLL_VCVTUNE) 4678 #define G_STATIC_C_PLL_VCVTUNE(x) (((x) >> S_STATIC_C_PLL_VCVTUNE) & M_STATIC_C_PLL_VCVTUNE) 4679 4680 #define S_STATIC_C_PLL_PREDIV_CNF5 8 4681 #define M_STATIC_C_PLL_PREDIV_CNF5 0x1fU 4682 #define V_STATIC_C_PLL_PREDIV_CNF5(x) ((x) << S_STATIC_C_PLL_PREDIV_CNF5) 4683 #define G_STATIC_C_PLL_PREDIV_CNF5(x) (((x) >> S_STATIC_C_PLL_PREDIV_CNF5) & M_STATIC_C_PLL_PREDIV_CNF5) 4684 4685 #define A_DBG_STATIC_U_PLL_CONF2 0x60e8 4686 4687 #define S_STATIC_U_PLL_LOCKTUNE 0 4688 #define M_STATIC_U_PLL_LOCKTUNE 0x1fU 4689 #define V_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_STATIC_U_PLL_LOCKTUNE) 4690 #define G_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_STATIC_U_PLL_LOCKTUNE) & M_STATIC_U_PLL_LOCKTUNE) 4691 4692 #define A_DBG_STATIC_U_PLL_CONF3 0x60ec 4693 4694 #define S_STATIC_U_PLL_LOCKSEL 28 4695 #define V_STATIC_U_PLL_LOCKSEL(x) ((x) << S_STATIC_U_PLL_LOCKSEL) 4696 #define F_STATIC_U_PLL_LOCKSEL V_STATIC_U_PLL_LOCKSEL(1U) 4697 4698 #define A_DBG_STATIC_KR_PLL_CONF1 0x60f8 4699 4700 #define S_STATIC_KR_PLL_VBOOSTDIV 27 4701 #define M_STATIC_KR_PLL_VBOOSTDIV 0x7U 4702 #define V_STATIC_KR_PLL_VBOOSTDIV(x) ((x) << S_STATIC_KR_PLL_VBOOSTDIV) 4703 #define G_STATIC_KR_PLL_VBOOSTDIV(x) (((x) >> S_STATIC_KR_PLL_VBOOSTDIV) & M_STATIC_KR_PLL_VBOOSTDIV) 4704 4705 #define S_STATIC_KR_PLL_BGOFFSET 11 4706 #define M_STATIC_KR_PLL_BGOFFSET 0xfU 4707 #define V_STATIC_KR_PLL_BGOFFSET(x) ((x) << S_STATIC_KR_PLL_BGOFFSET) 4708 #define G_STATIC_KR_PLL_BGOFFSET(x) (((x) >> S_STATIC_KR_PLL_BGOFFSET) & M_STATIC_KR_PLL_BGOFFSET) 4709 4710 #define A_DBG_STATIC_KX_PLL_CONF1 0x6108 4711 4712 #define S_STATIC_KX_PLL_VBOOSTDIV 27 4713 #define M_STATIC_KX_PLL_VBOOSTDIV 0x7U 4714 #define V_STATIC_KX_PLL_VBOOSTDIV(x) ((x) << S_STATIC_KX_PLL_VBOOSTDIV) 4715 #define G_STATIC_KX_PLL_VBOOSTDIV(x) (((x) >> S_STATIC_KX_PLL_VBOOSTDIV) & M_STATIC_KX_PLL_VBOOSTDIV) 4716 4717 #define S_STATIC_KX_PLL_BGOFFSET 11 4718 #define M_STATIC_KX_PLL_BGOFFSET 0xfU 4719 #define V_STATIC_KX_PLL_BGOFFSET(x) ((x) << S_STATIC_KX_PLL_BGOFFSET) 4720 #define G_STATIC_KX_PLL_BGOFFSET(x) (((x) >> S_STATIC_KX_PLL_BGOFFSET) & M_STATIC_KX_PLL_BGOFFSET) 4721 4722 4723 /* registers for module MC */ 4724 #define MC_BASE_ADDR 0x6200 4725 4726 #define A_MC_PAR_CAUSE 0x7510 4727 4728 #define S_ECC_UE_PAR_CAUSE 3 4729 #define V_ECC_UE_PAR_CAUSE(x) ((x) << S_ECC_UE_PAR_CAUSE) 4730 #define F_ECC_UE_PAR_CAUSE V_ECC_UE_PAR_CAUSE(1U) 4731 4732 #define S_ECC_CE_PAR_CAUSE 2 4733 #define V_ECC_CE_PAR_CAUSE(x) ((x) << S_ECC_CE_PAR_CAUSE) 4734 #define F_ECC_CE_PAR_CAUSE V_ECC_CE_PAR_CAUSE(1U) 4735 4736 #define S_FIFOR_PAR_CAUSE 1 4737 #define V_FIFOR_PAR_CAUSE(x) ((x) << S_FIFOR_PAR_CAUSE) 4738 #define F_FIFOR_PAR_CAUSE V_FIFOR_PAR_CAUSE(1U) 4739 4740 #define S_RDATA_FIFOR_PAR_CAUSE 0 4741 #define V_RDATA_FIFOR_PAR_CAUSE(x) ((x) << S_RDATA_FIFOR_PAR_CAUSE) 4742 #define F_RDATA_FIFOR_PAR_CAUSE V_RDATA_FIFOR_PAR_CAUSE(1U) 4743 4744 #define A_MC_INT_CAUSE 0x7518 4745 4746 #define S_ECC_UE_INT_CAUSE 2 4747 #define V_ECC_UE_INT_CAUSE(x) ((x) << S_ECC_UE_INT_CAUSE) 4748 #define F_ECC_UE_INT_CAUSE V_ECC_UE_INT_CAUSE(1U) 4749 4750 #define S_ECC_CE_INT_CAUSE 1 4751 #define V_ECC_CE_INT_CAUSE(x) ((x) << S_ECC_CE_INT_CAUSE) 4752 #define F_ECC_CE_INT_CAUSE V_ECC_CE_INT_CAUSE(1U) 4753 4754 #define S_PERR_INT_CAUSE 0 4755 #define V_PERR_INT_CAUSE(x) ((x) << S_PERR_INT_CAUSE) 4756 #define F_PERR_INT_CAUSE V_PERR_INT_CAUSE(1U) 4757 4758 #define A_MC_ECC_STATUS 0x751c 4759 4760 #define S_ECC_CECNT 16 4761 #define M_ECC_CECNT 0xffffU 4762 #define V_ECC_CECNT(x) ((x) << S_ECC_CECNT) 4763 #define G_ECC_CECNT(x) (((x) >> S_ECC_CECNT) & M_ECC_CECNT) 4764 4765 #define S_ECC_UECNT 0 4766 #define M_ECC_UECNT 0xffffU 4767 #define V_ECC_UECNT(x) ((x) << S_ECC_UECNT) 4768 #define G_ECC_UECNT(x) (((x) >> S_ECC_UECNT) & M_ECC_UECNT) 4769 4770 #define A_MC_BIST_CMD 0x7600 4771 4772 #define S_START_BIST 31 4773 #define V_START_BIST(x) ((x) << S_START_BIST) 4774 #define F_START_BIST V_START_BIST(1U) 4775 4776 #define S_BIST_CMD_GAP 8 4777 #define M_BIST_CMD_GAP 0xffU 4778 #define V_BIST_CMD_GAP(x) ((x) << S_BIST_CMD_GAP) 4779 #define G_BIST_CMD_GAP(x) (((x) >> S_BIST_CMD_GAP) & M_BIST_CMD_GAP) 4780 4781 #define S_BIST_OPCODE 0 4782 #define M_BIST_OPCODE 0x3U 4783 #define V_BIST_OPCODE(x) ((x) << S_BIST_OPCODE) 4784 #define G_BIST_OPCODE(x) (((x) >> S_BIST_OPCODE) & M_BIST_OPCODE) 4785 4786 #define A_MC_BIST_CMD_ADDR 0x7604 4787 #define A_MC_BIST_CMD_LEN 0x7608 4788 #define A_MC_BIST_DATA_PATTERN 0x760c 4789 4790 #define S_BIST_DATA_TYPE 0 4791 #define M_BIST_DATA_TYPE 0xfU 4792 #define V_BIST_DATA_TYPE(x) ((x) << S_BIST_DATA_TYPE) 4793 #define G_BIST_DATA_TYPE(x) (((x) >> S_BIST_DATA_TYPE) & M_BIST_DATA_TYPE) 4794 4795 #define A_MC_BIST_STATUS_RDATA 0x7688 4796 4797 /* registers for module MA */ 4798 #define MA_BASE_ADDR 0x7700 4799 4800 #define A_MA_EDRAM0_BAR 0x77c0 4801 4802 #define S_EDRAM0_BASE 16 4803 #define M_EDRAM0_BASE 0xfffU 4804 #define V_EDRAM0_BASE(x) ((x) << S_EDRAM0_BASE) 4805 #define G_EDRAM0_BASE(x) (((x) >> S_EDRAM0_BASE) & M_EDRAM0_BASE) 4806 4807 #define S_EDRAM0_SIZE 0 4808 #define M_EDRAM0_SIZE 0xfffU 4809 #define V_EDRAM0_SIZE(x) ((x) << S_EDRAM0_SIZE) 4810 #define G_EDRAM0_SIZE(x) (((x) >> S_EDRAM0_SIZE) & M_EDRAM0_SIZE) 4811 4812 #define A_MA_EDRAM1_BAR 0x77c4 4813 4814 #define S_EDRAM1_BASE 16 4815 #define M_EDRAM1_BASE 0xfffU 4816 #define V_EDRAM1_BASE(x) ((x) << S_EDRAM1_BASE) 4817 #define G_EDRAM1_BASE(x) (((x) >> S_EDRAM1_BASE) & M_EDRAM1_BASE) 4818 4819 #define S_EDRAM1_SIZE 0 4820 #define M_EDRAM1_SIZE 0xfffU 4821 #define V_EDRAM1_SIZE(x) ((x) << S_EDRAM1_SIZE) 4822 #define G_EDRAM1_SIZE(x) (((x) >> S_EDRAM1_SIZE) & M_EDRAM1_SIZE) 4823 4824 #define A_MA_EXT_MEMORY_BAR 0x77c8 4825 4826 #define S_EXT_MEM_BASE 16 4827 #define M_EXT_MEM_BASE 0xfffU 4828 #define V_EXT_MEM_BASE(x) ((x) << S_EXT_MEM_BASE) 4829 #define G_EXT_MEM_BASE(x) (((x) >> S_EXT_MEM_BASE) & M_EXT_MEM_BASE) 4830 4831 #define S_EXT_MEM_SIZE 0 4832 #define M_EXT_MEM_SIZE 0xfffU 4833 #define V_EXT_MEM_SIZE(x) ((x) << S_EXT_MEM_SIZE) 4834 #define G_EXT_MEM_SIZE(x) (((x) >> S_EXT_MEM_SIZE) & M_EXT_MEM_SIZE) 4835 4836 #define A_MA_EXT_MEMORY0_BAR 0x77c8 4837 4838 #define S_EXT_MEM0_BASE 16 4839 #define M_EXT_MEM0_BASE 0xfffU 4840 #define V_EXT_MEM0_BASE(x) ((x) << S_EXT_MEM0_BASE) 4841 #define G_EXT_MEM0_BASE(x) (((x) >> S_EXT_MEM0_BASE) & M_EXT_MEM0_BASE) 4842 4843 #define S_EXT_MEM0_SIZE 0 4844 #define M_EXT_MEM0_SIZE 0xfffU 4845 #define V_EXT_MEM0_SIZE(x) ((x) << S_EXT_MEM0_SIZE) 4846 #define G_EXT_MEM0_SIZE(x) (((x) >> S_EXT_MEM0_SIZE) & M_EXT_MEM0_SIZE) 4847 4848 #define A_MA_TARGET_MEM_ENABLE 0x77d8 4849 4850 #define S_HMA_ENABLE 3 4851 #define V_HMA_ENABLE(x) ((x) << S_HMA_ENABLE) 4852 #define F_HMA_ENABLE V_HMA_ENABLE(1U) 4853 4854 #define S_EXT_MEM_ENABLE 2 4855 #define V_EXT_MEM_ENABLE(x) ((x) << S_EXT_MEM_ENABLE) 4856 #define F_EXT_MEM_ENABLE V_EXT_MEM_ENABLE(1U) 4857 4858 #define S_EDRAM1_ENABLE 1 4859 #define V_EDRAM1_ENABLE(x) ((x) << S_EDRAM1_ENABLE) 4860 #define F_EDRAM1_ENABLE V_EDRAM1_ENABLE(1U) 4861 4862 #define S_EDRAM0_ENABLE 0 4863 #define V_EDRAM0_ENABLE(x) ((x) << S_EDRAM0_ENABLE) 4864 #define F_EDRAM0_ENABLE V_EDRAM0_ENABLE(1U) 4865 4866 #define S_HMA_MUX 5 4867 #define V_HMA_MUX(x) ((x) << S_HMA_MUX) 4868 #define F_HMA_MUX V_HMA_MUX(1U) 4869 4870 #define S_EXT_MEM1_ENABLE 4 4871 #define V_EXT_MEM1_ENABLE(x) ((x) << S_EXT_MEM1_ENABLE) 4872 #define F_EXT_MEM1_ENABLE V_EXT_MEM1_ENABLE(1U) 4873 4874 #define S_EXT_MEM0_ENABLE 2 4875 #define V_EXT_MEM0_ENABLE(x) ((x) << S_EXT_MEM0_ENABLE) 4876 #define F_EXT_MEM0_ENABLE V_EXT_MEM0_ENABLE(1U) 4877 4878 #define S_MC_SPLIT 6 4879 #define V_MC_SPLIT(x) ((x) << S_MC_SPLIT) 4880 #define F_MC_SPLIT V_MC_SPLIT(1U) 4881 4882 #define A_MA_INT_CAUSE 0x77e0 4883 4884 #define S_MEM_PERR_INT_CAUSE 1 4885 #define V_MEM_PERR_INT_CAUSE(x) ((x) << S_MEM_PERR_INT_CAUSE) 4886 #define F_MEM_PERR_INT_CAUSE V_MEM_PERR_INT_CAUSE(1U) 4887 4888 #define S_MEM_WRAP_INT_CAUSE 0 4889 #define V_MEM_WRAP_INT_CAUSE(x) ((x) << S_MEM_WRAP_INT_CAUSE) 4890 #define F_MEM_WRAP_INT_CAUSE V_MEM_WRAP_INT_CAUSE(1U) 4891 4892 #define A_MA_INT_WRAP_STATUS 0x77e4 4893 4894 #define S_MEM_WRAP_ADDRESS 4 4895 #define M_MEM_WRAP_ADDRESS 0xfffffffU 4896 #define V_MEM_WRAP_ADDRESS(x) ((x) << S_MEM_WRAP_ADDRESS) 4897 #define G_MEM_WRAP_ADDRESS(x) (((x) >> S_MEM_WRAP_ADDRESS) & M_MEM_WRAP_ADDRESS) 4898 4899 #define S_MEM_WRAP_CLIENT_NUM 0 4900 #define M_MEM_WRAP_CLIENT_NUM 0xfU 4901 #define V_MEM_WRAP_CLIENT_NUM(x) ((x) << S_MEM_WRAP_CLIENT_NUM) 4902 #define G_MEM_WRAP_CLIENT_NUM(x) (((x) >> S_MEM_WRAP_CLIENT_NUM) & M_MEM_WRAP_CLIENT_NUM) 4903 4904 #define A_MA_PARITY_ERROR_STATUS 0x77f4 4905 4906 #define S_TP_DMARBT_PAR_ERROR 31 4907 #define V_TP_DMARBT_PAR_ERROR(x) ((x) << S_TP_DMARBT_PAR_ERROR) 4908 #define F_TP_DMARBT_PAR_ERROR V_TP_DMARBT_PAR_ERROR(1U) 4909 4910 #define S_LOGIC_FIFO_PAR_ERROR 30 4911 #define V_LOGIC_FIFO_PAR_ERROR(x) ((x) << S_LOGIC_FIFO_PAR_ERROR) 4912 #define F_LOGIC_FIFO_PAR_ERROR V_LOGIC_FIFO_PAR_ERROR(1U) 4913 4914 #define S_ARB3_PAR_WRQUEUE_ERROR 29 4915 #define V_ARB3_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB3_PAR_WRQUEUE_ERROR) 4916 #define F_ARB3_PAR_WRQUEUE_ERROR V_ARB3_PAR_WRQUEUE_ERROR(1U) 4917 4918 #define S_ARB2_PAR_WRQUEUE_ERROR 28 4919 #define V_ARB2_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB2_PAR_WRQUEUE_ERROR) 4920 #define F_ARB2_PAR_WRQUEUE_ERROR V_ARB2_PAR_WRQUEUE_ERROR(1U) 4921 4922 #define S_ARB1_PAR_WRQUEUE_ERROR 27 4923 #define V_ARB1_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB1_PAR_WRQUEUE_ERROR) 4924 #define F_ARB1_PAR_WRQUEUE_ERROR V_ARB1_PAR_WRQUEUE_ERROR(1U) 4925 4926 #define S_ARB0_PAR_WRQUEUE_ERROR 26 4927 #define V_ARB0_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB0_PAR_WRQUEUE_ERROR) 4928 #define F_ARB0_PAR_WRQUEUE_ERROR V_ARB0_PAR_WRQUEUE_ERROR(1U) 4929 4930 #define S_ARB3_PAR_RDQUEUE_ERROR 25 4931 #define V_ARB3_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB3_PAR_RDQUEUE_ERROR) 4932 #define F_ARB3_PAR_RDQUEUE_ERROR V_ARB3_PAR_RDQUEUE_ERROR(1U) 4933 4934 #define S_ARB2_PAR_RDQUEUE_ERROR 24 4935 #define V_ARB2_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB2_PAR_RDQUEUE_ERROR) 4936 #define F_ARB2_PAR_RDQUEUE_ERROR V_ARB2_PAR_RDQUEUE_ERROR(1U) 4937 4938 #define S_ARB1_PAR_RDQUEUE_ERROR 23 4939 #define V_ARB1_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB1_PAR_RDQUEUE_ERROR) 4940 #define F_ARB1_PAR_RDQUEUE_ERROR V_ARB1_PAR_RDQUEUE_ERROR(1U) 4941 4942 #define S_ARB0_PAR_RDQUEUE_ERROR 22 4943 #define V_ARB0_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB0_PAR_RDQUEUE_ERROR) 4944 #define F_ARB0_PAR_RDQUEUE_ERROR V_ARB0_PAR_RDQUEUE_ERROR(1U) 4945 4946 #define S_CL10_PAR_WRQUEUE_ERROR 21 4947 #define V_CL10_PAR_WRQUEUE_ERROR(x) ((x) << S_CL10_PAR_WRQUEUE_ERROR) 4948 #define F_CL10_PAR_WRQUEUE_ERROR V_CL10_PAR_WRQUEUE_ERROR(1U) 4949 4950 #define S_CL9_PAR_WRQUEUE_ERROR 20 4951 #define V_CL9_PAR_WRQUEUE_ERROR(x) ((x) << S_CL9_PAR_WRQUEUE_ERROR) 4952 #define F_CL9_PAR_WRQUEUE_ERROR V_CL9_PAR_WRQUEUE_ERROR(1U) 4953 4954 #define S_CL8_PAR_WRQUEUE_ERROR 19 4955 #define V_CL8_PAR_WRQUEUE_ERROR(x) ((x) << S_CL8_PAR_WRQUEUE_ERROR) 4956 #define F_CL8_PAR_WRQUEUE_ERROR V_CL8_PAR_WRQUEUE_ERROR(1U) 4957 4958 #define S_CL7_PAR_WRQUEUE_ERROR 18 4959 #define V_CL7_PAR_WRQUEUE_ERROR(x) ((x) << S_CL7_PAR_WRQUEUE_ERROR) 4960 #define F_CL7_PAR_WRQUEUE_ERROR V_CL7_PAR_WRQUEUE_ERROR(1U) 4961 4962 #define S_CL6_PAR_WRQUEUE_ERROR 17 4963 #define V_CL6_PAR_WRQUEUE_ERROR(x) ((x) << S_CL6_PAR_WRQUEUE_ERROR) 4964 #define F_CL6_PAR_WRQUEUE_ERROR V_CL6_PAR_WRQUEUE_ERROR(1U) 4965 4966 #define S_CL5_PAR_WRQUEUE_ERROR 16 4967 #define V_CL5_PAR_WRQUEUE_ERROR(x) ((x) << S_CL5_PAR_WRQUEUE_ERROR) 4968 #define F_CL5_PAR_WRQUEUE_ERROR V_CL5_PAR_WRQUEUE_ERROR(1U) 4969 4970 #define S_CL4_PAR_WRQUEUE_ERROR 15 4971 #define V_CL4_PAR_WRQUEUE_ERROR(x) ((x) << S_CL4_PAR_WRQUEUE_ERROR) 4972 #define F_CL4_PAR_WRQUEUE_ERROR V_CL4_PAR_WRQUEUE_ERROR(1U) 4973 4974 #define S_CL3_PAR_WRQUEUE_ERROR 14 4975 #define V_CL3_PAR_WRQUEUE_ERROR(x) ((x) << S_CL3_PAR_WRQUEUE_ERROR) 4976 #define F_CL3_PAR_WRQUEUE_ERROR V_CL3_PAR_WRQUEUE_ERROR(1U) 4977 4978 #define S_CL2_PAR_WRQUEUE_ERROR 13 4979 #define V_CL2_PAR_WRQUEUE_ERROR(x) ((x) << S_CL2_PAR_WRQUEUE_ERROR) 4980 #define F_CL2_PAR_WRQUEUE_ERROR V_CL2_PAR_WRQUEUE_ERROR(1U) 4981 4982 #define S_CL1_PAR_WRQUEUE_ERROR 12 4983 #define V_CL1_PAR_WRQUEUE_ERROR(x) ((x) << S_CL1_PAR_WRQUEUE_ERROR) 4984 #define F_CL1_PAR_WRQUEUE_ERROR V_CL1_PAR_WRQUEUE_ERROR(1U) 4985 4986 #define S_CL0_PAR_WRQUEUE_ERROR 11 4987 #define V_CL0_PAR_WRQUEUE_ERROR(x) ((x) << S_CL0_PAR_WRQUEUE_ERROR) 4988 #define F_CL0_PAR_WRQUEUE_ERROR V_CL0_PAR_WRQUEUE_ERROR(1U) 4989 4990 #define S_CL10_PAR_RDQUEUE_ERROR 10 4991 #define V_CL10_PAR_RDQUEUE_ERROR(x) ((x) << S_CL10_PAR_RDQUEUE_ERROR) 4992 #define F_CL10_PAR_RDQUEUE_ERROR V_CL10_PAR_RDQUEUE_ERROR(1U) 4993 4994 #define S_CL9_PAR_RDQUEUE_ERROR 9 4995 #define V_CL9_PAR_RDQUEUE_ERROR(x) ((x) << S_CL9_PAR_RDQUEUE_ERROR) 4996 #define F_CL9_PAR_RDQUEUE_ERROR V_CL9_PAR_RDQUEUE_ERROR(1U) 4997 4998 #define S_CL8_PAR_RDQUEUE_ERROR 8 4999 #define V_CL8_PAR_RDQUEUE_ERROR(x) ((x) << S_CL8_PAR_RDQUEUE_ERROR) 5000 #define F_CL8_PAR_RDQUEUE_ERROR V_CL8_PAR_RDQUEUE_ERROR(1U) 5001 5002 #define S_CL7_PAR_RDQUEUE_ERROR 7 5003 #define V_CL7_PAR_RDQUEUE_ERROR(x) ((x) << S_CL7_PAR_RDQUEUE_ERROR) 5004 #define F_CL7_PAR_RDQUEUE_ERROR V_CL7_PAR_RDQUEUE_ERROR(1U) 5005 5006 #define S_CL6_PAR_RDQUEUE_ERROR 6 5007 #define V_CL6_PAR_RDQUEUE_ERROR(x) ((x) << S_CL6_PAR_RDQUEUE_ERROR) 5008 #define F_CL6_PAR_RDQUEUE_ERROR V_CL6_PAR_RDQUEUE_ERROR(1U) 5009 5010 #define S_CL5_PAR_RDQUEUE_ERROR 5 5011 #define V_CL5_PAR_RDQUEUE_ERROR(x) ((x) << S_CL5_PAR_RDQUEUE_ERROR) 5012 #define F_CL5_PAR_RDQUEUE_ERROR V_CL5_PAR_RDQUEUE_ERROR(1U) 5013 5014 #define S_CL4_PAR_RDQUEUE_ERROR 4 5015 #define V_CL4_PAR_RDQUEUE_ERROR(x) ((x) << S_CL4_PAR_RDQUEUE_ERROR) 5016 #define F_CL4_PAR_RDQUEUE_ERROR V_CL4_PAR_RDQUEUE_ERROR(1U) 5017 5018 #define S_CL3_PAR_RDQUEUE_ERROR 3 5019 #define V_CL3_PAR_RDQUEUE_ERROR(x) ((x) << S_CL3_PAR_RDQUEUE_ERROR) 5020 #define F_CL3_PAR_RDQUEUE_ERROR V_CL3_PAR_RDQUEUE_ERROR(1U) 5021 5022 #define S_CL2_PAR_RDQUEUE_ERROR 2 5023 #define V_CL2_PAR_RDQUEUE_ERROR(x) ((x) << S_CL2_PAR_RDQUEUE_ERROR) 5024 #define F_CL2_PAR_RDQUEUE_ERROR V_CL2_PAR_RDQUEUE_ERROR(1U) 5025 5026 #define S_CL1_PAR_RDQUEUE_ERROR 1 5027 #define V_CL1_PAR_RDQUEUE_ERROR(x) ((x) << S_CL1_PAR_RDQUEUE_ERROR) 5028 #define F_CL1_PAR_RDQUEUE_ERROR V_CL1_PAR_RDQUEUE_ERROR(1U) 5029 5030 #define S_CL0_PAR_RDQUEUE_ERROR 0 5031 #define V_CL0_PAR_RDQUEUE_ERROR(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR) 5032 #define F_CL0_PAR_RDQUEUE_ERROR V_CL0_PAR_RDQUEUE_ERROR(1U) 5033 5034 #define A_MA_PARITY_ERROR_STATUS1 0x77f4 5035 #define A_MA_PARITY_ERROR_STATUS2 0x7804 5036 5037 #define S_ARB4_PAR_WRQUEUE_ERROR 1 5038 #define V_ARB4_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR) 5039 #define F_ARB4_PAR_WRQUEUE_ERROR V_ARB4_PAR_WRQUEUE_ERROR(1U) 5040 5041 #define S_ARB4_PAR_RDQUEUE_ERROR 0 5042 #define V_ARB4_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR) 5043 #define F_ARB4_PAR_RDQUEUE_ERROR V_ARB4_PAR_RDQUEUE_ERROR(1U) 5044 5045 #define A_MA_EXT_MEMORY1_BAR 0x7808 5046 5047 #define S_EXT_MEM1_BASE 16 5048 #define M_EXT_MEM1_BASE 0xfffU 5049 #define V_EXT_MEM1_BASE(x) ((x) << S_EXT_MEM1_BASE) 5050 #define G_EXT_MEM1_BASE(x) (((x) >> S_EXT_MEM1_BASE) & M_EXT_MEM1_BASE) 5051 5052 #define S_EXT_MEM1_SIZE 0 5053 #define M_EXT_MEM1_SIZE 0xfffU 5054 #define V_EXT_MEM1_SIZE(x) ((x) << S_EXT_MEM1_SIZE) 5055 #define G_EXT_MEM1_SIZE(x) (((x) >> S_EXT_MEM1_SIZE) & M_EXT_MEM1_SIZE) 5056 5057 #define A_MA_LOCAL_DEBUG_CFG 0x78f8 5058 5059 #define S_DEBUG_OR 15 5060 #define V_DEBUG_OR(x) ((x) << S_DEBUG_OR) 5061 #define F_DEBUG_OR V_DEBUG_OR(1U) 5062 5063 #define S_DEBUG_HI 14 5064 #define V_DEBUG_HI(x) ((x) << S_DEBUG_HI) 5065 #define F_DEBUG_HI V_DEBUG_HI(1U) 5066 5067 #define S_DEBUG_RPT 13 5068 #define V_DEBUG_RPT(x) ((x) << S_DEBUG_RPT) 5069 #define F_DEBUG_RPT V_DEBUG_RPT(1U) 5070 5071 #define S_DEBUGPAGE 10 5072 #define M_DEBUGPAGE 0x7U 5073 #define V_DEBUGPAGE(x) ((x) << S_DEBUGPAGE) 5074 #define G_DEBUGPAGE(x) (((x) >> S_DEBUGPAGE) & M_DEBUGPAGE) 5075 5076 5077 /* registers for module EDC_0 */ 5078 #define EDC_0_BASE_ADDR 0x7900 5079 5080 #define A_EDC_BIST_CMD 0x7904 5081 #define A_EDC_BIST_CMD_ADDR 0x7908 5082 #define A_EDC_BIST_CMD_LEN 0x790c 5083 #define A_EDC_BIST_DATA_PATTERN 0x7910 5084 #define A_EDC_BIST_STATUS_RDATA 0x7928 5085 #define A_EDC_INT_CAUSE 0x7978 5086 5087 #define S_ECC_UE_PAR 5 5088 #define V_ECC_UE_PAR(x) ((x) << S_ECC_UE_PAR) 5089 #define F_ECC_UE_PAR V_ECC_UE_PAR(1U) 5090 5091 #define S_ECC_CE_PAR 4 5092 #define V_ECC_CE_PAR(x) ((x) << S_ECC_CE_PAR) 5093 #define F_ECC_CE_PAR V_ECC_CE_PAR(1U) 5094 5095 #define S_PERR_PAR_CAUSE 3 5096 #define V_PERR_PAR_CAUSE(x) ((x) << S_PERR_PAR_CAUSE) 5097 #define F_PERR_PAR_CAUSE V_PERR_PAR_CAUSE(1U) 5098 5099 #define A_EDC_ECC_STATUS 0x797c 5100 5101 /* registers for module EDC_1 */ 5102 #define EDC_1_BASE_ADDR 0x7980 5103 5104 /* registers for module HMA */ 5105 #define HMA_BASE_ADDR 0x7a00 5106 5107 /* registers for module CIM */ 5108 #define CIM_BASE_ADDR 0x7b00 5109 5110 #define A_CIM_VF_EXT_MAILBOX_CTRL 0x0 5111 5112 #define S_VFMBGENERIC 4 5113 #define M_VFMBGENERIC 0xfU 5114 #define V_VFMBGENERIC(x) ((x) << S_VFMBGENERIC) 5115 #define G_VFMBGENERIC(x) (((x) >> S_VFMBGENERIC) & M_VFMBGENERIC) 5116 5117 #define A_CIM_VF_EXT_MAILBOX_STATUS 0x4 5118 5119 #define S_MBVFREADY 0 5120 #define V_MBVFREADY(x) ((x) << S_MBVFREADY) 5121 #define F_MBVFREADY V_MBVFREADY(1U) 5122 5123 #define A_CIM_PF_MAILBOX_DATA 0x240 5124 #define A_CIM_PF_MAILBOX_CTRL 0x280 5125 5126 #define S_MBGENERIC 4 5127 #define M_MBGENERIC 0xfffffffU 5128 #define V_MBGENERIC(x) ((x) << S_MBGENERIC) 5129 #define G_MBGENERIC(x) (((x) >> S_MBGENERIC) & M_MBGENERIC) 5130 5131 #define S_MBMSGVALID 3 5132 #define V_MBMSGVALID(x) ((x) << S_MBMSGVALID) 5133 #define F_MBMSGVALID V_MBMSGVALID(1U) 5134 5135 #define S_MBINTREQ 2 5136 #define V_MBINTREQ(x) ((x) << S_MBINTREQ) 5137 #define F_MBINTREQ V_MBINTREQ(1U) 5138 5139 #define S_MBOWNER 0 5140 #define M_MBOWNER 0x3U 5141 #define V_MBOWNER(x) ((x) << S_MBOWNER) 5142 #define G_MBOWNER(x) (((x) >> S_MBOWNER) & M_MBOWNER) 5143 5144 #define A_CIM_PF_HOST_INT_ENABLE 0x288 5145 5146 #define S_MBMSGRDYINTEN 19 5147 #define V_MBMSGRDYINTEN(x) ((x) << S_MBMSGRDYINTEN) 5148 #define F_MBMSGRDYINTEN V_MBMSGRDYINTEN(1U) 5149 5150 #define A_CIM_PF_HOST_INT_CAUSE 0x28c 5151 5152 #define S_MBMSGRDYINT 19 5153 #define V_MBMSGRDYINT(x) ((x) << S_MBMSGRDYINT) 5154 #define F_MBMSGRDYINT V_MBMSGRDYINT(1U) 5155 5156 #define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290 5157 #define A_CIM_BOOT_CFG 0x7b00 5158 5159 #define S_BOOTADDR 8 5160 #define M_BOOTADDR 0xffffffU 5161 #define V_BOOTADDR(x) ((x) << S_BOOTADDR) 5162 #define G_BOOTADDR(x) (((x) >> S_BOOTADDR) & M_BOOTADDR) 5163 5164 #define S_UPGEN 2 5165 #define M_UPGEN 0x3fU 5166 #define V_UPGEN(x) ((x) << S_UPGEN) 5167 #define G_UPGEN(x) (((x) >> S_UPGEN) & M_UPGEN) 5168 5169 #define S_BOOTSDRAM 1 5170 #define V_BOOTSDRAM(x) ((x) << S_BOOTSDRAM) 5171 #define F_BOOTSDRAM V_BOOTSDRAM(1U) 5172 5173 #define S_UPCRST 0 5174 #define V_UPCRST(x) ((x) << S_UPCRST) 5175 #define F_UPCRST V_UPCRST(1U) 5176 5177 #define A_CIM_SDRAM_BASE_ADDR 0x7b14 5178 5179 #define S_SDRAMBASEADDR 6 5180 #define M_SDRAMBASEADDR 0x3ffffffU 5181 #define V_SDRAMBASEADDR(x) ((x) << S_SDRAMBASEADDR) 5182 #define G_SDRAMBASEADDR(x) (((x) >> S_SDRAMBASEADDR) & M_SDRAMBASEADDR) 5183 5184 #define A_CIM_SDRAM_ADDR_SIZE 0x7b18 5185 5186 #define S_SDRAMADDRSIZE 4 5187 #define M_SDRAMADDRSIZE 0xfffffffU 5188 #define V_SDRAMADDRSIZE(x) ((x) << S_SDRAMADDRSIZE) 5189 #define G_SDRAMADDRSIZE(x) (((x) >> S_SDRAMADDRSIZE) & M_SDRAMADDRSIZE) 5190 5191 #define A_CIM_EXTMEM2_BASE_ADDR 0x7b1c 5192 5193 #define S_EXTMEM2BASEADDR 6 5194 #define M_EXTMEM2BASEADDR 0x3ffffffU 5195 #define V_EXTMEM2BASEADDR(x) ((x) << S_EXTMEM2BASEADDR) 5196 #define G_EXTMEM2BASEADDR(x) (((x) >> S_EXTMEM2BASEADDR) & M_EXTMEM2BASEADDR) 5197 5198 #define A_CIM_EXTMEM2_ADDR_SIZE 0x7b20 5199 5200 #define S_EXTMEM2ADDRSIZE 4 5201 #define M_EXTMEM2ADDRSIZE 0xfffffffU 5202 #define V_EXTMEM2ADDRSIZE(x) ((x) << S_EXTMEM2ADDRSIZE) 5203 #define G_EXTMEM2ADDRSIZE(x) (((x) >> S_EXTMEM2ADDRSIZE) & M_EXTMEM2ADDRSIZE) 5204 5205 #define A_CIM_HOST_INT_CAUSE 0x7b2c 5206 5207 #define S_TIEQOUTPARERRINT 20 5208 #define V_TIEQOUTPARERRINT(x) ((x) << S_TIEQOUTPARERRINT) 5209 #define F_TIEQOUTPARERRINT V_TIEQOUTPARERRINT(1U) 5210 5211 #define S_TIEQINPARERRINT 19 5212 #define V_TIEQINPARERRINT(x) ((x) << S_TIEQINPARERRINT) 5213 #define F_TIEQINPARERRINT V_TIEQINPARERRINT(1U) 5214 5215 #define S_MBHOSTPARERR 18 5216 #define V_MBHOSTPARERR(x) ((x) << S_MBHOSTPARERR) 5217 #define F_MBHOSTPARERR V_MBHOSTPARERR(1U) 5218 5219 #define S_MBUPPARERR 17 5220 #define V_MBUPPARERR(x) ((x) << S_MBUPPARERR) 5221 #define F_MBUPPARERR V_MBUPPARERR(1U) 5222 5223 #define S_IBQTP0PARERR 16 5224 #define V_IBQTP0PARERR(x) ((x) << S_IBQTP0PARERR) 5225 #define F_IBQTP0PARERR V_IBQTP0PARERR(1U) 5226 5227 #define S_IBQTP1PARERR 15 5228 #define V_IBQTP1PARERR(x) ((x) << S_IBQTP1PARERR) 5229 #define F_IBQTP1PARERR V_IBQTP1PARERR(1U) 5230 5231 #define S_IBQULPPARERR 14 5232 #define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR) 5233 #define F_IBQULPPARERR V_IBQULPPARERR(1U) 5234 5235 #define S_IBQSGELOPARERR 13 5236 #define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR) 5237 #define F_IBQSGELOPARERR V_IBQSGELOPARERR(1U) 5238 5239 #define S_IBQSGEHIPARERR 12 5240 #define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR) 5241 #define F_IBQSGEHIPARERR V_IBQSGEHIPARERR(1U) 5242 5243 #define S_IBQNCSIPARERR 11 5244 #define V_IBQNCSIPARERR(x) ((x) << S_IBQNCSIPARERR) 5245 #define F_IBQNCSIPARERR V_IBQNCSIPARERR(1U) 5246 5247 #define S_OBQULP0PARERR 10 5248 #define V_OBQULP0PARERR(x) ((x) << S_OBQULP0PARERR) 5249 #define F_OBQULP0PARERR V_OBQULP0PARERR(1U) 5250 5251 #define S_OBQULP1PARERR 9 5252 #define V_OBQULP1PARERR(x) ((x) << S_OBQULP1PARERR) 5253 #define F_OBQULP1PARERR V_OBQULP1PARERR(1U) 5254 5255 #define S_OBQULP2PARERR 8 5256 #define V_OBQULP2PARERR(x) ((x) << S_OBQULP2PARERR) 5257 #define F_OBQULP2PARERR V_OBQULP2PARERR(1U) 5258 5259 #define S_OBQULP3PARERR 7 5260 #define V_OBQULP3PARERR(x) ((x) << S_OBQULP3PARERR) 5261 #define F_OBQULP3PARERR V_OBQULP3PARERR(1U) 5262 5263 #define S_OBQSGEPARERR 6 5264 #define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR) 5265 #define F_OBQSGEPARERR V_OBQSGEPARERR(1U) 5266 5267 #define S_OBQNCSIPARERR 5 5268 #define V_OBQNCSIPARERR(x) ((x) << S_OBQNCSIPARERR) 5269 #define F_OBQNCSIPARERR V_OBQNCSIPARERR(1U) 5270 5271 #define S_TIMER1INT 3 5272 #define V_TIMER1INT(x) ((x) << S_TIMER1INT) 5273 #define F_TIMER1INT V_TIMER1INT(1U) 5274 5275 #define S_TIMER0INT 2 5276 #define V_TIMER0INT(x) ((x) << S_TIMER0INT) 5277 #define F_TIMER0INT V_TIMER0INT(1U) 5278 5279 #define S_PREFDROPINT 1 5280 #define V_PREFDROPINT(x) ((x) << S_PREFDROPINT) 5281 #define F_PREFDROPINT V_PREFDROPINT(1U) 5282 5283 #define S_UPACCNONZERO 0 5284 #define V_UPACCNONZERO(x) ((x) << S_UPACCNONZERO) 5285 #define F_UPACCNONZERO V_UPACCNONZERO(1U) 5286 5287 #define S_MA_CIM_INTFPERR 28 5288 #define V_MA_CIM_INTFPERR(x) ((x) << S_MA_CIM_INTFPERR) 5289 #define F_MA_CIM_INTFPERR V_MA_CIM_INTFPERR(1U) 5290 5291 #define S_PLCIM_MSTRSPDATAPARERR 27 5292 #define V_PLCIM_MSTRSPDATAPARERR(x) ((x) << S_PLCIM_MSTRSPDATAPARERR) 5293 #define F_PLCIM_MSTRSPDATAPARERR V_PLCIM_MSTRSPDATAPARERR(1U) 5294 5295 #define S_NCSI2CIMINTFPARERR 26 5296 #define V_NCSI2CIMINTFPARERR(x) ((x) << S_NCSI2CIMINTFPARERR) 5297 #define F_NCSI2CIMINTFPARERR V_NCSI2CIMINTFPARERR(1U) 5298 5299 #define S_SGE2CIMINTFPARERR 25 5300 #define V_SGE2CIMINTFPARERR(x) ((x) << S_SGE2CIMINTFPARERR) 5301 #define F_SGE2CIMINTFPARERR V_SGE2CIMINTFPARERR(1U) 5302 5303 #define S_ULP2CIMINTFPARERR 24 5304 #define V_ULP2CIMINTFPARERR(x) ((x) << S_ULP2CIMINTFPARERR) 5305 #define F_ULP2CIMINTFPARERR V_ULP2CIMINTFPARERR(1U) 5306 5307 #define S_TP2CIMINTFPARERR 23 5308 #define V_TP2CIMINTFPARERR(x) ((x) << S_TP2CIMINTFPARERR) 5309 #define F_TP2CIMINTFPARERR V_TP2CIMINTFPARERR(1U) 5310 5311 #define S_OBQSGERX1PARERR 22 5312 #define V_OBQSGERX1PARERR(x) ((x) << S_OBQSGERX1PARERR) 5313 #define F_OBQSGERX1PARERR V_OBQSGERX1PARERR(1U) 5314 5315 #define S_OBQSGERX0PARERR 21 5316 #define V_OBQSGERX0PARERR(x) ((x) << S_OBQSGERX0PARERR) 5317 #define F_OBQSGERX0PARERR V_OBQSGERX0PARERR(1U) 5318 5319 #define S_PCIE2CIMINTFPARERR 29 5320 #define V_PCIE2CIMINTFPARERR(x) ((x) << S_PCIE2CIMINTFPARERR) 5321 #define F_PCIE2CIMINTFPARERR V_PCIE2CIMINTFPARERR(1U) 5322 5323 #define S_IBQPCIEPARERR 12 5324 #define V_IBQPCIEPARERR(x) ((x) << S_IBQPCIEPARERR) 5325 #define F_IBQPCIEPARERR V_IBQPCIEPARERR(1U) 5326 5327 #define A_CIM_HOST_UPACC_INT_CAUSE 0x7b34 5328 5329 #define S_EEPROMWRINT 30 5330 #define V_EEPROMWRINT(x) ((x) << S_EEPROMWRINT) 5331 #define F_EEPROMWRINT V_EEPROMWRINT(1U) 5332 5333 #define S_TIMEOUTMAINT 29 5334 #define V_TIMEOUTMAINT(x) ((x) << S_TIMEOUTMAINT) 5335 #define F_TIMEOUTMAINT V_TIMEOUTMAINT(1U) 5336 5337 #define S_TIMEOUTINT 28 5338 #define V_TIMEOUTINT(x) ((x) << S_TIMEOUTINT) 5339 #define F_TIMEOUTINT V_TIMEOUTINT(1U) 5340 5341 #define S_RSPOVRLOOKUPINT 27 5342 #define V_RSPOVRLOOKUPINT(x) ((x) << S_RSPOVRLOOKUPINT) 5343 #define F_RSPOVRLOOKUPINT V_RSPOVRLOOKUPINT(1U) 5344 5345 #define S_REQOVRLOOKUPINT 26 5346 #define V_REQOVRLOOKUPINT(x) ((x) << S_REQOVRLOOKUPINT) 5347 #define F_REQOVRLOOKUPINT V_REQOVRLOOKUPINT(1U) 5348 5349 #define S_BLKWRPLINT 25 5350 #define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT) 5351 #define F_BLKWRPLINT V_BLKWRPLINT(1U) 5352 5353 #define S_BLKRDPLINT 24 5354 #define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT) 5355 #define F_BLKRDPLINT V_BLKRDPLINT(1U) 5356 5357 #define S_SGLWRPLINT 23 5358 #define V_SGLWRPLINT(x) ((x) << S_SGLWRPLINT) 5359 #define F_SGLWRPLINT V_SGLWRPLINT(1U) 5360 5361 #define S_SGLRDPLINT 22 5362 #define V_SGLRDPLINT(x) ((x) << S_SGLRDPLINT) 5363 #define F_SGLRDPLINT V_SGLRDPLINT(1U) 5364 5365 #define S_BLKWRCTLINT 21 5366 #define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT) 5367 #define F_BLKWRCTLINT V_BLKWRCTLINT(1U) 5368 5369 #define S_BLKRDCTLINT 20 5370 #define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT) 5371 #define F_BLKRDCTLINT V_BLKRDCTLINT(1U) 5372 5373 #define S_SGLWRCTLINT 19 5374 #define V_SGLWRCTLINT(x) ((x) << S_SGLWRCTLINT) 5375 #define F_SGLWRCTLINT V_SGLWRCTLINT(1U) 5376 5377 #define S_SGLRDCTLINT 18 5378 #define V_SGLRDCTLINT(x) ((x) << S_SGLRDCTLINT) 5379 #define F_SGLRDCTLINT V_SGLRDCTLINT(1U) 5380 5381 #define S_BLKWREEPROMINT 17 5382 #define V_BLKWREEPROMINT(x) ((x) << S_BLKWREEPROMINT) 5383 #define F_BLKWREEPROMINT V_BLKWREEPROMINT(1U) 5384 5385 #define S_BLKRDEEPROMINT 16 5386 #define V_BLKRDEEPROMINT(x) ((x) << S_BLKRDEEPROMINT) 5387 #define F_BLKRDEEPROMINT V_BLKRDEEPROMINT(1U) 5388 5389 #define S_SGLWREEPROMINT 15 5390 #define V_SGLWREEPROMINT(x) ((x) << S_SGLWREEPROMINT) 5391 #define F_SGLWREEPROMINT V_SGLWREEPROMINT(1U) 5392 5393 #define S_SGLRDEEPROMINT 14 5394 #define V_SGLRDEEPROMINT(x) ((x) << S_SGLRDEEPROMINT) 5395 #define F_SGLRDEEPROMINT V_SGLRDEEPROMINT(1U) 5396 5397 #define S_BLKWRFLASHINT 13 5398 #define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT) 5399 #define F_BLKWRFLASHINT V_BLKWRFLASHINT(1U) 5400 5401 #define S_BLKRDFLASHINT 12 5402 #define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT) 5403 #define F_BLKRDFLASHINT V_BLKRDFLASHINT(1U) 5404 5405 #define S_SGLWRFLASHINT 11 5406 #define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT) 5407 #define F_SGLWRFLASHINT V_SGLWRFLASHINT(1U) 5408 5409 #define S_SGLRDFLASHINT 10 5410 #define V_SGLRDFLASHINT(x) ((x) << S_SGLRDFLASHINT) 5411 #define F_SGLRDFLASHINT V_SGLRDFLASHINT(1U) 5412 5413 #define S_BLKWRBOOTINT 9 5414 #define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT) 5415 #define F_BLKWRBOOTINT V_BLKWRBOOTINT(1U) 5416 5417 #define S_BLKRDBOOTINT 8 5418 #define V_BLKRDBOOTINT(x) ((x) << S_BLKRDBOOTINT) 5419 #define F_BLKRDBOOTINT V_BLKRDBOOTINT(1U) 5420 5421 #define S_SGLWRBOOTINT 7 5422 #define V_SGLWRBOOTINT(x) ((x) << S_SGLWRBOOTINT) 5423 #define F_SGLWRBOOTINT V_SGLWRBOOTINT(1U) 5424 5425 #define S_SGLRDBOOTINT 6 5426 #define V_SGLRDBOOTINT(x) ((x) << S_SGLRDBOOTINT) 5427 #define F_SGLRDBOOTINT V_SGLRDBOOTINT(1U) 5428 5429 #define S_ILLWRBEINT 5 5430 #define V_ILLWRBEINT(x) ((x) << S_ILLWRBEINT) 5431 #define F_ILLWRBEINT V_ILLWRBEINT(1U) 5432 5433 #define S_ILLRDBEINT 4 5434 #define V_ILLRDBEINT(x) ((x) << S_ILLRDBEINT) 5435 #define F_ILLRDBEINT V_ILLRDBEINT(1U) 5436 5437 #define S_ILLRDINT 3 5438 #define V_ILLRDINT(x) ((x) << S_ILLRDINT) 5439 #define F_ILLRDINT V_ILLRDINT(1U) 5440 5441 #define S_ILLWRINT 2 5442 #define V_ILLWRINT(x) ((x) << S_ILLWRINT) 5443 #define F_ILLWRINT V_ILLWRINT(1U) 5444 5445 #define S_ILLTRANSINT 1 5446 #define V_ILLTRANSINT(x) ((x) << S_ILLTRANSINT) 5447 #define F_ILLTRANSINT V_ILLTRANSINT(1U) 5448 5449 #define S_RSVDSPACEINT 0 5450 #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT) 5451 #define F_RSVDSPACEINT V_RSVDSPACEINT(1U) 5452 5453 #define A_CIM_QUEUE_CONFIG_REF 0x7b48 5454 5455 #define S_OBQSELECT 4 5456 #define V_OBQSELECT(x) ((x) << S_OBQSELECT) 5457 #define F_OBQSELECT V_OBQSELECT(1U) 5458 5459 #define S_IBQSELECT 3 5460 #define V_IBQSELECT(x) ((x) << S_IBQSELECT) 5461 #define F_IBQSELECT V_IBQSELECT(1U) 5462 5463 #define S_QUENUMSELECT 0 5464 #define M_QUENUMSELECT 0x7U 5465 #define V_QUENUMSELECT(x) ((x) << S_QUENUMSELECT) 5466 #define G_QUENUMSELECT(x) (((x) >> S_QUENUMSELECT) & M_QUENUMSELECT) 5467 5468 #define A_CIM_QUEUE_CONFIG_CTRL 0x7b4c 5469 5470 #define S_CIMQSIZE 24 5471 #define M_CIMQSIZE 0x3fU 5472 #define V_CIMQSIZE(x) ((x) << S_CIMQSIZE) 5473 #define G_CIMQSIZE(x) (((x) >> S_CIMQSIZE) & M_CIMQSIZE) 5474 5475 #define S_CIMQBASE 16 5476 #define M_CIMQBASE 0x3fU 5477 #define V_CIMQBASE(x) ((x) << S_CIMQBASE) 5478 #define G_CIMQBASE(x) (((x) >> S_CIMQBASE) & M_CIMQBASE) 5479 5480 #define S_CIMQDBG8BEN 9 5481 #define V_CIMQDBG8BEN(x) ((x) << S_CIMQDBG8BEN) 5482 #define F_CIMQDBG8BEN V_CIMQDBG8BEN(1U) 5483 5484 #define S_QUEFULLTHRSH 0 5485 #define M_QUEFULLTHRSH 0x1ffU 5486 #define V_QUEFULLTHRSH(x) ((x) << S_QUEFULLTHRSH) 5487 #define G_QUEFULLTHRSH(x) (((x) >> S_QUEFULLTHRSH) & M_QUEFULLTHRSH) 5488 5489 #define S_CIMQ1KEN 30 5490 #define V_CIMQ1KEN(x) ((x) << S_CIMQ1KEN) 5491 #define F_CIMQ1KEN V_CIMQ1KEN(1U) 5492 5493 #define A_CIM_HOST_ACC_CTRL 0x7b50 5494 5495 #define S_HOSTBUSY 17 5496 #define V_HOSTBUSY(x) ((x) << S_HOSTBUSY) 5497 #define F_HOSTBUSY V_HOSTBUSY(1U) 5498 5499 #define S_HOSTWRITE 16 5500 #define V_HOSTWRITE(x) ((x) << S_HOSTWRITE) 5501 #define F_HOSTWRITE V_HOSTWRITE(1U) 5502 5503 #define S_HOSTADDR 0 5504 #define M_HOSTADDR 0xffffU 5505 #define V_HOSTADDR(x) ((x) << S_HOSTADDR) 5506 #define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR) 5507 5508 #define A_CIM_HOST_ACC_DATA 0x7b54 5509 #define A_CIM_IBQ_DBG_CFG 0x7b60 5510 5511 #define S_IBQDBGADDR 16 5512 #define M_IBQDBGADDR 0xfffU 5513 #define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR) 5514 #define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR) 5515 5516 #define S_IBQDBGWR 2 5517 #define V_IBQDBGWR(x) ((x) << S_IBQDBGWR) 5518 #define F_IBQDBGWR V_IBQDBGWR(1U) 5519 5520 #define S_IBQDBGBUSY 1 5521 #define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY) 5522 #define F_IBQDBGBUSY V_IBQDBGBUSY(1U) 5523 5524 #define S_IBQDBGEN 0 5525 #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN) 5526 #define F_IBQDBGEN V_IBQDBGEN(1U) 5527 5528 #define A_CIM_OBQ_DBG_CFG 0x7b64 5529 5530 #define S_OBQDBGADDR 16 5531 #define M_OBQDBGADDR 0xfffU 5532 #define V_OBQDBGADDR(x) ((x) << S_OBQDBGADDR) 5533 #define G_OBQDBGADDR(x) (((x) >> S_OBQDBGADDR) & M_OBQDBGADDR) 5534 5535 #define S_OBQDBGWR 2 5536 #define V_OBQDBGWR(x) ((x) << S_OBQDBGWR) 5537 #define F_OBQDBGWR V_OBQDBGWR(1U) 5538 5539 #define S_OBQDBGBUSY 1 5540 #define V_OBQDBGBUSY(x) ((x) << S_OBQDBGBUSY) 5541 #define F_OBQDBGBUSY V_OBQDBGBUSY(1U) 5542 5543 #define S_OBQDBGEN 0 5544 #define V_OBQDBGEN(x) ((x) << S_OBQDBGEN) 5545 #define F_OBQDBGEN V_OBQDBGEN(1U) 5546 5547 #define A_CIM_IBQ_DBG_DATA 0x7b68 5548 #define A_CIM_OBQ_DBG_DATA 0x7b6c 5549 #define A_CIM_DEBUGCFG 0x7b70 5550 5551 #define S_POLADBGRDPTR 23 5552 #define M_POLADBGRDPTR 0x1ffU 5553 #define V_POLADBGRDPTR(x) ((x) << S_POLADBGRDPTR) 5554 #define G_POLADBGRDPTR(x) (((x) >> S_POLADBGRDPTR) & M_POLADBGRDPTR) 5555 5556 #define S_PILADBGRDPTR 14 5557 #define M_PILADBGRDPTR 0x1ffU 5558 #define V_PILADBGRDPTR(x) ((x) << S_PILADBGRDPTR) 5559 #define G_PILADBGRDPTR(x) (((x) >> S_PILADBGRDPTR) & M_PILADBGRDPTR) 5560 5561 #define S_LAMASKTRIG 13 5562 #define V_LAMASKTRIG(x) ((x) << S_LAMASKTRIG) 5563 #define F_LAMASKTRIG V_LAMASKTRIG(1U) 5564 5565 #define S_LADBGEN 12 5566 #define V_LADBGEN(x) ((x) << S_LADBGEN) 5567 #define F_LADBGEN V_LADBGEN(1U) 5568 5569 #define S_LAFILLONCE 11 5570 #define V_LAFILLONCE(x) ((x) << S_LAFILLONCE) 5571 #define F_LAFILLONCE V_LAFILLONCE(1U) 5572 5573 #define S_LAMASKSTOP 10 5574 #define V_LAMASKSTOP(x) ((x) << S_LAMASKSTOP) 5575 #define F_LAMASKSTOP V_LAMASKSTOP(1U) 5576 5577 #define S_DEBUGSELH 5 5578 #define M_DEBUGSELH 0x1fU 5579 #define V_DEBUGSELH(x) ((x) << S_DEBUGSELH) 5580 #define G_DEBUGSELH(x) (((x) >> S_DEBUGSELH) & M_DEBUGSELH) 5581 5582 #define S_DEBUGSELL 0 5583 #define M_DEBUGSELL 0x1fU 5584 #define V_DEBUGSELL(x) ((x) << S_DEBUGSELL) 5585 #define G_DEBUGSELL(x) (((x) >> S_DEBUGSELL) & M_DEBUGSELL) 5586 5587 #define A_CIM_DEBUGSTS 0x7b74 5588 5589 #define S_LARESET 31 5590 #define V_LARESET(x) ((x) << S_LARESET) 5591 #define F_LARESET V_LARESET(1U) 5592 5593 #define S_POLADBGWRPTR 16 5594 #define M_POLADBGWRPTR 0x1ffU 5595 #define V_POLADBGWRPTR(x) ((x) << S_POLADBGWRPTR) 5596 #define G_POLADBGWRPTR(x) (((x) >> S_POLADBGWRPTR) & M_POLADBGWRPTR) 5597 5598 #define S_PILADBGWRPTR 0 5599 #define M_PILADBGWRPTR 0x1ffU 5600 #define V_PILADBGWRPTR(x) ((x) << S_PILADBGWRPTR) 5601 #define G_PILADBGWRPTR(x) (((x) >> S_PILADBGWRPTR) & M_PILADBGWRPTR) 5602 5603 #define A_CIM_PO_LA_DEBUGDATA 0x7b78 5604 #define A_CIM_PI_LA_DEBUGDATA 0x7b7c 5605 #define A_CIM_PO_LA_MADEBUGDATA 0x7b80 5606 #define A_CIM_PI_LA_MADEBUGDATA 0x7b84 5607 #define A_CIM_DEBUG_ADDR_ILLEGAL 0x7c0c 5608 5609 #define S_DADDRILLEGAL 2 5610 #define M_DADDRILLEGAL 0x3fffffffU 5611 #define V_DADDRILLEGAL(x) ((x) << S_DADDRILLEGAL) 5612 #define G_DADDRILLEGAL(x) (((x) >> S_DADDRILLEGAL) & M_DADDRILLEGAL) 5613 5614 #define S_DADDRILLEGALTYPE 0 5615 #define M_DADDRILLEGALTYPE 0x3U 5616 #define V_DADDRILLEGALTYPE(x) ((x) << S_DADDRILLEGALTYPE) 5617 #define G_DADDRILLEGALTYPE(x) (((x) >> S_DADDRILLEGALTYPE) & M_DADDRILLEGALTYPE) 5618 5619 #define A_CIM_UP_OPERATION_FREQ 0x7c38 5620 5621 /* registers for module TP */ 5622 #define TP_BASE_ADDR 0x7d00 5623 5624 #define A_TP_IN_CONFIG 0x7d00 5625 5626 #define S_NICMODE 14 5627 #define V_NICMODE(x) ((x) << S_NICMODE) 5628 #define F_NICMODE V_NICMODE(1U) 5629 5630 #define S_ECHECKSUMCHECKTCP 13 5631 #define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP) 5632 #define F_ECHECKSUMCHECKTCP V_ECHECKSUMCHECKTCP(1U) 5633 5634 #define S_ECHECKSUMCHECKIP 12 5635 #define V_ECHECKSUMCHECKIP(x) ((x) << S_ECHECKSUMCHECKIP) 5636 #define F_ECHECKSUMCHECKIP V_ECHECKSUMCHECKIP(1U) 5637 5638 #define A_TP_OUT_CONFIG 0x7d04 5639 5640 #define S_IPIDSPLITMODE 16 5641 #define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE) 5642 #define F_IPIDSPLITMODE V_IPIDSPLITMODE(1U) 5643 5644 #define S_VLANEXTENABLEPORT3 15 5645 #define V_VLANEXTENABLEPORT3(x) ((x) << S_VLANEXTENABLEPORT3) 5646 #define F_VLANEXTENABLEPORT3 V_VLANEXTENABLEPORT3(1U) 5647 5648 #define S_VLANEXTENABLEPORT2 14 5649 #define V_VLANEXTENABLEPORT2(x) ((x) << S_VLANEXTENABLEPORT2) 5650 #define F_VLANEXTENABLEPORT2 V_VLANEXTENABLEPORT2(1U) 5651 5652 #define S_VLANEXTENABLEPORT1 13 5653 #define V_VLANEXTENABLEPORT1(x) ((x) << S_VLANEXTENABLEPORT1) 5654 #define F_VLANEXTENABLEPORT1 V_VLANEXTENABLEPORT1(1U) 5655 5656 #define S_VLANEXTENABLEPORT0 12 5657 #define V_VLANEXTENABLEPORT0(x) ((x) << S_VLANEXTENABLEPORT0) 5658 #define F_VLANEXTENABLEPORT0 V_VLANEXTENABLEPORT0(1U) 5659 5660 #define S_CRXPKTENC 3 5661 #define V_CRXPKTENC(x) ((x) << S_CRXPKTENC) 5662 #define F_CRXPKTENC V_CRXPKTENC(1U) 5663 5664 #define S_CRXPKTXT 1 5665 #define V_CRXPKTXT(x) ((x) << S_CRXPKTXT) 5666 #define F_CRXPKTXT V_CRXPKTXT(1U) 5667 5668 #define A_TP_GLOBAL_CONFIG 0x7d08 5669 5670 #define S_SYNCOOKIEPARAMS 26 5671 #define M_SYNCOOKIEPARAMS 0x3fU 5672 #define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS) 5673 #define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS) 5674 5675 #define S_RXFLOWCONTROLDISABLE 25 5676 #define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE) 5677 #define F_RXFLOWCONTROLDISABLE V_RXFLOWCONTROLDISABLE(1U) 5678 5679 #define S_TXPACINGENABLE 24 5680 #define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE) 5681 #define F_TXPACINGENABLE V_TXPACINGENABLE(1U) 5682 5683 #define S_ATTACKFILTERENABLE 23 5684 #define V_ATTACKFILTERENABLE(x) ((x) << S_ATTACKFILTERENABLE) 5685 #define F_ATTACKFILTERENABLE V_ATTACKFILTERENABLE(1U) 5686 5687 #define S_SYNCOOKIENOOPTIONS 22 5688 #define V_SYNCOOKIENOOPTIONS(x) ((x) << S_SYNCOOKIENOOPTIONS) 5689 #define F_SYNCOOKIENOOPTIONS V_SYNCOOKIENOOPTIONS(1U) 5690 5691 #define S_PROTECTEDMODE 21 5692 #define V_PROTECTEDMODE(x) ((x) << S_PROTECTEDMODE) 5693 #define F_PROTECTEDMODE V_PROTECTEDMODE(1U) 5694 5695 #define S_PINGDROP 20 5696 #define V_PINGDROP(x) ((x) << S_PINGDROP) 5697 #define F_PINGDROP V_PINGDROP(1U) 5698 5699 #define S_FRAGMENTDROP 19 5700 #define V_FRAGMENTDROP(x) ((x) << S_FRAGMENTDROP) 5701 #define F_FRAGMENTDROP V_FRAGMENTDROP(1U) 5702 5703 #define S_FIVETUPLELOOKUP 17 5704 #define M_FIVETUPLELOOKUP 0x3U 5705 #define V_FIVETUPLELOOKUP(x) ((x) << S_FIVETUPLELOOKUP) 5706 #define G_FIVETUPLELOOKUP(x) (((x) >> S_FIVETUPLELOOKUP) & M_FIVETUPLELOOKUP) 5707 5708 #define S_OFDMPSSTATS 16 5709 #define V_OFDMPSSTATS(x) ((x) << S_OFDMPSSTATS) 5710 #define F_OFDMPSSTATS V_OFDMPSSTATS(1U) 5711 5712 #define S_DONTFRAGMENT 15 5713 #define V_DONTFRAGMENT(x) ((x) << S_DONTFRAGMENT) 5714 #define F_DONTFRAGMENT V_DONTFRAGMENT(1U) 5715 5716 #define S_IPIDENTSPLIT 14 5717 #define V_IPIDENTSPLIT(x) ((x) << S_IPIDENTSPLIT) 5718 #define F_IPIDENTSPLIT V_IPIDENTSPLIT(1U) 5719 5720 #define S_IPCHECKSUMOFFLOAD 13 5721 #define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD) 5722 #define F_IPCHECKSUMOFFLOAD V_IPCHECKSUMOFFLOAD(1U) 5723 5724 #define S_UDPCHECKSUMOFFLOAD 12 5725 #define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD) 5726 #define F_UDPCHECKSUMOFFLOAD V_UDPCHECKSUMOFFLOAD(1U) 5727 5728 #define S_TCPCHECKSUMOFFLOAD 11 5729 #define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD) 5730 #define F_TCPCHECKSUMOFFLOAD V_TCPCHECKSUMOFFLOAD(1U) 5731 5732 #define S_RSSLOOPBACKENABLE 10 5733 #define V_RSSLOOPBACKENABLE(x) ((x) << S_RSSLOOPBACKENABLE) 5734 #define F_RSSLOOPBACKENABLE V_RSSLOOPBACKENABLE(1U) 5735 5736 #define S_TCAMSERVERUSE 8 5737 #define M_TCAMSERVERUSE 0x3U 5738 #define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE) 5739 #define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE) 5740 5741 #define S_IPTTL 0 5742 #define M_IPTTL 0xffU 5743 #define V_IPTTL(x) ((x) << S_IPTTL) 5744 #define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL) 5745 5746 #define S_RSSSYNSTEERENABLE 12 5747 #define V_RSSSYNSTEERENABLE(x) ((x) << S_RSSSYNSTEERENABLE) 5748 #define F_RSSSYNSTEERENABLE V_RSSSYNSTEERENABLE(1U) 5749 5750 #define S_ISSFROMCPLENABLE 11 5751 #define V_ISSFROMCPLENABLE(x) ((x) << S_ISSFROMCPLENABLE) 5752 #define F_ISSFROMCPLENABLE V_ISSFROMCPLENABLE(1U) 5753 5754 #define S_ACTIVEFILTERCOUNTS 22 5755 #define V_ACTIVEFILTERCOUNTS(x) ((x) << S_ACTIVEFILTERCOUNTS) 5756 #define F_ACTIVEFILTERCOUNTS V_ACTIVEFILTERCOUNTS(1U) 5757 5758 #define A_TP_CMM_TCB_BASE 0x7d10 5759 #define A_TP_CMM_MM_BASE 0x7d14 5760 #define A_TP_CMM_TIMER_BASE 0x7d18 5761 #define A_TP_PMM_TX_BASE 0x7d20 5762 #define A_TP_PMM_RX_BASE 0x7d28 5763 #define A_TP_PMM_RX_PAGE_SIZE 0x7d2c 5764 #define A_TP_PMM_RX_MAX_PAGE 0x7d30 5765 5766 #define S_PMRXNUMCHN 31 5767 #define V_PMRXNUMCHN(x) ((x) << S_PMRXNUMCHN) 5768 #define F_PMRXNUMCHN V_PMRXNUMCHN(1U) 5769 5770 #define S_PMRXMAXPAGE 0 5771 #define M_PMRXMAXPAGE 0x1fffffU 5772 #define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE) 5773 #define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE) 5774 5775 #define A_TP_PMM_TX_PAGE_SIZE 0x7d34 5776 #define A_TP_PMM_TX_MAX_PAGE 0x7d38 5777 5778 #define S_PMTXNUMCHN 30 5779 #define M_PMTXNUMCHN 0x3U 5780 #define V_PMTXNUMCHN(x) ((x) << S_PMTXNUMCHN) 5781 #define G_PMTXNUMCHN(x) (((x) >> S_PMTXNUMCHN) & M_PMTXNUMCHN) 5782 5783 #define S_PMTXMAXPAGE 0 5784 #define M_PMTXMAXPAGE 0x1fffffU 5785 #define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE) 5786 #define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE) 5787 5788 #define A_TP_DACK_CONFIG 0x7d44 5789 5790 #define S_AUTOSTATE3 30 5791 #define M_AUTOSTATE3 0x3U 5792 #define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3) 5793 #define G_AUTOSTATE3(x) (((x) >> S_AUTOSTATE3) & M_AUTOSTATE3) 5794 5795 #define S_AUTOSTATE2 28 5796 #define M_AUTOSTATE2 0x3U 5797 #define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2) 5798 #define G_AUTOSTATE2(x) (((x) >> S_AUTOSTATE2) & M_AUTOSTATE2) 5799 5800 #define S_AUTOSTATE1 26 5801 #define M_AUTOSTATE1 0x3U 5802 #define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1) 5803 #define G_AUTOSTATE1(x) (((x) >> S_AUTOSTATE1) & M_AUTOSTATE1) 5804 5805 #define S_BYTETHRESHOLD 8 5806 #define M_BYTETHRESHOLD 0x3ffffU 5807 #define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD) 5808 #define G_BYTETHRESHOLD(x) (((x) >> S_BYTETHRESHOLD) & M_BYTETHRESHOLD) 5809 5810 #define S_MSSTHRESHOLD 4 5811 #define M_MSSTHRESHOLD 0x7U 5812 #define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD) 5813 #define G_MSSTHRESHOLD(x) (((x) >> S_MSSTHRESHOLD) & M_MSSTHRESHOLD) 5814 5815 #define S_AUTOENABLE 1 5816 #define V_AUTOENABLE(x) ((x) << S_AUTOENABLE) 5817 #define F_AUTOENABLE V_AUTOENABLE(1U) 5818 5819 #define S_MODE 0 5820 #define V_MODE(x) ((x) << S_MODE) 5821 #define F_MODE V_MODE(1U) 5822 5823 #define A_TP_PARA_REG0 0x7d60 5824 5825 #define S_DUPACKTHRESH 20 5826 #define M_DUPACKTHRESH 0xfU 5827 #define V_DUPACKTHRESH(x) ((x) << S_DUPACKTHRESH) 5828 #define G_DUPACKTHRESH(x) (((x) >> S_DUPACKTHRESH) & M_DUPACKTHRESH) 5829 5830 #define A_TP_PARA_REG2 0x7d68 5831 5832 #define S_MAXRXDATA 16 5833 #define M_MAXRXDATA 0xffffU 5834 #define V_MAXRXDATA(x) ((x) << S_MAXRXDATA) 5835 #define G_MAXRXDATA(x) (((x) >> S_MAXRXDATA) & M_MAXRXDATA) 5836 5837 #define S_RXCOALESCESIZE 0 5838 #define M_RXCOALESCESIZE 0xffffU 5839 #define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE) 5840 #define G_RXCOALESCESIZE(x) (((x) >> S_RXCOALESCESIZE) & M_RXCOALESCESIZE) 5841 5842 #define A_TP_PARA_REG3 0x7d6c 5843 5844 #define S_TUNNELCNGDROP3 23 5845 #define V_TUNNELCNGDROP3(x) ((x) << S_TUNNELCNGDROP3) 5846 #define F_TUNNELCNGDROP3 V_TUNNELCNGDROP3(1U) 5847 5848 #define S_TUNNELCNGDROP2 22 5849 #define V_TUNNELCNGDROP2(x) ((x) << S_TUNNELCNGDROP2) 5850 #define F_TUNNELCNGDROP2 V_TUNNELCNGDROP2(1U) 5851 5852 #define S_TUNNELCNGDROP1 21 5853 #define V_TUNNELCNGDROP1(x) ((x) << S_TUNNELCNGDROP1) 5854 #define F_TUNNELCNGDROP1 V_TUNNELCNGDROP1(1U) 5855 5856 #define S_TUNNELCNGDROP0 20 5857 #define V_TUNNELCNGDROP0(x) ((x) << S_TUNNELCNGDROP0) 5858 #define F_TUNNELCNGDROP0 V_TUNNELCNGDROP0(1U) 5859 5860 #define S_RXURGTUNNEL 6 5861 #define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL) 5862 #define F_RXURGTUNNEL V_RXURGTUNNEL(1U) 5863 5864 #define A_TP_PARA_REG5 0x7d74 5865 5866 #define S_INDICATESIZE 16 5867 #define M_INDICATESIZE 0xffffU 5868 #define V_INDICATESIZE(x) ((x) << S_INDICATESIZE) 5869 #define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE) 5870 5871 #define S_REARMDDPOFFSET 4 5872 #define V_REARMDDPOFFSET(x) ((x) << S_REARMDDPOFFSET) 5873 #define F_REARMDDPOFFSET V_REARMDDPOFFSET(1U) 5874 5875 #define S_RESETDDPOFFSET 3 5876 #define V_RESETDDPOFFSET(x) ((x) << S_RESETDDPOFFSET) 5877 #define F_RESETDDPOFFSET V_RESETDDPOFFSET(1U) 5878 5879 #define A_TP_TIMER_RESOLUTION 0x7d90 5880 5881 #define S_TIMERRESOLUTION 16 5882 #define M_TIMERRESOLUTION 0xffU 5883 #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION) 5884 #define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION) 5885 5886 #define S_TIMESTAMPRESOLUTION 8 5887 #define M_TIMESTAMPRESOLUTION 0xffU 5888 #define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION) 5889 #define G_TIMESTAMPRESOLUTION(x) (((x) >> S_TIMESTAMPRESOLUTION) & M_TIMESTAMPRESOLUTION) 5890 5891 #define S_DELAYEDACKRESOLUTION 0 5892 #define M_DELAYEDACKRESOLUTION 0xffU 5893 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION) 5894 #define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION) 5895 5896 #define A_TP_MSL 0x7d94 5897 5898 #define S_MSL 0 5899 #define M_MSL 0x3fffffffU 5900 #define V_MSL(x) ((x) << S_MSL) 5901 #define G_MSL(x) (((x) >> S_MSL) & M_MSL) 5902 5903 #define A_TP_RXT_MIN 0x7d98 5904 5905 #define S_RXTMIN 0 5906 #define M_RXTMIN 0x3fffffffU 5907 #define V_RXTMIN(x) ((x) << S_RXTMIN) 5908 #define G_RXTMIN(x) (((x) >> S_RXTMIN) & M_RXTMIN) 5909 5910 #define A_TP_RXT_MAX 0x7d9c 5911 5912 #define S_RXTMAX 0 5913 #define M_RXTMAX 0x3fffffffU 5914 #define V_RXTMAX(x) ((x) << S_RXTMAX) 5915 #define G_RXTMAX(x) (((x) >> S_RXTMAX) & M_RXTMAX) 5916 5917 #define A_TP_PERS_MIN 0x7da0 5918 5919 #define S_PERSMIN 0 5920 #define M_PERSMIN 0x3fffffffU 5921 #define V_PERSMIN(x) ((x) << S_PERSMIN) 5922 #define G_PERSMIN(x) (((x) >> S_PERSMIN) & M_PERSMIN) 5923 5924 #define A_TP_PERS_MAX 0x7da4 5925 5926 #define S_PERSMAX 0 5927 #define M_PERSMAX 0x3fffffffU 5928 #define V_PERSMAX(x) ((x) << S_PERSMAX) 5929 #define G_PERSMAX(x) (((x) >> S_PERSMAX) & M_PERSMAX) 5930 5931 #define A_TP_KEEP_IDLE 0x7da8 5932 5933 #define S_KEEPALIVEIDLE 0 5934 #define M_KEEPALIVEIDLE 0x3fffffffU 5935 #define V_KEEPALIVEIDLE(x) ((x) << S_KEEPALIVEIDLE) 5936 #define G_KEEPALIVEIDLE(x) (((x) >> S_KEEPALIVEIDLE) & M_KEEPALIVEIDLE) 5937 5938 #define A_TP_KEEP_INTVL 0x7dac 5939 5940 #define S_KEEPALIVEINTVL 0 5941 #define M_KEEPALIVEINTVL 0x3fffffffU 5942 #define V_KEEPALIVEINTVL(x) ((x) << S_KEEPALIVEINTVL) 5943 #define G_KEEPALIVEINTVL(x) (((x) >> S_KEEPALIVEINTVL) & M_KEEPALIVEINTVL) 5944 5945 #define A_TP_INIT_SRTT 0x7db0 5946 5947 #define S_MAXRTT 16 5948 #define M_MAXRTT 0xffffU 5949 #define V_MAXRTT(x) ((x) << S_MAXRTT) 5950 #define G_MAXRTT(x) (((x) >> S_MAXRTT) & M_MAXRTT) 5951 5952 #define S_INITSRTT 0 5953 #define M_INITSRTT 0xffffU 5954 #define V_INITSRTT(x) ((x) << S_INITSRTT) 5955 #define G_INITSRTT(x) (((x) >> S_INITSRTT) & M_INITSRTT) 5956 5957 #define A_TP_DACK_TIMER 0x7db4 5958 5959 #define S_DACKTIME 0 5960 #define M_DACKTIME 0xfffU 5961 #define V_DACKTIME(x) ((x) << S_DACKTIME) 5962 #define G_DACKTIME(x) (((x) >> S_DACKTIME) & M_DACKTIME) 5963 5964 #define A_TP_FINWAIT2_TIMER 0x7db8 5965 5966 #define S_FINWAIT2TIME 0 5967 #define M_FINWAIT2TIME 0x3fffffffU 5968 #define V_FINWAIT2TIME(x) ((x) << S_FINWAIT2TIME) 5969 #define G_FINWAIT2TIME(x) (((x) >> S_FINWAIT2TIME) & M_FINWAIT2TIME) 5970 5971 #define A_TP_SHIFT_CNT 0x7dc0 5972 5973 #define S_SYNSHIFTMAX 24 5974 #define M_SYNSHIFTMAX 0xffU 5975 #define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX) 5976 #define G_SYNSHIFTMAX(x) (((x) >> S_SYNSHIFTMAX) & M_SYNSHIFTMAX) 5977 5978 #define S_RXTSHIFTMAXR1 20 5979 #define M_RXTSHIFTMAXR1 0xfU 5980 #define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1) 5981 #define G_RXTSHIFTMAXR1(x) (((x) >> S_RXTSHIFTMAXR1) & M_RXTSHIFTMAXR1) 5982 5983 #define S_RXTSHIFTMAXR2 16 5984 #define M_RXTSHIFTMAXR2 0xfU 5985 #define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2) 5986 #define G_RXTSHIFTMAXR2(x) (((x) >> S_RXTSHIFTMAXR2) & M_RXTSHIFTMAXR2) 5987 5988 #define S_PERSHIFTBACKOFFMAX 12 5989 #define M_PERSHIFTBACKOFFMAX 0xfU 5990 #define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX) 5991 #define G_PERSHIFTBACKOFFMAX(x) (((x) >> S_PERSHIFTBACKOFFMAX) & M_PERSHIFTBACKOFFMAX) 5992 5993 #define S_PERSHIFTMAX 8 5994 #define M_PERSHIFTMAX 0xfU 5995 #define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX) 5996 #define G_PERSHIFTMAX(x) (((x) >> S_PERSHIFTMAX) & M_PERSHIFTMAX) 5997 5998 #define S_KEEPALIVEMAXR1 4 5999 #define M_KEEPALIVEMAXR1 0xfU 6000 #define V_KEEPALIVEMAXR1(x) ((x) << S_KEEPALIVEMAXR1) 6001 #define G_KEEPALIVEMAXR1(x) (((x) >> S_KEEPALIVEMAXR1) & M_KEEPALIVEMAXR1) 6002 6003 #define S_KEEPALIVEMAXR2 0 6004 #define M_KEEPALIVEMAXR2 0xfU 6005 #define V_KEEPALIVEMAXR2(x) ((x) << S_KEEPALIVEMAXR2) 6006 #define G_KEEPALIVEMAXR2(x) (((x) >> S_KEEPALIVEMAXR2) & M_KEEPALIVEMAXR2) 6007 6008 #define S_T6_SYNSHIFTMAX 24 6009 #define M_T6_SYNSHIFTMAX 0xfU 6010 #define V_T6_SYNSHIFTMAX(x) ((x) << S_T6_SYNSHIFTMAX) 6011 #define G_T6_SYNSHIFTMAX(x) (((x) >> S_T6_SYNSHIFTMAX) & M_T6_SYNSHIFTMAX) 6012 6013 #define A_TP_TIME_LO 0x7dc8 6014 #define A_TP_TIME_HI 0x7dcc 6015 #define A_TP_PACE_TABLE 0x7dd8 6016 #define A_TP_CCTRL_TABLE 0x7ddc 6017 6018 #define S_ROWINDEX 16 6019 #define M_ROWINDEX 0xffffU 6020 #define V_ROWINDEX(x) ((x) << S_ROWINDEX) 6021 #define G_ROWINDEX(x) (((x) >> S_ROWINDEX) & M_ROWINDEX) 6022 6023 #define S_ROWVALUE 0 6024 #define M_ROWVALUE 0xffffU 6025 #define V_ROWVALUE(x) ((x) << S_ROWVALUE) 6026 #define G_ROWVALUE(x) (((x) >> S_ROWVALUE) & M_ROWVALUE) 6027 6028 #define A_TP_MTU_TABLE 0x7de4 6029 6030 #define S_MTUINDEX 24 6031 #define M_MTUINDEX 0xffU 6032 #define V_MTUINDEX(x) ((x) << S_MTUINDEX) 6033 #define G_MTUINDEX(x) (((x) >> S_MTUINDEX) & M_MTUINDEX) 6034 6035 #define S_MTUWIDTH 16 6036 #define M_MTUWIDTH 0xfU 6037 #define V_MTUWIDTH(x) ((x) << S_MTUWIDTH) 6038 #define G_MTUWIDTH(x) (((x) >> S_MTUWIDTH) & M_MTUWIDTH) 6039 6040 #define S_MTUVALUE 0 6041 #define M_MTUVALUE 0x3fffU 6042 #define V_MTUVALUE(x) ((x) << S_MTUVALUE) 6043 #define G_MTUVALUE(x) (((x) >> S_MTUVALUE) & M_MTUVALUE) 6044 6045 #define A_TP_RSS_LKP_TABLE 0x7dec 6046 6047 #define S_LKPTBLROWVLD 31 6048 #define V_LKPTBLROWVLD(x) ((x) << S_LKPTBLROWVLD) 6049 #define F_LKPTBLROWVLD V_LKPTBLROWVLD(1U) 6050 6051 #define S_LKPTBLROWIDX 20 6052 #define M_LKPTBLROWIDX 0x3ffU 6053 #define V_LKPTBLROWIDX(x) ((x) << S_LKPTBLROWIDX) 6054 #define G_LKPTBLROWIDX(x) (((x) >> S_LKPTBLROWIDX) & M_LKPTBLROWIDX) 6055 6056 #define S_LKPTBLQUEUE1 10 6057 #define M_LKPTBLQUEUE1 0x3ffU 6058 #define V_LKPTBLQUEUE1(x) ((x) << S_LKPTBLQUEUE1) 6059 #define G_LKPTBLQUEUE1(x) (((x) >> S_LKPTBLQUEUE1) & M_LKPTBLQUEUE1) 6060 6061 #define S_LKPTBLQUEUE0 0 6062 #define M_LKPTBLQUEUE0 0x3ffU 6063 #define V_LKPTBLQUEUE0(x) ((x) << S_LKPTBLQUEUE0) 6064 #define G_LKPTBLQUEUE0(x) (((x) >> S_LKPTBLQUEUE0) & M_LKPTBLQUEUE0) 6065 6066 #define S_T6_LKPTBLROWIDX 20 6067 #define M_T6_LKPTBLROWIDX 0x7ffU 6068 #define V_T6_LKPTBLROWIDX(x) ((x) << S_T6_LKPTBLROWIDX) 6069 #define G_T6_LKPTBLROWIDX(x) (((x) >> S_T6_LKPTBLROWIDX) & M_T6_LKPTBLROWIDX) 6070 6071 #define A_TP_RSS_CONFIG 0x7df0 6072 6073 #define S_TNL4TUPENIPV6 31 6074 #define V_TNL4TUPENIPV6(x) ((x) << S_TNL4TUPENIPV6) 6075 #define F_TNL4TUPENIPV6 V_TNL4TUPENIPV6(1U) 6076 6077 #define S_TNL2TUPENIPV6 30 6078 #define V_TNL2TUPENIPV6(x) ((x) << S_TNL2TUPENIPV6) 6079 #define F_TNL2TUPENIPV6 V_TNL2TUPENIPV6(1U) 6080 6081 #define S_TNL4TUPENIPV4 29 6082 #define V_TNL4TUPENIPV4(x) ((x) << S_TNL4TUPENIPV4) 6083 #define F_TNL4TUPENIPV4 V_TNL4TUPENIPV4(1U) 6084 6085 #define S_TNL2TUPENIPV4 28 6086 #define V_TNL2TUPENIPV4(x) ((x) << S_TNL2TUPENIPV4) 6087 #define F_TNL2TUPENIPV4 V_TNL2TUPENIPV4(1U) 6088 6089 #define S_TNLTCPSEL 27 6090 #define V_TNLTCPSEL(x) ((x) << S_TNLTCPSEL) 6091 #define F_TNLTCPSEL V_TNLTCPSEL(1U) 6092 6093 #define S_TNLIP6SEL 26 6094 #define V_TNLIP6SEL(x) ((x) << S_TNLIP6SEL) 6095 #define F_TNLIP6SEL V_TNLIP6SEL(1U) 6096 6097 #define S_TNLVRTSEL 25 6098 #define V_TNLVRTSEL(x) ((x) << S_TNLVRTSEL) 6099 #define F_TNLVRTSEL V_TNLVRTSEL(1U) 6100 6101 #define S_TNLMAPEN 24 6102 #define V_TNLMAPEN(x) ((x) << S_TNLMAPEN) 6103 #define F_TNLMAPEN V_TNLMAPEN(1U) 6104 6105 #define S_OFDHASHSAVE 19 6106 #define V_OFDHASHSAVE(x) ((x) << S_OFDHASHSAVE) 6107 #define F_OFDHASHSAVE V_OFDHASHSAVE(1U) 6108 6109 #define S_OFDVRTSEL 18 6110 #define V_OFDVRTSEL(x) ((x) << S_OFDVRTSEL) 6111 #define F_OFDVRTSEL V_OFDVRTSEL(1U) 6112 6113 #define S_OFDMAPEN 17 6114 #define V_OFDMAPEN(x) ((x) << S_OFDMAPEN) 6115 #define F_OFDMAPEN V_OFDMAPEN(1U) 6116 6117 #define S_OFDLKPEN 16 6118 #define V_OFDLKPEN(x) ((x) << S_OFDLKPEN) 6119 #define F_OFDLKPEN V_OFDLKPEN(1U) 6120 6121 #define S_SYN4TUPENIPV6 15 6122 #define V_SYN4TUPENIPV6(x) ((x) << S_SYN4TUPENIPV6) 6123 #define F_SYN4TUPENIPV6 V_SYN4TUPENIPV6(1U) 6124 6125 #define S_SYN2TUPENIPV6 14 6126 #define V_SYN2TUPENIPV6(x) ((x) << S_SYN2TUPENIPV6) 6127 #define F_SYN2TUPENIPV6 V_SYN2TUPENIPV6(1U) 6128 6129 #define S_SYN4TUPENIPV4 13 6130 #define V_SYN4TUPENIPV4(x) ((x) << S_SYN4TUPENIPV4) 6131 #define F_SYN4TUPENIPV4 V_SYN4TUPENIPV4(1U) 6132 6133 #define S_SYN2TUPENIPV4 12 6134 #define V_SYN2TUPENIPV4(x) ((x) << S_SYN2TUPENIPV4) 6135 #define F_SYN2TUPENIPV4 V_SYN2TUPENIPV4(1U) 6136 6137 #define S_SYNIP6SEL 11 6138 #define V_SYNIP6SEL(x) ((x) << S_SYNIP6SEL) 6139 #define F_SYNIP6SEL V_SYNIP6SEL(1U) 6140 6141 #define S_SYNVRTSEL 10 6142 #define V_SYNVRTSEL(x) ((x) << S_SYNVRTSEL) 6143 #define F_SYNVRTSEL V_SYNVRTSEL(1U) 6144 6145 #define S_SYNMAPEN 9 6146 #define V_SYNMAPEN(x) ((x) << S_SYNMAPEN) 6147 #define F_SYNMAPEN V_SYNMAPEN(1U) 6148 6149 #define S_SYNLKPEN 8 6150 #define V_SYNLKPEN(x) ((x) << S_SYNLKPEN) 6151 #define F_SYNLKPEN V_SYNLKPEN(1U) 6152 6153 #define S_CHANNELENABLE 7 6154 #define V_CHANNELENABLE(x) ((x) << S_CHANNELENABLE) 6155 #define F_CHANNELENABLE V_CHANNELENABLE(1U) 6156 6157 #define S_PORTENABLE 6 6158 #define V_PORTENABLE(x) ((x) << S_PORTENABLE) 6159 #define F_PORTENABLE V_PORTENABLE(1U) 6160 6161 #define S_TNLALLLOOKUP 5 6162 #define V_TNLALLLOOKUP(x) ((x) << S_TNLALLLOOKUP) 6163 #define F_TNLALLLOOKUP V_TNLALLLOOKUP(1U) 6164 6165 #define S_VIRTENABLE 4 6166 #define V_VIRTENABLE(x) ((x) << S_VIRTENABLE) 6167 #define F_VIRTENABLE V_VIRTENABLE(1U) 6168 6169 #define S_CONGESTIONENABLE 3 6170 #define V_CONGESTIONENABLE(x) ((x) << S_CONGESTIONENABLE) 6171 #define F_CONGESTIONENABLE V_CONGESTIONENABLE(1U) 6172 6173 #define S_HASHTOEPLITZ 2 6174 #define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ) 6175 #define F_HASHTOEPLITZ V_HASHTOEPLITZ(1U) 6176 6177 #define S_UDPENABLE 1 6178 #define V_UDPENABLE(x) ((x) << S_UDPENABLE) 6179 #define F_UDPENABLE V_UDPENABLE(1U) 6180 6181 #define S_DISABLE 0 6182 #define V_DISABLE(x) ((x) << S_DISABLE) 6183 #define F_DISABLE V_DISABLE(1U) 6184 6185 #define S_TNLFCOEMODE 23 6186 #define V_TNLFCOEMODE(x) ((x) << S_TNLFCOEMODE) 6187 #define F_TNLFCOEMODE V_TNLFCOEMODE(1U) 6188 6189 #define S_TNLFCOEEN 21 6190 #define V_TNLFCOEEN(x) ((x) << S_TNLFCOEEN) 6191 #define F_TNLFCOEEN V_TNLFCOEEN(1U) 6192 6193 #define S_HASHXOR 20 6194 #define V_HASHXOR(x) ((x) << S_HASHXOR) 6195 #define F_HASHXOR V_HASHXOR(1U) 6196 6197 #define S_TNLFCOESID 22 6198 #define V_TNLFCOESID(x) ((x) << S_TNLFCOESID) 6199 #define F_TNLFCOESID V_TNLFCOESID(1U) 6200 6201 #define A_TP_RSS_CONFIG_TNL 0x7df4 6202 6203 #define S_MASKSIZE 28 6204 #define M_MASKSIZE 0xfU 6205 #define V_MASKSIZE(x) ((x) << S_MASKSIZE) 6206 #define G_MASKSIZE(x) (((x) >> S_MASKSIZE) & M_MASKSIZE) 6207 6208 #define S_MASKFILTER 16 6209 #define M_MASKFILTER 0x7ffU 6210 #define V_MASKFILTER(x) ((x) << S_MASKFILTER) 6211 #define G_MASKFILTER(x) (((x) >> S_MASKFILTER) & M_MASKFILTER) 6212 6213 #define S_USEWIRECH 0 6214 #define V_USEWIRECH(x) ((x) << S_USEWIRECH) 6215 #define F_USEWIRECH V_USEWIRECH(1U) 6216 6217 #define S_HASHALL 2 6218 #define V_HASHALL(x) ((x) << S_HASHALL) 6219 #define F_HASHALL V_HASHALL(1U) 6220 6221 #define S_HASHETH 1 6222 #define V_HASHETH(x) ((x) << S_HASHETH) 6223 #define F_HASHETH V_HASHETH(1U) 6224 6225 #define A_TP_RSS_CONFIG_OFD 0x7df8 6226 6227 #define S_RRCPLMAPEN 20 6228 #define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN) 6229 #define F_RRCPLMAPEN V_RRCPLMAPEN(1U) 6230 6231 #define S_RRCPLQUEWIDTH 16 6232 #define M_RRCPLQUEWIDTH 0xfU 6233 #define V_RRCPLQUEWIDTH(x) ((x) << S_RRCPLQUEWIDTH) 6234 #define G_RRCPLQUEWIDTH(x) (((x) >> S_RRCPLQUEWIDTH) & M_RRCPLQUEWIDTH) 6235 6236 #define S_FRMWRQUEMASK 12 6237 #define M_FRMWRQUEMASK 0xfU 6238 #define V_FRMWRQUEMASK(x) ((x) << S_FRMWRQUEMASK) 6239 #define G_FRMWRQUEMASK(x) (((x) >> S_FRMWRQUEMASK) & M_FRMWRQUEMASK) 6240 6241 #define A_TP_RSS_CONFIG_SYN 0x7dfc 6242 #define A_TP_RSS_CONFIG_VRT 0x7e00 6243 6244 #define S_VFRDRG 25 6245 #define V_VFRDRG(x) ((x) << S_VFRDRG) 6246 #define F_VFRDRG V_VFRDRG(1U) 6247 6248 #define S_VFRDEN 24 6249 #define V_VFRDEN(x) ((x) << S_VFRDEN) 6250 #define F_VFRDEN V_VFRDEN(1U) 6251 6252 #define S_VFPERREN 23 6253 #define V_VFPERREN(x) ((x) << S_VFPERREN) 6254 #define F_VFPERREN V_VFPERREN(1U) 6255 6256 #define S_KEYPERREN 22 6257 #define V_KEYPERREN(x) ((x) << S_KEYPERREN) 6258 #define F_KEYPERREN V_KEYPERREN(1U) 6259 6260 #define S_DISABLEVLAN 21 6261 #define V_DISABLEVLAN(x) ((x) << S_DISABLEVLAN) 6262 #define F_DISABLEVLAN V_DISABLEVLAN(1U) 6263 6264 #define S_ENABLEUP0 20 6265 #define V_ENABLEUP0(x) ((x) << S_ENABLEUP0) 6266 #define F_ENABLEUP0 V_ENABLEUP0(1U) 6267 6268 #define S_HASHDELAY 16 6269 #define M_HASHDELAY 0xfU 6270 #define V_HASHDELAY(x) ((x) << S_HASHDELAY) 6271 #define G_HASHDELAY(x) (((x) >> S_HASHDELAY) & M_HASHDELAY) 6272 6273 #define S_VFWRADDR 8 6274 #define M_VFWRADDR 0x7fU 6275 #define V_VFWRADDR(x) ((x) << S_VFWRADDR) 6276 #define G_VFWRADDR(x) (((x) >> S_VFWRADDR) & M_VFWRADDR) 6277 6278 #define S_KEYMODE 6 6279 #define M_KEYMODE 0x3U 6280 #define V_KEYMODE(x) ((x) << S_KEYMODE) 6281 #define G_KEYMODE(x) (((x) >> S_KEYMODE) & M_KEYMODE) 6282 6283 #define S_VFWREN 5 6284 #define V_VFWREN(x) ((x) << S_VFWREN) 6285 #define F_VFWREN V_VFWREN(1U) 6286 6287 #define S_KEYWREN 4 6288 #define V_KEYWREN(x) ((x) << S_KEYWREN) 6289 #define F_KEYWREN V_KEYWREN(1U) 6290 6291 #define S_KEYWRADDR 0 6292 #define M_KEYWRADDR 0xfU 6293 #define V_KEYWRADDR(x) ((x) << S_KEYWRADDR) 6294 #define G_KEYWRADDR(x) (((x) >> S_KEYWRADDR) & M_KEYWRADDR) 6295 6296 #define S_VFVLANEN 21 6297 #define V_VFVLANEN(x) ((x) << S_VFVLANEN) 6298 #define F_VFVLANEN V_VFVLANEN(1U) 6299 6300 #define S_VFFWEN 20 6301 #define V_VFFWEN(x) ((x) << S_VFFWEN) 6302 #define F_VFFWEN V_VFFWEN(1U) 6303 6304 #define S_KEYWRADDRX 30 6305 #define M_KEYWRADDRX 0x3U 6306 #define V_KEYWRADDRX(x) ((x) << S_KEYWRADDRX) 6307 #define G_KEYWRADDRX(x) (((x) >> S_KEYWRADDRX) & M_KEYWRADDRX) 6308 6309 #define S_KEYEXTEND 26 6310 #define V_KEYEXTEND(x) ((x) << S_KEYEXTEND) 6311 #define F_KEYEXTEND V_KEYEXTEND(1U) 6312 6313 #define S_T6_VFWRADDR 8 6314 #define M_T6_VFWRADDR 0xffU 6315 #define V_T6_VFWRADDR(x) ((x) << S_T6_VFWRADDR) 6316 #define G_T6_VFWRADDR(x) (((x) >> S_T6_VFWRADDR) & M_T6_VFWRADDR) 6317 6318 #define A_TP_RSS_CONFIG_CNG 0x7e04 6319 6320 #define S_CHNCOUNT3 31 6321 #define V_CHNCOUNT3(x) ((x) << S_CHNCOUNT3) 6322 #define F_CHNCOUNT3 V_CHNCOUNT3(1U) 6323 6324 #define S_CHNCOUNT2 30 6325 #define V_CHNCOUNT2(x) ((x) << S_CHNCOUNT2) 6326 #define F_CHNCOUNT2 V_CHNCOUNT2(1U) 6327 6328 #define S_CHNCOUNT1 29 6329 #define V_CHNCOUNT1(x) ((x) << S_CHNCOUNT1) 6330 #define F_CHNCOUNT1 V_CHNCOUNT1(1U) 6331 6332 #define S_CHNCOUNT0 28 6333 #define V_CHNCOUNT0(x) ((x) << S_CHNCOUNT0) 6334 #define F_CHNCOUNT0 V_CHNCOUNT0(1U) 6335 6336 #define S_CHNUNDFLOW3 27 6337 #define V_CHNUNDFLOW3(x) ((x) << S_CHNUNDFLOW3) 6338 #define F_CHNUNDFLOW3 V_CHNUNDFLOW3(1U) 6339 6340 #define S_CHNUNDFLOW2 26 6341 #define V_CHNUNDFLOW2(x) ((x) << S_CHNUNDFLOW2) 6342 #define F_CHNUNDFLOW2 V_CHNUNDFLOW2(1U) 6343 6344 #define S_CHNUNDFLOW1 25 6345 #define V_CHNUNDFLOW1(x) ((x) << S_CHNUNDFLOW1) 6346 #define F_CHNUNDFLOW1 V_CHNUNDFLOW1(1U) 6347 6348 #define S_CHNUNDFLOW0 24 6349 #define V_CHNUNDFLOW0(x) ((x) << S_CHNUNDFLOW0) 6350 #define F_CHNUNDFLOW0 V_CHNUNDFLOW0(1U) 6351 6352 #define S_CHNOVRFLOW3 23 6353 #define V_CHNOVRFLOW3(x) ((x) << S_CHNOVRFLOW3) 6354 #define F_CHNOVRFLOW3 V_CHNOVRFLOW3(1U) 6355 6356 #define S_CHNOVRFLOW2 22 6357 #define V_CHNOVRFLOW2(x) ((x) << S_CHNOVRFLOW2) 6358 #define F_CHNOVRFLOW2 V_CHNOVRFLOW2(1U) 6359 6360 #define S_CHNOVRFLOW1 21 6361 #define V_CHNOVRFLOW1(x) ((x) << S_CHNOVRFLOW1) 6362 #define F_CHNOVRFLOW1 V_CHNOVRFLOW1(1U) 6363 6364 #define S_CHNOVRFLOW0 20 6365 #define V_CHNOVRFLOW0(x) ((x) << S_CHNOVRFLOW0) 6366 #define F_CHNOVRFLOW0 V_CHNOVRFLOW0(1U) 6367 6368 #define S_RSTCHN3 19 6369 #define V_RSTCHN3(x) ((x) << S_RSTCHN3) 6370 #define F_RSTCHN3 V_RSTCHN3(1U) 6371 6372 #define S_RSTCHN2 18 6373 #define V_RSTCHN2(x) ((x) << S_RSTCHN2) 6374 #define F_RSTCHN2 V_RSTCHN2(1U) 6375 6376 #define S_RSTCHN1 17 6377 #define V_RSTCHN1(x) ((x) << S_RSTCHN1) 6378 #define F_RSTCHN1 V_RSTCHN1(1U) 6379 6380 #define S_RSTCHN0 16 6381 #define V_RSTCHN0(x) ((x) << S_RSTCHN0) 6382 #define F_RSTCHN0 V_RSTCHN0(1U) 6383 6384 #define S_UPDVLD 15 6385 #define V_UPDVLD(x) ((x) << S_UPDVLD) 6386 #define F_UPDVLD V_UPDVLD(1U) 6387 6388 #define S_XOFF 14 6389 #define V_XOFF(x) ((x) << S_XOFF) 6390 #define F_XOFF V_XOFF(1U) 6391 6392 #define S_UPDCHN3 13 6393 #define V_UPDCHN3(x) ((x) << S_UPDCHN3) 6394 #define F_UPDCHN3 V_UPDCHN3(1U) 6395 6396 #define S_UPDCHN2 12 6397 #define V_UPDCHN2(x) ((x) << S_UPDCHN2) 6398 #define F_UPDCHN2 V_UPDCHN2(1U) 6399 6400 #define S_UPDCHN1 11 6401 #define V_UPDCHN1(x) ((x) << S_UPDCHN1) 6402 #define F_UPDCHN1 V_UPDCHN1(1U) 6403 6404 #define S_UPDCHN0 10 6405 #define V_UPDCHN0(x) ((x) << S_UPDCHN0) 6406 #define F_UPDCHN0 V_UPDCHN0(1U) 6407 6408 #define S_QUEUE 0 6409 #define M_QUEUE 0x3ffU 6410 #define V_QUEUE(x) ((x) << S_QUEUE) 6411 #define G_QUEUE(x) (((x) >> S_QUEUE) & M_QUEUE) 6412 6413 #define A_TP_TM_PIO_ADDR 0x7e18 6414 #define A_TP_TM_PIO_DATA 0x7e1c 6415 #define A_TP_MOD_CONFIG 0x7e24 6416 6417 #define S_RXCHANNELWEIGHT1 24 6418 #define M_RXCHANNELWEIGHT1 0xffU 6419 #define V_RXCHANNELWEIGHT1(x) ((x) << S_RXCHANNELWEIGHT1) 6420 #define G_RXCHANNELWEIGHT1(x) (((x) >> S_RXCHANNELWEIGHT1) & M_RXCHANNELWEIGHT1) 6421 6422 #define S_RXCHANNELWEIGHT0 16 6423 #define M_RXCHANNELWEIGHT0 0xffU 6424 #define V_RXCHANNELWEIGHT0(x) ((x) << S_RXCHANNELWEIGHT0) 6425 #define G_RXCHANNELWEIGHT0(x) (((x) >> S_RXCHANNELWEIGHT0) & M_RXCHANNELWEIGHT0) 6426 6427 #define S_TIMERMODE 8 6428 #define M_TIMERMODE 0xffU 6429 #define V_TIMERMODE(x) ((x) << S_TIMERMODE) 6430 #define G_TIMERMODE(x) (((x) >> S_TIMERMODE) & M_TIMERMODE) 6431 6432 #define S_TXCHANNELXOFFEN 0 6433 #define M_TXCHANNELXOFFEN 0xfU 6434 #define V_TXCHANNELXOFFEN(x) ((x) << S_TXCHANNELXOFFEN) 6435 #define G_TXCHANNELXOFFEN(x) (((x) >> S_TXCHANNELXOFFEN) & M_TXCHANNELXOFFEN) 6436 6437 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28 6438 6439 #define S_RX_MOD_WEIGHT 24 6440 #define M_RX_MOD_WEIGHT 0xffU 6441 #define V_RX_MOD_WEIGHT(x) ((x) << S_RX_MOD_WEIGHT) 6442 #define G_RX_MOD_WEIGHT(x) (((x) >> S_RX_MOD_WEIGHT) & M_RX_MOD_WEIGHT) 6443 6444 #define S_TX_MOD_WEIGHT 16 6445 #define M_TX_MOD_WEIGHT 0xffU 6446 #define V_TX_MOD_WEIGHT(x) ((x) << S_TX_MOD_WEIGHT) 6447 #define G_TX_MOD_WEIGHT(x) (((x) >> S_TX_MOD_WEIGHT) & M_TX_MOD_WEIGHT) 6448 6449 #define S_TX_MOD_QUEUE_REQ_MAP 0 6450 #define M_TX_MOD_QUEUE_REQ_MAP 0xffffU 6451 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP) 6452 #define G_TX_MOD_QUEUE_REQ_MAP(x) (((x) >> S_TX_MOD_QUEUE_REQ_MAP) & M_TX_MOD_QUEUE_REQ_MAP) 6453 6454 #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x7e2c 6455 6456 #define S_TX_MODQ_WEIGHT7 24 6457 #define M_TX_MODQ_WEIGHT7 0xffU 6458 #define V_TX_MODQ_WEIGHT7(x) ((x) << S_TX_MODQ_WEIGHT7) 6459 #define G_TX_MODQ_WEIGHT7(x) (((x) >> S_TX_MODQ_WEIGHT7) & M_TX_MODQ_WEIGHT7) 6460 6461 #define S_TX_MODQ_WEIGHT6 16 6462 #define M_TX_MODQ_WEIGHT6 0xffU 6463 #define V_TX_MODQ_WEIGHT6(x) ((x) << S_TX_MODQ_WEIGHT6) 6464 #define G_TX_MODQ_WEIGHT6(x) (((x) >> S_TX_MODQ_WEIGHT6) & M_TX_MODQ_WEIGHT6) 6465 6466 #define S_TX_MODQ_WEIGHT5 8 6467 #define M_TX_MODQ_WEIGHT5 0xffU 6468 #define V_TX_MODQ_WEIGHT5(x) ((x) << S_TX_MODQ_WEIGHT5) 6469 #define G_TX_MODQ_WEIGHT5(x) (((x) >> S_TX_MODQ_WEIGHT5) & M_TX_MODQ_WEIGHT5) 6470 6471 #define S_TX_MODQ_WEIGHT4 0 6472 #define M_TX_MODQ_WEIGHT4 0xffU 6473 #define V_TX_MODQ_WEIGHT4(x) ((x) << S_TX_MODQ_WEIGHT4) 6474 #define G_TX_MODQ_WEIGHT4(x) (((x) >> S_TX_MODQ_WEIGHT4) & M_TX_MODQ_WEIGHT4) 6475 6476 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30 6477 6478 #define S_TX_MODQ_WEIGHT3 24 6479 #define M_TX_MODQ_WEIGHT3 0xffU 6480 #define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3) 6481 #define G_TX_MODQ_WEIGHT3(x) (((x) >> S_TX_MODQ_WEIGHT3) & M_TX_MODQ_WEIGHT3) 6482 6483 #define S_TX_MODQ_WEIGHT2 16 6484 #define M_TX_MODQ_WEIGHT2 0xffU 6485 #define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2) 6486 #define G_TX_MODQ_WEIGHT2(x) (((x) >> S_TX_MODQ_WEIGHT2) & M_TX_MODQ_WEIGHT2) 6487 6488 #define S_TX_MODQ_WEIGHT1 8 6489 #define M_TX_MODQ_WEIGHT1 0xffU 6490 #define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1) 6491 #define G_TX_MODQ_WEIGHT1(x) (((x) >> S_TX_MODQ_WEIGHT1) & M_TX_MODQ_WEIGHT1) 6492 6493 #define S_TX_MODQ_WEIGHT0 0 6494 #define M_TX_MODQ_WEIGHT0 0xffU 6495 #define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0) 6496 #define G_TX_MODQ_WEIGHT0(x) (((x) >> S_TX_MODQ_WEIGHT0) & M_TX_MODQ_WEIGHT0) 6497 6498 #define A_TP_PIO_ADDR 0x7e40 6499 #define A_TP_PIO_DATA 0x7e44 6500 #define A_TP_MIB_INDEX 0x7e50 6501 #define A_TP_MIB_DATA 0x7e54 6502 #define A_TP_CMM_MM_RX_FLST_BASE 0x7e60 6503 #define A_TP_CMM_MM_TX_FLST_BASE 0x7e64 6504 #define A_TP_CMM_MM_PS_FLST_BASE 0x7e68 6505 #define A_TP_CMM_MM_MAX_PSTRUCT 0x7e6c 6506 6507 #define S_CMMAXPSTRUCT 0 6508 #define M_CMMAXPSTRUCT 0x1fffffU 6509 #define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT) 6510 #define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT) 6511 6512 #define A_TP_INT_ENABLE 0x7e70 6513 6514 #define S_FLMTXFLSTEMPTY 30 6515 #define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY) 6516 #define F_FLMTXFLSTEMPTY V_FLMTXFLSTEMPTY(1U) 6517 6518 #define A_TP_INT_CAUSE 0x7e74 6519 #define A_TP_PER_ENABLE 0x7e78 6520 #define A_TP_TX_ORATE 0x7ebc 6521 6522 #define S_OFDRATE3 24 6523 #define M_OFDRATE3 0xffU 6524 #define V_OFDRATE3(x) ((x) << S_OFDRATE3) 6525 #define G_OFDRATE3(x) (((x) >> S_OFDRATE3) & M_OFDRATE3) 6526 6527 #define S_OFDRATE2 16 6528 #define M_OFDRATE2 0xffU 6529 #define V_OFDRATE2(x) ((x) << S_OFDRATE2) 6530 #define G_OFDRATE2(x) (((x) >> S_OFDRATE2) & M_OFDRATE2) 6531 6532 #define S_OFDRATE1 8 6533 #define M_OFDRATE1 0xffU 6534 #define V_OFDRATE1(x) ((x) << S_OFDRATE1) 6535 #define G_OFDRATE1(x) (((x) >> S_OFDRATE1) & M_OFDRATE1) 6536 6537 #define S_OFDRATE0 0 6538 #define M_OFDRATE0 0xffU 6539 #define V_OFDRATE0(x) ((x) << S_OFDRATE0) 6540 #define G_OFDRATE0(x) (((x) >> S_OFDRATE0) & M_OFDRATE0) 6541 6542 #define A_TP_TX_TRATE 0x7ed0 6543 6544 #define S_TNLRATE3 24 6545 #define M_TNLRATE3 0xffU 6546 #define V_TNLRATE3(x) ((x) << S_TNLRATE3) 6547 #define G_TNLRATE3(x) (((x) >> S_TNLRATE3) & M_TNLRATE3) 6548 6549 #define S_TNLRATE2 16 6550 #define M_TNLRATE2 0xffU 6551 #define V_TNLRATE2(x) ((x) << S_TNLRATE2) 6552 #define G_TNLRATE2(x) (((x) >> S_TNLRATE2) & M_TNLRATE2) 6553 6554 #define S_TNLRATE1 8 6555 #define M_TNLRATE1 0xffU 6556 #define V_TNLRATE1(x) ((x) << S_TNLRATE1) 6557 #define G_TNLRATE1(x) (((x) >> S_TNLRATE1) & M_TNLRATE1) 6558 6559 #define S_TNLRATE0 0 6560 #define M_TNLRATE0 0xffU 6561 #define V_TNLRATE0(x) ((x) << S_TNLRATE0) 6562 #define G_TNLRATE0(x) (((x) >> S_TNLRATE0) & M_TNLRATE0) 6563 6564 #define A_TP_DBG_LA_CONFIG 0x7ed4 6565 6566 #define S_DBGLAOPCENABLE 24 6567 #define M_DBGLAOPCENABLE 0xffU 6568 #define V_DBGLAOPCENABLE(x) ((x) << S_DBGLAOPCENABLE) 6569 #define G_DBGLAOPCENABLE(x) (((x) >> S_DBGLAOPCENABLE) & M_DBGLAOPCENABLE) 6570 6571 #define S_DBGLAWHLF 23 6572 #define V_DBGLAWHLF(x) ((x) << S_DBGLAWHLF) 6573 #define F_DBGLAWHLF V_DBGLAWHLF(1U) 6574 6575 #define S_DBGLAWPTR 16 6576 #define M_DBGLAWPTR 0x7fU 6577 #define V_DBGLAWPTR(x) ((x) << S_DBGLAWPTR) 6578 #define G_DBGLAWPTR(x) (((x) >> S_DBGLAWPTR) & M_DBGLAWPTR) 6579 6580 #define S_DBGLAMODE 14 6581 #define M_DBGLAMODE 0x3U 6582 #define V_DBGLAMODE(x) ((x) << S_DBGLAMODE) 6583 #define G_DBGLAMODE(x) (((x) >> S_DBGLAMODE) & M_DBGLAMODE) 6584 6585 #define S_DBGLAFATALFREEZE 13 6586 #define V_DBGLAFATALFREEZE(x) ((x) << S_DBGLAFATALFREEZE) 6587 #define F_DBGLAFATALFREEZE V_DBGLAFATALFREEZE(1U) 6588 6589 #define S_DBGLAENABLE 12 6590 #define V_DBGLAENABLE(x) ((x) << S_DBGLAENABLE) 6591 #define F_DBGLAENABLE V_DBGLAENABLE(1U) 6592 6593 #define S_DBGLARPTR 0 6594 #define M_DBGLARPTR 0x7fU 6595 #define V_DBGLARPTR(x) ((x) << S_DBGLARPTR) 6596 #define G_DBGLARPTR(x) (((x) >> S_DBGLARPTR) & M_DBGLARPTR) 6597 6598 #define A_TP_DBG_LA_DATAL 0x7ed8 6599 #define A_TP_DBG_LA_DATAH 0x7edc 6600 #define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3 6601 6602 #define S_TXTIMERSEPQ1 16 6603 #define M_TXTIMERSEPQ1 0xffffU 6604 #define V_TXTIMERSEPQ1(x) ((x) << S_TXTIMERSEPQ1) 6605 #define G_TXTIMERSEPQ1(x) (((x) >> S_TXTIMERSEPQ1) & M_TXTIMERSEPQ1) 6606 6607 #define S_TXTIMERSEPQ0 0 6608 #define M_TXTIMERSEPQ0 0xffffU 6609 #define V_TXTIMERSEPQ0(x) ((x) << S_TXTIMERSEPQ0) 6610 #define G_TXTIMERSEPQ0(x) (((x) >> S_TXTIMERSEPQ0) & M_TXTIMERSEPQ0) 6611 6612 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8 6613 6614 #define S_TXRATEINCQ1 24 6615 #define M_TXRATEINCQ1 0xffU 6616 #define V_TXRATEINCQ1(x) ((x) << S_TXRATEINCQ1) 6617 #define G_TXRATEINCQ1(x) (((x) >> S_TXRATEINCQ1) & M_TXRATEINCQ1) 6618 6619 #define S_TXRATETCKQ1 16 6620 #define M_TXRATETCKQ1 0xffU 6621 #define V_TXRATETCKQ1(x) ((x) << S_TXRATETCKQ1) 6622 #define G_TXRATETCKQ1(x) (((x) >> S_TXRATETCKQ1) & M_TXRATETCKQ1) 6623 6624 #define S_TXRATEINCQ0 8 6625 #define M_TXRATEINCQ0 0xffU 6626 #define V_TXRATEINCQ0(x) ((x) << S_TXRATEINCQ0) 6627 #define G_TXRATEINCQ0(x) (((x) >> S_TXRATEINCQ0) & M_TXRATEINCQ0) 6628 6629 #define S_TXRATETCKQ0 0 6630 #define M_TXRATETCKQ0 0xffU 6631 #define V_TXRATETCKQ0(x) ((x) << S_TXRATETCKQ0) 6632 #define G_TXRATETCKQ0(x) (((x) >> S_TXRATETCKQ0) & M_TXRATETCKQ0) 6633 6634 #define A_TP_RSS_PF0_CONFIG 0x30 6635 6636 #define S_MAPENABLE 31 6637 #define V_MAPENABLE(x) ((x) << S_MAPENABLE) 6638 #define F_MAPENABLE V_MAPENABLE(1U) 6639 6640 #define S_CHNENABLE 30 6641 #define V_CHNENABLE(x) ((x) << S_CHNENABLE) 6642 #define F_CHNENABLE V_CHNENABLE(1U) 6643 6644 #define S_PRTENABLE 29 6645 #define V_PRTENABLE(x) ((x) << S_PRTENABLE) 6646 #define F_PRTENABLE V_PRTENABLE(1U) 6647 6648 #define S_UDPFOURTUPEN 28 6649 #define V_UDPFOURTUPEN(x) ((x) << S_UDPFOURTUPEN) 6650 #define F_UDPFOURTUPEN V_UDPFOURTUPEN(1U) 6651 6652 #define S_IP6FOURTUPEN 27 6653 #define V_IP6FOURTUPEN(x) ((x) << S_IP6FOURTUPEN) 6654 #define F_IP6FOURTUPEN V_IP6FOURTUPEN(1U) 6655 6656 #define S_IP6TWOTUPEN 26 6657 #define V_IP6TWOTUPEN(x) ((x) << S_IP6TWOTUPEN) 6658 #define F_IP6TWOTUPEN V_IP6TWOTUPEN(1U) 6659 6660 #define S_IP4FOURTUPEN 25 6661 #define V_IP4FOURTUPEN(x) ((x) << S_IP4FOURTUPEN) 6662 #define F_IP4FOURTUPEN V_IP4FOURTUPEN(1U) 6663 6664 #define S_IP4TWOTUPEN 24 6665 #define V_IP4TWOTUPEN(x) ((x) << S_IP4TWOTUPEN) 6666 #define F_IP4TWOTUPEN V_IP4TWOTUPEN(1U) 6667 6668 #define S_IVFWIDTH 20 6669 #define M_IVFWIDTH 0xfU 6670 #define V_IVFWIDTH(x) ((x) << S_IVFWIDTH) 6671 #define G_IVFWIDTH(x) (((x) >> S_IVFWIDTH) & M_IVFWIDTH) 6672 6673 #define S_CH1DEFAULTQUEUE 10 6674 #define M_CH1DEFAULTQUEUE 0x3ffU 6675 #define V_CH1DEFAULTQUEUE(x) ((x) << S_CH1DEFAULTQUEUE) 6676 #define G_CH1DEFAULTQUEUE(x) (((x) >> S_CH1DEFAULTQUEUE) & M_CH1DEFAULTQUEUE) 6677 6678 #define S_CH0DEFAULTQUEUE 0 6679 #define M_CH0DEFAULTQUEUE 0x3ffU 6680 #define V_CH0DEFAULTQUEUE(x) ((x) << S_CH0DEFAULTQUEUE) 6681 #define G_CH0DEFAULTQUEUE(x) (((x) >> S_CH0DEFAULTQUEUE) & M_CH0DEFAULTQUEUE) 6682 6683 #define S_PRIENABLE 30 6684 #define V_PRIENABLE(x) ((x) << S_PRIENABLE) 6685 #define F_PRIENABLE V_PRIENABLE(1U) 6686 6687 #define S_T6_CHNENABLE 29 6688 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE) 6689 #define F_T6_CHNENABLE V_T6_CHNENABLE(1U) 6690 6691 #define A_TP_RSS_PF_MAP 0x38 6692 6693 #define S_LKPIDXSIZE 24 6694 #define M_LKPIDXSIZE 0x3U 6695 #define V_LKPIDXSIZE(x) ((x) << S_LKPIDXSIZE) 6696 #define G_LKPIDXSIZE(x) (((x) >> S_LKPIDXSIZE) & M_LKPIDXSIZE) 6697 6698 #define S_PF7LKPIDX 21 6699 #define M_PF7LKPIDX 0x7U 6700 #define V_PF7LKPIDX(x) ((x) << S_PF7LKPIDX) 6701 #define G_PF7LKPIDX(x) (((x) >> S_PF7LKPIDX) & M_PF7LKPIDX) 6702 6703 #define S_PF6LKPIDX 18 6704 #define M_PF6LKPIDX 0x7U 6705 #define V_PF6LKPIDX(x) ((x) << S_PF6LKPIDX) 6706 #define G_PF6LKPIDX(x) (((x) >> S_PF6LKPIDX) & M_PF6LKPIDX) 6707 6708 #define S_PF5LKPIDX 15 6709 #define M_PF5LKPIDX 0x7U 6710 #define V_PF5LKPIDX(x) ((x) << S_PF5LKPIDX) 6711 #define G_PF5LKPIDX(x) (((x) >> S_PF5LKPIDX) & M_PF5LKPIDX) 6712 6713 #define S_PF4LKPIDX 12 6714 #define M_PF4LKPIDX 0x7U 6715 #define V_PF4LKPIDX(x) ((x) << S_PF4LKPIDX) 6716 #define G_PF4LKPIDX(x) (((x) >> S_PF4LKPIDX) & M_PF4LKPIDX) 6717 6718 #define S_PF3LKPIDX 9 6719 #define M_PF3LKPIDX 0x7U 6720 #define V_PF3LKPIDX(x) ((x) << S_PF3LKPIDX) 6721 #define G_PF3LKPIDX(x) (((x) >> S_PF3LKPIDX) & M_PF3LKPIDX) 6722 6723 #define S_PF2LKPIDX 6 6724 #define M_PF2LKPIDX 0x7U 6725 #define V_PF2LKPIDX(x) ((x) << S_PF2LKPIDX) 6726 #define G_PF2LKPIDX(x) (((x) >> S_PF2LKPIDX) & M_PF2LKPIDX) 6727 6728 #define S_PF1LKPIDX 3 6729 #define M_PF1LKPIDX 0x7U 6730 #define V_PF1LKPIDX(x) ((x) << S_PF1LKPIDX) 6731 #define G_PF1LKPIDX(x) (((x) >> S_PF1LKPIDX) & M_PF1LKPIDX) 6732 6733 #define S_PF0LKPIDX 0 6734 #define M_PF0LKPIDX 0x7U 6735 #define V_PF0LKPIDX(x) ((x) << S_PF0LKPIDX) 6736 #define G_PF0LKPIDX(x) (((x) >> S_PF0LKPIDX) & M_PF0LKPIDX) 6737 6738 #define A_TP_RSS_PF_MSK 0x39 6739 6740 #define S_PF7MSKSIZE 28 6741 #define M_PF7MSKSIZE 0xfU 6742 #define V_PF7MSKSIZE(x) ((x) << S_PF7MSKSIZE) 6743 #define G_PF7MSKSIZE(x) (((x) >> S_PF7MSKSIZE) & M_PF7MSKSIZE) 6744 6745 #define S_PF6MSKSIZE 24 6746 #define M_PF6MSKSIZE 0xfU 6747 #define V_PF6MSKSIZE(x) ((x) << S_PF6MSKSIZE) 6748 #define G_PF6MSKSIZE(x) (((x) >> S_PF6MSKSIZE) & M_PF6MSKSIZE) 6749 6750 #define S_PF5MSKSIZE 20 6751 #define M_PF5MSKSIZE 0xfU 6752 #define V_PF5MSKSIZE(x) ((x) << S_PF5MSKSIZE) 6753 #define G_PF5MSKSIZE(x) (((x) >> S_PF5MSKSIZE) & M_PF5MSKSIZE) 6754 6755 #define S_PF4MSKSIZE 16 6756 #define M_PF4MSKSIZE 0xfU 6757 #define V_PF4MSKSIZE(x) ((x) << S_PF4MSKSIZE) 6758 #define G_PF4MSKSIZE(x) (((x) >> S_PF4MSKSIZE) & M_PF4MSKSIZE) 6759 6760 #define S_PF3MSKSIZE 12 6761 #define M_PF3MSKSIZE 0xfU 6762 #define V_PF3MSKSIZE(x) ((x) << S_PF3MSKSIZE) 6763 #define G_PF3MSKSIZE(x) (((x) >> S_PF3MSKSIZE) & M_PF3MSKSIZE) 6764 6765 #define S_PF2MSKSIZE 8 6766 #define M_PF2MSKSIZE 0xfU 6767 #define V_PF2MSKSIZE(x) ((x) << S_PF2MSKSIZE) 6768 #define G_PF2MSKSIZE(x) (((x) >> S_PF2MSKSIZE) & M_PF2MSKSIZE) 6769 6770 #define S_PF1MSKSIZE 4 6771 #define M_PF1MSKSIZE 0xfU 6772 #define V_PF1MSKSIZE(x) ((x) << S_PF1MSKSIZE) 6773 #define G_PF1MSKSIZE(x) (((x) >> S_PF1MSKSIZE) & M_PF1MSKSIZE) 6774 6775 #define S_PF0MSKSIZE 0 6776 #define M_PF0MSKSIZE 0xfU 6777 #define V_PF0MSKSIZE(x) ((x) << S_PF0MSKSIZE) 6778 #define G_PF0MSKSIZE(x) (((x) >> S_PF0MSKSIZE) & M_PF0MSKSIZE) 6779 6780 #define A_TP_RSS_VFL_CONFIG 0x3a 6781 #define A_TP_RSS_VFH_CONFIG 0x3b 6782 6783 #define S_ENABLEUDPHASH 31 6784 #define V_ENABLEUDPHASH(x) ((x) << S_ENABLEUDPHASH) 6785 #define F_ENABLEUDPHASH V_ENABLEUDPHASH(1U) 6786 6787 #define S_VFUPEN 30 6788 #define V_VFUPEN(x) ((x) << S_VFUPEN) 6789 #define F_VFUPEN V_VFUPEN(1U) 6790 6791 #define S_VFVLNEX 28 6792 #define V_VFVLNEX(x) ((x) << S_VFVLNEX) 6793 #define F_VFVLNEX V_VFVLNEX(1U) 6794 6795 #define S_VFPRTEN 27 6796 #define V_VFPRTEN(x) ((x) << S_VFPRTEN) 6797 #define F_VFPRTEN V_VFPRTEN(1U) 6798 6799 #define S_VFCHNEN 26 6800 #define V_VFCHNEN(x) ((x) << S_VFCHNEN) 6801 #define F_VFCHNEN V_VFCHNEN(1U) 6802 6803 #define S_DEFAULTQUEUE 16 6804 #define M_DEFAULTQUEUE 0x3ffU 6805 #define V_DEFAULTQUEUE(x) ((x) << S_DEFAULTQUEUE) 6806 #define G_DEFAULTQUEUE(x) (((x) >> S_DEFAULTQUEUE) & M_DEFAULTQUEUE) 6807 6808 #define S_VFLKPIDX 8 6809 #define M_VFLKPIDX 0xffU 6810 #define V_VFLKPIDX(x) ((x) << S_VFLKPIDX) 6811 #define G_VFLKPIDX(x) (((x) >> S_VFLKPIDX) & M_VFLKPIDX) 6812 6813 #define S_VFIP6FOURTUPEN 7 6814 #define V_VFIP6FOURTUPEN(x) ((x) << S_VFIP6FOURTUPEN) 6815 #define F_VFIP6FOURTUPEN V_VFIP6FOURTUPEN(1U) 6816 6817 #define S_VFIP6TWOTUPEN 6 6818 #define V_VFIP6TWOTUPEN(x) ((x) << S_VFIP6TWOTUPEN) 6819 #define F_VFIP6TWOTUPEN V_VFIP6TWOTUPEN(1U) 6820 6821 #define S_VFIP4FOURTUPEN 5 6822 #define V_VFIP4FOURTUPEN(x) ((x) << S_VFIP4FOURTUPEN) 6823 #define F_VFIP4FOURTUPEN V_VFIP4FOURTUPEN(1U) 6824 6825 #define S_VFIP4TWOTUPEN 4 6826 #define V_VFIP4TWOTUPEN(x) ((x) << S_VFIP4TWOTUPEN) 6827 #define F_VFIP4TWOTUPEN V_VFIP4TWOTUPEN(1U) 6828 6829 #define S_KEYINDEX 0 6830 #define M_KEYINDEX 0xfU 6831 #define V_KEYINDEX(x) ((x) << S_KEYINDEX) 6832 #define G_KEYINDEX(x) (((x) >> S_KEYINDEX) & M_KEYINDEX) 6833 6834 #define A_TP_RSS_SECRET_KEY0 0x40 6835 #define A_TP_DBG_ESIDE_PKT0 0x130 6836 6837 #define S_ETXSOPCNT 28 6838 #define M_ETXSOPCNT 0xfU 6839 #define V_ETXSOPCNT(x) ((x) << S_ETXSOPCNT) 6840 #define G_ETXSOPCNT(x) (((x) >> S_ETXSOPCNT) & M_ETXSOPCNT) 6841 6842 #define S_ETXEOPCNT 24 6843 #define M_ETXEOPCNT 0xfU 6844 #define V_ETXEOPCNT(x) ((x) << S_ETXEOPCNT) 6845 #define G_ETXEOPCNT(x) (((x) >> S_ETXEOPCNT) & M_ETXEOPCNT) 6846 6847 #define S_ETXPLDSOPCNT 20 6848 #define M_ETXPLDSOPCNT 0xfU 6849 #define V_ETXPLDSOPCNT(x) ((x) << S_ETXPLDSOPCNT) 6850 #define G_ETXPLDSOPCNT(x) (((x) >> S_ETXPLDSOPCNT) & M_ETXPLDSOPCNT) 6851 6852 #define S_ETXPLDEOPCNT 16 6853 #define M_ETXPLDEOPCNT 0xfU 6854 #define V_ETXPLDEOPCNT(x) ((x) << S_ETXPLDEOPCNT) 6855 #define G_ETXPLDEOPCNT(x) (((x) >> S_ETXPLDEOPCNT) & M_ETXPLDEOPCNT) 6856 6857 #define S_ERXSOPCNT 12 6858 #define M_ERXSOPCNT 0xfU 6859 #define V_ERXSOPCNT(x) ((x) << S_ERXSOPCNT) 6860 #define G_ERXSOPCNT(x) (((x) >> S_ERXSOPCNT) & M_ERXSOPCNT) 6861 6862 #define S_ERXEOPCNT 8 6863 #define M_ERXEOPCNT 0xfU 6864 #define V_ERXEOPCNT(x) ((x) << S_ERXEOPCNT) 6865 #define G_ERXEOPCNT(x) (((x) >> S_ERXEOPCNT) & M_ERXEOPCNT) 6866 6867 #define S_ERXPLDSOPCNT 4 6868 #define M_ERXPLDSOPCNT 0xfU 6869 #define V_ERXPLDSOPCNT(x) ((x) << S_ERXPLDSOPCNT) 6870 #define G_ERXPLDSOPCNT(x) (((x) >> S_ERXPLDSOPCNT) & M_ERXPLDSOPCNT) 6871 6872 #define S_ERXPLDEOPCNT 0 6873 #define M_ERXPLDEOPCNT 0xfU 6874 #define V_ERXPLDEOPCNT(x) ((x) << S_ERXPLDEOPCNT) 6875 #define G_ERXPLDEOPCNT(x) (((x) >> S_ERXPLDEOPCNT) & M_ERXPLDEOPCNT) 6876 6877 #define A_TP_DBG_ESIDE_PKT1 0x131 6878 #define A_TP_DBG_ESIDE_PKT2 0x132 6879 #define A_TP_DBG_ESIDE_PKT3 0x133 6880 #define A_TP_VLAN_PRI_MAP 0x140 6881 6882 #define S_FRAGMENTATION 9 6883 #define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION) 6884 #define F_FRAGMENTATION V_FRAGMENTATION(1U) 6885 6886 #define S_MPSHITTYPE 8 6887 #define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE) 6888 #define F_MPSHITTYPE V_MPSHITTYPE(1U) 6889 6890 #define S_MACMATCH 7 6891 #define V_MACMATCH(x) ((x) << S_MACMATCH) 6892 #define F_MACMATCH V_MACMATCH(1U) 6893 6894 #define S_ETHERTYPE 6 6895 #define V_ETHERTYPE(x) ((x) << S_ETHERTYPE) 6896 #define F_ETHERTYPE V_ETHERTYPE(1U) 6897 6898 #define S_PROTOCOL 5 6899 #define V_PROTOCOL(x) ((x) << S_PROTOCOL) 6900 #define F_PROTOCOL V_PROTOCOL(1U) 6901 6902 #define S_TOS 4 6903 #define V_TOS(x) ((x) << S_TOS) 6904 #define F_TOS V_TOS(1U) 6905 6906 #define S_VLAN 3 6907 #define V_VLAN(x) ((x) << S_VLAN) 6908 #define F_VLAN V_VLAN(1U) 6909 6910 #define S_VNIC_ID 2 6911 #define V_VNIC_ID(x) ((x) << S_VNIC_ID) 6912 #define F_VNIC_ID V_VNIC_ID(1U) 6913 6914 #define S_PORT 1 6915 #define V_PORT(x) ((x) << S_PORT) 6916 #define F_PORT V_PORT(1U) 6917 6918 #define S_FCOE 0 6919 #define V_FCOE(x) ((x) << S_FCOE) 6920 #define F_FCOE V_FCOE(1U) 6921 6922 #define S_FILTERMODE 15 6923 #define V_FILTERMODE(x) ((x) << S_FILTERMODE) 6924 #define F_FILTERMODE V_FILTERMODE(1U) 6925 6926 #define S_FCOEMASK 14 6927 #define V_FCOEMASK(x) ((x) << S_FCOEMASK) 6928 #define F_FCOEMASK V_FCOEMASK(1U) 6929 6930 #define S_SRVRSRAM 13 6931 #define V_SRVRSRAM(x) ((x) << S_SRVRSRAM) 6932 #define F_SRVRSRAM V_SRVRSRAM(1U) 6933 6934 #define A_TP_INGRESS_CONFIG 0x141 6935 6936 #define S_OPAQUE_TYPE 16 6937 #define M_OPAQUE_TYPE 0xffffU 6938 #define V_OPAQUE_TYPE(x) ((x) << S_OPAQUE_TYPE) 6939 #define G_OPAQUE_TYPE(x) (((x) >> S_OPAQUE_TYPE) & M_OPAQUE_TYPE) 6940 6941 #define S_OPAQUE_RM 15 6942 #define V_OPAQUE_RM(x) ((x) << S_OPAQUE_RM) 6943 #define F_OPAQUE_RM V_OPAQUE_RM(1U) 6944 6945 #define S_OPAQUE_HDR_SIZE 14 6946 #define V_OPAQUE_HDR_SIZE(x) ((x) << S_OPAQUE_HDR_SIZE) 6947 #define F_OPAQUE_HDR_SIZE V_OPAQUE_HDR_SIZE(1U) 6948 6949 #define S_OPAQUE_RM_MAC_IN_MAC 13 6950 #define V_OPAQUE_RM_MAC_IN_MAC(x) ((x) << S_OPAQUE_RM_MAC_IN_MAC) 6951 #define F_OPAQUE_RM_MAC_IN_MAC V_OPAQUE_RM_MAC_IN_MAC(1U) 6952 6953 #define S_FCOE_TARGET 12 6954 #define V_FCOE_TARGET(x) ((x) << S_FCOE_TARGET) 6955 #define F_FCOE_TARGET V_FCOE_TARGET(1U) 6956 6957 #define S_VNIC 11 6958 #define V_VNIC(x) ((x) << S_VNIC) 6959 #define F_VNIC V_VNIC(1U) 6960 6961 #define S_CSUM_HAS_PSEUDO_HDR 10 6962 #define V_CSUM_HAS_PSEUDO_HDR(x) ((x) << S_CSUM_HAS_PSEUDO_HDR) 6963 #define F_CSUM_HAS_PSEUDO_HDR V_CSUM_HAS_PSEUDO_HDR(1U) 6964 6965 #define S_RM_OVLAN 9 6966 #define V_RM_OVLAN(x) ((x) << S_RM_OVLAN) 6967 #define F_RM_OVLAN V_RM_OVLAN(1U) 6968 6969 #define S_LOOKUPEVERYPKT 8 6970 #define V_LOOKUPEVERYPKT(x) ((x) << S_LOOKUPEVERYPKT) 6971 #define F_LOOKUPEVERYPKT V_LOOKUPEVERYPKT(1U) 6972 6973 #define S_IPV6_EXT_HDR_SKIP 0 6974 #define M_IPV6_EXT_HDR_SKIP 0xffU 6975 #define V_IPV6_EXT_HDR_SKIP(x) ((x) << S_IPV6_EXT_HDR_SKIP) 6976 #define G_IPV6_EXT_HDR_SKIP(x) (((x) >> S_IPV6_EXT_HDR_SKIP) & M_IPV6_EXT_HDR_SKIP) 6977 6978 #define S_FRAG_LEN_MOD8_COMPAT 12 6979 #define V_FRAG_LEN_MOD8_COMPAT(x) ((x) << S_FRAG_LEN_MOD8_COMPAT) 6980 #define F_FRAG_LEN_MOD8_COMPAT V_FRAG_LEN_MOD8_COMPAT(1U) 6981 6982 #define S_USE_ENC_IDX 13 6983 #define V_USE_ENC_IDX(x) ((x) << S_USE_ENC_IDX) 6984 #define F_USE_ENC_IDX V_USE_ENC_IDX(1U) 6985 6986 #define A_TP_ESIDE_CONFIG 0x160 6987 6988 #define S_VNI_EN 26 6989 #define V_VNI_EN(x) ((x) << S_VNI_EN) 6990 #define F_VNI_EN V_VNI_EN(1U) 6991 6992 #define S_ENC_RX_EN 25 6993 #define V_ENC_RX_EN(x) ((x) << S_ENC_RX_EN) 6994 #define F_ENC_RX_EN V_ENC_RX_EN(1U) 6995 6996 #define S_TNL_LKP_INNER_SEL 24 6997 #define V_TNL_LKP_INNER_SEL(x) ((x) << S_TNL_LKP_INNER_SEL) 6998 #define F_TNL_LKP_INNER_SEL V_TNL_LKP_INNER_SEL(1U) 6999 7000 #define S_ROCEV2UDPPORT 0 7001 #define M_ROCEV2UDPPORT 0xffffU 7002 #define V_ROCEV2UDPPORT(x) ((x) << S_ROCEV2UDPPORT) 7003 #define G_ROCEV2UDPPORT(x) (((x) >> S_ROCEV2UDPPORT) & M_ROCEV2UDPPORT) 7004 7005 #define A_TP_DBG_CSIDE_RX0 0x230 7006 7007 #define S_CRXSOPCNT 28 7008 #define M_CRXSOPCNT 0xfU 7009 #define V_CRXSOPCNT(x) ((x) << S_CRXSOPCNT) 7010 #define G_CRXSOPCNT(x) (((x) >> S_CRXSOPCNT) & M_CRXSOPCNT) 7011 7012 #define S_CRXEOPCNT 24 7013 #define M_CRXEOPCNT 0xfU 7014 #define V_CRXEOPCNT(x) ((x) << S_CRXEOPCNT) 7015 #define G_CRXEOPCNT(x) (((x) >> S_CRXEOPCNT) & M_CRXEOPCNT) 7016 7017 #define S_CRXPLDSOPCNT 20 7018 #define M_CRXPLDSOPCNT 0xfU 7019 #define V_CRXPLDSOPCNT(x) ((x) << S_CRXPLDSOPCNT) 7020 #define G_CRXPLDSOPCNT(x) (((x) >> S_CRXPLDSOPCNT) & M_CRXPLDSOPCNT) 7021 7022 #define S_CRXPLDEOPCNT 16 7023 #define M_CRXPLDEOPCNT 0xfU 7024 #define V_CRXPLDEOPCNT(x) ((x) << S_CRXPLDEOPCNT) 7025 #define G_CRXPLDEOPCNT(x) (((x) >> S_CRXPLDEOPCNT) & M_CRXPLDEOPCNT) 7026 7027 #define S_CRXARBSOPCNT 12 7028 #define M_CRXARBSOPCNT 0xfU 7029 #define V_CRXARBSOPCNT(x) ((x) << S_CRXARBSOPCNT) 7030 #define G_CRXARBSOPCNT(x) (((x) >> S_CRXARBSOPCNT) & M_CRXARBSOPCNT) 7031 7032 #define S_CRXARBEOPCNT 8 7033 #define M_CRXARBEOPCNT 0xfU 7034 #define V_CRXARBEOPCNT(x) ((x) << S_CRXARBEOPCNT) 7035 #define G_CRXARBEOPCNT(x) (((x) >> S_CRXARBEOPCNT) & M_CRXARBEOPCNT) 7036 7037 #define S_CRXCPLSOPCNT 4 7038 #define M_CRXCPLSOPCNT 0xfU 7039 #define V_CRXCPLSOPCNT(x) ((x) << S_CRXCPLSOPCNT) 7040 #define G_CRXCPLSOPCNT(x) (((x) >> S_CRXCPLSOPCNT) & M_CRXCPLSOPCNT) 7041 7042 #define S_CRXCPLEOPCNT 0 7043 #define M_CRXCPLEOPCNT 0xfU 7044 #define V_CRXCPLEOPCNT(x) ((x) << S_CRXCPLEOPCNT) 7045 #define G_CRXCPLEOPCNT(x) (((x) >> S_CRXCPLEOPCNT) & M_CRXCPLEOPCNT) 7046 7047 #define A_TP_DBG_CSIDE_RX1 0x231 7048 #define A_TP_DBG_CSIDE_RX2 0x232 7049 #define A_TP_DBG_CSIDE_RX3 0x233 7050 #define A_TP_DBG_CSIDE_TX0 0x234 7051 7052 #define S_TXSOPCNT 28 7053 #define M_TXSOPCNT 0xfU 7054 #define V_TXSOPCNT(x) ((x) << S_TXSOPCNT) 7055 #define G_TXSOPCNT(x) (((x) >> S_TXSOPCNT) & M_TXSOPCNT) 7056 7057 #define S_TXEOPCNT 24 7058 #define M_TXEOPCNT 0xfU 7059 #define V_TXEOPCNT(x) ((x) << S_TXEOPCNT) 7060 #define G_TXEOPCNT(x) (((x) >> S_TXEOPCNT) & M_TXEOPCNT) 7061 7062 #define S_TXPLDSOPCNT 20 7063 #define M_TXPLDSOPCNT 0xfU 7064 #define V_TXPLDSOPCNT(x) ((x) << S_TXPLDSOPCNT) 7065 #define G_TXPLDSOPCNT(x) (((x) >> S_TXPLDSOPCNT) & M_TXPLDSOPCNT) 7066 7067 #define S_TXPLDEOPCNT 16 7068 #define M_TXPLDEOPCNT 0xfU 7069 #define V_TXPLDEOPCNT(x) ((x) << S_TXPLDEOPCNT) 7070 #define G_TXPLDEOPCNT(x) (((x) >> S_TXPLDEOPCNT) & M_TXPLDEOPCNT) 7071 7072 #define S_TXARBSOPCNT 12 7073 #define M_TXARBSOPCNT 0xfU 7074 #define V_TXARBSOPCNT(x) ((x) << S_TXARBSOPCNT) 7075 #define G_TXARBSOPCNT(x) (((x) >> S_TXARBSOPCNT) & M_TXARBSOPCNT) 7076 7077 #define S_TXARBEOPCNT 8 7078 #define M_TXARBEOPCNT 0xfU 7079 #define V_TXARBEOPCNT(x) ((x) << S_TXARBEOPCNT) 7080 #define G_TXARBEOPCNT(x) (((x) >> S_TXARBEOPCNT) & M_TXARBEOPCNT) 7081 7082 #define S_TXCPLSOPCNT 4 7083 #define M_TXCPLSOPCNT 0xfU 7084 #define V_TXCPLSOPCNT(x) ((x) << S_TXCPLSOPCNT) 7085 #define G_TXCPLSOPCNT(x) (((x) >> S_TXCPLSOPCNT) & M_TXCPLSOPCNT) 7086 7087 #define S_TXCPLEOPCNT 0 7088 #define M_TXCPLEOPCNT 0xfU 7089 #define V_TXCPLEOPCNT(x) ((x) << S_TXCPLEOPCNT) 7090 #define G_TXCPLEOPCNT(x) (((x) >> S_TXCPLEOPCNT) & M_TXCPLEOPCNT) 7091 7092 #define A_TP_DBG_CSIDE_TX1 0x235 7093 #define A_TP_DBG_CSIDE_TX2 0x236 7094 #define A_TP_DBG_CSIDE_TX3 0x237 7095 #define A_TP_MIB_MAC_IN_ERR_0 0x0 7096 #define A_TP_MIB_MAC_IN_ERR_1 0x1 7097 #define A_TP_MIB_MAC_IN_ERR_2 0x2 7098 #define A_TP_MIB_MAC_IN_ERR_3 0x3 7099 #define A_TP_MIB_HDR_IN_ERR_0 0x4 7100 #define A_TP_MIB_HDR_IN_ERR_1 0x5 7101 #define A_TP_MIB_HDR_IN_ERR_2 0x6 7102 #define A_TP_MIB_HDR_IN_ERR_3 0x7 7103 #define A_TP_MIB_TCP_IN_ERR_0 0x8 7104 #define A_TP_MIB_TCP_IN_ERR_1 0x9 7105 #define A_TP_MIB_TCP_IN_ERR_2 0xa 7106 #define A_TP_MIB_TCP_IN_ERR_3 0xb 7107 #define A_TP_MIB_TCP_OUT_RST 0xc 7108 #define A_TP_MIB_TCP_IN_SEG_HI 0x10 7109 #define A_TP_MIB_TCP_IN_SEG_LO 0x11 7110 #define A_TP_MIB_TCP_OUT_SEG_HI 0x12 7111 #define A_TP_MIB_TCP_OUT_SEG_LO 0x13 7112 #define A_TP_MIB_TCP_RXT_SEG_HI 0x14 7113 #define A_TP_MIB_TCP_RXT_SEG_LO 0x15 7114 #define A_TP_MIB_TNL_CNG_DROP_0 0x18 7115 #define A_TP_MIB_TNL_CNG_DROP_1 0x19 7116 #define A_TP_MIB_TNL_CNG_DROP_2 0x1a 7117 #define A_TP_MIB_TNL_CNG_DROP_3 0x1b 7118 #define A_TP_MIB_OFD_CHN_DROP_0 0x1c 7119 #define A_TP_MIB_OFD_CHN_DROP_1 0x1d 7120 #define A_TP_MIB_OFD_CHN_DROP_2 0x1e 7121 #define A_TP_MIB_OFD_CHN_DROP_3 0x1f 7122 #define A_TP_MIB_TNL_OUT_PKT_0 0x20 7123 #define A_TP_MIB_TNL_OUT_PKT_1 0x21 7124 #define A_TP_MIB_TNL_OUT_PKT_2 0x22 7125 #define A_TP_MIB_TNL_OUT_PKT_3 0x23 7126 #define A_TP_MIB_TNL_IN_PKT_0 0x24 7127 #define A_TP_MIB_TNL_IN_PKT_1 0x25 7128 #define A_TP_MIB_TNL_IN_PKT_2 0x26 7129 #define A_TP_MIB_TNL_IN_PKT_3 0x27 7130 #define A_TP_MIB_TCP_V6IN_ERR_0 0x28 7131 #define A_TP_MIB_TCP_V6IN_ERR_1 0x29 7132 #define A_TP_MIB_TCP_V6IN_ERR_2 0x2a 7133 #define A_TP_MIB_TCP_V6IN_ERR_3 0x2b 7134 #define A_TP_MIB_TCP_V6OUT_RST 0x2c 7135 #define A_TP_MIB_TCP_V6IN_SEG_HI 0x30 7136 #define A_TP_MIB_TCP_V6IN_SEG_LO 0x31 7137 #define A_TP_MIB_TCP_V6OUT_SEG_HI 0x32 7138 #define A_TP_MIB_TCP_V6OUT_SEG_LO 0x33 7139 #define A_TP_MIB_TCP_V6RXT_SEG_HI 0x34 7140 #define A_TP_MIB_TCP_V6RXT_SEG_LO 0x35 7141 #define A_TP_MIB_OFD_ARP_DROP 0x36 7142 #define A_TP_MIB_OFD_DFR_DROP 0x37 7143 #define A_TP_MIB_CPL_IN_REQ_0 0x38 7144 #define A_TP_MIB_CPL_IN_REQ_1 0x39 7145 #define A_TP_MIB_CPL_IN_REQ_2 0x3a 7146 #define A_TP_MIB_CPL_IN_REQ_3 0x3b 7147 #define A_TP_MIB_CPL_OUT_RSP_0 0x3c 7148 #define A_TP_MIB_CPL_OUT_RSP_1 0x3d 7149 #define A_TP_MIB_CPL_OUT_RSP_2 0x3e 7150 #define A_TP_MIB_CPL_OUT_RSP_3 0x3f 7151 #define A_TP_MIB_TNL_LPBK_0 0x40 7152 #define A_TP_MIB_TNL_LPBK_1 0x41 7153 #define A_TP_MIB_TNL_LPBK_2 0x42 7154 #define A_TP_MIB_TNL_LPBK_3 0x43 7155 #define A_TP_MIB_TNL_DROP_0 0x44 7156 #define A_TP_MIB_TNL_DROP_1 0x45 7157 #define A_TP_MIB_TNL_DROP_2 0x46 7158 #define A_TP_MIB_TNL_DROP_3 0x47 7159 #define A_TP_MIB_FCOE_DDP_0 0x48 7160 #define A_TP_MIB_FCOE_DDP_1 0x49 7161 #define A_TP_MIB_FCOE_DDP_2 0x4a 7162 #define A_TP_MIB_FCOE_DDP_3 0x4b 7163 #define A_TP_MIB_FCOE_DROP_0 0x4c 7164 #define A_TP_MIB_FCOE_DROP_1 0x4d 7165 #define A_TP_MIB_FCOE_DROP_2 0x4e 7166 #define A_TP_MIB_FCOE_DROP_3 0x4f 7167 #define A_TP_MIB_FCOE_BYTE_0_HI 0x50 7168 #define A_TP_MIB_FCOE_BYTE_0_LO 0x51 7169 #define A_TP_MIB_FCOE_BYTE_1_HI 0x52 7170 #define A_TP_MIB_FCOE_BYTE_1_LO 0x53 7171 #define A_TP_MIB_FCOE_BYTE_2_HI 0x54 7172 #define A_TP_MIB_FCOE_BYTE_2_LO 0x55 7173 #define A_TP_MIB_FCOE_BYTE_3_HI 0x56 7174 #define A_TP_MIB_FCOE_BYTE_3_LO 0x57 7175 #define A_TP_MIB_OFD_VLN_DROP_0 0x58 7176 #define A_TP_MIB_OFD_VLN_DROP_1 0x59 7177 #define A_TP_MIB_OFD_VLN_DROP_2 0x5a 7178 #define A_TP_MIB_OFD_VLN_DROP_3 0x5b 7179 #define A_TP_MIB_USM_PKTS 0x5c 7180 #define A_TP_MIB_USM_DROP 0x5d 7181 #define A_TP_MIB_USM_BYTES_HI 0x5e 7182 #define A_TP_MIB_USM_BYTES_LO 0x5f 7183 #define A_TP_MIB_TID_DEL 0x60 7184 #define A_TP_MIB_TID_INV 0x61 7185 #define A_TP_MIB_TID_ACT 0x62 7186 #define A_TP_MIB_TID_PAS 0x63 7187 #define A_TP_MIB_RQE_DFR_PKT 0x64 7188 #define A_TP_MIB_RQE_DFR_MOD 0x65 7189 #define A_TP_MIB_CPL_OUT_ERR_0 0x68 7190 #define A_TP_MIB_CPL_OUT_ERR_1 0x69 7191 #define A_TP_MIB_CPL_OUT_ERR_2 0x6a 7192 #define A_TP_MIB_CPL_OUT_ERR_3 0x6b 7193 #define A_TP_MIB_ENG_LINE_0 0x6c 7194 #define A_TP_MIB_ENG_LINE_1 0x6d 7195 #define A_TP_MIB_ENG_LINE_2 0x6e 7196 #define A_TP_MIB_ENG_LINE_3 0x6f 7197 #define A_TP_MIB_TNL_ERR_0 0x70 7198 #define A_TP_MIB_TNL_ERR_1 0x71 7199 #define A_TP_MIB_TNL_ERR_2 0x72 7200 #define A_TP_MIB_TNL_ERR_3 0x73 7201 7202 /* registers for module ULP_TX */ 7203 #define ULP_TX_BASE_ADDR 0x8dc0 7204 7205 #define A_ULP_TX_INT_CAUSE 0x8dcc 7206 7207 #define S_PBL_BOUND_ERR_CH3 31 7208 #define V_PBL_BOUND_ERR_CH3(x) ((x) << S_PBL_BOUND_ERR_CH3) 7209 #define F_PBL_BOUND_ERR_CH3 V_PBL_BOUND_ERR_CH3(1U) 7210 7211 #define S_PBL_BOUND_ERR_CH2 30 7212 #define V_PBL_BOUND_ERR_CH2(x) ((x) << S_PBL_BOUND_ERR_CH2) 7213 #define F_PBL_BOUND_ERR_CH2 V_PBL_BOUND_ERR_CH2(1U) 7214 7215 #define S_PBL_BOUND_ERR_CH1 29 7216 #define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1) 7217 #define F_PBL_BOUND_ERR_CH1 V_PBL_BOUND_ERR_CH1(1U) 7218 7219 #define S_PBL_BOUND_ERR_CH0 28 7220 #define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0) 7221 #define F_PBL_BOUND_ERR_CH0 V_PBL_BOUND_ERR_CH0(1U) 7222 7223 #define S_SGE2ULP_FIFO_PERR_SET3 27 7224 #define V_SGE2ULP_FIFO_PERR_SET3(x) ((x) << S_SGE2ULP_FIFO_PERR_SET3) 7225 #define F_SGE2ULP_FIFO_PERR_SET3 V_SGE2ULP_FIFO_PERR_SET3(1U) 7226 7227 #define S_SGE2ULP_FIFO_PERR_SET2 26 7228 #define V_SGE2ULP_FIFO_PERR_SET2(x) ((x) << S_SGE2ULP_FIFO_PERR_SET2) 7229 #define F_SGE2ULP_FIFO_PERR_SET2 V_SGE2ULP_FIFO_PERR_SET2(1U) 7230 7231 #define S_SGE2ULP_FIFO_PERR_SET1 25 7232 #define V_SGE2ULP_FIFO_PERR_SET1(x) ((x) << S_SGE2ULP_FIFO_PERR_SET1) 7233 #define F_SGE2ULP_FIFO_PERR_SET1 V_SGE2ULP_FIFO_PERR_SET1(1U) 7234 7235 #define S_SGE2ULP_FIFO_PERR_SET0 24 7236 #define V_SGE2ULP_FIFO_PERR_SET0(x) ((x) << S_SGE2ULP_FIFO_PERR_SET0) 7237 #define F_SGE2ULP_FIFO_PERR_SET0 V_SGE2ULP_FIFO_PERR_SET0(1U) 7238 7239 #define S_CIM2ULP_FIFO_PERR_SET3 23 7240 #define V_CIM2ULP_FIFO_PERR_SET3(x) ((x) << S_CIM2ULP_FIFO_PERR_SET3) 7241 #define F_CIM2ULP_FIFO_PERR_SET3 V_CIM2ULP_FIFO_PERR_SET3(1U) 7242 7243 #define S_CIM2ULP_FIFO_PERR_SET2 22 7244 #define V_CIM2ULP_FIFO_PERR_SET2(x) ((x) << S_CIM2ULP_FIFO_PERR_SET2) 7245 #define F_CIM2ULP_FIFO_PERR_SET2 V_CIM2ULP_FIFO_PERR_SET2(1U) 7246 7247 #define S_CIM2ULP_FIFO_PERR_SET1 21 7248 #define V_CIM2ULP_FIFO_PERR_SET1(x) ((x) << S_CIM2ULP_FIFO_PERR_SET1) 7249 #define F_CIM2ULP_FIFO_PERR_SET1 V_CIM2ULP_FIFO_PERR_SET1(1U) 7250 7251 #define S_CIM2ULP_FIFO_PERR_SET0 20 7252 #define V_CIM2ULP_FIFO_PERR_SET0(x) ((x) << S_CIM2ULP_FIFO_PERR_SET0) 7253 #define F_CIM2ULP_FIFO_PERR_SET0 V_CIM2ULP_FIFO_PERR_SET0(1U) 7254 7255 #define S_CQE_FIFO_PERR_SET3 19 7256 #define V_CQE_FIFO_PERR_SET3(x) ((x) << S_CQE_FIFO_PERR_SET3) 7257 #define F_CQE_FIFO_PERR_SET3 V_CQE_FIFO_PERR_SET3(1U) 7258 7259 #define S_CQE_FIFO_PERR_SET2 18 7260 #define V_CQE_FIFO_PERR_SET2(x) ((x) << S_CQE_FIFO_PERR_SET2) 7261 #define F_CQE_FIFO_PERR_SET2 V_CQE_FIFO_PERR_SET2(1U) 7262 7263 #define S_CQE_FIFO_PERR_SET1 17 7264 #define V_CQE_FIFO_PERR_SET1(x) ((x) << S_CQE_FIFO_PERR_SET1) 7265 #define F_CQE_FIFO_PERR_SET1 V_CQE_FIFO_PERR_SET1(1U) 7266 7267 #define S_CQE_FIFO_PERR_SET0 16 7268 #define V_CQE_FIFO_PERR_SET0(x) ((x) << S_CQE_FIFO_PERR_SET0) 7269 #define F_CQE_FIFO_PERR_SET0 V_CQE_FIFO_PERR_SET0(1U) 7270 7271 #define S_PBL_FIFO_PERR_SET3 15 7272 #define V_PBL_FIFO_PERR_SET3(x) ((x) << S_PBL_FIFO_PERR_SET3) 7273 #define F_PBL_FIFO_PERR_SET3 V_PBL_FIFO_PERR_SET3(1U) 7274 7275 #define S_PBL_FIFO_PERR_SET2 14 7276 #define V_PBL_FIFO_PERR_SET2(x) ((x) << S_PBL_FIFO_PERR_SET2) 7277 #define F_PBL_FIFO_PERR_SET2 V_PBL_FIFO_PERR_SET2(1U) 7278 7279 #define S_PBL_FIFO_PERR_SET1 13 7280 #define V_PBL_FIFO_PERR_SET1(x) ((x) << S_PBL_FIFO_PERR_SET1) 7281 #define F_PBL_FIFO_PERR_SET1 V_PBL_FIFO_PERR_SET1(1U) 7282 7283 #define S_PBL_FIFO_PERR_SET0 12 7284 #define V_PBL_FIFO_PERR_SET0(x) ((x) << S_PBL_FIFO_PERR_SET0) 7285 #define F_PBL_FIFO_PERR_SET0 V_PBL_FIFO_PERR_SET0(1U) 7286 7287 #define S_CMD_FIFO_PERR_SET3 11 7288 #define V_CMD_FIFO_PERR_SET3(x) ((x) << S_CMD_FIFO_PERR_SET3) 7289 #define F_CMD_FIFO_PERR_SET3 V_CMD_FIFO_PERR_SET3(1U) 7290 7291 #define S_CMD_FIFO_PERR_SET2 10 7292 #define V_CMD_FIFO_PERR_SET2(x) ((x) << S_CMD_FIFO_PERR_SET2) 7293 #define F_CMD_FIFO_PERR_SET2 V_CMD_FIFO_PERR_SET2(1U) 7294 7295 #define S_CMD_FIFO_PERR_SET1 9 7296 #define V_CMD_FIFO_PERR_SET1(x) ((x) << S_CMD_FIFO_PERR_SET1) 7297 #define F_CMD_FIFO_PERR_SET1 V_CMD_FIFO_PERR_SET1(1U) 7298 7299 #define S_CMD_FIFO_PERR_SET0 8 7300 #define V_CMD_FIFO_PERR_SET0(x) ((x) << S_CMD_FIFO_PERR_SET0) 7301 #define F_CMD_FIFO_PERR_SET0 V_CMD_FIFO_PERR_SET0(1U) 7302 7303 #define S_LSO_HDR_SRAM_PERR_SET3 7 7304 #define V_LSO_HDR_SRAM_PERR_SET3(x) ((x) << S_LSO_HDR_SRAM_PERR_SET3) 7305 #define F_LSO_HDR_SRAM_PERR_SET3 V_LSO_HDR_SRAM_PERR_SET3(1U) 7306 7307 #define S_LSO_HDR_SRAM_PERR_SET2 6 7308 #define V_LSO_HDR_SRAM_PERR_SET2(x) ((x) << S_LSO_HDR_SRAM_PERR_SET2) 7309 #define F_LSO_HDR_SRAM_PERR_SET2 V_LSO_HDR_SRAM_PERR_SET2(1U) 7310 7311 #define S_LSO_HDR_SRAM_PERR_SET1 5 7312 #define V_LSO_HDR_SRAM_PERR_SET1(x) ((x) << S_LSO_HDR_SRAM_PERR_SET1) 7313 #define F_LSO_HDR_SRAM_PERR_SET1 V_LSO_HDR_SRAM_PERR_SET1(1U) 7314 7315 #define S_LSO_HDR_SRAM_PERR_SET0 4 7316 #define V_LSO_HDR_SRAM_PERR_SET0(x) ((x) << S_LSO_HDR_SRAM_PERR_SET0) 7317 #define F_LSO_HDR_SRAM_PERR_SET0 V_LSO_HDR_SRAM_PERR_SET0(1U) 7318 7319 #define S_IMM_DATA_PERR_SET_CH3 3 7320 #define V_IMM_DATA_PERR_SET_CH3(x) ((x) << S_IMM_DATA_PERR_SET_CH3) 7321 #define F_IMM_DATA_PERR_SET_CH3 V_IMM_DATA_PERR_SET_CH3(1U) 7322 7323 #define S_IMM_DATA_PERR_SET_CH2 2 7324 #define V_IMM_DATA_PERR_SET_CH2(x) ((x) << S_IMM_DATA_PERR_SET_CH2) 7325 #define F_IMM_DATA_PERR_SET_CH2 V_IMM_DATA_PERR_SET_CH2(1U) 7326 7327 #define S_IMM_DATA_PERR_SET_CH1 1 7328 #define V_IMM_DATA_PERR_SET_CH1(x) ((x) << S_IMM_DATA_PERR_SET_CH1) 7329 #define F_IMM_DATA_PERR_SET_CH1 V_IMM_DATA_PERR_SET_CH1(1U) 7330 7331 #define S_IMM_DATA_PERR_SET_CH0 0 7332 #define V_IMM_DATA_PERR_SET_CH0(x) ((x) << S_IMM_DATA_PERR_SET_CH0) 7333 #define F_IMM_DATA_PERR_SET_CH0 V_IMM_DATA_PERR_SET_CH0(1U) 7334 7335 #define A_ULP_TX_TPT_LLIMIT 0x8dd4 7336 #define A_ULP_TX_TPT_ULIMIT 0x8dd8 7337 #define A_ULP_TX_PBL_LLIMIT 0x8ddc 7338 #define A_ULP_TX_PBL_ULIMIT 0x8de0 7339 #define A_ULP_TX_ERR_TABLE_BASE 0x8e04 7340 #define A_ULP_TX_ULP2TP_BIST_CMD 0x8e30 7341 #define A_ULP_TX_ULP2TP_BIST_ERROR_CNT 0x8e34 7342 #define A_ULP_TX_FPGA_CMD_CTRL 0x8e38 7343 #define A_ULP_TX_FPGA_CMD_0 0x8e3c 7344 #define A_ULP_TX_FPGA_CMD_1 0x8e40 7345 #define A_ULP_TX_FPGA_CMD_2 0x8e44 7346 #define A_ULP_TX_FPGA_CMD_3 0x8e48 7347 #define A_ULP_TX_FPGA_CMD_4 0x8e4c 7348 #define A_ULP_TX_FPGA_CMD_5 0x8e50 7349 #define A_ULP_TX_FPGA_CMD_6 0x8e54 7350 #define A_ULP_TX_FPGA_CMD_7 0x8e58 7351 #define A_ULP_TX_FPGA_CMD_8 0x8e5c 7352 #define A_ULP_TX_FPGA_CMD_9 0x8e60 7353 #define A_ULP_TX_FPGA_CMD_10 0x8e64 7354 #define A_ULP_TX_FPGA_CMD_11 0x8e68 7355 #define A_ULP_TX_FPGA_CMD_12 0x8e6c 7356 #define A_ULP_TX_FPGA_CMD_13 0x8e70 7357 #define A_ULP_TX_FPGA_CMD_14 0x8e74 7358 #define A_ULP_TX_FPGA_CMD_15 0x8e78 7359 #define A_ULP_TX_INT_CAUSE_2 0x8e80 7360 7361 #define S_SMARBT2ULP_DATA_PERR_SET 12 7362 #define V_SMARBT2ULP_DATA_PERR_SET(x) ((x) << S_SMARBT2ULP_DATA_PERR_SET) 7363 #define F_SMARBT2ULP_DATA_PERR_SET V_SMARBT2ULP_DATA_PERR_SET(1U) 7364 7365 #define S_ULP2TP_DATA_PERR_SET 11 7366 #define V_ULP2TP_DATA_PERR_SET(x) ((x) << S_ULP2TP_DATA_PERR_SET) 7367 #define F_ULP2TP_DATA_PERR_SET V_ULP2TP_DATA_PERR_SET(1U) 7368 7369 #define S_MA2ULP_DATA_PERR_SET 10 7370 #define V_MA2ULP_DATA_PERR_SET(x) ((x) << S_MA2ULP_DATA_PERR_SET) 7371 #define F_MA2ULP_DATA_PERR_SET V_MA2ULP_DATA_PERR_SET(1U) 7372 7373 #define S_SGE2ULP_DATA_PERR_SET 9 7374 #define V_SGE2ULP_DATA_PERR_SET(x) ((x) << S_SGE2ULP_DATA_PERR_SET) 7375 #define F_SGE2ULP_DATA_PERR_SET V_SGE2ULP_DATA_PERR_SET(1U) 7376 7377 #define S_CIM2ULP_DATA_PERR_SET 8 7378 #define V_CIM2ULP_DATA_PERR_SET(x) ((x) << S_CIM2ULP_DATA_PERR_SET) 7379 #define F_CIM2ULP_DATA_PERR_SET V_CIM2ULP_DATA_PERR_SET(1U) 7380 7381 #define S_FSO_HDR_SRAM_PERR_SET3 7 7382 #define V_FSO_HDR_SRAM_PERR_SET3(x) ((x) << S_FSO_HDR_SRAM_PERR_SET3) 7383 #define F_FSO_HDR_SRAM_PERR_SET3 V_FSO_HDR_SRAM_PERR_SET3(1U) 7384 7385 #define S_FSO_HDR_SRAM_PERR_SET2 6 7386 #define V_FSO_HDR_SRAM_PERR_SET2(x) ((x) << S_FSO_HDR_SRAM_PERR_SET2) 7387 #define F_FSO_HDR_SRAM_PERR_SET2 V_FSO_HDR_SRAM_PERR_SET2(1U) 7388 7389 #define S_FSO_HDR_SRAM_PERR_SET1 5 7390 #define V_FSO_HDR_SRAM_PERR_SET1(x) ((x) << S_FSO_HDR_SRAM_PERR_SET1) 7391 #define F_FSO_HDR_SRAM_PERR_SET1 V_FSO_HDR_SRAM_PERR_SET1(1U) 7392 7393 #define S_FSO_HDR_SRAM_PERR_SET0 4 7394 #define V_FSO_HDR_SRAM_PERR_SET0(x) ((x) << S_FSO_HDR_SRAM_PERR_SET0) 7395 #define F_FSO_HDR_SRAM_PERR_SET0 V_FSO_HDR_SRAM_PERR_SET0(1U) 7396 7397 #define S_T10_PI_SRAM_PERR_SET3 3 7398 #define V_T10_PI_SRAM_PERR_SET3(x) ((x) << S_T10_PI_SRAM_PERR_SET3) 7399 #define F_T10_PI_SRAM_PERR_SET3 V_T10_PI_SRAM_PERR_SET3(1U) 7400 7401 #define S_T10_PI_SRAM_PERR_SET2 2 7402 #define V_T10_PI_SRAM_PERR_SET2(x) ((x) << S_T10_PI_SRAM_PERR_SET2) 7403 #define F_T10_PI_SRAM_PERR_SET2 V_T10_PI_SRAM_PERR_SET2(1U) 7404 7405 #define S_T10_PI_SRAM_PERR_SET1 1 7406 #define V_T10_PI_SRAM_PERR_SET1(x) ((x) << S_T10_PI_SRAM_PERR_SET1) 7407 #define F_T10_PI_SRAM_PERR_SET1 V_T10_PI_SRAM_PERR_SET1(1U) 7408 7409 #define S_T10_PI_SRAM_PERR_SET0 0 7410 #define V_T10_PI_SRAM_PERR_SET0(x) ((x) << S_T10_PI_SRAM_PERR_SET0) 7411 #define F_T10_PI_SRAM_PERR_SET0 V_T10_PI_SRAM_PERR_SET0(1U) 7412 7413 #define S_EDMA_IN_FIFO_PERR_SET3 31 7414 #define V_EDMA_IN_FIFO_PERR_SET3(x) ((x) << S_EDMA_IN_FIFO_PERR_SET3) 7415 #define F_EDMA_IN_FIFO_PERR_SET3 V_EDMA_IN_FIFO_PERR_SET3(1U) 7416 7417 #define S_EDMA_IN_FIFO_PERR_SET2 30 7418 #define V_EDMA_IN_FIFO_PERR_SET2(x) ((x) << S_EDMA_IN_FIFO_PERR_SET2) 7419 #define F_EDMA_IN_FIFO_PERR_SET2 V_EDMA_IN_FIFO_PERR_SET2(1U) 7420 7421 #define S_EDMA_IN_FIFO_PERR_SET1 29 7422 #define V_EDMA_IN_FIFO_PERR_SET1(x) ((x) << S_EDMA_IN_FIFO_PERR_SET1) 7423 #define F_EDMA_IN_FIFO_PERR_SET1 V_EDMA_IN_FIFO_PERR_SET1(1U) 7424 7425 #define S_EDMA_IN_FIFO_PERR_SET0 28 7426 #define V_EDMA_IN_FIFO_PERR_SET0(x) ((x) << S_EDMA_IN_FIFO_PERR_SET0) 7427 #define F_EDMA_IN_FIFO_PERR_SET0 V_EDMA_IN_FIFO_PERR_SET0(1U) 7428 7429 #define S_ALIGN_CTL_FIFO_PERR_SET3 27 7430 #define V_ALIGN_CTL_FIFO_PERR_SET3(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET3) 7431 #define F_ALIGN_CTL_FIFO_PERR_SET3 V_ALIGN_CTL_FIFO_PERR_SET3(1U) 7432 7433 #define S_ALIGN_CTL_FIFO_PERR_SET2 26 7434 #define V_ALIGN_CTL_FIFO_PERR_SET2(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET2) 7435 #define F_ALIGN_CTL_FIFO_PERR_SET2 V_ALIGN_CTL_FIFO_PERR_SET2(1U) 7436 7437 #define S_ALIGN_CTL_FIFO_PERR_SET1 25 7438 #define V_ALIGN_CTL_FIFO_PERR_SET1(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET1) 7439 #define F_ALIGN_CTL_FIFO_PERR_SET1 V_ALIGN_CTL_FIFO_PERR_SET1(1U) 7440 7441 #define S_ALIGN_CTL_FIFO_PERR_SET0 24 7442 #define V_ALIGN_CTL_FIFO_PERR_SET0(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET0) 7443 #define F_ALIGN_CTL_FIFO_PERR_SET0 V_ALIGN_CTL_FIFO_PERR_SET0(1U) 7444 7445 #define S_SGE_FIFO_PERR_SET3 23 7446 #define V_SGE_FIFO_PERR_SET3(x) ((x) << S_SGE_FIFO_PERR_SET3) 7447 #define F_SGE_FIFO_PERR_SET3 V_SGE_FIFO_PERR_SET3(1U) 7448 7449 #define S_SGE_FIFO_PERR_SET2 22 7450 #define V_SGE_FIFO_PERR_SET2(x) ((x) << S_SGE_FIFO_PERR_SET2) 7451 #define F_SGE_FIFO_PERR_SET2 V_SGE_FIFO_PERR_SET2(1U) 7452 7453 #define S_SGE_FIFO_PERR_SET1 21 7454 #define V_SGE_FIFO_PERR_SET1(x) ((x) << S_SGE_FIFO_PERR_SET1) 7455 #define F_SGE_FIFO_PERR_SET1 V_SGE_FIFO_PERR_SET1(1U) 7456 7457 #define S_SGE_FIFO_PERR_SET0 20 7458 #define V_SGE_FIFO_PERR_SET0(x) ((x) << S_SGE_FIFO_PERR_SET0) 7459 #define F_SGE_FIFO_PERR_SET0 V_SGE_FIFO_PERR_SET0(1U) 7460 7461 #define S_STAG_FIFO_PERR_SET3 19 7462 #define V_STAG_FIFO_PERR_SET3(x) ((x) << S_STAG_FIFO_PERR_SET3) 7463 #define F_STAG_FIFO_PERR_SET3 V_STAG_FIFO_PERR_SET3(1U) 7464 7465 #define S_STAG_FIFO_PERR_SET2 18 7466 #define V_STAG_FIFO_PERR_SET2(x) ((x) << S_STAG_FIFO_PERR_SET2) 7467 #define F_STAG_FIFO_PERR_SET2 V_STAG_FIFO_PERR_SET2(1U) 7468 7469 #define S_STAG_FIFO_PERR_SET1 17 7470 #define V_STAG_FIFO_PERR_SET1(x) ((x) << S_STAG_FIFO_PERR_SET1) 7471 #define F_STAG_FIFO_PERR_SET1 V_STAG_FIFO_PERR_SET1(1U) 7472 7473 #define S_STAG_FIFO_PERR_SET0 16 7474 #define V_STAG_FIFO_PERR_SET0(x) ((x) << S_STAG_FIFO_PERR_SET0) 7475 #define F_STAG_FIFO_PERR_SET0 V_STAG_FIFO_PERR_SET0(1U) 7476 7477 #define S_MAP_FIFO_PERR_SET3 15 7478 #define V_MAP_FIFO_PERR_SET3(x) ((x) << S_MAP_FIFO_PERR_SET3) 7479 #define F_MAP_FIFO_PERR_SET3 V_MAP_FIFO_PERR_SET3(1U) 7480 7481 #define S_MAP_FIFO_PERR_SET2 14 7482 #define V_MAP_FIFO_PERR_SET2(x) ((x) << S_MAP_FIFO_PERR_SET2) 7483 #define F_MAP_FIFO_PERR_SET2 V_MAP_FIFO_PERR_SET2(1U) 7484 7485 #define S_MAP_FIFO_PERR_SET1 13 7486 #define V_MAP_FIFO_PERR_SET1(x) ((x) << S_MAP_FIFO_PERR_SET1) 7487 #define F_MAP_FIFO_PERR_SET1 V_MAP_FIFO_PERR_SET1(1U) 7488 7489 #define S_MAP_FIFO_PERR_SET0 12 7490 #define V_MAP_FIFO_PERR_SET0(x) ((x) << S_MAP_FIFO_PERR_SET0) 7491 #define F_MAP_FIFO_PERR_SET0 V_MAP_FIFO_PERR_SET0(1U) 7492 7493 #define S_DMA_FIFO_PERR_SET3 11 7494 #define V_DMA_FIFO_PERR_SET3(x) ((x) << S_DMA_FIFO_PERR_SET3) 7495 #define F_DMA_FIFO_PERR_SET3 V_DMA_FIFO_PERR_SET3(1U) 7496 7497 #define S_DMA_FIFO_PERR_SET2 10 7498 #define V_DMA_FIFO_PERR_SET2(x) ((x) << S_DMA_FIFO_PERR_SET2) 7499 #define F_DMA_FIFO_PERR_SET2 V_DMA_FIFO_PERR_SET2(1U) 7500 7501 #define S_DMA_FIFO_PERR_SET1 9 7502 #define V_DMA_FIFO_PERR_SET1(x) ((x) << S_DMA_FIFO_PERR_SET1) 7503 #define F_DMA_FIFO_PERR_SET1 V_DMA_FIFO_PERR_SET1(1U) 7504 7505 #define S_DMA_FIFO_PERR_SET0 8 7506 #define V_DMA_FIFO_PERR_SET0(x) ((x) << S_DMA_FIFO_PERR_SET0) 7507 #define F_DMA_FIFO_PERR_SET0 V_DMA_FIFO_PERR_SET0(1U) 7508 7509 #define A_ULP_TX_SE_CNT_CH0 0x8ea8 7510 7511 #define S_SOP_CNT_ULP2TP 28 7512 #define M_SOP_CNT_ULP2TP 0xfU 7513 #define V_SOP_CNT_ULP2TP(x) ((x) << S_SOP_CNT_ULP2TP) 7514 #define G_SOP_CNT_ULP2TP(x) (((x) >> S_SOP_CNT_ULP2TP) & M_SOP_CNT_ULP2TP) 7515 7516 #define S_EOP_CNT_ULP2TP 24 7517 #define M_EOP_CNT_ULP2TP 0xfU 7518 #define V_EOP_CNT_ULP2TP(x) ((x) << S_EOP_CNT_ULP2TP) 7519 #define G_EOP_CNT_ULP2TP(x) (((x) >> S_EOP_CNT_ULP2TP) & M_EOP_CNT_ULP2TP) 7520 7521 #define S_SOP_CNT_LSO_IN 20 7522 #define M_SOP_CNT_LSO_IN 0xfU 7523 #define V_SOP_CNT_LSO_IN(x) ((x) << S_SOP_CNT_LSO_IN) 7524 #define G_SOP_CNT_LSO_IN(x) (((x) >> S_SOP_CNT_LSO_IN) & M_SOP_CNT_LSO_IN) 7525 7526 #define S_EOP_CNT_LSO_IN 16 7527 #define M_EOP_CNT_LSO_IN 0xfU 7528 #define V_EOP_CNT_LSO_IN(x) ((x) << S_EOP_CNT_LSO_IN) 7529 #define G_EOP_CNT_LSO_IN(x) (((x) >> S_EOP_CNT_LSO_IN) & M_EOP_CNT_LSO_IN) 7530 7531 #define S_SOP_CNT_ALG_IN 12 7532 #define M_SOP_CNT_ALG_IN 0xfU 7533 #define V_SOP_CNT_ALG_IN(x) ((x) << S_SOP_CNT_ALG_IN) 7534 #define G_SOP_CNT_ALG_IN(x) (((x) >> S_SOP_CNT_ALG_IN) & M_SOP_CNT_ALG_IN) 7535 7536 #define S_EOP_CNT_ALG_IN 8 7537 #define M_EOP_CNT_ALG_IN 0xfU 7538 #define V_EOP_CNT_ALG_IN(x) ((x) << S_EOP_CNT_ALG_IN) 7539 #define G_EOP_CNT_ALG_IN(x) (((x) >> S_EOP_CNT_ALG_IN) & M_EOP_CNT_ALG_IN) 7540 7541 #define S_SOP_CNT_CIM2ULP 4 7542 #define M_SOP_CNT_CIM2ULP 0xfU 7543 #define V_SOP_CNT_CIM2ULP(x) ((x) << S_SOP_CNT_CIM2ULP) 7544 #define G_SOP_CNT_CIM2ULP(x) (((x) >> S_SOP_CNT_CIM2ULP) & M_SOP_CNT_CIM2ULP) 7545 7546 #define S_EOP_CNT_CIM2ULP 0 7547 #define M_EOP_CNT_CIM2ULP 0xfU 7548 #define V_EOP_CNT_CIM2ULP(x) ((x) << S_EOP_CNT_CIM2ULP) 7549 #define G_EOP_CNT_CIM2ULP(x) (((x) >> S_EOP_CNT_CIM2ULP) & M_EOP_CNT_CIM2ULP) 7550 7551 #define A_ULP_TX_T5_SE_CNT_CH0 0x8ea8 7552 #define A_ULP_TX_SE_CNT_CH1 0x8eac 7553 #define A_ULP_TX_T5_SE_CNT_CH1 0x8eac 7554 #define A_ULP_TX_SE_CNT_CH2 0x8eb0 7555 #define A_ULP_TX_T5_SE_CNT_CH2 0x8eb0 7556 #define A_ULP_TX_SE_CNT_CH3 0x8eb4 7557 #define A_ULP_TX_T5_SE_CNT_CH3 0x8eb4 7558 #define A_ULP_TX_CSU_REVISION 0x8ebc 7559 #define A_ULP_TX_LA_RDPTR_0 0x8ec0 7560 #define A_ULP_TX_LA_RDDATA_0 0x8ec4 7561 #define A_ULP_TX_LA_WRPTR_0 0x8ec8 7562 #define A_ULP_TX_LA_RESERVED_0 0x8ecc 7563 #define A_ULP_TX_LA_RDPTR_1 0x8ed0 7564 #define A_ULP_TX_LA_RDDATA_1 0x8ed4 7565 #define A_ULP_TX_LA_WRPTR_1 0x8ed8 7566 #define A_ULP_TX_LA_RESERVED_1 0x8edc 7567 #define A_ULP_TX_LA_RDPTR_2 0x8ee0 7568 #define A_ULP_TX_LA_RDDATA_2 0x8ee4 7569 #define A_ULP_TX_LA_WRPTR_2 0x8ee8 7570 #define A_ULP_TX_LA_RESERVED_2 0x8eec 7571 #define A_ULP_TX_LA_RDPTR_3 0x8ef0 7572 #define A_ULP_TX_LA_RDDATA_3 0x8ef4 7573 #define A_ULP_TX_LA_WRPTR_3 0x8ef8 7574 #define A_ULP_TX_LA_RESERVED_3 0x8efc 7575 #define A_ULP_TX_LA_RDPTR_4 0x8f00 7576 #define A_ULP_TX_LA_RDDATA_4 0x8f04 7577 #define A_ULP_TX_LA_WRPTR_4 0x8f08 7578 #define A_ULP_TX_LA_RESERVED_4 0x8f0c 7579 #define A_ULP_TX_LA_RDPTR_5 0x8f10 7580 #define A_ULP_TX_LA_RDDATA_5 0x8f14 7581 #define A_ULP_TX_LA_WRPTR_5 0x8f18 7582 #define A_ULP_TX_LA_RESERVED_5 0x8f1c 7583 #define A_ULP_TX_LA_RDPTR_6 0x8f20 7584 #define A_ULP_TX_LA_RDDATA_6 0x8f24 7585 #define A_ULP_TX_LA_WRPTR_6 0x8f28 7586 #define A_ULP_TX_LA_RESERVED_6 0x8f2c 7587 #define A_ULP_TX_LA_RDPTR_7 0x8f30 7588 #define A_ULP_TX_LA_RDDATA_7 0x8f34 7589 #define A_ULP_TX_LA_WRPTR_7 0x8f38 7590 #define A_ULP_TX_LA_RESERVED_7 0x8f3c 7591 #define A_ULP_TX_LA_RDPTR_8 0x8f40 7592 #define A_ULP_TX_LA_RDDATA_8 0x8f44 7593 #define A_ULP_TX_LA_WRPTR_8 0x8f48 7594 #define A_ULP_TX_LA_RESERVED_8 0x8f4c 7595 #define A_ULP_TX_LA_RDPTR_9 0x8f50 7596 #define A_ULP_TX_LA_RDDATA_9 0x8f54 7597 #define A_ULP_TX_LA_WRPTR_9 0x8f58 7598 #define A_ULP_TX_LA_RESERVED_9 0x8f5c 7599 #define A_ULP_TX_LA_RDPTR_10 0x8f60 7600 #define A_ULP_TX_LA_RDDATA_10 0x8f64 7601 #define A_ULP_TX_LA_WRPTR_10 0x8f68 7602 #define A_ULP_TX_LA_RESERVED_10 0x8f6c 7603 7604 /* registers for module PM_RX */ 7605 #define PM_RX_BASE_ADDR 0x8fc0 7606 7607 #define A_PM_RX_STAT_CONFIG 0x8fc8 7608 #define A_PM_RX_STAT_COUNT 0x8fcc 7609 #define A_PM_RX_STAT_LSB 0x8fd0 7610 #define A_PM_RX_DBG_CTRL 0x8fd0 7611 7612 #define S_OSPIWRBUSY_T5 21 7613 #define M_OSPIWRBUSY_T5 0x3U 7614 #define V_OSPIWRBUSY_T5(x) ((x) << S_OSPIWRBUSY_T5) 7615 #define G_OSPIWRBUSY_T5(x) (((x) >> S_OSPIWRBUSY_T5) & M_OSPIWRBUSY_T5) 7616 7617 #define S_ISPIWRBUSY 17 7618 #define M_ISPIWRBUSY 0xfU 7619 #define V_ISPIWRBUSY(x) ((x) << S_ISPIWRBUSY) 7620 #define G_ISPIWRBUSY(x) (((x) >> S_ISPIWRBUSY) & M_ISPIWRBUSY) 7621 7622 #define S_PMDBGADDR 0 7623 #define M_PMDBGADDR 0x1ffffU 7624 #define V_PMDBGADDR(x) ((x) << S_PMDBGADDR) 7625 #define G_PMDBGADDR(x) (((x) >> S_PMDBGADDR) & M_PMDBGADDR) 7626 7627 #define A_PM_RX_STAT_MSB 0x8fd4 7628 #define A_PM_RX_DBG_DATA 0x8fd4 7629 #define A_PM_RX_INT_CAUSE 0x8fdc 7630 7631 #define S_ZERO_E_CMD_ERROR 22 7632 #define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR) 7633 #define F_ZERO_E_CMD_ERROR V_ZERO_E_CMD_ERROR(1U) 7634 7635 #define S_IESPI0_FIFO2X_RX_FRAMING_ERROR 21 7636 #define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR) 7637 #define F_IESPI0_FIFO2X_RX_FRAMING_ERROR V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U) 7638 7639 #define S_IESPI1_FIFO2X_RX_FRAMING_ERROR 20 7640 #define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR) 7641 #define F_IESPI1_FIFO2X_RX_FRAMING_ERROR V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U) 7642 7643 #define S_IESPI2_FIFO2X_RX_FRAMING_ERROR 19 7644 #define V_IESPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_FIFO2X_RX_FRAMING_ERROR) 7645 #define F_IESPI2_FIFO2X_RX_FRAMING_ERROR V_IESPI2_FIFO2X_RX_FRAMING_ERROR(1U) 7646 7647 #define S_IESPI3_FIFO2X_RX_FRAMING_ERROR 18 7648 #define V_IESPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_FIFO2X_RX_FRAMING_ERROR) 7649 #define F_IESPI3_FIFO2X_RX_FRAMING_ERROR V_IESPI3_FIFO2X_RX_FRAMING_ERROR(1U) 7650 7651 #define S_IESPI0_RX_FRAMING_ERROR 17 7652 #define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR) 7653 #define F_IESPI0_RX_FRAMING_ERROR V_IESPI0_RX_FRAMING_ERROR(1U) 7654 7655 #define S_IESPI1_RX_FRAMING_ERROR 16 7656 #define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR) 7657 #define F_IESPI1_RX_FRAMING_ERROR V_IESPI1_RX_FRAMING_ERROR(1U) 7658 7659 #define S_IESPI2_RX_FRAMING_ERROR 15 7660 #define V_IESPI2_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_RX_FRAMING_ERROR) 7661 #define F_IESPI2_RX_FRAMING_ERROR V_IESPI2_RX_FRAMING_ERROR(1U) 7662 7663 #define S_IESPI3_RX_FRAMING_ERROR 14 7664 #define V_IESPI3_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_RX_FRAMING_ERROR) 7665 #define F_IESPI3_RX_FRAMING_ERROR V_IESPI3_RX_FRAMING_ERROR(1U) 7666 7667 #define S_IESPI0_TX_FRAMING_ERROR 13 7668 #define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR) 7669 #define F_IESPI0_TX_FRAMING_ERROR V_IESPI0_TX_FRAMING_ERROR(1U) 7670 7671 #define S_IESPI1_TX_FRAMING_ERROR 12 7672 #define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR) 7673 #define F_IESPI1_TX_FRAMING_ERROR V_IESPI1_TX_FRAMING_ERROR(1U) 7674 7675 #define S_IESPI2_TX_FRAMING_ERROR 11 7676 #define V_IESPI2_TX_FRAMING_ERROR(x) ((x) << S_IESPI2_TX_FRAMING_ERROR) 7677 #define F_IESPI2_TX_FRAMING_ERROR V_IESPI2_TX_FRAMING_ERROR(1U) 7678 7679 #define S_IESPI3_TX_FRAMING_ERROR 10 7680 #define V_IESPI3_TX_FRAMING_ERROR(x) ((x) << S_IESPI3_TX_FRAMING_ERROR) 7681 #define F_IESPI3_TX_FRAMING_ERROR V_IESPI3_TX_FRAMING_ERROR(1U) 7682 7683 #define S_OCSPI0_RX_FRAMING_ERROR 9 7684 #define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR) 7685 #define F_OCSPI0_RX_FRAMING_ERROR V_OCSPI0_RX_FRAMING_ERROR(1U) 7686 7687 #define S_OCSPI1_RX_FRAMING_ERROR 8 7688 #define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR) 7689 #define F_OCSPI1_RX_FRAMING_ERROR V_OCSPI1_RX_FRAMING_ERROR(1U) 7690 7691 #define S_OCSPI0_TX_FRAMING_ERROR 7 7692 #define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR) 7693 #define F_OCSPI0_TX_FRAMING_ERROR V_OCSPI0_TX_FRAMING_ERROR(1U) 7694 7695 #define S_OCSPI1_TX_FRAMING_ERROR 6 7696 #define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR) 7697 #define F_OCSPI1_TX_FRAMING_ERROR V_OCSPI1_TX_FRAMING_ERROR(1U) 7698 7699 #define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR 5 7700 #define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR) 7701 #define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U) 7702 7703 #define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR 4 7704 #define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR) 7705 #define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U) 7706 7707 #define S_OCSPI_PAR_ERROR 3 7708 #define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR) 7709 #define F_OCSPI_PAR_ERROR V_OCSPI_PAR_ERROR(1U) 7710 7711 #define S_DB_OPTIONS_PAR_ERROR 2 7712 #define V_DB_OPTIONS_PAR_ERROR(x) ((x) << S_DB_OPTIONS_PAR_ERROR) 7713 #define F_DB_OPTIONS_PAR_ERROR V_DB_OPTIONS_PAR_ERROR(1U) 7714 7715 #define S_IESPI_PAR_ERROR 1 7716 #define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR) 7717 #define F_IESPI_PAR_ERROR V_IESPI_PAR_ERROR(1U) 7718 7719 #define S_E_PCMD_PAR_ERROR 0 7720 #define V_E_PCMD_PAR_ERROR(x) ((x) << S_E_PCMD_PAR_ERROR) 7721 #define F_E_PCMD_PAR_ERROR V_E_PCMD_PAR_ERROR(1U) 7722 7723 #define S_OSPI_OVERFLOW1 28 7724 #define V_OSPI_OVERFLOW1(x) ((x) << S_OSPI_OVERFLOW1) 7725 #define F_OSPI_OVERFLOW1 V_OSPI_OVERFLOW1(1U) 7726 7727 #define S_OSPI_OVERFLOW0 27 7728 #define V_OSPI_OVERFLOW0(x) ((x) << S_OSPI_OVERFLOW0) 7729 #define F_OSPI_OVERFLOW0 V_OSPI_OVERFLOW0(1U) 7730 7731 #define S_MA_INTF_SDC_ERR 26 7732 #define V_MA_INTF_SDC_ERR(x) ((x) << S_MA_INTF_SDC_ERR) 7733 #define F_MA_INTF_SDC_ERR V_MA_INTF_SDC_ERR(1U) 7734 7735 #define S_BUNDLE_LEN_PARERR 25 7736 #define V_BUNDLE_LEN_PARERR(x) ((x) << S_BUNDLE_LEN_PARERR) 7737 #define F_BUNDLE_LEN_PARERR V_BUNDLE_LEN_PARERR(1U) 7738 7739 #define S_BUNDLE_LEN_OVFL 24 7740 #define V_BUNDLE_LEN_OVFL(x) ((x) << S_BUNDLE_LEN_OVFL) 7741 #define F_BUNDLE_LEN_OVFL V_BUNDLE_LEN_OVFL(1U) 7742 7743 #define S_SDC_ERR 23 7744 #define V_SDC_ERR(x) ((x) << S_SDC_ERR) 7745 #define F_SDC_ERR V_SDC_ERR(1U) 7746 7747 #define A_PM_RX_DBG_STAT_MSB 0x10013 7748 #define A_PM_RX_DBG_STAT_LSB 0x10014 7749 7750 /* registers for module PM_TX */ 7751 #define PM_TX_BASE_ADDR 0x8fe0 7752 7753 #define A_PM_TX_STAT_CONFIG 0x8fe8 7754 #define A_PM_TX_STAT_COUNT 0x8fec 7755 #define A_PM_TX_STAT_LSB 0x8ff0 7756 #define A_PM_TX_DBG_CTRL 0x8ff0 7757 7758 #define S_OSPIWRBUSY 21 7759 #define M_OSPIWRBUSY 0xfU 7760 #define V_OSPIWRBUSY(x) ((x) << S_OSPIWRBUSY) 7761 #define G_OSPIWRBUSY(x) (((x) >> S_OSPIWRBUSY) & M_OSPIWRBUSY) 7762 7763 #define A_PM_TX_STAT_MSB 0x8ff4 7764 #define A_PM_TX_DBG_DATA 0x8ff4 7765 #define A_PM_TX_INT_CAUSE 0x8ffc 7766 7767 #define S_PCMD_LEN_OVFL0 31 7768 #define V_PCMD_LEN_OVFL0(x) ((x) << S_PCMD_LEN_OVFL0) 7769 #define F_PCMD_LEN_OVFL0 V_PCMD_LEN_OVFL0(1U) 7770 7771 #define S_PCMD_LEN_OVFL1 30 7772 #define V_PCMD_LEN_OVFL1(x) ((x) << S_PCMD_LEN_OVFL1) 7773 #define F_PCMD_LEN_OVFL1 V_PCMD_LEN_OVFL1(1U) 7774 7775 #define S_PCMD_LEN_OVFL2 29 7776 #define V_PCMD_LEN_OVFL2(x) ((x) << S_PCMD_LEN_OVFL2) 7777 #define F_PCMD_LEN_OVFL2 V_PCMD_LEN_OVFL2(1U) 7778 7779 #define S_ZERO_C_CMD_ERROR 28 7780 #define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR) 7781 #define F_ZERO_C_CMD_ERROR V_ZERO_C_CMD_ERROR(1U) 7782 7783 #define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR 27 7784 #define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR) 7785 #define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U) 7786 7787 #define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR 26 7788 #define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR) 7789 #define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U) 7790 7791 #define S_ICSPI2_FIFO2X_RX_FRAMING_ERROR 25 7792 #define V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_FIFO2X_RX_FRAMING_ERROR) 7793 #define F_ICSPI2_FIFO2X_RX_FRAMING_ERROR V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(1U) 7794 7795 #define S_ICSPI3_FIFO2X_RX_FRAMING_ERROR 24 7796 #define V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_FIFO2X_RX_FRAMING_ERROR) 7797 #define F_ICSPI3_FIFO2X_RX_FRAMING_ERROR V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(1U) 7798 7799 #define S_ICSPI0_RX_FRAMING_ERROR 23 7800 #define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR) 7801 #define F_ICSPI0_RX_FRAMING_ERROR V_ICSPI0_RX_FRAMING_ERROR(1U) 7802 7803 #define S_ICSPI1_RX_FRAMING_ERROR 22 7804 #define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR) 7805 #define F_ICSPI1_RX_FRAMING_ERROR V_ICSPI1_RX_FRAMING_ERROR(1U) 7806 7807 #define S_ICSPI2_RX_FRAMING_ERROR 21 7808 #define V_ICSPI2_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_RX_FRAMING_ERROR) 7809 #define F_ICSPI2_RX_FRAMING_ERROR V_ICSPI2_RX_FRAMING_ERROR(1U) 7810 7811 #define S_ICSPI3_RX_FRAMING_ERROR 20 7812 #define V_ICSPI3_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_RX_FRAMING_ERROR) 7813 #define F_ICSPI3_RX_FRAMING_ERROR V_ICSPI3_RX_FRAMING_ERROR(1U) 7814 7815 #define S_ICSPI0_TX_FRAMING_ERROR 19 7816 #define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR) 7817 #define F_ICSPI0_TX_FRAMING_ERROR V_ICSPI0_TX_FRAMING_ERROR(1U) 7818 7819 #define S_ICSPI1_TX_FRAMING_ERROR 18 7820 #define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR) 7821 #define F_ICSPI1_TX_FRAMING_ERROR V_ICSPI1_TX_FRAMING_ERROR(1U) 7822 7823 #define S_ICSPI2_TX_FRAMING_ERROR 17 7824 #define V_ICSPI2_TX_FRAMING_ERROR(x) ((x) << S_ICSPI2_TX_FRAMING_ERROR) 7825 #define F_ICSPI2_TX_FRAMING_ERROR V_ICSPI2_TX_FRAMING_ERROR(1U) 7826 7827 #define S_ICSPI3_TX_FRAMING_ERROR 16 7828 #define V_ICSPI3_TX_FRAMING_ERROR(x) ((x) << S_ICSPI3_TX_FRAMING_ERROR) 7829 #define F_ICSPI3_TX_FRAMING_ERROR V_ICSPI3_TX_FRAMING_ERROR(1U) 7830 7831 #define S_OESPI0_RX_FRAMING_ERROR 15 7832 #define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR) 7833 #define F_OESPI0_RX_FRAMING_ERROR V_OESPI0_RX_FRAMING_ERROR(1U) 7834 7835 #define S_OESPI1_RX_FRAMING_ERROR 14 7836 #define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR) 7837 #define F_OESPI1_RX_FRAMING_ERROR V_OESPI1_RX_FRAMING_ERROR(1U) 7838 7839 #define S_OESPI2_RX_FRAMING_ERROR 13 7840 #define V_OESPI2_RX_FRAMING_ERROR(x) ((x) << S_OESPI2_RX_FRAMING_ERROR) 7841 #define F_OESPI2_RX_FRAMING_ERROR V_OESPI2_RX_FRAMING_ERROR(1U) 7842 7843 #define S_OESPI3_RX_FRAMING_ERROR 12 7844 #define V_OESPI3_RX_FRAMING_ERROR(x) ((x) << S_OESPI3_RX_FRAMING_ERROR) 7845 #define F_OESPI3_RX_FRAMING_ERROR V_OESPI3_RX_FRAMING_ERROR(1U) 7846 7847 #define S_OESPI0_TX_FRAMING_ERROR 11 7848 #define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR) 7849 #define F_OESPI0_TX_FRAMING_ERROR V_OESPI0_TX_FRAMING_ERROR(1U) 7850 7851 #define S_OESPI1_TX_FRAMING_ERROR 10 7852 #define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR) 7853 #define F_OESPI1_TX_FRAMING_ERROR V_OESPI1_TX_FRAMING_ERROR(1U) 7854 7855 #define S_OESPI2_TX_FRAMING_ERROR 9 7856 #define V_OESPI2_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_TX_FRAMING_ERROR) 7857 #define F_OESPI2_TX_FRAMING_ERROR V_OESPI2_TX_FRAMING_ERROR(1U) 7858 7859 #define S_OESPI3_TX_FRAMING_ERROR 8 7860 #define V_OESPI3_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_TX_FRAMING_ERROR) 7861 #define F_OESPI3_TX_FRAMING_ERROR V_OESPI3_TX_FRAMING_ERROR(1U) 7862 7863 #define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR 7 7864 #define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR) 7865 #define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U) 7866 7867 #define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR 6 7868 #define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR) 7869 #define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U) 7870 7871 #define S_OESPI2_OFIFO2X_TX_FRAMING_ERROR 5 7872 #define V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_OFIFO2X_TX_FRAMING_ERROR) 7873 #define F_OESPI2_OFIFO2X_TX_FRAMING_ERROR V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(1U) 7874 7875 #define S_OESPI3_OFIFO2X_TX_FRAMING_ERROR 4 7876 #define V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_OFIFO2X_TX_FRAMING_ERROR) 7877 #define F_OESPI3_OFIFO2X_TX_FRAMING_ERROR V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(1U) 7878 7879 #define S_OESPI_PAR_ERROR 3 7880 #define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR) 7881 #define F_OESPI_PAR_ERROR V_OESPI_PAR_ERROR(1U) 7882 7883 #define S_ICSPI_PAR_ERROR 1 7884 #define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR) 7885 #define F_ICSPI_PAR_ERROR V_ICSPI_PAR_ERROR(1U) 7886 7887 #define S_C_PCMD_PAR_ERROR 0 7888 #define V_C_PCMD_PAR_ERROR(x) ((x) << S_C_PCMD_PAR_ERROR) 7889 #define F_C_PCMD_PAR_ERROR V_C_PCMD_PAR_ERROR(1U) 7890 7891 #define S_OSPI_OR_BUNDLE_LEN_PAR_ERR 3 7892 #define V_OSPI_OR_BUNDLE_LEN_PAR_ERR(x) ((x) << S_OSPI_OR_BUNDLE_LEN_PAR_ERR) 7893 #define F_OSPI_OR_BUNDLE_LEN_PAR_ERR V_OSPI_OR_BUNDLE_LEN_PAR_ERR(1U) 7894 7895 #define A_PM_TX_DBG_STAT_MSB 0x1001a 7896 #define A_PM_TX_DBG_STAT_LSB 0x1001b 7897 7898 /* registers for module MPS */ 7899 #define MPS_BASE_ADDR 0x9000 7900 7901 #define A_MPS_VF_CTL 0x0 7902 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L 0x80 7903 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_H 0x84 7904 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_L 0x88 7905 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_H 0x8c 7906 #define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_L 0x90 7907 #define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_H 0x94 7908 #define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_L 0x98 7909 #define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_H 0x9c 7910 #define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_L 0xa0 7911 #define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_H 0xa4 7912 #define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_L 0xa8 7913 #define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_H 0xac 7914 #define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_L 0xb0 7915 #define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_H 0xb4 7916 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_L 0xb8 7917 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_H 0xbc 7918 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_L 0xc0 7919 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_H 0xc4 7920 #define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_L 0xc8 7921 #define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_H 0xcc 7922 #define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_L 0xd0 7923 #define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_H 0xd4 7924 #define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_L 0xd8 7925 #define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_H 0xdc 7926 #define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_L 0xe0 7927 #define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_H 0xe4 7928 #define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_L 0xe8 7929 #define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_H 0xec 7930 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_L 0xf0 7931 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_H 0xf4 7932 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_L 0xf8 7933 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H 0xfc 7934 #define A_MPS_PORT_CLS_HASH_SRAM 0x200 7935 7936 #define S_VALID 20 7937 #define V_VALID(x) ((x) << S_VALID) 7938 #define F_VALID V_VALID(1U) 7939 7940 #define S_HASHPORTMAP 16 7941 #define M_HASHPORTMAP 0xfU 7942 #define V_HASHPORTMAP(x) ((x) << S_HASHPORTMAP) 7943 #define G_HASHPORTMAP(x) (((x) >> S_HASHPORTMAP) & M_HASHPORTMAP) 7944 7945 #define S_MULTILISTEN 15 7946 #define V_MULTILISTEN(x) ((x) << S_MULTILISTEN) 7947 #define F_MULTILISTEN V_MULTILISTEN(1U) 7948 7949 #define S_PRIORITY 12 7950 #define M_PRIORITY 0x7U 7951 #define V_PRIORITY(x) ((x) << S_PRIORITY) 7952 #define G_PRIORITY(x) (((x) >> S_PRIORITY) & M_PRIORITY) 7953 7954 #define S_REPLICATE 11 7955 #define V_REPLICATE(x) ((x) << S_REPLICATE) 7956 #define F_REPLICATE V_REPLICATE(1U) 7957 7958 #define S_PF 8 7959 #define M_PF 0x7U 7960 #define V_PF(x) ((x) << S_PF) 7961 #define G_PF(x) (((x) >> S_PF) & M_PF) 7962 7963 #define S_VF_VALID 7 7964 #define V_VF_VALID(x) ((x) << S_VF_VALID) 7965 #define F_VF_VALID V_VF_VALID(1U) 7966 7967 #define S_VF 0 7968 #define M_VF 0x7fU 7969 #define V_VF(x) ((x) << S_VF) 7970 #define G_VF(x) (((x) >> S_VF) & M_VF) 7971 7972 #define S_DISENCAPOUTERRPLCT 23 7973 #define V_DISENCAPOUTERRPLCT(x) ((x) << S_DISENCAPOUTERRPLCT) 7974 #define F_DISENCAPOUTERRPLCT V_DISENCAPOUTERRPLCT(1U) 7975 7976 #define S_DISENCAP 22 7977 #define V_DISENCAP(x) ((x) << S_DISENCAP) 7978 #define F_DISENCAP V_DISENCAP(1U) 7979 7980 #define S_T6_VALID 21 7981 #define V_T6_VALID(x) ((x) << S_T6_VALID) 7982 #define F_T6_VALID V_T6_VALID(1U) 7983 7984 #define S_T6_HASHPORTMAP 17 7985 #define M_T6_HASHPORTMAP 0xfU 7986 #define V_T6_HASHPORTMAP(x) ((x) << S_T6_HASHPORTMAP) 7987 #define G_T6_HASHPORTMAP(x) (((x) >> S_T6_HASHPORTMAP) & M_T6_HASHPORTMAP) 7988 7989 #define S_T6_MULTILISTEN 16 7990 #define V_T6_MULTILISTEN(x) ((x) << S_T6_MULTILISTEN) 7991 #define F_T6_MULTILISTEN V_T6_MULTILISTEN(1U) 7992 7993 #define S_T6_PRIORITY 13 7994 #define M_T6_PRIORITY 0x7U 7995 #define V_T6_PRIORITY(x) ((x) << S_T6_PRIORITY) 7996 #define G_T6_PRIORITY(x) (((x) >> S_T6_PRIORITY) & M_T6_PRIORITY) 7997 7998 #define S_T6_REPLICATE 12 7999 #define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE) 8000 #define F_T6_REPLICATE V_T6_REPLICATE(1U) 8001 8002 #define S_T6_PF 9 8003 #define M_T6_PF 0x7U 8004 #define V_T6_PF(x) ((x) << S_T6_PF) 8005 #define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF) 8006 8007 #define S_T6_VF_VALID 8 8008 #define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID) 8009 #define F_T6_VF_VALID V_T6_VF_VALID(1U) 8010 8011 #define S_T6_VF 0 8012 #define M_T6_VF 0xffU 8013 #define V_T6_VF(x) ((x) << S_T6_VF) 8014 #define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF) 8015 8016 #define A_MPS_PF_CTL 0x2c0 8017 8018 #define S_TXEN 1 8019 #define V_TXEN(x) ((x) << S_TXEN) 8020 #define F_TXEN V_TXEN(1U) 8021 8022 #define S_RXEN 0 8023 #define V_RXEN(x) ((x) << S_RXEN) 8024 #define F_RXEN V_RXEN(1U) 8025 8026 #define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400 8027 #define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404 8028 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408 8029 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c 8030 #define A_MPS_PORT_STAT_TX_PORT_BCAST_L 0x410 8031 #define A_MPS_PORT_STAT_TX_PORT_BCAST_H 0x414 8032 #define A_MPS_PORT_STAT_TX_PORT_MCAST_L 0x418 8033 #define A_MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c 8034 #define A_MPS_PORT_STAT_TX_PORT_UCAST_L 0x420 8035 #define A_MPS_PORT_STAT_TX_PORT_UCAST_H 0x424 8036 #define A_MPS_PORT_STAT_TX_PORT_ERROR_L 0x428 8037 #define A_MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c 8038 #define A_MPS_PORT_STAT_TX_PORT_64B_L 0x430 8039 #define A_MPS_PORT_STAT_TX_PORT_64B_H 0x434 8040 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438 8041 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c 8042 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440 8043 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444 8044 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448 8045 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c 8046 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450 8047 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454 8048 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458 8049 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c 8050 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460 8051 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464 8052 #define A_MPS_PORT_STAT_TX_PORT_DROP_L 0x468 8053 #define A_MPS_PORT_STAT_TX_PORT_DROP_H 0x46c 8054 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470 8055 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474 8056 #define A_MPS_PORT_STAT_TX_PORT_PPP0_L 0x478 8057 #define A_MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c 8058 #define A_MPS_PORT_STAT_TX_PORT_PPP1_L 0x480 8059 #define A_MPS_PORT_STAT_TX_PORT_PPP1_H 0x484 8060 #define A_MPS_PORT_STAT_TX_PORT_PPP2_L 0x488 8061 #define A_MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c 8062 #define A_MPS_PORT_STAT_TX_PORT_PPP3_L 0x490 8063 #define A_MPS_PORT_STAT_TX_PORT_PPP3_H 0x494 8064 #define A_MPS_PORT_STAT_TX_PORT_PPP4_L 0x498 8065 #define A_MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c 8066 #define A_MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0 8067 #define A_MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4 8068 #define A_MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8 8069 #define A_MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac 8070 #define A_MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0 8071 #define A_MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4 8072 #define A_MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0 8073 #define A_MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4 8074 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8 8075 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc 8076 #define A_MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0 8077 #define A_MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4 8078 #define A_MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8 8079 #define A_MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc 8080 #define A_MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0 8081 #define A_MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4 8082 #define A_MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8 8083 #define A_MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec 8084 #define A_MPS_PORT_STAT_LB_PORT_64B_L 0x4f0 8085 #define A_MPS_PORT_STAT_LB_PORT_64B_H 0x4f4 8086 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8 8087 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc 8088 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500 8089 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504 8090 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508 8091 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c 8092 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510 8093 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514 8094 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518 8095 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c 8096 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520 8097 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524 8098 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528 8099 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528 8100 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c 8101 #define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540 8102 #define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544 8103 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548 8104 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c 8105 #define A_MPS_PORT_STAT_RX_PORT_BCAST_L 0x550 8106 #define A_MPS_PORT_STAT_RX_PORT_BCAST_H 0x554 8107 #define A_MPS_PORT_STAT_RX_PORT_MCAST_L 0x558 8108 #define A_MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c 8109 #define A_MPS_PORT_STAT_RX_PORT_UCAST_L 0x560 8110 #define A_MPS_PORT_STAT_RX_PORT_UCAST_H 0x564 8111 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568 8112 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c 8113 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570 8114 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574 8115 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578 8116 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c 8117 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580 8118 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584 8119 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588 8120 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c 8121 #define A_MPS_PORT_STAT_RX_PORT_64B_L 0x590 8122 #define A_MPS_PORT_STAT_RX_PORT_64B_H 0x594 8123 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598 8124 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c 8125 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0 8126 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4 8127 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8 8128 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac 8129 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0 8130 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4 8131 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8 8132 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc 8133 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0 8134 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4 8135 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8 8136 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc 8137 #define A_MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0 8138 #define A_MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4 8139 #define A_MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8 8140 #define A_MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc 8141 #define A_MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0 8142 #define A_MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4 8143 #define A_MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8 8144 #define A_MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec 8145 #define A_MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0 8146 #define A_MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4 8147 #define A_MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8 8148 #define A_MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc 8149 #define A_MPS_PORT_STAT_RX_PORT_PPP6_L 0x600 8150 #define A_MPS_PORT_STAT_RX_PORT_PPP6_H 0x604 8151 #define A_MPS_PORT_STAT_RX_PORT_PPP7_L 0x608 8152 #define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c 8153 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 8154 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 8155 #define A_MPS_CMN_CTL 0x9000 8156 8157 #define S_DETECT8023 3 8158 #define V_DETECT8023(x) ((x) << S_DETECT8023) 8159 #define F_DETECT8023 V_DETECT8023(1U) 8160 8161 #define S_VFDIRECTACCESS 2 8162 #define V_VFDIRECTACCESS(x) ((x) << S_VFDIRECTACCESS) 8163 #define F_VFDIRECTACCESS V_VFDIRECTACCESS(1U) 8164 8165 #define S_NUMPORTS 0 8166 #define M_NUMPORTS 0x3U 8167 #define V_NUMPORTS(x) ((x) << S_NUMPORTS) 8168 #define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS) 8169 8170 #define S_LPBKCRDTCTRL 4 8171 #define V_LPBKCRDTCTRL(x) ((x) << S_LPBKCRDTCTRL) 8172 #define F_LPBKCRDTCTRL V_LPBKCRDTCTRL(1U) 8173 8174 #define A_MPS_INT_CAUSE 0x9008 8175 8176 #define S_STATINT 5 8177 #define V_STATINT(x) ((x) << S_STATINT) 8178 #define F_STATINT V_STATINT(1U) 8179 8180 #define S_TXINT 4 8181 #define V_TXINT(x) ((x) << S_TXINT) 8182 #define F_TXINT V_TXINT(1U) 8183 8184 #define S_RXINT 3 8185 #define V_RXINT(x) ((x) << S_RXINT) 8186 #define F_RXINT V_RXINT(1U) 8187 8188 #define S_TRCINT 2 8189 #define V_TRCINT(x) ((x) << S_TRCINT) 8190 #define F_TRCINT V_TRCINT(1U) 8191 8192 #define S_CLSINT 1 8193 #define V_CLSINT(x) ((x) << S_CLSINT) 8194 #define F_CLSINT V_CLSINT(1U) 8195 8196 #define S_PLINT 0 8197 #define V_PLINT(x) ((x) << S_PLINT) 8198 #define F_PLINT V_PLINT(1U) 8199 8200 #define A_MPS_TX_INT_CAUSE 0x9408 8201 8202 #define S_PORTERR 16 8203 #define V_PORTERR(x) ((x) << S_PORTERR) 8204 #define F_PORTERR V_PORTERR(1U) 8205 8206 #define S_FRMERR 15 8207 #define V_FRMERR(x) ((x) << S_FRMERR) 8208 #define F_FRMERR V_FRMERR(1U) 8209 8210 #define S_SECNTERR 14 8211 #define V_SECNTERR(x) ((x) << S_SECNTERR) 8212 #define F_SECNTERR V_SECNTERR(1U) 8213 8214 #define S_BUBBLE 13 8215 #define V_BUBBLE(x) ((x) << S_BUBBLE) 8216 #define F_BUBBLE V_BUBBLE(1U) 8217 8218 #define S_TXDESCFIFO 9 8219 #define M_TXDESCFIFO 0xfU 8220 #define V_TXDESCFIFO(x) ((x) << S_TXDESCFIFO) 8221 #define G_TXDESCFIFO(x) (((x) >> S_TXDESCFIFO) & M_TXDESCFIFO) 8222 8223 #define S_TXDATAFIFO 5 8224 #define M_TXDATAFIFO 0xfU 8225 #define V_TXDATAFIFO(x) ((x) << S_TXDATAFIFO) 8226 #define G_TXDATAFIFO(x) (((x) >> S_TXDATAFIFO) & M_TXDATAFIFO) 8227 8228 #define S_NCSIFIFO 4 8229 #define V_NCSIFIFO(x) ((x) << S_NCSIFIFO) 8230 #define F_NCSIFIFO V_NCSIFIFO(1U) 8231 8232 #define S_TPFIFO 0 8233 #define M_TPFIFO 0xfU 8234 #define V_TPFIFO(x) ((x) << S_TPFIFO) 8235 #define G_TPFIFO(x) (((x) >> S_TPFIFO) & M_TPFIFO) 8236 8237 #define A_MPS_TX_SE_CNT_TP01 0x9418 8238 #define A_MPS_TX_SE_CNT_TP23 0x941c 8239 #define A_MPS_TX_SE_CNT_MAC01 0x9420 8240 #define A_MPS_TX_SE_CNT_MAC23 0x9424 8241 #define A_MPS_STAT_CTL 0x9600 8242 8243 #define S_COUNTPAUSESTATRX 4 8244 #define V_COUNTPAUSESTATRX(x) ((x) << S_COUNTPAUSESTATRX) 8245 #define F_COUNTPAUSESTATRX V_COUNTPAUSESTATRX(1U) 8246 8247 #define S_COUNTPAUSESTATTX 2 8248 #define V_COUNTPAUSESTATTX(x) ((x) << S_COUNTPAUSESTATTX) 8249 #define F_COUNTPAUSESTATTX V_COUNTPAUSESTATTX(1U) 8250 8251 #define S_STATSTOPCTRL 10 8252 #define V_STATSTOPCTRL(x) ((x) << S_STATSTOPCTRL) 8253 #define F_STATSTOPCTRL V_STATSTOPCTRL(1U) 8254 8255 #define S_STOPSTAT 9 8256 #define V_STOPSTAT(x) ((x) << S_STOPSTAT) 8257 #define F_STOPSTAT V_STOPSTAT(1U) 8258 8259 #define S_STATWRITECTRL 8 8260 #define V_STATWRITECTRL(x) ((x) << S_STATWRITECTRL) 8261 #define F_STATWRITECTRL V_STATWRITECTRL(1U) 8262 8263 #define S_COUNTLBPF 7 8264 #define V_COUNTLBPF(x) ((x) << S_COUNTLBPF) 8265 #define F_COUNTLBPF V_COUNTLBPF(1U) 8266 8267 #define S_COUNTLBVF 6 8268 #define V_COUNTLBVF(x) ((x) << S_COUNTLBVF) 8269 #define F_COUNTLBVF V_COUNTLBVF(1U) 8270 8271 #define S_COUNTPAUSEMCRX 5 8272 #define V_COUNTPAUSEMCRX(x) ((x) << S_COUNTPAUSEMCRX) 8273 #define F_COUNTPAUSEMCRX V_COUNTPAUSEMCRX(1U) 8274 8275 #define S_COUNTPAUSEMCTX 3 8276 #define V_COUNTPAUSEMCTX(x) ((x) << S_COUNTPAUSEMCTX) 8277 #define F_COUNTPAUSEMCTX V_COUNTPAUSEMCTX(1U) 8278 8279 #define A_MPS_STAT_INT_CAUSE 0x960c 8280 8281 #define S_PLREADSYNCERR 0 8282 #define V_PLREADSYNCERR(x) ((x) << S_PLREADSYNCERR) 8283 #define F_PLREADSYNCERR V_PLREADSYNCERR(1U) 8284 8285 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614 8286 8287 #define S_RXBG 20 8288 #define V_RXBG(x) ((x) << S_RXBG) 8289 #define F_RXBG V_RXBG(1U) 8290 8291 #define S_RXVF 18 8292 #define M_RXVF 0x3U 8293 #define V_RXVF(x) ((x) << S_RXVF) 8294 #define G_RXVF(x) (((x) >> S_RXVF) & M_RXVF) 8295 8296 #define S_TXVF 16 8297 #define M_TXVF 0x3U 8298 #define V_TXVF(x) ((x) << S_TXVF) 8299 #define G_TXVF(x) (((x) >> S_TXVF) & M_TXVF) 8300 8301 #define S_RXPF 13 8302 #define M_RXPF 0x7U 8303 #define V_RXPF(x) ((x) << S_RXPF) 8304 #define G_RXPF(x) (((x) >> S_RXPF) & M_RXPF) 8305 8306 #define S_TXPF 11 8307 #define M_TXPF 0x3U 8308 #define V_TXPF(x) ((x) << S_TXPF) 8309 #define G_TXPF(x) (((x) >> S_TXPF) & M_TXPF) 8310 8311 #define S_RXPORT 7 8312 #define M_RXPORT 0xfU 8313 #define V_RXPORT(x) ((x) << S_RXPORT) 8314 #define G_RXPORT(x) (((x) >> S_RXPORT) & M_RXPORT) 8315 8316 #define S_LBPORT 4 8317 #define M_LBPORT 0x7U 8318 #define V_LBPORT(x) ((x) << S_LBPORT) 8319 #define G_LBPORT(x) (((x) >> S_LBPORT) & M_LBPORT) 8320 8321 #define S_TXPORT 0 8322 #define M_TXPORT 0xfU 8323 #define V_TXPORT(x) ((x) << S_TXPORT) 8324 #define G_TXPORT(x) (((x) >> S_TXPORT) & M_TXPORT) 8325 8326 #define S_T5_RXBG 27 8327 #define M_T5_RXBG 0x3U 8328 #define V_T5_RXBG(x) ((x) << S_T5_RXBG) 8329 #define G_T5_RXBG(x) (((x) >> S_T5_RXBG) & M_T5_RXBG) 8330 8331 #define S_T5_RXPF 22 8332 #define M_T5_RXPF 0x1fU 8333 #define V_T5_RXPF(x) ((x) << S_T5_RXPF) 8334 #define G_T5_RXPF(x) (((x) >> S_T5_RXPF) & M_T5_RXPF) 8335 8336 #define S_T5_TXPF 18 8337 #define M_T5_TXPF 0xfU 8338 #define V_T5_TXPF(x) ((x) << S_T5_TXPF) 8339 #define G_T5_TXPF(x) (((x) >> S_T5_TXPF) & M_T5_TXPF) 8340 8341 #define S_T5_RXPORT 11 8342 #define M_T5_RXPORT 0x7fU 8343 #define V_T5_RXPORT(x) ((x) << S_T5_RXPORT) 8344 #define G_T5_RXPORT(x) (((x) >> S_T5_RXPORT) & M_T5_RXPORT) 8345 8346 #define S_T5_LBPORT 6 8347 #define M_T5_LBPORT 0x1fU 8348 #define V_T5_LBPORT(x) ((x) << S_T5_LBPORT) 8349 #define G_T5_LBPORT(x) (((x) >> S_T5_LBPORT) & M_T5_LBPORT) 8350 8351 #define S_T5_TXPORT 0 8352 #define M_T5_TXPORT 0x3fU 8353 #define V_T5_TXPORT(x) ((x) << S_T5_TXPORT) 8354 #define G_T5_TXPORT(x) (((x) >> S_T5_TXPORT) & M_T5_TXPORT) 8355 8356 #define A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620 8357 8358 #define S_TX 12 8359 #define M_TX 0xffU 8360 #define V_TX(x) ((x) << S_TX) 8361 #define G_TX(x) (((x) >> S_TX) & M_TX) 8362 8363 #define S_TXPAUSEFIFO 8 8364 #define M_TXPAUSEFIFO 0xfU 8365 #define V_TXPAUSEFIFO(x) ((x) << S_TXPAUSEFIFO) 8366 #define G_TXPAUSEFIFO(x) (((x) >> S_TXPAUSEFIFO) & M_TXPAUSEFIFO) 8367 8368 #define S_DROP 0 8369 #define M_DROP 0xffU 8370 #define V_DROP(x) ((x) << S_DROP) 8371 #define G_DROP(x) (((x) >> S_DROP) & M_DROP) 8372 8373 #define S_TXCH 20 8374 #define M_TXCH 0xfU 8375 #define V_TXCH(x) ((x) << S_TXCH) 8376 #define G_TXCH(x) (((x) >> S_TXCH) & M_TXCH) 8377 8378 #define A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c 8379 8380 #define S_PAUSEFIFO 20 8381 #define M_PAUSEFIFO 0xfU 8382 #define V_PAUSEFIFO(x) ((x) << S_PAUSEFIFO) 8383 #define G_PAUSEFIFO(x) (((x) >> S_PAUSEFIFO) & M_PAUSEFIFO) 8384 8385 #define S_LPBK 16 8386 #define M_LPBK 0xfU 8387 #define V_LPBK(x) ((x) << S_LPBK) 8388 #define G_LPBK(x) (((x) >> S_LPBK) & M_LPBK) 8389 8390 #define S_NQ 8 8391 #define M_NQ 0xffU 8392 #define V_NQ(x) ((x) << S_NQ) 8393 #define G_NQ(x) (((x) >> S_NQ) & M_NQ) 8394 8395 #define S_PV 4 8396 #define M_PV 0xfU 8397 #define V_PV(x) ((x) << S_PV) 8398 #define G_PV(x) (((x) >> S_PV) & M_PV) 8399 8400 #define S_MAC 0 8401 #define M_MAC 0xfU 8402 #define V_MAC(x) ((x) << S_MAC) 8403 #define G_MAC(x) (((x) >> S_MAC) & M_MAC) 8404 8405 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640 8406 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644 8407 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648 8408 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c 8409 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650 8410 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654 8411 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658 8412 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c 8413 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660 8414 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664 8415 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668 8416 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c 8417 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670 8418 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674 8419 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678 8420 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c 8421 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680 8422 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684 8423 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688 8424 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c 8425 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690 8426 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694 8427 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698 8428 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c 8429 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0 8430 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4 8431 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8 8432 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac 8433 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0 8434 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4 8435 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8 8436 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc 8437 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM1 0x96c4 8438 8439 #define S_T5_RXVF 5 8440 #define M_T5_RXVF 0x7U 8441 #define V_T5_RXVF(x) ((x) << S_T5_RXVF) 8442 #define G_T5_RXVF(x) (((x) >> S_T5_RXVF) & M_T5_RXVF) 8443 8444 #define S_T5_TXVF 0 8445 #define M_T5_TXVF 0x1fU 8446 #define V_T5_TXVF(x) ((x) << S_T5_TXVF) 8447 #define G_T5_TXVF(x) (((x) >> S_T5_TXVF) & M_T5_TXVF) 8448 8449 #define A_MPS_TRC_CFG 0x9800 8450 8451 #define S_TRCFIFOEMPTY 4 8452 #define V_TRCFIFOEMPTY(x) ((x) << S_TRCFIFOEMPTY) 8453 #define F_TRCFIFOEMPTY V_TRCFIFOEMPTY(1U) 8454 8455 #define S_TRCIGNOREDROPINPUT 3 8456 #define V_TRCIGNOREDROPINPUT(x) ((x) << S_TRCIGNOREDROPINPUT) 8457 #define F_TRCIGNOREDROPINPUT V_TRCIGNOREDROPINPUT(1U) 8458 8459 #define S_TRCKEEPDUPLICATES 2 8460 #define V_TRCKEEPDUPLICATES(x) ((x) << S_TRCKEEPDUPLICATES) 8461 #define F_TRCKEEPDUPLICATES V_TRCKEEPDUPLICATES(1U) 8462 8463 #define S_TRCEN 1 8464 #define V_TRCEN(x) ((x) << S_TRCEN) 8465 #define F_TRCEN V_TRCEN(1U) 8466 8467 #define S_TRCMULTIFILTER 0 8468 #define V_TRCMULTIFILTER(x) ((x) << S_TRCMULTIFILTER) 8469 #define F_TRCMULTIFILTER V_TRCMULTIFILTER(1U) 8470 8471 #define S_TRCMULTIRSSFILTER 5 8472 #define V_TRCMULTIRSSFILTER(x) ((x) << S_TRCMULTIRSSFILTER) 8473 #define F_TRCMULTIRSSFILTER V_TRCMULTIRSSFILTER(1U) 8474 8475 #define A_MPS_TRC_RSS_CONTROL 0x9808 8476 8477 #define S_RSSCONTROL 16 8478 #define M_RSSCONTROL 0xffU 8479 #define V_RSSCONTROL(x) ((x) << S_RSSCONTROL) 8480 #define G_RSSCONTROL(x) (((x) >> S_RSSCONTROL) & M_RSSCONTROL) 8481 8482 #define S_QUEUENUMBER 0 8483 #define M_QUEUENUMBER 0xffffU 8484 #define V_QUEUENUMBER(x) ((x) << S_QUEUENUMBER) 8485 #define G_QUEUENUMBER(x) (((x) >> S_QUEUENUMBER) & M_QUEUENUMBER) 8486 8487 #define A_MPS_TRC_FILTER_MATCH_CTL_A 0x9810 8488 8489 #define S_TFINVERTMATCH 24 8490 #define V_TFINVERTMATCH(x) ((x) << S_TFINVERTMATCH) 8491 #define F_TFINVERTMATCH V_TFINVERTMATCH(1U) 8492 8493 #define S_TFPKTTOOLARGE 23 8494 #define V_TFPKTTOOLARGE(x) ((x) << S_TFPKTTOOLARGE) 8495 #define F_TFPKTTOOLARGE V_TFPKTTOOLARGE(1U) 8496 8497 #define S_TFEN 22 8498 #define V_TFEN(x) ((x) << S_TFEN) 8499 #define F_TFEN V_TFEN(1U) 8500 8501 #define S_TFPORT 18 8502 #define M_TFPORT 0xfU 8503 #define V_TFPORT(x) ((x) << S_TFPORT) 8504 #define G_TFPORT(x) (((x) >> S_TFPORT) & M_TFPORT) 8505 8506 #define S_TFDROP 17 8507 #define V_TFDROP(x) ((x) << S_TFDROP) 8508 #define F_TFDROP V_TFDROP(1U) 8509 8510 #define S_TFSOPEOPERR 16 8511 #define V_TFSOPEOPERR(x) ((x) << S_TFSOPEOPERR) 8512 #define F_TFSOPEOPERR V_TFSOPEOPERR(1U) 8513 8514 #define S_TFLENGTH 8 8515 #define M_TFLENGTH 0x1fU 8516 #define V_TFLENGTH(x) ((x) << S_TFLENGTH) 8517 #define G_TFLENGTH(x) (((x) >> S_TFLENGTH) & M_TFLENGTH) 8518 8519 #define S_TFOFFSET 0 8520 #define M_TFOFFSET 0x1fU 8521 #define V_TFOFFSET(x) ((x) << S_TFOFFSET) 8522 #define G_TFOFFSET(x) (((x) >> S_TFOFFSET) & M_TFOFFSET) 8523 8524 #define S_TFINSERTACTLEN 27 8525 #define V_TFINSERTACTLEN(x) ((x) << S_TFINSERTACTLEN) 8526 #define F_TFINSERTACTLEN V_TFINSERTACTLEN(1U) 8527 8528 #define S_TFINSERTTIMER 26 8529 #define V_TFINSERTTIMER(x) ((x) << S_TFINSERTTIMER) 8530 #define F_TFINSERTTIMER V_TFINSERTTIMER(1U) 8531 8532 #define S_T5_TFINVERTMATCH 25 8533 #define V_T5_TFINVERTMATCH(x) ((x) << S_T5_TFINVERTMATCH) 8534 #define F_T5_TFINVERTMATCH V_T5_TFINVERTMATCH(1U) 8535 8536 #define S_T5_TFPKTTOOLARGE 24 8537 #define V_T5_TFPKTTOOLARGE(x) ((x) << S_T5_TFPKTTOOLARGE) 8538 #define F_T5_TFPKTTOOLARGE V_T5_TFPKTTOOLARGE(1U) 8539 8540 #define S_T5_TFEN 23 8541 #define V_T5_TFEN(x) ((x) << S_T5_TFEN) 8542 #define F_T5_TFEN V_T5_TFEN(1U) 8543 8544 #define S_T5_TFPORT 18 8545 #define M_T5_TFPORT 0x1fU 8546 #define V_T5_TFPORT(x) ((x) << S_T5_TFPORT) 8547 #define G_T5_TFPORT(x) (((x) >> S_T5_TFPORT) & M_T5_TFPORT) 8548 8549 #define A_MPS_TRC_FILTER_MATCH_CTL_B 0x9820 8550 8551 #define S_TFMINPKTSIZE 16 8552 #define M_TFMINPKTSIZE 0x1ffU 8553 #define V_TFMINPKTSIZE(x) ((x) << S_TFMINPKTSIZE) 8554 #define G_TFMINPKTSIZE(x) (((x) >> S_TFMINPKTSIZE) & M_TFMINPKTSIZE) 8555 8556 #define S_TFCAPTUREMAX 0 8557 #define M_TFCAPTUREMAX 0x3fffU 8558 #define V_TFCAPTUREMAX(x) ((x) << S_TFCAPTUREMAX) 8559 #define G_TFCAPTUREMAX(x) (((x) >> S_TFCAPTUREMAX) & M_TFCAPTUREMAX) 8560 8561 #define A_MPS_TRC_INT_CAUSE 0x985c 8562 8563 #define S_TRCPLERRENB 9 8564 #define V_TRCPLERRENB(x) ((x) << S_TRCPLERRENB) 8565 #define F_TRCPLERRENB V_TRCPLERRENB(1U) 8566 8567 #define S_MISCPERR 8 8568 #define V_MISCPERR(x) ((x) << S_MISCPERR) 8569 #define F_MISCPERR V_MISCPERR(1U) 8570 8571 #define S_PKTFIFO 4 8572 #define M_PKTFIFO 0xfU 8573 #define V_PKTFIFO(x) ((x) << S_PKTFIFO) 8574 #define G_PKTFIFO(x) (((x) >> S_PKTFIFO) & M_PKTFIFO) 8575 8576 #define S_FILTMEM 0 8577 #define M_FILTMEM 0xfU 8578 #define V_FILTMEM(x) ((x) << S_FILTMEM) 8579 #define G_FILTMEM(x) (((x) >> S_FILTMEM) & M_FILTMEM) 8580 8581 #define A_MPS_TRC_FILTER0_MATCH 0x9c00 8582 #define A_MPS_TRC_FILTER0_DONT_CARE 0x9c80 8583 #define A_MPS_TRC_FILTER1_MATCH 0x9d00 8584 #define A_MPS_T5_TRC_RSS_CONTROL 0xa00c 8585 #define A_MPS_CLS_PERR_ENABLE 0xd020 8586 8587 #define S_HASHSRAM 2 8588 #define V_HASHSRAM(x) ((x) << S_HASHSRAM) 8589 #define F_HASHSRAM V_HASHSRAM(1U) 8590 8591 #define S_MATCHTCAM 1 8592 #define V_MATCHTCAM(x) ((x) << S_MATCHTCAM) 8593 #define F_MATCHTCAM V_MATCHTCAM(1U) 8594 8595 #define S_MATCHSRAM 0 8596 #define V_MATCHSRAM(x) ((x) << S_MATCHSRAM) 8597 #define F_MATCHSRAM V_MATCHSRAM(1U) 8598 8599 #define A_MPS_CLS_INT_ENABLE 0xd024 8600 8601 #define S_PLERRENB 3 8602 #define V_PLERRENB(x) ((x) << S_PLERRENB) 8603 #define F_PLERRENB V_PLERRENB(1U) 8604 8605 #define A_MPS_CLS_INT_CAUSE 0xd028 8606 #define A_MPS_CLS_SRAM_L 0xe000 8607 8608 #define S_MULTILISTEN3 28 8609 #define V_MULTILISTEN3(x) ((x) << S_MULTILISTEN3) 8610 #define F_MULTILISTEN3 V_MULTILISTEN3(1U) 8611 8612 #define S_MULTILISTEN2 27 8613 #define V_MULTILISTEN2(x) ((x) << S_MULTILISTEN2) 8614 #define F_MULTILISTEN2 V_MULTILISTEN2(1U) 8615 8616 #define S_MULTILISTEN1 26 8617 #define V_MULTILISTEN1(x) ((x) << S_MULTILISTEN1) 8618 #define F_MULTILISTEN1 V_MULTILISTEN1(1U) 8619 8620 #define S_MULTILISTEN0 25 8621 #define V_MULTILISTEN0(x) ((x) << S_MULTILISTEN0) 8622 #define F_MULTILISTEN0 V_MULTILISTEN0(1U) 8623 8624 #define S_SRAM_PRIO3 22 8625 #define M_SRAM_PRIO3 0x7U 8626 #define V_SRAM_PRIO3(x) ((x) << S_SRAM_PRIO3) 8627 #define G_SRAM_PRIO3(x) (((x) >> S_SRAM_PRIO3) & M_SRAM_PRIO3) 8628 8629 #define S_SRAM_PRIO2 19 8630 #define M_SRAM_PRIO2 0x7U 8631 #define V_SRAM_PRIO2(x) ((x) << S_SRAM_PRIO2) 8632 #define G_SRAM_PRIO2(x) (((x) >> S_SRAM_PRIO2) & M_SRAM_PRIO2) 8633 8634 #define S_SRAM_PRIO1 16 8635 #define M_SRAM_PRIO1 0x7U 8636 #define V_SRAM_PRIO1(x) ((x) << S_SRAM_PRIO1) 8637 #define G_SRAM_PRIO1(x) (((x) >> S_SRAM_PRIO1) & M_SRAM_PRIO1) 8638 8639 #define S_SRAM_PRIO0 13 8640 #define M_SRAM_PRIO0 0x7U 8641 #define V_SRAM_PRIO0(x) ((x) << S_SRAM_PRIO0) 8642 #define G_SRAM_PRIO0(x) (((x) >> S_SRAM_PRIO0) & M_SRAM_PRIO0) 8643 8644 #define S_SRAM_VLD 12 8645 #define V_SRAM_VLD(x) ((x) << S_SRAM_VLD) 8646 #define F_SRAM_VLD V_SRAM_VLD(1U) 8647 8648 #define A_MPS_T5_CLS_SRAM_L 0xe000 8649 8650 #define S_T6_DISENCAPOUTERRPLCT 31 8651 #define V_T6_DISENCAPOUTERRPLCT(x) ((x) << S_T6_DISENCAPOUTERRPLCT) 8652 #define F_T6_DISENCAPOUTERRPLCT V_T6_DISENCAPOUTERRPLCT(1U) 8653 8654 #define S_T6_DISENCAP 30 8655 #define V_T6_DISENCAP(x) ((x) << S_T6_DISENCAP) 8656 #define F_T6_DISENCAP V_T6_DISENCAP(1U) 8657 8658 #define S_T6_MULTILISTEN3 29 8659 #define V_T6_MULTILISTEN3(x) ((x) << S_T6_MULTILISTEN3) 8660 #define F_T6_MULTILISTEN3 V_T6_MULTILISTEN3(1U) 8661 8662 #define S_T6_MULTILISTEN2 28 8663 #define V_T6_MULTILISTEN2(x) ((x) << S_T6_MULTILISTEN2) 8664 #define F_T6_MULTILISTEN2 V_T6_MULTILISTEN2(1U) 8665 8666 #define S_T6_MULTILISTEN1 27 8667 #define V_T6_MULTILISTEN1(x) ((x) << S_T6_MULTILISTEN1) 8668 #define F_T6_MULTILISTEN1 V_T6_MULTILISTEN1(1U) 8669 8670 #define S_T6_MULTILISTEN0 26 8671 #define V_T6_MULTILISTEN0(x) ((x) << S_T6_MULTILISTEN0) 8672 #define F_T6_MULTILISTEN0 V_T6_MULTILISTEN0(1U) 8673 8674 #define S_T6_SRAM_PRIO3 23 8675 #define M_T6_SRAM_PRIO3 0x7U 8676 #define V_T6_SRAM_PRIO3(x) ((x) << S_T6_SRAM_PRIO3) 8677 #define G_T6_SRAM_PRIO3(x) (((x) >> S_T6_SRAM_PRIO3) & M_T6_SRAM_PRIO3) 8678 8679 #define S_T6_SRAM_PRIO2 20 8680 #define M_T6_SRAM_PRIO2 0x7U 8681 #define V_T6_SRAM_PRIO2(x) ((x) << S_T6_SRAM_PRIO2) 8682 #define G_T6_SRAM_PRIO2(x) (((x) >> S_T6_SRAM_PRIO2) & M_T6_SRAM_PRIO2) 8683 8684 #define S_T6_SRAM_PRIO1 17 8685 #define M_T6_SRAM_PRIO1 0x7U 8686 #define V_T6_SRAM_PRIO1(x) ((x) << S_T6_SRAM_PRIO1) 8687 #define G_T6_SRAM_PRIO1(x) (((x) >> S_T6_SRAM_PRIO1) & M_T6_SRAM_PRIO1) 8688 8689 #define S_T6_SRAM_PRIO0 14 8690 #define M_T6_SRAM_PRIO0 0x7U 8691 #define V_T6_SRAM_PRIO0(x) ((x) << S_T6_SRAM_PRIO0) 8692 #define G_T6_SRAM_PRIO0(x) (((x) >> S_T6_SRAM_PRIO0) & M_T6_SRAM_PRIO0) 8693 8694 #define S_T6_SRAM_VLD 13 8695 #define V_T6_SRAM_VLD(x) ((x) << S_T6_SRAM_VLD) 8696 #define F_T6_SRAM_VLD V_T6_SRAM_VLD(1U) 8697 8698 #define S_T6_REPLICATE 12 8699 #define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE) 8700 #define F_T6_REPLICATE V_T6_REPLICATE(1U) 8701 8702 #define S_T6_PF 9 8703 #define M_T6_PF 0x7U 8704 #define V_T6_PF(x) ((x) << S_T6_PF) 8705 #define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF) 8706 8707 #define S_T6_VF_VALID 8 8708 #define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID) 8709 #define F_T6_VF_VALID V_T6_VF_VALID(1U) 8710 8711 #define S_T6_VF 0 8712 #define M_T6_VF 0xffU 8713 #define V_T6_VF(x) ((x) << S_T6_VF) 8714 #define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF) 8715 8716 #define A_MPS_CLS_SRAM_H 0xe004 8717 8718 #define S_MACPARITY1 9 8719 #define V_MACPARITY1(x) ((x) << S_MACPARITY1) 8720 #define F_MACPARITY1 V_MACPARITY1(1U) 8721 8722 #define S_MACPARITY0 8 8723 #define V_MACPARITY0(x) ((x) << S_MACPARITY0) 8724 #define F_MACPARITY0 V_MACPARITY0(1U) 8725 8726 #define S_MACPARITYMASKSIZE 4 8727 #define M_MACPARITYMASKSIZE 0xfU 8728 #define V_MACPARITYMASKSIZE(x) ((x) << S_MACPARITYMASKSIZE) 8729 #define G_MACPARITYMASKSIZE(x) (((x) >> S_MACPARITYMASKSIZE) & M_MACPARITYMASKSIZE) 8730 8731 #define S_PORTMAP 0 8732 #define M_PORTMAP 0xfU 8733 #define V_PORTMAP(x) ((x) << S_PORTMAP) 8734 #define G_PORTMAP(x) (((x) >> S_PORTMAP) & M_PORTMAP) 8735 8736 #define A_MPS_T5_CLS_SRAM_H 0xe004 8737 8738 #define S_MACPARITY2 10 8739 #define V_MACPARITY2(x) ((x) << S_MACPARITY2) 8740 #define F_MACPARITY2 V_MACPARITY2(1U) 8741 8742 #define A_MPS_CLS_TCAM_Y_L 0xf000 8743 #define A_MPS_CLS_TCAM_DATA0 0xf000 8744 #define A_MPS_CLS_TCAM_DATA1 0xf004 8745 8746 #define S_VIDL 16 8747 #define M_VIDL 0xffffU 8748 #define V_VIDL(x) ((x) << S_VIDL) 8749 #define G_VIDL(x) (((x) >> S_VIDL) & M_VIDL) 8750 8751 #define S_DMACH 0 8752 #define M_DMACH 0xffffU 8753 #define V_DMACH(x) ((x) << S_DMACH) 8754 #define G_DMACH(x) (((x) >> S_DMACH) & M_DMACH) 8755 8756 #define A_MPS_CLS_TCAM_X_L 0xf008 8757 #define A_MPS_CLS_TCAM_DATA2_CTL 0xf008 8758 8759 #define S_CTLCMDTYPE 31 8760 #define V_CTLCMDTYPE(x) ((x) << S_CTLCMDTYPE) 8761 #define F_CTLCMDTYPE V_CTLCMDTYPE(1U) 8762 8763 #define S_CTLREQID 30 8764 #define V_CTLREQID(x) ((x) << S_CTLREQID) 8765 #define F_CTLREQID V_CTLREQID(1U) 8766 8767 #define S_CTLTCAMSEL 25 8768 #define V_CTLTCAMSEL(x) ((x) << S_CTLTCAMSEL) 8769 #define F_CTLTCAMSEL V_CTLTCAMSEL(1U) 8770 8771 #define S_CTLTCAMINDEX 17 8772 #define M_CTLTCAMINDEX 0xffU 8773 #define V_CTLTCAMINDEX(x) ((x) << S_CTLTCAMINDEX) 8774 #define G_CTLTCAMINDEX(x) (((x) >> S_CTLTCAMINDEX) & M_CTLTCAMINDEX) 8775 8776 #define S_CTLXYBITSEL 16 8777 #define V_CTLXYBITSEL(x) ((x) << S_CTLXYBITSEL) 8778 #define F_CTLXYBITSEL V_CTLXYBITSEL(1U) 8779 8780 #define S_DATAPORTNUM 12 8781 #define M_DATAPORTNUM 0xfU 8782 #define V_DATAPORTNUM(x) ((x) << S_DATAPORTNUM) 8783 #define G_DATAPORTNUM(x) (((x) >> S_DATAPORTNUM) & M_DATAPORTNUM) 8784 8785 #define S_DATALKPTYPE 10 8786 #define M_DATALKPTYPE 0x3U 8787 #define V_DATALKPTYPE(x) ((x) << S_DATALKPTYPE) 8788 #define G_DATALKPTYPE(x) (((x) >> S_DATALKPTYPE) & M_DATALKPTYPE) 8789 8790 #define S_DATADIPHIT 8 8791 #define V_DATADIPHIT(x) ((x) << S_DATADIPHIT) 8792 #define F_DATADIPHIT V_DATADIPHIT(1U) 8793 8794 #define S_DATAVIDH2 7 8795 #define V_DATAVIDH2(x) ((x) << S_DATAVIDH2) 8796 #define F_DATAVIDH2 V_DATAVIDH2(1U) 8797 8798 #define S_DATAVIDH1 0 8799 #define M_DATAVIDH1 0x7fU 8800 #define V_DATAVIDH1(x) ((x) << S_DATAVIDH1) 8801 #define G_DATAVIDH1(x) (((x) >> S_DATAVIDH1) & M_DATAVIDH1) 8802 8803 #define A_MPS_CLS_TCAM_RDATA0_REQ_ID0 0xf010 8804 #define A_MPS_CLS_TCAM_RDATA1_REQ_ID0 0xf014 8805 #define A_MPS_CLS_TCAM_RDATA2_REQ_ID0 0xf018 8806 #define A_MPS_CLS_TCAM_RDATA0_REQ_ID1 0xf020 8807 #define A_MPS_CLS_TCAM_RDATA1_REQ_ID1 0xf024 8808 #define A_MPS_CLS_TCAM_RDATA2_REQ_ID1 0xf028 8809 #define A_MPS_RX_PG_RSV0 0x11010 8810 8811 #define S_CLR_INTR 31 8812 #define V_CLR_INTR(x) ((x) << S_CLR_INTR) 8813 #define F_CLR_INTR V_CLR_INTR(1U) 8814 8815 #define S_SET_INTR 30 8816 #define V_SET_INTR(x) ((x) << S_SET_INTR) 8817 #define F_SET_INTR V_SET_INTR(1U) 8818 8819 #define S_USED 16 8820 #define M_USED 0x7ffU 8821 #define V_USED(x) ((x) << S_USED) 8822 #define G_USED(x) (((x) >> S_USED) & M_USED) 8823 8824 #define S_ALLOC 0 8825 #define M_ALLOC 0x7ffU 8826 #define V_ALLOC(x) ((x) << S_ALLOC) 8827 #define G_ALLOC(x) (((x) >> S_ALLOC) & M_ALLOC) 8828 8829 #define S_T5_USED 16 8830 #define M_T5_USED 0xfffU 8831 #define V_T5_USED(x) ((x) << S_T5_USED) 8832 #define G_T5_USED(x) (((x) >> S_T5_USED) & M_T5_USED) 8833 8834 #define S_T5_ALLOC 0 8835 #define M_T5_ALLOC 0xfffU 8836 #define V_T5_ALLOC(x) ((x) << S_T5_ALLOC) 8837 #define G_T5_ALLOC(x) (((x) >> S_T5_ALLOC) & M_T5_ALLOC) 8838 8839 #define A_MPS_RX_PG_RSV1 0x11014 8840 #define A_MPS_RX_PG_RSV2 0x11018 8841 #define A_MPS_RX_PG_RSV3 0x1101c 8842 #define A_MPS_RX_PG_RSV4 0x11020 8843 #define A_MPS_RX_PG_RSV5 0x11024 8844 #define A_MPS_RX_PG_RSV6 0x11028 8845 #define A_MPS_RX_PG_RSV7 0x1102c 8846 #define A_MPS_RX_PERR_INT_CAUSE 0x11074 8847 8848 #define S_FF 23 8849 #define V_FF(x) ((x) << S_FF) 8850 #define F_FF V_FF(1U) 8851 8852 #define S_PGMO 22 8853 #define V_PGMO(x) ((x) << S_PGMO) 8854 #define F_PGMO V_PGMO(1U) 8855 8856 #define S_PGME 21 8857 #define V_PGME(x) ((x) << S_PGME) 8858 #define F_PGME V_PGME(1U) 8859 8860 #define S_CHMN 20 8861 #define V_CHMN(x) ((x) << S_CHMN) 8862 #define F_CHMN V_CHMN(1U) 8863 8864 #define S_RPLC 19 8865 #define V_RPLC(x) ((x) << S_RPLC) 8866 #define F_RPLC V_RPLC(1U) 8867 8868 #define S_ATRB 18 8869 #define V_ATRB(x) ((x) << S_ATRB) 8870 #define F_ATRB V_ATRB(1U) 8871 8872 #define S_PSMX 17 8873 #define V_PSMX(x) ((x) << S_PSMX) 8874 #define F_PSMX V_PSMX(1U) 8875 8876 #define S_PGLL 16 8877 #define V_PGLL(x) ((x) << S_PGLL) 8878 #define F_PGLL V_PGLL(1U) 8879 8880 #define S_PGFL 15 8881 #define V_PGFL(x) ((x) << S_PGFL) 8882 #define F_PGFL V_PGFL(1U) 8883 8884 #define S_PKTQ 14 8885 #define V_PKTQ(x) ((x) << S_PKTQ) 8886 #define F_PKTQ V_PKTQ(1U) 8887 8888 #define S_PKFL 13 8889 #define V_PKFL(x) ((x) << S_PKFL) 8890 #define F_PKFL V_PKFL(1U) 8891 8892 #define S_PPM3 12 8893 #define V_PPM3(x) ((x) << S_PPM3) 8894 #define F_PPM3 V_PPM3(1U) 8895 8896 #define S_PPM2 11 8897 #define V_PPM2(x) ((x) << S_PPM2) 8898 #define F_PPM2 V_PPM2(1U) 8899 8900 #define S_PPM1 10 8901 #define V_PPM1(x) ((x) << S_PPM1) 8902 #define F_PPM1 V_PPM1(1U) 8903 8904 #define S_PPM0 9 8905 #define V_PPM0(x) ((x) << S_PPM0) 8906 #define F_PPM0 V_PPM0(1U) 8907 8908 #define S_SPMX 8 8909 #define V_SPMX(x) ((x) << S_SPMX) 8910 #define F_SPMX V_SPMX(1U) 8911 8912 #define S_CDL3 7 8913 #define V_CDL3(x) ((x) << S_CDL3) 8914 #define F_CDL3 V_CDL3(1U) 8915 8916 #define S_CDL2 6 8917 #define V_CDL2(x) ((x) << S_CDL2) 8918 #define F_CDL2 V_CDL2(1U) 8919 8920 #define S_CDL1 5 8921 #define V_CDL1(x) ((x) << S_CDL1) 8922 #define F_CDL1 V_CDL1(1U) 8923 8924 #define S_CDL0 4 8925 #define V_CDL0(x) ((x) << S_CDL0) 8926 #define F_CDL0 V_CDL0(1U) 8927 8928 #define S_CDM3 3 8929 #define V_CDM3(x) ((x) << S_CDM3) 8930 #define F_CDM3 V_CDM3(1U) 8931 8932 #define S_CDM2 2 8933 #define V_CDM2(x) ((x) << S_CDM2) 8934 #define F_CDM2 V_CDM2(1U) 8935 8936 #define S_CDM1 1 8937 #define V_CDM1(x) ((x) << S_CDM1) 8938 #define F_CDM1 V_CDM1(1U) 8939 8940 #define S_CDM0 0 8941 #define V_CDM0(x) ((x) << S_CDM0) 8942 #define F_CDM0 V_CDM0(1U) 8943 8944 #define A_MPS_RX_SE_CNT_IN0 0x11148 8945 8946 #define S_SOP_CNT_PM 24 8947 #define M_SOP_CNT_PM 0xffU 8948 #define V_SOP_CNT_PM(x) ((x) << S_SOP_CNT_PM) 8949 #define G_SOP_CNT_PM(x) (((x) >> S_SOP_CNT_PM) & M_SOP_CNT_PM) 8950 8951 #define S_EOP_CNT_PM 16 8952 #define M_EOP_CNT_PM 0xffU 8953 #define V_EOP_CNT_PM(x) ((x) << S_EOP_CNT_PM) 8954 #define G_EOP_CNT_PM(x) (((x) >> S_EOP_CNT_PM) & M_EOP_CNT_PM) 8955 8956 #define S_SOP_CNT_IN 8 8957 #define M_SOP_CNT_IN 0xffU 8958 #define V_SOP_CNT_IN(x) ((x) << S_SOP_CNT_IN) 8959 #define G_SOP_CNT_IN(x) (((x) >> S_SOP_CNT_IN) & M_SOP_CNT_IN) 8960 8961 #define S_EOP_CNT_IN 0 8962 #define M_EOP_CNT_IN 0xffU 8963 #define V_EOP_CNT_IN(x) ((x) << S_EOP_CNT_IN) 8964 #define G_EOP_CNT_IN(x) (((x) >> S_EOP_CNT_IN) & M_EOP_CNT_IN) 8965 8966 #define A_MPS_RX_SE_CNT_IN1 0x1114c 8967 #define A_MPS_RX_SE_CNT_IN2 0x11150 8968 #define A_MPS_RX_SE_CNT_IN3 0x11154 8969 #define A_MPS_RX_SE_CNT_IN4 0x11158 8970 #define A_MPS_RX_SE_CNT_IN5 0x1115c 8971 #define A_MPS_RX_SE_CNT_IN6 0x11160 8972 #define A_MPS_RX_SE_CNT_IN7 0x11164 8973 #define A_MPS_RX_SE_CNT_OUT01 0x11168 8974 8975 #define S_SOP_CNT_1 24 8976 #define M_SOP_CNT_1 0xffU 8977 #define V_SOP_CNT_1(x) ((x) << S_SOP_CNT_1) 8978 #define G_SOP_CNT_1(x) (((x) >> S_SOP_CNT_1) & M_SOP_CNT_1) 8979 8980 #define S_EOP_CNT_1 16 8981 #define M_EOP_CNT_1 0xffU 8982 #define V_EOP_CNT_1(x) ((x) << S_EOP_CNT_1) 8983 #define G_EOP_CNT_1(x) (((x) >> S_EOP_CNT_1) & M_EOP_CNT_1) 8984 8985 #define S_SOP_CNT_0 8 8986 #define M_SOP_CNT_0 0xffU 8987 #define V_SOP_CNT_0(x) ((x) << S_SOP_CNT_0) 8988 #define G_SOP_CNT_0(x) (((x) >> S_SOP_CNT_0) & M_SOP_CNT_0) 8989 8990 #define S_EOP_CNT_0 0 8991 #define M_EOP_CNT_0 0xffU 8992 #define V_EOP_CNT_0(x) ((x) << S_EOP_CNT_0) 8993 #define G_EOP_CNT_0(x) (((x) >> S_EOP_CNT_0) & M_EOP_CNT_0) 8994 8995 #define A_MPS_RX_SE_CNT_OUT23 0x1116c 8996 8997 #define S_SOP_CNT_3 24 8998 #define M_SOP_CNT_3 0xffU 8999 #define V_SOP_CNT_3(x) ((x) << S_SOP_CNT_3) 9000 #define G_SOP_CNT_3(x) (((x) >> S_SOP_CNT_3) & M_SOP_CNT_3) 9001 9002 #define S_EOP_CNT_3 16 9003 #define M_EOP_CNT_3 0xffU 9004 #define V_EOP_CNT_3(x) ((x) << S_EOP_CNT_3) 9005 #define G_EOP_CNT_3(x) (((x) >> S_EOP_CNT_3) & M_EOP_CNT_3) 9006 9007 #define S_SOP_CNT_2 8 9008 #define M_SOP_CNT_2 0xffU 9009 #define V_SOP_CNT_2(x) ((x) << S_SOP_CNT_2) 9010 #define G_SOP_CNT_2(x) (((x) >> S_SOP_CNT_2) & M_SOP_CNT_2) 9011 9012 #define S_EOP_CNT_2 0 9013 #define M_EOP_CNT_2 0xffU 9014 #define V_EOP_CNT_2(x) ((x) << S_EOP_CNT_2) 9015 #define G_EOP_CNT_2(x) (((x) >> S_EOP_CNT_2) & M_EOP_CNT_2) 9016 9017 #define A_MPS_RX_CLS_DROP_CNT0 0x11180 9018 9019 #define S_LPBK_CNT0 16 9020 #define M_LPBK_CNT0 0xffffU 9021 #define V_LPBK_CNT0(x) ((x) << S_LPBK_CNT0) 9022 #define G_LPBK_CNT0(x) (((x) >> S_LPBK_CNT0) & M_LPBK_CNT0) 9023 9024 #define S_MAC_CNT0 0 9025 #define M_MAC_CNT0 0xffffU 9026 #define V_MAC_CNT0(x) ((x) << S_MAC_CNT0) 9027 #define G_MAC_CNT0(x) (((x) >> S_MAC_CNT0) & M_MAC_CNT0) 9028 9029 #define A_MPS_RX_CLS_DROP_CNT1 0x11184 9030 9031 #define S_LPBK_CNT1 16 9032 #define M_LPBK_CNT1 0xffffU 9033 #define V_LPBK_CNT1(x) ((x) << S_LPBK_CNT1) 9034 #define G_LPBK_CNT1(x) (((x) >> S_LPBK_CNT1) & M_LPBK_CNT1) 9035 9036 #define S_MAC_CNT1 0 9037 #define M_MAC_CNT1 0xffffU 9038 #define V_MAC_CNT1(x) ((x) << S_MAC_CNT1) 9039 #define G_MAC_CNT1(x) (((x) >> S_MAC_CNT1) & M_MAC_CNT1) 9040 9041 #define A_MPS_RX_CLS_DROP_CNT2 0x11188 9042 9043 #define S_LPBK_CNT2 16 9044 #define M_LPBK_CNT2 0xffffU 9045 #define V_LPBK_CNT2(x) ((x) << S_LPBK_CNT2) 9046 #define G_LPBK_CNT2(x) (((x) >> S_LPBK_CNT2) & M_LPBK_CNT2) 9047 9048 #define S_MAC_CNT2 0 9049 #define M_MAC_CNT2 0xffffU 9050 #define V_MAC_CNT2(x) ((x) << S_MAC_CNT2) 9051 #define G_MAC_CNT2(x) (((x) >> S_MAC_CNT2) & M_MAC_CNT2) 9052 9053 #define A_MPS_RX_CLS_DROP_CNT3 0x1118c 9054 9055 #define S_LPBK_CNT3 16 9056 #define M_LPBK_CNT3 0xffffU 9057 #define V_LPBK_CNT3(x) ((x) << S_LPBK_CNT3) 9058 #define G_LPBK_CNT3(x) (((x) >> S_LPBK_CNT3) & M_LPBK_CNT3) 9059 9060 #define S_MAC_CNT3 0 9061 #define M_MAC_CNT3 0xffffU 9062 #define V_MAC_CNT3(x) ((x) << S_MAC_CNT3) 9063 #define G_MAC_CNT3(x) (((x) >> S_MAC_CNT3) & M_MAC_CNT3) 9064 9065 #define A_MPS_RX_MAC_CLS_DROP_CNT0 0x111e4 9066 #define A_MPS_RX_MAC_CLS_DROP_CNT1 0x111e8 9067 #define A_MPS_RX_MAC_CLS_DROP_CNT2 0x111ec 9068 #define A_MPS_RX_MAC_CLS_DROP_CNT3 0x111f0 9069 #define A_MPS_RX_LPBK_CLS_DROP_CNT0 0x111f4 9070 #define A_MPS_RX_LPBK_CLS_DROP_CNT1 0x111f8 9071 #define A_MPS_RX_LPBK_CLS_DROP_CNT2 0x111fc 9072 #define A_MPS_RX_LPBK_CLS_DROP_CNT3 0x11200 9073 #define A_MPS_RX_MAC_BG_PG_CNT0 0x11208 9074 9075 #define S_MAC_USED 16 9076 #define M_MAC_USED 0x7ffU 9077 #define V_MAC_USED(x) ((x) << S_MAC_USED) 9078 #define G_MAC_USED(x) (((x) >> S_MAC_USED) & M_MAC_USED) 9079 9080 #define S_MAC_ALLOC 0 9081 #define M_MAC_ALLOC 0x7ffU 9082 #define V_MAC_ALLOC(x) ((x) << S_MAC_ALLOC) 9083 #define G_MAC_ALLOC(x) (((x) >> S_MAC_ALLOC) & M_MAC_ALLOC) 9084 9085 #define A_MPS_RX_MAC_BG_PG_CNT1 0x1120c 9086 #define A_MPS_RX_MAC_BG_PG_CNT2 0x11210 9087 #define A_MPS_RX_MAC_BG_PG_CNT3 0x11214 9088 #define A_MPS_RX_LPBK_BG_PG_CNT0 0x11218 9089 9090 #define S_LPBK_USED 16 9091 #define M_LPBK_USED 0x7ffU 9092 #define V_LPBK_USED(x) ((x) << S_LPBK_USED) 9093 #define G_LPBK_USED(x) (((x) >> S_LPBK_USED) & M_LPBK_USED) 9094 9095 #define S_LPBK_ALLOC 0 9096 #define M_LPBK_ALLOC 0x7ffU 9097 #define V_LPBK_ALLOC(x) ((x) << S_LPBK_ALLOC) 9098 #define G_LPBK_ALLOC(x) (((x) >> S_LPBK_ALLOC) & M_LPBK_ALLOC) 9099 9100 #define A_MPS_RX_LPBK_BG_PG_CNT1 0x1121c 9101 #define A_MPS_RX_GRE_PROT_TYPE 0x11230 9102 9103 #define S_NVGRE_EN 9 9104 #define V_NVGRE_EN(x) ((x) << S_NVGRE_EN) 9105 #define F_NVGRE_EN V_NVGRE_EN(1U) 9106 9107 #define S_GRE_EN 8 9108 #define V_GRE_EN(x) ((x) << S_GRE_EN) 9109 #define F_GRE_EN V_GRE_EN(1U) 9110 9111 #define S_GRE 0 9112 #define M_GRE 0xffU 9113 #define V_GRE(x) ((x) << S_GRE) 9114 #define G_GRE(x) (((x) >> S_GRE) & M_GRE) 9115 9116 #define A_MPS_RX_VXLAN_TYPE 0x11234 9117 9118 #define S_VXLAN_EN 16 9119 #define V_VXLAN_EN(x) ((x) << S_VXLAN_EN) 9120 #define F_VXLAN_EN V_VXLAN_EN(1U) 9121 9122 #define S_VXLAN 0 9123 #define M_VXLAN 0xffffU 9124 #define V_VXLAN(x) ((x) << S_VXLAN) 9125 #define G_VXLAN(x) (((x) >> S_VXLAN) & M_VXLAN) 9126 9127 #define A_MPS_RX_GENEVE_TYPE 0x11238 9128 9129 #define S_GENEVE_EN 16 9130 #define V_GENEVE_EN(x) ((x) << S_GENEVE_EN) 9131 #define F_GENEVE_EN V_GENEVE_EN(1U) 9132 9133 #define S_GENEVE 0 9134 #define M_GENEVE 0xffffU 9135 #define V_GENEVE(x) ((x) << S_GENEVE) 9136 #define G_GENEVE(x) (((x) >> S_GENEVE) & M_GENEVE) 9137 9138 #define A_MPS_RX_ENCAP_NVGRE 0x11240 9139 9140 #define S_ETYPE_EN 16 9141 #define V_ETYPE_EN(x) ((x) << S_ETYPE_EN) 9142 #define F_ETYPE_EN V_ETYPE_EN(1U) 9143 9144 #define S_ETYPE 0 9145 #define M_ETYPE 0xffffU 9146 #define V_ETYPE(x) ((x) << S_ETYPE) 9147 #define G_ETYPE(x) (((x) >> S_ETYPE) & M_ETYPE) 9148 9149 #define A_MPS_RX_ENCAP_GENEVE 0x11244 9150 9151 /* registers for module CPL_SWITCH */ 9152 #define CPL_SWITCH_BASE_ADDR 0x19040 9153 9154 #define A_CPL_INTR_ENABLE 0x19050 9155 9156 #define S_CIM_OP_MAP_PERR 5 9157 #define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR) 9158 #define F_CIM_OP_MAP_PERR V_CIM_OP_MAP_PERR(1U) 9159 9160 #define S_CIM_OVFL_ERROR 4 9161 #define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR) 9162 #define F_CIM_OVFL_ERROR V_CIM_OVFL_ERROR(1U) 9163 9164 #define S_TP_FRAMING_ERROR 3 9165 #define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR) 9166 #define F_TP_FRAMING_ERROR V_TP_FRAMING_ERROR(1U) 9167 9168 #define S_SGE_FRAMING_ERROR 2 9169 #define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR) 9170 #define F_SGE_FRAMING_ERROR V_SGE_FRAMING_ERROR(1U) 9171 9172 #define S_CIM_FRAMING_ERROR 1 9173 #define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR) 9174 #define F_CIM_FRAMING_ERROR V_CIM_FRAMING_ERROR(1U) 9175 9176 #define S_ZERO_SWITCH_ERROR 0 9177 #define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR) 9178 #define F_ZERO_SWITCH_ERROR V_ZERO_SWITCH_ERROR(1U) 9179 9180 #define S_PERR_CPL_128TO128_1 7 9181 #define V_PERR_CPL_128TO128_1(x) ((x) << S_PERR_CPL_128TO128_1) 9182 #define F_PERR_CPL_128TO128_1 V_PERR_CPL_128TO128_1(1U) 9183 9184 #define S_PERR_CPL_128TO128_0 6 9185 #define V_PERR_CPL_128TO128_0(x) ((x) << S_PERR_CPL_128TO128_0) 9186 #define F_PERR_CPL_128TO128_0 V_PERR_CPL_128TO128_0(1U) 9187 9188 #define A_CPL_INTR_CAUSE 0x19054 9189 9190 /* registers for module SMB */ 9191 #define SMB_BASE_ADDR 0x19060 9192 9193 #define A_SMB_INT_ENABLE 0x1908c 9194 9195 #define S_MSTTXFIFOPAREN 21 9196 #define V_MSTTXFIFOPAREN(x) ((x) << S_MSTTXFIFOPAREN) 9197 #define F_MSTTXFIFOPAREN V_MSTTXFIFOPAREN(1U) 9198 9199 #define S_MSTRXFIFOPAREN 20 9200 #define V_MSTRXFIFOPAREN(x) ((x) << S_MSTRXFIFOPAREN) 9201 #define F_MSTRXFIFOPAREN V_MSTRXFIFOPAREN(1U) 9202 9203 #define S_SLVFIFOPAREN 19 9204 #define V_SLVFIFOPAREN(x) ((x) << S_SLVFIFOPAREN) 9205 #define F_SLVFIFOPAREN V_SLVFIFOPAREN(1U) 9206 9207 #define A_SMB_INT_CAUSE 0x19090 9208 9209 #define S_MSTTXFIFOPARINT 21 9210 #define V_MSTTXFIFOPARINT(x) ((x) << S_MSTTXFIFOPARINT) 9211 #define F_MSTTXFIFOPARINT V_MSTTXFIFOPARINT(1U) 9212 9213 #define S_MSTRXFIFOPARINT 20 9214 #define V_MSTRXFIFOPARINT(x) ((x) << S_MSTRXFIFOPARINT) 9215 #define F_MSTRXFIFOPARINT V_MSTRXFIFOPARINT(1U) 9216 9217 #define S_SLVFIFOPARINT 19 9218 #define V_SLVFIFOPARINT(x) ((x) << S_SLVFIFOPARINT) 9219 #define F_SLVFIFOPARINT V_SLVFIFOPARINT(1U) 9220 9221 9222 /* registers for module I2CM */ 9223 #define I2CM_BASE_ADDR 0x190f0 9224 9225 #define A_I2CM_CFG 0x190f0 9226 9227 #define S_I2C_CLKDIV16B 0 9228 #define M_I2C_CLKDIV16B 0xffffU 9229 #define V_I2C_CLKDIV16B(x) ((x) << S_I2C_CLKDIV16B) 9230 #define G_I2C_CLKDIV16B(x) (((x) >> S_I2C_CLKDIV16B) & M_I2C_CLKDIV16B) 9231 9232 9233 /* registers for module MI */ 9234 #define MI_BASE_ADDR 0x19100 9235 9236 9237 /* registers for module UART */ 9238 #define UART_BASE_ADDR 0x19110 9239 9240 9241 /* registers for module PMU */ 9242 #define PMU_BASE_ADDR 0x19120 9243 9244 9245 /* registers for module ULP_RX */ 9246 #define ULP_RX_BASE_ADDR 0x19150 9247 9248 #define A_ULP_RX_CTL 0x19150 9249 9250 #define S_PCMD1THRESHOLD 24 9251 #define M_PCMD1THRESHOLD 0xffU 9252 #define V_PCMD1THRESHOLD(x) ((x) << S_PCMD1THRESHOLD) 9253 #define G_PCMD1THRESHOLD(x) (((x) >> S_PCMD1THRESHOLD) & M_PCMD1THRESHOLD) 9254 9255 #define S_PCMD0THRESHOLD 16 9256 #define M_PCMD0THRESHOLD 0xffU 9257 #define V_PCMD0THRESHOLD(x) ((x) << S_PCMD0THRESHOLD) 9258 #define G_PCMD0THRESHOLD(x) (((x) >> S_PCMD0THRESHOLD) & M_PCMD0THRESHOLD) 9259 9260 #define S_DISABLE_0B_STAG_ERR 14 9261 #define V_DISABLE_0B_STAG_ERR(x) ((x) << S_DISABLE_0B_STAG_ERR) 9262 #define F_DISABLE_0B_STAG_ERR V_DISABLE_0B_STAG_ERR(1U) 9263 9264 #define S_RDMA_0B_WR_OPCODE 10 9265 #define M_RDMA_0B_WR_OPCODE 0xfU 9266 #define V_RDMA_0B_WR_OPCODE(x) ((x) << S_RDMA_0B_WR_OPCODE) 9267 #define G_RDMA_0B_WR_OPCODE(x) (((x) >> S_RDMA_0B_WR_OPCODE) & M_RDMA_0B_WR_OPCODE) 9268 9269 #define S_RDMA_0B_WR_PASS 9 9270 #define V_RDMA_0B_WR_PASS(x) ((x) << S_RDMA_0B_WR_PASS) 9271 #define F_RDMA_0B_WR_PASS V_RDMA_0B_WR_PASS(1U) 9272 9273 #define S_STAG_RQE 8 9274 #define V_STAG_RQE(x) ((x) << S_STAG_RQE) 9275 #define F_STAG_RQE V_STAG_RQE(1U) 9276 9277 #define S_RDMA_STATE_EN 7 9278 #define V_RDMA_STATE_EN(x) ((x) << S_RDMA_STATE_EN) 9279 #define F_RDMA_STATE_EN V_RDMA_STATE_EN(1U) 9280 9281 #define S_CRC1_EN 6 9282 #define V_CRC1_EN(x) ((x) << S_CRC1_EN) 9283 #define F_CRC1_EN V_CRC1_EN(1U) 9284 9285 #define S_RDMA_0B_WR_CQE 5 9286 #define V_RDMA_0B_WR_CQE(x) ((x) << S_RDMA_0B_WR_CQE) 9287 #define F_RDMA_0B_WR_CQE V_RDMA_0B_WR_CQE(1U) 9288 9289 #define S_PCIE_ATRB_EN 4 9290 #define V_PCIE_ATRB_EN(x) ((x) << S_PCIE_ATRB_EN) 9291 #define F_PCIE_ATRB_EN V_PCIE_ATRB_EN(1U) 9292 9293 #define S_RDMA_PERMISSIVE_MODE 3 9294 #define V_RDMA_PERMISSIVE_MODE(x) ((x) << S_RDMA_PERMISSIVE_MODE) 9295 #define F_RDMA_PERMISSIVE_MODE V_RDMA_PERMISSIVE_MODE(1U) 9296 9297 #define S_PAGEPODME 2 9298 #define V_PAGEPODME(x) ((x) << S_PAGEPODME) 9299 #define F_PAGEPODME V_PAGEPODME(1U) 9300 9301 #define S_ISCSITAGTCB 1 9302 #define V_ISCSITAGTCB(x) ((x) << S_ISCSITAGTCB) 9303 #define F_ISCSITAGTCB V_ISCSITAGTCB(1U) 9304 9305 #define S_TDDPTAGTCB 0 9306 #define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB) 9307 #define F_TDDPTAGTCB V_TDDPTAGTCB(1U) 9308 9309 #define A_ULP_RX_INT_CAUSE 0x19158 9310 9311 #define S_CAUSE_CTX_1 24 9312 #define V_CAUSE_CTX_1(x) ((x) << S_CAUSE_CTX_1) 9313 #define F_CAUSE_CTX_1 V_CAUSE_CTX_1(1U) 9314 9315 #define S_CAUSE_CTX_0 23 9316 #define V_CAUSE_CTX_0(x) ((x) << S_CAUSE_CTX_0) 9317 #define F_CAUSE_CTX_0 V_CAUSE_CTX_0(1U) 9318 9319 #define S_CAUSE_FF 22 9320 #define V_CAUSE_FF(x) ((x) << S_CAUSE_FF) 9321 #define F_CAUSE_FF V_CAUSE_FF(1U) 9322 9323 #define S_CAUSE_APF_1 21 9324 #define V_CAUSE_APF_1(x) ((x) << S_CAUSE_APF_1) 9325 #define F_CAUSE_APF_1 V_CAUSE_APF_1(1U) 9326 9327 #define S_CAUSE_APF_0 20 9328 #define V_CAUSE_APF_0(x) ((x) << S_CAUSE_APF_0) 9329 #define F_CAUSE_APF_0 V_CAUSE_APF_0(1U) 9330 9331 #define S_CAUSE_AF_1 19 9332 #define V_CAUSE_AF_1(x) ((x) << S_CAUSE_AF_1) 9333 #define F_CAUSE_AF_1 V_CAUSE_AF_1(1U) 9334 9335 #define S_CAUSE_AF_0 18 9336 #define V_CAUSE_AF_0(x) ((x) << S_CAUSE_AF_0) 9337 #define F_CAUSE_AF_0 V_CAUSE_AF_0(1U) 9338 9339 #define S_CAUSE_DDPDF_1 17 9340 #define V_CAUSE_DDPDF_1(x) ((x) << S_CAUSE_DDPDF_1) 9341 #define F_CAUSE_DDPDF_1 V_CAUSE_DDPDF_1(1U) 9342 9343 #define S_CAUSE_DDPMF_1 16 9344 #define V_CAUSE_DDPMF_1(x) ((x) << S_CAUSE_DDPMF_1) 9345 #define F_CAUSE_DDPMF_1 V_CAUSE_DDPMF_1(1U) 9346 9347 #define S_CAUSE_MEMRF_1 15 9348 #define V_CAUSE_MEMRF_1(x) ((x) << S_CAUSE_MEMRF_1) 9349 #define F_CAUSE_MEMRF_1 V_CAUSE_MEMRF_1(1U) 9350 9351 #define S_CAUSE_PRSDF_1 14 9352 #define V_CAUSE_PRSDF_1(x) ((x) << S_CAUSE_PRSDF_1) 9353 #define F_CAUSE_PRSDF_1 V_CAUSE_PRSDF_1(1U) 9354 9355 #define S_CAUSE_DDPDF_0 13 9356 #define V_CAUSE_DDPDF_0(x) ((x) << S_CAUSE_DDPDF_0) 9357 #define F_CAUSE_DDPDF_0 V_CAUSE_DDPDF_0(1U) 9358 9359 #define S_CAUSE_DDPMF_0 12 9360 #define V_CAUSE_DDPMF_0(x) ((x) << S_CAUSE_DDPMF_0) 9361 #define F_CAUSE_DDPMF_0 V_CAUSE_DDPMF_0(1U) 9362 9363 #define S_CAUSE_MEMRF_0 11 9364 #define V_CAUSE_MEMRF_0(x) ((x) << S_CAUSE_MEMRF_0) 9365 #define F_CAUSE_MEMRF_0 V_CAUSE_MEMRF_0(1U) 9366 9367 #define S_CAUSE_PRSDF_0 10 9368 #define V_CAUSE_PRSDF_0(x) ((x) << S_CAUSE_PRSDF_0) 9369 #define F_CAUSE_PRSDF_0 V_CAUSE_PRSDF_0(1U) 9370 9371 #define S_CAUSE_PCMDF_1 9 9372 #define V_CAUSE_PCMDF_1(x) ((x) << S_CAUSE_PCMDF_1) 9373 #define F_CAUSE_PCMDF_1 V_CAUSE_PCMDF_1(1U) 9374 9375 #define S_CAUSE_TPTCF_1 8 9376 #define V_CAUSE_TPTCF_1(x) ((x) << S_CAUSE_TPTCF_1) 9377 #define F_CAUSE_TPTCF_1 V_CAUSE_TPTCF_1(1U) 9378 9379 #define S_CAUSE_DDPCF_1 7 9380 #define V_CAUSE_DDPCF_1(x) ((x) << S_CAUSE_DDPCF_1) 9381 #define F_CAUSE_DDPCF_1 V_CAUSE_DDPCF_1(1U) 9382 9383 #define S_CAUSE_MPARF_1 6 9384 #define V_CAUSE_MPARF_1(x) ((x) << S_CAUSE_MPARF_1) 9385 #define F_CAUSE_MPARF_1 V_CAUSE_MPARF_1(1U) 9386 9387 #define S_CAUSE_MPARC_1 5 9388 #define V_CAUSE_MPARC_1(x) ((x) << S_CAUSE_MPARC_1) 9389 #define F_CAUSE_MPARC_1 V_CAUSE_MPARC_1(1U) 9390 9391 #define S_CAUSE_PCMDF_0 4 9392 #define V_CAUSE_PCMDF_0(x) ((x) << S_CAUSE_PCMDF_0) 9393 #define F_CAUSE_PCMDF_0 V_CAUSE_PCMDF_0(1U) 9394 9395 #define S_CAUSE_TPTCF_0 3 9396 #define V_CAUSE_TPTCF_0(x) ((x) << S_CAUSE_TPTCF_0) 9397 #define F_CAUSE_TPTCF_0 V_CAUSE_TPTCF_0(1U) 9398 9399 #define S_CAUSE_DDPCF_0 2 9400 #define V_CAUSE_DDPCF_0(x) ((x) << S_CAUSE_DDPCF_0) 9401 #define F_CAUSE_DDPCF_0 V_CAUSE_DDPCF_0(1U) 9402 9403 #define S_CAUSE_MPARF_0 1 9404 #define V_CAUSE_MPARF_0(x) ((x) << S_CAUSE_MPARF_0) 9405 #define F_CAUSE_MPARF_0 V_CAUSE_MPARF_0(1U) 9406 9407 #define S_CAUSE_MPARC_0 0 9408 #define V_CAUSE_MPARC_0(x) ((x) << S_CAUSE_MPARC_0) 9409 #define F_CAUSE_MPARC_0 V_CAUSE_MPARC_0(1U) 9410 9411 #define S_SE_CNT_MISMATCH_1 26 9412 #define V_SE_CNT_MISMATCH_1(x) ((x) << S_SE_CNT_MISMATCH_1) 9413 #define F_SE_CNT_MISMATCH_1 V_SE_CNT_MISMATCH_1(1U) 9414 9415 #define S_SE_CNT_MISMATCH_0 25 9416 #define V_SE_CNT_MISMATCH_0(x) ((x) << S_SE_CNT_MISMATCH_0) 9417 #define F_SE_CNT_MISMATCH_0 V_SE_CNT_MISMATCH_0(1U) 9418 9419 #define A_ULP_RX_ISCSI_LLIMIT 0x1915c 9420 9421 #define S_ISCSILLIMIT 6 9422 #define M_ISCSILLIMIT 0x3ffffffU 9423 #define V_ISCSILLIMIT(x) ((x) << S_ISCSILLIMIT) 9424 #define G_ISCSILLIMIT(x) (((x) >> S_ISCSILLIMIT) & M_ISCSILLIMIT) 9425 9426 #define A_ULP_RX_ISCSI_ULIMIT 0x19160 9427 9428 #define S_ISCSIULIMIT 6 9429 #define M_ISCSIULIMIT 0x3ffffffU 9430 #define V_ISCSIULIMIT(x) ((x) << S_ISCSIULIMIT) 9431 #define G_ISCSIULIMIT(x) (((x) >> S_ISCSIULIMIT) & M_ISCSIULIMIT) 9432 9433 #define A_ULP_RX_ISCSI_TAGMASK 0x19164 9434 9435 #define S_ISCSITAGMASK 6 9436 #define M_ISCSITAGMASK 0x3ffffffU 9437 #define V_ISCSITAGMASK(x) ((x) << S_ISCSITAGMASK) 9438 #define G_ISCSITAGMASK(x) (((x) >> S_ISCSITAGMASK) & M_ISCSITAGMASK) 9439 9440 #define A_ULP_RX_ISCSI_PSZ 0x19168 9441 9442 #define S_HPZ3 24 9443 #define M_HPZ3 0xfU 9444 #define V_HPZ3(x) ((x) << S_HPZ3) 9445 #define G_HPZ3(x) (((x) >> S_HPZ3) & M_HPZ3) 9446 9447 #define S_HPZ2 16 9448 #define M_HPZ2 0xfU 9449 #define V_HPZ2(x) ((x) << S_HPZ2) 9450 #define G_HPZ2(x) (((x) >> S_HPZ2) & M_HPZ2) 9451 9452 #define S_HPZ1 8 9453 #define M_HPZ1 0xfU 9454 #define V_HPZ1(x) ((x) << S_HPZ1) 9455 #define G_HPZ1(x) (((x) >> S_HPZ1) & M_HPZ1) 9456 9457 #define S_HPZ0 0 9458 #define M_HPZ0 0xfU 9459 #define V_HPZ0(x) ((x) << S_HPZ0) 9460 #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0) 9461 9462 #define A_ULP_RX_TDDP_LLIMIT 0x1916c 9463 9464 #define S_TDDPLLIMIT 6 9465 #define M_TDDPLLIMIT 0x3ffffffU 9466 #define V_TDDPLLIMIT(x) ((x) << S_TDDPLLIMIT) 9467 #define G_TDDPLLIMIT(x) (((x) >> S_TDDPLLIMIT) & M_TDDPLLIMIT) 9468 9469 #define A_ULP_RX_TDDP_ULIMIT 0x19170 9470 9471 #define S_TDDPULIMIT 6 9472 #define M_TDDPULIMIT 0x3ffffffU 9473 #define V_TDDPULIMIT(x) ((x) << S_TDDPULIMIT) 9474 #define G_TDDPULIMIT(x) (((x) >> S_TDDPULIMIT) & M_TDDPULIMIT) 9475 9476 #define A_ULP_RX_TDDP_TAGMASK 0x19174 9477 9478 #define S_TDDPTAGMASK 6 9479 #define M_TDDPTAGMASK 0x3ffffffU 9480 #define V_TDDPTAGMASK(x) ((x) << S_TDDPTAGMASK) 9481 #define G_TDDPTAGMASK(x) (((x) >> S_TDDPTAGMASK) & M_TDDPTAGMASK) 9482 9483 #define A_ULP_RX_TDDP_PSZ 0x19178 9484 #define A_ULP_RX_STAG_LLIMIT 0x1917c 9485 #define A_ULP_RX_STAG_ULIMIT 0x19180 9486 #define A_ULP_RX_RQ_LLIMIT 0x19184 9487 #define A_ULP_RX_RQ_ULIMIT 0x19188 9488 #define A_ULP_RX_PBL_LLIMIT 0x1918c 9489 #define A_ULP_RX_PBL_ULIMIT 0x19190 9490 #define A_ULP_RX_CTX_BASE 0x19194 9491 #define A_ULP_RX_RQUDP_LLIMIT 0x191a4 9492 #define A_ULP_RX_RQUDP_ULIMIT 0x191a8 9493 #define A_ULP_RX_SE_CNT_CH0 0x191d8 9494 9495 #define S_SOP_CNT_OUT0 28 9496 #define M_SOP_CNT_OUT0 0xfU 9497 #define V_SOP_CNT_OUT0(x) ((x) << S_SOP_CNT_OUT0) 9498 #define G_SOP_CNT_OUT0(x) (((x) >> S_SOP_CNT_OUT0) & M_SOP_CNT_OUT0) 9499 9500 #define S_EOP_CNT_OUT0 24 9501 #define M_EOP_CNT_OUT0 0xfU 9502 #define V_EOP_CNT_OUT0(x) ((x) << S_EOP_CNT_OUT0) 9503 #define G_EOP_CNT_OUT0(x) (((x) >> S_EOP_CNT_OUT0) & M_EOP_CNT_OUT0) 9504 9505 #define S_SOP_CNT_AL0 20 9506 #define M_SOP_CNT_AL0 0xfU 9507 #define V_SOP_CNT_AL0(x) ((x) << S_SOP_CNT_AL0) 9508 #define G_SOP_CNT_AL0(x) (((x) >> S_SOP_CNT_AL0) & M_SOP_CNT_AL0) 9509 9510 #define S_EOP_CNT_AL0 16 9511 #define M_EOP_CNT_AL0 0xfU 9512 #define V_EOP_CNT_AL0(x) ((x) << S_EOP_CNT_AL0) 9513 #define G_EOP_CNT_AL0(x) (((x) >> S_EOP_CNT_AL0) & M_EOP_CNT_AL0) 9514 9515 #define S_SOP_CNT_MR0 12 9516 #define M_SOP_CNT_MR0 0xfU 9517 #define V_SOP_CNT_MR0(x) ((x) << S_SOP_CNT_MR0) 9518 #define G_SOP_CNT_MR0(x) (((x) >> S_SOP_CNT_MR0) & M_SOP_CNT_MR0) 9519 9520 #define S_EOP_CNT_MR0 8 9521 #define M_EOP_CNT_MR0 0xfU 9522 #define V_EOP_CNT_MR0(x) ((x) << S_EOP_CNT_MR0) 9523 #define G_EOP_CNT_MR0(x) (((x) >> S_EOP_CNT_MR0) & M_EOP_CNT_MR0) 9524 9525 #define S_SOP_CNT_IN0 4 9526 #define M_SOP_CNT_IN0 0xfU 9527 #define V_SOP_CNT_IN0(x) ((x) << S_SOP_CNT_IN0) 9528 #define G_SOP_CNT_IN0(x) (((x) >> S_SOP_CNT_IN0) & M_SOP_CNT_IN0) 9529 9530 #define S_EOP_CNT_IN0 0 9531 #define M_EOP_CNT_IN0 0xfU 9532 #define V_EOP_CNT_IN0(x) ((x) << S_EOP_CNT_IN0) 9533 #define G_EOP_CNT_IN0(x) (((x) >> S_EOP_CNT_IN0) & M_EOP_CNT_IN0) 9534 9535 #define A_ULP_RX_SE_CNT_CH1 0x191dc 9536 9537 #define S_SOP_CNT_OUT1 28 9538 #define M_SOP_CNT_OUT1 0xfU 9539 #define V_SOP_CNT_OUT1(x) ((x) << S_SOP_CNT_OUT1) 9540 #define G_SOP_CNT_OUT1(x) (((x) >> S_SOP_CNT_OUT1) & M_SOP_CNT_OUT1) 9541 9542 #define S_EOP_CNT_OUT1 24 9543 #define M_EOP_CNT_OUT1 0xfU 9544 #define V_EOP_CNT_OUT1(x) ((x) << S_EOP_CNT_OUT1) 9545 #define G_EOP_CNT_OUT1(x) (((x) >> S_EOP_CNT_OUT1) & M_EOP_CNT_OUT1) 9546 9547 #define S_SOP_CNT_AL1 20 9548 #define M_SOP_CNT_AL1 0xfU 9549 #define V_SOP_CNT_AL1(x) ((x) << S_SOP_CNT_AL1) 9550 #define G_SOP_CNT_AL1(x) (((x) >> S_SOP_CNT_AL1) & M_SOP_CNT_AL1) 9551 9552 #define S_EOP_CNT_AL1 16 9553 #define M_EOP_CNT_AL1 0xfU 9554 #define V_EOP_CNT_AL1(x) ((x) << S_EOP_CNT_AL1) 9555 #define G_EOP_CNT_AL1(x) (((x) >> S_EOP_CNT_AL1) & M_EOP_CNT_AL1) 9556 9557 #define S_SOP_CNT_MR1 12 9558 #define M_SOP_CNT_MR1 0xfU 9559 #define V_SOP_CNT_MR1(x) ((x) << S_SOP_CNT_MR1) 9560 #define G_SOP_CNT_MR1(x) (((x) >> S_SOP_CNT_MR1) & M_SOP_CNT_MR1) 9561 9562 #define S_EOP_CNT_MR1 8 9563 #define M_EOP_CNT_MR1 0xfU 9564 #define V_EOP_CNT_MR1(x) ((x) << S_EOP_CNT_MR1) 9565 #define G_EOP_CNT_MR1(x) (((x) >> S_EOP_CNT_MR1) & M_EOP_CNT_MR1) 9566 9567 #define S_SOP_CNT_IN1 4 9568 #define M_SOP_CNT_IN1 0xfU 9569 #define V_SOP_CNT_IN1(x) ((x) << S_SOP_CNT_IN1) 9570 #define G_SOP_CNT_IN1(x) (((x) >> S_SOP_CNT_IN1) & M_SOP_CNT_IN1) 9571 9572 #define S_EOP_CNT_IN1 0 9573 #define M_EOP_CNT_IN1 0xfU 9574 #define V_EOP_CNT_IN1(x) ((x) << S_EOP_CNT_IN1) 9575 #define G_EOP_CNT_IN1(x) (((x) >> S_EOP_CNT_IN1) & M_EOP_CNT_IN1) 9576 9577 #define A_ULP_RX_LA_CTL 0x1923c 9578 9579 #define S_TRC_SEL 0 9580 #define V_TRC_SEL(x) ((x) << S_TRC_SEL) 9581 #define F_TRC_SEL V_TRC_SEL(1U) 9582 9583 #define A_ULP_RX_LA_RDPTR 0x19240 9584 9585 #define S_RD_PTR 0 9586 #define M_RD_PTR 0x1ffU 9587 #define V_RD_PTR(x) ((x) << S_RD_PTR) 9588 #define G_RD_PTR(x) (((x) >> S_RD_PTR) & M_RD_PTR) 9589 9590 #define A_ULP_RX_LA_RDDATA 0x19244 9591 #define A_ULP_RX_LA_WRPTR 0x19248 9592 9593 #define S_WR_PTR 0 9594 #define M_WR_PTR 0x1ffU 9595 #define V_WR_PTR(x) ((x) << S_WR_PTR) 9596 #define G_WR_PTR(x) (((x) >> S_WR_PTR) & M_WR_PTR) 9597 9598 #define A_ULP_RX_LA_RESERVED 0x1924c 9599 #define A_ULP_RX_INT_CAUSE_2 0x19270 9600 9601 #define S_ULPRX2MA_INTFPERR 8 9602 #define V_ULPRX2MA_INTFPERR(x) ((x) << S_ULPRX2MA_INTFPERR) 9603 #define F_ULPRX2MA_INTFPERR V_ULPRX2MA_INTFPERR(1U) 9604 9605 #define S_ALN_SDC_ERR_1 7 9606 #define V_ALN_SDC_ERR_1(x) ((x) << S_ALN_SDC_ERR_1) 9607 #define F_ALN_SDC_ERR_1 V_ALN_SDC_ERR_1(1U) 9608 9609 #define S_ALN_SDC_ERR_0 6 9610 #define V_ALN_SDC_ERR_0(x) ((x) << S_ALN_SDC_ERR_0) 9611 #define F_ALN_SDC_ERR_0 V_ALN_SDC_ERR_0(1U) 9612 9613 #define S_PF_UNTAGGED_TPT_1 5 9614 #define V_PF_UNTAGGED_TPT_1(x) ((x) << S_PF_UNTAGGED_TPT_1) 9615 #define F_PF_UNTAGGED_TPT_1 V_PF_UNTAGGED_TPT_1(1U) 9616 9617 #define S_PF_UNTAGGED_TPT_0 4 9618 #define V_PF_UNTAGGED_TPT_0(x) ((x) << S_PF_UNTAGGED_TPT_0) 9619 #define F_PF_UNTAGGED_TPT_0 V_PF_UNTAGGED_TPT_0(1U) 9620 9621 #define S_PF_PBL_1 3 9622 #define V_PF_PBL_1(x) ((x) << S_PF_PBL_1) 9623 #define F_PF_PBL_1 V_PF_PBL_1(1U) 9624 9625 #define S_PF_PBL_0 2 9626 #define V_PF_PBL_0(x) ((x) << S_PF_PBL_0) 9627 #define F_PF_PBL_0 V_PF_PBL_0(1U) 9628 9629 #define S_DDP_HINT_1 1 9630 #define V_DDP_HINT_1(x) ((x) << S_DDP_HINT_1) 9631 #define F_DDP_HINT_1 V_DDP_HINT_1(1U) 9632 9633 #define S_DDP_HINT_0 0 9634 #define V_DDP_HINT_0(x) ((x) << S_DDP_HINT_0) 9635 #define F_DDP_HINT_0 V_DDP_HINT_0(1U) 9636 9637 #define A_ULP_RX_TLS_PP_LLIMIT 0x192a4 9638 9639 #define S_TLSPPLLIMIT 6 9640 #define M_TLSPPLLIMIT 0x3ffffffU 9641 #define V_TLSPPLLIMIT(x) ((x) << S_TLSPPLLIMIT) 9642 #define G_TLSPPLLIMIT(x) (((x) >> S_TLSPPLLIMIT) & M_TLSPPLLIMIT) 9643 9644 #define A_ULP_RX_TLS_PP_ULIMIT 0x192a8 9645 9646 #define S_TLSPPULIMIT 6 9647 #define M_TLSPPULIMIT 0x3ffffffU 9648 #define V_TLSPPULIMIT(x) ((x) << S_TLSPPULIMIT) 9649 #define G_TLSPPULIMIT(x) (((x) >> S_TLSPPULIMIT) & M_TLSPPULIMIT) 9650 9651 #define A_ULP_RX_TLS_KEY_LLIMIT 0x192ac 9652 9653 #define S_TLSKEYLLIMIT 8 9654 #define M_TLSKEYLLIMIT 0xffffffU 9655 #define V_TLSKEYLLIMIT(x) ((x) << S_TLSKEYLLIMIT) 9656 #define G_TLSKEYLLIMIT(x) (((x) >> S_TLSKEYLLIMIT) & M_TLSKEYLLIMIT) 9657 9658 #define A_ULP_RX_TLS_KEY_ULIMIT 0x192b0 9659 9660 #define S_TLSKEYULIMIT 8 9661 #define M_TLSKEYULIMIT 0xffffffU 9662 #define V_TLSKEYULIMIT(x) ((x) << S_TLSKEYULIMIT) 9663 #define G_TLSKEYULIMIT(x) (((x) >> S_TLSKEYULIMIT) & M_TLSKEYULIMIT) 9664 9665 9666 /* registers for module SF */ 9667 #define SF_BASE_ADDR 0x193f8 9668 9669 #define A_SF_DATA 0x193f8 9670 #define A_SF_OP 0x193fc 9671 9672 #define S_SF_LOCK 4 9673 #define V_SF_LOCK(x) ((x) << S_SF_LOCK) 9674 #define F_SF_LOCK V_SF_LOCK(1U) 9675 9676 #define S_CONT 3 9677 #define V_CONT(x) ((x) << S_CONT) 9678 #define F_CONT V_CONT(1U) 9679 9680 #define S_BYTECNT 1 9681 #define M_BYTECNT 0x3U 9682 #define V_BYTECNT(x) ((x) << S_BYTECNT) 9683 #define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT) 9684 9685 #define S_OP 0 9686 #define V_OP(x) ((x) << S_OP) 9687 #define F_OP V_OP(1U) 9688 9689 /* registers for module PL */ 9690 #define PL_BASE_ADDR 0x19400 9691 9692 #define A_PL_VF_WHOAMI 0x0 9693 9694 #define S_PORTXMAP 24 9695 #define M_PORTXMAP 0x7U 9696 #define V_PORTXMAP(x) ((x) << S_PORTXMAP) 9697 #define G_PORTXMAP(x) (((x) >> S_PORTXMAP) & M_PORTXMAP) 9698 9699 #define S_SOURCEBUS 16 9700 #define M_SOURCEBUS 0x3U 9701 #define V_SOURCEBUS(x) ((x) << S_SOURCEBUS) 9702 #define G_SOURCEBUS(x) (((x) >> S_SOURCEBUS) & M_SOURCEBUS) 9703 9704 #define S_SOURCEPF 8 9705 #define M_SOURCEPF 0x7U 9706 #define V_SOURCEPF(x) ((x) << S_SOURCEPF) 9707 #define G_SOURCEPF(x) (((x) >> S_SOURCEPF) & M_SOURCEPF) 9708 9709 #define S_ISVF 7 9710 #define V_ISVF(x) ((x) << S_ISVF) 9711 #define F_ISVF V_ISVF(1U) 9712 9713 #define S_VFID 0 9714 #define M_VFID 0x7fU 9715 #define V_VFID(x) ((x) << S_VFID) 9716 #define G_VFID(x) (((x) >> S_VFID) & M_VFID) 9717 9718 #define S_T6_SOURCEPF 9 9719 #define M_T6_SOURCEPF 0x7U 9720 #define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF) 9721 #define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF) 9722 9723 #define S_T6_ISVF 8 9724 #define V_T6_ISVF(x) ((x) << S_T6_ISVF) 9725 #define F_T6_ISVF V_T6_ISVF(1U) 9726 9727 #define S_T6_VFID 0 9728 #define M_T6_VFID 0xffU 9729 #define V_T6_VFID(x) ((x) << S_T6_VFID) 9730 #define G_T6_VFID(x) (((x) >> S_T6_VFID) & M_T6_VFID) 9731 9732 #define A_PL_VF_REV 0x4 9733 9734 #define S_CHIPID 4 9735 #define M_CHIPID 0xfU 9736 #define V_CHIPID(x) ((x) << S_CHIPID) 9737 #define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID) 9738 9739 #define A_PL_VF_REVISION 0x8 9740 #define A_PL_PF_INT_CAUSE 0x3c0 9741 #define A_PL_PF_INT_ENABLE 0x3c4 9742 9743 #define S_PFSW 3 9744 #define V_PFSW(x) ((x) << S_PFSW) 9745 #define F_PFSW V_PFSW(1U) 9746 9747 #define S_PFSGE 2 9748 #define V_PFSGE(x) ((x) << S_PFSGE) 9749 #define F_PFSGE V_PFSGE(1U) 9750 9751 #define S_PFCIM 1 9752 #define V_PFCIM(x) ((x) << S_PFCIM) 9753 #define F_PFCIM V_PFCIM(1U) 9754 9755 #define S_PFMPS 0 9756 #define V_PFMPS(x) ((x) << S_PFMPS) 9757 #define F_PFMPS V_PFMPS(1U) 9758 9759 #define A_PL_PF_CTL 0x3c8 9760 9761 #define S_SWINT 0 9762 #define V_SWINT(x) ((x) << S_SWINT) 9763 #define F_SWINT V_SWINT(1U) 9764 9765 #define A_PL_WHOAMI 0x19400 9766 9767 #define S_T6_SOURCEPF 9 9768 #define M_T6_SOURCEPF 0x7U 9769 #define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF) 9770 #define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF) 9771 9772 #define S_T6_ISVF 8 9773 #define V_T6_ISVF(x) ((x) << S_T6_ISVF) 9774 #define F_T6_ISVF V_T6_ISVF(1U) 9775 9776 #define S_T6_VFID 0 9777 #define M_T6_VFID 0xffU 9778 #define V_T6_VFID(x) ((x) << S_T6_VFID) 9779 #define G_T6_VFID(x) (((x) >> S_T6_VFID) & M_T6_VFID) 9780 9781 #define A_PL_INT_CAUSE 0x1940c 9782 9783 #define S_MC1 31 9784 #define V_MC1(x) ((x) << S_MC1) 9785 #define F_MC1 V_MC1(1U) 9786 9787 #define S_MAC3 12 9788 #define V_MAC3(x) ((x) << S_MAC3) 9789 #define F_MAC3 V_MAC3(1U) 9790 9791 #define S_MAC2 11 9792 #define V_MAC2(x) ((x) << S_MAC2) 9793 #define F_MAC2 V_MAC2(1U) 9794 9795 #define S_FLR 30 9796 #define V_FLR(x) ((x) << S_FLR) 9797 #define F_FLR V_FLR(1U) 9798 9799 #define S_SW_CIM 29 9800 #define V_SW_CIM(x) ((x) << S_SW_CIM) 9801 #define F_SW_CIM V_SW_CIM(1U) 9802 9803 #define S_UART 28 9804 #define V_UART(x) ((x) << S_UART) 9805 #define F_UART V_UART(1U) 9806 9807 #define S_ULP_TX 27 9808 #define V_ULP_TX(x) ((x) << S_ULP_TX) 9809 #define F_ULP_TX V_ULP_TX(1U) 9810 9811 #define S_SGE 26 9812 #define V_SGE(x) ((x) << S_SGE) 9813 #define F_SGE V_SGE(1U) 9814 9815 #define S_HMA 25 9816 #define V_HMA(x) ((x) << S_HMA) 9817 #define F_HMA V_HMA(1U) 9818 9819 #define S_CPL_SWITCH 24 9820 #define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH) 9821 #define F_CPL_SWITCH V_CPL_SWITCH(1U) 9822 9823 #define S_ULP_RX 23 9824 #define V_ULP_RX(x) ((x) << S_ULP_RX) 9825 #define F_ULP_RX V_ULP_RX(1U) 9826 9827 #define S_PM_RX 22 9828 #define V_PM_RX(x) ((x) << S_PM_RX) 9829 #define F_PM_RX V_PM_RX(1U) 9830 9831 #define S_PM_TX 21 9832 #define V_PM_TX(x) ((x) << S_PM_TX) 9833 #define F_PM_TX V_PM_TX(1U) 9834 9835 #define S_MA 20 9836 #define V_MA(x) ((x) << S_MA) 9837 #define F_MA V_MA(1U) 9838 9839 #define S_TP 19 9840 #define V_TP(x) ((x) << S_TP) 9841 #define F_TP V_TP(1U) 9842 9843 #define S_LE 18 9844 #define V_LE(x) ((x) << S_LE) 9845 #define F_LE V_LE(1U) 9846 9847 #define S_EDC1 17 9848 #define V_EDC1(x) ((x) << S_EDC1) 9849 #define F_EDC1 V_EDC1(1U) 9850 9851 #define S_EDC0 16 9852 #define V_EDC0(x) ((x) << S_EDC0) 9853 #define F_EDC0 V_EDC0(1U) 9854 9855 #define S_MC0 15 9856 #define V_MC0(x) ((x) << S_MC0) 9857 #define F_MC0 V_MC0(1U) 9858 9859 #define S_PCIE 14 9860 #define V_PCIE(x) ((x) << S_PCIE) 9861 #define F_PCIE V_PCIE(1U) 9862 9863 #define S_PMU 13 9864 #define V_PMU(x) ((x) << S_PMU) 9865 #define F_PMU V_PMU(1U) 9866 9867 #define S_MAC1 10 9868 #define V_MAC1(x) ((x) << S_MAC1) 9869 #define F_MAC1 V_MAC1(1U) 9870 9871 #define S_MAC0 9 9872 #define V_MAC0(x) ((x) << S_MAC0) 9873 #define F_MAC0 V_MAC0(1U) 9874 9875 #define S_SMB 8 9876 #define V_SMB(x) ((x) << S_SMB) 9877 #define F_SMB V_SMB(1U) 9878 9879 #define S_PL 6 9880 #define V_PL(x) ((x) << S_PL) 9881 #define F_PL V_PL(1U) 9882 9883 #define S_NCSI 5 9884 #define V_NCSI(x) ((x) << S_NCSI) 9885 #define F_NCSI V_NCSI(1U) 9886 9887 #define S_MPS 4 9888 #define V_MPS(x) ((x) << S_MPS) 9889 #define F_MPS V_MPS(1U) 9890 9891 #define S_MI 3 9892 #define V_MI(x) ((x) << S_MI) 9893 #define F_MI V_MI(1U) 9894 9895 #define S_DBG 2 9896 #define V_DBG(x) ((x) << S_DBG) 9897 #define F_DBG V_DBG(1U) 9898 9899 #define S_I2CM 1 9900 #define V_I2CM(x) ((x) << S_I2CM) 9901 #define F_I2CM V_I2CM(1U) 9902 9903 #define S_CIM 0 9904 #define V_CIM(x) ((x) << S_CIM) 9905 #define F_CIM V_CIM(1U) 9906 9907 #define A_PL_INT_ENABLE 0x19410 9908 9909 #define S_SF 7 9910 #define V_SF(x) ((x) << S_SF) 9911 #define F_SF V_SF(1U) 9912 9913 #define A_PL_INT_MAP0 0x19414 9914 9915 #define S_MAPNCSI 16 9916 #define M_MAPNCSI 0x1ffU 9917 #define V_MAPNCSI(x) ((x) << S_MAPNCSI) 9918 #define G_MAPNCSI(x) (((x) >> S_MAPNCSI) & M_MAPNCSI) 9919 9920 #define S_MAPDEFAULT 0 9921 #define M_MAPDEFAULT 0x1ffU 9922 #define V_MAPDEFAULT(x) ((x) << S_MAPDEFAULT) 9923 #define G_MAPDEFAULT(x) (((x) >> S_MAPDEFAULT) & M_MAPDEFAULT) 9924 9925 #define A_PL_RST 0x19428 9926 9927 #define S_FATALPERREN 3 9928 #define V_FATALPERREN(x) ((x) << S_FATALPERREN) 9929 #define F_FATALPERREN V_FATALPERREN(1U) 9930 9931 #define S_SWINTCIM 2 9932 #define V_SWINTCIM(x) ((x) << S_SWINTCIM) 9933 #define F_SWINTCIM V_SWINTCIM(1U) 9934 9935 #define S_PIORST 1 9936 #define V_PIORST(x) ((x) << S_PIORST) 9937 #define F_PIORST V_PIORST(1U) 9938 9939 #define S_PIORSTMODE 0 9940 #define V_PIORSTMODE(x) ((x) << S_PIORSTMODE) 9941 #define F_PIORSTMODE V_PIORSTMODE(1U) 9942 9943 #define S_AUTOPCIEPAUSE 4 9944 #define V_AUTOPCIEPAUSE(x) ((x) << S_AUTOPCIEPAUSE) 9945 #define F_AUTOPCIEPAUSE V_AUTOPCIEPAUSE(1U) 9946 9947 #define A_PL_PL_INT_CAUSE 0x19430 9948 9949 #define S_PF_ENABLEERR 5 9950 #define V_PF_ENABLEERR(x) ((x) << S_PF_ENABLEERR) 9951 #define F_PF_ENABLEERR V_PF_ENABLEERR(1U) 9952 9953 #define S_FATALPERR 4 9954 #define V_FATALPERR(x) ((x) << S_FATALPERR) 9955 #define F_FATALPERR V_FATALPERR(1U) 9956 9957 #define S_INVALIDACCESS 3 9958 #define V_INVALIDACCESS(x) ((x) << S_INVALIDACCESS) 9959 #define F_INVALIDACCESS V_INVALIDACCESS(1U) 9960 9961 #define S_TIMEOUT 2 9962 #define V_TIMEOUT(x) ((x) << S_TIMEOUT) 9963 #define F_TIMEOUT V_TIMEOUT(1U) 9964 9965 #define S_PLERR 1 9966 #define V_PLERR(x) ((x) << S_PLERR) 9967 #define F_PLERR V_PLERR(1U) 9968 9969 #define S_PERRVFID 0 9970 #define V_PERRVFID(x) ((x) << S_PERRVFID) 9971 #define F_PERRVFID V_PERRVFID(1U) 9972 9973 #define S_PL_BUSPERR 6 9974 #define V_PL_BUSPERR(x) ((x) << S_PL_BUSPERR) 9975 #define F_PL_BUSPERR V_PL_BUSPERR(1U) 9976 9977 #define A_PL_PL_INT_ENABLE 0x19434 9978 #define A_PL_PL_PERR_ENABLE 0x19438 9979 #define A_PL_REV 0x1943c 9980 9981 #define S_REV 0 9982 #define M_REV 0xfU 9983 #define V_REV(x) ((x) << S_REV) 9984 #define G_REV(x) (((x) >> S_REV) & M_REV) 9985 9986 #define A_PL_TIMEOUT_STATUS1 0x194f8 9987 9988 #define S_PL_TORID 0 9989 #define M_PL_TORID 0xffffU 9990 #define V_PL_TORID(x) ((x) << S_PL_TORID) 9991 #define G_PL_TORID(x) (((x) >> S_PL_TORID) & M_PL_TORID) 9992 9993 #define S_PL_TOVFID 0 9994 #define M_PL_TOVFID 0xffU 9995 #define V_PL_TOVFID(x) ((x) << S_PL_TOVFID) 9996 #define G_PL_TOVFID(x) (((x) >> S_PL_TOVFID) & M_PL_TOVFID) 9997 9998 #define S_T6_PL_TOVFID 0 9999 #define M_T6_PL_TOVFID 0x1ffU 10000 #define V_T6_PL_TOVFID(x) ((x) << S_T6_PL_TOVFID) 10001 #define G_T6_PL_TOVFID(x) (((x) >> S_T6_PL_TOVFID) & M_T6_PL_TOVFID) 10002 10003 10004 /* registers for module LE */ 10005 #define LE_BASE_ADDR 0x19c00 10006 10007 #define A_LE_DB_CONFIG 0x19c04 10008 10009 #define S_TCAMCMDOVLAPEN 21 10010 #define V_TCAMCMDOVLAPEN(x) ((x) << S_TCAMCMDOVLAPEN) 10011 #define F_TCAMCMDOVLAPEN V_TCAMCMDOVLAPEN(1U) 10012 10013 #define S_HASHEN 20 10014 #define V_HASHEN(x) ((x) << S_HASHEN) 10015 #define F_HASHEN V_HASHEN(1U) 10016 10017 #define S_ASBOTHSRCHEN 18 10018 #define V_ASBOTHSRCHEN(x) ((x) << S_ASBOTHSRCHEN) 10019 #define F_ASBOTHSRCHEN V_ASBOTHSRCHEN(1U) 10020 10021 #define S_ASLIPCOMPEN 17 10022 #define V_ASLIPCOMPEN(x) ((x) << S_ASLIPCOMPEN) 10023 #define F_ASLIPCOMPEN V_ASLIPCOMPEN(1U) 10024 10025 #define S_BUILD 16 10026 #define V_BUILD(x) ((x) << S_BUILD) 10027 #define F_BUILD V_BUILD(1U) 10028 10029 #define S_FILTEREN 11 10030 #define V_FILTEREN(x) ((x) << S_FILTEREN) 10031 #define F_FILTEREN V_FILTEREN(1U) 10032 10033 #define S_SYNMODE 7 10034 #define M_SYNMODE 0x3U 10035 #define V_SYNMODE(x) ((x) << S_SYNMODE) 10036 #define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE) 10037 10038 #define S_LEBUSEN 5 10039 #define V_LEBUSEN(x) ((x) << S_LEBUSEN) 10040 #define F_LEBUSEN V_LEBUSEN(1U) 10041 10042 #define S_ELOOKDUMEN 4 10043 #define V_ELOOKDUMEN(x) ((x) << S_ELOOKDUMEN) 10044 #define F_ELOOKDUMEN V_ELOOKDUMEN(1U) 10045 10046 #define S_IPV4ONLYEN 3 10047 #define V_IPV4ONLYEN(x) ((x) << S_IPV4ONLYEN) 10048 #define F_IPV4ONLYEN V_IPV4ONLYEN(1U) 10049 10050 #define S_MOSTCMDOEN 2 10051 #define V_MOSTCMDOEN(x) ((x) << S_MOSTCMDOEN) 10052 #define F_MOSTCMDOEN V_MOSTCMDOEN(1U) 10053 10054 #define S_DELACTSYNOEN 1 10055 #define V_DELACTSYNOEN(x) ((x) << S_DELACTSYNOEN) 10056 #define F_DELACTSYNOEN V_DELACTSYNOEN(1U) 10057 10058 #define S_CMDOVERLAPDIS 0 10059 #define V_CMDOVERLAPDIS(x) ((x) << S_CMDOVERLAPDIS) 10060 #define F_CMDOVERLAPDIS V_CMDOVERLAPDIS(1U) 10061 10062 #define S_MASKCMDOLAPDIS 26 10063 #define V_MASKCMDOLAPDIS(x) ((x) << S_MASKCMDOLAPDIS) 10064 #define F_MASKCMDOLAPDIS V_MASKCMDOLAPDIS(1U) 10065 10066 #define S_IPV4HASHSIZEEN 25 10067 #define V_IPV4HASHSIZEEN(x) ((x) << S_IPV4HASHSIZEEN) 10068 #define F_IPV4HASHSIZEEN V_IPV4HASHSIZEEN(1U) 10069 10070 #define S_PROTOCOLMASKEN 24 10071 #define V_PROTOCOLMASKEN(x) ((x) << S_PROTOCOLMASKEN) 10072 #define F_PROTOCOLMASKEN V_PROTOCOLMASKEN(1U) 10073 10074 #define S_TUPLESIZEEN 23 10075 #define V_TUPLESIZEEN(x) ((x) << S_TUPLESIZEEN) 10076 #define F_TUPLESIZEEN V_TUPLESIZEEN(1U) 10077 10078 #define S_SRVRSRAMEN 22 10079 #define V_SRVRSRAMEN(x) ((x) << S_SRVRSRAMEN) 10080 #define F_SRVRSRAMEN V_SRVRSRAMEN(1U) 10081 10082 #define S_ASBOTHSRCHENPR 19 10083 #define V_ASBOTHSRCHENPR(x) ((x) << S_ASBOTHSRCHENPR) 10084 #define F_ASBOTHSRCHENPR V_ASBOTHSRCHENPR(1U) 10085 10086 #define S_POCLIPTID0 15 10087 #define V_POCLIPTID0(x) ((x) << S_POCLIPTID0) 10088 #define F_POCLIPTID0 V_POCLIPTID0(1U) 10089 10090 #define S_TCAMARBOFF 14 10091 #define V_TCAMARBOFF(x) ((x) << S_TCAMARBOFF) 10092 #define F_TCAMARBOFF V_TCAMARBOFF(1U) 10093 10094 #define S_ACCNTFULLEN 13 10095 #define V_ACCNTFULLEN(x) ((x) << S_ACCNTFULLEN) 10096 #define F_ACCNTFULLEN V_ACCNTFULLEN(1U) 10097 10098 #define S_FILTERRWNOCLIP 12 10099 #define V_FILTERRWNOCLIP(x) ((x) << S_FILTERRWNOCLIP) 10100 #define F_FILTERRWNOCLIP V_FILTERRWNOCLIP(1U) 10101 10102 #define S_CRCHASH 10 10103 #define V_CRCHASH(x) ((x) << S_CRCHASH) 10104 #define F_CRCHASH V_CRCHASH(1U) 10105 10106 #define S_COMPTID 9 10107 #define V_COMPTID(x) ((x) << S_COMPTID) 10108 #define F_COMPTID V_COMPTID(1U) 10109 10110 #define S_SINGLETHREAD 6 10111 #define V_SINGLETHREAD(x) ((x) << S_SINGLETHREAD) 10112 #define F_SINGLETHREAD V_SINGLETHREAD(1U) 10113 10114 #define S_CHK_FUL_TUP_ZERO 27 10115 #define V_CHK_FUL_TUP_ZERO(x) ((x) << S_CHK_FUL_TUP_ZERO) 10116 #define F_CHK_FUL_TUP_ZERO V_CHK_FUL_TUP_ZERO(1U) 10117 10118 #define S_PRI_HASH 26 10119 #define V_PRI_HASH(x) ((x) << S_PRI_HASH) 10120 #define F_PRI_HASH V_PRI_HASH(1U) 10121 10122 #define S_EXTN_HASH_IPV4 25 10123 #define V_EXTN_HASH_IPV4(x) ((x) << S_EXTN_HASH_IPV4) 10124 #define F_EXTN_HASH_IPV4 V_EXTN_HASH_IPV4(1U) 10125 10126 #define S_ASLIPCOMPEN_IPV4 18 10127 #define V_ASLIPCOMPEN_IPV4(x) ((x) << S_ASLIPCOMPEN_IPV4) 10128 #define F_ASLIPCOMPEN_IPV4 V_ASLIPCOMPEN_IPV4(1U) 10129 10130 #define S_IGNR_TUP_ZERO 9 10131 #define V_IGNR_TUP_ZERO(x) ((x) << S_IGNR_TUP_ZERO) 10132 #define F_IGNR_TUP_ZERO V_IGNR_TUP_ZERO(1U) 10133 10134 #define S_IGNR_LIP_ZERO 8 10135 #define V_IGNR_LIP_ZERO(x) ((x) << S_IGNR_LIP_ZERO) 10136 #define F_IGNR_LIP_ZERO V_IGNR_LIP_ZERO(1U) 10137 10138 #define S_CLCAM_INIT_BUSY 7 10139 #define V_CLCAM_INIT_BUSY(x) ((x) << S_CLCAM_INIT_BUSY) 10140 #define F_CLCAM_INIT_BUSY V_CLCAM_INIT_BUSY(1U) 10141 10142 #define S_CLCAM_INIT 6 10143 #define V_CLCAM_INIT(x) ((x) << S_CLCAM_INIT) 10144 #define F_CLCAM_INIT V_CLCAM_INIT(1U) 10145 10146 #define S_MTCAM_INIT_BUSY 5 10147 #define V_MTCAM_INIT_BUSY(x) ((x) << S_MTCAM_INIT_BUSY) 10148 #define F_MTCAM_INIT_BUSY V_MTCAM_INIT_BUSY(1U) 10149 10150 #define S_MTCAM_INIT 4 10151 #define V_MTCAM_INIT(x) ((x) << S_MTCAM_INIT) 10152 #define F_MTCAM_INIT V_MTCAM_INIT(1U) 10153 10154 #define S_REGION_EN 0 10155 #define M_REGION_EN 0xfU 10156 #define V_REGION_EN(x) ((x) << S_REGION_EN) 10157 #define G_REGION_EN(x) (((x) >> S_REGION_EN) & M_REGION_EN) 10158 10159 #define A_LE_DB_ROUTING_TABLE_INDEX 0x19c10 10160 10161 #define S_RTINDX 7 10162 #define M_RTINDX 0x3fU 10163 #define V_RTINDX(x) ((x) << S_RTINDX) 10164 #define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX) 10165 10166 #define A_LE_DB_ACTIVE_TABLE_START_INDEX 0x19c10 10167 10168 #define S_ATINDX 0 10169 #define M_ATINDX 0xfffffU 10170 #define V_ATINDX(x) ((x) << S_ATINDX) 10171 #define G_ATINDX(x) (((x) >> S_ATINDX) & M_ATINDX) 10172 10173 #define A_LE_DB_FILTER_TABLE_INDEX 0x19c14 10174 10175 #define S_FTINDX 7 10176 #define M_FTINDX 0x3fU 10177 #define V_FTINDX(x) ((x) << S_FTINDX) 10178 #define G_FTINDX(x) (((x) >> S_FTINDX) & M_FTINDX) 10179 10180 #define A_LE_DB_NORM_FILT_TABLE_START_INDEX 0x19c14 10181 10182 #define S_NFTINDX 0 10183 #define M_NFTINDX 0xfffffU 10184 #define V_NFTINDX(x) ((x) << S_NFTINDX) 10185 #define G_NFTINDX(x) (((x) >> S_NFTINDX) & M_NFTINDX) 10186 10187 #define A_LE_DB_SERVER_INDEX 0x19c18 10188 10189 #define S_SRINDX 7 10190 #define M_SRINDX 0x3fU 10191 #define V_SRINDX(x) ((x) << S_SRINDX) 10192 #define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX) 10193 10194 #define A_LE_DB_SRVR_START_INDEX 0x19c18 10195 10196 #define S_T6_SRINDX 0 10197 #define M_T6_SRINDX 0xfffffU 10198 #define V_T6_SRINDX(x) ((x) << S_T6_SRINDX) 10199 #define G_T6_SRINDX(x) (((x) >> S_T6_SRINDX) & M_T6_SRINDX) 10200 10201 #define A_LE_DB_CLIP_TABLE_INDEX 0x19c1c 10202 10203 #define S_CLIPTINDX 7 10204 #define M_CLIPTINDX 0x3fU 10205 #define V_CLIPTINDX(x) ((x) << S_CLIPTINDX) 10206 #define G_CLIPTINDX(x) (((x) >> S_CLIPTINDX) & M_CLIPTINDX) 10207 10208 #define A_LE_DB_HPRI_FILT_TABLE_START_INDEX 0x19c1c 10209 10210 #define S_HFTINDX 0 10211 #define M_HFTINDX 0xfffffU 10212 #define V_HFTINDX(x) ((x) << S_HFTINDX) 10213 #define G_HFTINDX(x) (((x) >> S_HFTINDX) & M_HFTINDX) 10214 10215 #define A_LE_DB_ACT_CNT_IPV4 0x19c20 10216 10217 #define S_ACTCNTIPV4 0 10218 #define M_ACTCNTIPV4 0xfffffU 10219 #define V_ACTCNTIPV4(x) ((x) << S_ACTCNTIPV4) 10220 #define G_ACTCNTIPV4(x) (((x) >> S_ACTCNTIPV4) & M_ACTCNTIPV4) 10221 10222 #define A_LE_DB_ACT_CNT_IPV6 0x19c24 10223 10224 #define S_ACTCNTIPV6 0 10225 #define M_ACTCNTIPV6 0xfffffU 10226 #define V_ACTCNTIPV6(x) ((x) << S_ACTCNTIPV6) 10227 #define G_ACTCNTIPV6(x) (((x) >> S_ACTCNTIPV6) & M_ACTCNTIPV6) 10228 10229 #define A_LE_DB_HASH_CONFIG 0x19c28 10230 10231 #define S_HASHTIDSIZE 16 10232 #define M_HASHTIDSIZE 0x3fU 10233 #define V_HASHTIDSIZE(x) ((x) << S_HASHTIDSIZE) 10234 #define G_HASHTIDSIZE(x) (((x) >> S_HASHTIDSIZE) & M_HASHTIDSIZE) 10235 10236 #define S_HASHSIZE 0 10237 #define M_HASHSIZE 0x3fU 10238 #define V_HASHSIZE(x) ((x) << S_HASHSIZE) 10239 #define G_HASHSIZE(x) (((x) >> S_HASHSIZE) & M_HASHSIZE) 10240 10241 #define A_LE_DB_HASH_TID_BASE 0x19c30 10242 #define A_LE_DB_HASH_TBL_BASE_ADDR 0x19c30 10243 10244 #define S_HASHTBLADDR 4 10245 #define M_HASHTBLADDR 0xfffffffU 10246 #define V_HASHTBLADDR(x) ((x) << S_HASHTBLADDR) 10247 #define G_HASHTBLADDR(x) (((x) >> S_HASHTBLADDR) & M_HASHTBLADDR) 10248 10249 #define A_LE_DB_INT_ENABLE 0x19c38 10250 10251 #define S_CLIPSUBERR 29 10252 #define V_CLIPSUBERR(x) ((x) << S_CLIPSUBERR) 10253 #define F_CLIPSUBERR V_CLIPSUBERR(1U) 10254 10255 #define S_CLCAMFIFOERR 28 10256 #define V_CLCAMFIFOERR(x) ((x) << S_CLCAMFIFOERR) 10257 #define F_CLCAMFIFOERR V_CLCAMFIFOERR(1U) 10258 10259 #define S_HASHTBLMEMCRCERR 27 10260 #define V_HASHTBLMEMCRCERR(x) ((x) << S_HASHTBLMEMCRCERR) 10261 #define F_HASHTBLMEMCRCERR V_HASHTBLMEMCRCERR(1U) 10262 10263 #define S_CTCAMINVLDENT 26 10264 #define V_CTCAMINVLDENT(x) ((x) << S_CTCAMINVLDENT) 10265 #define F_CTCAMINVLDENT V_CTCAMINVLDENT(1U) 10266 10267 #define S_TCAMINVLDENT 25 10268 #define V_TCAMINVLDENT(x) ((x) << S_TCAMINVLDENT) 10269 #define F_TCAMINVLDENT V_TCAMINVLDENT(1U) 10270 10271 #define S_TOTCNTERR 24 10272 #define V_TOTCNTERR(x) ((x) << S_TOTCNTERR) 10273 #define F_TOTCNTERR V_TOTCNTERR(1U) 10274 10275 #define S_CMDPRSRINTERR 23 10276 #define V_CMDPRSRINTERR(x) ((x) << S_CMDPRSRINTERR) 10277 #define F_CMDPRSRINTERR V_CMDPRSRINTERR(1U) 10278 10279 #define S_CMDTIDERR 22 10280 #define V_CMDTIDERR(x) ((x) << S_CMDTIDERR) 10281 #define F_CMDTIDERR V_CMDTIDERR(1U) 10282 10283 #define S_T6_ACTRGNFULL 21 10284 #define V_T6_ACTRGNFULL(x) ((x) << S_T6_ACTRGNFULL) 10285 #define F_T6_ACTRGNFULL V_T6_ACTRGNFULL(1U) 10286 10287 #define S_T6_ACTCNTIPV6TZERO 20 10288 #define V_T6_ACTCNTIPV6TZERO(x) ((x) << S_T6_ACTCNTIPV6TZERO) 10289 #define F_T6_ACTCNTIPV6TZERO V_T6_ACTCNTIPV6TZERO(1U) 10290 10291 #define S_T6_ACTCNTIPV4TZERO 19 10292 #define V_T6_ACTCNTIPV4TZERO(x) ((x) << S_T6_ACTCNTIPV4TZERO) 10293 #define F_T6_ACTCNTIPV4TZERO V_T6_ACTCNTIPV4TZERO(1U) 10294 10295 #define S_T6_ACTCNTIPV6ZERO 18 10296 #define V_T6_ACTCNTIPV6ZERO(x) ((x) << S_T6_ACTCNTIPV6ZERO) 10297 #define F_T6_ACTCNTIPV6ZERO V_T6_ACTCNTIPV6ZERO(1U) 10298 10299 #define S_T6_ACTCNTIPV4ZERO 17 10300 #define V_T6_ACTCNTIPV4ZERO(x) ((x) << S_T6_ACTCNTIPV4ZERO) 10301 #define F_T6_ACTCNTIPV4ZERO V_T6_ACTCNTIPV4ZERO(1U) 10302 10303 #define S_MAIFWRINTPERR 16 10304 #define V_MAIFWRINTPERR(x) ((x) << S_MAIFWRINTPERR) 10305 #define F_MAIFWRINTPERR V_MAIFWRINTPERR(1U) 10306 10307 #define S_HASHTBLMEMACCERR 15 10308 #define V_HASHTBLMEMACCERR(x) ((x) << S_HASHTBLMEMACCERR) 10309 #define F_HASHTBLMEMACCERR V_HASHTBLMEMACCERR(1U) 10310 10311 #define S_TCAMCRCERR 14 10312 #define V_TCAMCRCERR(x) ((x) << S_TCAMCRCERR) 10313 #define F_TCAMCRCERR V_TCAMCRCERR(1U) 10314 10315 #define S_TCAMINTPERR 13 10316 #define V_TCAMINTPERR(x) ((x) << S_TCAMINTPERR) 10317 #define F_TCAMINTPERR V_TCAMINTPERR(1U) 10318 10319 #define S_VFSRAMPERR 12 10320 #define V_VFSRAMPERR(x) ((x) << S_VFSRAMPERR) 10321 #define F_VFSRAMPERR V_VFSRAMPERR(1U) 10322 10323 #define S_SRVSRAMPERR 11 10324 #define V_SRVSRAMPERR(x) ((x) << S_SRVSRAMPERR) 10325 #define F_SRVSRAMPERR V_SRVSRAMPERR(1U) 10326 10327 #define S_SSRAMINTPERR 10 10328 #define V_SSRAMINTPERR(x) ((x) << S_SSRAMINTPERR) 10329 #define F_SSRAMINTPERR V_SSRAMINTPERR(1U) 10330 10331 #define S_CLCAMINTPERR 9 10332 #define V_CLCAMINTPERR(x) ((x) << S_CLCAMINTPERR) 10333 #define F_CLCAMINTPERR V_CLCAMINTPERR(1U) 10334 10335 #define S_CLCAMCRCPARERR 8 10336 #define V_CLCAMCRCPARERR(x) ((x) << S_CLCAMCRCPARERR) 10337 #define F_CLCAMCRCPARERR V_CLCAMCRCPARERR(1U) 10338 10339 #define S_HASHTBLACCFAIL 7 10340 #define V_HASHTBLACCFAIL(x) ((x) << S_HASHTBLACCFAIL) 10341 #define F_HASHTBLACCFAIL V_HASHTBLACCFAIL(1U) 10342 10343 #define S_TCAMACCFAIL 6 10344 #define V_TCAMACCFAIL(x) ((x) << S_TCAMACCFAIL) 10345 #define F_TCAMACCFAIL V_TCAMACCFAIL(1U) 10346 10347 #define S_SRVSRAMACCFAIL 5 10348 #define V_SRVSRAMACCFAIL(x) ((x) << S_SRVSRAMACCFAIL) 10349 #define F_SRVSRAMACCFAIL V_SRVSRAMACCFAIL(1U) 10350 10351 #define S_CLIPTCAMACCFAIL 4 10352 #define V_CLIPTCAMACCFAIL(x) ((x) << S_CLIPTCAMACCFAIL) 10353 #define F_CLIPTCAMACCFAIL V_CLIPTCAMACCFAIL(1U) 10354 10355 #define S_T6_UNKNOWNCMD 3 10356 #define V_T6_UNKNOWNCMD(x) ((x) << S_T6_UNKNOWNCMD) 10357 #define F_T6_UNKNOWNCMD V_T6_UNKNOWNCMD(1U) 10358 10359 #define S_T6_LIP0 2 10360 #define V_T6_LIP0(x) ((x) << S_T6_LIP0) 10361 #define F_T6_LIP0 V_T6_LIP0(1U) 10362 10363 #define S_T6_LIPMISS 1 10364 #define V_T6_LIPMISS(x) ((x) << S_T6_LIPMISS) 10365 #define F_T6_LIPMISS V_T6_LIPMISS(1U) 10366 10367 #define S_PIPELINEERR 0 10368 #define V_PIPELINEERR(x) ((x) << S_PIPELINEERR) 10369 #define F_PIPELINEERR V_PIPELINEERR(1U) 10370 10371 #define A_LE_DB_INT_CAUSE 0x19c3c 10372 10373 #define S_REQQPARERR 16 10374 #define V_REQQPARERR(x) ((x) << S_REQQPARERR) 10375 #define F_REQQPARERR V_REQQPARERR(1U) 10376 10377 #define S_UNKNOWNCMD 15 10378 #define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD) 10379 #define F_UNKNOWNCMD V_UNKNOWNCMD(1U) 10380 10381 #define S_DROPFILTERHIT 13 10382 #define V_DROPFILTERHIT(x) ((x) << S_DROPFILTERHIT) 10383 #define F_DROPFILTERHIT V_DROPFILTERHIT(1U) 10384 10385 #define S_FILTERHIT 12 10386 #define V_FILTERHIT(x) ((x) << S_FILTERHIT) 10387 #define F_FILTERHIT V_FILTERHIT(1U) 10388 10389 #define S_SYNCOOKIEOFF 11 10390 #define V_SYNCOOKIEOFF(x) ((x) << S_SYNCOOKIEOFF) 10391 #define F_SYNCOOKIEOFF V_SYNCOOKIEOFF(1U) 10392 10393 #define S_SYNCOOKIEBAD 10 10394 #define V_SYNCOOKIEBAD(x) ((x) << S_SYNCOOKIEBAD) 10395 #define F_SYNCOOKIEBAD V_SYNCOOKIEBAD(1U) 10396 10397 #define S_SYNCOOKIE 9 10398 #define V_SYNCOOKIE(x) ((x) << S_SYNCOOKIE) 10399 #define F_SYNCOOKIE V_SYNCOOKIE(1U) 10400 10401 #define S_NFASRCHFAIL 8 10402 #define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL) 10403 #define F_NFASRCHFAIL V_NFASRCHFAIL(1U) 10404 10405 #define S_ACTRGNFULL 7 10406 #define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL) 10407 #define F_ACTRGNFULL V_ACTRGNFULL(1U) 10408 10409 #define S_PARITYERR 6 10410 #define V_PARITYERR(x) ((x) << S_PARITYERR) 10411 #define F_PARITYERR V_PARITYERR(1U) 10412 10413 #define S_LIPMISS 5 10414 #define V_LIPMISS(x) ((x) << S_LIPMISS) 10415 #define F_LIPMISS V_LIPMISS(1U) 10416 10417 #define S_LIP0 4 10418 #define V_LIP0(x) ((x) << S_LIP0) 10419 #define F_LIP0 V_LIP0(1U) 10420 10421 #define S_MISS 3 10422 #define V_MISS(x) ((x) << S_MISS) 10423 #define F_MISS V_MISS(1U) 10424 10425 #define S_ROUTINGHIT 2 10426 #define V_ROUTINGHIT(x) ((x) << S_ROUTINGHIT) 10427 #define F_ROUTINGHIT V_ROUTINGHIT(1U) 10428 10429 #define S_ACTIVEHIT 1 10430 #define V_ACTIVEHIT(x) ((x) << S_ACTIVEHIT) 10431 #define F_ACTIVEHIT V_ACTIVEHIT(1U) 10432 10433 #define S_SERVERHIT 0 10434 #define V_SERVERHIT(x) ((x) << S_SERVERHIT) 10435 #define F_SERVERHIT V_SERVERHIT(1U) 10436 10437 #define S_ACTCNTIPV6TZERO 21 10438 #define V_ACTCNTIPV6TZERO(x) ((x) << S_ACTCNTIPV6TZERO) 10439 #define F_ACTCNTIPV6TZERO V_ACTCNTIPV6TZERO(1U) 10440 10441 #define S_ACTCNTIPV4TZERO 20 10442 #define V_ACTCNTIPV4TZERO(x) ((x) << S_ACTCNTIPV4TZERO) 10443 #define F_ACTCNTIPV4TZERO V_ACTCNTIPV4TZERO(1U) 10444 10445 #define S_ACTCNTIPV6ZERO 19 10446 #define V_ACTCNTIPV6ZERO(x) ((x) << S_ACTCNTIPV6ZERO) 10447 #define F_ACTCNTIPV6ZERO V_ACTCNTIPV6ZERO(1U) 10448 10449 #define S_ACTCNTIPV4ZERO 18 10450 #define V_ACTCNTIPV4ZERO(x) ((x) << S_ACTCNTIPV4ZERO) 10451 #define F_ACTCNTIPV4ZERO V_ACTCNTIPV4ZERO(1U) 10452 10453 #define S_MARSPPARERR 17 10454 #define V_MARSPPARERR(x) ((x) << S_MARSPPARERR) 10455 #define F_MARSPPARERR V_MARSPPARERR(1U) 10456 10457 #define S_VFPARERR 14 10458 #define V_VFPARERR(x) ((x) << S_VFPARERR) 10459 #define F_VFPARERR V_VFPARERR(1U) 10460 10461 #define S_T6_ACTRGNFULL 21 10462 #define V_T6_ACTRGNFULL(x) ((x) << S_T6_ACTRGNFULL) 10463 #define F_T6_ACTRGNFULL V_T6_ACTRGNFULL(1U) 10464 10465 #define S_T6_ACTCNTIPV6TZERO 20 10466 #define V_T6_ACTCNTIPV6TZERO(x) ((x) << S_T6_ACTCNTIPV6TZERO) 10467 #define F_T6_ACTCNTIPV6TZERO V_T6_ACTCNTIPV6TZERO(1U) 10468 10469 #define S_T6_ACTCNTIPV4TZERO 19 10470 #define V_T6_ACTCNTIPV4TZERO(x) ((x) << S_T6_ACTCNTIPV4TZERO) 10471 #define F_T6_ACTCNTIPV4TZERO V_T6_ACTCNTIPV4TZERO(1U) 10472 10473 #define S_T6_ACTCNTIPV6ZERO 18 10474 #define V_T6_ACTCNTIPV6ZERO(x) ((x) << S_T6_ACTCNTIPV6ZERO) 10475 #define F_T6_ACTCNTIPV6ZERO V_T6_ACTCNTIPV6ZERO(1U) 10476 10477 #define S_T6_ACTCNTIPV4ZERO 17 10478 #define V_T6_ACTCNTIPV4ZERO(x) ((x) << S_T6_ACTCNTIPV4ZERO) 10479 #define F_T6_ACTCNTIPV4ZERO V_T6_ACTCNTIPV4ZERO(1U) 10480 10481 #define S_T6_UNKNOWNCMD 3 10482 #define V_T6_UNKNOWNCMD(x) ((x) << S_T6_UNKNOWNCMD) 10483 #define F_T6_UNKNOWNCMD V_T6_UNKNOWNCMD(1U) 10484 10485 #define S_T6_LIP0 2 10486 #define V_T6_LIP0(x) ((x) << S_T6_LIP0) 10487 #define F_T6_LIP0 V_T6_LIP0(1U) 10488 10489 #define S_T6_LIPMISS 1 10490 #define V_T6_LIPMISS(x) ((x) << S_T6_LIPMISS) 10491 #define F_T6_LIPMISS V_T6_LIPMISS(1U) 10492 10493 #define A_LE_DB_RSP_CODE_0 0x19c74 10494 10495 #define S_SUCCESS 25 10496 #define M_SUCCESS 0x1fU 10497 #define V_SUCCESS(x) ((x) << S_SUCCESS) 10498 #define G_SUCCESS(x) (((x) >> S_SUCCESS) & M_SUCCESS) 10499 10500 #define S_TCAM_ACTV_SUCC 20 10501 #define M_TCAM_ACTV_SUCC 0x1fU 10502 #define V_TCAM_ACTV_SUCC(x) ((x) << S_TCAM_ACTV_SUCC) 10503 #define G_TCAM_ACTV_SUCC(x) (((x) >> S_TCAM_ACTV_SUCC) & M_TCAM_ACTV_SUCC) 10504 10505 #define S_HASH_ACTV_SUCC 15 10506 #define M_HASH_ACTV_SUCC 0x1fU 10507 #define V_HASH_ACTV_SUCC(x) ((x) << S_HASH_ACTV_SUCC) 10508 #define G_HASH_ACTV_SUCC(x) (((x) >> S_HASH_ACTV_SUCC) & M_HASH_ACTV_SUCC) 10509 10510 #define S_TCAM_SRVR_HIT 10 10511 #define M_TCAM_SRVR_HIT 0x1fU 10512 #define V_TCAM_SRVR_HIT(x) ((x) << S_TCAM_SRVR_HIT) 10513 #define G_TCAM_SRVR_HIT(x) (((x) >> S_TCAM_SRVR_HIT) & M_TCAM_SRVR_HIT) 10514 10515 #define S_SRAM_SRVR_HIT 5 10516 #define M_SRAM_SRVR_HIT 0x1fU 10517 #define V_SRAM_SRVR_HIT(x) ((x) << S_SRAM_SRVR_HIT) 10518 #define G_SRAM_SRVR_HIT(x) (((x) >> S_SRAM_SRVR_HIT) & M_SRAM_SRVR_HIT) 10519 10520 #define S_TCAM_ACTV_HIT 0 10521 #define M_TCAM_ACTV_HIT 0x1fU 10522 #define V_TCAM_ACTV_HIT(x) ((x) << S_TCAM_ACTV_HIT) 10523 #define G_TCAM_ACTV_HIT(x) (((x) >> S_TCAM_ACTV_HIT) & M_TCAM_ACTV_HIT) 10524 10525 #define A_LE_DB_RSP_CODE_1 0x19c78 10526 10527 #define S_HASH_ACTV_HIT 25 10528 #define M_HASH_ACTV_HIT 0x1fU 10529 #define V_HASH_ACTV_HIT(x) ((x) << S_HASH_ACTV_HIT) 10530 #define G_HASH_ACTV_HIT(x) (((x) >> S_HASH_ACTV_HIT) & M_HASH_ACTV_HIT) 10531 10532 #define S_T6_MISS 20 10533 #define M_T6_MISS 0x1fU 10534 #define V_T6_MISS(x) ((x) << S_T6_MISS) 10535 #define G_T6_MISS(x) (((x) >> S_T6_MISS) & M_T6_MISS) 10536 10537 #define S_NORM_FILT_HIT 15 10538 #define M_NORM_FILT_HIT 0x1fU 10539 #define V_NORM_FILT_HIT(x) ((x) << S_NORM_FILT_HIT) 10540 #define G_NORM_FILT_HIT(x) (((x) >> S_NORM_FILT_HIT) & M_NORM_FILT_HIT) 10541 10542 #define S_HPRI_FILT_HIT 10 10543 #define M_HPRI_FILT_HIT 0x1fU 10544 #define V_HPRI_FILT_HIT(x) ((x) << S_HPRI_FILT_HIT) 10545 #define G_HPRI_FILT_HIT(x) (((x) >> S_HPRI_FILT_HIT) & M_HPRI_FILT_HIT) 10546 10547 #define S_ACTV_OPEN_ERR 5 10548 #define M_ACTV_OPEN_ERR 0x1fU 10549 #define V_ACTV_OPEN_ERR(x) ((x) << S_ACTV_OPEN_ERR) 10550 #define G_ACTV_OPEN_ERR(x) (((x) >> S_ACTV_OPEN_ERR) & M_ACTV_OPEN_ERR) 10551 10552 #define S_ACTV_FULL_ERR 0 10553 #define M_ACTV_FULL_ERR 0x1fU 10554 #define V_ACTV_FULL_ERR(x) ((x) << S_ACTV_FULL_ERR) 10555 #define G_ACTV_FULL_ERR(x) (((x) >> S_ACTV_FULL_ERR) & M_ACTV_FULL_ERR) 10556 10557 #define A_LE_DB_ACT_CNT_IPV4_TCAM 0x19c94 10558 #define A_LE_DB_ACT_CNT_IPV6_TCAM 0x19c98 10559 #define A_LE_ACT_CNT_THRSH 0x19c9c 10560 10561 #define S_ACT_CNT_THRSH 0 10562 #define M_ACT_CNT_THRSH 0x1fffffU 10563 #define V_ACT_CNT_THRSH(x) ((x) << S_ACT_CNT_THRSH) 10564 #define G_ACT_CNT_THRSH(x) (((x) >> S_ACT_CNT_THRSH) & M_ACT_CNT_THRSH) 10565 10566 #define A_LE_DB_REQ_RSP_CNT 0x19ce4 10567 10568 #define S_RSPCNTLE 16 10569 #define M_RSPCNTLE 0xffffU 10570 #define V_RSPCNTLE(x) ((x) << S_RSPCNTLE) 10571 #define G_RSPCNTLE(x) (((x) >> S_RSPCNTLE) & M_RSPCNTLE) 10572 10573 #define S_REQCNTLE 0 10574 #define M_REQCNTLE 0xffffU 10575 #define V_REQCNTLE(x) ((x) << S_REQCNTLE) 10576 #define G_REQCNTLE(x) (((x) >> S_REQCNTLE) & M_REQCNTLE) 10577 10578 #define A_LE_DB_DBGI_CONFIG 0x19cf0 10579 10580 #define S_DBGICMDPERR 31 10581 #define V_DBGICMDPERR(x) ((x) << S_DBGICMDPERR) 10582 #define F_DBGICMDPERR V_DBGICMDPERR(1U) 10583 10584 #define S_DBGICMDRANGE 22 10585 #define M_DBGICMDRANGE 0x7U 10586 #define V_DBGICMDRANGE(x) ((x) << S_DBGICMDRANGE) 10587 #define G_DBGICMDRANGE(x) (((x) >> S_DBGICMDRANGE) & M_DBGICMDRANGE) 10588 10589 #define S_DBGICMDMSKTYPE 21 10590 #define V_DBGICMDMSKTYPE(x) ((x) << S_DBGICMDMSKTYPE) 10591 #define F_DBGICMDMSKTYPE V_DBGICMDMSKTYPE(1U) 10592 10593 #define S_DBGICMDSEARCH 20 10594 #define V_DBGICMDSEARCH(x) ((x) << S_DBGICMDSEARCH) 10595 #define F_DBGICMDSEARCH V_DBGICMDSEARCH(1U) 10596 10597 #define S_DBGICMDREAD 19 10598 #define V_DBGICMDREAD(x) ((x) << S_DBGICMDREAD) 10599 #define F_DBGICMDREAD V_DBGICMDREAD(1U) 10600 10601 #define S_DBGICMDLEARN 18 10602 #define V_DBGICMDLEARN(x) ((x) << S_DBGICMDLEARN) 10603 #define F_DBGICMDLEARN V_DBGICMDLEARN(1U) 10604 10605 #define S_DBGICMDERASE 17 10606 #define V_DBGICMDERASE(x) ((x) << S_DBGICMDERASE) 10607 #define F_DBGICMDERASE V_DBGICMDERASE(1U) 10608 10609 #define S_DBGICMDIPV6 16 10610 #define V_DBGICMDIPV6(x) ((x) << S_DBGICMDIPV6) 10611 #define F_DBGICMDIPV6 V_DBGICMDIPV6(1U) 10612 10613 #define S_DBGICMDTYPE 13 10614 #define M_DBGICMDTYPE 0x7U 10615 #define V_DBGICMDTYPE(x) ((x) << S_DBGICMDTYPE) 10616 #define G_DBGICMDTYPE(x) (((x) >> S_DBGICMDTYPE) & M_DBGICMDTYPE) 10617 10618 #define S_DBGICMDACKERR 12 10619 #define V_DBGICMDACKERR(x) ((x) << S_DBGICMDACKERR) 10620 #define F_DBGICMDACKERR V_DBGICMDACKERR(1U) 10621 10622 #define S_DBGICMDBUSY 3 10623 #define V_DBGICMDBUSY(x) ((x) << S_DBGICMDBUSY) 10624 #define F_DBGICMDBUSY V_DBGICMDBUSY(1U) 10625 10626 #define S_DBGICMDSTRT 2 10627 #define V_DBGICMDSTRT(x) ((x) << S_DBGICMDSTRT) 10628 #define F_DBGICMDSTRT V_DBGICMDSTRT(1U) 10629 10630 #define S_DBGICMDMODE 0 10631 #define M_DBGICMDMODE 0x3U 10632 #define V_DBGICMDMODE(x) ((x) << S_DBGICMDMODE) 10633 #define G_DBGICMDMODE(x) (((x) >> S_DBGICMDMODE) & M_DBGICMDMODE) 10634 10635 #define A_LE_DB_DBGI_REQ_TCAM_CMD 0x19cf4 10636 10637 #define S_DBGICMD 20 10638 #define M_DBGICMD 0xfU 10639 #define V_DBGICMD(x) ((x) << S_DBGICMD) 10640 #define G_DBGICMD(x) (((x) >> S_DBGICMD) & M_DBGICMD) 10641 10642 #define S_DBGITINDEX 0 10643 #define M_DBGITINDEX 0xfffffU 10644 #define V_DBGITINDEX(x) ((x) << S_DBGITINDEX) 10645 #define G_DBGITINDEX(x) (((x) >> S_DBGITINDEX) & M_DBGITINDEX) 10646 10647 #define A_LE_DB_DBGI_REQ_CMD 0x19cf4 10648 10649 #define S_DBGITID 0 10650 #define M_DBGITID 0xfffffU 10651 #define V_DBGITID(x) ((x) << S_DBGITID) 10652 #define G_DBGITID(x) (((x) >> S_DBGITID) & M_DBGITID) 10653 10654 #define A_LE_PERR_ENABLE 0x19cf8 10655 10656 #define S_BKCHKPERIOD 22 10657 #define M_BKCHKPERIOD 0x3ffU 10658 #define V_BKCHKPERIOD(x) ((x) << S_BKCHKPERIOD) 10659 #define G_BKCHKPERIOD(x) (((x) >> S_BKCHKPERIOD) & M_BKCHKPERIOD) 10660 10661 #define S_TCAMBKCHKEN 21 10662 #define V_TCAMBKCHKEN(x) ((x) << S_TCAMBKCHKEN) 10663 #define F_TCAMBKCHKEN V_TCAMBKCHKEN(1U) 10664 10665 #define S_T6_CLCAMFIFOERR 2 10666 #define V_T6_CLCAMFIFOERR(x) ((x) << S_T6_CLCAMFIFOERR) 10667 #define F_T6_CLCAMFIFOERR V_T6_CLCAMFIFOERR(1U) 10668 10669 #define S_T6_HASHTBLMEMCRCERR 1 10670 #define V_T6_HASHTBLMEMCRCERR(x) ((x) << S_T6_HASHTBLMEMCRCERR) 10671 #define F_T6_HASHTBLMEMCRCERR V_T6_HASHTBLMEMCRCERR(1U) 10672 10673 #define A_LE_DB_DBGI_REQ_DATA 0x19d00 10674 #define A_LE_DB_DBGI_REQ_MASK 0x19d50 10675 #define A_LE_DB_DBGI_RSP_STATUS 0x19d94 10676 10677 #define S_DBGIRSPINDEX 12 10678 #define M_DBGIRSPINDEX 0xfffffU 10679 #define V_DBGIRSPINDEX(x) ((x) << S_DBGIRSPINDEX) 10680 #define G_DBGIRSPINDEX(x) (((x) >> S_DBGIRSPINDEX) & M_DBGIRSPINDEX) 10681 10682 #define S_DBGIRSPMSG 8 10683 #define M_DBGIRSPMSG 0xfU 10684 #define V_DBGIRSPMSG(x) ((x) << S_DBGIRSPMSG) 10685 #define G_DBGIRSPMSG(x) (((x) >> S_DBGIRSPMSG) & M_DBGIRSPMSG) 10686 10687 #define S_DBGIRSPMSGVLD 7 10688 #define V_DBGIRSPMSGVLD(x) ((x) << S_DBGIRSPMSGVLD) 10689 #define F_DBGIRSPMSGVLD V_DBGIRSPMSGVLD(1U) 10690 10691 #define S_DBGIRSPMHIT 2 10692 #define V_DBGIRSPMHIT(x) ((x) << S_DBGIRSPMHIT) 10693 #define F_DBGIRSPMHIT V_DBGIRSPMHIT(1U) 10694 10695 #define S_DBGIRSPHIT 1 10696 #define V_DBGIRSPHIT(x) ((x) << S_DBGIRSPHIT) 10697 #define F_DBGIRSPHIT V_DBGIRSPHIT(1U) 10698 10699 #define S_DBGIRSPVALID 0 10700 #define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID) 10701 #define F_DBGIRSPVALID V_DBGIRSPVALID(1U) 10702 10703 #define S_DBGIRSPTID 12 10704 #define M_DBGIRSPTID 0xfffffU 10705 #define V_DBGIRSPTID(x) ((x) << S_DBGIRSPTID) 10706 #define G_DBGIRSPTID(x) (((x) >> S_DBGIRSPTID) & M_DBGIRSPTID) 10707 10708 #define S_DBGIRSPLEARN 2 10709 #define V_DBGIRSPLEARN(x) ((x) << S_DBGIRSPLEARN) 10710 #define F_DBGIRSPLEARN V_DBGIRSPLEARN(1U) 10711 10712 #define A_LE_DBG_SEL 0x19d98 10713 #define A_LE_DB_DBGI_RSP_DATA 0x19da0 10714 #define A_LE_DB_TCAM_TID_BASE 0x19df0 10715 10716 #define S_TCAM_TID_BASE 0 10717 #define M_TCAM_TID_BASE 0xfffffU 10718 #define V_TCAM_TID_BASE(x) ((x) << S_TCAM_TID_BASE) 10719 #define G_TCAM_TID_BASE(x) (((x) >> S_TCAM_TID_BASE) & M_TCAM_TID_BASE) 10720 10721 #define A_LE_DB_CLCAM_TID_BASE 0x19df4 10722 10723 #define S_CLCAM_TID_BASE 0 10724 #define M_CLCAM_TID_BASE 0xfffffU 10725 #define V_CLCAM_TID_BASE(x) ((x) << S_CLCAM_TID_BASE) 10726 #define G_CLCAM_TID_BASE(x) (((x) >> S_CLCAM_TID_BASE) & M_CLCAM_TID_BASE) 10727 10728 #define A_LE_DB_TID_HASHBASE 0x19df8 10729 10730 #define S_HASHBASE_ADDR 2 10731 #define M_HASHBASE_ADDR 0xfffffU 10732 #define V_HASHBASE_ADDR(x) ((x) << S_HASHBASE_ADDR) 10733 #define G_HASHBASE_ADDR(x) (((x) >> S_HASHBASE_ADDR) & M_HASHBASE_ADDR) 10734 10735 #define A_T6_LE_DB_HASH_TID_BASE 0x19df8 10736 10737 #define S_HASH_TID_BASE 0 10738 #define M_HASH_TID_BASE 0xfffffU 10739 #define V_HASH_TID_BASE(x) ((x) << S_HASH_TID_BASE) 10740 #define G_HASH_TID_BASE(x) (((x) >> S_HASH_TID_BASE) & M_HASH_TID_BASE) 10741 10742 #define A_LE_DB_SSRAM_TID_BASE 0x19dfc 10743 10744 #define S_SSRAM_TID_BASE 0 10745 #define M_SSRAM_TID_BASE 0xfffffU 10746 #define V_SSRAM_TID_BASE(x) ((x) << S_SSRAM_TID_BASE) 10747 #define G_SSRAM_TID_BASE(x) (((x) >> S_SSRAM_TID_BASE) & M_SSRAM_TID_BASE) 10748 10749 #define A_LE_DEBUG_LA_CONFIG 0x19f20 10750 #define A_LE_REQ_DEBUG_LA_DATA 0x19f24 10751 #define A_LE_REQ_DEBUG_LA_WRPTR 0x19f28 10752 #define A_LE_RSP_DEBUG_LA_DATA 0x19f2c 10753 #define A_LE_RSP_DEBUG_LA_WRPTR 0x19f30 10754 #define A_LE_DEBUG_LA_SELECTOR 0x19f34 10755 #define A_LE_SRVR_SRAM_INIT 0x19f34 10756 10757 #define S_SRVRSRAMBASE 2 10758 #define M_SRVRSRAMBASE 0xfffffU 10759 #define V_SRVRSRAMBASE(x) ((x) << S_SRVRSRAMBASE) 10760 #define G_SRVRSRAMBASE(x) (((x) >> S_SRVRSRAMBASE) & M_SRVRSRAMBASE) 10761 10762 #define S_SRVRINITBUSY 1 10763 #define V_SRVRINITBUSY(x) ((x) << S_SRVRINITBUSY) 10764 #define F_SRVRINITBUSY V_SRVRINITBUSY(1U) 10765 10766 #define S_SRVRINIT 0 10767 #define V_SRVRINIT(x) ((x) << S_SRVRINIT) 10768 #define F_SRVRINIT V_SRVRINIT(1U) 10769 10770 #define A_LE_DEBUG_LA_CAPTURED_DATA 0x19f38 10771 #define A_LE_MA_DEBUG_LA_DATA 0x19f3c 10772 #define A_LE_RSP_DEBUG_LA_HASH_WRPTR 0x19f40 10773 #define A_LE_HASH_DEBUG_LA_DATA 0x19f44 10774 #define A_LE_RSP_DEBUG_LA_TCAM_WRPTR 0x19f48 10775 #define A_LE_TCAM_DEBUG_LA_DATA 0x19f4c 10776 #define A_LE_DEBUG_LA_CONFIGT5 0x19fd0 10777 #define A_LE_REQ_DEBUG_LA_DATAT5 0x19fd4 10778 #define A_LE_REQ_DEBUG_LA_WRPTRT5 0x19fd8 10779 #define A_LE_RSP_DEBUG_LA_DATAT5 0x19fdc 10780 #define A_LE_RSP_DEBUG_LA_WRPTRT5 0x19fe0 10781 #define A_LE_DEBUG_LA_SEL_DATA 0x19fe4 10782 10783 /* registers for module NCSI */ 10784 #define NCSI_BASE_ADDR 0x1a000 10785 10786 #define A_NCSI_LA_RESERVED 0x1a0cc 10787 #define A_NCSI_INT_ENABLE 0x1a0d4 10788 10789 #define S_CIM_DM_PRTY_ERR 8 10790 #define V_CIM_DM_PRTY_ERR(x) ((x) << S_CIM_DM_PRTY_ERR) 10791 #define F_CIM_DM_PRTY_ERR V_CIM_DM_PRTY_ERR(1U) 10792 10793 #define S_MPS_DM_PRTY_ERR 7 10794 #define V_MPS_DM_PRTY_ERR(x) ((x) << S_MPS_DM_PRTY_ERR) 10795 #define F_MPS_DM_PRTY_ERR V_MPS_DM_PRTY_ERR(1U) 10796 10797 #define S_TOKEN 6 10798 #define V_TOKEN(x) ((x) << S_TOKEN) 10799 #define F_TOKEN V_TOKEN(1U) 10800 10801 #define S_ARB_DONE 5 10802 #define V_ARB_DONE(x) ((x) << S_ARB_DONE) 10803 #define F_ARB_DONE V_ARB_DONE(1U) 10804 10805 #define S_ARB_STARTED 4 10806 #define V_ARB_STARTED(x) ((x) << S_ARB_STARTED) 10807 #define F_ARB_STARTED V_ARB_STARTED(1U) 10808 10809 #define S_WOL 3 10810 #define V_WOL(x) ((x) << S_WOL) 10811 #define F_WOL V_WOL(1U) 10812 10813 #define S_MACINT 2 10814 #define V_MACINT(x) ((x) << S_MACINT) 10815 #define F_MACINT V_MACINT(1U) 10816 10817 #define S_TXFIFO_PRTY_ERR 1 10818 #define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR) 10819 #define F_TXFIFO_PRTY_ERR V_TXFIFO_PRTY_ERR(1U) 10820 10821 #define S_RXFIFO_PRTY_ERR 0 10822 #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR) 10823 #define F_RXFIFO_PRTY_ERR V_RXFIFO_PRTY_ERR(1U) 10824 10825 #define A_NCSI_INT_CAUSE 0x1a0d8 10826 #define A_NCSI_PERR_ENABLE 0x1a0f8 10827 10828 /* registers for module XGMAC */ 10829 #define XGMAC_BASE_ADDR 0x0 10830 10831 #define A_XGMAC_PORT_CFG 0x1000 10832 10833 #define S_SIGNAL_DET 14 10834 #define V_SIGNAL_DET(x) ((x) << S_SIGNAL_DET) 10835 #define F_SIGNAL_DET V_SIGNAL_DET(1U) 10836 10837 #define A_XGMAC_PORT_INT_CAUSE 0x10dc 10838 10839 #define S_EXT_LOS 28 10840 #define V_EXT_LOS(x) ((x) << S_EXT_LOS) 10841 #define F_EXT_LOS V_EXT_LOS(1U) 10842 10843 #define S_INCMPTBL_LINK 27 10844 #define V_INCMPTBL_LINK(x) ((x) << S_INCMPTBL_LINK) 10845 #define F_INCMPTBL_LINK V_INCMPTBL_LINK(1U) 10846 10847 #define S_PATDETWAKE 26 10848 #define V_PATDETWAKE(x) ((x) << S_PATDETWAKE) 10849 #define F_PATDETWAKE V_PATDETWAKE(1U) 10850 10851 #define S_MAGICWAKE 25 10852 #define V_MAGICWAKE(x) ((x) << S_MAGICWAKE) 10853 #define F_MAGICWAKE V_MAGICWAKE(1U) 10854 10855 #define S_SIGDETCHG 24 10856 #define V_SIGDETCHG(x) ((x) << S_SIGDETCHG) 10857 #define F_SIGDETCHG V_SIGDETCHG(1U) 10858 10859 #define S_PCSR_FEC_CORR 23 10860 #define V_PCSR_FEC_CORR(x) ((x) << S_PCSR_FEC_CORR) 10861 #define F_PCSR_FEC_CORR V_PCSR_FEC_CORR(1U) 10862 10863 #define S_AE_TRAIN_LOCAL 22 10864 #define V_AE_TRAIN_LOCAL(x) ((x) << S_AE_TRAIN_LOCAL) 10865 #define F_AE_TRAIN_LOCAL V_AE_TRAIN_LOCAL(1U) 10866 10867 #define S_HSSPLL_LOCK 21 10868 #define V_HSSPLL_LOCK(x) ((x) << S_HSSPLL_LOCK) 10869 #define F_HSSPLL_LOCK V_HSSPLL_LOCK(1U) 10870 10871 #define S_HSSPRT_READY 20 10872 #define V_HSSPRT_READY(x) ((x) << S_HSSPRT_READY) 10873 #define F_HSSPRT_READY V_HSSPRT_READY(1U) 10874 10875 #define S_AUTONEG_DONE 19 10876 #define V_AUTONEG_DONE(x) ((x) << S_AUTONEG_DONE) 10877 #define F_AUTONEG_DONE V_AUTONEG_DONE(1U) 10878 10879 #define S_PCSR_HI_BER 18 10880 #define V_PCSR_HI_BER(x) ((x) << S_PCSR_HI_BER) 10881 #define F_PCSR_HI_BER V_PCSR_HI_BER(1U) 10882 10883 #define S_PCSR_FEC_ERROR 17 10884 #define V_PCSR_FEC_ERROR(x) ((x) << S_PCSR_FEC_ERROR) 10885 #define F_PCSR_FEC_ERROR V_PCSR_FEC_ERROR(1U) 10886 10887 #define S_PCSR_LINK_FAIL 16 10888 #define V_PCSR_LINK_FAIL(x) ((x) << S_PCSR_LINK_FAIL) 10889 #define F_PCSR_LINK_FAIL V_PCSR_LINK_FAIL(1U) 10890 10891 #define S_XAUI_DEC_ERROR 15 10892 #define V_XAUI_DEC_ERROR(x) ((x) << S_XAUI_DEC_ERROR) 10893 #define F_XAUI_DEC_ERROR V_XAUI_DEC_ERROR(1U) 10894 10895 #define S_XAUI_LINK_FAIL 14 10896 #define V_XAUI_LINK_FAIL(x) ((x) << S_XAUI_LINK_FAIL) 10897 #define F_XAUI_LINK_FAIL V_XAUI_LINK_FAIL(1U) 10898 10899 #define S_PCS_CTC_ERROR 13 10900 #define V_PCS_CTC_ERROR(x) ((x) << S_PCS_CTC_ERROR) 10901 #define F_PCS_CTC_ERROR V_PCS_CTC_ERROR(1U) 10902 10903 #define S_PCS_LINK_GOOD 12 10904 #define V_PCS_LINK_GOOD(x) ((x) << S_PCS_LINK_GOOD) 10905 #define F_PCS_LINK_GOOD V_PCS_LINK_GOOD(1U) 10906 10907 #define S_PCS_LINK_FAIL 11 10908 #define V_PCS_LINK_FAIL(x) ((x) << S_PCS_LINK_FAIL) 10909 #define F_PCS_LINK_FAIL V_PCS_LINK_FAIL(1U) 10910 10911 #define S_RXFIFOOVERFLOW 10 10912 #define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW) 10913 #define F_RXFIFOOVERFLOW V_RXFIFOOVERFLOW(1U) 10914 10915 #define S_HSSPRBSERR 9 10916 #define V_HSSPRBSERR(x) ((x) << S_HSSPRBSERR) 10917 #define F_HSSPRBSERR V_HSSPRBSERR(1U) 10918 10919 #define S_HSSEYEQUAL 8 10920 #define V_HSSEYEQUAL(x) ((x) << S_HSSEYEQUAL) 10921 #define F_HSSEYEQUAL V_HSSEYEQUAL(1U) 10922 10923 #define S_REMOTEFAULT 7 10924 #define V_REMOTEFAULT(x) ((x) << S_REMOTEFAULT) 10925 #define F_REMOTEFAULT V_REMOTEFAULT(1U) 10926 10927 #define S_LOCALFAULT 6 10928 #define V_LOCALFAULT(x) ((x) << S_LOCALFAULT) 10929 #define F_LOCALFAULT V_LOCALFAULT(1U) 10930 10931 #define S_MAC_LINK_DOWN 5 10932 #define V_MAC_LINK_DOWN(x) ((x) << S_MAC_LINK_DOWN) 10933 #define F_MAC_LINK_DOWN V_MAC_LINK_DOWN(1U) 10934 10935 #define S_MAC_LINK_UP 4 10936 #define V_MAC_LINK_UP(x) ((x) << S_MAC_LINK_UP) 10937 #define F_MAC_LINK_UP V_MAC_LINK_UP(1U) 10938 10939 #define S_BEAN_INT 3 10940 #define V_BEAN_INT(x) ((x) << S_BEAN_INT) 10941 #define F_BEAN_INT V_BEAN_INT(1U) 10942 10943 #define S_XGM_INT 2 10944 #define V_XGM_INT(x) ((x) << S_XGM_INT) 10945 #define F_XGM_INT V_XGM_INT(1U) 10946 10947 10948 /* registers for module UP */ 10949 #define UP_BASE_ADDR 0x0 10950 10951 #define A_UP_IBQ_0_RDADDR 0x10 10952 10953 #define S_QUEID 13 10954 #define M_QUEID 0x7ffffU 10955 #define V_QUEID(x) ((x) << S_QUEID) 10956 #define G_QUEID(x) (((x) >> S_QUEID) & M_QUEID) 10957 10958 #define S_IBQRDADDR 0 10959 #define M_IBQRDADDR 0x1fffU 10960 #define V_IBQRDADDR(x) ((x) << S_IBQRDADDR) 10961 #define G_IBQRDADDR(x) (((x) >> S_IBQRDADDR) & M_IBQRDADDR) 10962 10963 #define A_UP_IBQ_0_WRADDR 0x14 10964 10965 #define S_IBQWRADDR 0 10966 #define M_IBQWRADDR 0x1fffU 10967 #define V_IBQWRADDR(x) ((x) << S_IBQWRADDR) 10968 #define G_IBQWRADDR(x) (((x) >> S_IBQWRADDR) & M_IBQWRADDR) 10969 10970 #define A_UP_IBQ_0_STATUS 0x18 10971 10972 #define S_QUEERRFRAME 31 10973 #define V_QUEERRFRAME(x) ((x) << S_QUEERRFRAME) 10974 #define F_QUEERRFRAME V_QUEERRFRAME(1U) 10975 10976 #define S_QUEREMFLITS 0 10977 #define M_QUEREMFLITS 0x7ffU 10978 #define V_QUEREMFLITS(x) ((x) << S_QUEREMFLITS) 10979 #define G_QUEREMFLITS(x) (((x) >> S_QUEREMFLITS) & M_QUEREMFLITS) 10980 10981 #define A_UP_IBQ_0_PKTCNT 0x1c 10982 10983 #define S_QUEEOPCNT 16 10984 #define M_QUEEOPCNT 0xfffU 10985 #define V_QUEEOPCNT(x) ((x) << S_QUEEOPCNT) 10986 #define G_QUEEOPCNT(x) (((x) >> S_QUEEOPCNT) & M_QUEEOPCNT) 10987 10988 #define S_QUESOPCNT 0 10989 #define M_QUESOPCNT 0xfffU 10990 #define V_QUESOPCNT(x) ((x) << S_QUESOPCNT) 10991 #define G_QUESOPCNT(x) (((x) >> S_QUESOPCNT) & M_QUESOPCNT) 10992 10993 #define A_UP_OBQ_0_RDADDR 0x70 10994 10995 #define S_OBQID 15 10996 #define M_OBQID 0x1ffffU 10997 #define V_OBQID(x) ((x) << S_OBQID) 10998 #define G_OBQID(x) (((x) >> S_OBQID) & M_OBQID) 10999 11000 #define S_QUERDADDR 0 11001 #define M_QUERDADDR 0x7fffU 11002 #define V_QUERDADDR(x) ((x) << S_QUERDADDR) 11003 #define G_QUERDADDR(x) (((x) >> S_QUERDADDR) & M_QUERDADDR) 11004 11005 #define A_UP_OBQ_0_REALADDR 0x104 11006 11007 #define S_QUEMEMADDR 3 11008 #define M_QUEMEMADDR 0x7ffU 11009 #define V_QUEMEMADDR(x) ((x) << S_QUEMEMADDR) 11010 #define G_QUEMEMADDR(x) (((x) >> S_QUEMEMADDR) & M_QUEMEMADDR) 11011 11012 #define A_UP_UP_DBG_LA_CFG 0x140 11013 11014 #define S_UPDBGLACAPTBUB 31 11015 #define V_UPDBGLACAPTBUB(x) ((x) << S_UPDBGLACAPTBUB) 11016 #define F_UPDBGLACAPTBUB V_UPDBGLACAPTBUB(1U) 11017 11018 #define S_UPDBGLACAPTPCONLY 30 11019 #define V_UPDBGLACAPTPCONLY(x) ((x) << S_UPDBGLACAPTPCONLY) 11020 #define F_UPDBGLACAPTPCONLY V_UPDBGLACAPTPCONLY(1U) 11021 11022 #define S_UPDBGLAMASKSTOP 29 11023 #define V_UPDBGLAMASKSTOP(x) ((x) << S_UPDBGLAMASKSTOP) 11024 #define F_UPDBGLAMASKSTOP V_UPDBGLAMASKSTOP(1U) 11025 11026 #define S_UPDBGLAMASKTRIG 28 11027 #define V_UPDBGLAMASKTRIG(x) ((x) << S_UPDBGLAMASKTRIG) 11028 #define F_UPDBGLAMASKTRIG V_UPDBGLAMASKTRIG(1U) 11029 11030 #define S_UPDBGLAWRPTR 16 11031 #define M_UPDBGLAWRPTR 0xfffU 11032 #define V_UPDBGLAWRPTR(x) ((x) << S_UPDBGLAWRPTR) 11033 #define G_UPDBGLAWRPTR(x) (((x) >> S_UPDBGLAWRPTR) & M_UPDBGLAWRPTR) 11034 11035 #define S_UPDBGLARDPTR 2 11036 #define M_UPDBGLARDPTR 0xfffU 11037 #define V_UPDBGLARDPTR(x) ((x) << S_UPDBGLARDPTR) 11038 #define G_UPDBGLARDPTR(x) (((x) >> S_UPDBGLARDPTR) & M_UPDBGLARDPTR) 11039 11040 #define S_UPDBGLARDEN 1 11041 #define V_UPDBGLARDEN(x) ((x) << S_UPDBGLARDEN) 11042 #define F_UPDBGLARDEN V_UPDBGLARDEN(1U) 11043 11044 #define S_UPDBGLAEN 0 11045 #define V_UPDBGLAEN(x) ((x) << S_UPDBGLAEN) 11046 #define F_UPDBGLAEN V_UPDBGLAEN(1U) 11047 11048 #define S_UPDBGLABUSY 14 11049 #define V_UPDBGLABUSY(x) ((x) << S_UPDBGLABUSY) 11050 #define F_UPDBGLABUSY V_UPDBGLABUSY(1U) 11051 11052 #define A_UP_UP_DBG_LA_DATA 0x144 11053 #define A_UP_IBQ_0_SHADOW_RDADDR 0x280 11054 #define A_UP_IBQ_0_SHADOW_WRADDR 0x284 11055 #define A_UP_IBQ_0_SHADOW_STATUS 0x288 11056 #define A_UP_IBQ_0_SHADOW_PKTCNT 0x28c 11057 #define A_UP_IBQ_1_SHADOW_RDADDR 0x290 11058 #define A_UP_IBQ_1_SHADOW_WRADDR 0x294 11059 #define A_UP_IBQ_1_SHADOW_STATUS 0x298 11060 #define A_UP_IBQ_1_SHADOW_PKTCNT 0x29c 11061 #define A_UP_IBQ_2_SHADOW_RDADDR 0x2a0 11062 #define A_UP_IBQ_2_SHADOW_WRADDR 0x2a4 11063 #define A_UP_IBQ_2_SHADOW_STATUS 0x2a8 11064 #define A_UP_IBQ_2_SHADOW_PKTCNT 0x2ac 11065 #define A_UP_IBQ_3_SHADOW_RDADDR 0x2b0 11066 #define A_UP_IBQ_3_SHADOW_WRADDR 0x2b4 11067 #define A_UP_IBQ_3_SHADOW_STATUS 0x2b8 11068 #define A_UP_IBQ_3_SHADOW_PKTCNT 0x2bc 11069 #define A_UP_IBQ_4_SHADOW_RDADDR 0x2c0 11070 #define A_UP_IBQ_4_SHADOW_WRADDR 0x2c4 11071 #define A_UP_IBQ_4_SHADOW_STATUS 0x2c8 11072 #define A_UP_IBQ_4_SHADOW_PKTCNT 0x2cc 11073 #define A_UP_IBQ_5_SHADOW_RDADDR 0x2d0 11074 #define A_UP_IBQ_5_SHADOW_WRADDR 0x2d4 11075 #define A_UP_IBQ_5_SHADOW_STATUS 0x2d8 11076 #define A_UP_IBQ_5_SHADOW_PKTCNT 0x2dc 11077 #define A_UP_OBQ_0_SHADOW_RDADDR 0x2e0 11078 #define A_UP_OBQ_0_SHADOW_WRADDR 0x2e4 11079 11080 #define S_QUEWRADDR 0 11081 #define M_QUEWRADDR 0x7fffU 11082 #define V_QUEWRADDR(x) ((x) << S_QUEWRADDR) 11083 #define G_QUEWRADDR(x) (((x) >> S_QUEWRADDR) & M_QUEWRADDR) 11084 11085 #define A_UP_OBQ_0_SHADOW_STATUS 0x2e8 11086 #define A_UP_OBQ_0_SHADOW_PKTCNT 0x2ec 11087 #define A_UP_OBQ_1_SHADOW_RDADDR 0x2f0 11088 #define A_UP_OBQ_1_SHADOW_WRADDR 0x2f4 11089 #define A_UP_OBQ_1_SHADOW_STATUS 0x2f8 11090 #define A_UP_OBQ_1_SHADOW_PKTCNT 0x2fc 11091 #define A_UP_OBQ_2_SHADOW_RDADDR 0x300 11092 #define A_UP_OBQ_2_SHADOW_WRADDR 0x304 11093 #define A_UP_OBQ_2_SHADOW_STATUS 0x308 11094 #define A_UP_OBQ_2_SHADOW_PKTCNT 0x30c 11095 #define A_UP_OBQ_3_SHADOW_RDADDR 0x310 11096 #define A_UP_OBQ_3_SHADOW_WRADDR 0x314 11097 #define A_UP_OBQ_3_SHADOW_STATUS 0x318 11098 #define A_UP_OBQ_3_SHADOW_PKTCNT 0x31c 11099 #define A_UP_OBQ_4_SHADOW_RDADDR 0x320 11100 #define A_UP_OBQ_4_SHADOW_WRADDR 0x324 11101 #define A_UP_OBQ_4_SHADOW_STATUS 0x328 11102 #define A_UP_OBQ_4_SHADOW_PKTCNT 0x32c 11103 #define A_UP_OBQ_5_SHADOW_RDADDR 0x330 11104 #define A_UP_OBQ_5_SHADOW_WRADDR 0x334 11105 #define A_UP_OBQ_5_SHADOW_STATUS 0x338 11106 #define A_UP_OBQ_5_SHADOW_PKTCNT 0x33c 11107 #define A_UP_OBQ_6_SHADOW_RDADDR 0x340 11108 #define A_UP_OBQ_6_SHADOW_WRADDR 0x344 11109 #define A_UP_OBQ_6_SHADOW_STATUS 0x348 11110 #define A_UP_OBQ_6_SHADOW_PKTCNT 0x34c 11111 #define A_UP_OBQ_7_SHADOW_RDADDR 0x350 11112 #define A_UP_OBQ_7_SHADOW_WRADDR 0x354 11113 #define A_UP_OBQ_7_SHADOW_STATUS 0x358 11114 #define A_UP_OBQ_7_SHADOW_PKTCNT 0x35c 11115 #define A_UP_IBQ_0_SHADOW_CONFIG 0x360 11116 11117 #define S_QUESIZE 26 11118 #define M_QUESIZE 0x3fU 11119 #define V_QUESIZE(x) ((x) << S_QUESIZE) 11120 #define G_QUESIZE(x) (((x) >> S_QUESIZE) & M_QUESIZE) 11121 11122 #define S_QUEBASE 8 11123 #define M_QUEBASE 0x3fU 11124 #define V_QUEBASE(x) ((x) << S_QUEBASE) 11125 #define G_QUEBASE(x) (((x) >> S_QUEBASE) & M_QUEBASE) 11126 11127 #define S_QUEDBG8BEN 7 11128 #define V_QUEDBG8BEN(x) ((x) << S_QUEDBG8BEN) 11129 #define F_QUEDBG8BEN V_QUEDBG8BEN(1U) 11130 11131 #define S_QUEBAREADDR 0 11132 #define V_QUEBAREADDR(x) ((x) << S_QUEBAREADDR) 11133 #define F_QUEBAREADDR V_QUEBAREADDR(1U) 11134 11135 #define A_UP_IBQ_0_SHADOW_REALADDR 0x364 11136 11137 #define S_QUERDADDRWRAP 31 11138 #define V_QUERDADDRWRAP(x) ((x) << S_QUERDADDRWRAP) 11139 #define F_QUERDADDRWRAP V_QUERDADDRWRAP(1U) 11140 11141 #define S_QUEWRADDRWRAP 30 11142 #define V_QUEWRADDRWRAP(x) ((x) << S_QUEWRADDRWRAP) 11143 #define F_QUEWRADDRWRAP V_QUEWRADDRWRAP(1U) 11144 11145 #define A_UP_IBQ_1_SHADOW_CONFIG 0x368 11146 #define A_UP_IBQ_1_SHADOW_REALADDR 0x36c 11147 #define A_UP_IBQ_2_SHADOW_CONFIG 0x370 11148 #define A_UP_IBQ_2_SHADOW_REALADDR 0x374 11149 #define A_UP_IBQ_3_SHADOW_CONFIG 0x378 11150 #define A_UP_IBQ_3_SHADOW_REALADDR 0x37c 11151 #define A_UP_IBQ_4_SHADOW_CONFIG 0x380 11152 #define A_UP_IBQ_4_SHADOW_REALADDR 0x384 11153 #define A_UP_IBQ_5_SHADOW_CONFIG 0x388 11154 #define A_UP_IBQ_5_SHADOW_REALADDR 0x38c 11155 #define A_UP_OBQ_0_SHADOW_CONFIG 0x390 11156 #define A_UP_OBQ_0_SHADOW_REALADDR 0x394 11157 #define A_UP_OBQ_1_SHADOW_CONFIG 0x398 11158 #define A_UP_OBQ_1_SHADOW_REALADDR 0x39c 11159 #define A_UP_OBQ_2_SHADOW_CONFIG 0x3a0 11160 #define A_UP_OBQ_2_SHADOW_REALADDR 0x3a4 11161 #define A_UP_OBQ_3_SHADOW_CONFIG 0x3a8 11162 #define A_UP_OBQ_3_SHADOW_REALADDR 0x3ac 11163 #define A_UP_OBQ_4_SHADOW_CONFIG 0x3b0 11164 #define A_UP_OBQ_4_SHADOW_REALADDR 0x3b4 11165 #define A_UP_OBQ_5_SHADOW_CONFIG 0x3b8 11166 #define A_UP_OBQ_5_SHADOW_REALADDR 0x3bc 11167 #define A_UP_OBQ_6_SHADOW_CONFIG 0x3c0 11168 #define A_UP_OBQ_6_SHADOW_REALADDR 0x3c4 11169 #define A_UP_OBQ_7_SHADOW_CONFIG 0x3c8 11170 #define A_UP_OBQ_7_SHADOW_REALADDR 0x3cc 11171 11172 /* registers for module CIM_CTL */ 11173 #define CIM_CTL_BASE_ADDR 0x0 11174 11175 11176 /* registers for module MAC */ 11177 #define MAC_BASE_ADDR 0x0 11178 11179 #define A_MAC_PORT_CFG 0x800 11180 11181 #define S_MAC_CLK_SEL 29 11182 #define M_MAC_CLK_SEL 0x7U 11183 #define V_MAC_CLK_SEL(x) ((x) << S_MAC_CLK_SEL) 11184 #define G_MAC_CLK_SEL(x) (((x) >> S_MAC_CLK_SEL) & M_MAC_CLK_SEL) 11185 11186 #define S_SINKTX 27 11187 #define V_SINKTX(x) ((x) << S_SINKTX) 11188 #define F_SINKTX V_SINKTX(1U) 11189 11190 #define S_SINKTXONLINKDOWN 26 11191 #define V_SINKTXONLINKDOWN(x) ((x) << S_SINKTXONLINKDOWN) 11192 #define F_SINKTXONLINKDOWN V_SINKTXONLINKDOWN(1U) 11193 11194 #define S_LOOPNOFWD 24 11195 #define V_LOOPNOFWD(x) ((x) << S_LOOPNOFWD) 11196 #define F_LOOPNOFWD V_LOOPNOFWD(1U) 11197 11198 #define S_SMUX_RX_LOOP 19 11199 #define V_SMUX_RX_LOOP(x) ((x) << S_SMUX_RX_LOOP) 11200 #define F_SMUX_RX_LOOP V_SMUX_RX_LOOP(1U) 11201 11202 #define S_RX_LANE_SWAP 18 11203 #define V_RX_LANE_SWAP(x) ((x) << S_RX_LANE_SWAP) 11204 #define F_RX_LANE_SWAP V_RX_LANE_SWAP(1U) 11205 11206 #define S_TX_LANE_SWAP 17 11207 #define V_TX_LANE_SWAP(x) ((x) << S_TX_LANE_SWAP) 11208 #define F_TX_LANE_SWAP V_TX_LANE_SWAP(1U) 11209 11210 #define S_SMUXTXSEL 9 11211 #define V_SMUXTXSEL(x) ((x) << S_SMUXTXSEL) 11212 #define F_SMUXTXSEL V_SMUXTXSEL(1U) 11213 11214 #define S_SMUXRXSEL 8 11215 #define V_SMUXRXSEL(x) ((x) << S_SMUXRXSEL) 11216 #define F_SMUXRXSEL V_SMUXRXSEL(1U) 11217 11218 #define S_PORTSPEED 4 11219 #define M_PORTSPEED 0x3U 11220 #define V_PORTSPEED(x) ((x) << S_PORTSPEED) 11221 #define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED) 11222 11223 #define S_RX_BYTE_SWAP 3 11224 #define V_RX_BYTE_SWAP(x) ((x) << S_RX_BYTE_SWAP) 11225 #define F_RX_BYTE_SWAP V_RX_BYTE_SWAP(1U) 11226 11227 #define S_TX_BYTE_SWAP 2 11228 #define V_TX_BYTE_SWAP(x) ((x) << S_TX_BYTE_SWAP) 11229 #define F_TX_BYTE_SWAP V_TX_BYTE_SWAP(1U) 11230 11231 #define S_PORT_SEL 0 11232 #define V_PORT_SEL(x) ((x) << S_PORT_SEL) 11233 #define F_PORT_SEL V_PORT_SEL(1U) 11234 11235 #define S_ENA_ERR_RSP 28 11236 #define V_ENA_ERR_RSP(x) ((x) << S_ENA_ERR_RSP) 11237 #define F_ENA_ERR_RSP V_ENA_ERR_RSP(1U) 11238 11239 #define S_DEBUG_CLR 25 11240 #define V_DEBUG_CLR(x) ((x) << S_DEBUG_CLR) 11241 #define F_DEBUG_CLR V_DEBUG_CLR(1U) 11242 11243 #define S_PLL_SEL 23 11244 #define V_PLL_SEL(x) ((x) << S_PLL_SEL) 11245 #define F_PLL_SEL V_PLL_SEL(1U) 11246 11247 #define S_PORT_MAP 20 11248 #define M_PORT_MAP 0x7U 11249 #define V_PORT_MAP(x) ((x) << S_PORT_MAP) 11250 #define G_PORT_MAP(x) (((x) >> S_PORT_MAP) & M_PORT_MAP) 11251 11252 #define S_AEC_PAT_DATA 15 11253 #define V_AEC_PAT_DATA(x) ((x) << S_AEC_PAT_DATA) 11254 #define F_AEC_PAT_DATA V_AEC_PAT_DATA(1U) 11255 11256 #define S_MACCLK_SEL 13 11257 #define V_MACCLK_SEL(x) ((x) << S_MACCLK_SEL) 11258 #define F_MACCLK_SEL V_MACCLK_SEL(1U) 11259 11260 #define S_XGMII_SEL 12 11261 #define V_XGMII_SEL(x) ((x) << S_XGMII_SEL) 11262 #define F_XGMII_SEL V_XGMII_SEL(1U) 11263 11264 #define S_DEBUG_PORT_SEL 10 11265 #define M_DEBUG_PORT_SEL 0x3U 11266 #define V_DEBUG_PORT_SEL(x) ((x) << S_DEBUG_PORT_SEL) 11267 #define G_DEBUG_PORT_SEL(x) (((x) >> S_DEBUG_PORT_SEL) & M_DEBUG_PORT_SEL) 11268 11269 #define S_ENABLE_25G 7 11270 #define V_ENABLE_25G(x) ((x) << S_ENABLE_25G) 11271 #define F_ENABLE_25G V_ENABLE_25G(1U) 11272 11273 #define S_ENABLE_50G 6 11274 #define V_ENABLE_50G(x) ((x) << S_ENABLE_50G) 11275 #define F_ENABLE_50G V_ENABLE_50G(1U) 11276 11277 #define S_DEBUG_TX_RX_SEL 1 11278 #define V_DEBUG_TX_RX_SEL(x) ((x) << S_DEBUG_TX_RX_SEL) 11279 #define F_DEBUG_TX_RX_SEL V_DEBUG_TX_RX_SEL(1U) 11280 11281 #define A_MAC_PORT_RESET_CTRL 0x804 11282 11283 #define S_TWGDSK_HSSC16B 31 11284 #define V_TWGDSK_HSSC16B(x) ((x) << S_TWGDSK_HSSC16B) 11285 #define F_TWGDSK_HSSC16B V_TWGDSK_HSSC16B(1U) 11286 11287 #define S_EEE_RESET 30 11288 #define V_EEE_RESET(x) ((x) << S_EEE_RESET) 11289 #define F_EEE_RESET V_EEE_RESET(1U) 11290 11291 #define S_PTP_TIMER 29 11292 #define V_PTP_TIMER(x) ((x) << S_PTP_TIMER) 11293 #define F_PTP_TIMER V_PTP_TIMER(1U) 11294 11295 #define S_MTIPREFRESET 28 11296 #define V_MTIPREFRESET(x) ((x) << S_MTIPREFRESET) 11297 #define F_MTIPREFRESET V_MTIPREFRESET(1U) 11298 11299 #define S_MAC100G40G_RESET 27 11300 #define V_MAC100G40G_RESET(x) ((x) << S_MAC100G40G_RESET) 11301 #define F_MAC100G40G_RESET V_MAC100G40G_RESET(1U) 11302 11303 #define S_MAC10G1G_RESET 26 11304 #define V_MAC10G1G_RESET(x) ((x) << S_MAC10G1G_RESET) 11305 #define F_MAC10G1G_RESET V_MAC10G1G_RESET(1U) 11306 11307 #define S_MTIPREGRESET 25 11308 #define V_MTIPREGRESET(x) ((x) << S_MTIPREGRESET) 11309 #define F_MTIPREGRESET V_MTIPREGRESET(1U) 11310 11311 #define S_PCS1G_RESET 24 11312 #define V_PCS1G_RESET(x) ((x) << S_PCS1G_RESET) 11313 #define F_PCS1G_RESET V_PCS1G_RESET(1U) 11314 11315 #define S_AEC3RESET 23 11316 #define V_AEC3RESET(x) ((x) << S_AEC3RESET) 11317 #define F_AEC3RESET V_AEC3RESET(1U) 11318 11319 #define S_AEC2RESET 22 11320 #define V_AEC2RESET(x) ((x) << S_AEC2RESET) 11321 #define F_AEC2RESET V_AEC2RESET(1U) 11322 11323 #define S_AEC1RESET 21 11324 #define V_AEC1RESET(x) ((x) << S_AEC1RESET) 11325 #define F_AEC1RESET V_AEC1RESET(1U) 11326 11327 #define S_AEC0RESET 20 11328 #define V_AEC0RESET(x) ((x) << S_AEC0RESET) 11329 #define F_AEC0RESET V_AEC0RESET(1U) 11330 11331 #define S_AET3RESET 19 11332 #define V_AET3RESET(x) ((x) << S_AET3RESET) 11333 #define F_AET3RESET V_AET3RESET(1U) 11334 11335 #define S_AET2RESET 18 11336 #define V_AET2RESET(x) ((x) << S_AET2RESET) 11337 #define F_AET2RESET V_AET2RESET(1U) 11338 11339 #define S_AET1RESET 17 11340 #define V_AET1RESET(x) ((x) << S_AET1RESET) 11341 #define F_AET1RESET V_AET1RESET(1U) 11342 11343 #define S_AET0RESET 16 11344 #define V_AET0RESET(x) ((x) << S_AET0RESET) 11345 #define F_AET0RESET V_AET0RESET(1U) 11346 11347 #define S_PCS10G_RESET 15 11348 #define V_PCS10G_RESET(x) ((x) << S_PCS10G_RESET) 11349 #define F_PCS10G_RESET V_PCS10G_RESET(1U) 11350 11351 #define S_PCS40G_RESET 14 11352 #define V_PCS40G_RESET(x) ((x) << S_PCS40G_RESET) 11353 #define F_PCS40G_RESET V_PCS40G_RESET(1U) 11354 11355 #define S_PCS100G_RESET 13 11356 #define V_PCS100G_RESET(x) ((x) << S_PCS100G_RESET) 11357 #define F_PCS100G_RESET V_PCS100G_RESET(1U) 11358 11359 #define S_TXIF_RESET 12 11360 #define V_TXIF_RESET(x) ((x) << S_TXIF_RESET) 11361 #define F_TXIF_RESET V_TXIF_RESET(1U) 11362 11363 #define S_RXIF_RESET 11 11364 #define V_RXIF_RESET(x) ((x) << S_RXIF_RESET) 11365 #define F_RXIF_RESET V_RXIF_RESET(1U) 11366 11367 #define S_AUXEXT_RESET 10 11368 #define V_AUXEXT_RESET(x) ((x) << S_AUXEXT_RESET) 11369 #define F_AUXEXT_RESET V_AUXEXT_RESET(1U) 11370 11371 #define S_MTIPSD3TXRST 9 11372 #define V_MTIPSD3TXRST(x) ((x) << S_MTIPSD3TXRST) 11373 #define F_MTIPSD3TXRST V_MTIPSD3TXRST(1U) 11374 11375 #define S_MTIPSD2TXRST 8 11376 #define V_MTIPSD2TXRST(x) ((x) << S_MTIPSD2TXRST) 11377 #define F_MTIPSD2TXRST V_MTIPSD2TXRST(1U) 11378 11379 #define S_MTIPSD1TXRST 7 11380 #define V_MTIPSD1TXRST(x) ((x) << S_MTIPSD1TXRST) 11381 #define F_MTIPSD1TXRST V_MTIPSD1TXRST(1U) 11382 11383 #define S_MTIPSD0TXRST 6 11384 #define V_MTIPSD0TXRST(x) ((x) << S_MTIPSD0TXRST) 11385 #define F_MTIPSD0TXRST V_MTIPSD0TXRST(1U) 11386 11387 #define S_MTIPSD3RXRST 5 11388 #define V_MTIPSD3RXRST(x) ((x) << S_MTIPSD3RXRST) 11389 #define F_MTIPSD3RXRST V_MTIPSD3RXRST(1U) 11390 11391 #define S_MTIPSD2RXRST 4 11392 #define V_MTIPSD2RXRST(x) ((x) << S_MTIPSD2RXRST) 11393 #define F_MTIPSD2RXRST V_MTIPSD2RXRST(1U) 11394 11395 #define S_MTIPSD1RXRST 3 11396 #define V_MTIPSD1RXRST(x) ((x) << S_MTIPSD1RXRST) 11397 #define F_MTIPSD1RXRST V_MTIPSD1RXRST(1U) 11398 11399 #define S_WOL_RESET 2 11400 #define V_WOL_RESET(x) ((x) << S_WOL_RESET) 11401 #define F_WOL_RESET V_WOL_RESET(1U) 11402 11403 #define S_MTIPSD0RXRST 1 11404 #define V_MTIPSD0RXRST(x) ((x) << S_MTIPSD0RXRST) 11405 #define F_MTIPSD0RXRST V_MTIPSD0RXRST(1U) 11406 11407 #define S_HSS_RESET 0 11408 #define V_HSS_RESET(x) ((x) << S_HSS_RESET) 11409 #define F_HSS_RESET V_HSS_RESET(1U) 11410 11411 #define A_MAC_PORT_PKT_COUNT 0x81c 11412 11413 #define S_TX_SOP_COUNT 24 11414 #define M_TX_SOP_COUNT 0xffU 11415 #define V_TX_SOP_COUNT(x) ((x) << S_TX_SOP_COUNT) 11416 #define G_TX_SOP_COUNT(x) (((x) >> S_TX_SOP_COUNT) & M_TX_SOP_COUNT) 11417 11418 #define S_TX_EOP_COUNT 16 11419 #define M_TX_EOP_COUNT 0xffU 11420 #define V_TX_EOP_COUNT(x) ((x) << S_TX_EOP_COUNT) 11421 #define G_TX_EOP_COUNT(x) (((x) >> S_TX_EOP_COUNT) & M_TX_EOP_COUNT) 11422 11423 #define S_RX_SOP_COUNT 8 11424 #define M_RX_SOP_COUNT 0xffU 11425 #define V_RX_SOP_COUNT(x) ((x) << S_RX_SOP_COUNT) 11426 #define G_RX_SOP_COUNT(x) (((x) >> S_RX_SOP_COUNT) & M_RX_SOP_COUNT) 11427 11428 #define S_RX_EOP_COUNT 0 11429 #define M_RX_EOP_COUNT 0xffU 11430 #define V_RX_EOP_COUNT(x) ((x) << S_RX_EOP_COUNT) 11431 #define G_RX_EOP_COUNT(x) (((x) >> S_RX_EOP_COUNT) & M_RX_EOP_COUNT) 11432 11433 #define A_MAC_PORT_MTIP_RESET_CTRL 0x82c 11434 11435 #define S_AN_RESET_SD_TX_CLK 31 11436 #define V_AN_RESET_SD_TX_CLK(x) ((x) << S_AN_RESET_SD_TX_CLK) 11437 #define F_AN_RESET_SD_TX_CLK V_AN_RESET_SD_TX_CLK(1U) 11438 11439 #define S_AN_RESET_SD_RX_CLK 30 11440 #define V_AN_RESET_SD_RX_CLK(x) ((x) << S_AN_RESET_SD_RX_CLK) 11441 #define F_AN_RESET_SD_RX_CLK V_AN_RESET_SD_RX_CLK(1U) 11442 11443 #define S_SGMII_RESET_TX_CLK 29 11444 #define V_SGMII_RESET_TX_CLK(x) ((x) << S_SGMII_RESET_TX_CLK) 11445 #define F_SGMII_RESET_TX_CLK V_SGMII_RESET_TX_CLK(1U) 11446 11447 #define S_SGMII_RESET_RX_CLK 28 11448 #define V_SGMII_RESET_RX_CLK(x) ((x) << S_SGMII_RESET_RX_CLK) 11449 #define F_SGMII_RESET_RX_CLK V_SGMII_RESET_RX_CLK(1U) 11450 11451 #define S_SGMII_RESET_REF_CLK 27 11452 #define V_SGMII_RESET_REF_CLK(x) ((x) << S_SGMII_RESET_REF_CLK) 11453 #define F_SGMII_RESET_REF_CLK V_SGMII_RESET_REF_CLK(1U) 11454 11455 #define S_PCS10G_RESET_XFI_RXCLK 26 11456 #define V_PCS10G_RESET_XFI_RXCLK(x) ((x) << S_PCS10G_RESET_XFI_RXCLK) 11457 #define F_PCS10G_RESET_XFI_RXCLK V_PCS10G_RESET_XFI_RXCLK(1U) 11458 11459 #define S_PCS10G_RESET_XFI_TXCLK 25 11460 #define V_PCS10G_RESET_XFI_TXCLK(x) ((x) << S_PCS10G_RESET_XFI_TXCLK) 11461 #define F_PCS10G_RESET_XFI_TXCLK V_PCS10G_RESET_XFI_TXCLK(1U) 11462 11463 #define S_PCS10G_RESET_SD_TX_CLK 24 11464 #define V_PCS10G_RESET_SD_TX_CLK(x) ((x) << S_PCS10G_RESET_SD_TX_CLK) 11465 #define F_PCS10G_RESET_SD_TX_CLK V_PCS10G_RESET_SD_TX_CLK(1U) 11466 11467 #define S_PCS10G_RESET_SD_RX_CLK 23 11468 #define V_PCS10G_RESET_SD_RX_CLK(x) ((x) << S_PCS10G_RESET_SD_RX_CLK) 11469 #define F_PCS10G_RESET_SD_RX_CLK V_PCS10G_RESET_SD_RX_CLK(1U) 11470 11471 #define S_PCS40G_RESET_RXCLK 22 11472 #define V_PCS40G_RESET_RXCLK(x) ((x) << S_PCS40G_RESET_RXCLK) 11473 #define F_PCS40G_RESET_RXCLK V_PCS40G_RESET_RXCLK(1U) 11474 11475 #define S_PCS40G_RESET_SD_TX_CLK 21 11476 #define V_PCS40G_RESET_SD_TX_CLK(x) ((x) << S_PCS40G_RESET_SD_TX_CLK) 11477 #define F_PCS40G_RESET_SD_TX_CLK V_PCS40G_RESET_SD_TX_CLK(1U) 11478 11479 #define S_PCS40G_RESET_SD0_RX_CLK 20 11480 #define V_PCS40G_RESET_SD0_RX_CLK(x) ((x) << S_PCS40G_RESET_SD0_RX_CLK) 11481 #define F_PCS40G_RESET_SD0_RX_CLK V_PCS40G_RESET_SD0_RX_CLK(1U) 11482 11483 #define S_PCS40G_RESET_SD1_RX_CLK 19 11484 #define V_PCS40G_RESET_SD1_RX_CLK(x) ((x) << S_PCS40G_RESET_SD1_RX_CLK) 11485 #define F_PCS40G_RESET_SD1_RX_CLK V_PCS40G_RESET_SD1_RX_CLK(1U) 11486 11487 #define S_PCS40G_RESET_SD2_RX_CLK 18 11488 #define V_PCS40G_RESET_SD2_RX_CLK(x) ((x) << S_PCS40G_RESET_SD2_RX_CLK) 11489 #define F_PCS40G_RESET_SD2_RX_CLK V_PCS40G_RESET_SD2_RX_CLK(1U) 11490 11491 #define S_PCS40G_RESET_SD3_RX_CLK 17 11492 #define V_PCS40G_RESET_SD3_RX_CLK(x) ((x) << S_PCS40G_RESET_SD3_RX_CLK) 11493 #define F_PCS40G_RESET_SD3_RX_CLK V_PCS40G_RESET_SD3_RX_CLK(1U) 11494 11495 #define S_PCS100G_RESET_CGMII_RXCLK 16 11496 #define V_PCS100G_RESET_CGMII_RXCLK(x) ((x) << S_PCS100G_RESET_CGMII_RXCLK) 11497 #define F_PCS100G_RESET_CGMII_RXCLK V_PCS100G_RESET_CGMII_RXCLK(1U) 11498 11499 #define S_PCS100G_RESET_CGMII_TXCLK 15 11500 #define V_PCS100G_RESET_CGMII_TXCLK(x) ((x) << S_PCS100G_RESET_CGMII_TXCLK) 11501 #define F_PCS100G_RESET_CGMII_TXCLK V_PCS100G_RESET_CGMII_TXCLK(1U) 11502 11503 #define S_PCS100G_RESET_TX_CLK 14 11504 #define V_PCS100G_RESET_TX_CLK(x) ((x) << S_PCS100G_RESET_TX_CLK) 11505 #define F_PCS100G_RESET_TX_CLK V_PCS100G_RESET_TX_CLK(1U) 11506 11507 #define S_PCS100G_RESET_SD0_RX_CLK 13 11508 #define V_PCS100G_RESET_SD0_RX_CLK(x) ((x) << S_PCS100G_RESET_SD0_RX_CLK) 11509 #define F_PCS100G_RESET_SD0_RX_CLK V_PCS100G_RESET_SD0_RX_CLK(1U) 11510 11511 #define S_PCS100G_RESET_SD1_RX_CLK 12 11512 #define V_PCS100G_RESET_SD1_RX_CLK(x) ((x) << S_PCS100G_RESET_SD1_RX_CLK) 11513 #define F_PCS100G_RESET_SD1_RX_CLK V_PCS100G_RESET_SD1_RX_CLK(1U) 11514 11515 #define S_PCS100G_RESET_SD2_RX_CLK 11 11516 #define V_PCS100G_RESET_SD2_RX_CLK(x) ((x) << S_PCS100G_RESET_SD2_RX_CLK) 11517 #define F_PCS100G_RESET_SD2_RX_CLK V_PCS100G_RESET_SD2_RX_CLK(1U) 11518 11519 #define S_PCS100G_RESET_SD3_RX_CLK 10 11520 #define V_PCS100G_RESET_SD3_RX_CLK(x) ((x) << S_PCS100G_RESET_SD3_RX_CLK) 11521 #define F_PCS100G_RESET_SD3_RX_CLK V_PCS100G_RESET_SD3_RX_CLK(1U) 11522 11523 #define S_MAC40G100G_RESET_TXCLK 9 11524 #define V_MAC40G100G_RESET_TXCLK(x) ((x) << S_MAC40G100G_RESET_TXCLK) 11525 #define F_MAC40G100G_RESET_TXCLK V_MAC40G100G_RESET_TXCLK(1U) 11526 11527 #define S_MAC40G100G_RESET_RXCLK 8 11528 #define V_MAC40G100G_RESET_RXCLK(x) ((x) << S_MAC40G100G_RESET_RXCLK) 11529 #define F_MAC40G100G_RESET_RXCLK V_MAC40G100G_RESET_RXCLK(1U) 11530 11531 #define S_MAC40G100G_RESET_FF_TX_CLK 7 11532 #define V_MAC40G100G_RESET_FF_TX_CLK(x) ((x) << S_MAC40G100G_RESET_FF_TX_CLK) 11533 #define F_MAC40G100G_RESET_FF_TX_CLK V_MAC40G100G_RESET_FF_TX_CLK(1U) 11534 11535 #define S_MAC40G100G_RESET_FF_RX_CLK 6 11536 #define V_MAC40G100G_RESET_FF_RX_CLK(x) ((x) << S_MAC40G100G_RESET_FF_RX_CLK) 11537 #define F_MAC40G100G_RESET_FF_RX_CLK V_MAC40G100G_RESET_FF_RX_CLK(1U) 11538 11539 #define S_MAC40G100G_RESET_TS_CLK 5 11540 #define V_MAC40G100G_RESET_TS_CLK(x) ((x) << S_MAC40G100G_RESET_TS_CLK) 11541 #define F_MAC40G100G_RESET_TS_CLK V_MAC40G100G_RESET_TS_CLK(1U) 11542 11543 #define S_MAC1G10G_RESET_RXCLK 4 11544 #define V_MAC1G10G_RESET_RXCLK(x) ((x) << S_MAC1G10G_RESET_RXCLK) 11545 #define F_MAC1G10G_RESET_RXCLK V_MAC1G10G_RESET_RXCLK(1U) 11546 11547 #define S_MAC1G10G_RESET_TXCLK 3 11548 #define V_MAC1G10G_RESET_TXCLK(x) ((x) << S_MAC1G10G_RESET_TXCLK) 11549 #define F_MAC1G10G_RESET_TXCLK V_MAC1G10G_RESET_TXCLK(1U) 11550 11551 #define S_MAC1G10G_RESET_FF_RX_CLK 2 11552 #define V_MAC1G10G_RESET_FF_RX_CLK(x) ((x) << S_MAC1G10G_RESET_FF_RX_CLK) 11553 #define F_MAC1G10G_RESET_FF_RX_CLK V_MAC1G10G_RESET_FF_RX_CLK(1U) 11554 11555 #define S_MAC1G10G_RESET_FF_TX_CLK 1 11556 #define V_MAC1G10G_RESET_FF_TX_CLK(x) ((x) << S_MAC1G10G_RESET_FF_TX_CLK) 11557 #define F_MAC1G10G_RESET_FF_TX_CLK V_MAC1G10G_RESET_FF_TX_CLK(1U) 11558 11559 #define S_XGMII_CLK_RESET 0 11560 #define V_XGMII_CLK_RESET(x) ((x) << S_XGMII_CLK_RESET) 11561 #define F_XGMII_CLK_RESET V_XGMII_CLK_RESET(1U) 11562 11563 #define A_MAC_PORT_MTIP_GATE_CTRL 0x830 11564 11565 #define S_AN_GATE_SD_TX_CLK 31 11566 #define V_AN_GATE_SD_TX_CLK(x) ((x) << S_AN_GATE_SD_TX_CLK) 11567 #define F_AN_GATE_SD_TX_CLK V_AN_GATE_SD_TX_CLK(1U) 11568 11569 #define S_AN_GATE_SD_RX_CLK 30 11570 #define V_AN_GATE_SD_RX_CLK(x) ((x) << S_AN_GATE_SD_RX_CLK) 11571 #define F_AN_GATE_SD_RX_CLK V_AN_GATE_SD_RX_CLK(1U) 11572 11573 #define S_SGMII_GATE_TX_CLK 29 11574 #define V_SGMII_GATE_TX_CLK(x) ((x) << S_SGMII_GATE_TX_CLK) 11575 #define F_SGMII_GATE_TX_CLK V_SGMII_GATE_TX_CLK(1U) 11576 11577 #define S_SGMII_GATE_RX_CLK 28 11578 #define V_SGMII_GATE_RX_CLK(x) ((x) << S_SGMII_GATE_RX_CLK) 11579 #define F_SGMII_GATE_RX_CLK V_SGMII_GATE_RX_CLK(1U) 11580 11581 #define S_SGMII_GATE_REF_CLK 27 11582 #define V_SGMII_GATE_REF_CLK(x) ((x) << S_SGMII_GATE_REF_CLK) 11583 #define F_SGMII_GATE_REF_CLK V_SGMII_GATE_REF_CLK(1U) 11584 11585 #define S_PCS10G_GATE_XFI_RXCLK 26 11586 #define V_PCS10G_GATE_XFI_RXCLK(x) ((x) << S_PCS10G_GATE_XFI_RXCLK) 11587 #define F_PCS10G_GATE_XFI_RXCLK V_PCS10G_GATE_XFI_RXCLK(1U) 11588 11589 #define S_PCS10G_GATE_XFI_TXCLK 25 11590 #define V_PCS10G_GATE_XFI_TXCLK(x) ((x) << S_PCS10G_GATE_XFI_TXCLK) 11591 #define F_PCS10G_GATE_XFI_TXCLK V_PCS10G_GATE_XFI_TXCLK(1U) 11592 11593 #define S_PCS10G_GATE_SD_TX_CLK 24 11594 #define V_PCS10G_GATE_SD_TX_CLK(x) ((x) << S_PCS10G_GATE_SD_TX_CLK) 11595 #define F_PCS10G_GATE_SD_TX_CLK V_PCS10G_GATE_SD_TX_CLK(1U) 11596 11597 #define S_PCS10G_GATE_SD_RX_CLK 23 11598 #define V_PCS10G_GATE_SD_RX_CLK(x) ((x) << S_PCS10G_GATE_SD_RX_CLK) 11599 #define F_PCS10G_GATE_SD_RX_CLK V_PCS10G_GATE_SD_RX_CLK(1U) 11600 11601 #define S_PCS40G_GATE_RXCLK 22 11602 #define V_PCS40G_GATE_RXCLK(x) ((x) << S_PCS40G_GATE_RXCLK) 11603 #define F_PCS40G_GATE_RXCLK V_PCS40G_GATE_RXCLK(1U) 11604 11605 #define S_PCS40G_GATE_SD_TX_CLK 21 11606 #define V_PCS40G_GATE_SD_TX_CLK(x) ((x) << S_PCS40G_GATE_SD_TX_CLK) 11607 #define F_PCS40G_GATE_SD_TX_CLK V_PCS40G_GATE_SD_TX_CLK(1U) 11608 11609 #define S_PCS40G_GATE_SD_RX_CLK 20 11610 #define V_PCS40G_GATE_SD_RX_CLK(x) ((x) << S_PCS40G_GATE_SD_RX_CLK) 11611 #define F_PCS40G_GATE_SD_RX_CLK V_PCS40G_GATE_SD_RX_CLK(1U) 11612 11613 #define S_PCS100G_GATE_CGMII_RXCLK 19 11614 #define V_PCS100G_GATE_CGMII_RXCLK(x) ((x) << S_PCS100G_GATE_CGMII_RXCLK) 11615 #define F_PCS100G_GATE_CGMII_RXCLK V_PCS100G_GATE_CGMII_RXCLK(1U) 11616 11617 #define S_PCS100G_GATE_CGMII_TXCLK 18 11618 #define V_PCS100G_GATE_CGMII_TXCLK(x) ((x) << S_PCS100G_GATE_CGMII_TXCLK) 11619 #define F_PCS100G_GATE_CGMII_TXCLK V_PCS100G_GATE_CGMII_TXCLK(1U) 11620 11621 #define S_PCS100G_GATE_TX_CLK 17 11622 #define V_PCS100G_GATE_TX_CLK(x) ((x) << S_PCS100G_GATE_TX_CLK) 11623 #define F_PCS100G_GATE_TX_CLK V_PCS100G_GATE_TX_CLK(1U) 11624 11625 #define S_PCS100G_GATE_SD_RX_CLK 16 11626 #define V_PCS100G_GATE_SD_RX_CLK(x) ((x) << S_PCS100G_GATE_SD_RX_CLK) 11627 #define F_PCS100G_GATE_SD_RX_CLK V_PCS100G_GATE_SD_RX_CLK(1U) 11628 11629 #define S_MAC40G100G_GATE_TXCLK 15 11630 #define V_MAC40G100G_GATE_TXCLK(x) ((x) << S_MAC40G100G_GATE_TXCLK) 11631 #define F_MAC40G100G_GATE_TXCLK V_MAC40G100G_GATE_TXCLK(1U) 11632 11633 #define S_MAC40G100G_GATE_RXCLK 14 11634 #define V_MAC40G100G_GATE_RXCLK(x) ((x) << S_MAC40G100G_GATE_RXCLK) 11635 #define F_MAC40G100G_GATE_RXCLK V_MAC40G100G_GATE_RXCLK(1U) 11636 11637 #define S_MAC40G100G_GATE_FF_TX_CLK 13 11638 #define V_MAC40G100G_GATE_FF_TX_CLK(x) ((x) << S_MAC40G100G_GATE_FF_TX_CLK) 11639 #define F_MAC40G100G_GATE_FF_TX_CLK V_MAC40G100G_GATE_FF_TX_CLK(1U) 11640 11641 #define S_MAC40G100G_GATE_FF_RX_CLK 12 11642 #define V_MAC40G100G_GATE_FF_RX_CLK(x) ((x) << S_MAC40G100G_GATE_FF_RX_CLK) 11643 #define F_MAC40G100G_GATE_FF_RX_CLK V_MAC40G100G_GATE_FF_RX_CLK(1U) 11644 11645 #define S_MAC40G100G_TS_CLK 11 11646 #define V_MAC40G100G_TS_CLK(x) ((x) << S_MAC40G100G_TS_CLK) 11647 #define F_MAC40G100G_TS_CLK V_MAC40G100G_TS_CLK(1U) 11648 11649 #define S_MAC1G10G_GATE_RXCLK 10 11650 #define V_MAC1G10G_GATE_RXCLK(x) ((x) << S_MAC1G10G_GATE_RXCLK) 11651 #define F_MAC1G10G_GATE_RXCLK V_MAC1G10G_GATE_RXCLK(1U) 11652 11653 #define S_MAC1G10G_GATE_TXCLK 9 11654 #define V_MAC1G10G_GATE_TXCLK(x) ((x) << S_MAC1G10G_GATE_TXCLK) 11655 #define F_MAC1G10G_GATE_TXCLK V_MAC1G10G_GATE_TXCLK(1U) 11656 11657 #define S_MAC1G10G_GATE_FF_RX_CLK 8 11658 #define V_MAC1G10G_GATE_FF_RX_CLK(x) ((x) << S_MAC1G10G_GATE_FF_RX_CLK) 11659 #define F_MAC1G10G_GATE_FF_RX_CLK V_MAC1G10G_GATE_FF_RX_CLK(1U) 11660 11661 #define S_MAC1G10G_GATE_FF_TX_CLK 7 11662 #define V_MAC1G10G_GATE_FF_TX_CLK(x) ((x) << S_MAC1G10G_GATE_FF_TX_CLK) 11663 #define F_MAC1G10G_GATE_FF_TX_CLK V_MAC1G10G_GATE_FF_TX_CLK(1U) 11664 11665 #define S_AEC_RX 6 11666 #define V_AEC_RX(x) ((x) << S_AEC_RX) 11667 #define F_AEC_RX V_AEC_RX(1U) 11668 11669 #define S_AEC_TX 5 11670 #define V_AEC_TX(x) ((x) << S_AEC_TX) 11671 #define F_AEC_TX V_AEC_TX(1U) 11672 11673 #define S_PCS100G_CLK_ENABLE 4 11674 #define V_PCS100G_CLK_ENABLE(x) ((x) << S_PCS100G_CLK_ENABLE) 11675 #define F_PCS100G_CLK_ENABLE V_PCS100G_CLK_ENABLE(1U) 11676 11677 #define S_PCS40G_CLK_ENABLE 3 11678 #define V_PCS40G_CLK_ENABLE(x) ((x) << S_PCS40G_CLK_ENABLE) 11679 #define F_PCS40G_CLK_ENABLE V_PCS40G_CLK_ENABLE(1U) 11680 11681 #define S_PCS10G_CLK_ENABLE 2 11682 #define V_PCS10G_CLK_ENABLE(x) ((x) << S_PCS10G_CLK_ENABLE) 11683 #define F_PCS10G_CLK_ENABLE V_PCS10G_CLK_ENABLE(1U) 11684 11685 #define S_PCS1G_CLK_ENABLE 1 11686 #define V_PCS1G_CLK_ENABLE(x) ((x) << S_PCS1G_CLK_ENABLE) 11687 #define F_PCS1G_CLK_ENABLE V_PCS1G_CLK_ENABLE(1U) 11688 11689 #define S_AN_CLK_ENABLE 0 11690 #define V_AN_CLK_ENABLE(x) ((x) << S_AN_CLK_ENABLE) 11691 #define F_AN_CLK_ENABLE V_AN_CLK_ENABLE(1U) 11692 11693 #define A_MAC_PORT_PERR_INT_CAUSE_100G 0x888 11694 11695 #define S_PERR_RX_FEC100G_DLY 29 11696 #define V_PERR_RX_FEC100G_DLY(x) ((x) << S_PERR_RX_FEC100G_DLY) 11697 #define F_PERR_RX_FEC100G_DLY V_PERR_RX_FEC100G_DLY(1U) 11698 11699 #define S_PERR_RX_FEC100G 28 11700 #define V_PERR_RX_FEC100G(x) ((x) << S_PERR_RX_FEC100G) 11701 #define F_PERR_RX_FEC100G V_PERR_RX_FEC100G(1U) 11702 11703 #define S_PERR_RX3_FEC100G_DK 27 11704 #define V_PERR_RX3_FEC100G_DK(x) ((x) << S_PERR_RX3_FEC100G_DK) 11705 #define F_PERR_RX3_FEC100G_DK V_PERR_RX3_FEC100G_DK(1U) 11706 11707 #define S_PERR_RX2_FEC100G_DK 26 11708 #define V_PERR_RX2_FEC100G_DK(x) ((x) << S_PERR_RX2_FEC100G_DK) 11709 #define F_PERR_RX2_FEC100G_DK V_PERR_RX2_FEC100G_DK(1U) 11710 11711 #define S_PERR_RX1_FEC100G_DK 25 11712 #define V_PERR_RX1_FEC100G_DK(x) ((x) << S_PERR_RX1_FEC100G_DK) 11713 #define F_PERR_RX1_FEC100G_DK V_PERR_RX1_FEC100G_DK(1U) 11714 11715 #define S_PERR_RX0_FEC100G_DK 24 11716 #define V_PERR_RX0_FEC100G_DK(x) ((x) << S_PERR_RX0_FEC100G_DK) 11717 #define F_PERR_RX0_FEC100G_DK V_PERR_RX0_FEC100G_DK(1U) 11718 11719 #define S_PERR_TX3_PCS100G 23 11720 #define V_PERR_TX3_PCS100G(x) ((x) << S_PERR_TX3_PCS100G) 11721 #define F_PERR_TX3_PCS100G V_PERR_TX3_PCS100G(1U) 11722 11723 #define S_PERR_TX2_PCS100G 22 11724 #define V_PERR_TX2_PCS100G(x) ((x) << S_PERR_TX2_PCS100G) 11725 #define F_PERR_TX2_PCS100G V_PERR_TX2_PCS100G(1U) 11726 11727 #define S_PERR_TX1_PCS100G 21 11728 #define V_PERR_TX1_PCS100G(x) ((x) << S_PERR_TX1_PCS100G) 11729 #define F_PERR_TX1_PCS100G V_PERR_TX1_PCS100G(1U) 11730 11731 #define S_PERR_TX0_PCS100G 20 11732 #define V_PERR_TX0_PCS100G(x) ((x) << S_PERR_TX0_PCS100G) 11733 #define F_PERR_TX0_PCS100G V_PERR_TX0_PCS100G(1U) 11734 11735 #define S_PERR_RX19_PCS100G 19 11736 #define V_PERR_RX19_PCS100G(x) ((x) << S_PERR_RX19_PCS100G) 11737 #define F_PERR_RX19_PCS100G V_PERR_RX19_PCS100G(1U) 11738 11739 #define S_PERR_RX18_PCS100G 18 11740 #define V_PERR_RX18_PCS100G(x) ((x) << S_PERR_RX18_PCS100G) 11741 #define F_PERR_RX18_PCS100G V_PERR_RX18_PCS100G(1U) 11742 11743 #define S_PERR_RX17_PCS100G 17 11744 #define V_PERR_RX17_PCS100G(x) ((x) << S_PERR_RX17_PCS100G) 11745 #define F_PERR_RX17_PCS100G V_PERR_RX17_PCS100G(1U) 11746 11747 #define S_PERR_RX16_PCS100G 16 11748 #define V_PERR_RX16_PCS100G(x) ((x) << S_PERR_RX16_PCS100G) 11749 #define F_PERR_RX16_PCS100G V_PERR_RX16_PCS100G(1U) 11750 11751 #define S_PERR_RX15_PCS100G 15 11752 #define V_PERR_RX15_PCS100G(x) ((x) << S_PERR_RX15_PCS100G) 11753 #define F_PERR_RX15_PCS100G V_PERR_RX15_PCS100G(1U) 11754 11755 #define S_PERR_RX14_PCS100G 14 11756 #define V_PERR_RX14_PCS100G(x) ((x) << S_PERR_RX14_PCS100G) 11757 #define F_PERR_RX14_PCS100G V_PERR_RX14_PCS100G(1U) 11758 11759 #define S_PERR_RX13_PCS100G 13 11760 #define V_PERR_RX13_PCS100G(x) ((x) << S_PERR_RX13_PCS100G) 11761 #define F_PERR_RX13_PCS100G V_PERR_RX13_PCS100G(1U) 11762 11763 #define S_PERR_RX12_PCS100G 12 11764 #define V_PERR_RX12_PCS100G(x) ((x) << S_PERR_RX12_PCS100G) 11765 #define F_PERR_RX12_PCS100G V_PERR_RX12_PCS100G(1U) 11766 11767 #define S_PERR_RX11_PCS100G 11 11768 #define V_PERR_RX11_PCS100G(x) ((x) << S_PERR_RX11_PCS100G) 11769 #define F_PERR_RX11_PCS100G V_PERR_RX11_PCS100G(1U) 11770 11771 #define S_PERR_RX10_PCS100G 10 11772 #define V_PERR_RX10_PCS100G(x) ((x) << S_PERR_RX10_PCS100G) 11773 #define F_PERR_RX10_PCS100G V_PERR_RX10_PCS100G(1U) 11774 11775 #define S_PERR_RX9_PCS100G 9 11776 #define V_PERR_RX9_PCS100G(x) ((x) << S_PERR_RX9_PCS100G) 11777 #define F_PERR_RX9_PCS100G V_PERR_RX9_PCS100G(1U) 11778 11779 #define S_PERR_RX8_PCS100G 8 11780 #define V_PERR_RX8_PCS100G(x) ((x) << S_PERR_RX8_PCS100G) 11781 #define F_PERR_RX8_PCS100G V_PERR_RX8_PCS100G(1U) 11782 11783 #define S_PERR_RX7_PCS100G 7 11784 #define V_PERR_RX7_PCS100G(x) ((x) << S_PERR_RX7_PCS100G) 11785 #define F_PERR_RX7_PCS100G V_PERR_RX7_PCS100G(1U) 11786 11787 #define S_PERR_RX6_PCS100G 6 11788 #define V_PERR_RX6_PCS100G(x) ((x) << S_PERR_RX6_PCS100G) 11789 #define F_PERR_RX6_PCS100G V_PERR_RX6_PCS100G(1U) 11790 11791 #define S_PERR_RX5_PCS100G 5 11792 #define V_PERR_RX5_PCS100G(x) ((x) << S_PERR_RX5_PCS100G) 11793 #define F_PERR_RX5_PCS100G V_PERR_RX5_PCS100G(1U) 11794 11795 #define S_PERR_RX4_PCS100G 4 11796 #define V_PERR_RX4_PCS100G(x) ((x) << S_PERR_RX4_PCS100G) 11797 #define F_PERR_RX4_PCS100G V_PERR_RX4_PCS100G(1U) 11798 11799 #define S_PERR_RX3_PCS100G 3 11800 #define V_PERR_RX3_PCS100G(x) ((x) << S_PERR_RX3_PCS100G) 11801 #define F_PERR_RX3_PCS100G V_PERR_RX3_PCS100G(1U) 11802 11803 #define S_PERR_RX2_PCS100G 2 11804 #define V_PERR_RX2_PCS100G(x) ((x) << S_PERR_RX2_PCS100G) 11805 #define F_PERR_RX2_PCS100G V_PERR_RX2_PCS100G(1U) 11806 11807 #define S_PERR_RX1_PCS100G 1 11808 #define V_PERR_RX1_PCS100G(x) ((x) << S_PERR_RX1_PCS100G) 11809 #define F_PERR_RX1_PCS100G V_PERR_RX1_PCS100G(1U) 11810 11811 #define S_PERR_RX0_PCS100G 0 11812 #define V_PERR_RX0_PCS100G(x) ((x) << S_PERR_RX0_PCS100G) 11813 #define F_PERR_RX0_PCS100G V_PERR_RX0_PCS100G(1U) 11814 11815 #define A_MAC_PORT_INT_CAUSE 0x8dc 11816 11817 #define S_TX_TS_AVAIL 29 11818 #define V_TX_TS_AVAIL(x) ((x) << S_TX_TS_AVAIL) 11819 #define F_TX_TS_AVAIL V_TX_TS_AVAIL(1U) 11820 11821 #define S_AN_PAGE_RCVD 2 11822 #define V_AN_PAGE_RCVD(x) ((x) << S_AN_PAGE_RCVD) 11823 #define F_AN_PAGE_RCVD V_AN_PAGE_RCVD(1U) 11824 11825 #define A_MAC_PORT_PERR_INT_CAUSE 0x8e4 11826 11827 #define S_PERR_PKT_RAM 24 11828 #define V_PERR_PKT_RAM(x) ((x) << S_PERR_PKT_RAM) 11829 #define F_PERR_PKT_RAM V_PERR_PKT_RAM(1U) 11830 11831 #define S_PERR_MASK_RAM 23 11832 #define V_PERR_MASK_RAM(x) ((x) << S_PERR_MASK_RAM) 11833 #define F_PERR_MASK_RAM V_PERR_MASK_RAM(1U) 11834 11835 #define S_PERR_CRC_RAM 22 11836 #define V_PERR_CRC_RAM(x) ((x) << S_PERR_CRC_RAM) 11837 #define F_PERR_CRC_RAM V_PERR_CRC_RAM(1U) 11838 11839 #define S_RX_DFF_SEG0 21 11840 #define V_RX_DFF_SEG0(x) ((x) << S_RX_DFF_SEG0) 11841 #define F_RX_DFF_SEG0 V_RX_DFF_SEG0(1U) 11842 11843 #define S_RX_SFF_SEG0 20 11844 #define V_RX_SFF_SEG0(x) ((x) << S_RX_SFF_SEG0) 11845 #define F_RX_SFF_SEG0 V_RX_SFF_SEG0(1U) 11846 11847 #define S_RX_DFF_MAC10 19 11848 #define V_RX_DFF_MAC10(x) ((x) << S_RX_DFF_MAC10) 11849 #define F_RX_DFF_MAC10 V_RX_DFF_MAC10(1U) 11850 11851 #define S_RX_SFF_MAC10 18 11852 #define V_RX_SFF_MAC10(x) ((x) << S_RX_SFF_MAC10) 11853 #define F_RX_SFF_MAC10 V_RX_SFF_MAC10(1U) 11854 11855 #define S_TX_DFF_SEG0 17 11856 #define V_TX_DFF_SEG0(x) ((x) << S_TX_DFF_SEG0) 11857 #define F_TX_DFF_SEG0 V_TX_DFF_SEG0(1U) 11858 11859 #define S_TX_SFF_SEG0 16 11860 #define V_TX_SFF_SEG0(x) ((x) << S_TX_SFF_SEG0) 11861 #define F_TX_SFF_SEG0 V_TX_SFF_SEG0(1U) 11862 11863 #define S_TX_DFF_MAC10 15 11864 #define V_TX_DFF_MAC10(x) ((x) << S_TX_DFF_MAC10) 11865 #define F_TX_DFF_MAC10 V_TX_DFF_MAC10(1U) 11866 11867 #define S_TX_SFF_MAC10 14 11868 #define V_TX_SFF_MAC10(x) ((x) << S_TX_SFF_MAC10) 11869 #define F_TX_SFF_MAC10 V_TX_SFF_MAC10(1U) 11870 11871 #define S_RX_STATS 13 11872 #define V_RX_STATS(x) ((x) << S_RX_STATS) 11873 #define F_RX_STATS V_RX_STATS(1U) 11874 11875 #define S_TX_STATS 12 11876 #define V_TX_STATS(x) ((x) << S_TX_STATS) 11877 #define F_TX_STATS V_TX_STATS(1U) 11878 11879 #define S_PERR3_RX_MIX 11 11880 #define V_PERR3_RX_MIX(x) ((x) << S_PERR3_RX_MIX) 11881 #define F_PERR3_RX_MIX V_PERR3_RX_MIX(1U) 11882 11883 #define S_PERR3_RX_SD 10 11884 #define V_PERR3_RX_SD(x) ((x) << S_PERR3_RX_SD) 11885 #define F_PERR3_RX_SD V_PERR3_RX_SD(1U) 11886 11887 #define S_PERR3_TX 9 11888 #define V_PERR3_TX(x) ((x) << S_PERR3_TX) 11889 #define F_PERR3_TX V_PERR3_TX(1U) 11890 11891 #define S_PERR2_RX_MIX 8 11892 #define V_PERR2_RX_MIX(x) ((x) << S_PERR2_RX_MIX) 11893 #define F_PERR2_RX_MIX V_PERR2_RX_MIX(1U) 11894 11895 #define S_PERR2_RX_SD 7 11896 #define V_PERR2_RX_SD(x) ((x) << S_PERR2_RX_SD) 11897 #define F_PERR2_RX_SD V_PERR2_RX_SD(1U) 11898 11899 #define S_PERR2_TX 6 11900 #define V_PERR2_TX(x) ((x) << S_PERR2_TX) 11901 #define F_PERR2_TX V_PERR2_TX(1U) 11902 11903 #define S_PERR1_RX_MIX 5 11904 #define V_PERR1_RX_MIX(x) ((x) << S_PERR1_RX_MIX) 11905 #define F_PERR1_RX_MIX V_PERR1_RX_MIX(1U) 11906 11907 #define S_PERR1_RX_SD 4 11908 #define V_PERR1_RX_SD(x) ((x) << S_PERR1_RX_SD) 11909 #define F_PERR1_RX_SD V_PERR1_RX_SD(1U) 11910 11911 #define S_PERR1_TX 3 11912 #define V_PERR1_TX(x) ((x) << S_PERR1_TX) 11913 #define F_PERR1_TX V_PERR1_TX(1U) 11914 11915 #define S_PERR0_RX_MIX 2 11916 #define V_PERR0_RX_MIX(x) ((x) << S_PERR0_RX_MIX) 11917 #define F_PERR0_RX_MIX V_PERR0_RX_MIX(1U) 11918 11919 #define S_PERR0_RX_SD 1 11920 #define V_PERR0_RX_SD(x) ((x) << S_PERR0_RX_SD) 11921 #define F_PERR0_RX_SD V_PERR0_RX_SD(1U) 11922 11923 #define S_PERR0_TX 0 11924 #define V_PERR0_TX(x) ((x) << S_PERR0_TX) 11925 #define F_PERR0_TX V_PERR0_TX(1U) 11926 11927 #define S_T6_PERR_PKT_RAM 31 11928 #define V_T6_PERR_PKT_RAM(x) ((x) << S_T6_PERR_PKT_RAM) 11929 #define F_T6_PERR_PKT_RAM V_T6_PERR_PKT_RAM(1U) 11930 11931 #define S_T6_PERR_MASK_RAM 30 11932 #define V_T6_PERR_MASK_RAM(x) ((x) << S_T6_PERR_MASK_RAM) 11933 #define F_T6_PERR_MASK_RAM V_T6_PERR_MASK_RAM(1U) 11934 11935 #define S_T6_PERR_CRC_RAM 29 11936 #define V_T6_PERR_CRC_RAM(x) ((x) << S_T6_PERR_CRC_RAM) 11937 #define F_T6_PERR_CRC_RAM V_T6_PERR_CRC_RAM(1U) 11938 11939 #define S_RX_MAC40G 28 11940 #define V_RX_MAC40G(x) ((x) << S_RX_MAC40G) 11941 #define F_RX_MAC40G V_RX_MAC40G(1U) 11942 11943 #define S_TX_MAC40G 27 11944 #define V_TX_MAC40G(x) ((x) << S_TX_MAC40G) 11945 #define F_TX_MAC40G V_TX_MAC40G(1U) 11946 11947 #define S_RX_ST_MAC40G 26 11948 #define V_RX_ST_MAC40G(x) ((x) << S_RX_ST_MAC40G) 11949 #define F_RX_ST_MAC40G V_RX_ST_MAC40G(1U) 11950 11951 #define S_TX_ST_MAC40G 25 11952 #define V_TX_ST_MAC40G(x) ((x) << S_TX_ST_MAC40G) 11953 #define F_TX_ST_MAC40G V_TX_ST_MAC40G(1U) 11954 11955 #define S_TX_MAC1G10G 24 11956 #define V_TX_MAC1G10G(x) ((x) << S_TX_MAC1G10G) 11957 #define F_TX_MAC1G10G V_TX_MAC1G10G(1U) 11958 11959 #define S_RX_MAC1G10G 23 11960 #define V_RX_MAC1G10G(x) ((x) << S_RX_MAC1G10G) 11961 #define F_RX_MAC1G10G V_RX_MAC1G10G(1U) 11962 11963 #define S_RX_STATUS_MAC1G10G 22 11964 #define V_RX_STATUS_MAC1G10G(x) ((x) << S_RX_STATUS_MAC1G10G) 11965 #define F_RX_STATUS_MAC1G10G V_RX_STATUS_MAC1G10G(1U) 11966 11967 #define S_RX_ST_MAC1G10G 21 11968 #define V_RX_ST_MAC1G10G(x) ((x) << S_RX_ST_MAC1G10G) 11969 #define F_RX_ST_MAC1G10G V_RX_ST_MAC1G10G(1U) 11970 11971 #define S_TX_ST_MAC1G10G 20 11972 #define V_TX_ST_MAC1G10G(x) ((x) << S_TX_ST_MAC1G10G) 11973 #define F_TX_ST_MAC1G10G V_TX_ST_MAC1G10G(1U) 11974 11975 #define S_PERR_TX0_PCS40G 19 11976 #define V_PERR_TX0_PCS40G(x) ((x) << S_PERR_TX0_PCS40G) 11977 #define F_PERR_TX0_PCS40G V_PERR_TX0_PCS40G(1U) 11978 11979 #define S_PERR_TX1_PCS40G 18 11980 #define V_PERR_TX1_PCS40G(x) ((x) << S_PERR_TX1_PCS40G) 11981 #define F_PERR_TX1_PCS40G V_PERR_TX1_PCS40G(1U) 11982 11983 #define S_PERR_TX2_PCS40G 17 11984 #define V_PERR_TX2_PCS40G(x) ((x) << S_PERR_TX2_PCS40G) 11985 #define F_PERR_TX2_PCS40G V_PERR_TX2_PCS40G(1U) 11986 11987 #define S_PERR_TX3_PCS40G 16 11988 #define V_PERR_TX3_PCS40G(x) ((x) << S_PERR_TX3_PCS40G) 11989 #define F_PERR_TX3_PCS40G V_PERR_TX3_PCS40G(1U) 11990 11991 #define S_PERR_TX0_FEC40G 15 11992 #define V_PERR_TX0_FEC40G(x) ((x) << S_PERR_TX0_FEC40G) 11993 #define F_PERR_TX0_FEC40G V_PERR_TX0_FEC40G(1U) 11994 11995 #define S_PERR_TX1_FEC40G 14 11996 #define V_PERR_TX1_FEC40G(x) ((x) << S_PERR_TX1_FEC40G) 11997 #define F_PERR_TX1_FEC40G V_PERR_TX1_FEC40G(1U) 11998 11999 #define S_PERR_TX2_FEC40G 13 12000 #define V_PERR_TX2_FEC40G(x) ((x) << S_PERR_TX2_FEC40G) 12001 #define F_PERR_TX2_FEC40G V_PERR_TX2_FEC40G(1U) 12002 12003 #define S_PERR_TX3_FEC40G 12 12004 #define V_PERR_TX3_FEC40G(x) ((x) << S_PERR_TX3_FEC40G) 12005 #define F_PERR_TX3_FEC40G V_PERR_TX3_FEC40G(1U) 12006 12007 #define S_PERR_RX0_PCS40G 11 12008 #define V_PERR_RX0_PCS40G(x) ((x) << S_PERR_RX0_PCS40G) 12009 #define F_PERR_RX0_PCS40G V_PERR_RX0_PCS40G(1U) 12010 12011 #define S_PERR_RX1_PCS40G 10 12012 #define V_PERR_RX1_PCS40G(x) ((x) << S_PERR_RX1_PCS40G) 12013 #define F_PERR_RX1_PCS40G V_PERR_RX1_PCS40G(1U) 12014 12015 #define S_PERR_RX2_PCS40G 9 12016 #define V_PERR_RX2_PCS40G(x) ((x) << S_PERR_RX2_PCS40G) 12017 #define F_PERR_RX2_PCS40G V_PERR_RX2_PCS40G(1U) 12018 12019 #define S_PERR_RX3_PCS40G 8 12020 #define V_PERR_RX3_PCS40G(x) ((x) << S_PERR_RX3_PCS40G) 12021 #define F_PERR_RX3_PCS40G V_PERR_RX3_PCS40G(1U) 12022 12023 #define S_PERR_RX0_FEC40G 7 12024 #define V_PERR_RX0_FEC40G(x) ((x) << S_PERR_RX0_FEC40G) 12025 #define F_PERR_RX0_FEC40G V_PERR_RX0_FEC40G(1U) 12026 12027 #define S_PERR_RX1_FEC40G 6 12028 #define V_PERR_RX1_FEC40G(x) ((x) << S_PERR_RX1_FEC40G) 12029 #define F_PERR_RX1_FEC40G V_PERR_RX1_FEC40G(1U) 12030 12031 #define S_PERR_RX2_FEC40G 5 12032 #define V_PERR_RX2_FEC40G(x) ((x) << S_PERR_RX2_FEC40G) 12033 #define F_PERR_RX2_FEC40G V_PERR_RX2_FEC40G(1U) 12034 12035 #define S_PERR_RX3_FEC40G 4 12036 #define V_PERR_RX3_FEC40G(x) ((x) << S_PERR_RX3_FEC40G) 12037 #define F_PERR_RX3_FEC40G V_PERR_RX3_FEC40G(1U) 12038 12039 #define S_PERR_RX_PCS10G_LPBK 3 12040 #define V_PERR_RX_PCS10G_LPBK(x) ((x) << S_PERR_RX_PCS10G_LPBK) 12041 #define F_PERR_RX_PCS10G_LPBK V_PERR_RX_PCS10G_LPBK(1U) 12042 12043 #define S_PERR_RX_PCS10G 2 12044 #define V_PERR_RX_PCS10G(x) ((x) << S_PERR_RX_PCS10G) 12045 #define F_PERR_RX_PCS10G V_PERR_RX_PCS10G(1U) 12046 12047 #define S_PERR_RX_PCS1G 1 12048 #define V_PERR_RX_PCS1G(x) ((x) << S_PERR_RX_PCS1G) 12049 #define F_PERR_RX_PCS1G V_PERR_RX_PCS1G(1U) 12050 12051 #define S_PERR_TX_PCS1G 0 12052 #define V_PERR_TX_PCS1G(x) ((x) << S_PERR_TX_PCS1G) 12053 #define F_PERR_TX_PCS1G V_PERR_TX_PCS1G(1U) 12054 12055 #define A_MAC_PORT_TX_TS_VAL_LO 0x928 12056 #define A_MAC_PORT_TX_TS_VAL_HI 0x92c 12057 #define A_MAC_PORT_AFRAMESTRANSMITTEDOK 0xa80 12058 #define A_MAC_PORT_AFRAMESTRANSMITTEDOKHI 0xa84 12059 #define A_MAC_PORT_AFRAMESRECEIVEDOK 0xa88 12060 #define A_MAC_PORT_AFRAMESRECEIVEDOKHI 0xa8c 12061 #define A_MAC_PORT_MTIP_1G10G_RX_FRAMESOK 0xe20 12062 #define A_MAC_PORT_MTIP_1G10G_RX_FRAMESOKHI 0xe24 12063 #define A_MAC_PORT_MTIP_1G10G_TX_FRAMESOKHI 0xf24 12064 #define A_MAC_PORT_MTIP_1G10G_TX_CRCERRORS 0xf28 12065 12066 /* registers for module MC_0 */ 12067 #define MC_0_BASE_ADDR 0x40000 12068 12069 #define A_MC_P_PAR_CAUSE 0x41310 12070 #define A_MC_P_INT_CAUSE 0x41318 12071 #define A_MC_P_ECC_STATUS 0x4131c 12072 #define A_MC_P_BIST_CMD 0x41400 12073 12074 #define S_BURST_LEN 16 12075 #define M_BURST_LEN 0x3U 12076 #define V_BURST_LEN(x) ((x) << S_BURST_LEN) 12077 #define G_BURST_LEN(x) (((x) >> S_BURST_LEN) & M_BURST_LEN) 12078 12079 #define A_MC_P_BIST_CMD_ADDR 0x41404 12080 #define A_MC_P_BIST_CMD_LEN 0x41408 12081 #define A_MC_P_BIST_DATA_PATTERN 0x4140c 12082 #define A_MC_P_BIST_STATUS_RDATA 0x41488 12083 #define A_MC_DDRPHY_DP18_WRCLK_AUX_CNTL 0x4407c 12084 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE 0x45860 12085 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 0x458a0 12086 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 0x458a4 12087 #define A_MC_DDRPHY_APB_MTSTAT_REG0 0x47828 12088 12089 /* registers for module MC_1 */ 12090 #define MC_1_BASE_ADDR 0x48000 12091 12092 /* registers for module EDC_T50 */ 12093 #define EDC_T50_BASE_ADDR 0x50000 12094 12095 #define A_EDC_H_BIST_CMD 0x50004 12096 #define A_EDC_H_BIST_CMD_ADDR 0x50008 12097 #define A_EDC_H_BIST_CMD_LEN 0x5000c 12098 #define A_EDC_H_BIST_DATA_PATTERN 0x50010 12099 #define A_EDC_H_BIST_STATUS_RDATA 0x50028 12100 #define A_EDC_H_INT_CAUSE 0x50078 12101 12102 #define S_ECC_UE_INT0_CAUSE 5 12103 #define V_ECC_UE_INT0_CAUSE(x) ((x) << S_ECC_UE_INT0_CAUSE) 12104 #define F_ECC_UE_INT0_CAUSE V_ECC_UE_INT0_CAUSE(1U) 12105 12106 #define S_ECC_CE_INT0_CAUSE 4 12107 #define V_ECC_CE_INT0_CAUSE(x) ((x) << S_ECC_CE_INT0_CAUSE) 12108 #define F_ECC_CE_INT0_CAUSE V_ECC_CE_INT0_CAUSE(1U) 12109 12110 #define S_PERR_INT0_CAUSE 3 12111 #define V_PERR_INT0_CAUSE(x) ((x) << S_PERR_INT0_CAUSE) 12112 #define F_PERR_INT0_CAUSE V_PERR_INT0_CAUSE(1U) 12113 12114 #define A_EDC_H_ECC_STATUS 0x5007c 12115 #define A_EDC_H_ECC_ERR_ADDR 0x50084 12116 #define A_EDC_H_ECC_ERR_DATA_RDATA 0x50090 12117 12118 /* registers for module EDC_T51 */ 12119 #define EDC_T51_BASE_ADDR 0x50800 12120 12121 /* registers for module HMA_T5 */ 12122 #define HMA_T5_BASE_ADDR 0x51000 12123 12124 12125 /* registers for module EDC_T60 */ 12126 #define EDC_T60_BASE_ADDR 0x50000 12127 12128 #define S_ECC_ADDR 0 12129 #define M_ECC_ADDR 0x7fffffU 12130 #define V_ECC_ADDR(x) ((x) << S_ECC_ADDR) 12131 #define G_ECC_ADDR(x) (((x) >> S_ECC_ADDR) & M_ECC_ADDR) 12132 12133 12134 /* registers for module EDC_T61 */ 12135 #define EDC_T61_BASE_ADDR 0x50800 12136 12137 /* registers for module HMA_T6 */ 12138 #define HMA_T6_BASE_ADDR 0x51000 12139 12140 #define A_HMA_LOCAL_DEBUG_CFG 0x51320 12141