1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4 Ethernet driver. 14 * 15 * Copyright (C) 2009-2013 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23 #ifndef __CXGBE_T4_HW_H 24 #define __CXGBE_T4_HW_H 25 26 #include "osdep.h" 27 28 enum { 29 NCHAN = 4, /* # of HW channels */ 30 MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */ 31 EEPROMSIZE = 17408,/* Serial EEPROM physical size */ 32 EEPROMVSIZE = 32768,/* Serial EEPROM virtual address space size */ 33 EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */ 34 RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */ 35 TCB_SIZE = 128, /* TCB size */ 36 NMTUS = 16, /* size of MTU table */ 37 NCCTRL_WIN = 32, /* # of congestion control windows */ 38 NTX_SCHED = 8, /* # of HW Tx scheduling queues */ 39 PM_NSTATS = 5, /* # of PM stats */ 40 MBOX_LEN = 64, /* mailbox size in bytes */ 41 TRACE_LEN = 112, /* length of trace data and mask */ 42 FILTER_OPT_LEN = 36, /* filter tuple width of optional components */ 43 NWOL_PAT = 8, /* # of WoL patterns */ 44 WOL_PAT_LEN = 128, /* length of WoL patterns */ 45 UDBS_SEG_SIZE = 128, /* Segment size of BAR2 doorbells */ 46 UDBS_SEG_SHIFT = 7, /* log2(UDBS_SEG_SIZE) */ 47 UDBS_DB_OFFSET = 8, /* offset of the 4B doorbell in a segment */ 48 UDBS_WR_OFFSET = 64, /* offset of the work request in a segment */ 49 }; 50 51 enum { 52 CIM_NUM_IBQ = 6, /* # of CIM IBQs */ 53 CIM_NUM_OBQ = 6, /* # of CIM OBQs */ 54 CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */ 55 CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */ 56 CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */ 57 CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */ 58 CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */ 59 CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */ 60 TPLA_SIZE = 128, /* # of 64-bit words in TP LA */ 61 ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */ 62 }; 63 64 enum { 65 SF_PAGE_SIZE = 256, /* serial flash page size */ 66 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */ 67 }; 68 69 /* SGE context types */ 70 enum ctxt_type { CTXT_EGRESS, CTXT_INGRESS, CTXT_FLM, CTXT_CNM }; 71 72 enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */ 73 74 enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */ 75 76 enum { 77 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */ 78 SGE_CTXT_SIZE = 24, /* size of SGE context */ 79 SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */ 80 SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */ 81 SGE_MAX_IQ_SIZE = 65520, 82 }; 83 84 struct sge_qstat { /* data written to SGE queue status entries */ 85 volatile __be32 qid; 86 volatile __be16 cidx; 87 volatile __be16 pidx; 88 }; 89 90 #define S_QSTAT_PIDX 0 91 #define M_QSTAT_PIDX 0xffff 92 #define G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX) 93 94 #define S_QSTAT_CIDX 16 95 #define M_QSTAT_CIDX 0xffff 96 #define G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX) 97 98 /* 99 * Structure for last 128 bits of response descriptors 100 */ 101 struct rsp_ctrl { 102 __be32 hdrbuflen_pidx; 103 __be32 pldbuflen_qid; 104 union { 105 u8 type_gen; 106 __be64 last_flit; 107 } u; 108 }; 109 110 #define S_RSPD_NEWBUF 31 111 #define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF) 112 #define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U) 113 114 #define S_RSPD_LEN 0 115 #define M_RSPD_LEN 0x7fffffff 116 #define V_RSPD_LEN(x) ((x) << S_RSPD_LEN) 117 #define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN) 118 119 #define S_RSPD_QID S_RSPD_LEN 120 #define M_RSPD_QID M_RSPD_LEN 121 #define V_RSPD_QID(x) V_RSPD_LEN(x) 122 #define G_RSPD_QID(x) G_RSPD_LEN(x) 123 124 #define S_RSPD_GEN 7 125 #define V_RSPD_GEN(x) ((x) << S_RSPD_GEN) 126 #define F_RSPD_GEN V_RSPD_GEN(1U) 127 128 #define S_RSPD_QOVFL 6 129 #define V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL) 130 #define F_RSPD_QOVFL V_RSPD_QOVFL(1U) 131 132 #define S_RSPD_TYPE 4 133 #define M_RSPD_TYPE 0x3 134 #define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE) 135 #define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE) 136 137 /* Rx queue interrupt deferral fields: counter enable and timer index */ 138 #define S_QINTR_CNT_EN 0 139 #define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN) 140 #define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U) 141 142 #define S_QINTR_TIMER_IDX 1 143 #define M_QINTR_TIMER_IDX 0x7 144 #define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX) 145 #define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX) 146 147 /* # of pages a pagepod can hold without needing another pagepod */ 148 #define PPOD_PAGES 4U 149 150 struct pagepod { 151 __be64 vld_tid_pgsz_tag_color; 152 __be64 len_offset; 153 __be64 rsvd; 154 __be64 addr[PPOD_PAGES + 1]; 155 }; 156 157 #define S_PPOD_COLOR 0 158 #define M_PPOD_COLOR 0x3F 159 #define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR) 160 161 #define S_PPOD_TAG 6 162 #define M_PPOD_TAG 0xFFFFFF 163 #define V_PPOD_TAG(x) ((x) << S_PPOD_TAG) 164 #define G_PPOD_TAG(x) (((x) >> S_PPOD_TAG) & M_PPOD_TAG) 165 166 #define S_PPOD_PGSZ 30 167 #define M_PPOD_PGSZ 0x3 168 #define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ) 169 #define G_PPOD_PGSZ(x) (((x) >> S_PPOD_PGSZ) & M_PPOD_PGSZ) 170 171 #define S_PPOD_TID 32 172 #define M_PPOD_TID 0xFFFFFF 173 #define V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID) 174 175 #define S_PPOD_VALID 56 176 #define V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID) 177 #define F_PPOD_VALID V_PPOD_VALID(1ULL) 178 179 #define S_PPOD_LEN 32 180 #define M_PPOD_LEN 0xFFFFFFFF 181 #define V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN) 182 183 #define S_PPOD_OFST 0 184 #define M_PPOD_OFST 0xFFFFFFFF 185 #define V_PPOD_OFST(x) ((x) << S_PPOD_OFST) 186 187 /* 188 * Flash layout. 189 */ 190 #define FLASH_START(start) ((start) * SF_SEC_SIZE) 191 #define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE) 192 193 enum { 194 /* 195 * Various Expansion-ROM boot images, etc. 196 */ 197 FLASH_EXP_ROM_START_SEC = 0, 198 FLASH_EXP_ROM_NSECS = 6, 199 FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC), 200 FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS), 201 202 /* 203 * iSCSI Boot Firmware Table (iBFT) and other driver-related 204 * parameters ... 205 */ 206 FLASH_IBFT_START_SEC = 6, 207 FLASH_IBFT_NSECS = 1, 208 FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC), 209 FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS), 210 211 /* 212 * Boot configuration data. 213 */ 214 FLASH_BOOTCFG_START_SEC = 7, 215 FLASH_BOOTCFG_NSECS = 1, 216 FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC), 217 FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS), 218 219 /* 220 * Location of firmware image in FLASH. 221 */ 222 FLASH_FW_START_SEC = 8, 223 FLASH_FW_NSECS = 16, 224 FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC), 225 FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS), 226 227 /* 228 * Location of bootstrap firmware image in FLASH. 229 */ 230 FLASH_FWBOOTSTRAP_START_SEC = 27, 231 FLASH_FWBOOTSTRAP_NSECS = 1, 232 FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC), 233 FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS), 234 235 /* 236 * iSCSI persistent/crash information. 237 */ 238 FLASH_ISCSI_CRASH_START_SEC = 29, 239 FLASH_ISCSI_CRASH_NSECS = 1, 240 FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC), 241 FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS), 242 243 /* 244 * FCoE persistent/crash information. 245 */ 246 FLASH_FCOE_CRASH_START_SEC = 30, 247 FLASH_FCOE_CRASH_NSECS = 1, 248 FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC), 249 FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS), 250 251 /* 252 * Location of Firmware Configuration File in FLASH. Since the FPGA 253 * "FLASH" is smaller we need to store the Configuration File in a 254 * different location -- which will overlap the end of the firmware 255 * image if firmware ever gets that large ... 256 */ 257 FLASH_CFG_START_SEC = 31, 258 FLASH_CFG_NSECS = 1, 259 FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC), 260 FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS), 261 262 FLASH_FPGA_CFG_START_SEC = 15, 263 FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC), 264 265 /* 266 * Sectors 32-63 are reserved for FLASH failover. 267 */ 268 }; 269 270 #undef FLASH_START 271 #undef FLASH_MAX_SIZE 272 273 #endif /* __CXGBE_T4_HW_H */ 274