1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4/T5/T6 Ethernet driver. 14 * 15 * Copyright (C) 2005-2017 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23 #ifndef __CHELSIO_COMMON_H 24 #define __CHELSIO_COMMON_H 25 26 #include "t4_hw.h" 27 #include "t4_chip_type.h" 28 #include "t4fw_version.h" 29 #include "t5fw_version.h" 30 #include "t6fw_version.h" 31 32 #define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC0 | F_EDC0 | \ 33 F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \ 34 F_CPL_SWITCH | F_SGE | F_ULP_TX) 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #ifndef __linux__ 41 #define __force 42 #define usleep_range(_min, _max) msleep(_max / 1000) 43 #endif 44 45 /* 46 * Firmware minimum version macros are used by t4_check_fw_version() to check 47 * if the FW is supported by the driver. 48 * Initially these macros were in t4fw_interface.h, but was removed, as the 49 * file is automatically replaced during a new FW commit. So untill these 50 * macros moves to one of the firmware header files, it has to be here. 51 */ 52 #define T4FW_MIN_VERSION_MAJOR 0x01 53 #define T4FW_MIN_VERSION_MINOR 0x04 54 #define T4FW_MIN_VERSION_MICRO 0x00 55 56 #define T5FW_MIN_VERSION_MAJOR 0x00 57 #define T5FW_MIN_VERSION_MINOR 0x00 58 #define T5FW_MIN_VERSION_MICRO 0x00 59 60 #define T6FW_MIN_VERSION_MAJOR 0x00 61 #define T6FW_MIN_VERSION_MINOR 0x00 62 #define T6FW_MIN_VERSION_MICRO 0x00 63 64 enum { 65 MAX_NPORTS = 4, /* max # of ports */ 66 SERNUM_LEN = 24, /* Serial # length */ 67 EC_LEN = 16, /* E/C length */ 68 ID_LEN = 16, /* ID length */ 69 PN_LEN = 16, /* Part Number length */ 70 MACADDR_LEN = 12, /* MAC Address length */ 71 }; 72 73 enum { 74 T4_REGMAP_SIZE = (160 * 1024), 75 T5_REGMAP_SIZE = (332 * 1024), 76 }; 77 78 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; 79 80 enum { 81 MEMWIN0_APERTURE = 2048, 82 MEMWIN0_BASE = 0x1b800, 83 84 MEMWIN1_APERTURE = 32768, 85 MEMWIN1_BASE = 0x28000, 86 87 MEMWIN2_APERTURE = 65536, 88 MEMWIN2_BASE = 0x30000, 89 90 MEMWIN2_APERTURE_T5 = 128 * 1024, 91 MEMWIN2_BASE_T5 = 0x60000, 92 }; 93 94 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 95 96 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 97 98 enum { 99 PAUSE_RX = 1 << 0, 100 PAUSE_TX = 1 << 1, 101 PAUSE_AUTONEG = 1 << 2 102 }; 103 104 enum { 105 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 106 FEC_RS = 1 << 1, /* Reed-Solomon */ 107 FEC_BASER_RS = 1 << 2, /* BaseR/Reed-Solomon */ 108 }; 109 110 enum { 111 ULP_T10DIF_ISCSI = 1 << 0, 112 ULP_T10DIF_FCOE = 1 << 1 113 }; 114 115 enum { 116 ULP_CRYPTO_LOOKASIDE = 1 << 0, 117 ULP_CRYPTO_INLINE_TLS = 1 << 1 118 }; 119 120 struct port_stats { 121 u64 tx_octets; /* total # of octets in good frames */ 122 u64 tx_frames; /* all good frames */ 123 u64 tx_bcast_frames; /* all broadcast frames */ 124 u64 tx_mcast_frames; /* all multicast frames */ 125 u64 tx_ucast_frames; /* all unicast frames */ 126 u64 tx_error_frames; /* all error frames */ 127 128 u64 tx_frames_64; /* # of Tx frames in a particular range */ 129 u64 tx_frames_65_127; 130 u64 tx_frames_128_255; 131 u64 tx_frames_256_511; 132 u64 tx_frames_512_1023; 133 u64 tx_frames_1024_1518; 134 u64 tx_frames_1519_max; 135 136 u64 tx_drop; /* # of dropped Tx frames */ 137 u64 tx_pause; /* # of transmitted pause frames */ 138 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 139 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 140 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 141 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 142 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 143 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 144 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 145 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 146 147 u64 rx_octets; /* total # of octets in good frames */ 148 u64 rx_frames; /* all good frames */ 149 u64 rx_bcast_frames; /* all broadcast frames */ 150 u64 rx_mcast_frames; /* all multicast frames */ 151 u64 rx_ucast_frames; /* all unicast frames */ 152 u64 rx_too_long; /* # of frames exceeding MTU */ 153 u64 rx_jabber; /* # of jabber frames */ 154 u64 rx_fcs_err; /* # of received frames with bad FCS */ 155 u64 rx_len_err; /* # of received frames with length error */ 156 u64 rx_symbol_err; /* symbol errors */ 157 u64 rx_runt; /* # of short frames */ 158 159 u64 rx_frames_64; /* # of Rx frames in a particular range */ 160 u64 rx_frames_65_127; 161 u64 rx_frames_128_255; 162 u64 rx_frames_256_511; 163 u64 rx_frames_512_1023; 164 u64 rx_frames_1024_1518; 165 u64 rx_frames_1519_max; 166 167 u64 rx_pause; /* # of received pause frames */ 168 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 169 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 170 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 171 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 172 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 173 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 174 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 175 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 176 177 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 178 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 179 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 180 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 181 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 182 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 183 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 184 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 185 }; 186 187 struct lb_port_stats { 188 u64 octets; 189 u64 frames; 190 u64 bcast_frames; 191 u64 mcast_frames; 192 u64 ucast_frames; 193 u64 error_frames; 194 195 u64 frames_64; 196 u64 frames_65_127; 197 u64 frames_128_255; 198 u64 frames_256_511; 199 u64 frames_512_1023; 200 u64 frames_1024_1518; 201 u64 frames_1519_max; 202 203 u64 drop; 204 205 u64 ovflow0; 206 u64 ovflow1; 207 u64 ovflow2; 208 u64 ovflow3; 209 u64 trunc0; 210 u64 trunc1; 211 u64 trunc2; 212 u64 trunc3; 213 }; 214 215 struct tp_tcp_stats { 216 u32 tcp_out_rsts; 217 u64 tcp_in_segs; 218 u64 tcp_out_segs; 219 u64 tcp_retrans_segs; 220 }; 221 222 struct tp_usm_stats { 223 u32 frames; 224 u32 drops; 225 u64 octets; 226 }; 227 228 struct tp_fcoe_stats { 229 u32 frames_ddp; 230 u32 frames_drop; 231 u64 octets_ddp; 232 }; 233 234 struct tp_err_stats { 235 u32 mac_in_errs[4]; 236 u32 hdr_in_errs[4]; 237 u32 tcp_in_errs[4]; 238 u32 tnl_cong_drops[4]; 239 u32 ofld_chan_drops[4]; 240 u32 tnl_tx_drops[4]; 241 u32 ofld_vlan_drops[4]; 242 u32 tcp6_in_errs[4]; 243 u32 ofld_no_neigh; 244 u32 ofld_cong_defer; 245 }; 246 247 struct tp_proxy_stats { 248 u32 proxy[4]; 249 }; 250 251 struct tp_cpl_stats { 252 u32 req[4]; 253 u32 rsp[4]; 254 }; 255 256 struct tp_rdma_stats { 257 u32 rqe_dfr_pkt; 258 u32 rqe_dfr_mod; 259 }; 260 261 struct sge_params { 262 u32 hps; /* host page size for our PF/VF */ 263 u32 eq_qpp; /* egress queues/page for our PF/VF */ 264 u32 iq_qpp; /* egress queues/page for our PF/VF */ 265 }; 266 267 struct tp_params { 268 unsigned int tre; /* log2 of core clocks per TP tick */ 269 unsigned int dack_re; /* DACK timer resolution */ 270 unsigned int la_mask; /* what events are recorded by TP LA */ 271 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 272 273 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 274 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 275 /* cached TP_OUT_CONFIG compressed error vector 276 * and passing outer header info for encapsulated packets. 277 */ 278 int rx_pkt_encap; 279 280 /* 281 * TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 282 * subset of the set of fields which may be present in the Compressed 283 * Filter Tuple portion of filters and TCP TCB connections. The 284 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 285 * Since a variable number of fields may or may not be present, their 286 * shifted field positions within the Compressed Filter Tuple may 287 * vary, or not even be present if the field isn't selected in 288 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 289 * places we store their offsets here, or a -1 if the field isn't 290 * present. 291 */ 292 int fcoe_shift; 293 int port_shift; 294 int vnic_shift; 295 int vlan_shift; 296 int tos_shift; 297 int protocol_shift; 298 int ethertype_shift; 299 int macmatch_shift; 300 int matchtype_shift; 301 int frag_shift; 302 }; 303 304 struct vpd_params { 305 unsigned int cclk; 306 u8 ec[EC_LEN + 1]; 307 u8 sn[SERNUM_LEN + 1]; 308 u8 id[ID_LEN + 1]; 309 u8 pn[PN_LEN + 1]; 310 u8 na[MACADDR_LEN + 1]; 311 }; 312 313 struct pci_params { 314 uint16_t vendor_id; 315 uint16_t device_id; 316 uint32_t vpd_cap_addr; 317 uint16_t speed; 318 uint8_t width; 319 }; 320 321 /* 322 * Firmware device log. 323 */ 324 struct devlog_params { 325 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 326 u32 start; /* start of log in firmware memory */ 327 u32 size; /* size of log */ 328 }; 329 330 /* Stores chip specific parameters */ 331 struct arch_specific_params { 332 u8 nchan; 333 u8 pm_stats_cnt; 334 u8 cng_ch_bits_log; /* congestion channel map bits width */ 335 u16 mps_rplc_size; 336 u16 vfcount; 337 u32 sge_fl_db; 338 u16 mps_tcam_size; 339 }; 340 341 struct adapter_params { 342 struct sge_params sge; 343 struct tp_params tp; 344 struct vpd_params vpd; 345 struct pci_params pci; 346 struct devlog_params devlog; 347 enum pcie_memwin drv_memwin; 348 349 unsigned int sf_size; /* serial flash size in bytes */ 350 unsigned int sf_nsec; /* # of flash sectors */ 351 352 unsigned int fw_vers; /* firmware version */ 353 unsigned int bs_vers; /* bootstrap version */ 354 unsigned int tp_vers; /* TP microcode version */ 355 unsigned int er_vers; /* expansion ROM version */ 356 unsigned int scfg_vers; /* Serial Configuration version */ 357 unsigned int vpd_vers; /* VPD version */ 358 359 unsigned short mtus[NMTUS]; 360 unsigned short a_wnd[NCCTRL_WIN]; 361 unsigned short b_wnd[NCCTRL_WIN]; 362 363 unsigned int mc_size; /* MC memory size */ 364 unsigned int nfilters; /* size of filter region */ 365 366 unsigned int cim_la_size; 367 368 unsigned char nports; /* # of ethernet ports */ 369 unsigned char portvec; 370 unsigned char offload; 371 372 unsigned char bypass; 373 unsigned char hash_filter; 374 375 enum chip_type chip; /* chip code */ 376 struct arch_specific_params arch; /* chip specific params */ 377 378 unsigned int ofldq_wr_cred; 379 380 unsigned int nsched_cls; /* number of traffic classes */ 381 382 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 383 unsigned int max_ird_adapter; /* Max read depth per adapter */ 384 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 385 unsigned char ulp_t10dif; /* t10dif support for ulp */ 386 unsigned char ulp_crypto; /* Crypto support */ 387 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 388 bool filter2_wr_support; /* FW support for FILTER2_WR */ 389 }; 390 391 /* 392 * State needed to monitor the forward progress of SGE Ingress DMA activities 393 * and possible hangs. 394 */ 395 struct sge_idma_monitor_state { 396 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 397 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 398 unsigned int idma_state[2]; /* IDMA Hang detect state */ 399 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 400 unsigned int idma_warn[2]; /* time to warning in HZ */ 401 }; 402 403 /* 404 * Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 405 * The access and execute times are signed in order to accommodate negative 406 * error returns. 407 */ 408 struct mbox_cmd { 409 u64 cmd[MBOX_LEN/8]; /* a Firmware Mailbox Command/Reply */ 410 u64 timestamp; /* OS-dependent timestamp */ 411 u32 seqno; /* sequence number */ 412 s16 access; /* time (ms) to access mailbox */ 413 s16 execute; /* time (ms) to execute */ 414 }; 415 416 struct mbox_cmd_log { 417 unsigned int size; /* number of entries in the log */ 418 unsigned int cursor; /* next position in the log to write */ 419 u32 seqno; /* next sequence number */ 420 /* variable length mailbox command log starts here */ 421 }; 422 423 /* 424 * Given a pointer to a Firmware Mailbox Command Log and a log entry index, 425 * return a pointer to the specified entry. 426 */ 427 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 428 unsigned int entry_idx) 429 { 430 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 431 } 432 433 #include <t4fw_interface.h> 434 435 #define FW_VERSION(chip) ( \ 436 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 437 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 438 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 439 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 440 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 441 442 struct fw_info { 443 u8 chip; 444 char *fs_name; 445 char *fw_mod_name; 446 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */ 447 }; 448 449 struct trace_params { 450 u32 data[TRACE_LEN / 4]; 451 u32 mask[TRACE_LEN / 4]; 452 unsigned short snap_len; 453 unsigned short min_len; 454 unsigned char skip_ofst; 455 unsigned char skip_len; 456 unsigned char invert; 457 unsigned char port; 458 }; 459 460 struct link_config { 461 unsigned short supported; /* link capabilities */ 462 unsigned short advertising; /* advertised capabilities */ 463 unsigned short lp_advertising; /* peer advertised capabilities */ 464 unsigned int requested_speed; /* speed user has requested */ 465 unsigned int speed; /* actual link speed */ 466 unsigned char requested_fc; /* flow control user has requested */ 467 unsigned char fc; /* actual link flow control */ 468 unsigned char auto_fec; /* Forward Error Correction: */ 469 unsigned char requested_fec; /* "automatic" (IEEE 802.3), */ 470 unsigned char fec; /* requested, and actual in use */ 471 unsigned char autoneg; /* autonegotiating? */ 472 unsigned char link_ok; /* link up? */ 473 unsigned char link_down_rc; /* link down reason */ 474 }; 475 476 /* 477 * Partial EEPROM Vital Product Data structure. Includes only the ID and 478 * VPD-R sections. 479 */ 480 struct t4_vpd_hdr { 481 u8 id_tag; 482 u8 id_len[2]; 483 u8 id_data[ID_LEN]; 484 u8 vpdr_tag; 485 u8 vpdr_len[2]; 486 }; 487 488 #include "adapter.h" 489 490 #ifndef PCI_VENDOR_ID_CHELSIO 491 # define PCI_VENDOR_ID_CHELSIO 0x1425 492 #endif 493 494 #define for_each_port(adapter, iter) \ 495 for (iter = 0; iter < (adapter)->params.nports; ++iter) 496 497 static inline int is_offload(const struct adapter *adap) 498 { 499 return adap->params.offload; 500 } 501 502 static inline int is_crypto(const struct adapter *adap) 503 { 504 return (adap->params.ulp_crypto & ULP_CRYPTO_LOOKASIDE); 505 } 506 507 static inline int is_hashfilter(const struct adapter *adap) 508 { 509 return adap->params.hash_filter; 510 } 511 512 static inline int is_bypass(const adapter_t *adap) 513 { 514 return adap->params.bypass; 515 } 516 517 static inline int is_bypass_device(int device) 518 { 519 /* XXX - this should be set based upon device capabilities */ 520 switch(device) { 521 #ifdef CONFIG_CHELSIO_BYPASS 522 case 0x440b: 523 case 0x440c: 524 return 1; 525 #endif 526 527 default: 528 return 0; 529 } 530 } 531 532 static inline int is_10gbt_device(int device) 533 { 534 /* XXX - this should be set based upon device capabilities */ 535 switch(device) { 536 case 0x4409: 537 case 0x4486: 538 return 1; 539 540 default: 541 return 0; 542 } 543 } 544 545 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 546 { 547 return adap->params.vpd.cclk / 1000; 548 } 549 550 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 551 unsigned int us) 552 { 553 return (us * adap->params.vpd.cclk) / 1000; 554 } 555 556 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 557 unsigned int ticks) 558 { 559 /* add Core Clock / 2 to round ticks to nearest uS */ 560 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 561 adapter->params.vpd.cclk); 562 } 563 564 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 565 unsigned int ticks) 566 { 567 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 568 } 569 570 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val); 571 572 void t4_record_mbox_marker(struct adapter *adapter, 573 const void *marker, unsigned int size); 574 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 575 int size, void *rpl, bool sleep_ok, int timeout); 576 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 577 void *rpl, bool sleep_ok); 578 579 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 580 const void *cmd, int size, void *rpl, 581 int timeout) 582 { 583 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 584 timeout); 585 } 586 587 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 588 int size, void *rpl) 589 { 590 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 591 } 592 593 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 594 int size, void *rpl) 595 { 596 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 597 } 598 599 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 600 unsigned int data_reg, u32 *vals, unsigned int nregs, 601 unsigned int start_idx); 602 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 603 unsigned int data_reg, const u32 *vals, 604 unsigned int nregs, unsigned int start_idx); 605 606 void t4_hw_pci_read_cfg4(adapter_t *adapter, int reg, u32 *val); 607 608 struct fw_filter_wr; 609 610 void t4_intr_enable(struct adapter *adapter); 611 void t4_intr_disable(struct adapter *adapter); 612 int t4_slow_intr_handler(struct adapter *adapter); 613 614 int t4_hash_mac_addr(const u8 *addr); 615 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 616 struct link_config *lc); 617 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 618 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 619 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 620 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 621 int t4_seeprom_wp(struct adapter *adapter, int enable); 622 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 623 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 624 int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, 625 u32 *data, int byte_oriented); 626 int t4_write_flash(struct adapter *adapter, unsigned int addr, 627 unsigned int n, const u8 *data, int byte_oriented); 628 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size, 629 unsigned int bootstrap); 630 int t4_load_phy_fw(struct adapter *adap, 631 int win, t4_os_lock_t *lock, 632 int (*phy_fw_version)(const u8 *, size_t), 633 const u8 *phy_fw_data, size_t phy_fw_size); 634 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 635 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 636 int t5_fw_init_extern_mem(struct adapter *adap); 637 #ifdef CHELSIO_T4_DIAGS 638 int t4_erase_sf(struct adapter *adapter); 639 #endif 640 int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 641 int t4_load_boot(struct adapter *adap, u8 *boot_data, 642 unsigned int boot_addr, unsigned int size); 643 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end); 644 int t4_flash_cfg_addr(struct adapter *adapter); 645 int t4_check_fw_version(struct adapter *adap); 646 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 647 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 648 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 649 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 650 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 651 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 652 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 653 int t4_get_version_info(struct adapter *adapter); 654 void t4_dump_version_info(struct adapter *adapter); 655 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 656 const u8 *fw_data, unsigned int fw_size, 657 struct fw_hdr *card_fw, const int t4_fw_install, 658 enum dev_state state, int *reset); 659 int t4_wait_dev_ready(struct adapter *adapter); 660 enum chip_type t4_get_chip_type(struct adapter *adap, int ver); 661 int t4_prep_adapter(struct adapter *adapter, bool reset); 662 int t4_prep_pf(struct adapter *adapter); 663 int t4_prep_master_pf(struct adapter *adapter); 664 int t4_shutdown_adapter(struct adapter *adapter); 665 666 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 667 int t4_bar2_sge_qregs(struct adapter *adapter, 668 unsigned int qid, 669 enum t4_bar2_qtype qtype, 670 int user, 671 u64 *pbar2_qoffset, 672 unsigned int *pbar2_qid); 673 674 int t4_init_devlog_params(struct adapter *adapter, int fw_attach); 675 int t4_init_sge_params(struct adapter *adapter); 676 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 677 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 678 int t4_create_filter_info(const struct adapter *adapter, 679 u64 *filter_value, u64 *filter_mask, 680 int fcoe, int port, int vnic_id, 681 int vlan, int vlan_pcp, int vlan_dei, 682 int tos, int protocol, int ethertype, 683 int macmatch, int mpshittype, int fragmentation); 684 int t4_init_rss_mode(struct adapter *adap, int mbox); 685 int t4_init_portinfo(struct port_info *pi, int mbox, 686 int port, int pf, int vf, u8 mac[]); 687 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 688 int t4_mirror_init(struct adapter *adap, int mbox, int pf, int vf); 689 void t4_fatal_err(struct adapter *adapter); 690 void t4_db_full(struct adapter *adapter); 691 void t4_db_dropped(struct adapter *adapter); 692 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 693 int filter_index, int enable); 694 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 695 int filter_index, int *enabled); 696 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 697 int start, int n, const u16 *rspq, unsigned int nrspq); 698 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 699 unsigned int flags); 700 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 701 unsigned int flags, unsigned int defq, unsigned int skeyidx, 702 unsigned int skey); 703 int t4_read_rss(struct adapter *adapter, u16 *entries); 704 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 705 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 706 bool sleep_ok); 707 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 708 u32 *valp, bool sleep_ok); 709 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 710 u32 val, bool sleep_ok); 711 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 712 u32 *vfl, u32 *vfh, bool sleep_ok); 713 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 714 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 715 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 716 unsigned int t4_get_tp_e2c_map(struct adapter *adapter, int pidx); 717 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 718 int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); 719 int t4_read_tcb(struct adapter *adap, int win, int tid, u32 tcb[TCB_SIZE/4]); 720 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 721 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 722 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 723 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 724 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 725 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 726 unsigned int *valp); 727 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 728 const unsigned int *valp); 729 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 730 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 731 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); 732 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 733 int t4_get_flash_params(struct adapter *adapter); 734 735 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach); 736 int t4_get_util_window(struct adapter *adap, int drv_fw_attach); 737 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 738 void t4_idma_monitor_init(struct adapter *adapter, 739 struct sge_idma_monitor_state *idma); 740 void t4_idma_monitor(struct adapter *adapter, 741 struct sge_idma_monitor_state *idma, 742 int hz, int ticks); 743 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 744 unsigned int naddr, u8 *addr); 745 746 #define T4_MEMORY_WRITE 0 747 #define T4_MEMORY_READ 1 748 int t4_memory_rw_addr(struct adapter *adap, int win, 749 u32 addr, u32 len, 750 void *hbuf, int dir); 751 int t4_memory_rw_mtype(struct adapter *adap, int win, 752 int mtype, u32 maddr, u32 len, 753 void *hbuf, int dir); 754 755 /* legacy compatibility routines */ 756 static inline int t4_memory_rw(struct adapter *adap, int win, 757 int mtype, u32 maddr, u32 len, 758 void *hbuf, int dir) 759 { 760 return t4_memory_rw_mtype(adap, win, mtype, maddr, len, hbuf, dir); 761 } 762 763 static inline int t4_memory_read(struct adapter *adap, int mtype, u32 addr, 764 u32 len, __be32 *buf) 765 { 766 return t4_memory_rw(adap, MEMWIN_NIC, mtype, addr, len, buf, T4_MEMORY_READ); 767 } 768 769 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 770 u32 len, __be32 *buf) 771 { 772 return t4_memory_rw(adap, MEMWIN_NIC, mtype, addr, len, buf, T4_MEMORY_WRITE); 773 } 774 775 /** 776 * hash_mac_addr - return the hash value of a MAC address 777 * @addr: the 48-bit Ethernet MAC address 778 * 779 * Hashes a MAC address according to the hash function used by hardware 780 * inexact (hash) address matching. The description in the hardware 781 * documentation for the MPS says this: 782 * 783 * The hash function takes the 48 bit MAC address and hashes 784 * it down to six bits. Bit zero of the hash is the XOR of 785 * bits 0, 6 ... 42 of the MAC address. The other hash bits 786 * are computed in a similar fashion ending with bit five of 787 * the hash as the XOR of bits 5, 11 ... 47 of the MAC address. 788 */ 789 static inline int hash_mac_addr(const u8 *addr) 790 { 791 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 792 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 793 794 a ^= b; 795 a ^= (a >> 12); 796 a ^= (a >> 6); 797 return a & 0x3f; 798 } 799 800 extern unsigned int t4_get_regs_len(struct adapter *adapter); 801 extern void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 802 803 const char *t4_get_port_type_description(enum fw_port_type port_type); 804 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 805 void t4_get_port_stats_offset(struct adapter *adap, int idx, 806 struct port_stats *stats, 807 struct port_stats *offset); 808 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 809 void t4_clr_port_stats(struct adapter *adap, int idx); 810 811 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 812 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 813 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 814 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 815 unsigned int *ipg, bool sleep_ok); 816 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 817 unsigned int mask, unsigned int val); 818 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 819 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 820 bool sleep_ok); 821 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 822 bool sleep_ok); 823 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 824 bool sleep_ok); 825 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 826 bool sleep_ok); 827 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 828 struct tp_tcp_stats *v6, bool sleep_ok); 829 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 830 struct tp_fcoe_stats *st, bool sleep_ok); 831 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 832 const unsigned short *alpha, const unsigned short *beta); 833 834 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 835 836 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 837 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map, 838 bool sleep_ok); 839 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, 840 int rqtype, int qid); 841 842 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 843 enum dev_master master, enum dev_state *state); 844 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 845 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 846 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 847 const u8 *fw_data, unsigned int size, int force); 848 int t4_fl_pkt_align(struct adapter *adap, bool is_packed); 849 int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size, 850 unsigned int cache_line_size, 851 enum chip_type chip_compat); 852 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 853 unsigned int cache_line_size); 854 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 855 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 856 unsigned int vf, unsigned int nparams, const u32 *params, 857 u32 *val); 858 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 859 unsigned int vf, unsigned int nparams, const u32 *params, 860 u32 *val); 861 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 862 unsigned int vf, unsigned int nparams, const u32 *params, 863 u32 *val, int rw, bool sleep_ok); 864 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 865 unsigned int pf, unsigned int vf, 866 unsigned int nparams, const u32 *params, 867 const u32 *val, int timeout); 868 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 869 unsigned int vf, unsigned int nparams, const u32 *params, 870 const u32 *val); 871 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 872 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 873 unsigned int rxqi, unsigned int rxq, unsigned int tc, 874 unsigned int vi, unsigned int cmask, unsigned int pmask, 875 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps); 876 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 877 unsigned int port, unsigned int pf, unsigned int vf, 878 unsigned int nmac, u8 *mac, unsigned int *rss_size, 879 unsigned int portfunc, unsigned int idstype); 880 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 881 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 882 unsigned int *rss_size); 883 int t4_free_vi(struct adapter *adap, unsigned int mbox, 884 unsigned int pf, unsigned int vf, 885 unsigned int viid); 886 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 887 int mtu, int promisc, int all_multi, int bcast, int vlanex, 888 bool sleep_ok); 889 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, 890 bool free, unsigned int naddr, const u8 **addr, u16 *idx, 891 u64 *hash, bool sleep_ok); 892 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 893 unsigned int viid, unsigned int naddr, 894 const u8 **addr, bool sleep_ok); 895 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 896 const u8 *addr, const u8 *mask, unsigned int idx, 897 u8 lookup_type, bool sleep_ok); 898 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 899 int idx, const u8 *addr, bool persist, bool add_smt); 900 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 901 bool ucast, u64 vec, bool sleep_ok); 902 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 903 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 904 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 905 bool rx_en, bool tx_en); 906 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 907 unsigned int nblinks); 908 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 909 unsigned int mmd, unsigned int reg, unsigned int *valp); 910 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 911 unsigned int mmd, unsigned int reg, unsigned int val); 912 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 913 int port, unsigned int devid, 914 unsigned int offset, unsigned int len, 915 u8 *buf); 916 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 917 int port, unsigned int devid, 918 unsigned int offset, unsigned int len, 919 u8 *buf); 920 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 921 unsigned int vf, unsigned int iqtype, unsigned int iqid, 922 unsigned int fl0id, unsigned int fl1id); 923 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 924 unsigned int vf, unsigned int iqtype, unsigned int iqid, 925 unsigned int fl0id, unsigned int fl1id); 926 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 927 unsigned int vf, unsigned int eqid); 928 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 929 unsigned int vf, unsigned int eqid); 930 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 931 unsigned int vf, unsigned int eqid); 932 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 933 enum ctxt_type ctype, u32 *data); 934 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 935 u32 *data); 936 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 937 const char *t4_link_down_rc_str(unsigned char link_down_rc); 938 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 939 int t4_update_port_info(struct port_info *pi); 940 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 941 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val); 942 943 int t4_sched_config(struct adapter *adapter, int type, int minmaxen); 944 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 945 int rateunit, int ratemode, int channel, int class, 946 int minrate, int maxrate, int weight, int pktsize); 947 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 948 unsigned int pf, unsigned int vf, 949 unsigned int timeout, unsigned int action); 950 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level); 951 int t4_set_devlog_level(struct adapter *adapter, unsigned int level); 952 953 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 954 955 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 956 u32 start_index, bool sleep_ok); 957 void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs, 958 u32 start_index, bool sleep_ok); 959 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 960 u32 start_index, bool sleep_ok); 961 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 962 u32 start_index, bool sleep_ok); 963 #ifdef __cplusplus 964 } 965 #endif 966 #endif /* __CHELSIO_COMMON_H */ 967