1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * This file is part of the Chelsio T1 Ethernet driver. 29 * 30 * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 31 */ 32 33 #ifndef _CHELSIO_OSCHTOE_H 34 #define _CHELSIO_OSCHTOE_H 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 typedef struct _pesge pesge; 41 42 /* looks like this should really be with mc5.h */ 43 #define DEFAULT_SERVER_REGION_LEN 256 44 #define DEFAULT_RT_REGION_LEN 1024 45 46 /* 47 * Bits used to configure driver behavior. 48 */ 49 #define CFGDMP_RSPQ 0x00000001 /* dump respq info */ 50 #define CFGDMP_CMDQ0 0x00000010 /* dump cmdq0 info */ 51 #define CFGDMP_CMDQ0MB 0x00000020 /* dump cmdq0 mbufs */ 52 #define CFGDMP_CMDQ1 0x00000040 /* dump cmdq1 info */ 53 #define CFGDMP_CMDQ1MB 0x00000080 /* dump cmdq1 mbufs */ 54 #define CFGDMP_FLQ0 0x00000100 /* dump flq0 info */ 55 #define CFGDMP_FLQ0MB 0x00000200 /* dump flq0 mbufs */ 56 #define CFGDMP_FLQ1 0x00000400 /* dump flq1 info */ 57 #define CFGDMP_FLQ1MB 0x00000800 /* dump flq1 mbufs */ 58 #define CFGDMP_ISRC 0x00001000 /* dump ISR 32 bit cause */ 59 #define CFGDMP_ISR 0x00002000 /* dump ISR info */ 60 #define CFGDMP_OUT 0x00004000 /* dump OUT info */ 61 #define CFGDMP_GMACC 0x00010000 /* dump GMAC cause bits */ 62 #define CFGDMP_PCIXC 0x00020000 /* dump PCIX cause bits */ 63 #define CFGDMP_TPC 0x00040000 /* dump TP cause bits */ 64 #define CFGDMP_MC5C 0x00080000 /* dump MC5 cause bits */ 65 66 #define CFGMD_RINGB 0x00100000 /* Store all packets in ring buffer */ 67 #define CFGMD_PROFILE 0x00200000 /* Enable driver profiling */ 68 69 #define CFGDMP_ERR 0x01000000 /* dump errors */ 70 #define CFGDMP_WRN 0x02000000 /* dump warnings */ 71 #define CFGDMP_STA 0x04000000 /* dump status info */ 72 #define CFGDMP_PTH 0x08000000 /* dump function paths */ 73 74 #define CFGMD_TUNNEL 0x10000000 /* Global tunnel mode ( 0-offload mode ) */ 75 #define CFGMD_144BIT 0x20000000 /* Puts MC5 in 144 bit mode */ 76 #define CFGMD_CPLBPF 0x40000000 /* Include CPL header when bpf_map called */ 77 78 /* 79 * Structure used to store drivers configuration information. 80 * Some of this information will be move out later or 81 * stored elsewhere. For now, it helps with development. 82 */ 83 typedef struct pe_config_data { 84 uint32_t gtm; /* run in Global Tunnel Mode */ 85 uint32_t global_config; /* override global debug value */ 86 87 uint32_t is_asic; 88 89 /* 90 * 5-auto-neg 91 * 2-1000Gbps(force); 92 * 1-100Gbps(force); 93 * 0-10Gbps(force) 94 */ 95 uint32_t link_speed; 96 97 uint32_t num_of_ports; /* Set the number of ports [1-4] */ 98 99 uint32_t tp_reset_cm; /* reset CM memory map */ 100 101 uint32_t phy_tx_fifo; /* phy's tx fifo depth */ 102 uint32_t phy_rx_fifo; /* phy's rx fifo depth */ 103 uint32_t phy_force_master; /* force link always in master mode */ 104 105 uint32_t mc5_rtbl_size; /* TCAM routing table size */ 106 uint32_t mc5_dbsvr_size; /* TCAM server size */ 107 uint32_t mc5_mode; /* 72 bit or 144 bit mode */ 108 uint32_t mc5_parity; /* Enable parity error checking */ 109 uint32_t mc5_issue_syn; /* Allow for transaction overlap */ 110 111 uint32_t packet_tracing; 112 113 uint32_t server_region_len; 114 uint32_t rt_region_len; 115 116 uint32_t offload_ip_cksum; /* on/off checksum offloading */ 117 uint32_t offload_udp_cksum; 118 uint32_t offload_tcp_cksum; 119 120 uint32_t sge_cmdq_sp; /* set sw schedule policy */ 121 uint32_t sge_cmdq_threshold; /* used w/ sw schedule policy */ 122 uint32_t sge_flq_threshold; /* set SGE's flq threshold register */ 123 124 uint32_t sge_cmdq0_cnt; /* set # entries of cmdq0 */ 125 uint32_t sge_cmdq1_cnt; /* set # entries of cmdq1 */ 126 uint32_t sge_flq0_cnt; /* set # entries of flq0 */ 127 uint32_t sge_flq1_cnt; /* set # entries of flq1 */ 128 uint32_t sge_respq_cnt; /* set # entries of respq */ 129 130 131 /* 132 * Update MAC stats automatically. 133 * Sometimes we don't want this to 134 * happen when debugging 135 */ 136 uint32_t stats; 137 138 /* 139 * Add microsecond delay to packets 140 * sent in Tx direction. This is useful 141 * in testing hardware. 142 */ 143 uint32_t tx_delay_us; 144 145 /* 146 * Can change chip revision support 147 * settting -1 default. Uses hardware 148 * lookup table. 149 * 0 force T1A 150 * 1 force T1B 151 */ 152 uint32_t chip; 153 154 /* 155 * Used to only initialize PCI so 156 * read/write registers work. The 157 * driver does not initialize anything 158 * of the HW blocks. 159 */ 160 uint32_t exit_early; 161 162 /* local ring buffer */ 163 uint32_t rb_num_of_entries; /* number of entries */ 164 uint32_t rb_size_of_entries; /* bytes size of an entry */ 165 uint32_t rb_flag; /* varies flags */ 166 167 /* Opt values used to store CATP options. */ 168 uint32_t type; 169 uint64_t cat_opt0; 170 uint64_t cat_opt1; 171 172 } pe_config_data_t; 173 174 struct pe_port_t { 175 uint8_t enaddr[6]; 176 struct cmac *mac; 177 struct cphy *phy; 178 struct link_config link_config; 179 u32 line_up; 180 }; 181 182 #define DBGASSERT(c) ASSERT(c) 183 184 #define t1_is_T1A(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1A) 185 #define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B) 186 #define t1_is_T1C(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1C) 187 188 #ifdef __cplusplus 189 } 190 #endif 191 192 #endif /* _CHELSIO_OSCHTOE_H */ 193