1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" /* elmer0.h */ 27 28 #ifndef CHELSIO_ELMER0_H 29 #define CHELSIO_ELMER0_H 30 31 /* ELMER0 flavors */ 32 enum { 33 ELMER0_XC2S300E_6FT256_C, 34 ELMER0_XC2S100E_6TQ144_C 35 }; 36 37 /* ELMER0 registers */ 38 #define A_ELMER0_VERSION 0x100000 39 #define A_ELMER0_PHY_CFG 0x100004 40 #define A_ELMER0_INT_ENABLE 0x100008 41 #define A_ELMER0_INT_CAUSE 0x10000c 42 #define A_ELMER0_GPI_CFG 0x100010 43 #define A_ELMER0_GPI_STAT 0x100014 44 #define A_ELMER0_GPO 0x100018 45 #define A_ELMER0_PORT0_MI1_CFG 0x400000 46 47 #define S_MI1_MDI_ENABLE 0 48 #define V_MI1_MDI_ENABLE(x) ((x) << S_MI1_MDI_ENABLE) 49 #define F_MI1_MDI_ENABLE V_MI1_MDI_ENABLE(1U) 50 51 #define S_MI1_MDI_INVERT 1 52 #define V_MI1_MDI_INVERT(x) ((x) << S_MI1_MDI_INVERT) 53 #define F_MI1_MDI_INVERT V_MI1_MDI_INVERT(1U) 54 55 #define S_MI1_PREAMBLE_ENABLE 2 56 #define V_MI1_PREAMBLE_ENABLE(x) ((x) << S_MI1_PREAMBLE_ENABLE) 57 #define F_MI1_PREAMBLE_ENABLE V_MI1_PREAMBLE_ENABLE(1U) 58 59 #define S_MI1_SOF 3 60 #define M_MI1_SOF 0x3 61 #define V_MI1_SOF(x) ((x) << S_MI1_SOF) 62 #define G_MI1_SOF(x) (((x) >> S_MI1_SOF) & M_MI1_SOF) 63 64 #define S_MI1_CLK_DIV 5 65 #define M_MI1_CLK_DIV 0xff 66 #define V_MI1_CLK_DIV(x) ((x) << S_MI1_CLK_DIV) 67 #define G_MI1_CLK_DIV(x) (((x) >> S_MI1_CLK_DIV) & M_MI1_CLK_DIV) 68 69 #define A_ELMER0_PORT0_MI1_ADDR 0x400004 70 71 #define S_MI1_REG_ADDR 0 72 #define M_MI1_REG_ADDR 0x1f 73 #define V_MI1_REG_ADDR(x) ((x) << S_MI1_REG_ADDR) 74 #define G_MI1_REG_ADDR(x) (((x) >> S_MI1_REG_ADDR) & M_MI1_REG_ADDR) 75 76 #define S_MI1_PHY_ADDR 5 77 #define M_MI1_PHY_ADDR 0x1f 78 #define V_MI1_PHY_ADDR(x) ((x) << S_MI1_PHY_ADDR) 79 #define G_MI1_PHY_ADDR(x) (((x) >> S_MI1_PHY_ADDR) & M_MI1_PHY_ADDR) 80 81 #define A_ELMER0_PORT0_MI1_DATA 0x400008 82 83 #define S_MI1_DATA 0 84 #define M_MI1_DATA 0xffff 85 #define V_MI1_DATA(x) ((x) << S_MI1_DATA) 86 #define G_MI1_DATA(x) (((x) >> S_MI1_DATA) & M_MI1_DATA) 87 88 #define A_ELMER0_PORT0_MI1_OP 0x40000c 89 90 #define S_MI1_OP 0 91 #define M_MI1_OP 0x3 92 #define V_MI1_OP(x) ((x) << S_MI1_OP) 93 #define G_MI1_OP(x) (((x) >> S_MI1_OP) & M_MI1_OP) 94 95 #define S_MI1_ADDR_AUTOINC 2 96 #define V_MI1_ADDR_AUTOINC(x) ((x) << S_MI1_ADDR_AUTOINC) 97 #define F_MI1_ADDR_AUTOINC V_MI1_ADDR_AUTOINC(1U) 98 99 #define S_MI1_OP_BUSY 31 100 #define V_MI1_OP_BUSY(x) ((x) << S_MI1_OP_BUSY) 101 #define F_MI1_OP_BUSY V_MI1_OP_BUSY(1U) 102 103 #define A_ELMER0_PORT1_MI1_CFG 0x500000 104 #define A_ELMER0_PORT1_MI1_ADDR 0x500004 105 #define A_ELMER0_PORT1_MI1_DATA 0x500008 106 #define A_ELMER0_PORT1_MI1_OP 0x50000c 107 #define A_ELMER0_PORT2_MI1_CFG 0x600000 108 #define A_ELMER0_PORT2_MI1_ADDR 0x600004 109 #define A_ELMER0_PORT2_MI1_DATA 0x600008 110 #define A_ELMER0_PORT2_MI1_OP 0x60000c 111 #define A_ELMER0_PORT3_MI1_CFG 0x700000 112 #define A_ELMER0_PORT3_MI1_ADDR 0x700004 113 #define A_ELMER0_PORT3_MI1_DATA 0x700008 114 #define A_ELMER0_PORT3_MI1_OP 0x70000c 115 116 /* Simple bit definition for GPI and GP0 registers. */ 117 #define ELMER0_GP_BIT0 0x0001 118 #define ELMER0_GP_BIT1 0x0002 119 #define ELMER0_GP_BIT2 0x0004 120 #define ELMER0_GP_BIT3 0x0008 121 #define ELMER0_GP_BIT4 0x0010 122 #define ELMER0_GP_BIT5 0x0020 123 #define ELMER0_GP_BIT6 0x0040 124 #define ELMER0_GP_BIT7 0x0080 125 #define ELMER0_GP_BIT8 0x0100 126 #define ELMER0_GP_BIT9 0x0200 127 #define ELMER0_GP_BIT10 0x0400 128 #define ELMER0_GP_BIT11 0x0800 129 #define ELMER0_GP_BIT12 0x1000 130 #define ELMER0_GP_BIT13 0x2000 131 #define ELMER0_GP_BIT14 0x4000 132 #define ELMER0_GP_BIT15 0x8000 133 #define ELMER0_GP_BIT16 0x10000 134 #define ELMER0_GP_BIT17 0x20000 135 #define ELMER0_GP_BIT18 0x40000 136 #define ELMER0_GP_BIT19 0x80000 137 138 #define MI1_OP_DIRECT_WRITE 1 139 #define MI1_OP_DIRECT_READ 2 140 141 #define MI1_OP_INDIRECT_ADDRESS 0 142 #define MI1_OP_INDIRECT_WRITE 1 143 #define MI1_OP_INDIRECT_READ_INC 2 144 #define MI1_OP_INDIRECT_READ 3 145 146 #endif 147