1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 24 */ 25 26 #ifndef CHELSIO_COMMON_H 27 #define CHELSIO_COMMON_H 28 29 #define DIMOF(x) (sizeof(x)/sizeof(x[0])) 30 31 #define NMTUS 8 32 #define MAX_NPORTS 4 33 #define TCB_SIZE 128 34 35 enum { 36 CHBT_BOARD_7500, 37 CHBT_BOARD_8000, 38 CHBT_BOARD_CHT101, 39 CHBT_BOARD_CHT110, 40 CHBT_BOARD_CHT210, 41 CHBT_BOARD_CHT204, 42 CHBT_BOARD_CHT204V, 43 CHBT_BOARD_N110, 44 CHBT_BOARD_N210, 45 CHBT_BOARD_COUGAR, 46 CHBT_BOARD_6800, 47 CHBT_BOARD_SIMUL 48 }; 49 50 enum { 51 CHBT_TERM_FPGA, 52 CHBT_TERM_T1, 53 CHBT_TERM_T2, 54 CHBT_TERM_T3 55 }; 56 57 enum { 58 CHBT_MAC_CHELSIO_A, 59 CHBT_MAC_IXF1010, 60 CHBT_MAC_PM3393, 61 CHBT_MAC_VSC7321, 62 CHBT_MAC_DUMMY 63 }; 64 65 enum { 66 CHBT_PHY_88E1041, 67 CHBT_PHY_88E1111, 68 CHBT_PHY_88X2010, 69 CHBT_PHY_XPAK, 70 CHBT_PHY_MY3126, 71 CHBT_PHY_DUMMY 72 }; 73 74 enum { 75 PAUSE_RX = 1, 76 PAUSE_TX = 2, 77 PAUSE_AUTONEG = 4 78 }; 79 80 /* Revisions of T1 chip */ 81 #define TERM_T1A 0 82 #define TERM_T1B 1 83 #define TERM_T2 3 84 85 struct tp_params { 86 unsigned int pm_size; 87 unsigned int cm_size; 88 unsigned int pm_rx_base; 89 unsigned int pm_tx_base; 90 unsigned int pm_rx_pg_size; 91 unsigned int pm_tx_pg_size; 92 unsigned int pm_rx_num_pgs; 93 unsigned int pm_tx_num_pgs; 94 unsigned int use_5tuple_mode; 95 }; 96 97 struct sge_params { 98 unsigned int cmdQ_size[2]; 99 unsigned int freelQ_size[2]; 100 unsigned int large_buf_capacity; 101 unsigned int rx_coalesce_usecs; 102 unsigned int last_rx_coalesce_raw; 103 unsigned int default_rx_coalesce_usecs; 104 unsigned int sample_interval_usecs; 105 unsigned int coalesce_enable; 106 unsigned int polling; 107 }; 108 109 struct mc5_params { 110 unsigned int mode; /* selects MC5 width */ 111 unsigned int nservers; /* size of server region */ 112 unsigned int nroutes; /* size of routing region */ 113 }; 114 115 /* Default MC5 region sizes */ 116 #define DEFAULT_SERVER_REGION_LEN 256 117 #define DEFAULT_RT_REGION_LEN 1024 118 119 struct pci_params { 120 unsigned short speed; 121 unsigned char width; 122 unsigned char is_pcix; 123 }; 124 125 struct adapter_params { 126 struct sge_params sge; 127 struct mc5_params mc5; 128 struct tp_params tp; 129 struct pci_params pci; 130 131 const struct board_info *brd_info; 132 133 unsigned short mtus[NMTUS]; 134 unsigned int nports; /* # of ethernet ports */ 135 unsigned int stats_update_period; 136 unsigned short chip_revision; 137 unsigned char chip_version; 138 unsigned char is_asic; 139 }; 140 141 struct pci_err_cnt { 142 unsigned int master_parity_err; 143 unsigned int sig_target_abort; 144 unsigned int rcv_target_abort; 145 unsigned int rcv_master_abort; 146 unsigned int sig_sys_err; 147 unsigned int det_parity_err; 148 unsigned int pio_parity_err; 149 unsigned int wf_parity_err; 150 unsigned int rf_parity_err; 151 unsigned int cf_parity_err; 152 }; 153 154 struct link_config { 155 unsigned int supported; /* link capabilities */ 156 unsigned int advertising; /* advertised capabilities */ 157 unsigned short requested_speed; /* speed user has requested */ 158 unsigned short speed; /* actual link speed */ 159 unsigned char requested_duplex; /* duplex user has requested */ 160 unsigned char duplex; /* actual link duplex */ 161 unsigned char requested_fc; /* flow control user has requested */ 162 unsigned char fc; /* actual link flow control */ 163 unsigned char autoneg; /* autonegotiating? */ 164 }; 165 166 #define SPEED_INVALID 0xffff 167 #define DUPLEX_INVALID 0xff 168 169 struct mdio_ops; 170 struct gmac; 171 struct gphy; 172 173 struct board_info { 174 unsigned char board; 175 unsigned char port_number; 176 unsigned long caps; 177 unsigned char chip_term; 178 unsigned char chip_mac; 179 unsigned char chip_phy; 180 unsigned int clock_core; 181 unsigned int clock_mc3; 182 unsigned int clock_mc4; 183 unsigned int espi_nports; 184 unsigned int clock_cspi; 185 unsigned int clock_elmer0; 186 unsigned char mdio_mdien; 187 unsigned char mdio_mdiinv; 188 unsigned char mdio_mdc; 189 unsigned char mdio_phybaseaddr; 190 struct gmac *gmac; 191 struct gphy *gphy; 192 struct mdio_ops *mdio_ops; 193 const char *desc; 194 }; 195 196 #include "osdep.h" 197 198 #ifndef PCI_VENDOR_ID_CHELSIO 199 #define PCI_VENDOR_ID_CHELSIO 0x1425 200 #endif 201 202 extern struct pci_device_id t1_pci_tbl[]; 203 204 static inline int t1_is_asic(const adapter_t *adapter) 205 { 206 return adapter->params.is_asic; 207 } 208 209 static inline int adapter_matches_type(const adapter_t *adapter, 210 int version, int revision) 211 { 212 return adapter->params.chip_version == version && 213 adapter->params.chip_revision == revision; 214 } 215 216 #define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B) 217 #define is_T2(adap) adapter_matches_type(adap, CHBT_TERM_T2, TERM_T2) 218 219 /* Returns true if an adapter supports VLAN acceleration and TSO */ 220 static inline int vlan_tso_capable(const adapter_t *adapter) 221 { 222 return !t1_is_T1B(adapter); 223 } 224 225 #define for_each_port(adapter, iter) \ 226 for (iter = 0; iter < (adapter)->params.nports; ++iter) 227 228 #define board_info(adapter) ((adapter)->params.brd_info) 229 #define is_10G(adapter) (board_info(adapter)->caps & SUPPORTED_10000baseT_Full) 230 231 static inline unsigned int core_ticks_per_usec(const adapter_t *adap) 232 { 233 return board_info(adap)->clock_core / 1000000; 234 } 235 236 int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp); 237 int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value); 238 int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value); 239 int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value); 240 int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity, 241 int attempts, int delay); 242 243 void t1_interrupts_enable(adapter_t *adapter); 244 void t1_interrupts_disable(adapter_t *adapter); 245 void t1_interrupts_clear(adapter_t *adapter); 246 int elmer0_ext_intr_handler(adapter_t *adapter); 247 int t1_slow_intr_handler(adapter_t *adapter); 248 249 int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); 250 const struct board_info *t1_get_board_info(unsigned int board_id); 251 const struct board_info *t1_get_board_info_from_ids(unsigned int devid, 252 unsigned short ssid); 253 int t1_seeprom_read(adapter_t *adapter, u32 addr, u32 *data); 254 int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi, 255 struct adapter_params *p); 256 int t1_init_hw_modules(adapter_t *adapter); 257 int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi); 258 void t1_free_sw_modules(adapter_t *adapter); 259 void t1_fatal_err(adapter_t *adapter); 260 void link_changed(adapter_t *adapter, int port_id); 261 void init_mtus(unsigned short mtus[]); 262 #endif /* CHELSIO_COMMON_H */ 263