xref: /illumos-gate/usr/src/uts/common/io/cardbus/cardbus_cfg.c (revision 8c4267180173328ebba9487634f0f232387d067f)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 /*
26  * Copyright (c)  * Copyright (c) 2001 Tadpole Technology plc
27  * All rights reserved.
28  * From "@(#)pcicfg.c   1.31    99/06/18 SMI"
29  */
30 
31 /*
32  * Copyright 2023 Oxide Computer Company
33  */
34 
35 /*
36  * Cardbus configurator
37  */
38 
39 #include <sys/ddi.h>
40 #include <sys/sunndi.h>
41 #include <sys/ndi_impldefs.h>
42 
43 #include <sys/pci.h>
44 #include <sys/ebus.h>
45 #include <sys/hotplug/hpctrl.h>
46 #include <sys/hotplug/pci/pcicfg.h>
47 
48 #include <sys/pctypes.h>
49 #include <sys/pcmcia.h>
50 #include <sys/sservice.h>
51 
52 #include <sys/isa_defs.h>
53 
54 #include <sys/note.h>
55 
56 #include <sys/ethernet.h>
57 
58 #include "cardbus.h"
59 #include "cardbus_parse.h"
60 #include "cardbus_cfg.h"
61 
62 /*
63  * ************************************************************************
64  * *** Implementation specific local data structures/definitions.       ***
65  * ************************************************************************
66  */
67 
68 #define	PCICFG_MAX_DEVICE 32
69 #define	PCICFG_MAX_FUNCTION 8
70 
71 static uint32_t pcicfg_max_device = PCICFG_MAX_DEVICE;
72 static uint32_t pcicfg_max_function = PCICFG_MAX_FUNCTION;
73 
74 #define	PCICFG_NODEVICE 42
75 #define	PCICFG_NOMEMORY 43
76 #define	PCICFG_NOMULTI  44
77 
78 #define	PCICFG_HIADDR(n) ((uint32_t)(((uint64_t)(n) & 0xFFFFFFFF00000000)>> 32))
79 #define	PCICFG_LOADDR(n) ((uint32_t)((uint64_t)(n) & 0x00000000FFFFFFFF))
80 #define	PCICFG_LADDR(lo, hi)    (((uint64_t)(hi) << 32) | (uint32_t)(lo))
81 
82 #define	PCICFG_HIWORD(n) ((uint16_t)(((uint32_t)(n) & 0xFFFF0000)>> 16))
83 #define	PCICFG_LOWORD(n) ((uint16_t)((uint32_t)(n) & 0x0000FFFF))
84 #define	PCICFG_HIBYTE(n) ((uint8_t)(((uint16_t)(n) & 0xFF00)>> 8))
85 #define	PCICFG_LOBYTE(n) ((uint8_t)((uint16_t)(n) & 0x00FF))
86 
87 #define	PCICFG_ROUND_UP(addr, gran) ((uintptr_t)((gran+addr-1)&(~(gran-1))))
88 #define	PCICFG_ROUND_DOWN(addr, gran) ((uintptr_t)((addr) & ~(gran-1)))
89 
90 #define	PCICFG_MEMGRAN 0x100000
91 #define	PCICFG_IOGRAN 0x1000
92 #define	PCICFG_4GIG_LIMIT 0xFFFFFFFFUL
93 #define	CBCFG_MEMGRAN 0x1000
94 #define	CBCFG_IOGRAN 0x4
95 
96 #define	PCICFG_MEM_MULT 4
97 #define	PCICFG_IO_MULT 4
98 #define	PCICFG_RANGE_LEN 2 /* Number of range entries */
99 
100 /*
101  * ISA node declaration structure.
102  */
103 struct isa_node {
104 	char	*name;
105 	char	*compatible[5];
106 	char	*type;
107 	char	*model;
108 	uint16_t	reg;
109 	uint16_t	span;
110 };
111 
112 struct cardbus_name_entry {
113 	uint32_t class_code;
114 	char  *name;
115 	int pil;
116 };
117 
118 struct cardbus_find_ctrl {
119 	uint_t		bus;
120 	uint_t		device;
121 	uint_t		function;
122 	dev_info_t	*dip;
123 };
124 
125 #define	PCICFG_MAKE_REG_HIGH(busnum, devnum, funcnum, register)\
126 	(\
127 	((ulong_t)(busnum & 0xff) << 16)    |\
128 	((ulong_t)(devnum & 0x1f) << 11)    |\
129 	((ulong_t)(funcnum & 0x7) <<  8)    |\
130 	((ulong_t)(register & 0x3f)))
131 
132 typedef struct cardbus_phdl cardbus_phdl_t;
133 
134 struct cardbus_phdl {
135 
136 	dev_info_t	*dip;	/* Associated with the attach point */
137 	dev_info_t	*res_dip; /* dip from which io/mem is allocated */
138 	cardbus_phdl_t  *next;
139 
140 	uint64_t	memory_base;    /* Memory base for this attach point */
141 	uint64_t	memory_last;
142 	uint64_t	memory_len;
143 	uint32_t	memory_gran;
144 	uint32_t	io_base;	/* I/O base for this attach point */
145 	uint32_t	io_last;
146 	uint32_t	io_len;
147 	uint32_t	io_gran;
148 
149 	int	error;
150 	uint_t	highest_bus;    /* Highest bus seen on the probe */
151 	ndi_ra_request_t mem_req;	/* allocator request for memory */
152 	ndi_ra_request_t io_req;	/* allocator request for I/O */
153 };
154 
155 typedef struct {
156 	dev_info_t  *dip;	/* Associated with the attach point */
157 	ddi_acc_handle_t handle;    /* open handle on parent PCI config space */
158 	uint32_t    io_base;	/* I/O base for this attach point */
159 	int	io_decode_reg;
160 } isa_phdl_t;
161 
162 
163 /*
164  * forward declarations for routines defined in this module (called here)
165  */
166 static cardbus_phdl_t *cardbus_find_phdl(dev_info_t *dip);
167 static cardbus_phdl_t *cardbus_create_phdl(dev_info_t *dip);
168 static int cardbus_destroy_phdl(dev_info_t *dip);
169 static int cardbus_program_ap(dev_info_t *);
170 static void cardbus_topbridge_assign(dev_info_t *, cardbus_phdl_t *);
171 static int cardbus_bridge_ranges(dev_info_t *, cardbus_phdl_t *,
172 			ddi_acc_handle_t);
173 static int cardbus_bridge_assign(dev_info_t *, void *);
174 static int cardbus_isa_bridge_ranges(dev_info_t *dip, cardbus_phdl_t *entry,
175 			ddi_acc_handle_t handle);
176 static int cardbus_add_isa_reg(dev_info_t *, void *);
177 static int cardbus_allocate_chunk(dev_info_t *, uint8_t, uint8_t);
178 static int cardbus_free_chunk(dev_info_t *);
179 static void cardbus_setup_bridge(dev_info_t *, cardbus_phdl_t *,
180 			ddi_acc_handle_t);
181 static void cardbus_update_bridge(dev_info_t *, cardbus_phdl_t *,
182 			ddi_acc_handle_t);
183 static void cardbus_get_mem(dev_info_t *, cardbus_phdl_t *, uint32_t,
184 			uint64_t *);
185 static void cardbus_get_io(dev_info_t *, cardbus_phdl_t *, uint32_t,
186 			uint32_t *);
187 static int cardbus_sum_resources(dev_info_t *, void *);
188 static int cardbus_free_bridge_resources(dev_info_t *);
189 static int cardbus_free_device_resources(dev_info_t *);
190 static int cardbus_free_resources(dev_info_t *);
191 static int cardbus_probe_bridge(cbus_t *, dev_info_t *, uint_t,
192 			uint_t, uint_t);
193 static int cardbus_probe_children(cbus_t *, dev_info_t *, uint_t, uint_t,
194 			uint_t, uint8_t *);
195 static int cardbus_add_config_reg(dev_info_t *, uint_t, uint_t, uint_t);
196 static int cardbus_add_isa_node(cbus_t *, dev_info_t *, struct isa_node *);
197 static int cardbus_config_setup(dev_info_t *, ddi_acc_handle_t *);
198 static void cardbus_config_teardown(ddi_acc_handle_t *);
199 static void cardbus_reparent_children(dev_info_t *, dev_info_t *);
200 static int cardbus_update_assigned_prop(dev_info_t *, pci_regspec_t *);
201 static int cardbus_update_available_prop(dev_info_t *, uint32_t,
202 			uint64_t, uint64_t);
203 static int cardbus_update_ranges_prop(dev_info_t *, cardbus_range_t *);
204 static int cardbus_update_reg_prop(dev_info_t *dip, uint32_t regvalue,
205 			uint_t reg_offset);
206 static int cardbus_set_standard_props(dev_info_t *parent, dev_info_t *dip,
207 			ddi_acc_handle_t config_handle);
208 static int cardbus_set_isa_props(dev_info_t *parent, dev_info_t *dip,
209 			char *name, char *compat[]);
210 static int cardbus_set_busnode_props(dev_info_t *);
211 static int cardbus_set_busnode_isaprops(dev_info_t *);
212 static int cardbus_set_childnode_props(dev_info_t *dip,
213 			ddi_acc_handle_t config_handle);
214 static void cardbus_set_bus_numbers(ddi_acc_handle_t config_handle,
215 			uint_t primary, uint_t secondary);
216 static void enable_pci_isa_bridge(dev_info_t *dip,
217 			ddi_acc_handle_t config_handle);
218 static void enable_pci_pci_bridge(dev_info_t *dip,
219 			ddi_acc_handle_t config_handle);
220 static void enable_cardbus_bridge(dev_info_t *dip,
221 			ddi_acc_handle_t config_handle);
222 static void disable_pci_pci_bridge(dev_info_t *dip,
223 			ddi_acc_handle_t config_handle);
224 static void disable_cardbus_bridge(dev_info_t *dip,
225 			ddi_acc_handle_t config_handle);
226 static void enable_cardbus_device(dev_info_t *, ddi_acc_handle_t);
227 static void disable_cardbus_device(ddi_acc_handle_t config_handle);
228 static void cardbus_force_boolprop(dev_info_t *dip, char *pname);
229 static void cardbus_force_intprop(dev_info_t *dip, char *pname,
230 			int *pval, int len);
231 static void cardbus_force_stringprop(dev_info_t *dip, char *pname,
232 			char *pval);
233 static void split_addr(char *, int *, int *);
234 #ifdef DEBUG
235 static void cardbus_dump_common_config(ddi_acc_handle_t config_handle);
236 static void cardbus_dump_device_config(ddi_acc_handle_t config_handle);
237 static void cardbus_dump_bridge_config(ddi_acc_handle_t config_handle,
238 			uint8_t header_type);
239 static void cardbus_dump_config(ddi_acc_handle_t config_handle);
240 static void cardbus_dump_reg(dev_info_t *dip, const pci_regspec_t *regspec,
241 			int nelems);
242 #endif
243 
244 static cardbus_phdl_t *cardbus_phdl_list = NULL;
245 
246 static struct cardbus_name_entry cardbus_class_lookup [] = {
247 	{ 0x001, "display", 9 },
248 	{ 0x100, "scsi", 4 },
249 	{ 0x101, "ide", 4 },
250 	{ 0x102, "fdc", 4 },
251 	{ 0x103, "ipi", 4 },
252 	{ 0x104, "raid", 4 },
253 	{ 0x200, "ethernet", 6 },
254 	{ 0x201, "token-ring", 6 },
255 	{ 0x202, "fddi", 6 },
256 	{ 0x203, "atm", 6 },
257 	{ 0x300, "display", 9 },    /* VGA card */
258 	{ 0x380, "display", 9 },    /* other - for the Raptor Card */
259 	{ 0x400, "video", 11 },
260 	{ 0x401, "sound", 11 },
261 	{ 0x500, "memory", 11 },
262 	{ 0x501, "flash", 11 },
263 	{ 0x600, "host", 11 },
264 	{ 0x601, "isa", 11 },
265 	{ 0x602, "eisa", 11 },
266 	{ 0x603, "mca", 11 },
267 	{ 0x604, "pci", 11 },
268 	{ 0x605, "pcmcia", 11 },
269 	{ 0x606, "nubus", 11 },
270 	{ 0x607, "cardbus", 11 },
271 	{ 0x680, NULL, 8 },
272 	{ 0x700, "serial", 11 },
273 	{ 0x701, "parallel", 6 },
274 	{ 0x800, "interrupt-controller", 3 },
275 	{ 0x801, "dma-controller", 3 },
276 	{ 0x802, "timer", 3 },
277 	{ 0x803, "rtc", 3 },
278 	{ 0x900, "keyboard", 8 },
279 	{ 0x901, "pen", 8 },
280 	{ 0x902, "mouse", 8 },
281 	{ 0xa00, "dock", 1 },
282 	{ 0xb00, "cpu", 1 },
283 	{ 0xc00, "firewire", 9 },
284 	{ 0xc01, "access-bus", 4 },
285 	{ 0xc02, "ssa", 4 },
286 	{ 0xc03, "usb", 9 },
287 	{ 0xc04, "fibre-channel", 6 },
288 	{ 0, 0 }
289 };
290 
291 #ifndef _DONT_USE_1275_GENERIC_NAMES
292 static char *cardbus_get_class_name(uint32_t classcode);
293 #endif /* _DONT_USE_1275_GENERIC_NAMES */
294 
295 /*
296  * Reprogram ILINE with default value only if BIOS doesn't program it
297  */
298 int
299 cardbus_validate_iline(dev_info_t *dip, ddi_acc_handle_t handle)
300 {
301 	uint8_t intline = 0xff;
302 
303 	if (pci_config_get8(handle, PCI_CONF_IPIN)) {
304 	intline = pci_config_get8(handle, PCI_CONF_ILINE);
305 	if ((intline == 0) || (intline == 0xff)) {
306 		intline = ddi_getprop(DDI_DEV_T_ANY, dip,
307 			DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS,
308 			"interrupt-line", 0xff);
309 		if (intline == (uint8_t)0xff) {
310 			intline = ddi_getprop(DDI_DEV_T_ANY,
311 				ddi_get_parent(dip),
312 				DDI_PROP_CANSLEEP /* |DDI_PROP_DONTPASS */,
313 				"interrupt-line", 0xb);
314 		}
315 
316 		pci_config_put8(handle, PCI_CONF_ILINE, intline);
317 	}
318 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
319 		"interrupt-line", intline);
320 	}
321 	return (intline);
322 }
323 
324 /*
325  * This entry point is called to configure a device (and
326  * all its children) on the given bus. It is called when
327  * a new device is added to the PCI domain.  This routine
328  * will create the device tree and program the devices
329  * registers.
330  */
331 int
332 cardbus_configure(cbus_t *cbp)
333 {
334 	uint_t bus;
335 	int cardbus_dev, func;
336 	dev_info_t *attach_point;
337 
338 	cardbus_err(cbp->cb_dip, 6, "cardbus_configure ()\n");
339 
340 	bus = cardbus_primary_busno(cbp->cb_dip);
341 
342 	if (ndi_devi_alloc(cbp->cb_dip, DEVI_PSEUDO_NEXNAME,
343 	    (pnode_t)DEVI_SID_NODEID,
344 	    &attach_point) != NDI_SUCCESS) {
345 		cardbus_err(cbp->cb_dip, 1,
346 		    "cardbus_configure(): Failed to alloc probe node\n");
347 		return (PCICFG_FAILURE);
348 	}
349 
350 	/*
351 	 * Node name marks this node as the "attachment point".
352 	 */
353 	if (ndi_devi_set_nodename(attach_point,
354 	    "hp_attachment", 0) != NDI_SUCCESS) {
355 	    cardbus_err(cbp->cb_dip, 1,
356 		    "Failed to set nodename for attachment node\n");
357 		(void) ndi_devi_free(attach_point);
358 		return (PCICFG_FAILURE);
359 	}
360 
361 	cardbus_err(ddi_get_parent(attach_point), 8,
362 	    "Set bus type to cardbus\n");
363 	(void) ddi_prop_update_string(DDI_DEV_T_NONE,
364 	    ddi_get_parent(attach_point), PCM_DEVICETYPE,
365 	    "cardbus");
366 
367 	split_addr(ddi_get_name_addr(cbp->cb_dip), &cardbus_dev, &func);
368 
369 	cardbus_err(attach_point, 8,
370 	    "Configuring [0x%x][0x%x][0x%x]\n", bus, cardbus_dev, func);
371 
372 	switch (cardbus_probe_bridge(cbp, attach_point,
373 	    bus, cardbus_dev, func)) {
374 	case PCICFG_FAILURE:
375 		cardbus_err(cbp->cb_dip, 4,
376 		    "configure failed: bus [0x%x] slot [0x%x] func [0x%x]\n",
377 		    bus, cardbus_dev, func);
378 		goto cleanup;
379 	case PCICFG_NODEVICE:
380 		cardbus_err(cbp->cb_dip, 4,
381 		    "no device: bus [0x%x] slot [0x%x] func [0x%x]\n",
382 		    bus, cardbus_dev, func);
383 		goto cleanup;
384 	default:
385 		cardbus_err(cbp->cb_dip, 9,
386 		    "configure: bus => [%d] slot => [%d] func => [%d]\n",
387 		    bus, cardbus_dev, func);
388 		break;
389 	}
390 
391 	if (cardbus_program_ap(cbp->cb_dip) == PCICFG_SUCCESS) {
392 		(void) cardbus_reparent_children(attach_point, cbp->cb_dip);
393 		(void) ndi_devi_free(attach_point);
394 		cbp->cb_nex_ops->enable_intr(cbp->cb_dip);
395 		return (PCICFG_SUCCESS);
396 	}
397 
398 	cardbus_err(cbp->cb_dip, 1, "Failed to program devices\n");
399 
400 cleanup:
401 	/*
402 	 * Clean up a partially created "probe state" tree.
403 	 * There are no resources allocated to the in the
404 	 * probe state.
405 	 */
406 
407 	cardbus_err(cbp->cb_dip, 6,
408 	    "Look up device [0x%x] function [0x%x] to clean up\n",
409 	    cardbus_dev, func);
410 
411 	cardbus_err(cbp->cb_dip, 6,
412 	    "Cleaning up device [0x%x] function [0x%x]\n",
413 	    cardbus_dev, func);
414 
415 	/*
416 	 * If this was a bridge device it will have a
417 	 * probe handle - if not, no harm in calling this.
418 	 */
419 	(void) cardbus_destroy_phdl(cbp->cb_dip);
420 
421 	if (ddi_get_child(attach_point)) {
422 		/*
423 		 * This will free up the node
424 		 */
425 		(void) ndi_devi_offline(ddi_get_child(attach_point),
426 		    NDI_UNCONFIG|NDI_DEVI_REMOVE);
427 	}
428 	(void) ndi_devi_free(attach_point);
429 
430 	return (PCICFG_FAILURE);
431 }
432 
433 int
434 cardbus_unconfigure(cbus_t *cbp)
435 {
436 	ddi_acc_handle_t config_handle;
437 	dev_info_t *dip = cbp->cb_dip;
438 
439 	cbp->cb_nex_ops->disable_intr(dip);
440 	if (pci_config_setup(dip, &config_handle) == DDI_SUCCESS) {
441 		disable_cardbus_bridge(dip, config_handle);
442 		(void) pci_config_teardown(&config_handle);
443 	} else {
444 		cardbus_err(dip, 1,
445 		    "cardbus_unconfigure(): Failed to setup config space\n");
446 	}
447 
448 	(void) cardbus_free_chunk(dip);
449 	cardbus_err(dip, 6,
450 	    "cardbus_unconfigure: calling cardbus_free_bridge_resources\n");
451 	(void) cardbus_free_bridge_resources(dip);
452 
453 	return (PCICFG_SUCCESS);
454 }
455 
456 int
457 cardbus_teardown_device(dev_info_t *dip)
458 {
459 	/*
460 	 * Free up resources associated with 'dip'
461 	 */
462 
463 	if (cardbus_free_resources(dip) != PCICFG_SUCCESS) {
464 		cardbus_err(dip, 1,
465 		    "cardbus_teardown_device: Failed to free resources\n");
466 		return (PCICFG_FAILURE);
467 	}
468 
469 	if (ndi_devi_offline(dip, NDI_DEVI_REMOVE) != NDI_SUCCESS) {
470 		cardbus_err(dip, 1,
471 		    "cardbus_teardown_device: "
472 		    "Failed to offline and remove node\n");
473 		return (PCICFG_FAILURE);
474 	}
475 
476 	return (PCICFG_SUCCESS);
477 }
478 
479 /*
480  * Get the primary pci bus number. This should be the lowest number
481  * in the bus-range property of our parent.
482  */
483 int
484 cardbus_primary_busno(dev_info_t *dip)
485 {
486 	int	len, rval;
487 	char	bus_type[16] = "(unknown)";
488 	dev_info_t *par = ddi_get_parent(dip);
489 	cardbus_bus_range_t *bus_range;
490 
491 	ASSERT(strcmp(ddi_driver_name(dip), "pcic") == 0);
492 	len = sizeof (bus_type);
493 	if ((ddi_prop_op(DDI_DEV_T_ANY, par, PROP_LEN_AND_VAL_BUF,
494 	    DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS,
495 	    "device_type",
496 	    (caddr_t)&bus_type, &len) == DDI_SUCCESS)) {
497 		ASSERT((strcmp(bus_type, "pci") == 0) ||
498 		    (strcmp(bus_type, "cardbus") == 0));
499 		if (ddi_getlongprop(DDI_DEV_T_ANY, par, 0, "bus-range",
500 		    (caddr_t)&bus_range, &len) == DDI_PROP_SUCCESS) {
501 			cardbus_err(dip, 9,
502 			    "cardbus_primary_busno: bus range is %d to %d\n",
503 			    bus_range->lo, bus_range->hi);
504 			rval = (int)bus_range->lo;
505 			kmem_free((caddr_t)bus_range, len);
506 			return (rval);
507 		}
508 	}
509 
510 	cardbus_err(dip, 2,
511 	    "cardbus_primary_busno: Not a pci device or no bus-range\n");
512 	return (-1);
513 }
514 
515 static cardbus_phdl_t *
516 cardbus_find_phdl(dev_info_t *dip)
517 {
518 	cardbus_phdl_t *entry;
519 
520 	mutex_enter(&cardbus_list_mutex);
521 	for (entry = cardbus_phdl_list; entry != NULL; entry = entry->next) {
522 		if (entry->dip == dip) {
523 			mutex_exit(&cardbus_list_mutex);
524 			return (entry);
525 		}
526 	}
527 	mutex_exit(&cardbus_list_mutex);
528 
529 	/*
530 	 * Did'nt find entry - create one
531 	 */
532 	return (cardbus_create_phdl(dip));
533 }
534 
535 static cardbus_phdl_t *
536 cardbus_create_phdl(dev_info_t *dip)
537 {
538 	cardbus_phdl_t *new;
539 
540 	new = (cardbus_phdl_t *)kmem_zalloc(sizeof (cardbus_phdl_t), KM_SLEEP);
541 
542 	new->dip = dip;
543 	new->io_gran = CBCFG_IOGRAN;
544 	new->memory_gran = CBCFG_MEMGRAN;
545 	mutex_enter(&cardbus_list_mutex);
546 	new->next = cardbus_phdl_list;
547 	cardbus_phdl_list = new;
548 	mutex_exit(&cardbus_list_mutex);
549 
550 	return (new);
551 }
552 
553 static int
554 cardbus_destroy_phdl(dev_info_t *dip)
555 {
556 	cardbus_phdl_t *entry;
557 	cardbus_phdl_t *follow = NULL;
558 	ra_return_t	res;
559 
560 	mutex_enter(&cardbus_list_mutex);
561 	for (entry = cardbus_phdl_list; entry != NULL; follow = entry,
562 	    entry = entry->next) {
563 		if (entry->dip == dip) {
564 			if (entry == cardbus_phdl_list) {
565 				cardbus_phdl_list = entry->next;
566 			} else {
567 				follow->next = entry->next;
568 			}
569 			/*
570 			 * If this entry has any allocated memory
571 			 * or IO space associated with it, that
572 			 * must be freed up.
573 			 */
574 			if (entry->memory_len > 0) {
575 				res.ra_addr_lo = entry->memory_base;
576 				res.ra_len = entry->memory_len;
577 				(void) pcmcia_free_mem(entry->res_dip, &res);
578 #ifdef  _LP64
579 				cardbus_err(dip, 8,
580 				    "cardbus_destroy_phdl: "
581 				    "MEMORY BASE = [0x%lx] length [0x%lx]\n",
582 				    entry->memory_base, entry->memory_len);
583 #else
584 				cardbus_err(dip, 8,
585 				    "cardbus_destroy_phdl: "
586 				    "MEMORY BASE = [0x%llx] length [0x%llx]\n",
587 				    entry->memory_base, entry->memory_len);
588 #endif
589 			}
590 			if (entry->io_len > 0) {
591 				res.ra_addr_lo = entry->io_base;
592 				res.ra_len = entry->io_len;
593 				(void) pcmcia_free_io(entry->res_dip, &res);
594 				cardbus_err(dip, 8,
595 				    "cardbus_destroy_phdl: "
596 				    "IO BASE = [0x%x] length [0x%x]\n",
597 				    entry->io_base, entry->io_len);
598 			}
599 			/*
600 			 * Destroy this entry
601 			 */
602 			kmem_free((caddr_t)entry, sizeof (cardbus_phdl_t));
603 			mutex_exit(&cardbus_list_mutex);
604 			return (PCICFG_SUCCESS);
605 		}
606 	}
607 
608 	mutex_exit(&cardbus_list_mutex);
609 
610 	/*
611 	 * Didn't find the entry
612 	 */
613 	return (PCICFG_FAILURE);
614 }
615 
616 static int
617 cardbus_program_ap(dev_info_t *dip)
618 {
619 	cardbus_phdl_t *phdl;
620 	uint8_t header_type, sec_bus;
621 	ddi_acc_handle_t handle;
622 
623 	if (pci_config_setup(dip, &handle) != DDI_SUCCESS) {
624 		cardbus_err(dip, 1,
625 		    "cardbus_program_ap: Failed to map config space!\n");
626 		return (PCICFG_FAILURE);
627 	}
628 
629 	header_type = pci_config_get8(handle, PCI_CONF_HEADER);
630 	sec_bus = pci_config_get8(handle, PCI_BCNF_SECBUS);
631 
632 	cardbus_err(dip, 6,
633 	    "cardbus_program_ap (header_type=0x%x)\n", header_type);
634 	(void) pci_config_teardown(&handle);
635 
636 	/*
637 	 * Header type two is PCI to Cardbus bridge, see page 43 of the
638 	 * CL-PD6832 data sheet
639 	 */
640 	switch (header_type & PCI_HEADER_TYPE_M) {
641 	case PCI_HEADER_CARDBUS:
642 		cardbus_err(dip, 8,
643 		    "cardbus_program_ap calling cardbus_allocate_chunk\n");
644 		if (cardbus_allocate_chunk(dip,
645 		    header_type & PCI_HEADER_TYPE_M,
646 		    sec_bus) != PCICFG_SUCCESS) {
647 			cardbus_err(dip, 1,
648 			    "cardbus_program_ap: "
649 			    "Not enough memory to hotplug\n");
650 			(void) cardbus_destroy_phdl(dip);
651 			return (PCICFG_FAILURE);
652 		}
653 
654 		cardbus_err(dip, 8,
655 		    "cardbus_program_ap calling cardbus_find_phdl\n");
656 		phdl = cardbus_find_phdl(dip);
657 		ASSERT(phdl);
658 
659 		if (phdl == NULL) {
660 			cardbus_err(dip, 1, "cardbus_find_phdl failed\n");
661 			return (PCICFG_FAILURE);
662 		}
663 		phdl->error = PCICFG_SUCCESS;
664 		cardbus_err(dip, 8,
665 		    "cardbus_program_ap calling cardbus_topbridge_assign\n");
666 		cardbus_topbridge_assign(dip, phdl);
667 
668 		if (phdl->error != PCICFG_SUCCESS) {
669 			cardbus_err(dip, 1, "Problem assigning bridge\n");
670 			(void) cardbus_destroy_phdl(dip);
671 			return (phdl->error);
672 		}
673 		break;
674 
675 	default:
676 		return (PCICFG_FAILURE);
677 	}
678 
679 	return (PCICFG_SUCCESS);
680 }
681 
682 static void
683 cardbus_topbridge_assign(dev_info_t *dip, cardbus_phdl_t *entry)
684 {
685 	ddi_acc_handle_t handle;
686 	uint8_t header_type;
687 
688 	cardbus_err(dip, 6, "cardbus_topbridge_assign\n");
689 
690 	if (pci_config_setup(dip, &handle) != DDI_SUCCESS) {
691 		cardbus_err(dip, 1,
692 		    "cardbus_topbridge_bridge_assign: "
693 		    "Failed to map config space!\n");
694 		return;
695 	}
696 
697 	header_type = pci_config_get8(handle,
698 	    PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
699 
700 	/* cardbus bridge is the same as PCI-PCI bridge */
701 	ASSERT((header_type == PCI_HEADER_PPB) ||
702 	    (header_type == PCI_HEADER_CARDBUS));
703 
704 	(void) cardbus_bridge_ranges(dip, entry, handle);
705 
706 	(void) pci_config_teardown(&handle);
707 }
708 
709 static int
710 cardbus_bridge_ranges(dev_info_t *dip, cardbus_phdl_t *entry,
711 			ddi_acc_handle_t handle)
712 {
713 	cardbus_range_t range[PCICFG_RANGE_LEN];
714 	int bus_range[2];
715 	int i;
716 
717 	cardbus_err(dip, 8, "cardbus_bridge_ranges\n");
718 
719 	bzero((caddr_t)range, sizeof (cardbus_range_t) * PCICFG_RANGE_LEN);
720 
721 	(void) cardbus_setup_bridge(dip, entry, handle);
722 
723 	range[0].child_hi = range[0].parent_hi |= (PCI_REG_REL_M | PCI_ADDR_IO);
724 	range[0].child_lo = range[0].parent_lo = entry->io_last;
725 	range[1].child_hi = range[1].parent_hi |= (PCI_REG_REL_M |
726 						PCI_ADDR_MEM32);
727 	range[1].child_lo = range[1].parent_lo = entry->memory_last;
728 
729 	ndi_devi_enter(dip);
730 	ddi_walk_devs(ddi_get_child(dip), cardbus_bridge_assign, (void *)entry);
731 	ndi_devi_exit(dip);
732 
733 	(void) cardbus_update_bridge(dip, entry, handle);
734 
735 	bus_range[0] = pci_config_get8(handle, PCI_BCNF_SECBUS);
736 	bus_range[1] = pci_config_get8(handle, PCI_BCNF_SUBBUS);
737 
738 	cardbus_err(dip, 8,
739 	    "Set up bus-range property to %u->%u\n",
740 	    bus_range[0], bus_range[1]);
741 
742 	if ((i = ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
743 	    "bus-range",
744 	    bus_range, 2)) != DDI_SUCCESS) {
745 
746 		if (i == DDI_PROP_NOT_FOUND) {
747 			cardbus_err(dip, 8,
748 			    "Create bus-range property, %u->%u\n",
749 			    bus_range[0], bus_range[1]);
750 			i = ddi_prop_create(DDI_DEV_T_NONE, dip,
751 			    DDI_PROP_CANSLEEP,
752 			    "bus-range", (caddr_t)bus_range,
753 			    sizeof (bus_range));
754 		}
755 
756 		if (i != DDI_PROP_SUCCESS) {
757 			cardbus_err(dip, 1,
758 			    "Failed to set bus-range property, %u->%u (%d)\n",
759 			    bus_range[0], bus_range[1], i);
760 			entry->error = PCICFG_FAILURE;
761 			return (DDI_WALK_TERMINATE);
762 		}
763 	}
764 
765 	if (entry->io_len > 0) {
766 		range[0].size_lo = entry->io_last - entry->io_base;
767 		if (cardbus_update_ranges_prop(dip, &range[0])) {
768 			cardbus_err(dip, 1, "Failed to update ranges (i/o)\n");
769 			entry->error = PCICFG_FAILURE;
770 			return (DDI_WALK_TERMINATE);
771 		}
772 	}
773 	if (entry->memory_len > 0) {
774 		range[1].size_lo = entry->memory_last - entry->memory_base;
775 		if (cardbus_update_ranges_prop(dip, &range[1])) {
776 			cardbus_err(dip, 1,
777 			    "Failed to update ranges (memory)\n");
778 			entry->error = PCICFG_FAILURE;
779 			return (DDI_WALK_TERMINATE);
780 		}
781 	}
782 
783 	return (DDI_WALK_PRUNECHILD);
784 }
785 static int
786 cardbus_bridge_assign(dev_info_t *dip, void *hdl)
787 {
788 	ddi_acc_handle_t handle;
789 	pci_regspec_t *reg;
790 	int length;
791 	int rcount;
792 	int i;
793 	int offset;
794 	uint64_t mem_answer;
795 	uint32_t io_answer, request;
796 	uint8_t header_type, base_class;
797 	cardbus_phdl_t *entry = (cardbus_phdl_t *)hdl;
798 
799 	/*
800 	 * Ignore the attachment point and pcs.
801 	 */
802 	if (strcmp(ddi_binding_name(dip), "hp_attachment") == 0 ||
803 	    strcmp(ddi_binding_name(dip), "pcs") == 0) {
804 		cardbus_err(dip, 8, "cardbus_bridge_assign: Ignoring\n");
805 		return (DDI_WALK_CONTINUE);
806 	}
807 
808 
809 	cardbus_err(dip, 6, "cardbus_bridge_assign\n");
810 
811 	if (entry == NULL) {
812 		cardbus_err(dip, 1, "Failed to get entry\n");
813 		return (DDI_WALK_TERMINATE);
814 	}
815 	if (cardbus_config_setup(dip, &handle) != DDI_SUCCESS) {
816 		cardbus_err(dip, 1,
817 		    "cardbus_bridge_assign: Failed to map config space!\n");
818 		entry->error = PCICFG_FAILURE;
819 		return (DDI_WALK_TERMINATE);
820 	}
821 
822 	header_type = pci_config_get8(handle, PCI_CONF_HEADER) &
823 		PCI_HEADER_TYPE_M;
824 	base_class = pci_config_get8(handle, PCI_CONF_BASCLASS);
825 
826 	/*
827 	 * This function is not called for the top bridge and we are
828 	 * not enumerating down a further cardbus interface yet!
829 	 */
830 	if (base_class == PCI_CLASS_BRIDGE) {
831 		uint8_t	sub_class;
832 
833 		sub_class = pci_config_get8(handle, PCI_CONF_SUBCLASS);
834 
835 		switch (sub_class) {
836 		case PCI_BRIDGE_PCI:
837 			if (header_type == PCI_HEADER_PPB) {
838 				i = cardbus_bridge_ranges(dip, entry, handle);
839 				(void) cardbus_config_teardown(&handle);
840 				return (i);
841 			}
842 			goto bad_device;
843 
844 		case PCI_BRIDGE_ISA:
845 			i = cardbus_isa_bridge_ranges(dip, entry, handle);
846 			(void) cardbus_config_teardown(&handle);
847 			return (i);
848 
849 		case PCI_BRIDGE_CARDBUS:
850 			/*
851 			 * Fall through, there should be at least one register
852 			 * set for this.
853 			 */
854 			break;
855 
856 		case PCI_BRIDGE_OTHER:
857 		default:
858 			break;
859 		}
860 	}
861 
862 #ifdef sparc
863 	/*
864 	 * If there is an interrupt pin set program
865 	 * interrupt line with default values.
866 	 */
867 	if (pci_config_get8(handle, PCI_CONF_IPIN)) {
868 	    pci_config_put8(handle, PCI_CONF_ILINE, 0xf);
869 	}
870 #else
871 	(void) cardbus_validate_iline(dip, handle);
872 #endif
873 
874 	/*
875 	 * A single device (under a bridge).
876 	 * For each "reg" property with a length, allocate memory
877 	 * and program the base registers.
878 	 */
879 	if (ddi_getlongprop(DDI_DEV_T_ANY, dip,
880 	    DDI_PROP_DONTPASS, "reg", (caddr_t)&reg,
881 	    &length) != DDI_PROP_SUCCESS) {
882 		cardbus_err(dip, 1, "Failed to read reg property\n");
883 		entry->error = PCICFG_FAILURE;
884 		(void) cardbus_config_teardown(&handle);
885 		return (DDI_WALK_TERMINATE);
886 	}
887 
888 	rcount = length / sizeof (pci_regspec_t);
889 	cardbus_err(dip, 9, "rcount = %d\n", rcount);
890 
891 	for (i = 0; i < rcount; i++) {
892 		if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) {
893 			offset = PCI_REG_REG_G(reg[i].pci_phys_hi);
894 			switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
895 			case PCI_REG_ADDR_G(PCI_ADDR_MEM64):
896 
897 				(void) cardbus_get_mem(ddi_get_parent(dip),
898 				    entry, reg[i].pci_size_low, &mem_answer);
899 				ASSERT(!PCICFG_HIADDR(mem_answer));
900 				pci_config_put32(handle, offset,
901 				    PCICFG_LOADDR(mem_answer));
902 				pci_config_put32(handle, offset + 4,
903 				    PCICFG_HIADDR(mem_answer));
904 				cardbus_err(dip, 8,
905 				    "REGISTER (64)LO [0x%x] ----> [0x%02x]\n",
906 				    pci_config_get32(handle, offset), offset);
907 				cardbus_err(dip, 8,
908 				    "REGISTER (64)HI [0x%x] ----> [0x%02x]\n",
909 				    pci_config_get32(handle, offset+4),
910 					offset+4);
911 				reg[i].pci_phys_low = PCICFG_HIADDR(mem_answer);
912 				reg[i].pci_phys_mid = PCICFG_LOADDR(mem_answer);
913 				break;
914 
915 			case PCI_REG_ADDR_G(PCI_ADDR_MEM32):
916 				/* allocate memory space from the allocator */
917 
918 				(void) cardbus_get_mem(ddi_get_parent(dip),
919 				    entry, reg[i].pci_size_low, &mem_answer);
920 				pci_config_put32(handle, offset, 0xffffffff);
921 				request = pci_config_get32(handle, offset);
922 
923 				pci_config_put32(handle, offset,
924 				    (uint32_t)mem_answer);
925 				reg[i].pci_phys_low = (uint32_t)mem_answer;
926 				reg[i].pci_phys_mid = 0;
927 				if (((PCI_BASE_TYPE_M & request) ==
928 					PCI_BASE_TYPE_ALL) &&
929 				    ((PCI_BASE_SPACE_M & request) ==
930 					PCI_BASE_SPACE_MEM)) {
931 					cardbus_err(dip, 8,
932 					    "REGISTER (64)LO [0x%x] ----> "
933 					    "[0x%02x]\n",
934 					    pci_config_get32(handle, offset),
935 						offset);
936 					    pci_config_put32(handle,
937 						offset + 4, 0);
938 					cardbus_err(dip, 8,
939 					    "REGISTER (64)HI [0x%x] ----> "
940 					    "[0x%02x]\n",
941 					    pci_config_get32(handle, offset+4),
942 						offset+4);
943 				} else {
944 					cardbus_err(dip, 8,
945 					    "REGISTER (32)LO [0x%x] ----> "
946 					    "[0x%02x]\n",
947 					    pci_config_get32(handle, offset),
948 					    offset);
949 				}
950 				break;
951 
952 			case PCI_REG_ADDR_G(PCI_ADDR_IO):
953 				/* allocate I/O space from the allocator */
954 
955 				(void) cardbus_get_io(ddi_get_parent(dip),
956 				    entry, reg[i].pci_size_low, &io_answer);
957 				pci_config_put32(handle, offset, io_answer);
958 				cardbus_err(dip, 8,
959 				    "REGISTER (I/O)LO [0x%x] ----> [0x%02x]\n",
960 				    pci_config_get32(handle, offset), offset);
961 				reg[i].pci_phys_low = io_answer;
962 				break;
963 
964 			default:
965 				cardbus_err(dip, 1, "Unknown register type\n");
966 				kmem_free(reg, length);
967 				(void) cardbus_config_teardown(&handle);
968 				entry->error = PCICFG_FAILURE;
969 				return (DDI_WALK_TERMINATE);
970 			} /* switch */
971 
972 			/*
973 			 * Now that memory locations are assigned,
974 			 * update the assigned address property.
975 			 */
976 			if (cardbus_update_assigned_prop(dip,
977 			    &reg[i]) != PCICFG_SUCCESS) {
978 				kmem_free(reg, length);
979 				(void) cardbus_config_teardown(&handle);
980 				entry->error = PCICFG_FAILURE;
981 				return (DDI_WALK_TERMINATE);
982 			}
983 		}
984 	}
985 	kmem_free(reg, length);
986 	enable_cardbus_device(dip, handle);
987 #ifdef CARDBUS_DEBUG
988 	if (cardbus_debug >= 9) {
989 		cardbus_dump_config(handle);
990 	}
991 #endif
992 bad_device:
993 	(void) cardbus_config_teardown(&handle);
994 	return (DDI_WALK_CONTINUE);
995 }
996 
997 static int
998 cardbus_isa_bridge_ranges(dev_info_t *dip, cardbus_phdl_t *entry,
999 			ddi_acc_handle_t handle)
1000 {
1001 	struct ebus_pci_rangespec range;
1002 	pci_regspec_t *reg;
1003 	int length;
1004 	int rcount;
1005 	uint32_t io_answer = 0xffffffff;
1006 	isa_phdl_t isa_phdl;
1007 	int i;
1008 
1009 	cardbus_err(dip, 8, "cardbus_isa_bridge_ranges\n");
1010 
1011 	bzero((caddr_t)&range, sizeof (range));
1012 
1013 #ifdef sparc
1014 	/*
1015 	 * If there is an interrupt pin set program
1016 	 * interrupt line with default values.
1017 	 */
1018 	if (pci_config_get8(handle, PCI_CONF_IPIN)) {
1019 	    pci_config_put8(handle, PCI_CONF_ILINE, 0xf);
1020 	}
1021 #else
1022 	(void) cardbus_validate_iline(dip, handle);
1023 #endif
1024 
1025 	/*
1026 	 * For each "reg" property with a length, allocate memory.
1027 	 */
1028 	if (ddi_getlongprop(DDI_DEV_T_ANY, dip,
1029 	    DDI_PROP_DONTPASS, "reg", (caddr_t)&reg,
1030 	    &length) != DDI_PROP_SUCCESS) {
1031 		cardbus_err(dip, 1, "Failed to read reg property\n");
1032 		entry->error = PCICFG_FAILURE;
1033 		return (DDI_WALK_TERMINATE);
1034 	}
1035 
1036 	rcount = length / sizeof (pci_regspec_t);
1037 
1038 	for (i = 0; i < rcount; i++) {
1039 		if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) {
1040 			switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
1041 			case PCI_REG_ADDR_G(PCI_ADDR_IO):
1042 				/* allocate I/O space from the allocator */
1043 
1044 				(void) cardbus_get_io(ddi_get_parent(dip),
1045 				    entry, reg[i].pci_size_low, &io_answer);
1046 				cardbus_err(dip, 8,
1047 				    "ISA (I/O)LO ----> [0x%x]\n", io_answer);
1048 				reg[i].pci_phys_low = io_answer;
1049 				range.phys_hi = 0;
1050 				range.phys_low = io_answer;
1051 				range.par_phys_hi = reg[i].pci_phys_hi |
1052 						PCI_REG_REL_M;
1053 				range.par_phys_low = reg[i].pci_phys_low;
1054 				range.par_phys_mid = reg[i].pci_phys_mid;
1055 				range.rng_size = reg[i].pci_size_low;
1056 				i = rcount;
1057 				break;
1058 
1059 			default:
1060 				cardbus_err(dip, 1, "Unknown register type\n");
1061 				kmem_free(reg, length);
1062 				(void) cardbus_config_teardown(&handle);
1063 				entry->error = PCICFG_FAILURE;
1064 				return (DDI_WALK_TERMINATE);
1065 			} /* switch */
1066 		}
1067 	}
1068 	kmem_free(reg, length);
1069 
1070 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
1071 	    dip, "ranges", (int *)&range,
1072 	    sizeof (range)/sizeof (int));
1073 	if (io_answer != 0xffffffff) {
1074 		isa_phdl.dip = dip;
1075 		isa_phdl.handle = handle;
1076 		isa_phdl.io_base = io_answer;
1077 		isa_phdl.io_decode_reg = 0x58; /* Pos decoded IO space 0 reg */
1078 		/* i_ndi_block_device_tree_changes(&count); */
1079 		ndi_devi_enter(dip);
1080 		ddi_walk_devs(ddi_get_child(dip),
1081 			cardbus_add_isa_reg, (void *)&isa_phdl);
1082 		/* i_ndi_allow_device_tree_changes(count); */
1083 		ndi_devi_exit(dip);
1084 	}
1085 	return (DDI_WALK_PRUNECHILD);
1086 }
1087 
1088 /*
1089  * This is specific to ITE8888 chip.
1090  */
1091 static int
1092 cardbus_add_isa_reg(dev_info_t *dip, void *arg)
1093 {
1094 	uint32_t	io_reg = 0;
1095 	int		length;
1096 	uint32_t	reg[3], *breg;
1097 	isa_phdl_t	*phdl;
1098 	uint8_t		sz;
1099 
1100 	phdl = (isa_phdl_t *)arg;
1101 	cardbus_err(dip, 6,
1102 	    "cardbus_add_isa_reg, base 0x%x\n", phdl->io_base);
1103 
1104 	if (ddi_getlongprop(DDI_DEV_T_ANY, dip,
1105 	    DDI_PROP_DONTPASS, "basereg", (caddr_t)&breg,
1106 	    &length) != DDI_PROP_SUCCESS) {
1107 		return (DDI_WALK_CONTINUE);
1108 	}
1109 
1110 	if ((length / sizeof (reg)) < 1) {
1111 		kmem_free(breg, length);
1112 		return (DDI_WALK_CONTINUE);
1113 	}
1114 
1115 	/*
1116 	 * Add the "reg" property.
1117 	 */
1118 	reg[0] = 0;
1119 	reg[1] = breg[1] + phdl->io_base;
1120 	reg[2] = breg[2];
1121 
1122 	/*
1123 	 * Generate the postive IO decode register setting.
1124 	 */
1125 	for (sz = 0; sz < 8; sz++)
1126 		if ((1<<sz) >= breg[2]) {
1127 			io_reg = breg[1]
1128 			    | (1uL <<31) /* Enable */
1129 			    | (2uL <<29) /* Medium speed */
1130 			    | (1uL <<28) /* Aliase enable, */
1131 					/* Don't care A[15:10] */
1132 			    | (sz<<24); /* Size code */
1133 			break;
1134 		}
1135 
1136 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1137 	    "reg", (int *)reg, 3);
1138 	(void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "basereg");
1139 
1140 	if (io_reg) {
1141 		pci_config_put32(phdl->handle, phdl->io_decode_reg, io_reg);
1142 		cardbus_err(dip, 6,
1143 		    "cardbus_add_isa_reg: I/O decode reg (0x%x) set to 0x%x\n",
1144 		    phdl->io_decode_reg,
1145 		    pci_config_get32(phdl->handle, phdl->io_decode_reg));
1146 		phdl->io_decode_reg += sizeof (io_reg);
1147 	} else
1148 		cardbus_err(dip, 1,
1149 		    "cardbus_add_isa_reg: register size (0x%x) too large\n",
1150 		    breg[2]);
1151 	kmem_free(breg, length);
1152 	return (DDI_WALK_CONTINUE);
1153 }
1154 
1155 /*
1156  * In case we want to ensure that some space is allocated to the
1157  * device tree below the cardbus bridge.
1158  * This is only necessary if there is a device that needs to allocate
1159  * resource below us. This can happen if there is another cardbus/PCMCIA
1160  * bridge downstream.
1161  */
1162 static uint32_t cardbus_min_spare_mem = 0;
1163 static uint32_t cardbus_min_spare_io = 0;
1164 
1165 /*
1166  * The "dip" passed to this routine is assumed to be
1167  * the device at the attachment point. Currently it is
1168  * assumed to be a bridge.
1169  */
1170 static int
1171 cardbus_allocate_chunk(dev_info_t *dip, uint8_t type, uint8_t sec_bus)
1172 {
1173 	cardbus_phdl_t		*phdl;
1174 	ndi_ra_request_t	*mem_request;
1175 	ndi_ra_request_t	*io_request;
1176 	ra_return_t		res;
1177 
1178 	/*
1179 	 * This should not find an existing entry - so
1180 	 * it will create a new one.
1181 	 */
1182 	phdl = cardbus_find_phdl(dip);
1183 	ASSERT(phdl);
1184 
1185 	mem_request = &phdl->mem_req;
1186 	io_request  = &phdl->io_req;
1187 
1188 	/*
1189 	 * Set highest_bus here.
1190 	 * Otherwise if we don't find another bridge
1191 	 * this never gets set.
1192 	 */
1193 	phdl->highest_bus = sec_bus;
1194 
1195 	/*
1196 	 * From this point in the tree - walk the devices,
1197 	 * The function passed in will read and "sum" up
1198 	 * the memory and I/O requirements and put them in
1199 	 * structure "phdl".
1200 	 */
1201 	phdl->error = PCICFG_SUCCESS;
1202 	ndi_devi_enter(dip);
1203 	ddi_walk_devs(ddi_get_child(dip), cardbus_sum_resources, (void *)phdl);
1204 	ndi_devi_exit(dip);
1205 
1206 	if (phdl->error != PCICFG_SUCCESS) {
1207 		cmn_err(CE_WARN, "Failure summing resources\n");
1208 		return (phdl->error);
1209 	}
1210 
1211 	/*
1212 	 * Call into the memory allocator with the request.
1213 	 * Record the addresses returned in the phdl
1214 	 */
1215 #ifdef  _LP64
1216 	cardbus_err(dip, 8,
1217 	    "AP requires [0x%lx] bytes of memory space, alligned 0x%x\n",
1218 	    mem_request->ra_len, phdl->memory_gran);
1219 	cardbus_err(dip, 8,
1220 	    "AP requires [0x%lx] bytes of I/O space, alligned 0x%x\n",
1221 	    io_request->ra_len, phdl->io_gran);
1222 #else
1223 	cardbus_err(dip, 8,
1224 	    "AP requires [0x%llx] bytes of memory space, alligned 0x%x\n",
1225 	    mem_request->ra_len, phdl->memory_gran);
1226 	cardbus_err(dip, 8,
1227 	    "AP requires [0x%llx] bytes of I/O space, alligned 0x%x\n",
1228 	    io_request->ra_len, phdl->io_gran);
1229 #endif
1230 
1231 	ASSERT(type == PCI_HEADER_CARDBUS);
1232 
1233 	mem_request->ra_align_mask = phdl->memory_gran - 1;
1234 	io_request->ra_align_mask = phdl->io_gran - 1;
1235 	phdl->res_dip = (dev_info_t *)-1;
1236 
1237 	mem_request->ra_len += cardbus_min_spare_mem;
1238 	if (mem_request->ra_len) {
1239 		mem_request->ra_len = PCICFG_ROUND_UP(
1240 					mem_request->ra_len,
1241 					phdl->memory_gran);
1242 #ifdef _LP64
1243 		cardbus_err(dip, 8,
1244 		    "cardbus_allocate_chunk: ndi_ra_alloc 0x%lx bytes\n",
1245 		    mem_request->ra_len);
1246 #else
1247 		cardbus_err(dip, 8,
1248 		    "cardbus_allocate_chunk: ndi_ra_alloc 0x%llx bytes\n",
1249 		    mem_request->ra_len);
1250 #endif
1251 
1252 		if (pcmcia_alloc_mem(dip, mem_request, &res,
1253 		    &phdl->res_dip) != NDI_SUCCESS) {
1254 			cmn_err(CE_WARN, "Failed to allocate memory for %s\n",
1255 				ddi_driver_name(dip));
1256 			return (PCICFG_FAILURE);
1257 		}
1258 
1259 		phdl->memory_base = phdl->memory_last = res.ra_addr_lo;
1260 		phdl->memory_len = res.ra_len;
1261 	}
1262 
1263 	io_request->ra_len += cardbus_min_spare_io;
1264 	if (io_request->ra_len) {
1265 
1266 #if defined(__x86)
1267 		io_request->ra_boundbase = 0x1000;
1268 		io_request->ra_boundlen = 0xefff;
1269 #else
1270 		io_request->ra_boundbase = 0;
1271 		io_request->ra_boundlen = PCICFG_4GIG_LIMIT;
1272 #endif
1273 		io_request->ra_flags |= NDI_RA_ALLOC_BOUNDED;
1274 		io_request->ra_len = PCICFG_ROUND_UP(io_request->ra_len,
1275 				phdl->io_gran);
1276 		io_request->ra_align_mask = max(PCICFG_IOGRAN,
1277 				phdl->io_gran) - 1;
1278 
1279 		if (pcmcia_alloc_io(dip, io_request, &res,
1280 		    &phdl->res_dip) != NDI_SUCCESS) {
1281 			cmn_err(CE_WARN, "Failed to allocate I/O space "
1282 				"for %s\n", ddi_driver_name(dip));
1283 			if (mem_request->ra_len) {
1284 				res.ra_addr_lo = phdl->memory_base;
1285 				res.ra_len = phdl->memory_len;
1286 				(void) pcmcia_free_mem(phdl->res_dip, &res);
1287 				phdl->memory_len = phdl->io_len = 0;
1288 			}
1289 			return (PCICFG_FAILURE);
1290 		}
1291 
1292 		phdl->io_base = phdl->io_last = (uint32_t)res.ra_addr_lo;
1293 		phdl->io_len  = (uint32_t)res.ra_len;
1294 	}
1295 
1296 #ifdef  _LP64
1297 	cardbus_err(dip, 6,
1298 	    "MEMORY BASE = [0x%lx] length [0x%lx]\n",
1299 	    phdl->memory_base, phdl->memory_len);
1300 #else
1301 	cardbus_err(dip, 6,
1302 	    "MEMORY BASE = [0x%llx] length [0x%llx]\n",
1303 	    phdl->memory_base, phdl->memory_len);
1304 #endif
1305 	cardbus_err(dip, 6,
1306 	    "IO BASE = [0x%x] length [0x%x]\n",
1307 	    phdl->io_base, phdl->io_len);
1308 
1309 	return (PCICFG_SUCCESS);
1310 }
1311 
1312 static int
1313 cardbus_free_chunk(dev_info_t *dip)
1314 {
1315 	uint_t	*bus;
1316 	int	k;
1317 
1318 	cardbus_err(dip, 6, "cardbus_free_chunk\n");
1319 
1320 	(void) cardbus_destroy_phdl(dip);
1321 
1322 	if (ddi_getlongprop(DDI_DEV_T_ANY, dip,
1323 	    DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus,
1324 	    &k) != DDI_PROP_SUCCESS) {
1325 		cardbus_err(dip, 1,
1326 		    "cardbus_free_chunk: Failed to read bus-range property\n");
1327 		return (PCICFG_FAILURE);
1328 	}
1329 
1330 	cardbus_err(dip, 6,
1331 	    "cardbus_free_chunk: Freeing bus [%d] range [%d]\n",
1332 	    bus[0], bus[1] - bus[0] + 1);
1333 
1334 	if (ndi_ra_free(dip,
1335 	    (uint64_t)bus[0], (uint64_t)(bus[1] - bus[0] + 1),
1336 	    NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS) != NDI_SUCCESS) {
1337 		cardbus_err(dip, 1,
1338 		    "cardbus_free_chunk: Failed to free bus numbers\n");
1339 
1340 		kmem_free(bus, k);
1341 		return (PCICFG_FAILURE);
1342 	}
1343 
1344 	kmem_free(bus, k);
1345 	return (PCICFG_SUCCESS);
1346 }
1347 
1348 /*
1349  * Put bridge registers into initial state
1350  */
1351 static void
1352 cardbus_setup_bridge(dev_info_t *dip, cardbus_phdl_t *entry,
1353 		ddi_acc_handle_t handle)
1354 {
1355 	uint8_t header_type = pci_config_get8(handle, PCI_CONF_HEADER);
1356 
1357 #ifdef _LP64
1358 	cardbus_err(NULL, 6,
1359 	    "cardbus_setup_bridge: "
1360 	    "highest bus %d, mem_last 0x%lx, io_last 0x%x\n",
1361 	    entry->highest_bus, entry->memory_last, entry->io_last);
1362 #else
1363 	cardbus_err(NULL, 6,
1364 	    "cardbus_setup_bridge: "
1365 	    "highest bus %d, mem_last 0x%llx, io_last 0x%x\n",
1366 	    entry->highest_bus, entry->memory_last, entry->io_last);
1367 #endif
1368 
1369 	if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) {
1370 		uint32_t uval;
1371 
1372 		/*
1373 		 * The highest bus seen during probing is
1374 		 * the max-subordinate bus
1375 		 */
1376 		pci_config_put8(handle, PCI_BCNF_SUBBUS, entry->highest_bus);
1377 
1378 		uval = PCICFG_ROUND_UP(entry->memory_last, PCICFG_MEMGRAN);
1379 		if (uval != entry->memory_last) {
1380 #ifdef _LP64
1381 			cardbus_err(dip, 8,
1382 			    "Adding [0x%lx] before bridge (mem)\n",
1383 			    uval - entry->memory_last);
1384 #else
1385 			cardbus_err(dip, 8,
1386 			    "Adding [0x%llx] before bridge (mem)\n",
1387 			    uval - entry->memory_last);
1388 #endif
1389 			(void) cardbus_get_mem(ddi_get_parent(dip), entry,
1390 			    uval - entry->memory_last, NULL);
1391 		}
1392 
1393 		/*
1394 		 * Program the memory base register with the
1395 		 * start of the memory range
1396 		 */
1397 #ifdef _LP64
1398 		cardbus_err(NULL, 8,
1399 		    "store 0x%x(0x%lx) in pci bridge memory base register\n",
1400 		    PCICFG_HIWORD(PCICFG_LOADDR(uval)),
1401 		    entry->memory_last);
1402 #else
1403 		cardbus_err(NULL, 8,
1404 		    "store 0x%x(0x%llx) in pci bridge memory base register\n",
1405 		    PCICFG_HIWORD(PCICFG_LOADDR(uval)),
1406 		    entry->memory_last);
1407 #endif
1408 		pci_config_put16(handle, PCI_BCNF_MEM_BASE,
1409 		    PCICFG_HIWORD(PCICFG_LOADDR(uval)));
1410 
1411 		uval = PCICFG_ROUND_UP(entry->io_last, PCICFG_IOGRAN);
1412 		if (uval != entry->io_last) {
1413 			cardbus_err(dip, 8,
1414 			    "Adding [0x%x] before bridge (I/O)\n",
1415 			    uval - entry->io_last);
1416 			(void) cardbus_get_io(ddi_get_parent(dip), entry,
1417 			    uval - entry->io_last, NULL);
1418 		}
1419 		cardbus_err(NULL, 8,
1420 		    "store 0x%02x/0x%04x(0x%x) in "
1421 		    "pci bridge I/O hi/low base register\n",
1422 		    PCICFG_HIWORD(PCICFG_LOADDR(uval)),
1423 		    PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(uval))),
1424 		    entry->io_last);
1425 		/*
1426 		 * Program the I/O base register with the start of the I/O range
1427 		 */
1428 		pci_config_put8(handle, PCI_BCNF_IO_BASE_LOW,
1429 		    PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(uval))));
1430 
1431 		pci_config_put16(handle, PCI_BCNF_IO_BASE_HI,
1432 		    PCICFG_HIWORD(PCICFG_LOADDR(uval)));
1433 
1434 		/*
1435 		 * Clear status bits
1436 		 */
1437 		pci_config_put16(handle, PCI_BCNF_SEC_STATUS, 0xffff);
1438 
1439 		/*
1440 		 * Turn off prefetchable range
1441 		 */
1442 		pci_config_put32(handle, PCI_BCNF_PF_BASE_LOW, 0x0000ffff);
1443 		pci_config_put32(handle, PCI_BCNF_PF_BASE_HIGH, 0xffffffff);
1444 
1445 		pci_config_put32(handle, PCI_BCNF_PF_LIMIT_HIGH, 0x0);
1446 
1447 #ifdef sparc
1448 		/*
1449 		 * If there is an interrupt pin set program
1450 		 * interrupt line with default values.
1451 		 */
1452 		if (pci_config_get8(handle, PCI_CONF_IPIN)) {
1453 		    pci_config_put8(handle, PCI_CONF_ILINE, 0xf);
1454 		}
1455 #else
1456 		(void) cardbus_validate_iline(dip, handle);
1457 #endif
1458 
1459 
1460 	} else if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_CARDBUS) {
1461 
1462 		/*
1463 		 * The highest bus seen during probing is
1464 		 * the max-subordinate bus
1465 		 */
1466 		pci_config_put8(handle, PCI_CBUS_SUB_BUS_NO,
1467 		    entry->highest_bus);
1468 
1469 		/*
1470 		 * Program the memory base register with the
1471 		 * start of the memory range
1472 		 */
1473 #ifdef _LP64
1474 		cardbus_err(NULL, 8,
1475 		    "store 0x%x(0x%lx) in "
1476 		    "cardbus memory base register 0, len 0x%lx\n",
1477 		    PCICFG_LOADDR(entry->memory_last), entry->memory_last,
1478 		    entry->memory_len);
1479 #else
1480 		cardbus_err(NULL, 8,
1481 		    "store 0x%x(0x%llx) in "
1482 		    "cardbus memory base register 0, len 0x%llx\n",
1483 		    PCICFG_LOADDR(entry->memory_last), entry->memory_last,
1484 		    entry->memory_len);
1485 #endif
1486 
1487 		pci_config_put32(handle, PCI_CBUS_MEM_BASE0,
1488 		    PCICFG_LOADDR(entry->memory_last));
1489 
1490 		/*
1491 		 * Program the I/O base register with the start of the I/O range
1492 		 */
1493 		cardbus_err(NULL, 8,
1494 		    "store 0x%x in cb IO base register 0 len 0x%x\n",
1495 		    PCICFG_LOADDR(entry->io_last),
1496 		    entry->io_len);
1497 
1498 		pci_config_put32(handle, PCI_CBUS_IO_BASE0,
1499 		    PCICFG_LOADDR(entry->io_last));
1500 
1501 		/*
1502 		 * Clear status bits
1503 		 */
1504 		pci_config_put16(handle, PCI_CBUS_SEC_STATUS, 0xffff);
1505 
1506 #ifdef sparc
1507 		/*
1508 		 * If there is an interrupt pin set program
1509 		 * interrupt line with default values.
1510 		 */
1511 		if (pci_config_get8(handle, PCI_CONF_IPIN)) {
1512 		    pci_config_put8(handle, PCI_CONF_ILINE, 0xf);
1513 		}
1514 #else
1515 		(void) cardbus_validate_iline(dip, handle);
1516 #endif
1517 
1518 
1519 		/*
1520 		 * LATER: use these registers
1521 		 */
1522 		pci_config_put32(handle, PCI_CBUS_MEM_BASE1, 0);
1523 		pci_config_put32(handle, PCI_CBUS_MEM_LIMIT1, 0);
1524 		pci_config_put32(handle, PCI_CBUS_IO_BASE1, 0);
1525 		pci_config_put32(handle, PCI_CBUS_IO_LIMIT1, 0);
1526 	} else {
1527 		cmn_err(CE_WARN, "header type 0x%x, probably unknown bridge\n",
1528 		    header_type & PCI_HEADER_TYPE_M);
1529 	}
1530 
1531 	cardbus_err(NULL, 7, "cardbus_setup_bridge complete\n");
1532 }
1533 
1534 static void
1535 cardbus_update_bridge(dev_info_t *dip, cardbus_phdl_t *entry,
1536 		ddi_acc_handle_t handle)
1537 {
1538 	uint_t length;
1539 	uint16_t word16 = pci_config_get16(handle, PCI_CONF_COMM);
1540 	const	uint8_t header_type = pci_config_get8(handle, PCI_CONF_HEADER)
1541 			& PCI_HEADER_TYPE_M;
1542 	uint32_t bridge_gran;
1543 	uint64_t rlval;
1544 
1545 	if (header_type == PCI_HEADER_CARDBUS)
1546 		bridge_gran = CBCFG_MEMGRAN;
1547 	else
1548 		bridge_gran = PCICFG_MEMGRAN;
1549 
1550 	/*
1551 	 * Program the memory limit register with the end of the memory range
1552 	 */
1553 #ifdef _LP64
1554 	cardbus_err(dip, 6,
1555 	    "cardbus_update_bridge: Mem base 0x%lx len 0x%lx "
1556 	    "last 0x%lx gran 0x%x gran end 0x%lx\n",
1557 	    entry->memory_base, entry->memory_len,
1558 	    entry->memory_last, entry->memory_gran,
1559 	    PCICFG_ROUND_UP(entry->memory_last, entry->memory_gran));
1560 #else
1561 	cardbus_err(dip, 6,
1562 	    "cardbus_update_bridge: Mem base 0x%llx len 0x%llx "
1563 	    "last 0x%llx gran 0x%x gran end 0x%lx\n",
1564 	    entry->memory_base, entry->memory_len,
1565 	    entry->memory_last, entry->memory_gran,
1566 	    PCICFG_ROUND_UP(entry->memory_last, entry->memory_gran));
1567 #endif
1568 	/*
1569 	 * Since this is a bridge, the rest of this range will
1570 	 * be responded to by the bridge.  We have to round up
1571 	 * so no other device claims it.
1572 	 */
1573 	length = PCICFG_ROUND_UP(entry->memory_last + cardbus_min_spare_mem,
1574 	    bridge_gran) - entry->memory_last;
1575 
1576 	if (length > 0) {
1577 		/*
1578 		 * This is to allow space that isn't actually being used by
1579 		 * anything to be allocated by devices such as a downstream
1580 		 * PCMCIA controller.
1581 		 */
1582 		(void) cardbus_get_mem(dip, entry, length, NULL);
1583 		cardbus_err(dip, 8,
1584 		    "Added [0x%x] at the top of the bridge (mem)\n", length);
1585 	}
1586 
1587 	if (entry->memory_len) {
1588 		if (header_type == PCI_HEADER_CARDBUS) {
1589 			rlval = PCICFG_ROUND_DOWN(entry->memory_last - 1,
1590 			    CBCFG_MEMGRAN);
1591 #ifdef _LP64
1592 			cardbus_err(dip, 8,
1593 			    "store 0x%x(0x%lx) in memory limit register 0\n",
1594 			    PCICFG_LOADDR(rlval), rlval);
1595 #else
1596 			cardbus_err(dip, 8,
1597 			    "store 0x%x(0x%llx) in memory limit register 0\n",
1598 			    PCICFG_LOADDR(rlval), rlval);
1599 #endif
1600 			pci_config_put32(handle, PCI_CBUS_MEM_LIMIT0,
1601 			    PCICFG_LOADDR(rlval));
1602 		} else {
1603 			rlval = PCICFG_ROUND_DOWN(entry->memory_last - 1,
1604 			    PCICFG_MEMGRAN);
1605 #ifdef _LP64
1606 			cardbus_err(dip, 8,
1607 			    "store 0x%x(0x%lx) in memory limit register\n",
1608 			    PCICFG_HIWORD(PCICFG_LOADDR(rlval)),
1609 			    rlval);
1610 #else
1611 			cardbus_err(dip, 8,
1612 			    "store 0x%x(0x%llx) in memory limit register\n",
1613 			    PCICFG_HIWORD(PCICFG_LOADDR(rlval)),
1614 			    rlval);
1615 #endif
1616 			pci_config_put16(handle, PCI_BCNF_MEM_LIMIT,
1617 			    PCICFG_HIWORD(PCICFG_LOADDR(rlval)));
1618 		}
1619 		word16 |= PCI_COMM_MAE;
1620 	}
1621 
1622 	cardbus_err(dip, 6,
1623 	    "cardbus_update_bridge: I/O base 0x%x len 0x%x last 0x%x "
1624 	    "gran 0x%x gran_end 0x%lx\n",
1625 	    entry->io_base, entry->io_len, entry->io_last, entry->io_gran,
1626 	    PCICFG_ROUND_UP(entry->io_last, entry->io_gran));
1627 
1628 	if (header_type == PCI_HEADER_CARDBUS)
1629 		bridge_gran = CBCFG_IOGRAN;
1630 	else
1631 		bridge_gran = PCICFG_IOGRAN;
1632 
1633 	/*
1634 	 * Same as above for I/O space. Since this is a
1635 	 * bridge, the rest of this range will be responded
1636 	 * to by the bridge.  We have to round up so no
1637 	 * other device claims it.
1638 	 */
1639 	length = PCICFG_ROUND_UP(entry->io_last + cardbus_min_spare_io,
1640 	    bridge_gran) - entry->io_last;
1641 	if (length > 0) {
1642 		(void) cardbus_get_io(dip, entry, length, NULL);
1643 		cardbus_err(dip, 8,
1644 		    "Added [0x%x] at the top of the bridge (I/O)\n",  length);
1645 	}
1646 
1647 	/*
1648 	 * Program the I/O limit register with the end of the I/O range
1649 	 */
1650 	if (entry->io_len) {
1651 		if (header_type == PCI_HEADER_CARDBUS) {
1652 			rlval = PCICFG_ROUND_DOWN(entry->io_last - 1,
1653 			    CBCFG_IOGRAN);
1654 #ifdef _LP64
1655 			cardbus_err(dip, 8,
1656 			    "store 0x%lx in IO limit register 0\n", rlval);
1657 #else
1658 			cardbus_err(dip, 8,
1659 			    "store 0x%llx in IO limit register 0\n", rlval);
1660 #endif
1661 			pci_config_put32(handle, PCI_CBUS_IO_LIMIT0, rlval);
1662 		} else {
1663 			rlval = PCICFG_ROUND_DOWN(entry->io_last - 1,
1664 			    PCICFG_IOGRAN);
1665 #ifdef _LP64
1666 			cardbus_err(dip, 8,
1667 			    "store 0x%x/0x%x(0x%lx) in "
1668 			    "IO limit low/hi register\n",
1669 			    PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(rlval))),
1670 			    PCICFG_HIWORD(PCICFG_LOADDR(rlval)),
1671 			    rlval);
1672 #else
1673 			cardbus_err(dip, 8,
1674 			    "store 0x%x/0x%x(0x%llx) in "
1675 			    "IO limit low/hi register\n",
1676 			    PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(rlval))),
1677 			    PCICFG_HIWORD(PCICFG_LOADDR(rlval)),
1678 			    rlval);
1679 #endif
1680 
1681 			pci_config_put8(handle, PCI_BCNF_IO_LIMIT_LOW,
1682 			    PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(rlval))));
1683 			pci_config_put16(handle, PCI_BCNF_IO_LIMIT_HI,
1684 			    PCICFG_HIWORD(PCICFG_LOADDR(rlval)));
1685 		}
1686 		word16 |= PCI_COMM_IO;
1687 	}
1688 
1689 	pci_config_put16(handle, PCI_CONF_COMM, word16);
1690 }
1691 
1692 static void
1693 cardbus_get_mem(dev_info_t *dip, cardbus_phdl_t *entry,
1694 		uint32_t length, uint64_t *ans)
1695 {
1696 	uint32_t hole;
1697 
1698 #ifdef  _LP64
1699 	cardbus_err(NULL, 6,
1700 	    "cardbus_get_mem: memory_last 0x%lx, length 0x%x, "
1701 	    "memory_base 0x%lx, memory_len 0x%lx ans=0x%p\n",
1702 	    entry->memory_last, length,
1703 	    entry->memory_base, entry->memory_len, (void *) ans);
1704 #else
1705 	cardbus_err(NULL, 6,
1706 	    "cardbus_get_mem: memory_last 0x%llx, length 0x%x, "
1707 	    "memory_base 0x%llx, memory_len 0x%llx ans=0x%p\n",
1708 	    entry->memory_last, length,
1709 	    entry->memory_base, entry->memory_len, (void *) ans);
1710 #endif
1711 
1712 	if (ans) {
1713 		/*
1714 		 * Round up the request to the "size" boundary
1715 		 */
1716 		hole = PCICFG_ROUND_UP(entry->memory_last, length)
1717 			- entry->memory_last;
1718 		if (hole != 0) {
1719 			(void) cardbus_update_available_prop(dip,
1720 			    PCI_ADDR_MEM32,
1721 			    entry->memory_last,
1722 			    (uint64_t)hole);
1723 			entry->memory_last += hole;
1724 
1725 #ifdef  _LP64
1726 			cardbus_err(NULL, 6,
1727 			    "cardbus_get_mem: "
1728 			    "rounded memory_last up by 0x%x to 0x%lx, ",
1729 			    hole, entry->memory_last);
1730 #else
1731 			cardbus_err(NULL, 6,
1732 			    "cardbus_get_mem: "
1733 			    "rounded memory_last up by 0x%x to 0x%llx, ",
1734 			    hole, entry->memory_last);
1735 #endif
1736 		}
1737 	} else
1738 		(void) cardbus_update_available_prop(dip, PCI_ADDR_MEM32,
1739 			entry->memory_last,
1740 			(uint64_t)length);
1741 
1742 	/*
1743 	 * These routines should parcel out the memory
1744 	 * completely.  There should never be a case of
1745 	 * over running the bounds.
1746 	 */
1747 	if ((entry->memory_last + length) >
1748 	    (entry->memory_base + entry->memory_len))
1749 #ifdef  _LP64
1750 		cardbus_err(NULL, 1,
1751 		    "cardbus_get_mem: assert will fail %ld <= %ld,"
1752 		    "(0x%lx + 0x%x) <= (0x%lx + 0x%lx)\n",
1753 #else
1754 		cardbus_err(NULL, 1,
1755 		    "cardbus_get_mem: assert will fail %lld <= %lld, "
1756 		    "(0x%llx + 0x%x) <= (0x%llx + 0x%llx)\n",
1757 #endif
1758 		    entry->memory_last + length,
1759 		    entry->memory_base + entry->memory_len,
1760 		    entry->memory_last,
1761 		    length,
1762 		    entry->memory_base,
1763 		    entry->memory_len);
1764 
1765 	ASSERT((entry->memory_last + length) <=
1766 	(entry->memory_base + entry->memory_len));
1767 	/*
1768 	 * If ans is NULL don't return anything,
1769 	 * they are just asking to reserve the memory.
1770 	 */
1771 	if (ans != NULL)
1772 		*ans = entry->memory_last;
1773 
1774 	/*
1775 	 * Increment to the next location
1776 	 */
1777 	entry->memory_last += length;
1778 }
1779 
1780 static void
1781 cardbus_get_io(dev_info_t *dip, cardbus_phdl_t *entry,
1782 		uint32_t length, uint32_t *ans)
1783 {
1784 	uint32_t	hole;
1785 
1786 	cardbus_err(NULL, 6,
1787 	    "cardbus_get_io: io_last 0x%x, length 0x%x, "
1788 	    "io_base 0x%x, io_len 0x%x ans=0x%p\n",
1789 	    entry->io_last, length,
1790 	    entry->io_base, entry->io_len, (void *) ans);
1791 
1792 	if (ans) {
1793 		/*
1794 		 * Round up the request to the "size" boundary
1795 		 */
1796 		hole = PCICFG_ROUND_UP(entry->io_last, length) - entry->io_last;
1797 		if (hole != 0) {
1798 			(void) cardbus_update_available_prop(dip, PCI_ADDR_IO,
1799 			    (uint64_t)entry->io_last,
1800 			    (uint64_t)hole);
1801 			entry->io_last += hole;
1802 
1803 			cardbus_err(NULL, 6,
1804 			    "cardbus_get_io: "
1805 			    "rounded io_last up by 0x%x to 0x%x, ",
1806 			    hole, entry->io_last);
1807 		}
1808 	} else
1809 		(void) cardbus_update_available_prop(dip, PCI_ADDR_IO,
1810 		    (uint64_t)entry->io_last,
1811 		    (uint64_t)length);
1812 	/*
1813 	 * These routines should parcel out the memory
1814 	 * completely.  There should never be a case of
1815 	 * over running the bounds.
1816 	 */
1817 	ASSERT((entry->io_last + length) <=
1818 	    (entry->io_base + entry->io_len));
1819 
1820 	/*
1821 	 * If ans is NULL don't return anything,
1822 	 * they are just asking to reserve the memory.
1823 	 */
1824 	if (ans != NULL)
1825 		*ans = entry->io_last;
1826 
1827 	/*
1828 	 * Increment to the next location
1829 	 */
1830 	entry->io_last += length;
1831 }
1832 
1833 static int
1834 cardbus_sum_resources(dev_info_t *dip, void *hdl)
1835 {
1836 	cardbus_phdl_t *entry = (cardbus_phdl_t *)hdl;
1837 	pci_regspec_t *pci_rp;
1838 	int length;
1839 	int rcount;
1840 	int i, ret;
1841 	ndi_ra_request_t *mem_request;
1842 	ndi_ra_request_t *io_request;
1843 	uint8_t header_type, base_class;
1844 	ddi_acc_handle_t handle;
1845 
1846 	/*
1847 	 * Ignore the attachment point and pcs.
1848 	 */
1849 	if (strcmp(ddi_binding_name(dip), "hp_attachment") == 0 ||
1850 	    strcmp(ddi_binding_name(dip), "pcs") == 0) {
1851 		cardbus_err(dip, 8, "cardbus_sum_resources: Ignoring\n");
1852 		return (DDI_WALK_CONTINUE);
1853 	}
1854 
1855 	mem_request = &entry->mem_req;
1856 	io_request =  &entry->io_req;
1857 
1858 	if (cardbus_config_setup(dip, &handle) != DDI_SUCCESS) {
1859 		cardbus_err(dip, 1,
1860 		    "cardbus_sum_resources: Failed to map config space!\n");
1861 		entry->error = PCICFG_FAILURE;
1862 		return (DDI_WALK_TERMINATE);
1863 	}
1864 
1865 	ret = DDI_WALK_CONTINUE;
1866 	header_type = pci_config_get8(handle, PCI_CONF_HEADER);
1867 	base_class = pci_config_get8(handle, PCI_CONF_BASCLASS);
1868 
1869 	/*
1870 	 * If its a bridge - just record the highest bus seen
1871 	 */
1872 	if (base_class == PCI_CLASS_BRIDGE) {
1873 		uint8_t	sub_class;
1874 
1875 		sub_class = pci_config_get8(handle, PCI_CONF_SUBCLASS);
1876 
1877 		switch (sub_class) {
1878 		case PCI_BRIDGE_PCI:
1879 			if ((header_type & PCI_HEADER_TYPE_M)
1880 			    == PCI_HEADER_PPB) {
1881 
1882 				if (entry->highest_bus < pci_config_get8(handle,
1883 				    PCI_BCNF_SECBUS)) {
1884 					entry->highest_bus = pci_config_get8(
1885 					    handle, PCI_BCNF_SECBUS);
1886 				}
1887 
1888 				(void) cardbus_config_teardown(&handle);
1889 #if defined(CARDBUS_DEBUG)
1890 				if (mem_request->ra_len !=
1891 				    PCICFG_ROUND_UP(mem_request->ra_len,
1892 				    PCICFG_MEMGRAN)) {
1893 
1894 #ifdef _LP64
1895 					cardbus_err(dip, 8,
1896 					    "Pre-align [0x%lx] to PCI bridge "
1897 					    "memory gran "
1898 					    "[0x%lx] -> [0x%lx]\n",
1899 					    PCICFG_ROUND_UP(mem_request->ra_len,
1900 						PCICFG_MEMGRAN) -
1901 						mem_request->ra_len,
1902 					    mem_request->ra_len,
1903 					    PCICFG_ROUND_UP(mem_request->ra_len,
1904 						PCICFG_MEMGRAN));
1905 #else
1906 					cardbus_err(dip, 8,
1907 					    "Pre-align [0x%llx] to PCI bridge "
1908 					    "memory gran "
1909 					    "[0x%llx] -> [0x%lx]\n",
1910 					    PCICFG_ROUND_UP(mem_request->ra_len,
1911 						PCICFG_MEMGRAN) -
1912 						mem_request->ra_len,
1913 					    mem_request->ra_len,
1914 					    PCICFG_ROUND_UP(mem_request->ra_len,
1915 						PCICFG_MEMGRAN));
1916 #endif
1917 				}
1918 
1919 				if (io_request->ra_len !=
1920 				    PCICFG_ROUND_UP(io_request->ra_len,
1921 				    PCICFG_IOGRAN)) {
1922 
1923 #ifdef _LP64
1924 					cardbus_err(dip, 8,
1925 					    "Pre-align [0x%lx] to PCI bridge "
1926 					    "I/O gran "
1927 					    "[0x%lx] -> [0x%lx]\n",
1928 					    PCICFG_ROUND_UP(io_request->ra_len,
1929 						PCICFG_IOGRAN) -
1930 						io_request->ra_len,
1931 					    io_request->ra_len,
1932 					    PCICFG_ROUND_UP(io_request->ra_len,
1933 						PCICFG_IOGRAN));
1934 #else
1935 					cardbus_err(dip, 8,
1936 					    "Pre-align [0x%llx] to PCI bridge "
1937 					    "I/O gran "
1938 					    "[0x%llx] -> [0x%lx]\n",
1939 					    PCICFG_ROUND_UP(io_request->ra_len,
1940 						PCICFG_IOGRAN) -
1941 						io_request->ra_len,
1942 					    io_request->ra_len,
1943 					    PCICFG_ROUND_UP(io_request->ra_len,
1944 						PCICFG_IOGRAN));
1945 #endif
1946 				}
1947 
1948 #endif
1949 				mem_request->ra_len = PCICFG_ROUND_UP(
1950 							mem_request->ra_len,
1951 							PCICFG_MEMGRAN);
1952 				io_request->ra_len = PCICFG_ROUND_UP(
1953 							io_request->ra_len,
1954 							PCICFG_IOGRAN);
1955 				if (entry->memory_gran < PCICFG_MEMGRAN)
1956 					entry->memory_gran = PCICFG_MEMGRAN;
1957 				if (entry->io_gran < PCICFG_IOGRAN)
1958 					entry->io_gran = PCICFG_IOGRAN;
1959 				ddi_walk_devs(ddi_get_child(dip),
1960 				    cardbus_sum_resources,
1961 				    (void *)entry);
1962 #if defined(CARDBUS_DEBUG)
1963 				if (mem_request->ra_len !=
1964 				    PCICFG_ROUND_UP(mem_request->ra_len +
1965 				    cardbus_min_spare_mem, PCICFG_MEMGRAN)) {
1966 
1967 #ifdef _LP64
1968 					cardbus_err(dip, 8,
1969 					    "Post-align [0x%lx] to PCI bridge "
1970 					    "memory gran "
1971 					    "[0x%lx] -> [0x%lx]\n",
1972 					    PCICFG_ROUND_UP(
1973 						mem_request->ra_len +
1974 						cardbus_min_spare_mem,
1975 						PCICFG_MEMGRAN) -
1976 						mem_request->ra_len,
1977 					    mem_request->ra_len,
1978 					    PCICFG_ROUND_UP(mem_request->ra_len
1979 						+ cardbus_min_spare_mem,
1980 						PCICFG_MEMGRAN));
1981 #else
1982 					cardbus_err(dip, 8,
1983 					    "Post-align [0x%llx] to PCI bridge "
1984 					    "memory gran "
1985 					    "[0x%llx] -> [0x%lx]\n",
1986 					    PCICFG_ROUND_UP(
1987 						mem_request->ra_len +
1988 						cardbus_min_spare_mem,
1989 						PCICFG_MEMGRAN) -
1990 						mem_request->ra_len,
1991 					    mem_request->ra_len,
1992 					    PCICFG_ROUND_UP(mem_request->ra_len
1993 						+ cardbus_min_spare_mem,
1994 						PCICFG_MEMGRAN));
1995 #endif
1996 				}
1997 
1998 				if (io_request->ra_len !=
1999 				    PCICFG_ROUND_UP(io_request->ra_len +
2000 				    cardbus_min_spare_io,
2001 				    PCICFG_IOGRAN)) {
2002 
2003 #ifdef _LP64
2004 					cardbus_err(dip, 8,
2005 					    "Post-align [0x%lx] to PCI bridge "
2006 					    "I/O gran "
2007 					    "[0x%lx] -> [0x%lx]\n",
2008 					    PCICFG_ROUND_UP(io_request->ra_len +
2009 						cardbus_min_spare_io,
2010 						PCICFG_IOGRAN) -
2011 						io_request->ra_len,
2012 					    io_request->ra_len,
2013 					    PCICFG_ROUND_UP(io_request->ra_len +
2014 						cardbus_min_spare_io,
2015 						PCICFG_IOGRAN));
2016 #else
2017 					cardbus_err(dip, 8,
2018 					    "Post-align [0x%llx] to PCI bridge "
2019 					    "I/O gran "
2020 					    "[0x%llx] -> [0x%lx]\n",
2021 					    PCICFG_ROUND_UP(io_request->ra_len +
2022 						cardbus_min_spare_io,
2023 						PCICFG_IOGRAN) -
2024 						io_request->ra_len,
2025 					    io_request->ra_len,
2026 					    PCICFG_ROUND_UP(io_request->ra_len +
2027 						cardbus_min_spare_io,
2028 						PCICFG_IOGRAN));
2029 #endif
2030 				}
2031 #endif
2032 				mem_request->ra_len = PCICFG_ROUND_UP(
2033 						mem_request->ra_len +
2034 						    cardbus_min_spare_mem,
2035 						PCICFG_MEMGRAN);
2036 				io_request->ra_len = PCICFG_ROUND_UP(
2037 						io_request->ra_len +
2038 						    cardbus_min_spare_io,
2039 						PCICFG_IOGRAN);
2040 			}
2041 			return (DDI_WALK_PRUNECHILD);
2042 
2043 		case PCI_BRIDGE_CARDBUS:
2044 			/*
2045 			 * Cardbus has I/O registers.
2046 			 */
2047 			break;
2048 
2049 		case PCI_BRIDGE_ISA:
2050 			/*
2051 			 * All the registers requirements for ISA
2052 			 * are stored in the reg structure of the bridge.
2053 			 * Children of ISA are not of type PCI
2054 			 * so must not come through here because
2055 			 * cardbus_config_setup() will fail.
2056 			 */
2057 			ret = DDI_WALK_PRUNECHILD;
2058 			break;
2059 
2060 		default:
2061 			/*
2062 			 * Treat other bridges as leaf nodes.
2063 			 */
2064 			break;
2065 		}
2066 	}
2067 
2068 	if (ddi_getlongprop(DDI_DEV_T_ANY, dip,
2069 	    DDI_PROP_DONTPASS, "reg", (caddr_t)&pci_rp,
2070 	    &length) != DDI_PROP_SUCCESS) {
2071 		/*
2072 		 * If one node in (the subtree of nodes)
2073 		 * does'nt have a "reg" property fail the
2074 		 * allocation.
2075 		 */
2076 		entry->memory_len = 0;
2077 		entry->io_len = 0;
2078 		entry->error = PCICFG_FAILURE;
2079 		(void) cardbus_config_teardown(&handle);
2080 		return (DDI_WALK_TERMINATE);
2081 	}
2082 
2083 	/*
2084 	 * For each "reg" property with a length, add that to the
2085 	 * total memory (or I/O) to allocate.
2086 	 */
2087 	rcount = length / sizeof (pci_regspec_t);
2088 
2089 	for (i = 0; i < rcount; i++) {
2090 
2091 		switch (PCI_REG_ADDR_G(pci_rp[i].pci_phys_hi)) {
2092 
2093 		case PCI_REG_ADDR_G(PCI_ADDR_MEM32):
2094 			mem_request->ra_len =
2095 				pci_rp[i].pci_size_low +
2096 				PCICFG_ROUND_UP(mem_request->ra_len,
2097 					pci_rp[i].pci_size_low);
2098 
2099 			cardbus_err(dip, 8,
2100 			    "ADDING 32 --->0x%x for BAR@0x%x\n",
2101 			    pci_rp[i].pci_size_low,
2102 			    PCI_REG_REG_G(pci_rp[i].pci_phys_hi));
2103 			/*
2104 			 * the granualarity needs to be the larger of
2105 			 * the maximum amount of memory that we're going to
2106 			 * ask for, and the PCI-PCI bridge granularity (1M)
2107 			 */
2108 			if (pci_rp[i].pci_size_low > entry->memory_gran)
2109 				entry->memory_gran = pci_rp[i].pci_size_low;
2110 			break;
2111 
2112 		case PCI_REG_ADDR_G(PCI_ADDR_MEM64):
2113 			mem_request->ra_len =
2114 				pci_rp[i].pci_size_low +
2115 				PCICFG_ROUND_UP(mem_request->ra_len,
2116 					pci_rp[i].pci_size_low);
2117 			cardbus_err(dip, 8,
2118 			    "ADDING 64 --->0x%x for BAR@0x%x\n",
2119 			    pci_rp[i].pci_size_low,
2120 			    PCI_REG_REG_G(pci_rp[i].pci_phys_hi));
2121 
2122 			if (pci_rp[i].pci_size_low > entry->memory_gran)
2123 				entry->memory_gran = pci_rp[i].pci_size_low;
2124 			break;
2125 
2126 		case PCI_REG_ADDR_G(PCI_ADDR_IO):
2127 			io_request->ra_len =
2128 				pci_rp[i].pci_size_low +
2129 				PCICFG_ROUND_UP(io_request->ra_len,
2130 					pci_rp[i].pci_size_low);
2131 			cardbus_err(dip, 8,
2132 			    "ADDING I/O --->0x%x for BAR@0x%x\n",
2133 			    pci_rp[i].pci_size_low,
2134 			    PCI_REG_REG_G(pci_rp[i].pci_phys_hi));
2135 
2136 			if (pci_rp[i].pci_size_low > entry->io_gran)
2137 				entry->io_gran = pci_rp[i].pci_size_low;
2138 			break;
2139 
2140 		default:
2141 			/* Config space register - not included */
2142 			break;
2143 		}
2144 	}
2145 
2146 	/*
2147 	 * free the memory allocated by ddi_getlongprop
2148 	 */
2149 	kmem_free(pci_rp, length);
2150 
2151 	/*
2152 	 * continue the walk to the next sibling to sum memory
2153 	 */
2154 
2155 	(void) cardbus_config_teardown(&handle);
2156 
2157 #ifdef  _LP64
2158 	cardbus_err(dip, 8,
2159 	    "Memory 0x%lx bytes, I/O 0x%lx bytes, "
2160 	    "Memgran 0x%x, IOgran 0x%x\n",
2161 	    mem_request->ra_len, io_request->ra_len,
2162 	    entry->memory_gran, entry->io_gran);
2163 #else
2164 	cardbus_err(dip, 8,
2165 	    "Memory 0x%llx bytes, I/O 0x%llx bytes, "
2166 	    "Memgran 0x%x, IOgran 0x%x\n",
2167 	    mem_request->ra_len, io_request->ra_len,
2168 	    entry->memory_gran, entry->io_gran);
2169 #endif
2170 
2171 	return (ret);
2172 }
2173 
2174 /*
2175  * Free resources allocated to a bridge.
2176  * Note that this routine does not call ndi_ra_free() to actually
2177  * free memory/IO/Bus. This is done as a single chunk for the entire
2178  * device tree in cardbus_free_chunk().
2179  */
2180 static int
2181 cardbus_free_bridge_resources(dev_info_t *dip)
2182 {
2183 	cardbus_range_t	*ranges;
2184 	uint_t		*bus;
2185 	int		k;
2186 	int		length;
2187 	int		i;
2188 
2189 	cardbus_err(dip, 6, "cardbus_free_bridge_resources\n");
2190 
2191 	if (ddi_getlongprop(DDI_DEV_T_ANY, dip,
2192 	    DDI_PROP_DONTPASS, "ranges", (caddr_t)&ranges,
2193 	    &length) == DDI_PROP_SUCCESS) {
2194 		for (i = 0; i < length / sizeof (cardbus_range_t); i++) {
2195 			if (ranges[i].size_lo != 0 || ranges[i].size_hi != 0) {
2196 				switch (ranges[i].parent_hi & PCI_REG_ADDR_M) {
2197 				case PCI_ADDR_IO:
2198 					cardbus_err(dip, 6,
2199 					    "Need to Free I/O    "
2200 					    "base/length = [0x%x]/[0x%x]\n",
2201 					    ranges[i].child_lo,
2202 					    ranges[i].size_lo);
2203 					break;
2204 
2205 				case PCI_ADDR_MEM32:
2206 				case PCI_ADDR_MEM64:
2207 					cardbus_err(dip, 6,
2208 					    "Need to Free Memory base/length = "
2209 					    "[0x%x.%x]/[0x%x]\n",
2210 					    ranges[i].child_mid,
2211 					    ranges[i].child_lo,
2212 					    ranges[i].size_lo);
2213 					break;
2214 
2215 				default:
2216 					cardbus_err(dip, 6,
2217 					    "Unknown memory space\n");
2218 					break;
2219 				}
2220 			}
2221 		}
2222 
2223 		kmem_free(ranges, length);
2224 		(void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "ranges");
2225 	} else {
2226 		cardbus_err(dip, 8,
2227 		    "cardbus_free_bridge_resources: Failed"
2228 		    "to read ranges property\n");
2229 	}
2230 
2231 	if (ddi_getlongprop(DDI_DEV_T_ANY, dip,
2232 	    DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus,
2233 	    &k) != DDI_PROP_SUCCESS) {
2234 		cardbus_err(dip, 6, "Failed to read bus-range property\n");
2235 		return (PCICFG_FAILURE);
2236 	}
2237 
2238 	cardbus_err(dip, 6,
2239 	    "Need to free bus [%d] range [%d]\n",
2240 	    bus[0], bus[1] - bus[0] + 1);
2241 	kmem_free(bus, k);
2242 	(void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "available");
2243 	(void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "bus-range");
2244 
2245 	return (PCICFG_SUCCESS);
2246 }
2247 
2248 static int
2249 cardbus_free_device_resources(dev_info_t *dip)
2250 {
2251 	pci_regspec_t *assigned;
2252 
2253 	int length;
2254 	int acount;
2255 	int i;
2256 
2257 	if (ddi_getlongprop(DDI_DEV_T_ANY, dip,
2258 	    DDI_PROP_DONTPASS, "assigned-addresses",
2259 	    (caddr_t)&assigned,
2260 	    &length) != DDI_PROP_SUCCESS) {
2261 		cardbus_err(dip, 1,
2262 		    "Failed to read assigned-addresses property\n");
2263 		return (PCICFG_FAILURE);
2264 	}
2265 
2266 	/*
2267 	 * For each "assigned-addresses" property entry with a length,
2268 	 * call the memory allocation routines to return the
2269 	 * resource.
2270 	 */
2271 	acount = length / sizeof (pci_regspec_t);
2272 	for (i = 0; i < acount; i++) {
2273 
2274 		/*
2275 		 * Free the resource if the size of it is not zero.
2276 		 */
2277 		if ((assigned[i].pci_size_low != 0)||
2278 		    (assigned[i].pci_size_hi != 0)) {
2279 			switch (PCI_REG_ADDR_G(assigned[i].pci_phys_hi)) {
2280 			case PCI_REG_ADDR_G(PCI_ADDR_MEM32):
2281 				cardbus_err(dip, 6,
2282 				    "Need to return 0x%x of 32 bit MEM space"
2283 				    " @ 0x%x from register 0x%x\n",
2284 				    assigned[i].pci_size_low,
2285 				    assigned[i].pci_phys_low,
2286 				    PCI_REG_REG_G(assigned[i].pci_phys_hi));
2287 
2288 				break;
2289 
2290 			case PCI_REG_ADDR_G(PCI_ADDR_MEM64):
2291 				cardbus_err(dip, 6,
2292 				    "Need to return 0x%x of 64 bit MEM space"
2293 				    " @ 0x%x.%x from register 0x%x\n",
2294 				    assigned[i].pci_size_low,
2295 				    assigned[i].pci_phys_mid,
2296 				    assigned[i].pci_phys_low,
2297 				    PCI_REG_REG_G(assigned[i].pci_phys_hi));
2298 
2299 				break;
2300 
2301 			case PCI_REG_ADDR_G(PCI_ADDR_IO):
2302 				cardbus_err(dip, 6,
2303 				    "Need to return 0x%x of IO space @ 0x%x"
2304 				    " from register 0x%x\n",
2305 				    assigned[i].pci_size_low,
2306 				    assigned[i].pci_phys_low,
2307 				    PCI_REG_REG_G(assigned[i].pci_phys_hi));
2308 				break;
2309 
2310 			default:
2311 				cardbus_err(dip, 1, "Unknown register type\n");
2312 				kmem_free(assigned, length);
2313 				return (PCICFG_FAILURE);
2314 			} /* switch */
2315 		}
2316 	}
2317 	kmem_free(assigned, length);
2318 	return (PCICFG_SUCCESS);
2319 }
2320 
2321 static int
2322 cardbus_free_resources(dev_info_t *dip)
2323 {
2324 	uint32_t classcode;
2325 
2326 	classcode = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
2327 				"class-code", -1);
2328 	/*
2329 	 * A different algorithim is used for bridges and leaf devices.
2330 	 */
2331 	if (classcode != -1) {
2332 		classcode = ((uint_t)classcode & 0xffff00) >> 8;
2333 		if (classcode == 0x604 || classcode == 0x607) {
2334 			if (cardbus_free_bridge_resources(dip)
2335 			    != PCICFG_SUCCESS) {
2336 				cardbus_err(dip, 1,
2337 				    "Failed freeing up bridge resources\n");
2338 				return (PCICFG_FAILURE);
2339 			}
2340 			return (PCICFG_SUCCESS);
2341 		}
2342 	}
2343 
2344 	if (cardbus_free_device_resources(dip) != PCICFG_SUCCESS) {
2345 		cardbus_err(dip, 1, "Failed freeing up device resources\n");
2346 		return (PCICFG_FAILURE);
2347 	}
2348 	return (PCICFG_SUCCESS);
2349 }
2350 
2351 static int
2352 cardbus_probe_bridge(cbus_t *cbp, dev_info_t *attpt, uint_t bus,
2353 			uint_t device, uint_t func)
2354 {
2355 	/* Declairations */
2356 	cardbus_bus_range_t	*bus_range;
2357 	int			i, j;
2358 	uint8_t			header_type;
2359 	ddi_acc_handle_t	config_handle;
2360 	ndi_ra_request_t	req;
2361 	uint_t			new_bus;
2362 	uint64_t		blen;
2363 	uint64_t		next_bus;
2364 
2365 	cardbus_err(cbp->cb_dip, 6,
2366 	    "cardbus_probe_bridge bus %d device %d func %d\n",
2367 	    bus, device, func);
2368 
2369 	ndi_devi_enter(cbp->cb_dip);
2370 	if (pci_config_setup(cbp->cb_dip, &config_handle) != DDI_SUCCESS) {
2371 
2372 		cardbus_err(cbp->cb_dip, 1,
2373 		    "cardbus_probe_bridge(): Failed to setup config space\n");
2374 
2375 		ndi_devi_exit(cbp->cb_dip);
2376 		return (PCICFG_FAILURE);
2377 	}
2378 
2379 	header_type = pci_config_get8(config_handle, PCI_CONF_HEADER);
2380 
2381 	/*
2382 	 * As soon as we have access to config space, check device
2383 	 * is a bridge.
2384 	 */
2385 	if ((header_type & PCI_HEADER_TYPE_M) != PCI_HEADER_CARDBUS)
2386 		goto failed;
2387 
2388 	cardbus_err(cbp->cb_dip, 8,
2389 	    "---Vendor ID = [0x%04x]\n",
2390 	    pci_config_get16(config_handle, PCI_CONF_VENID));
2391 	cardbus_err(cbp->cb_dip, 8,
2392 	    "---Device ID = [0x%04x]\n",
2393 	    pci_config_get16(config_handle, PCI_CONF_DEVID));
2394 
2395 	/* say what type of header */
2396 	cardbus_err(cbp->cb_dip, 8,
2397 	    "--%s bridge found root bus [0x%x] device [0x%x] func [0x%x]\n",
2398 	    ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) ?
2399 		"PCI-PCI" : "Cardbus",
2400 	    bus, device, func);
2401 
2402 	if (ddi_getlongprop(DDI_DEV_T_ANY, cbp->cb_dip, 0, "bus-range",
2403 	    (caddr_t)&bus_range, &i) != DDI_PROP_SUCCESS)
2404 		cardbus_err(cbp->cb_dip, 1,
2405 		    "No bus-range property seems to have been set up\n");
2406 	else {
2407 		cardbus_err(cbp->cb_dip, 8,
2408 		    "allowable bus range is %u->%u\n",
2409 		    bus_range->lo, bus_range->hi);
2410 		kmem_free((caddr_t)bus_range, i);
2411 	}
2412 
2413 	/*
2414 	 * Get next bus in sequence and program device.
2415 	 */
2416 	bzero((caddr_t)&req, sizeof (ndi_ra_request_t));
2417 	req.ra_len = 1;
2418 
2419 	if (ndi_ra_alloc(cbp->cb_dip, &req,
2420 	    &next_bus, &blen, NDI_RA_TYPE_PCI_BUSNUM,
2421 	    NDI_RA_PASS) != NDI_SUCCESS) {
2422 		cmn_err(CE_WARN, "Failed to get a bus number\n");
2423 		goto failed;
2424 	}
2425 
2426 	new_bus = next_bus;
2427 	cardbus_err(cbp->cb_dip, 8,
2428 	    "NEW bus found [%u]->[%u]\n", bus, new_bus);
2429 
2430 	(void) cardbus_set_bus_numbers(config_handle, bus, new_bus);
2431 
2432 	/* Enable it all */
2433 	enable_cardbus_bridge(cbp->cb_dip, config_handle);
2434 
2435 	/*
2436 	 * Probe all children devices
2437 	 */
2438 	for (i = 0; i < pcicfg_max_device; i++)
2439 		for (j = 0; j < pcicfg_max_function; j++)
2440 			switch (cardbus_probe_children(cbp, attpt, new_bus, i,
2441 			    j, &header_type)) {
2442 
2443 			case PCICFG_FAILURE:
2444 				cardbus_err(cbp->cb_dip, 1,
2445 				    "Failed to configure bus "
2446 				    "[0x%x] device [0x%x] func [0x%x]\n",
2447 				    new_bus, i, j);
2448 				disable_cardbus_bridge(cbp->cb_dip,
2449 				    config_handle);
2450 				goto failed;
2451 
2452 			case PCICFG_NODEVICE:
2453 				/*
2454 				 * if there's no function 0
2455 				 * there's no point in probing other
2456 				 * functions
2457 				 */
2458 				if (j != 0)
2459 					break;
2460 				/* FALLTHROUGH */
2461 			case PCICFG_NOMULTI:
2462 				j = pcicfg_max_function;
2463 				break;
2464 
2465 			default:
2466 				break;
2467 			}
2468 
2469 	(void) pci_config_teardown(&config_handle);
2470 	(void) i_ndi_config_node(attpt, DS_LINKED, 0);
2471 	ndi_devi_exit(cbp->cb_dip);
2472 
2473 	return (PCICFG_SUCCESS);
2474 
2475 failed:
2476 	(void) pci_config_teardown(&config_handle);
2477 	ndi_devi_exit(cbp->cb_dip);
2478 
2479 	return (PCICFG_FAILURE);
2480 }
2481 
2482 static struct isa_node isa_nodes[] = {
2483 	{"dummy", {NULL, NULL, NULL, NULL, NULL}, "serial", "", 0x4e, 0x2}
2484 };
2485 
2486 static int
2487 cardbus_probe_children(cbus_t *cbp, dev_info_t *parent, uint_t bus,
2488 			uint_t device, uint_t func, uint8_t *header_type)
2489 {
2490 	dev_info_t		*new_child;
2491 	ddi_acc_handle_t	config_handle;
2492 	int			i, j;
2493 	ndi_ra_request_t	req;
2494 	uint64_t		next_bus;
2495 	uint64_t		blen;
2496 	uint32_t		request;
2497 	uint8_t			base_class;
2498 	uint_t			new_bus;
2499 	int			ret;
2500 
2501 	cardbus_err(parent, 6,
2502 	    "cardbus_probe_children bus %d device %d func %d\n",
2503 	    bus, device, func);
2504 
2505 	/*
2506 	 * This node will be put immediately below
2507 	 * "parent". Allocate a blank device node.  It will either
2508 	 * be filled in or freed up based on further probing.
2509 	 */
2510 
2511 	ndi_devi_enter(parent);
2512 
2513 	if (ndi_devi_alloc(parent, DEVI_PSEUDO_NEXNAME,
2514 	    (pnode_t)DEVI_SID_NODEID,
2515 	    &new_child) != NDI_SUCCESS) {
2516 		cardbus_err(parent, 1,
2517 		    "cardbus_probe_children(): Failed to alloc child node\n");
2518 		ndi_devi_exit(parent);
2519 		return (PCICFG_FAILURE);
2520 	}
2521 
2522 	if (cardbus_add_config_reg(new_child, bus,
2523 	    device, func) != DDI_SUCCESS) {
2524 		cardbus_err(parent, 1,
2525 		    "cardbus_probe_children(): Failed to add candidate REG\n");
2526 		goto failedconfig;
2527 	}
2528 
2529 	if ((ret = cardbus_config_setup(new_child, &config_handle))
2530 	    != PCICFG_SUCCESS) {
2531 
2532 		if (ret == PCICFG_NODEVICE) {
2533 			(void) ndi_devi_free(new_child);
2534 			return (ret);
2535 		}
2536 		cardbus_err(parent, 1,
2537 		    "cardbus_probe_children(): Failed to setup config space\n");
2538 
2539 		goto failedconfig;
2540 	}
2541 
2542 	base_class = pci_config_get8(config_handle, PCI_CONF_BASCLASS);
2543 
2544 	if (func == 0) {
2545 		/*
2546 		 * Preserve the header type from function 0.
2547 		 * Additional functions may not preserve the PCI_HEADER_MULTI
2548 		 * bit.
2549 		 */
2550 		*header_type = pci_config_get8(config_handle, PCI_CONF_HEADER);
2551 	} else if (!(*header_type & PCI_HEADER_MULTI) ||
2552 		    ((*header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) ||
2553 		    (base_class == PCI_CLASS_BRIDGE)) {
2554 
2555 		(void) cardbus_config_teardown(&config_handle);
2556 		(void) ndi_devi_free(new_child);
2557 		return (PCICFG_NOMULTI);
2558 	}
2559 
2560 	/*
2561 	 * As soon as we have access to config space,
2562 	 * turn off device. It will get turned on
2563 	 * later (after memory is assigned).
2564 	 * not if it's a cardbus device. It may be OK to leave
2565 	 * it on - try LATER
2566 	 */
2567 	disable_cardbus_device(config_handle);
2568 
2569 	/*
2570 	 * Set 1275 properties common to all devices
2571 	 */
2572 	if (cardbus_set_standard_props(parent, new_child,
2573 	    config_handle) != PCICFG_SUCCESS) {
2574 		cardbus_err(parent, 1, "Failed to set standard properties\n");
2575 		goto failedchild;
2576 	}
2577 
2578 	/*
2579 	 * Child node properties  NOTE: Both for PCI-PCI bridge and child node
2580 	 */
2581 	if (cardbus_set_childnode_props(new_child,
2582 	    config_handle) != PCICFG_SUCCESS) {
2583 		goto failedchild;
2584 	}
2585 
2586 	cardbus_err(parent, 8,
2587 	    "---Vendor ID = [0x%04x]\n",
2588 	    pci_config_get16(config_handle, PCI_CONF_VENID));
2589 	cardbus_err(parent, 8,
2590 	    "---Device ID = [0x%04x]\n",
2591 	    pci_config_get16(config_handle, PCI_CONF_DEVID));
2592 
2593 	if (base_class == PCI_CLASS_BRIDGE) {
2594 		uint8_t	sub_class;
2595 
2596 		sub_class = pci_config_get8(config_handle, PCI_CONF_SUBCLASS);
2597 
2598 		switch (sub_class) {
2599 		case PCI_BRIDGE_PCI:
2600 			if ((*header_type & PCI_HEADER_TYPE_M)
2601 			    == PCI_HEADER_PPB) {
2602 				cardbus_bus_range_t *bus_range;
2603 				int k;
2604 
2605 				/* say what type of header */
2606 				cardbus_err(parent, 8,
2607 				    "-- Found PCI-PCI bridge @ "
2608 				    " bus [0x%x] device [0x%x] func [0x%x]\n",
2609 				    bus, device, func);
2610 
2611 				if (ddi_getlongprop(DDI_DEV_T_ANY,
2612 				    new_child, 0, "bus-range",
2613 				    (caddr_t)&bus_range,
2614 				    &k) != DDI_PROP_SUCCESS)
2615 					cardbus_err(new_child, 1,
2616 					    "No bus-range property"
2617 					    " seems to have been set up\n");
2618 				else {
2619 					cardbus_err(new_child, 8,
2620 					    "allowable bus range is %u->%u\n",
2621 					    bus_range->lo, bus_range->hi);
2622 					kmem_free((caddr_t)bus_range, k);
2623 				}
2624 
2625 				/*
2626 				 * Get next bus in sequence and program device.
2627 				 */
2628 				bzero((caddr_t)&req, sizeof (ndi_ra_request_t));
2629 				req.ra_len = 1;
2630 
2631 				if (ndi_ra_alloc(new_child, &req,
2632 				    &next_bus, &blen,
2633 				    NDI_RA_TYPE_PCI_BUSNUM,
2634 				    NDI_RA_PASS) != NDI_SUCCESS) {
2635 					cmn_err(CE_WARN,
2636 					    "Failed to get a bus number\n");
2637 					goto failedchild;
2638 				}
2639 
2640 				new_bus = next_bus;
2641 
2642 				cardbus_err(new_child, 8,
2643 				    "NEW bus found [%u]->[%u]\n", bus, new_bus);
2644 
2645 				/* Enable it all */
2646 				enable_pci_pci_bridge(new_child, config_handle);
2647 				(void) cardbus_set_bus_numbers(config_handle,
2648 				    bus, new_bus);
2649 
2650 #if defined(CARDBUS_DEBUG)
2651 				if (cardbus_debug >= 9) {
2652 					cardbus_dump_config(config_handle);
2653 				}
2654 #endif
2655 
2656 				/*
2657 				 * Set bus properties
2658 				 */
2659 				if (cardbus_set_busnode_props(new_child)
2660 				    != PCICFG_SUCCESS) {
2661 					cardbus_err(new_child, 1,
2662 					    "Failed to set busnode props\n");
2663 					disable_pci_pci_bridge(new_child,
2664 					    config_handle);
2665 					goto failedchild;
2666 				}
2667 
2668 				/*
2669 				 * Probe all children devices
2670 				 */
2671 				for (i = 0; i < pcicfg_max_device; i++)
2672 					for (j = 0; j < pcicfg_max_function;
2673 					    j++)
2674 						switch (cardbus_probe_children(
2675 						    cbp,
2676 						    new_child,
2677 						    new_bus, i,
2678 						    j, header_type)) {
2679 						case PCICFG_FAILURE:
2680 							cardbus_err(parent, 1,
2681 							    "Failed to "
2682 							    "configure "
2683 							    "bus [0x%x] "
2684 							    "device [0x%x] "
2685 							    "func [0x%x]\n",
2686 							    new_bus, i, j);
2687 							disable_pci_pci_bridge(
2688 								new_child,
2689 								config_handle);
2690 							goto failedchild;
2691 
2692 						case PCICFG_NODEVICE:
2693 							/*
2694 							 * if there's no
2695 							 * function 0
2696 							 * there's no point in
2697 							 * probing other
2698 							 * functions
2699 							 */
2700 							if (j != 0)
2701 								break;
2702 							/* FALLTHROUGH */
2703 						case PCICFG_NOMULTI:
2704 							j = pcicfg_max_function;
2705 							break;
2706 
2707 						default:
2708 							break;
2709 						}
2710 			}
2711 			break;
2712 
2713 		case PCI_BRIDGE_CARDBUS:
2714 			cardbus_err(parent, 8,
2715 			    "--Found Cardbus bridge @ "
2716 			    "bus [0x%x] device [0x%x] func [0x%x]\n",
2717 			    bus, device, func);
2718 			pci_config_put32(config_handle,
2719 			    PCI_CONF_BASE0, 0xffffffff);
2720 
2721 			request = pci_config_get32(config_handle,
2722 			    PCI_CONF_BASE0);
2723 
2724 			/*
2725 			 * If its a zero length, don't do
2726 			 * any programming.
2727 			 */
2728 			if (request != 0) {
2729 				if (request == (uint32_t)0xffffffff) {
2730 					cmn_err(CE_WARN,
2731 					    "cardbus_probe_children: "
2732 					    "can't access device");
2733 					goto failedchild;
2734 				}
2735 				/*
2736 				 * Add to the "reg" property
2737 				 */
2738 				if (cardbus_update_reg_prop(new_child,
2739 				    request,
2740 				    PCI_CONF_BASE0) != PCICFG_SUCCESS) {
2741 					goto failedchild;
2742 				}
2743 				cardbus_err(parent, 8,
2744 				    "BASE register [0x%x] asks for "
2745 				    "[0x%x]=[0x%x](32)\n",
2746 				    PCI_CONF_BASE0, request,
2747 				    (~(PCI_BASE_M_ADDR_M & request))+1);
2748 			}
2749 			break;
2750 
2751 		case PCI_BRIDGE_ISA:
2752 			cardbus_err(parent, 8,
2753 			    "--Found ISA bridge @ "
2754 			    "bus [0x%x] device [0x%x] func [0x%x]\n",
2755 			    bus, device, func);
2756 			enable_pci_isa_bridge(new_child, config_handle);
2757 
2758 #if defined(CARDBUS_DEBUG)
2759 			if (cardbus_debug >= 4) {
2760 				cardbus_dump_common_config(config_handle);
2761 				cardbus_err(NULL, 1,
2762 				    " DDMA SlvCh0 = [0x%04x]        "
2763 				    "DDMA SlvCh1 = [0x%04x]\n",
2764 				    pci_config_get16(config_handle, 0x40),
2765 				    pci_config_get16(config_handle, 0x42));
2766 				cardbus_err(NULL, 1,
2767 				    " DDMA SlvCh2 = [0x%04x]        "
2768 				    "DDMA SlvCh3 = [0x%04x]\n",
2769 				    pci_config_get16(config_handle, 0x44),
2770 				    pci_config_get16(config_handle, 0x46));
2771 				cardbus_err(NULL, 1,
2772 				    " DDMA SlvCh5 = [0x%04x]        "
2773 				    "DDMA SlvCh6 = [0x%04x]\n",
2774 				    pci_config_get16(config_handle, 0x4a),
2775 				    pci_config_get16(config_handle, 0x4c));
2776 				cardbus_err(NULL, 1,
2777 				    " DDMA SlvCh7 = [0x%04x]        "
2778 				    "Misc Cntrl  = [0x%02x]\n",
2779 				    pci_config_get16(config_handle, 0x4e),
2780 				    pci_config_get8(config_handle, 0x57));
2781 				cardbus_err(NULL, 1,
2782 				    " DMA Cntl    = [0x%02x]          "
2783 				    "DMA TyF Tim = [0x%02x]\n",
2784 				    pci_config_get8(config_handle, 0x48),
2785 				    pci_config_get8(config_handle, 0x49));
2786 				cardbus_err(NULL, 1,
2787 				    " TimCntrl    = [0x%02x]          "
2788 				    "MTOP        = [0x%02x]\n",
2789 				    pci_config_get8(config_handle, 0x50),
2790 				    pci_config_get8(config_handle, 0x51));
2791 				cardbus_err(NULL, 1,
2792 				    " MDMA Access = [0x%02x]          "
2793 				    "ROMCS       = [0x%02x]\n",
2794 				    pci_config_get8(config_handle, 0x52),
2795 				    pci_config_get8(config_handle, 0x53));
2796 				cardbus_err(NULL, 1,
2797 				    " Dscrd Tmr   = [0x%02x]          "
2798 				    "Retry Tmr   = [0x%02x]\n",
2799 				    pci_config_get8(config_handle, 0x55),
2800 				    pci_config_get8(config_handle, 0x54));
2801 				cardbus_err(NULL, 1,
2802 				    " I/O Spc 0   = [0x%08x]    "
2803 				    "I/O Spc 1   = [0x%08x]\n",
2804 				    pci_config_get32(config_handle, 0x58),
2805 				    pci_config_get32(config_handle, 0x5c));
2806 				cardbus_err(NULL, 1,
2807 				    " I/O Spc 2   = [0x%08x]    "
2808 				    "I/O Spc 3   = [0x%08x]\n",
2809 				    pci_config_get32(config_handle, 0x60),
2810 				    pci_config_get32(config_handle, 0x64));
2811 				cardbus_err(NULL, 1,
2812 				    " I/O Spc 4   = [0x%08x]    "
2813 				    "I/O Spc 5   = [0x%08x]\n",
2814 				    pci_config_get32(config_handle, 0x68),
2815 				    pci_config_get32(config_handle, 0x6c));
2816 				cardbus_err(NULL, 1,
2817 				    " Mem Spc 0   = [0x%08x]    "
2818 				    "Mem Spc 1   = [0x%08x]\n",
2819 				    pci_config_get32(config_handle, 0x70),
2820 				    pci_config_get32(config_handle, 0x74));
2821 				cardbus_err(NULL, 1,
2822 				    " Mem Spc 2   = [0x%08x]    "
2823 				    "Mem Spc 3   = [0x%08x]\n",
2824 				    pci_config_get32(config_handle, 0x78),
2825 				    pci_config_get32(config_handle, 0x7c));
2826 			}
2827 #endif
2828 			/*
2829 			 * Set bus properties
2830 			 */
2831 			if (cardbus_set_busnode_isaprops(new_child)
2832 			    != PCICFG_SUCCESS) {
2833 				cardbus_err(new_child, 1,
2834 				    "Failed to set busnode props\n");
2835 				disable_cardbus_device(config_handle);
2836 				goto failedchild;
2837 			}
2838 
2839 			/*
2840 			 * Add to the "reg" property.
2841 			 * Simply grab 1K of I/O space.
2842 			 */
2843 			if (cardbus_update_reg_prop(new_child,
2844 			    0xfffffc00 | PCI_BASE_SPACE_IO,
2845 			    PCI_CONF_BASE0) != PCICFG_SUCCESS) {
2846 				goto failedchild;
2847 			}
2848 
2849 			/*
2850 			 * Probe all potential children devices.
2851 			 */
2852 			for (i = 0;
2853 			    i < sizeof (isa_nodes) / sizeof (isa_nodes[0]);
2854 			    i++)
2855 				switch (cardbus_add_isa_node(cbp, new_child,
2856 				    &isa_nodes[i])) {
2857 				case PCICFG_FAILURE:
2858 					cardbus_err(parent, 1,
2859 					    "Failed to configure isa bus\n");
2860 					disable_cardbus_device(config_handle);
2861 					goto failedchild;
2862 
2863 				case PCICFG_NODEVICE:
2864 					continue;
2865 				}
2866 
2867 			break;
2868 
2869 		case PCI_BRIDGE_OTHER:
2870 		default:
2871 			cardbus_err(parent, 8,
2872 			    "--Found unknown bridge, subclass 0x%x @ "
2873 			    "bus [0x%x] device [0x%x] func [0x%x]\n",
2874 			    sub_class, bus, device, func);
2875 			goto leaf_node;
2876 		}
2877 	} else {
2878 		cardbus_err(parent, 8,
2879 		    "--Leaf device found "
2880 		    "bus [0x%x] device [0x%x] func [0x%x]\n",
2881 		    bus, device, func);
2882 		/*
2883 		 * Ethernet devices.
2884 		 */
2885 		if (strcmp(ddi_binding_name(new_child), "ethernet") == 0) {
2886 			extern int localetheraddr(struct ether_addr *,
2887 			    struct ether_addr *);
2888 			uchar_t mac[6];
2889 
2890 			cardbus_force_stringprop(new_child,
2891 			    "device_type", "network");
2892 
2893 			if (localetheraddr(NULL, (struct ether_addr *)mac)) {
2894 				(void) ddi_prop_create(DDI_DEV_T_NONE,
2895 				    new_child,
2896 				    DDI_PROP_CANSLEEP, "local-mac-address",
2897 				    (caddr_t)mac, 6);
2898 			}
2899 		}
2900 leaf_node:
2901 		if (cbp->cb_dsp) {
2902 			struct cb_deviceset_props *cdsp = cbp->cb_dsp;
2903 			uint16_t venid = pci_config_get16(config_handle,
2904 						PCI_CONF_VENID);
2905 			uint16_t devid = pci_config_get16(config_handle,
2906 						PCI_CONF_DEVID);
2907 			ddi_prop_t *propp;
2908 
2909 			for (cdsp = cbp->cb_dsp; cdsp; cdsp = cdsp->next) {
2910 				if (cdsp->binding_name &&
2911 				    strcmp(ddi_binding_name(new_child),
2912 				    cdsp->binding_name))
2913 					continue;
2914 				if (cdsp->venid && (cdsp->venid != venid))
2915 					continue;
2916 				if (cdsp->devid && (cdsp->devid != devid))
2917 					continue;
2918 				if (cdsp->nodename) {
2919 					if (ndi_devi_set_nodename(new_child,
2920 					    cdsp->nodename,
2921 					    0) != NDI_SUCCESS)
2922 						cardbus_err(new_child, 1,
2923 						    "Failed to set nodename\n");
2924 				}
2925 				for (propp = cdsp->prop_list; propp;
2926 				    propp = propp->prop_next) {
2927 					switch (propp->prop_flags) {
2928 					case DDI_PROP_TYPE_INT:
2929 						cardbus_force_intprop(
2930 						    new_child,
2931 						    propp->prop_name,
2932 						    (int *)propp->prop_val,
2933 						    propp->prop_len);
2934 						break;
2935 					case DDI_PROP_TYPE_STRING:
2936 						cardbus_force_stringprop(
2937 						    new_child,
2938 						    propp->prop_name,
2939 						    (char *)propp->prop_val);
2940 						break;
2941 					case DDI_PROP_TYPE_ANY:
2942 						cardbus_force_boolprop(
2943 						    new_child,
2944 						    propp->prop_name);
2945 						break;
2946 					}
2947 				}
2948 			}
2949 		}
2950 
2951 #if defined(CARDBUS_DEBUG)
2952 		if (cardbus_debug >= 9) {
2953 			cardbus_dump_config(config_handle);
2954 		}
2955 #endif
2956 
2957 		i = PCI_CONF_BASE0;
2958 
2959 		while (i <= PCI_CONF_BASE5) {
2960 			pci_config_put32(config_handle, i, 0xffffffff);
2961 
2962 			request = pci_config_get32(config_handle, i);
2963 
2964 			/*
2965 			 * If its a zero length, don't do
2966 			 * any programming.
2967 			 */
2968 			if (request != 0) {
2969 				if (request == (uint32_t)0xffffffff) {
2970 					cmn_err(CE_WARN,
2971 					    "cardbus_probe_children: "
2972 					    "can't access device");
2973 					goto failedchild;
2974 				}
2975 				/*
2976 				 * Add to the "reg" property
2977 				 */
2978 				if (cardbus_update_reg_prop(new_child,
2979 				    request, i) != PCICFG_SUCCESS) {
2980 					goto failedchild;
2981 				}
2982 			} else {
2983 				cardbus_err(parent, 8, "All memory found\n");
2984 				break;
2985 			}
2986 
2987 			/*
2988 			 * Increment by eight if it is 64 bit address space
2989 			 * only if memory space
2990 			 */
2991 			if (((PCI_BASE_TYPE_M & request)
2992 				== PCI_BASE_TYPE_ALL) &&
2993 			    ((PCI_BASE_SPACE_M & request)
2994 				== PCI_BASE_SPACE_MEM)) {
2995 				cardbus_err(parent, 8,
2996 				    "BASE register [0x%x] asks for "
2997 				    "[0x%x]=[0x%x] (64)\n",
2998 				    i, request,
2999 				    (~(PCI_BASE_M_ADDR_M & request))+1);
3000 				i += 8;
3001 			} else {
3002 				cardbus_err(parent, 8,
3003 				    "BASE register [0x%x] asks for "
3004 				    "[0x%x]=[0x%x](32)\n",
3005 				    i, request,
3006 				    (~(PCI_BASE_M_ADDR_M & request))+1);
3007 				i += 4;
3008 			}
3009 		}
3010 
3011 		/*
3012 		 * Get the ROM size and create register for it
3013 		 */
3014 		pci_config_put32(config_handle, PCI_CONF_ROM, 0xffffffff);
3015 
3016 		request = pci_config_get32(config_handle, PCI_CONF_ROM);
3017 		/*
3018 		 * If its a zero length, don't do
3019 		 * any programming.
3020 		 */
3021 
3022 		if (request != 0) {
3023 			cardbus_err(parent, 9,
3024 			    "BASE register [0x%x] asks for "
3025 			    "[0x%x]=[0x%x] (ROM)\n",
3026 			    PCI_CONF_ROM, request,
3027 			    (~(PCI_BASE_ROM_ADDR_M & request))+1);
3028 			/*
3029 			 * Add to the "reg" property
3030 			 */
3031 			if (cardbus_update_reg_prop(new_child,
3032 			    request,
3033 			    PCI_CONF_ROM) != PCICFG_SUCCESS) {
3034 				goto failedchild;
3035 			}
3036 		}
3037 	}
3038 
3039 	(void) cardbus_config_teardown(&config_handle);
3040 
3041 	/*
3042 	 * Attach the child to its parent
3043 	 */
3044 	(void) i_ndi_config_node(new_child, DS_LINKED, 0);
3045 	ndi_devi_exit(parent);
3046 
3047 	return (PCICFG_SUCCESS);
3048 failedchild:
3049 	/*
3050 	 * check if it should be taken offline (if online)
3051 	 */
3052 	(void) cardbus_config_teardown(&config_handle);
3053 
3054 failedconfig:
3055 
3056 	(void) ndi_devi_free(new_child);
3057 	ndi_devi_exit(parent);
3058 
3059 	return (PCICFG_FAILURE);
3060 }
3061 
3062 static int
3063 cardbus_add_config_reg(dev_info_t *dip,
3064 		uint_t bus, uint_t device, uint_t func)
3065 {
3066 	int reg[10] = { PCI_ADDR_CONFIG, 0, 0, 0, 0};
3067 
3068 	reg[0] = PCICFG_MAKE_REG_HIGH(bus, device, func, 0);
3069 
3070 	return (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
3071 	    "reg", reg, 5));
3072 }
3073 
3074 static int
3075 cardbus_add_isa_node(cbus_t *cbp, dev_info_t *parent, struct isa_node *node)
3076 {
3077 	dev_info_t		*new_child;
3078 	int			ret;
3079 	uint32_t		reg[3];
3080 
3081 	_NOTE(ARGUNUSED(cbp))
3082 
3083 	cardbus_err(parent, 6, "cardbus_add_isa_node\n");
3084 
3085 	/*
3086 	 * This node will be put immediately below
3087 	 * "parent". Allocate a blank device node.
3088 	 */
3089 	if (ndi_devi_alloc(parent, DEVI_PSEUDO_NEXNAME,
3090 	    (pnode_t)DEVI_SID_NODEID,
3091 	    &new_child) != NDI_SUCCESS) {
3092 		cardbus_err(parent, 1,
3093 		    "cardbus_add_isa_child(): Failed to alloc child node\n");
3094 		return (PCICFG_FAILURE);
3095 	}
3096 
3097 	/*
3098 	 * Set properties common to ISA devices
3099 	 */
3100 	if (cardbus_set_isa_props(parent, new_child, node->name,
3101 	    node->compatible) != PCICFG_SUCCESS) {
3102 		cardbus_err(parent, 1, "Failed to set ISA properties\n");
3103 		goto failed;
3104 	}
3105 
3106 	cardbus_err(new_child, 8, "--Leaf ISA device\n");
3107 
3108 	/*
3109 	 * Add the "reg" property.
3110 	 */
3111 	reg[0] = 0;
3112 	reg[1] = node->reg;
3113 	reg[2] = node->span;
3114 
3115 	ret = ndi_prop_update_int_array(DDI_DEV_T_NONE, new_child,
3116 	    "basereg", (int *)reg, 3);
3117 	if (ret != DDI_SUCCESS)
3118 		goto failed;
3119 
3120 	(void) i_ndi_config_node(new_child, DS_LINKED, 0);
3121 
3122 	return (PCICFG_SUCCESS);
3123 
3124 failed:
3125 	(void) ndi_devi_free(new_child);
3126 
3127 	return (PCICFG_FAILURE);
3128 }
3129 
3130 static int
3131 cardbus_config_setup(dev_info_t *dip, ddi_acc_handle_t *handle)
3132 {
3133 	caddr_t		cfgaddr;
3134 	ddi_device_acc_attr_t	attr;
3135 	dev_info_t	*anode;
3136 	int	status;
3137 	int	rlen;
3138 	pci_regspec_t	*reg;
3139 	int		ret;
3140 #ifdef sparc
3141 	int16_t		val;
3142 #endif
3143 
3144 	cardbus_err(dip, 10,
3145 	    "cardbus_config_setup(dip=0x%p)\n", (void *) dip);
3146 
3147 	/*
3148 	 * Get the pci register spec from the node
3149 	 */
3150 	status = ddi_getlongprop(DDI_DEV_T_NONE,
3151 	    dip, DDI_PROP_DONTPASS, "reg",
3152 	    (caddr_t)&reg, &rlen);
3153 
3154 	cardbus_err(dip, 10,
3155 	    "cardbus_config_setup, reg = 0x%p\n", (void *) reg);
3156 
3157 	switch (status) {
3158 	case DDI_PROP_SUCCESS:
3159 		break;
3160 	case DDI_PROP_NO_MEMORY:
3161 		cardbus_err(dip, 1, "reg present, but unable to get memory\n");
3162 		return (PCICFG_FAILURE);
3163 	default:
3164 		cardbus_err(dip, 1, "no reg property\n");
3165 		return (PCICFG_FAILURE);
3166 	}
3167 
3168 	anode = dip;
3169 
3170 	/*
3171 	 * Find the attachment point node
3172 	 */
3173 	while ((anode != NULL) && (strcmp(ddi_binding_name(anode),
3174 	    "hp_attachment") != 0)) {
3175 		anode = ddi_get_parent(anode);
3176 	}
3177 
3178 	if (anode == NULL) {
3179 		cardbus_err(dip, 1, "Tree not in PROBE state\n");
3180 		kmem_free((caddr_t)reg, rlen);
3181 		return (PCICFG_FAILURE);
3182 	}
3183 
3184 	if ((ret = ndi_prop_update_int_array(DDI_DEV_T_NONE, anode,
3185 	    "reg", (int *)reg, 5)) != 0) {
3186 		cardbus_err(dip, 1,
3187 		    "Failed to update reg property, error code %d\n", ret);
3188 		kmem_free((caddr_t)reg, rlen);
3189 		return (PCICFG_FAILURE);
3190 	}
3191 
3192 	attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
3193 	attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
3194 	attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
3195 
3196 	if (ddi_regs_map_setup(anode, 0, &cfgaddr,
3197 	    0, /* PCI_CONF_HDR_SIZE */
3198 	    0,
3199 	    &attr, handle) != DDI_SUCCESS) {
3200 		cardbus_err(dip, 1,
3201 		    "Failed to setup registers for [0x%x][0x%x][0x%x]\n",
3202 		    PCI_REG_BUS_G(reg->pci_phys_hi),
3203 		    PCI_REG_DEV_G(reg->pci_phys_hi),
3204 		    PCI_REG_FUNC_G(reg->pci_phys_hi));
3205 		kmem_free((caddr_t)reg, rlen);
3206 		return (PCICFG_FAILURE);
3207 	}
3208 
3209 	cardbus_err(dip, 9,
3210 	    "PROBING =>->->->->->-> [0x%x][0x%x][0x%x] 0x%x 0x%p\n",
3211 	    PCI_REG_BUS_G(reg->pci_phys_hi),
3212 	    PCI_REG_DEV_G(reg->pci_phys_hi),
3213 	    PCI_REG_FUNC_G(reg->pci_phys_hi),
3214 	    reg->pci_phys_hi, (void *) cfgaddr);
3215 
3216 	/*
3217 	 * must do peek16 otherwise the system crashes when probing
3218 	 * a non zero function on a non-multi-function card.
3219 	 */
3220 #ifdef sparc
3221 	if (ddi_peek16(anode, (int16_t *)cfgaddr, &val) != DDI_SUCCESS) {
3222 		cardbus_err(dip, 8,
3223 		    "cardbus_config_setup peek failed\n");
3224 		ret = PCICFG_NODEVICE;
3225 	} else if (ddi_get16(*handle, (uint16_t *)cfgaddr) == 0xffff) {
3226 		cardbus_err(dip, 8,
3227 		    "cardbus_config_setup PCICFG_NODEVICE\n");
3228 		ret = PCICFG_NODEVICE;
3229 #elif defined(__x86)
3230 	if (ddi_get16(*handle, (uint16_t *)cfgaddr) == 0xffff) {
3231 		cardbus_err(dip, 8,
3232 		    "cardbus_config_setup PCICFG_NODEVICE\n");
3233 		ret = PCICFG_NODEVICE;
3234 #endif
3235 	} else {
3236 		cardbus_err(dip, 1,
3237 		    "cardbus_config_setup found device at:[0x%x][0x%x][0x%x]\n",
3238 		    PCI_REG_BUS_G(reg->pci_phys_hi),
3239 		    PCI_REG_DEV_G(reg->pci_phys_hi),
3240 		    PCI_REG_FUNC_G(reg->pci_phys_hi));
3241 
3242 		ret = PCICFG_SUCCESS;
3243 	}
3244 
3245 	kmem_free((caddr_t)reg, rlen);
3246 	if (ret != PCICFG_SUCCESS) {
3247 		cardbus_config_teardown(handle);
3248 	}
3249 
3250 	cardbus_err(dip, 7,
3251 	    "cardbus_config_setup returning %d\n", ret);
3252 
3253 	return (ret);
3254 }
3255 
3256 static void
3257 cardbus_config_teardown(ddi_acc_handle_t *handle)
3258 {
3259 	(void) ddi_regs_map_free(handle);
3260 }
3261 
3262 static void
3263 cardbus_reparent_children(dev_info_t *dip, dev_info_t *parent)
3264 {
3265 	dev_info_t *child;
3266 
3267 	while (child = ddi_get_child(dip)) {
3268 		ASSERT(i_ddi_node_state(child) <= DS_LINKED);
3269 		/*
3270 		 * Unlink node from tree before reparenting
3271 		 */
3272 		ndi_devi_enter(dip);
3273 		(void) i_ndi_unconfig_node(child, DS_PROTO, 0);
3274 		ndi_devi_exit(dip);
3275 		DEVI(child)->devi_parent = DEVI(parent);
3276 		DEVI(child)->devi_bus_ctl = DEVI(parent);
3277 		ndi_devi_enter(parent);
3278 		(void) i_ndi_config_node(child, DS_LINKED, 0);
3279 		ndi_devi_exit(parent);
3280 	}
3281 }
3282 
3283 static int
3284 cardbus_update_assigned_prop(dev_info_t *dip, pci_regspec_t *newone)
3285 {
3286 	int		alen;
3287 	pci_regspec_t	*assigned;
3288 	caddr_t		newreg;
3289 	uint_t		status;
3290 
3291 	status = ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS,
3292 	    "assigned-addresses", (caddr_t)&assigned, &alen);
3293 	switch (status) {
3294 	case DDI_PROP_SUCCESS:
3295 		cardbus_err(dip, 5,
3296 		    "cardbus_update_assigned_prop: found prop len %d\n",
3297 		    alen);
3298 		/*
3299 		 * Allocate memory for the existing
3300 		 * assigned-addresses(s) plus one and then
3301 		 * build it.
3302 		 */
3303 		newreg = kmem_zalloc(alen+sizeof (*newone), KM_SLEEP);
3304 
3305 		bcopy(assigned, newreg, alen);
3306 		bcopy(newone, newreg + alen, sizeof (*newone));
3307 		break;
3308 
3309 	case DDI_PROP_NO_MEMORY:
3310 		cardbus_err(dip, 1,
3311 		    "no memory for assigned-addresses property\n");
3312 		return (PCICFG_FAILURE);
3313 
3314 	default:
3315 		cardbus_err(dip, 5,
3316 		    "cardbus_update_assigned_prop: creating prop\n");
3317 		alen = 0;
3318 		newreg = (caddr_t)newone;
3319 		break;
3320 	}
3321 
3322 	/*
3323 	 * Write out the new "assigned-addresses" spec
3324 	 */
3325 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
3326 	    "assigned-addresses", (int *)newreg,
3327 	    (alen + sizeof (*newone))/sizeof (int));
3328 
3329 	if (status == DDI_PROP_SUCCESS)
3330 		kmem_free((caddr_t)newreg, alen+sizeof (*newone));
3331 
3332 	if (alen)
3333 		kmem_free(assigned, alen);
3334 
3335 	return (PCICFG_SUCCESS);
3336 }
3337 
3338 static int
3339 cardbus_update_available_prop(dev_info_t *dip, uint32_t hi_type,
3340 				uint64_t base, uint64_t size)
3341 {
3342 	int		alen, rlen;
3343 	pci_regspec_t	*available, *reg;
3344 	pci_regspec_t	addition;
3345 	caddr_t		newreg;
3346 	uint_t		status;
3347 
3348 	cardbus_err(dip, 6, "cardbus_update_available_prop\n");
3349 
3350 	status = ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS,
3351 	    "reg", (caddr_t)&reg, &rlen);
3352 
3353 	switch (status) {
3354 	case DDI_PROP_SUCCESS:
3355 		break;
3356 	case DDI_PROP_NO_MEMORY:
3357 		cardbus_err(dip, 1, "reg present, but unable to get memory\n");
3358 		return (PCICFG_FAILURE);
3359 	default:
3360 		cardbus_err(dip, 1, "no reg property\n");
3361 		return (PCICFG_FAILURE);
3362 	}
3363 
3364 	status = ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS,
3365 	    "available", (caddr_t)&available, &alen);
3366 	switch (status) {
3367 	case DDI_PROP_SUCCESS:
3368 		break;
3369 	case DDI_PROP_NO_MEMORY:
3370 		cardbus_err(dip, 1, "no memory for available property\n");
3371 		kmem_free((caddr_t)reg, rlen);
3372 		return (PCICFG_FAILURE);
3373 	default:
3374 		alen = 0;
3375 	}
3376 
3377 	/*
3378 	 * Allocate memory for the existing
3379 	 * available(s) plus one and then
3380 	 * build it.
3381 	 */
3382 	newreg = kmem_zalloc(alen + sizeof (pci_regspec_t), KM_SLEEP);
3383 
3384 	/*
3385 	 * Build the regspec, then add it to the existing one(s)
3386 	 */
3387 	addition.pci_phys_hi = hi_type |
3388 	    PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi),
3389 	    PCI_REG_DEV_G(reg->pci_phys_hi),
3390 	    PCI_REG_FUNC_G(reg->pci_phys_hi), 0);
3391 
3392 	addition.pci_phys_mid = (uint32_t)((base>>32) & 0xffffffff);
3393 	addition.pci_phys_low = (uint32_t)(base & 0xffffffff);
3394 	addition.pci_size_hi = (uint32_t)((size>>32) & 0xffffffff);
3395 	addition.pci_size_low = (uint32_t)(size & 0xffffffff);
3396 
3397 #ifdef DEBUG
3398 	cardbus_dump_reg(dip, &addition, 1);
3399 #endif
3400 
3401 	if (alen)
3402 		bcopy(available, newreg, alen);
3403 	bcopy(&addition, newreg + alen, sizeof (pci_regspec_t));
3404 
3405 	/*
3406 	 * Write out the new "available" spec
3407 	 */
3408 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
3409 	    "available", (int *)newreg,
3410 	    (alen + sizeof (pci_regspec_t))/sizeof (int));
3411 
3412 	if (alen)
3413 		kmem_free((caddr_t)available, alen);
3414 	kmem_free((caddr_t)reg, rlen);
3415 	kmem_free((caddr_t)newreg, alen + sizeof (pci_regspec_t));
3416 
3417 	return (PCICFG_SUCCESS);
3418 }
3419 
3420 static int
3421 cardbus_update_ranges_prop(dev_info_t *dip, cardbus_range_t *addition)
3422 {
3423 	int		rlen;
3424 	cardbus_range_t	*ranges;
3425 	caddr_t		newreg;
3426 	uint_t		status;
3427 #if defined(CARDBUS_DEBUG)
3428 	int	i, nrange;
3429 	const cardbus_range_t	*nr;
3430 #endif
3431 
3432 	cardbus_err(dip, 6, "cardbus_update_ranges_prop\n");
3433 
3434 	status = ddi_getlongprop(DDI_DEV_T_NONE,
3435 	    dip, DDI_PROP_DONTPASS, "ranges",
3436 	    (caddr_t)&ranges, &rlen);
3437 
3438 	switch (status) {
3439 	case DDI_PROP_SUCCESS:
3440 		break;
3441 	case DDI_PROP_NO_MEMORY:
3442 		cardbus_err(dip, 1,
3443 		    "ranges present, but unable to get memory\n");
3444 		return (PCICFG_FAILURE);
3445 	default:
3446 		cardbus_err(dip, 8, "no ranges property - creating one\n");
3447 		if (ndi_prop_update_int_array(DDI_DEV_T_NONE,
3448 		    dip, "ranges", (int *)addition,
3449 		    sizeof (cardbus_range_t)/sizeof (int))
3450 		    != DDI_SUCCESS) {
3451 			cardbus_err(dip, 1, "Did'nt create ranges property\n");
3452 			return (PCICFG_FAILURE);
3453 		}
3454 		return (PCICFG_SUCCESS);
3455 	}
3456 
3457 	/*
3458 	 * Allocate memory for the existing reg(s) plus one and then
3459 	 * build it.
3460 	 */
3461 	newreg = kmem_zalloc(rlen+sizeof (cardbus_range_t), KM_SLEEP);
3462 
3463 	bcopy(ranges, newreg, rlen);
3464 	bcopy(addition, newreg + rlen, sizeof (cardbus_range_t));
3465 
3466 	/*
3467 	 * Write out the new "ranges" property
3468 	 */
3469 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
3470 	    dip, "ranges", (int *)newreg,
3471 	    (rlen + sizeof (cardbus_range_t))/sizeof (int));
3472 
3473 #if defined(CARDBUS_DEBUG)
3474 	cardbus_err(dip, 8, "cardbus_update_ranges_prop ranges property:\n");
3475 
3476 	nrange = rlen / sizeof (cardbus_range_t);
3477 	nr = (cardbus_range_t *)newreg;
3478 	for (i = 0; i <= nrange; i++) {
3479 		/* nrange is one higher for new entry */
3480 		cardbus_err(dip, 9,
3481 		    "\trange parent addr 0x%x.0x%x.0x%x "
3482 		    "child addr 0x%x.0x%x.0x%x size 0x%x.0x%x\n",
3483 		    nr->parent_hi,
3484 		    nr->parent_mid, nr->parent_lo,
3485 		    nr->child_hi,
3486 		    nr->child_mid, nr->child_lo,
3487 		    nr->size_hi, nr->size_lo);
3488 		nr++;
3489 	}
3490 #endif
3491 
3492 	kmem_free((caddr_t)newreg, rlen+sizeof (cardbus_range_t));
3493 	kmem_free((caddr_t)ranges, rlen);
3494 
3495 	return (PCICFG_SUCCESS);
3496 }
3497 
3498 static int
3499 cardbus_update_reg_prop(dev_info_t *dip, uint32_t regvalue, uint_t reg_offset)
3500 {
3501 	int	rlen;
3502 	pci_regspec_t	*reg;
3503 	caddr_t		newreg;
3504 	uint32_t	hiword;
3505 	pci_regspec_t	addition;
3506 	uint32_t	size;
3507 	uint_t		status;
3508 
3509 	status = ddi_getlongprop(DDI_DEV_T_NONE,
3510 	    dip, DDI_PROP_DONTPASS, "reg", (caddr_t)&reg, &rlen);
3511 
3512 	switch (status) {
3513 	case DDI_PROP_SUCCESS:
3514 		break;
3515 	case DDI_PROP_NO_MEMORY:
3516 		cardbus_err(dip, 1, "reg present, but unable to get memory\n");
3517 		return (PCICFG_FAILURE);
3518 	default:
3519 		cardbus_err(dip, 1, "no reg property\n");
3520 		return (PCICFG_FAILURE);
3521 	}
3522 
3523 	/*
3524 	 * Allocate memory for the existing reg(s) plus one and then
3525 	 * build it.
3526 	 */
3527 	newreg = kmem_zalloc(rlen+sizeof (pci_regspec_t), KM_SLEEP);
3528 
3529 	/*
3530 	 * Build the regspec, then add it to the existing one(s)
3531 	 */
3532 	hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi),
3533 			PCI_REG_DEV_G(reg->pci_phys_hi),
3534 			PCI_REG_FUNC_G(reg->pci_phys_hi),
3535 			reg_offset);
3536 
3537 	if (reg_offset == PCI_CONF_ROM) {
3538 		size = (~(PCI_BASE_ROM_ADDR_M & regvalue))+1;
3539 		hiword |= PCI_ADDR_MEM32;
3540 	} else {
3541 		size = (~(PCI_BASE_M_ADDR_M & regvalue))+1;
3542 
3543 		if ((PCI_BASE_SPACE_M & regvalue) == PCI_BASE_SPACE_MEM) {
3544 			if ((PCI_BASE_TYPE_M & regvalue) == PCI_BASE_TYPE_MEM) {
3545 				hiword |= PCI_ADDR_MEM32;
3546 			} else if ((PCI_BASE_TYPE_M & regvalue)
3547 				    == PCI_BASE_TYPE_ALL) {
3548 				/*
3549 				 * This is a 64 bit PCI memory space.
3550 				 * It needs to be allocated as 32 bit
3551 				 * for bus map purposes.
3552 				 */
3553 				hiword |= PCI_ADDR_MEM32;
3554 			}
3555 		} else {
3556 			hiword |= PCI_ADDR_IO;
3557 		}
3558 	}
3559 
3560 	addition.pci_phys_hi = hiword;
3561 	addition.pci_phys_mid = 0;
3562 	addition.pci_phys_low = 0;
3563 	addition.pci_size_hi = 0;
3564 	addition.pci_size_low = size;
3565 
3566 	cardbus_err(dip, 8,
3567 	    "cardbus_update_reg_prop, phys_hi 0x%08x,"
3568 	    " phys_mid 0x%08x, phys_low 0x%08x, size_hi 0x%08x,"
3569 	    " size_low 0x%08x\n", hiword, 0, 0, 0, size);
3570 
3571 	bcopy(reg, newreg, rlen);
3572 	bcopy(&addition, newreg + rlen, sizeof (pci_regspec_t));
3573 
3574 	/*
3575 	 * Write out the new "reg" property
3576 	 */
3577 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
3578 	    dip, "reg", (int *)newreg,
3579 	    (rlen + sizeof (pci_regspec_t))/sizeof (int));
3580 
3581 	kmem_free((caddr_t)reg, rlen);
3582 	kmem_free((caddr_t)newreg, rlen+sizeof (pci_regspec_t));
3583 
3584 	return (PCICFG_SUCCESS);
3585 }
3586 
3587 /*
3588  * Setup the basic 1275 properties based on information found in the config
3589  * header of the PCI device
3590  */
3591 static int
3592 cardbus_set_standard_props(dev_info_t *parent, dev_info_t *dip,
3593 			ddi_acc_handle_t config_handle)
3594 {
3595 	int ret;
3596 	uint16_t val;
3597 	uint32_t wordval;
3598 	uint8_t byteval;
3599 
3600 	/* These two exists only for non-bridges */
3601 	if ((pci_config_get8(config_handle,
3602 	    PCI_CONF_HEADER) & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) {
3603 		byteval = pci_config_get8(config_handle, PCI_CONF_MIN_G);
3604 		if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3605 		    "min-grant", byteval)) != DDI_SUCCESS) {
3606 			cardbus_err(dip, 1, "Failed to sent min-grant\n");
3607 			return (ret);
3608 		}
3609 
3610 		byteval = pci_config_get8(config_handle, PCI_CONF_MAX_L);
3611 		if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3612 		    "max-latency", byteval)) != DDI_SUCCESS) {
3613 			return (ret);
3614 		}
3615 	}
3616 
3617 	/*
3618 	 * These should always exist and have the value of the
3619 	 * corresponding register value
3620 	 */
3621 	val = pci_config_get16(config_handle, PCI_CONF_VENID);
3622 
3623 	/*
3624 	 * according to section 6.2.1 of revision 2 of the PCI local
3625 	 * bus specification - 0FFFFh is an invalid value for the vendor ID
3626 	 */
3627 	if (val == 0xffff) {
3628 		cardbus_err(dip, 1, "Illegal vendor-id 0x%x\n", val);
3629 		return (PCICFG_FAILURE);
3630 	}
3631 	if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3632 	    "vendor-id", val)) != DDI_SUCCESS) {
3633 		return (ret);
3634 	}
3635 
3636 	val = pci_config_get16(config_handle, PCI_CONF_DEVID);
3637 	if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3638 	    "device-id", val)) != DDI_SUCCESS) {
3639 		return (ret);
3640 	}
3641 	byteval = pci_config_get8(config_handle, PCI_CONF_REVID);
3642 	if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3643 	    "revision-id", byteval)) != DDI_SUCCESS) {
3644 		return (ret);
3645 	}
3646 
3647 	wordval = (pci_config_get16(config_handle, PCI_CONF_SUBCLASS)<< 8) |
3648 		(pci_config_get8(config_handle, PCI_CONF_PROGCLASS));
3649 
3650 	if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3651 	    "class-code", wordval)) != DDI_SUCCESS) {
3652 		return (ret);
3653 	}
3654 	val = (pci_config_get16(config_handle,
3655 	    PCI_CONF_STAT) & PCI_STAT_DEVSELT) >> 9;
3656 	if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3657 	    "devsel-speed", val)) != DDI_SUCCESS) {
3658 		return (ret);
3659 	}
3660 
3661 	/*
3662 	 * The next three are bits set in the status register.  The property is
3663 	 * present (but with no value other than its own existence) if the bit
3664 	 * is set, non-existent otherwise
3665 	 */
3666 	if (ddi_prop_exists(DDI_DEV_T_ANY, parent, DDI_PROP_DONTPASS,
3667 	    "fast-back-to-back") &&
3668 	    pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_FBBC) {
3669 
3670 		if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3671 		    "fast-back-to-back", 0)) != DDI_SUCCESS) {
3672 			return (ret);
3673 		}
3674 	}
3675 	if (pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_66MHZ) {
3676 		if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3677 		    "66mhz-capable", 0)) != DDI_SUCCESS) {
3678 			return (ret);
3679 		}
3680 	}
3681 	if (pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_UDF) {
3682 		if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3683 		    "udf-supported", 0)) != DDI_SUCCESS) {
3684 			return (ret);
3685 		}
3686 	}
3687 
3688 	/*
3689 	 * These next three are optional and are not present
3690 	 * if the corresponding register is zero.  If the value
3691 	 * is non-zero then the property exists with the value
3692 	 * of the register.
3693 	 */
3694 
3695 	/* look in the correct place for header type 2 */
3696 	byteval = pci_config_get8(config_handle, PCI_CONF_HEADER);
3697 	if ((byteval & PCI_HEADER_TYPE_M) == PCI_HEADER_TWO) {
3698 		if ((val = pci_config_get16(config_handle,
3699 		    PCI_CBUS_SUBVENID)) != 0) {
3700 			if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3701 			    "subsystem-vendor-id", val)) != DDI_SUCCESS) {
3702 				return (ret);
3703 			}
3704 		}
3705 		if ((val = pci_config_get16(config_handle,
3706 		    PCI_CBUS_SUBSYSID)) != 0) {
3707 			if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3708 			    "subsystem-id", val)) != DDI_SUCCESS) {
3709 				return (ret);
3710 			}
3711 		}
3712 	} else {
3713 		if ((val = pci_config_get16(config_handle,
3714 		    PCI_CONF_SUBVENID)) != 0) {
3715 			if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3716 			    "subsystem-vendor-id", val)) != DDI_SUCCESS) {
3717 				return (ret);
3718 			}
3719 		}
3720 		if ((val = pci_config_get16(config_handle,
3721 		    PCI_CONF_SUBSYSID)) != 0) {
3722 			if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3723 			    "subsystem-id", val)) != DDI_SUCCESS) {
3724 				return (ret);
3725 			}
3726 		}
3727 	}
3728 
3729 	if ((val = pci_config_get8(config_handle,
3730 	    PCI_CONF_CACHE_LINESZ)) != 0) {
3731 		if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3732 		    "cache-line-size", val)) != DDI_SUCCESS) {
3733 			return (ret);
3734 		}
3735 	}
3736 
3737 	/*
3738 	 * If the Interrupt Pin register is non-zero then the
3739 	 * interrupts property exists
3740 	 */
3741 	if ((byteval = pci_config_get8(config_handle, PCI_CONF_IPIN)) != 0) {
3742 		/*
3743 		 * If interrupt pin is non-zero,
3744 		 * record the interrupt line used
3745 		 */
3746 		cardbus_err(dip, 8, "Adding interrupts property\n");
3747 		if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3748 		    "interrupts", byteval)) != DDI_SUCCESS) {
3749 			return (ret);
3750 		}
3751 	}
3752 	return (PCICFG_SUCCESS);
3753 }
3754 
3755 /*
3756  * Setup the basic properties required by the ISA node.
3757  */
3758 static int
3759 cardbus_set_isa_props(dev_info_t *parent, dev_info_t *dip,
3760 			char *name, char *compat[])
3761 {
3762 	int ret, n;
3763 
3764 	_NOTE(ARGUNUSED(parent))
3765 
3766 	cardbus_err(dip, 8, "Adding interrupts property\n");
3767 	if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3768 	    "interrupts", 1)) != DDI_SUCCESS) {
3769 		return (ret);
3770 	}
3771 
3772 	/*
3773 	 * The node name field needs to be filled in with the name
3774 	 */
3775 	if (ndi_devi_set_nodename(dip, name, 0) != NDI_SUCCESS) {
3776 		cardbus_err(dip, 1, "Failed to set nodename for node\n");
3777 		return (PCICFG_FAILURE);
3778 	}
3779 
3780 	/*
3781 	 * Create the compatible property as an array of pointers
3782 	 * to strings.  Start with the buffer created above.
3783 	 */
3784 	n = 0;
3785 	while (compat[n] != NULL)
3786 		n++;
3787 
3788 	if (n != 0)
3789 		if ((ret = ndi_prop_update_string_array(DDI_DEV_T_NONE, dip,
3790 		    "compatible", compat, n)) != DDI_SUCCESS)
3791 			return (ret);
3792 
3793 	return (PCICFG_SUCCESS);
3794 }
3795 
3796 static int
3797 cardbus_set_busnode_props(dev_info_t *dip)
3798 {
3799 	cardbus_err(dip, 6, "cardbus_set_busnode_props\n");
3800 
3801 	cardbus_force_stringprop(dip, "device_type", "pci");
3802 
3803 	if (ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3804 	    "#address-cells", 3) != DDI_SUCCESS) {
3805 		cardbus_err(dip, 4, "Failed to set #address-cells\n");
3806 	}
3807 	if (ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3808 	    "#size-cells", 2) != DDI_SUCCESS) {
3809 		cardbus_err(dip, 4, "Failed to set #size-cells\n");
3810 	}
3811 	return (PCICFG_SUCCESS);
3812 }
3813 
3814 static int
3815 cardbus_set_busnode_isaprops(dev_info_t *dip)
3816 {
3817 	cardbus_err(dip, 6, "cardbus_set_busnode_props\n");
3818 
3819 	cardbus_force_stringprop(dip, "device_type", "isa");
3820 
3821 	if (ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3822 	    "#address-cells", 2) != DDI_SUCCESS) {
3823 		cardbus_err(dip, 4, "Failed to set #address-cells\n");
3824 	}
3825 	if (ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3826 	    "#size-cells", 1) != DDI_SUCCESS) {
3827 		cardbus_err(dip, 4, "Failed to set #size-cells\n");
3828 	}
3829 	return (PCICFG_SUCCESS);
3830 }
3831 
3832 /*
3833  * Use cb%x,%x rather than pci%x,%x so that we can use specific cardbus
3834  * drivers in /etc/driver_aliases if required
3835  */
3836 static int
3837 cardbus_set_childnode_props(dev_info_t *dip, ddi_acc_handle_t config_handle)
3838 {
3839 	int		ret;
3840 #ifndef _DONT_USE_1275_GENERIC_NAMES
3841 	uint32_t	wordval;
3842 #endif
3843 	char		*name;
3844 	char		buffer[64];
3845 	uint32_t	classcode;
3846 	char		*compat[8];
3847 	int		i, n;
3848 	uint16_t	subsysid, subvenid, devid, venid;
3849 	uint8_t		header_type;
3850 
3851 	/*
3852 	 * NOTE: These are for both a child and PCI-PCI bridge node
3853 	 */
3854 #ifndef _DONT_USE_1275_GENERIC_NAMES
3855 	wordval = (pci_config_get16(config_handle, PCI_CONF_SUBCLASS)<< 8) |
3856 	    (pci_config_get8(config_handle, PCI_CONF_PROGCLASS));
3857 #endif
3858 
3859 	/* Cardbus support */
3860 	venid = pci_config_get16(config_handle, PCI_CONF_VENID);
3861 	devid = pci_config_get16(config_handle, PCI_CONF_DEVID);
3862 
3863 	header_type = pci_config_get8(config_handle, PCI_CONF_HEADER);
3864 	if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_TWO) {
3865 		subvenid = pci_config_get16(config_handle, PCI_CBUS_SUBVENID);
3866 		subsysid = pci_config_get16(config_handle, PCI_CBUS_SUBSYSID);
3867 	} else {
3868 		subvenid = pci_config_get16(config_handle, PCI_CONF_SUBVENID);
3869 		subsysid = pci_config_get16(config_handle, PCI_CONF_SUBSYSID);
3870 	}
3871 
3872 	if (subsysid != 0) {
3873 		(void) sprintf(buffer, "pci%x,%x", subvenid, subsysid);
3874 	} else {
3875 		(void) sprintf(buffer, "pci%x,%x", venid, devid);
3876 	}
3877 
3878 	cardbus_err(dip, 8, "Childname is %s\n", buffer);
3879 
3880 	/*
3881 	 * In some environments, trying to use "generic" 1275 names is
3882 	 * not the convention.  In those cases use the name as created
3883 	 * above.  In all the rest of the cases, check to see if there
3884 	 * is a generic name first.
3885 	 */
3886 #ifdef _DONT_USE_1275_GENERIC_NAMES
3887 	name = buffer;
3888 #else
3889 	if ((name = cardbus_get_class_name(wordval>>8)) == NULL) {
3890 		/*
3891 		 * Set name to the above fabricated name
3892 		 */
3893 		name = buffer;
3894 	}
3895 
3896 	cardbus_err(dip, 8, "Set nodename to %s\n", name);
3897 #endif
3898 
3899 	/*
3900 	 * The node name field needs to be filled in with the name
3901 	 */
3902 	if (ndi_devi_set_nodename(dip, name, 0) != NDI_SUCCESS) {
3903 		cardbus_err(dip, 1, "Failed to set nodename for node\n");
3904 		return (PCICFG_FAILURE);
3905 	}
3906 
3907 	/*
3908 	 * Create the compatible property as an array of pointers
3909 	 * to strings.  Start with the cb name.
3910 	 */
3911 	n = 0;
3912 
3913 	if (subsysid != 0) {
3914 		(void) sprintf(buffer, "cb%x,%x", subvenid, subsysid);
3915 	} else {
3916 		(void) sprintf(buffer, "cb%x,%x", venid, devid);
3917 	}
3918 
3919 	compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP);
3920 	(void) strcpy(compat[n++], buffer);
3921 
3922 	if (subsysid != 0) {
3923 		/*
3924 		 * Add subsys numbers as pci compatible.
3925 		 */
3926 		(void) sprintf(buffer, "pci%x,%x", subvenid, subsysid);
3927 		compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP);
3928 		(void) strcpy(compat[n++], buffer);
3929 	}
3930 
3931 	/*
3932 	 * Add in the VendorID/DeviceID compatible name.
3933 	 */
3934 	(void) sprintf(buffer, "pci%x,%x", venid, devid);
3935 
3936 	compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP);
3937 	(void) strcpy(compat[n++], buffer);
3938 
3939 	classcode = (pci_config_get16(config_handle, PCI_CONF_SUBCLASS)<< 8) |
3940 	    (pci_config_get8(config_handle, PCI_CONF_PROGCLASS));
3941 
3942 	/*
3943 	 * Add in the Classcode
3944 	 */
3945 	(void) sprintf(buffer, "pciclass,%06x", classcode);
3946 
3947 	cardbus_err(dip, 8, "class code %s\n", buffer);
3948 
3949 	compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP);
3950 	(void) strcpy(compat[n++], buffer);
3951 
3952 	if ((ret = ndi_prop_update_string_array(DDI_DEV_T_NONE, dip,
3953 	    "compatible", (char **)compat, n)) != DDI_SUCCESS) {
3954 		return (ret);
3955 	}
3956 
3957 	for (i = 0; i < n; i++) {
3958 		kmem_free(compat[i], strlen(compat[i]) + 1);
3959 	}
3960 
3961 	return (PCICFG_SUCCESS);
3962 }
3963 
3964 /*
3965  * Program the bus numbers into the bridge
3966  */
3967 static void
3968 cardbus_set_bus_numbers(ddi_acc_handle_t config_handle,
3969 			uint_t primary, uint_t secondary)
3970 {
3971 	cardbus_err(NULL, 8,
3972 	    "cardbus_set_bus_numbers [%d->%d]\n", primary, secondary);
3973 
3974 	/*
3975 	 * Primary bus#
3976 	 */
3977 	pci_config_put8(config_handle, PCI_BCNF_PRIBUS, primary);
3978 
3979 	/*
3980 	 * Secondary bus#
3981 	 */
3982 	pci_config_put8(config_handle, PCI_BCNF_SECBUS, secondary);
3983 
3984 	/*
3985 	 * Set the subordinate bus number to ff in order to pass through any
3986 	 * type 1 cycle with a bus number higher than the secondary bus#
3987 	 * Note that this is reduced once the probe is complete in the
3988 	 * cardbus_setup_bridge() function.
3989 	 */
3990 	pci_config_put8(config_handle, PCI_BCNF_SUBBUS, 0xFF);
3991 }
3992 
3993 static void
3994 enable_pci_isa_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle)
3995 {
3996 	uint16_t comm, stat;
3997 
3998 	stat = pci_config_get16(config_handle, PCI_CONF_STAT);
3999 	comm = pci_config_get16(config_handle, PCI_CONF_COMM);
4000 
4001 	/*
4002 	 * Enable memory, IO, bus mastership and error detection.
4003 	 */
4004 	comm |= (PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO |
4005 	    PCI_COMM_PARITY_DETECT | PCI_COMM_SERR_ENABLE);
4006 	if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
4007 	    "fast-back-to-back"))
4008 		comm |= PCI_COMM_BACK2BACK_ENAB;
4009 	pci_config_put16(config_handle, PCI_CONF_COMM, comm);
4010 	cardbus_err(NULL, 8,
4011 	    "enable_pci_isa_bridge stat 0x%04x comm 0x%04x\n", stat, comm);
4012 
4013 	/*
4014 	 * ITE8888 Specific registers.
4015 	 */
4016 	pci_config_put8(config_handle, 0x50, 0x00); /* Timing Control */
4017 	pci_config_put8(config_handle, 0x52, 0x00); /* Master DMA Access */
4018 	pci_config_put8(config_handle, 0x53, 0x01); /* ROMCS */
4019 }
4020 
4021 static void
4022 enable_pci_pci_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle)
4023 {
4024 	uint16_t comm, stat, bctrl;
4025 
4026 	stat = pci_config_get16(config_handle, PCI_CONF_STAT);
4027 	comm = pci_config_get16(config_handle, PCI_CONF_COMM);
4028 	bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL);
4029 
4030 	comm &= ~(PCI_COMM_IO | PCI_COMM_MAE);
4031 	comm |= (PCI_COMM_ME | PCI_COMM_PARITY_DETECT | PCI_COMM_SERR_ENABLE);
4032 
4033 	/*
4034 	 * Enable back to back.
4035 	 */
4036 	if (stat & PCI_STAT_FBBC)
4037 		comm |= PCI_COMM_BACK2BACK_ENAB;
4038 
4039 	pci_config_put16(config_handle, PCI_CONF_COMM, comm);
4040 
4041 	/*
4042 	 * Reset the sub-ordinate bus.
4043 	 */
4044 	if (!(bctrl & PCI_BCNF_BCNTRL_RESET))
4045 		pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL,
4046 			bctrl | PCI_BCNF_BCNTRL_RESET);
4047 	else
4048 		bctrl &= ~PCI_BCNF_BCNTRL_RESET;
4049 
4050 	/*
4051 	 * Enable error reporting.
4052 	 */
4053 	bctrl |= (PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE |
4054 	    PCI_BCNF_BCNTRL_MAST_AB_MODE);
4055 
4056 	/*
4057 	 * Enable back to back on secondary bus.
4058 	 */
4059 	if (stat & PCI_STAT_FBBC)
4060 		bctrl |= PCI_BCNF_BCNTRL_B2B_ENAB;
4061 
4062 	pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl);
4063 	cardbus_err(dip, 8,
4064 	    "enable_pci_pci_bridge stat 0x%04x comm 0x%04x bctrl 0x%04x\n",
4065 	    stat, comm, bctrl);
4066 }
4067 
4068 static int	cardbus_reset_wait = 20;
4069 
4070 static void
4071 enable_cardbus_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle)
4072 {
4073 	uint16_t comm, stat, bctrl;
4074 
4075 	stat = pci_config_get16(config_handle, PCI_CONF_STAT);
4076 	comm = pci_config_get16(config_handle, PCI_CONF_COMM);
4077 	bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL);
4078 
4079 	/*
4080 	 * Don't mess with the command register on the cardbus bridge
4081 	 * itself. This should have been done when it's parent
4082 	 * did the setup. Some devices *require* certain things to
4083 	 * disabled, this can be done using the "command-preserve"
4084 	 * property and if we mess with it here it breaks that.
4085 	 *
4086 	 * comm |= (PCI_COMM_ME | PCI_COMM_PARITY_DETECT |
4087 	 *	PCI_COMM_SERR_ENABLE);
4088 	 */
4089 
4090 	/*
4091 	 * Reset the sub-ordinate bus.
4092 	 */
4093 	if (!(bctrl & PCI_BCNF_BCNTRL_RESET))
4094 		pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL,
4095 			bctrl | PCI_BCNF_BCNTRL_RESET);
4096 	else
4097 		bctrl &= ~PCI_BCNF_BCNTRL_RESET;
4098 
4099 	/*
4100 	 * Turn off pre-fetch.
4101 	 */
4102 	bctrl &= ~(CB_BCNF_BCNTRL_MEM0_PREF | CB_BCNF_BCNTRL_MEM1_PREF |
4103 	    PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE);
4104 
4105 	/*
4106 	 * Enable error reporting.
4107 	 */
4108 	bctrl |= (PCI_BCNF_BCNTRL_MAST_AB_MODE | CB_BCNF_BCNTRL_WRITE_POST);
4109 	if (comm & PCI_COMM_PARITY_DETECT)
4110 		bctrl |= PCI_BCNF_BCNTRL_PARITY_ENABLE;
4111 	if (comm & PCI_COMM_SERR_ENABLE)
4112 		bctrl |= PCI_BCNF_BCNTRL_SERR_ENABLE;
4113 
4114 	pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl);
4115 	pci_config_put8(config_handle, PCI_CBUS_LATENCY_TIMER,
4116 	    cardbus_latency_timer);
4117 
4118 	pci_config_put16(config_handle, PCI_CONF_STAT, stat);
4119 	pci_config_put16(config_handle, PCI_CONF_COMM, comm);
4120 
4121 	cardbus_err(dip, 8,
4122 	    "enable_cardbus_bridge() stat 0x%04x comm 0x%04x bctrl 0x%04x\n",
4123 	    stat, comm, bctrl);
4124 
4125 	/* after resetting the bridge, wait for everything to stablize */
4126 	delay(drv_usectohz(cardbus_reset_wait * 1000));
4127 
4128 }
4129 
4130 static void
4131 disable_pci_pci_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle)
4132 {
4133 	uint16_t comm, bctrl;
4134 
4135 	comm = pci_config_get16(config_handle, PCI_CONF_COMM);
4136 	bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL);
4137 
4138 	/*
4139 	 * Turn off subordinate bus access.
4140 	 */
4141 	pci_config_put8(config_handle, PCI_BCNF_SECBUS, 0);
4142 	pci_config_put8(config_handle, PCI_BCNF_SUBBUS, 0);
4143 
4144 	/*
4145 	 * Disable error reporting.
4146 	 */
4147 	bctrl &= ~(PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE |
4148 	    PCI_BCNF_BCNTRL_MAST_AB_MODE);
4149 	comm = 0;
4150 
4151 	pci_config_put16(config_handle, PCI_CONF_COMM, comm);
4152 	pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl);
4153 
4154 	cardbus_err(dip, 6,
4155 	    "disable_pci_pci_bridge() stat 0x%04x comm 0x%04x bctrl 0x%04x\n",
4156 	    pci_config_get16(config_handle, PCI_CONF_STAT), comm, bctrl);
4157 }
4158 
4159 static void
4160 disable_cardbus_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle)
4161 {
4162 	uint16_t comm, bctrl;
4163 
4164 	comm = pci_config_get16(config_handle, PCI_CONF_COMM);
4165 	bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL);
4166 
4167 	/*
4168 	 * Turn off subordinate bus access.
4169 	 */
4170 	pci_config_put8(config_handle, PCI_BCNF_SECBUS, 0);
4171 	pci_config_put8(config_handle, PCI_BCNF_SUBBUS, 0);
4172 
4173 	/*
4174 	 * Disable error reporting.
4175 	 */
4176 	bctrl &= ~(PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE |
4177 	    PCI_BCNF_BCNTRL_MAST_AB_MODE);
4178 
4179 	pci_config_put32(config_handle, PCI_CBUS_MEM_LIMIT0, 0);
4180 	pci_config_put32(config_handle, PCI_CBUS_MEM_BASE0, 0);
4181 	pci_config_put32(config_handle, PCI_CBUS_IO_LIMIT0, 0);
4182 	pci_config_put32(config_handle, PCI_CBUS_IO_BASE0, 0);
4183 	pci_config_put16(config_handle, PCI_CONF_COMM, comm);
4184 	pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl);
4185 
4186 	cardbus_err(dip, 6,
4187 	    "disable_cardbus_bridge() stat 0x%04x comm 0x%04x bctrl 0x%04x\n",
4188 	    pci_config_get16(config_handle, PCI_CONF_STAT), comm, bctrl);
4189 }
4190 
4191 static void
4192 enable_cardbus_device(dev_info_t *dip, ddi_acc_handle_t config_handle)
4193 {
4194 	uint16_t comm, stat;
4195 
4196 	stat = pci_config_get16(config_handle, PCI_CONF_STAT);
4197 	comm = pci_config_get16(config_handle, PCI_CONF_COMM);
4198 
4199 	/*
4200 	 * Enable memory, IO, bus mastership and error detection.
4201 	 */
4202 	comm |= (PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO |
4203 	    PCI_COMM_PARITY_DETECT | PCI_COMM_SERR_ENABLE);
4204 	if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
4205 	    "fast-back-to-back"))
4206 		comm |= PCI_COMM_BACK2BACK_ENAB;
4207 	pci_config_put16(config_handle, PCI_CONF_COMM, comm);
4208 	cardbus_err(NULL, 8,
4209 	    "enable_cardbus_device stat 0x%04x comm 0x%04x\n", stat, comm);
4210 }
4211 
4212 static void
4213 disable_cardbus_device(ddi_acc_handle_t config_handle)
4214 {
4215 	cardbus_err(NULL, 8, "disable_cardbus_device\n");
4216 
4217 	/*
4218 	 * Turn off everything in the command register.
4219 	 */
4220 	pci_config_put16(config_handle, PCI_CONF_COMM, 0x0);
4221 }
4222 
4223 #ifndef _DONT_USE_1275_GENERIC_NAMES
4224 static char *
4225 cardbus_get_class_name(uint32_t classcode)
4226 {
4227 	struct cardbus_name_entry *ptr;
4228 
4229 	for (ptr = &cardbus_class_lookup[0]; ptr->name != NULL; ptr++) {
4230 		if (ptr->class_code == classcode) {
4231 			return (ptr->name);
4232 		}
4233 	}
4234 	return (NULL);
4235 }
4236 #endif /* _DONT_USE_1275_GENERIC_NAMES */
4237 
4238 static void
4239 cardbus_force_boolprop(dev_info_t *dip, char *pname)
4240 {
4241 	int ret;
4242 
4243 	if ((ret = ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
4244 	    pname)) != DDI_SUCCESS) {
4245 		if (ret == DDI_PROP_NOT_FOUND)
4246 			if (ddi_prop_create(DDI_DEV_T_NONE, dip,
4247 			    DDI_PROP_CANSLEEP, pname,
4248 			    (caddr_t)NULL, 0) != DDI_SUCCESS)
4249 				cardbus_err(dip, 4,
4250 				    "Failed to set boolean property "
4251 				    "\"%s\"\n", pname);
4252 	}
4253 }
4254 
4255 static void
4256 cardbus_force_intprop(dev_info_t *dip, char *pname, int *pval, int len)
4257 {
4258 	int ret;
4259 
4260 	if ((ret = ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
4261 	    pname, pval, len)) != DDI_SUCCESS) {
4262 		if (ret == DDI_PROP_NOT_FOUND)
4263 			if (ddi_prop_create(DDI_DEV_T_NONE, dip,
4264 			    DDI_PROP_CANSLEEP, pname,
4265 			    (caddr_t)pval, len*sizeof (int))
4266 			    != DDI_SUCCESS)
4267 				cardbus_err(dip, 4,
4268 				    "Failed to set int property \"%s\"\n",
4269 				    pname);
4270 	}
4271 }
4272 
4273 static void
4274 cardbus_force_stringprop(dev_info_t *dip, char *pname, char *pval)
4275 {
4276 	int ret;
4277 
4278 	if ((ret = ndi_prop_update_string(DDI_DEV_T_NONE, dip,
4279 	    pname, pval)) != DDI_SUCCESS) {
4280 		if (ret == DDI_PROP_NOT_FOUND)
4281 			if (ddi_prop_create(DDI_DEV_T_NONE, dip,
4282 			    DDI_PROP_CANSLEEP, pname,
4283 			    pval, strlen(pval) + 1) != DDI_SUCCESS)
4284 				cardbus_err(dip, 4,
4285 				    "Failed to set string property "
4286 				    "\"%s\" to \"%s\"\n",
4287 				    pname, pval);
4288 	}
4289 }
4290 
4291 static void
4292 split_addr(char *naddr, int *dev, int *func)
4293 {
4294 	char	c;
4295 	int	*ip = dev;
4296 
4297 	*dev = 0;
4298 	*func = 0;
4299 
4300 	while (c = *naddr++) {
4301 		if (c == ',') {
4302 			ip = func;
4303 			continue;
4304 		}
4305 		if (c >= '0' && c <= '9') {
4306 			*ip = (*ip * 16) + (c - '0');
4307 		} else if (c >= 'a' && c <= 'f') {
4308 			*ip = (*ip * 16) + 10 + (c - 'a');
4309 		} else
4310 			break;
4311 	}
4312 }
4313 
4314 #ifdef DEBUG
4315 static void
4316 cardbus_dump_common_config(ddi_acc_handle_t config_handle)
4317 {
4318 	cardbus_err(NULL, 1,
4319 	    " Vendor ID   = [0x%04x]        "
4320 	    "Device ID   = [0x%04x]\n",
4321 	    pci_config_get16(config_handle, PCI_CONF_VENID),
4322 	    pci_config_get16(config_handle, PCI_CONF_DEVID));
4323 	cardbus_err(NULL, 1,
4324 	    " Command REG = [0x%04x]        "
4325 	    "Status  REG = [0x%04x]\n",
4326 	    pci_config_get16(config_handle, PCI_CONF_COMM),
4327 	    pci_config_get16(config_handle, PCI_CONF_STAT));
4328 	cardbus_err(NULL, 1,
4329 	    " Revision ID = [0x%02x]          "
4330 	    "Prog Class  = [0x%02x]\n",
4331 	    pci_config_get8(config_handle, PCI_CONF_REVID),
4332 	    pci_config_get8(config_handle, PCI_CONF_PROGCLASS));
4333 	cardbus_err(NULL, 1,
4334 	    " Dev Class   = [0x%02x]          "
4335 	    "Base Class  = [0x%02x]\n",
4336 	    pci_config_get8(config_handle, PCI_CONF_SUBCLASS),
4337 	    pci_config_get8(config_handle, PCI_CONF_BASCLASS));
4338 	cardbus_err(NULL, 1,
4339 	    " Cache LnSz  = [0x%02x]          "
4340 	    "Latency Tmr = [0x%02x]\n",
4341 	    pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ),
4342 	    pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER));
4343 	cardbus_err(NULL, 1,
4344 	    " Header Type = [0x%02x]          "
4345 	    "BIST        = [0x%02x]\n",
4346 	    pci_config_get8(config_handle, PCI_CONF_HEADER),
4347 	    pci_config_get8(config_handle, PCI_CONF_BIST));
4348 }
4349 
4350 static void
4351 cardbus_dump_device_config(ddi_acc_handle_t config_handle)
4352 {
4353 	cardbus_dump_common_config(config_handle);
4354 
4355 	cardbus_err(NULL, 1,
4356 	    " BASE 0      = [0x%08x]	BASE 1      = [0x%08x]\n",
4357 	    pci_config_get32(config_handle, PCI_CONF_BASE0),
4358 	    pci_config_get32(config_handle, PCI_CONF_BASE1));
4359 	cardbus_err(NULL, 1,
4360 	    " BASE 2      = [0x%08x]	BASE 3      = [0x%08x]\n",
4361 	    pci_config_get32(config_handle, PCI_CONF_BASE2),
4362 	    pci_config_get32(config_handle, PCI_CONF_BASE3));
4363 	cardbus_err(NULL, 1,
4364 	    " BASE 4      = [0x%08x]	BASE 5      = [0x%08x]\n",
4365 	    pci_config_get32(config_handle, PCI_CONF_BASE4),
4366 	    pci_config_get32(config_handle, PCI_CONF_BASE5));
4367 	cardbus_err(NULL, 1,
4368 	    " Cardbus CIS = [0x%08x]	ROM         = [0x%08x]\n",
4369 	    pci_config_get32(config_handle, PCI_CONF_CIS),
4370 	    pci_config_get32(config_handle, PCI_CONF_ROM));
4371 	cardbus_err(NULL, 1,
4372 	    " Sub VID     = [0x%04x]	Sub SID     = [0x%04x]\n",
4373 	    pci_config_get16(config_handle, PCI_CONF_SUBVENID),
4374 	    pci_config_get16(config_handle, PCI_CONF_SUBSYSID));
4375 	cardbus_err(NULL, 1,
4376 	    " I Line      = [0x%02x]	I Pin       = [0x%02x]\n",
4377 	    pci_config_get8(config_handle, PCI_CONF_ILINE),
4378 	    pci_config_get8(config_handle, PCI_CONF_IPIN));
4379 	cardbus_err(NULL, 1,
4380 	    " Max Grant   = [0x%02x]	Max Latent  = [0x%02x]\n",
4381 	    pci_config_get8(config_handle, PCI_CONF_MIN_G),
4382 	    pci_config_get8(config_handle, PCI_CONF_MAX_L));
4383 }
4384 
4385 static void
4386 cardbus_dump_bridge_config(ddi_acc_handle_t config_handle,
4387 			uint8_t header_type)
4388 {
4389 	if (header_type == PCI_HEADER_PPB) {
4390 		cardbus_dump_common_config(config_handle);
4391 		cardbus_err(NULL, 1,
4392 		    "........................................\n");
4393 	} else {
4394 		cardbus_dump_common_config(config_handle);
4395 		cardbus_err(NULL, 1,
4396 		    " Mem Base    = [0x%08x]	CBus Status = [0x%04x]\n",
4397 		    pci_config_get32(config_handle, PCI_CBUS_SOCK_REG),
4398 		    pci_config_get16(config_handle, PCI_CBUS_SEC_STATUS));
4399 	}
4400 
4401 	cardbus_err(NULL, 1,
4402 	    " Pri Bus	= [0x%02x]		Sec Bus	= [0x%02x]\n",
4403 	    pci_config_get8(config_handle, PCI_BCNF_PRIBUS),
4404 	    pci_config_get8(config_handle, PCI_BCNF_SECBUS));
4405 	cardbus_err(NULL, 1,
4406 	    " Sub Bus     = [0x%02x]		Sec Latency = [0x%02x]\n",
4407 	    pci_config_get8(config_handle, PCI_BCNF_SUBBUS),
4408 	    pci_config_get8(config_handle, PCI_BCNF_LATENCY_TIMER));
4409 
4410 	switch (header_type) {
4411 	case PCI_HEADER_PPB:
4412 		cardbus_err(NULL, 1,
4413 		    " I/O Base LO = [0x%02x]	I/O Lim LO  = [0x%02x]\n",
4414 		    pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW),
4415 		    pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW));
4416 		cardbus_err(NULL, 1,
4417 		    " Sec. Status = [0x%04x]\n",
4418 		    pci_config_get16(config_handle, PCI_BCNF_SEC_STATUS));
4419 		cardbus_err(NULL, 1,
4420 		    " Mem Base    = [0x%04x]	Mem Limit   = [0x%04x]\n",
4421 		    pci_config_get16(config_handle, PCI_BCNF_MEM_BASE),
4422 		    pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT));
4423 		cardbus_err(NULL, 1,
4424 		    " PF Mem Base = [0x%04x]	PF Mem Lim  = [0x%04x]\n",
4425 		    pci_config_get16(config_handle, PCI_BCNF_PF_BASE_LOW),
4426 		    pci_config_get16(config_handle, PCI_BCNF_PF_LIMIT_LOW));
4427 		cardbus_err(NULL, 1,
4428 		    " PF Base HI  = [0x%08x]	PF Lim  HI  = [0x%08x]\n",
4429 		    pci_config_get32(config_handle, PCI_BCNF_PF_BASE_HIGH),
4430 		    pci_config_get32(config_handle, PCI_BCNF_PF_LIMIT_HIGH));
4431 		cardbus_err(NULL, 1,
4432 		    " I/O Base HI = [0x%04x]	I/O Lim HI  = [0x%04x]\n",
4433 		    pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI),
4434 		    pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI));
4435 		cardbus_err(NULL, 1,
4436 		    " ROM addr    = [0x%08x]\n",
4437 		    pci_config_get32(config_handle, PCI_BCNF_ROM));
4438 		break;
4439 	case PCI_HEADER_CARDBUS:
4440 		cardbus_err(NULL, 1,
4441 		    " Mem Base 0  = [0x%08x]	Mem Limit 0 = [0x%08x]\n",
4442 		    pci_config_get32(config_handle, PCI_CBUS_MEM_BASE0),
4443 		    pci_config_get32(config_handle, PCI_CBUS_MEM_LIMIT0));
4444 		cardbus_err(NULL, 1,
4445 		    " Mem Base 1  = [0x%08x]	Mem Limit 1 = [0x%08x]\n",
4446 		    pci_config_get32(config_handle, PCI_CBUS_MEM_BASE1),
4447 		    pci_config_get32(config_handle, PCI_CBUS_MEM_LIMIT1));
4448 		cardbus_err(NULL, 1,
4449 		    " IO Base 0   = [0x%08x]	IO Limit 0  = [0x%08x]\n",
4450 		    pci_config_get32(config_handle, PCI_CBUS_IO_BASE0),
4451 		    pci_config_get32(config_handle, PCI_CBUS_IO_LIMIT0));
4452 		cardbus_err(NULL, 1,
4453 		    " IO Base 1   = [0x%08x]	IO Limit 1  = [0x%08x]\n",
4454 		    pci_config_get32(config_handle, PCI_CBUS_IO_BASE1),
4455 		    pci_config_get32(config_handle, PCI_CBUS_IO_LIMIT1));
4456 		break;
4457 	}
4458 	cardbus_err(NULL, 1,
4459 	    " Intr Line   = [0x%02x]		Intr Pin    = [0x%02x]\n",
4460 	    pci_config_get8(config_handle, PCI_BCNF_ILINE),
4461 	    pci_config_get8(config_handle, PCI_BCNF_IPIN));
4462 	cardbus_err(NULL, 1,
4463 	    " Bridge Ctrl = [0x%04x]\n",
4464 	    pci_config_get16(config_handle, PCI_BCNF_BCNTRL));
4465 
4466 	switch (header_type) {
4467 	case PCI_HEADER_CARDBUS:
4468 		cardbus_err(NULL, 1,
4469 		    " Sub VID     = [0x%04x]	Sub SID     = [0x%04x]\n",
4470 		    pci_config_get16(config_handle, PCI_CBUS_SUBVENID),
4471 		    pci_config_get16(config_handle, PCI_CBUS_SUBSYSID));
4472 		/* LATER: TI1250 only */
4473 		cardbus_err(NULL, 1,
4474 		    " Sys Control = [0x%08x]\n",
4475 		    pci_config_get32(config_handle, 0x80));
4476 	}
4477 }
4478 
4479 static void
4480 cardbus_dump_config(ddi_acc_handle_t config_handle)
4481 {
4482 	uint8_t header_type = pci_config_get8(config_handle,
4483 	    PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
4484 
4485 	if (header_type == PCI_HEADER_PPB || header_type == PCI_HEADER_CARDBUS)
4486 		cardbus_dump_bridge_config(config_handle, header_type);
4487 	else
4488 		cardbus_dump_device_config(config_handle);
4489 }
4490 
4491 static void
4492 cardbus_dump_reg(dev_info_t *dip, const pci_regspec_t *regspec, int nelems)
4493 {
4494 	/* int rlen = nelems * sizeof(pci_regspec_t); */
4495 
4496 	cardbus_err(dip, 6,
4497 	    "cardbus_dump_reg: \"reg\" has %d elements\n", nelems);
4498 
4499 #if defined(CARDBUS_DEBUG)
4500 	if (cardbus_debug >= 1) {
4501 		int	i;
4502 		uint32_t *regs = (uint32_t *)regspec;
4503 
4504 		for (i = 0; i < nelems; i++) {
4505 
4506 			cardbus_err(NULL, 6,
4507 			    "\t%d:%08x %08x %08x %08x %08x\n",
4508 			    i, regs[0], regs[1], regs[2], regs[3], regs[4]);
4509 		}
4510 	}
4511 #endif
4512 }
4513 
4514 #endif
4515 
4516 #if defined(CARDBUS_DEBUG)
4517 void
4518 cardbus_dump_children(dev_info_t *dip, int level)
4519 {
4520 	dev_info_t *next;
4521 
4522 	cardbus_err(dip, 1,
4523 	    "\t%d: %s: 0x%p\n", level, ddi_node_name(dip), (void *) dip);
4524 	for (next = ddi_get_child(dip); next;
4525 	    next = ddi_get_next_sibling(next))
4526 		cardbus_dump_children(next, level + 1);
4527 }
4528 
4529 void
4530 cardbus_dump_family_tree(dev_info_t *dip)
4531 {
4532 	cardbus_err(dip, 1, "0x%p family tree:\n", (void *) dip);
4533 	cardbus_dump_children(dip, 1);
4534 }
4535 #endif
4536