1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * Copyright (c) * Copyright (c) 2001 Tadpole Technology plc 27 * All rights reserved. 28 * From "@(#)pcicfg.c 1.31 99/06/18 SMI" 29 */ 30 31 /* 32 * Cardbus configurator 33 */ 34 35 #include <sys/ddi.h> 36 #include <sys/sunndi.h> 37 #include <sys/ndi_impldefs.h> 38 39 #include <sys/pci.h> 40 #include <sys/ebus.h> 41 #include <sys/hotplug/hpctrl.h> 42 #include <sys/hotplug/pci/pcicfg.h> 43 44 #include <sys/pctypes.h> 45 #include <sys/pcmcia.h> 46 #include <sys/sservice.h> 47 48 #include <sys/isa_defs.h> 49 50 #include <sys/note.h> 51 52 #include <sys/ethernet.h> 53 54 #include "cardbus.h" 55 #include "cardbus_parse.h" 56 #include "cardbus_cfg.h" 57 58 /* 59 * ************************************************************************ 60 * *** Implementation specific local data structures/definitions. *** 61 * ************************************************************************ 62 */ 63 64 #define PCICFG_MAX_DEVICE 32 65 #define PCICFG_MAX_FUNCTION 8 66 67 static uint32_t pcicfg_max_device = PCICFG_MAX_DEVICE; 68 static uint32_t pcicfg_max_function = PCICFG_MAX_FUNCTION; 69 70 #define PCICFG_NODEVICE 42 71 #define PCICFG_NOMEMORY 43 72 #define PCICFG_NOMULTI 44 73 74 #define PCICFG_HIADDR(n) ((uint32_t)(((uint64_t)(n) & 0xFFFFFFFF00000000)>> 32)) 75 #define PCICFG_LOADDR(n) ((uint32_t)((uint64_t)(n) & 0x00000000FFFFFFFF)) 76 #define PCICFG_LADDR(lo, hi) (((uint64_t)(hi) << 32) | (uint32_t)(lo)) 77 78 #define PCICFG_HIWORD(n) ((uint16_t)(((uint32_t)(n) & 0xFFFF0000)>> 16)) 79 #define PCICFG_LOWORD(n) ((uint16_t)((uint32_t)(n) & 0x0000FFFF)) 80 #define PCICFG_HIBYTE(n) ((uint8_t)(((uint16_t)(n) & 0xFF00)>> 8)) 81 #define PCICFG_LOBYTE(n) ((uint8_t)((uint16_t)(n) & 0x00FF)) 82 83 #define PCICFG_ROUND_UP(addr, gran) ((uintptr_t)((gran+addr-1)&(~(gran-1)))) 84 #define PCICFG_ROUND_DOWN(addr, gran) ((uintptr_t)((addr) & ~(gran-1))) 85 86 #define PCICFG_MEMGRAN 0x100000 87 #define PCICFG_IOGRAN 0x1000 88 #define PCICFG_4GIG_LIMIT 0xFFFFFFFFUL 89 #define CBCFG_MEMGRAN 0x1000 90 #define CBCFG_IOGRAN 0x4 91 92 #define PCICFG_MEM_MULT 4 93 #define PCICFG_IO_MULT 4 94 #define PCICFG_RANGE_LEN 2 /* Number of range entries */ 95 96 /* 97 * ISA node declaration structure. 98 */ 99 struct isa_node { 100 char *name; 101 char *compatible[5]; 102 char *type; 103 char *model; 104 uint16_t reg; 105 uint16_t span; 106 }; 107 108 struct cardbus_name_entry { 109 uint32_t class_code; 110 char *name; 111 int pil; 112 }; 113 114 struct cardbus_find_ctrl { 115 uint_t bus; 116 uint_t device; 117 uint_t function; 118 dev_info_t *dip; 119 }; 120 121 #define PCICFG_MAKE_REG_HIGH(busnum, devnum, funcnum, register)\ 122 (\ 123 ((ulong_t)(busnum & 0xff) << 16) |\ 124 ((ulong_t)(devnum & 0x1f) << 11) |\ 125 ((ulong_t)(funcnum & 0x7) << 8) |\ 126 ((ulong_t)(register & 0x3f))) 127 128 typedef struct cardbus_phdl cardbus_phdl_t; 129 130 struct cardbus_phdl { 131 132 dev_info_t *dip; /* Associated with the attach point */ 133 dev_info_t *res_dip; /* dip from which io/mem is allocated */ 134 cardbus_phdl_t *next; 135 136 uint64_t memory_base; /* Memory base for this attach point */ 137 uint64_t memory_last; 138 uint64_t memory_len; 139 uint32_t memory_gran; 140 uint32_t io_base; /* I/O base for this attach point */ 141 uint32_t io_last; 142 uint32_t io_len; 143 uint32_t io_gran; 144 145 int error; 146 uint_t highest_bus; /* Highest bus seen on the probe */ 147 ndi_ra_request_t mem_req; /* allocator request for memory */ 148 ndi_ra_request_t io_req; /* allocator request for I/O */ 149 }; 150 151 typedef struct { 152 dev_info_t *dip; /* Associated with the attach point */ 153 ddi_acc_handle_t handle; /* open handle on parent PCI config space */ 154 uint32_t io_base; /* I/O base for this attach point */ 155 int io_decode_reg; 156 } isa_phdl_t; 157 158 159 /* 160 * forward declarations for routines defined in this module (called here) 161 */ 162 static cardbus_phdl_t *cardbus_find_phdl(dev_info_t *dip); 163 static cardbus_phdl_t *cardbus_create_phdl(dev_info_t *dip); 164 static int cardbus_destroy_phdl(dev_info_t *dip); 165 static int cardbus_program_ap(dev_info_t *); 166 static void cardbus_topbridge_assign(dev_info_t *, cardbus_phdl_t *); 167 static int cardbus_bridge_ranges(dev_info_t *, cardbus_phdl_t *, 168 ddi_acc_handle_t); 169 static int cardbus_bridge_assign(dev_info_t *, void *); 170 static int cardbus_isa_bridge_ranges(dev_info_t *dip, cardbus_phdl_t *entry, 171 ddi_acc_handle_t handle); 172 static int cardbus_add_isa_reg(dev_info_t *, void *); 173 static int cardbus_allocate_chunk(dev_info_t *, uint8_t, uint8_t); 174 static int cardbus_free_chunk(dev_info_t *); 175 static void cardbus_setup_bridge(dev_info_t *, cardbus_phdl_t *, 176 ddi_acc_handle_t); 177 static void cardbus_update_bridge(dev_info_t *, cardbus_phdl_t *, 178 ddi_acc_handle_t); 179 static void cardbus_get_mem(dev_info_t *, cardbus_phdl_t *, uint32_t, 180 uint64_t *); 181 static void cardbus_get_io(dev_info_t *, cardbus_phdl_t *, uint32_t, 182 uint32_t *); 183 static int cardbus_sum_resources(dev_info_t *, void *); 184 static int cardbus_free_bridge_resources(dev_info_t *); 185 static int cardbus_free_device_resources(dev_info_t *); 186 static int cardbus_free_resources(dev_info_t *); 187 static int cardbus_probe_bridge(cbus_t *, dev_info_t *, uint_t, 188 uint_t, uint_t); 189 static int cardbus_probe_children(cbus_t *, dev_info_t *, uint_t, uint_t, 190 uint_t, uint8_t *); 191 static int cardbus_add_config_reg(dev_info_t *, uint_t, uint_t, uint_t); 192 static int cardbus_add_isa_node(cbus_t *, dev_info_t *, struct isa_node *); 193 static int cardbus_config_setup(dev_info_t *, ddi_acc_handle_t *); 194 static void cardbus_config_teardown(ddi_acc_handle_t *); 195 static void cardbus_reparent_children(dev_info_t *, dev_info_t *); 196 static int cardbus_update_assigned_prop(dev_info_t *, pci_regspec_t *); 197 static int cardbus_update_available_prop(dev_info_t *, uint32_t, 198 uint64_t, uint64_t); 199 static int cardbus_update_ranges_prop(dev_info_t *, cardbus_range_t *); 200 static int cardbus_update_reg_prop(dev_info_t *dip, uint32_t regvalue, 201 uint_t reg_offset); 202 static int cardbus_set_standard_props(dev_info_t *parent, dev_info_t *dip, 203 ddi_acc_handle_t config_handle); 204 static int cardbus_set_isa_props(dev_info_t *parent, dev_info_t *dip, 205 char *name, char *compat[]); 206 static int cardbus_set_busnode_props(dev_info_t *); 207 static int cardbus_set_busnode_isaprops(dev_info_t *); 208 static int cardbus_set_childnode_props(dev_info_t *dip, 209 ddi_acc_handle_t config_handle); 210 static void cardbus_set_bus_numbers(ddi_acc_handle_t config_handle, 211 uint_t primary, uint_t secondary); 212 static void enable_pci_isa_bridge(dev_info_t *dip, 213 ddi_acc_handle_t config_handle); 214 static void enable_pci_pci_bridge(dev_info_t *dip, 215 ddi_acc_handle_t config_handle); 216 static void enable_cardbus_bridge(dev_info_t *dip, 217 ddi_acc_handle_t config_handle); 218 static void disable_pci_pci_bridge(dev_info_t *dip, 219 ddi_acc_handle_t config_handle); 220 static void disable_cardbus_bridge(dev_info_t *dip, 221 ddi_acc_handle_t config_handle); 222 static void enable_cardbus_device(dev_info_t *, ddi_acc_handle_t); 223 static void disable_cardbus_device(ddi_acc_handle_t config_handle); 224 static void cardbus_force_boolprop(dev_info_t *dip, char *pname); 225 static void cardbus_force_intprop(dev_info_t *dip, char *pname, 226 int *pval, int len); 227 static void cardbus_force_stringprop(dev_info_t *dip, char *pname, 228 char *pval); 229 static void split_addr(char *, int *, int *); 230 #ifdef DEBUG 231 static void cardbus_dump_common_config(ddi_acc_handle_t config_handle); 232 static void cardbus_dump_device_config(ddi_acc_handle_t config_handle); 233 static void cardbus_dump_bridge_config(ddi_acc_handle_t config_handle, 234 uint8_t header_type); 235 static void cardbus_dump_config(ddi_acc_handle_t config_handle); 236 static void cardbus_dump_reg(dev_info_t *dip, const pci_regspec_t *regspec, 237 int nelems); 238 #endif 239 240 static cardbus_phdl_t *cardbus_phdl_list = NULL; 241 242 static struct cardbus_name_entry cardbus_class_lookup [] = { 243 { 0x001, "display", 9 }, 244 { 0x100, "scsi", 4 }, 245 { 0x101, "ide", 4 }, 246 { 0x102, "fdc", 4 }, 247 { 0x103, "ipi", 4 }, 248 { 0x104, "raid", 4 }, 249 { 0x200, "ethernet", 6 }, 250 { 0x201, "token-ring", 6 }, 251 { 0x202, "fddi", 6 }, 252 { 0x203, "atm", 6 }, 253 { 0x300, "display", 9 }, /* VGA card */ 254 { 0x380, "display", 9 }, /* other - for the Raptor Card */ 255 { 0x400, "video", 11 }, 256 { 0x401, "sound", 11 }, 257 { 0x500, "memory", 11 }, 258 { 0x501, "flash", 11 }, 259 { 0x600, "host", 11 }, 260 { 0x601, "isa", 11 }, 261 { 0x602, "eisa", 11 }, 262 { 0x603, "mca", 11 }, 263 { 0x604, "pci", 11 }, 264 { 0x605, "pcmcia", 11 }, 265 { 0x606, "nubus", 11 }, 266 { 0x607, "cardbus", 11 }, 267 { 0x680, NULL, 8 }, 268 { 0x700, "serial", 11 }, 269 { 0x701, "parallel", 6 }, 270 { 0x800, "interrupt-controller", 3 }, 271 { 0x801, "dma-controller", 3 }, 272 { 0x802, "timer", 3 }, 273 { 0x803, "rtc", 3 }, 274 { 0x900, "keyboard", 8 }, 275 { 0x901, "pen", 8 }, 276 { 0x902, "mouse", 8 }, 277 { 0xa00, "dock", 1 }, 278 { 0xb00, "cpu", 1 }, 279 { 0xc00, "firewire", 9 }, 280 { 0xc01, "access-bus", 4 }, 281 { 0xc02, "ssa", 4 }, 282 { 0xc03, "usb", 9 }, 283 { 0xc04, "fibre-channel", 6 }, 284 { 0, 0 } 285 }; 286 287 #ifndef _DONT_USE_1275_GENERIC_NAMES 288 static char *cardbus_get_class_name(uint32_t classcode); 289 #endif /* _DONT_USE_1275_GENERIC_NAMES */ 290 291 /* 292 * Reprogram ILINE with default value only if BIOS doesn't program it 293 */ 294 int 295 cardbus_validate_iline(dev_info_t *dip, ddi_acc_handle_t handle) 296 { 297 uint8_t intline = 0xff; 298 299 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 300 intline = pci_config_get8(handle, PCI_CONF_ILINE); 301 if ((intline == 0) || (intline == 0xff)) { 302 intline = ddi_getprop(DDI_DEV_T_ANY, dip, 303 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 304 "interrupt-line", 0xff); 305 if (intline == (uint8_t)0xff) { 306 intline = ddi_getprop(DDI_DEV_T_ANY, 307 ddi_get_parent(dip), 308 DDI_PROP_CANSLEEP /* |DDI_PROP_DONTPASS */, 309 "interrupt-line", 0xb); 310 } 311 312 pci_config_put8(handle, PCI_CONF_ILINE, intline); 313 } 314 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 315 "interrupt-line", intline); 316 } 317 return (intline); 318 } 319 320 /* 321 * This entry point is called to configure a device (and 322 * all its children) on the given bus. It is called when 323 * a new device is added to the PCI domain. This routine 324 * will create the device tree and program the devices 325 * registers. 326 */ 327 int 328 cardbus_configure(cbus_t *cbp) 329 { 330 uint_t bus; 331 int cardbus_dev, func; 332 dev_info_t *attach_point; 333 334 cardbus_err(cbp->cb_dip, 6, "cardbus_configure ()\n"); 335 336 bus = cardbus_primary_busno(cbp->cb_dip); 337 338 if (ndi_devi_alloc(cbp->cb_dip, DEVI_PSEUDO_NEXNAME, 339 (pnode_t)DEVI_SID_NODEID, 340 &attach_point) != NDI_SUCCESS) { 341 cardbus_err(cbp->cb_dip, 1, 342 "cardbus_configure(): Failed to alloc probe node\n"); 343 return (PCICFG_FAILURE); 344 } 345 346 /* 347 * Node name marks this node as the "attachment point". 348 */ 349 if (ndi_devi_set_nodename(attach_point, 350 "hp_attachment", 0) != NDI_SUCCESS) { 351 cardbus_err(cbp->cb_dip, 1, 352 "Failed to set nodename for attachment node\n"); 353 (void) ndi_devi_free(attach_point); 354 return (PCICFG_FAILURE); 355 } 356 357 cardbus_err(ddi_get_parent(attach_point), 8, 358 "Set bus type to cardbus\n"); 359 (void) ddi_prop_update_string(DDI_DEV_T_NONE, 360 ddi_get_parent(attach_point), PCM_DEVICETYPE, 361 "cardbus"); 362 363 split_addr(ddi_get_name_addr(cbp->cb_dip), &cardbus_dev, &func); 364 365 cardbus_err(attach_point, 8, 366 "Configuring [0x%x][0x%x][0x%x]\n", bus, cardbus_dev, func); 367 368 switch (cardbus_probe_bridge(cbp, attach_point, 369 bus, cardbus_dev, func)) { 370 case PCICFG_FAILURE: 371 cardbus_err(cbp->cb_dip, 4, 372 "configure failed: bus [0x%x] slot [0x%x] func [0x%x]\n", 373 bus, cardbus_dev, func); 374 goto cleanup; 375 case PCICFG_NODEVICE: 376 cardbus_err(cbp->cb_dip, 4, 377 "no device: bus [0x%x] slot [0x%x] func [0x%x]\n", 378 bus, cardbus_dev, func); 379 goto cleanup; 380 default: 381 cardbus_err(cbp->cb_dip, 9, 382 "configure: bus => [%d] slot => [%d] func => [%d]\n", 383 bus, cardbus_dev, func); 384 break; 385 } 386 387 if (cardbus_program_ap(cbp->cb_dip) == PCICFG_SUCCESS) { 388 (void) cardbus_reparent_children(attach_point, cbp->cb_dip); 389 (void) ndi_devi_free(attach_point); 390 cbp->cb_nex_ops->enable_intr(cbp->cb_dip); 391 return (PCICFG_SUCCESS); 392 } 393 394 cardbus_err(cbp->cb_dip, 1, "Failed to program devices\n"); 395 396 cleanup: 397 /* 398 * Clean up a partially created "probe state" tree. 399 * There are no resources allocated to the in the 400 * probe state. 401 */ 402 403 cardbus_err(cbp->cb_dip, 6, 404 "Look up device [0x%x] function [0x%x] to clean up\n", 405 cardbus_dev, func); 406 407 cardbus_err(cbp->cb_dip, 6, 408 "Cleaning up device [0x%x] function [0x%x]\n", 409 cardbus_dev, func); 410 411 /* 412 * If this was a bridge device it will have a 413 * probe handle - if not, no harm in calling this. 414 */ 415 (void) cardbus_destroy_phdl(cbp->cb_dip); 416 417 if (ddi_get_child(attach_point)) { 418 /* 419 * This will free up the node 420 */ 421 (void) ndi_devi_offline(ddi_get_child(attach_point), 422 NDI_UNCONFIG|NDI_DEVI_REMOVE); 423 } 424 (void) ndi_devi_free(attach_point); 425 426 return (PCICFG_FAILURE); 427 } 428 429 int 430 cardbus_unconfigure(cbus_t *cbp) 431 { 432 ddi_acc_handle_t config_handle; 433 dev_info_t *dip = cbp->cb_dip; 434 435 cbp->cb_nex_ops->disable_intr(dip); 436 if (pci_config_setup(dip, &config_handle) == DDI_SUCCESS) { 437 disable_cardbus_bridge(dip, config_handle); 438 (void) pci_config_teardown(&config_handle); 439 } else { 440 cardbus_err(dip, 1, 441 "cardbus_unconfigure(): Failed to setup config space\n"); 442 } 443 444 (void) cardbus_free_chunk(dip); 445 cardbus_err(dip, 6, 446 "cardbus_unconfigure: calling cardbus_free_bridge_resources\n"); 447 (void) cardbus_free_bridge_resources(dip); 448 449 return (PCICFG_SUCCESS); 450 } 451 452 int 453 cardbus_teardown_device(dev_info_t *dip) 454 { 455 /* 456 * Free up resources associated with 'dip' 457 */ 458 459 if (cardbus_free_resources(dip) != PCICFG_SUCCESS) { 460 cardbus_err(dip, 1, 461 "cardbus_teardown_device: Failed to free resources\n"); 462 return (PCICFG_FAILURE); 463 } 464 465 if (ndi_devi_offline(dip, NDI_DEVI_REMOVE) != NDI_SUCCESS) { 466 cardbus_err(dip, 1, 467 "cardbus_teardown_device: " 468 "Failed to offline and remove node\n"); 469 return (PCICFG_FAILURE); 470 } 471 472 return (PCICFG_SUCCESS); 473 } 474 475 /* 476 * Get the primary pci bus number. This should be the lowest number 477 * in the bus-range property of our parent. 478 */ 479 int 480 cardbus_primary_busno(dev_info_t *dip) 481 { 482 int len, rval; 483 char bus_type[16] = "(unknown)"; 484 dev_info_t *par = ddi_get_parent(dip); 485 cardbus_bus_range_t *bus_range; 486 487 ASSERT(strcmp(ddi_driver_name(dip), "pcic") == 0); 488 len = sizeof (bus_type); 489 if ((ddi_prop_op(DDI_DEV_T_ANY, par, PROP_LEN_AND_VAL_BUF, 490 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, 491 "device_type", 492 (caddr_t)&bus_type, &len) == DDI_SUCCESS)) { 493 ASSERT((strcmp(bus_type, "pci") == 0) || 494 (strcmp(bus_type, "cardbus") == 0)); 495 if (ddi_getlongprop(DDI_DEV_T_ANY, par, 0, "bus-range", 496 (caddr_t)&bus_range, &len) == DDI_PROP_SUCCESS) { 497 cardbus_err(dip, 9, 498 "cardbus_primary_busno: bus range is %d to %d\n", 499 bus_range->lo, bus_range->hi); 500 rval = (int)bus_range->lo; 501 kmem_free((caddr_t)bus_range, len); 502 return (rval); 503 } 504 } 505 506 cardbus_err(dip, 2, 507 "cardbus_primary_busno: Not a pci device or no bus-range\n"); 508 return (-1); 509 } 510 511 static cardbus_phdl_t * 512 cardbus_find_phdl(dev_info_t *dip) 513 { 514 cardbus_phdl_t *entry; 515 516 mutex_enter(&cardbus_list_mutex); 517 for (entry = cardbus_phdl_list; entry != NULL; entry = entry->next) { 518 if (entry->dip == dip) { 519 mutex_exit(&cardbus_list_mutex); 520 return (entry); 521 } 522 } 523 mutex_exit(&cardbus_list_mutex); 524 525 /* 526 * Did'nt find entry - create one 527 */ 528 return (cardbus_create_phdl(dip)); 529 } 530 531 static cardbus_phdl_t * 532 cardbus_create_phdl(dev_info_t *dip) 533 { 534 cardbus_phdl_t *new; 535 536 new = (cardbus_phdl_t *)kmem_zalloc(sizeof (cardbus_phdl_t), KM_SLEEP); 537 538 new->dip = dip; 539 new->io_gran = CBCFG_IOGRAN; 540 new->memory_gran = CBCFG_MEMGRAN; 541 mutex_enter(&cardbus_list_mutex); 542 new->next = cardbus_phdl_list; 543 cardbus_phdl_list = new; 544 mutex_exit(&cardbus_list_mutex); 545 546 return (new); 547 } 548 549 static int 550 cardbus_destroy_phdl(dev_info_t *dip) 551 { 552 cardbus_phdl_t *entry; 553 cardbus_phdl_t *follow = NULL; 554 ra_return_t res; 555 556 mutex_enter(&cardbus_list_mutex); 557 for (entry = cardbus_phdl_list; entry != NULL; follow = entry, 558 entry = entry->next) { 559 if (entry->dip == dip) { 560 if (entry == cardbus_phdl_list) { 561 cardbus_phdl_list = entry->next; 562 } else { 563 follow->next = entry->next; 564 } 565 /* 566 * If this entry has any allocated memory 567 * or IO space associated with it, that 568 * must be freed up. 569 */ 570 if (entry->memory_len > 0) { 571 res.ra_addr_lo = entry->memory_base; 572 res.ra_len = entry->memory_len; 573 (void) pcmcia_free_mem(entry->res_dip, &res); 574 #ifdef _LP64 575 cardbus_err(dip, 8, 576 "cardbus_destroy_phdl: " 577 "MEMORY BASE = [0x%lx] length [0x%lx]\n", 578 entry->memory_base, entry->memory_len); 579 #else 580 cardbus_err(dip, 8, 581 "cardbus_destroy_phdl: " 582 "MEMORY BASE = [0x%llx] length [0x%llx]\n", 583 entry->memory_base, entry->memory_len); 584 #endif 585 } 586 if (entry->io_len > 0) { 587 res.ra_addr_lo = entry->io_base; 588 res.ra_len = entry->io_len; 589 (void) pcmcia_free_io(entry->res_dip, &res); 590 cardbus_err(dip, 8, 591 "cardbus_destroy_phdl: " 592 "IO BASE = [0x%x] length [0x%x]\n", 593 entry->io_base, entry->io_len); 594 } 595 /* 596 * Destroy this entry 597 */ 598 kmem_free((caddr_t)entry, sizeof (cardbus_phdl_t)); 599 mutex_exit(&cardbus_list_mutex); 600 return (PCICFG_SUCCESS); 601 } 602 } 603 604 mutex_exit(&cardbus_list_mutex); 605 606 /* 607 * Didn't find the entry 608 */ 609 return (PCICFG_FAILURE); 610 } 611 612 static int 613 cardbus_program_ap(dev_info_t *dip) 614 { 615 cardbus_phdl_t *phdl; 616 uint8_t header_type, sec_bus; 617 ddi_acc_handle_t handle; 618 619 if (pci_config_setup(dip, &handle) != DDI_SUCCESS) { 620 cardbus_err(dip, 1, 621 "cardbus_program_ap: Failed to map config space!\n"); 622 return (PCICFG_FAILURE); 623 } 624 625 header_type = pci_config_get8(handle, PCI_CONF_HEADER); 626 sec_bus = pci_config_get8(handle, PCI_BCNF_SECBUS); 627 628 cardbus_err(dip, 6, 629 "cardbus_program_ap (header_type=0x%x)\n", header_type); 630 (void) pci_config_teardown(&handle); 631 632 /* 633 * Header type two is PCI to Cardbus bridge, see page 43 of the 634 * CL-PD6832 data sheet 635 */ 636 switch (header_type & PCI_HEADER_TYPE_M) { 637 case PCI_HEADER_CARDBUS: 638 cardbus_err(dip, 8, 639 "cardbus_program_ap calling cardbus_allocate_chunk\n"); 640 if (cardbus_allocate_chunk(dip, 641 header_type & PCI_HEADER_TYPE_M, 642 sec_bus) != PCICFG_SUCCESS) { 643 cardbus_err(dip, 1, 644 "cardbus_program_ap: " 645 "Not enough memory to hotplug\n"); 646 (void) cardbus_destroy_phdl(dip); 647 return (PCICFG_FAILURE); 648 } 649 650 cardbus_err(dip, 8, 651 "cardbus_program_ap calling cardbus_find_phdl\n"); 652 phdl = cardbus_find_phdl(dip); 653 ASSERT(phdl); 654 655 if (phdl == NULL) { 656 cardbus_err(dip, 1, "cardbus_find_phdl failed\n"); 657 return (PCICFG_FAILURE); 658 } 659 phdl->error = PCICFG_SUCCESS; 660 cardbus_err(dip, 8, 661 "cardbus_program_ap calling cardbus_topbridge_assign\n"); 662 cardbus_topbridge_assign(dip, phdl); 663 664 if (phdl->error != PCICFG_SUCCESS) { 665 cardbus_err(dip, 1, "Problem assigning bridge\n"); 666 (void) cardbus_destroy_phdl(dip); 667 return (phdl->error); 668 } 669 break; 670 671 default: 672 return (PCICFG_FAILURE); 673 } 674 675 return (PCICFG_SUCCESS); 676 } 677 678 static void 679 cardbus_topbridge_assign(dev_info_t *dip, cardbus_phdl_t *entry) 680 { 681 ddi_acc_handle_t handle; 682 uint8_t header_type; 683 684 cardbus_err(dip, 6, "cardbus_topbridge_assign\n"); 685 686 if (pci_config_setup(dip, &handle) != DDI_SUCCESS) { 687 cardbus_err(dip, 1, 688 "cardbus_topbridge_bridge_assign: " 689 "Failed to map config space!\n"); 690 return; 691 } 692 693 header_type = pci_config_get8(handle, 694 PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 695 696 /* cardbus bridge is the same as PCI-PCI bridge */ 697 ASSERT((header_type == PCI_HEADER_PPB) || 698 (header_type == PCI_HEADER_CARDBUS)); 699 700 (void) cardbus_bridge_ranges(dip, entry, handle); 701 702 (void) pci_config_teardown(&handle); 703 } 704 705 static int 706 cardbus_bridge_ranges(dev_info_t *dip, cardbus_phdl_t *entry, 707 ddi_acc_handle_t handle) 708 { 709 cardbus_range_t range[PCICFG_RANGE_LEN]; 710 int bus_range[2]; 711 int count; 712 int i; 713 714 cardbus_err(dip, 8, "cardbus_bridge_ranges\n"); 715 716 bzero((caddr_t)range, sizeof (cardbus_range_t) * PCICFG_RANGE_LEN); 717 718 (void) cardbus_setup_bridge(dip, entry, handle); 719 720 range[0].child_hi = range[0].parent_hi |= (PCI_REG_REL_M | PCI_ADDR_IO); 721 range[0].child_lo = range[0].parent_lo = entry->io_last; 722 range[1].child_hi = range[1].parent_hi |= (PCI_REG_REL_M | 723 PCI_ADDR_MEM32); 724 range[1].child_lo = range[1].parent_lo = entry->memory_last; 725 726 ndi_devi_enter(dip, &count); 727 ddi_walk_devs(ddi_get_child(dip), cardbus_bridge_assign, (void *)entry); 728 ndi_devi_exit(dip, count); 729 730 (void) cardbus_update_bridge(dip, entry, handle); 731 732 bus_range[0] = pci_config_get8(handle, PCI_BCNF_SECBUS); 733 bus_range[1] = pci_config_get8(handle, PCI_BCNF_SUBBUS); 734 735 cardbus_err(dip, 8, 736 "Set up bus-range property to %u->%u\n", 737 bus_range[0], bus_range[1]); 738 739 if ((i = ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 740 "bus-range", 741 bus_range, 2)) != DDI_SUCCESS) { 742 743 if (i == DDI_PROP_NOT_FOUND) { 744 cardbus_err(dip, 8, 745 "Create bus-range property, %u->%u\n", 746 bus_range[0], bus_range[1]); 747 i = ddi_prop_create(DDI_DEV_T_NONE, dip, 748 DDI_PROP_CANSLEEP, 749 "bus-range", (caddr_t)bus_range, 750 sizeof (bus_range)); 751 } 752 753 if (i != DDI_PROP_SUCCESS) { 754 cardbus_err(dip, 1, 755 "Failed to set bus-range property, %u->%u (%d)\n", 756 bus_range[0], bus_range[1], i); 757 entry->error = PCICFG_FAILURE; 758 return (DDI_WALK_TERMINATE); 759 } 760 } 761 762 if (entry->io_len > 0) { 763 range[0].size_lo = entry->io_last - entry->io_base; 764 if (cardbus_update_ranges_prop(dip, &range[0])) { 765 cardbus_err(dip, 1, "Failed to update ranges (i/o)\n"); 766 entry->error = PCICFG_FAILURE; 767 return (DDI_WALK_TERMINATE); 768 } 769 } 770 if (entry->memory_len > 0) { 771 range[1].size_lo = entry->memory_last - entry->memory_base; 772 if (cardbus_update_ranges_prop(dip, &range[1])) { 773 cardbus_err(dip, 1, 774 "Failed to update ranges (memory)\n"); 775 entry->error = PCICFG_FAILURE; 776 return (DDI_WALK_TERMINATE); 777 } 778 } 779 780 return (DDI_WALK_PRUNECHILD); 781 } 782 static int 783 cardbus_bridge_assign(dev_info_t *dip, void *hdl) 784 { 785 ddi_acc_handle_t handle; 786 pci_regspec_t *reg; 787 int length; 788 int rcount; 789 int i; 790 int offset; 791 uint64_t mem_answer; 792 uint32_t io_answer, request; 793 uint8_t header_type, base_class; 794 cardbus_phdl_t *entry = (cardbus_phdl_t *)hdl; 795 796 /* 797 * Ignore the attachment point and pcs. 798 */ 799 if (strcmp(ddi_binding_name(dip), "hp_attachment") == 0 || 800 strcmp(ddi_binding_name(dip), "pcs") == 0) { 801 cardbus_err(dip, 8, "cardbus_bridge_assign: Ignoring\n"); 802 return (DDI_WALK_CONTINUE); 803 } 804 805 806 cardbus_err(dip, 6, "cardbus_bridge_assign\n"); 807 808 if (entry == NULL) { 809 cardbus_err(dip, 1, "Failed to get entry\n"); 810 return (DDI_WALK_TERMINATE); 811 } 812 if (cardbus_config_setup(dip, &handle) != DDI_SUCCESS) { 813 cardbus_err(dip, 1, 814 "cardbus_bridge_assign: Failed to map config space!\n"); 815 entry->error = PCICFG_FAILURE; 816 return (DDI_WALK_TERMINATE); 817 } 818 819 header_type = pci_config_get8(handle, PCI_CONF_HEADER) & 820 PCI_HEADER_TYPE_M; 821 base_class = pci_config_get8(handle, PCI_CONF_BASCLASS); 822 823 /* 824 * This function is not called for the top bridge and we are 825 * not enumerating down a further cardbus interface yet! 826 */ 827 if (base_class == PCI_CLASS_BRIDGE) { 828 uint8_t sub_class; 829 830 sub_class = pci_config_get8(handle, PCI_CONF_SUBCLASS); 831 832 switch (sub_class) { 833 case PCI_BRIDGE_PCI: 834 if (header_type == PCI_HEADER_PPB) { 835 i = cardbus_bridge_ranges(dip, entry, handle); 836 (void) cardbus_config_teardown(&handle); 837 return (i); 838 } 839 goto bad_device; 840 841 case PCI_BRIDGE_ISA: 842 i = cardbus_isa_bridge_ranges(dip, entry, handle); 843 (void) cardbus_config_teardown(&handle); 844 return (i); 845 846 case PCI_BRIDGE_CARDBUS: 847 /* 848 * Fall through, there should be at least one register 849 * set for this. 850 */ 851 break; 852 853 case PCI_BRIDGE_OTHER: 854 default: 855 break; 856 } 857 } 858 859 #ifdef sparc 860 /* 861 * If there is an interrupt pin set program 862 * interrupt line with default values. 863 */ 864 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 865 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 866 } 867 #else 868 (void) cardbus_validate_iline(dip, handle); 869 #endif 870 871 /* 872 * A single device (under a bridge). 873 * For each "reg" property with a length, allocate memory 874 * and program the base registers. 875 */ 876 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 877 DDI_PROP_DONTPASS, "reg", (caddr_t)®, 878 &length) != DDI_PROP_SUCCESS) { 879 cardbus_err(dip, 1, "Failed to read reg property\n"); 880 entry->error = PCICFG_FAILURE; 881 (void) cardbus_config_teardown(&handle); 882 return (DDI_WALK_TERMINATE); 883 } 884 885 rcount = length / sizeof (pci_regspec_t); 886 cardbus_err(dip, 9, "rcount = %d\n", rcount); 887 888 for (i = 0; i < rcount; i++) { 889 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) { 890 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); 891 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { 892 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 893 894 (void) cardbus_get_mem(ddi_get_parent(dip), 895 entry, reg[i].pci_size_low, &mem_answer); 896 ASSERT(!PCICFG_HIADDR(mem_answer)); 897 pci_config_put32(handle, offset, 898 PCICFG_LOADDR(mem_answer)); 899 pci_config_put32(handle, offset + 4, 900 PCICFG_HIADDR(mem_answer)); 901 cardbus_err(dip, 8, 902 "REGISTER (64)LO [0x%x] ----> [0x%02x]\n", 903 pci_config_get32(handle, offset), offset); 904 cardbus_err(dip, 8, 905 "REGISTER (64)HI [0x%x] ----> [0x%02x]\n", 906 pci_config_get32(handle, offset+4), 907 offset+4); 908 reg[i].pci_phys_low = PCICFG_HIADDR(mem_answer); 909 reg[i].pci_phys_mid = PCICFG_LOADDR(mem_answer); 910 break; 911 912 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 913 /* allocate memory space from the allocator */ 914 915 (void) cardbus_get_mem(ddi_get_parent(dip), 916 entry, reg[i].pci_size_low, &mem_answer); 917 pci_config_put32(handle, offset, 0xffffffff); 918 request = pci_config_get32(handle, offset); 919 920 pci_config_put32(handle, offset, 921 (uint32_t)mem_answer); 922 reg[i].pci_phys_low = (uint32_t)mem_answer; 923 reg[i].pci_phys_mid = 0; 924 if (((PCI_BASE_TYPE_M & request) == 925 PCI_BASE_TYPE_ALL) && 926 ((PCI_BASE_SPACE_M & request) == 927 PCI_BASE_SPACE_MEM)) { 928 cardbus_err(dip, 8, 929 "REGISTER (64)LO [0x%x] ----> " 930 "[0x%02x]\n", 931 pci_config_get32(handle, offset), 932 offset); 933 pci_config_put32(handle, 934 offset + 4, 0); 935 cardbus_err(dip, 8, 936 "REGISTER (64)HI [0x%x] ----> " 937 "[0x%02x]\n", 938 pci_config_get32(handle, offset+4), 939 offset+4); 940 } else { 941 cardbus_err(dip, 8, 942 "REGISTER (32)LO [0x%x] ----> " 943 "[0x%02x]\n", 944 pci_config_get32(handle, offset), 945 offset); 946 } 947 break; 948 949 case PCI_REG_ADDR_G(PCI_ADDR_IO): 950 /* allocate I/O space from the allocator */ 951 952 (void) cardbus_get_io(ddi_get_parent(dip), 953 entry, reg[i].pci_size_low, &io_answer); 954 pci_config_put32(handle, offset, io_answer); 955 cardbus_err(dip, 8, 956 "REGISTER (I/O)LO [0x%x] ----> [0x%02x]\n", 957 pci_config_get32(handle, offset), offset); 958 reg[i].pci_phys_low = io_answer; 959 break; 960 961 default: 962 cardbus_err(dip, 1, "Unknown register type\n"); 963 kmem_free(reg, length); 964 (void) cardbus_config_teardown(&handle); 965 entry->error = PCICFG_FAILURE; 966 return (DDI_WALK_TERMINATE); 967 } /* switch */ 968 969 /* 970 * Now that memory locations are assigned, 971 * update the assigned address property. 972 */ 973 if (cardbus_update_assigned_prop(dip, 974 ®[i]) != PCICFG_SUCCESS) { 975 kmem_free(reg, length); 976 (void) cardbus_config_teardown(&handle); 977 entry->error = PCICFG_FAILURE; 978 return (DDI_WALK_TERMINATE); 979 } 980 } 981 } 982 kmem_free(reg, length); 983 enable_cardbus_device(dip, handle); 984 #ifdef CARDBUS_DEBUG 985 if (cardbus_debug >= 9) { 986 cardbus_dump_config(handle); 987 } 988 #endif 989 bad_device: 990 (void) cardbus_config_teardown(&handle); 991 return (DDI_WALK_CONTINUE); 992 } 993 994 static int 995 cardbus_isa_bridge_ranges(dev_info_t *dip, cardbus_phdl_t *entry, 996 ddi_acc_handle_t handle) 997 { 998 struct ebus_pci_rangespec range; 999 int count; 1000 pci_regspec_t *reg; 1001 int length; 1002 int rcount; 1003 uint32_t io_answer = 0xffffffff; 1004 isa_phdl_t isa_phdl; 1005 int i; 1006 1007 cardbus_err(dip, 8, "cardbus_isa_bridge_ranges\n"); 1008 1009 bzero((caddr_t)&range, sizeof (range)); 1010 1011 #ifdef sparc 1012 /* 1013 * If there is an interrupt pin set program 1014 * interrupt line with default values. 1015 */ 1016 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 1017 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 1018 } 1019 #else 1020 (void) cardbus_validate_iline(dip, handle); 1021 #endif 1022 1023 /* 1024 * For each "reg" property with a length, allocate memory. 1025 */ 1026 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 1027 DDI_PROP_DONTPASS, "reg", (caddr_t)®, 1028 &length) != DDI_PROP_SUCCESS) { 1029 cardbus_err(dip, 1, "Failed to read reg property\n"); 1030 entry->error = PCICFG_FAILURE; 1031 return (DDI_WALK_TERMINATE); 1032 } 1033 1034 rcount = length / sizeof (pci_regspec_t); 1035 1036 for (i = 0; i < rcount; i++) { 1037 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) { 1038 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { 1039 case PCI_REG_ADDR_G(PCI_ADDR_IO): 1040 /* allocate I/O space from the allocator */ 1041 1042 (void) cardbus_get_io(ddi_get_parent(dip), 1043 entry, reg[i].pci_size_low, &io_answer); 1044 cardbus_err(dip, 8, 1045 "ISA (I/O)LO ----> [0x%x]\n", io_answer); 1046 reg[i].pci_phys_low = io_answer; 1047 range.phys_hi = 0; 1048 range.phys_low = io_answer; 1049 range.par_phys_hi = reg[i].pci_phys_hi | 1050 PCI_REG_REL_M; 1051 range.par_phys_low = reg[i].pci_phys_low; 1052 range.par_phys_mid = reg[i].pci_phys_mid; 1053 range.rng_size = reg[i].pci_size_low; 1054 i = rcount; 1055 break; 1056 1057 default: 1058 cardbus_err(dip, 1, "Unknown register type\n"); 1059 kmem_free(reg, length); 1060 (void) cardbus_config_teardown(&handle); 1061 entry->error = PCICFG_FAILURE; 1062 return (DDI_WALK_TERMINATE); 1063 } /* switch */ 1064 } 1065 } 1066 kmem_free(reg, length); 1067 1068 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1069 dip, "ranges", (int *)&range, 1070 sizeof (range)/sizeof (int)); 1071 if (io_answer != 0xffffffff) { 1072 isa_phdl.dip = dip; 1073 isa_phdl.handle = handle; 1074 isa_phdl.io_base = io_answer; 1075 isa_phdl.io_decode_reg = 0x58; /* Pos decoded IO space 0 reg */ 1076 /* i_ndi_block_device_tree_changes(&count); */ 1077 ndi_devi_enter(dip, &count); 1078 ddi_walk_devs(ddi_get_child(dip), 1079 cardbus_add_isa_reg, (void *)&isa_phdl); 1080 /* i_ndi_allow_device_tree_changes(count); */ 1081 ndi_devi_exit(dip, count); 1082 } 1083 return (DDI_WALK_PRUNECHILD); 1084 } 1085 1086 /* 1087 * This is specific to ITE8888 chip. 1088 */ 1089 static int 1090 cardbus_add_isa_reg(dev_info_t *dip, void *arg) 1091 { 1092 uint32_t io_reg = 0; 1093 int length; 1094 uint32_t reg[3], *breg; 1095 isa_phdl_t *phdl; 1096 uint8_t sz; 1097 1098 phdl = (isa_phdl_t *)arg; 1099 cardbus_err(dip, 6, 1100 "cardbus_add_isa_reg, base 0x%x\n", phdl->io_base); 1101 1102 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 1103 DDI_PROP_DONTPASS, "basereg", (caddr_t)&breg, 1104 &length) != DDI_PROP_SUCCESS) { 1105 return (DDI_WALK_CONTINUE); 1106 } 1107 1108 if ((length / sizeof (reg)) < 1) { 1109 kmem_free(breg, length); 1110 return (DDI_WALK_CONTINUE); 1111 } 1112 1113 /* 1114 * Add the "reg" property. 1115 */ 1116 reg[0] = 0; 1117 reg[1] = breg[1] + phdl->io_base; 1118 reg[2] = breg[2]; 1119 1120 /* 1121 * Generate the postive IO decode register setting. 1122 */ 1123 for (sz = 0; sz < 8; sz++) 1124 if ((1<<sz) >= breg[2]) { 1125 io_reg = breg[1] 1126 | (1uL <<31) /* Enable */ 1127 | (2uL <<29) /* Medium speed */ 1128 | (1uL <<28) /* Aliase enable, */ 1129 /* Don't care A[15:10] */ 1130 | (sz<<24); /* Size code */ 1131 break; 1132 } 1133 1134 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1135 "reg", (int *)reg, 3); 1136 (void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "basereg"); 1137 1138 if (io_reg) { 1139 pci_config_put32(phdl->handle, phdl->io_decode_reg, io_reg); 1140 cardbus_err(dip, 6, 1141 "cardbus_add_isa_reg: I/O decode reg (0x%x) set to 0x%x\n", 1142 phdl->io_decode_reg, 1143 pci_config_get32(phdl->handle, phdl->io_decode_reg)); 1144 phdl->io_decode_reg += sizeof (io_reg); 1145 } else 1146 cardbus_err(dip, 1, 1147 "cardbus_add_isa_reg: register size (0x%x) too large\n", 1148 breg[2]); 1149 kmem_free(breg, length); 1150 return (DDI_WALK_CONTINUE); 1151 } 1152 1153 /* 1154 * In case we want to ensure that some space is allocated to the 1155 * device tree below the cardbus bridge. 1156 * This is only necessary if there is a device that needs to allocate 1157 * resource below us. This can happen if there is another cardbus/PCMCIA 1158 * bridge downstream. 1159 */ 1160 static uint32_t cardbus_min_spare_mem = 0; 1161 static uint32_t cardbus_min_spare_io = 0; 1162 1163 /* 1164 * The "dip" passed to this routine is assumed to be 1165 * the device at the attachment point. Currently it is 1166 * assumed to be a bridge. 1167 */ 1168 static int 1169 cardbus_allocate_chunk(dev_info_t *dip, uint8_t type, uint8_t sec_bus) 1170 { 1171 cardbus_phdl_t *phdl; 1172 ndi_ra_request_t *mem_request; 1173 ndi_ra_request_t *io_request; 1174 ra_return_t res; 1175 int count; 1176 1177 /* 1178 * This should not find an existing entry - so 1179 * it will create a new one. 1180 */ 1181 phdl = cardbus_find_phdl(dip); 1182 ASSERT(phdl); 1183 1184 mem_request = &phdl->mem_req; 1185 io_request = &phdl->io_req; 1186 1187 /* 1188 * Set highest_bus here. 1189 * Otherwise if we don't find another bridge 1190 * this never gets set. 1191 */ 1192 phdl->highest_bus = sec_bus; 1193 1194 /* 1195 * From this point in the tree - walk the devices, 1196 * The function passed in will read and "sum" up 1197 * the memory and I/O requirements and put them in 1198 * structure "phdl". 1199 */ 1200 phdl->error = PCICFG_SUCCESS; 1201 ndi_devi_enter(dip, &count); 1202 ddi_walk_devs(ddi_get_child(dip), cardbus_sum_resources, (void *)phdl); 1203 ndi_devi_exit(dip, count); 1204 1205 if (phdl->error != PCICFG_SUCCESS) { 1206 cmn_err(CE_WARN, "Failure summing resources\n"); 1207 return (phdl->error); 1208 } 1209 1210 /* 1211 * Call into the memory allocator with the request. 1212 * Record the addresses returned in the phdl 1213 */ 1214 #ifdef _LP64 1215 cardbus_err(dip, 8, 1216 "AP requires [0x%lx] bytes of memory space, alligned 0x%x\n", 1217 mem_request->ra_len, phdl->memory_gran); 1218 cardbus_err(dip, 8, 1219 "AP requires [0x%lx] bytes of I/O space, alligned 0x%x\n", 1220 io_request->ra_len, phdl->io_gran); 1221 #else 1222 cardbus_err(dip, 8, 1223 "AP requires [0x%llx] bytes of memory space, alligned 0x%x\n", 1224 mem_request->ra_len, phdl->memory_gran); 1225 cardbus_err(dip, 8, 1226 "AP requires [0x%llx] bytes of I/O space, alligned 0x%x\n", 1227 io_request->ra_len, phdl->io_gran); 1228 #endif 1229 1230 ASSERT(type == PCI_HEADER_CARDBUS); 1231 1232 mem_request->ra_align_mask = phdl->memory_gran - 1; 1233 io_request->ra_align_mask = phdl->io_gran - 1; 1234 phdl->res_dip = (dev_info_t *)-1; 1235 1236 mem_request->ra_len += cardbus_min_spare_mem; 1237 if (mem_request->ra_len) { 1238 mem_request->ra_len = PCICFG_ROUND_UP( 1239 mem_request->ra_len, 1240 phdl->memory_gran); 1241 #ifdef _LP64 1242 cardbus_err(dip, 8, 1243 "cardbus_allocate_chunk: ndi_ra_alloc 0x%lx bytes\n", 1244 mem_request->ra_len); 1245 #else 1246 cardbus_err(dip, 8, 1247 "cardbus_allocate_chunk: ndi_ra_alloc 0x%llx bytes\n", 1248 mem_request->ra_len); 1249 #endif 1250 1251 if (pcmcia_alloc_mem(dip, mem_request, &res, 1252 &phdl->res_dip) != NDI_SUCCESS) { 1253 cmn_err(CE_WARN, "Failed to allocate memory for %s\n", 1254 ddi_driver_name(dip)); 1255 return (PCICFG_FAILURE); 1256 } 1257 1258 phdl->memory_base = phdl->memory_last = res.ra_addr_lo; 1259 phdl->memory_len = res.ra_len; 1260 } 1261 1262 io_request->ra_len += cardbus_min_spare_io; 1263 if (io_request->ra_len) { 1264 1265 #if defined(__x86) 1266 io_request->ra_boundbase = 0x1000; 1267 io_request->ra_boundlen = 0xefff; 1268 #else 1269 io_request->ra_boundbase = 0; 1270 io_request->ra_boundlen = PCICFG_4GIG_LIMIT; 1271 #endif 1272 io_request->ra_flags |= NDI_RA_ALLOC_BOUNDED; 1273 io_request->ra_len = PCICFG_ROUND_UP(io_request->ra_len, 1274 phdl->io_gran); 1275 io_request->ra_align_mask = max(PCICFG_IOGRAN, 1276 phdl->io_gran) - 1; 1277 1278 if (pcmcia_alloc_io(dip, io_request, &res, 1279 &phdl->res_dip) != NDI_SUCCESS) { 1280 cmn_err(CE_WARN, "Failed to allocate I/O space " 1281 "for %s\n", ddi_driver_name(dip)); 1282 if (mem_request->ra_len) { 1283 res.ra_addr_lo = phdl->memory_base; 1284 res.ra_len = phdl->memory_len; 1285 (void) pcmcia_free_mem(phdl->res_dip, &res); 1286 phdl->memory_len = phdl->io_len = 0; 1287 } 1288 return (PCICFG_FAILURE); 1289 } 1290 1291 phdl->io_base = phdl->io_last = (uint32_t)res.ra_addr_lo; 1292 phdl->io_len = (uint32_t)res.ra_len; 1293 } 1294 1295 #ifdef _LP64 1296 cardbus_err(dip, 6, 1297 "MEMORY BASE = [0x%lx] length [0x%lx]\n", 1298 phdl->memory_base, phdl->memory_len); 1299 #else 1300 cardbus_err(dip, 6, 1301 "MEMORY BASE = [0x%llx] length [0x%llx]\n", 1302 phdl->memory_base, phdl->memory_len); 1303 #endif 1304 cardbus_err(dip, 6, 1305 "IO BASE = [0x%x] length [0x%x]\n", 1306 phdl->io_base, phdl->io_len); 1307 1308 return (PCICFG_SUCCESS); 1309 } 1310 1311 static int 1312 cardbus_free_chunk(dev_info_t *dip) 1313 { 1314 uint_t *bus; 1315 int k; 1316 1317 cardbus_err(dip, 6, "cardbus_free_chunk\n"); 1318 1319 (void) cardbus_destroy_phdl(dip); 1320 1321 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 1322 DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus, 1323 &k) != DDI_PROP_SUCCESS) { 1324 cardbus_err(dip, 1, 1325 "cardbus_free_chunk: Failed to read bus-range property\n"); 1326 return (PCICFG_FAILURE); 1327 } 1328 1329 cardbus_err(dip, 6, 1330 "cardbus_free_chunk: Freeing bus [%d] range [%d]\n", 1331 bus[0], bus[1] - bus[0] + 1); 1332 1333 if (ndi_ra_free(dip, 1334 (uint64_t)bus[0], (uint64_t)(bus[1] - bus[0] + 1), 1335 NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS) != NDI_SUCCESS) { 1336 cardbus_err(dip, 1, 1337 "cardbus_free_chunk: Failed to free bus numbers\n"); 1338 1339 kmem_free(bus, k); 1340 return (PCICFG_FAILURE); 1341 } 1342 1343 kmem_free(bus, k); 1344 return (PCICFG_SUCCESS); 1345 } 1346 1347 /* 1348 * Put bridge registers into initial state 1349 */ 1350 static void 1351 cardbus_setup_bridge(dev_info_t *dip, cardbus_phdl_t *entry, 1352 ddi_acc_handle_t handle) 1353 { 1354 uint8_t header_type = pci_config_get8(handle, PCI_CONF_HEADER); 1355 1356 #ifdef _LP64 1357 cardbus_err(NULL, 6, 1358 "cardbus_setup_bridge: " 1359 "highest bus %d, mem_last 0x%lx, io_last 0x%x\n", 1360 entry->highest_bus, entry->memory_last, entry->io_last); 1361 #else 1362 cardbus_err(NULL, 6, 1363 "cardbus_setup_bridge: " 1364 "highest bus %d, mem_last 0x%llx, io_last 0x%x\n", 1365 entry->highest_bus, entry->memory_last, entry->io_last); 1366 #endif 1367 1368 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) { 1369 uint32_t uval; 1370 1371 /* 1372 * The highest bus seen during probing is 1373 * the max-subordinate bus 1374 */ 1375 pci_config_put8(handle, PCI_BCNF_SUBBUS, entry->highest_bus); 1376 1377 uval = PCICFG_ROUND_UP(entry->memory_last, PCICFG_MEMGRAN); 1378 if (uval != entry->memory_last) { 1379 #ifdef _LP64 1380 cardbus_err(dip, 8, 1381 "Adding [0x%lx] before bridge (mem)\n", 1382 uval - entry->memory_last); 1383 #else 1384 cardbus_err(dip, 8, 1385 "Adding [0x%llx] before bridge (mem)\n", 1386 uval - entry->memory_last); 1387 #endif 1388 (void) cardbus_get_mem(ddi_get_parent(dip), entry, 1389 uval - entry->memory_last, NULL); 1390 } 1391 1392 /* 1393 * Program the memory base register with the 1394 * start of the memory range 1395 */ 1396 #ifdef _LP64 1397 cardbus_err(NULL, 8, 1398 "store 0x%x(0x%lx) in pci bridge memory base register\n", 1399 PCICFG_HIWORD(PCICFG_LOADDR(uval)), 1400 entry->memory_last); 1401 #else 1402 cardbus_err(NULL, 8, 1403 "store 0x%x(0x%llx) in pci bridge memory base register\n", 1404 PCICFG_HIWORD(PCICFG_LOADDR(uval)), 1405 entry->memory_last); 1406 #endif 1407 pci_config_put16(handle, PCI_BCNF_MEM_BASE, 1408 PCICFG_HIWORD(PCICFG_LOADDR(uval))); 1409 1410 uval = PCICFG_ROUND_UP(entry->io_last, PCICFG_IOGRAN); 1411 if (uval != entry->io_last) { 1412 cardbus_err(dip, 8, 1413 "Adding [0x%x] before bridge (I/O)\n", 1414 uval - entry->io_last); 1415 (void) cardbus_get_io(ddi_get_parent(dip), entry, 1416 uval - entry->io_last, NULL); 1417 } 1418 cardbus_err(NULL, 8, 1419 "store 0x%02x/0x%04x(0x%x) in " 1420 "pci bridge I/O hi/low base register\n", 1421 PCICFG_HIWORD(PCICFG_LOADDR(uval)), 1422 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(uval))), 1423 entry->io_last); 1424 /* 1425 * Program the I/O base register with the start of the I/O range 1426 */ 1427 pci_config_put8(handle, PCI_BCNF_IO_BASE_LOW, 1428 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(uval)))); 1429 1430 pci_config_put16(handle, PCI_BCNF_IO_BASE_HI, 1431 PCICFG_HIWORD(PCICFG_LOADDR(uval))); 1432 1433 /* 1434 * Clear status bits 1435 */ 1436 pci_config_put16(handle, PCI_BCNF_SEC_STATUS, 0xffff); 1437 1438 /* 1439 * Turn off prefetchable range 1440 */ 1441 pci_config_put32(handle, PCI_BCNF_PF_BASE_LOW, 0x0000ffff); 1442 pci_config_put32(handle, PCI_BCNF_PF_BASE_HIGH, 0xffffffff); 1443 1444 pci_config_put32(handle, PCI_BCNF_PF_LIMIT_HIGH, 0x0); 1445 1446 #ifdef sparc 1447 /* 1448 * If there is an interrupt pin set program 1449 * interrupt line with default values. 1450 */ 1451 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 1452 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 1453 } 1454 #else 1455 (void) cardbus_validate_iline(dip, handle); 1456 #endif 1457 1458 1459 } else if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_CARDBUS) { 1460 1461 /* 1462 * The highest bus seen during probing is 1463 * the max-subordinate bus 1464 */ 1465 pci_config_put8(handle, PCI_CBUS_SUB_BUS_NO, 1466 entry->highest_bus); 1467 1468 /* 1469 * Program the memory base register with the 1470 * start of the memory range 1471 */ 1472 #ifdef _LP64 1473 cardbus_err(NULL, 8, 1474 "store 0x%x(0x%lx) in " 1475 "cardbus memory base register 0, len 0x%lx\n", 1476 PCICFG_LOADDR(entry->memory_last), entry->memory_last, 1477 entry->memory_len); 1478 #else 1479 cardbus_err(NULL, 8, 1480 "store 0x%x(0x%llx) in " 1481 "cardbus memory base register 0, len 0x%llx\n", 1482 PCICFG_LOADDR(entry->memory_last), entry->memory_last, 1483 entry->memory_len); 1484 #endif 1485 1486 pci_config_put32(handle, PCI_CBUS_MEM_BASE0, 1487 PCICFG_LOADDR(entry->memory_last)); 1488 1489 /* 1490 * Program the I/O base register with the start of the I/O range 1491 */ 1492 cardbus_err(NULL, 8, 1493 "store 0x%x in cb IO base register 0 len 0x%x\n", 1494 PCICFG_LOADDR(entry->io_last), 1495 entry->io_len); 1496 1497 pci_config_put32(handle, PCI_CBUS_IO_BASE0, 1498 PCICFG_LOADDR(entry->io_last)); 1499 1500 /* 1501 * Clear status bits 1502 */ 1503 pci_config_put16(handle, PCI_CBUS_SEC_STATUS, 0xffff); 1504 1505 #ifdef sparc 1506 /* 1507 * If there is an interrupt pin set program 1508 * interrupt line with default values. 1509 */ 1510 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 1511 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 1512 } 1513 #else 1514 (void) cardbus_validate_iline(dip, handle); 1515 #endif 1516 1517 1518 /* 1519 * LATER: use these registers 1520 */ 1521 pci_config_put32(handle, PCI_CBUS_MEM_BASE1, 0); 1522 pci_config_put32(handle, PCI_CBUS_MEM_LIMIT1, 0); 1523 pci_config_put32(handle, PCI_CBUS_IO_BASE1, 0); 1524 pci_config_put32(handle, PCI_CBUS_IO_LIMIT1, 0); 1525 } else { 1526 cmn_err(CE_WARN, "header type 0x%x, probably unknown bridge\n", 1527 header_type & PCI_HEADER_TYPE_M); 1528 } 1529 1530 cardbus_err(NULL, 7, "cardbus_setup_bridge complete\n"); 1531 } 1532 1533 static void 1534 cardbus_update_bridge(dev_info_t *dip, cardbus_phdl_t *entry, 1535 ddi_acc_handle_t handle) 1536 { 1537 uint_t length; 1538 uint16_t word16 = pci_config_get16(handle, PCI_CONF_COMM); 1539 const uint8_t header_type = pci_config_get8(handle, PCI_CONF_HEADER) 1540 & PCI_HEADER_TYPE_M; 1541 uint32_t bridge_gran; 1542 uint64_t rlval; 1543 1544 if (header_type == PCI_HEADER_CARDBUS) 1545 bridge_gran = CBCFG_MEMGRAN; 1546 else 1547 bridge_gran = PCICFG_MEMGRAN; 1548 1549 /* 1550 * Program the memory limit register with the end of the memory range 1551 */ 1552 #ifdef _LP64 1553 cardbus_err(dip, 6, 1554 "cardbus_update_bridge: Mem base 0x%lx len 0x%lx " 1555 "last 0x%lx gran 0x%x gran end 0x%lx\n", 1556 entry->memory_base, entry->memory_len, 1557 entry->memory_last, entry->memory_gran, 1558 PCICFG_ROUND_UP(entry->memory_last, entry->memory_gran)); 1559 #else 1560 cardbus_err(dip, 6, 1561 "cardbus_update_bridge: Mem base 0x%llx len 0x%llx " 1562 "last 0x%llx gran 0x%x gran end 0x%lx\n", 1563 entry->memory_base, entry->memory_len, 1564 entry->memory_last, entry->memory_gran, 1565 PCICFG_ROUND_UP(entry->memory_last, entry->memory_gran)); 1566 #endif 1567 /* 1568 * Since this is a bridge, the rest of this range will 1569 * be responded to by the bridge. We have to round up 1570 * so no other device claims it. 1571 */ 1572 length = PCICFG_ROUND_UP(entry->memory_last + cardbus_min_spare_mem, 1573 bridge_gran) - entry->memory_last; 1574 1575 if (length > 0) { 1576 /* 1577 * This is to allow space that isn't actually being used by 1578 * anything to be allocated by devices such as a downstream 1579 * PCMCIA controller. 1580 */ 1581 (void) cardbus_get_mem(dip, entry, length, NULL); 1582 cardbus_err(dip, 8, 1583 "Added [0x%x] at the top of the bridge (mem)\n", length); 1584 } 1585 1586 if (entry->memory_len) { 1587 if (header_type == PCI_HEADER_CARDBUS) { 1588 rlval = PCICFG_ROUND_DOWN(entry->memory_last - 1, 1589 CBCFG_MEMGRAN); 1590 #ifdef _LP64 1591 cardbus_err(dip, 8, 1592 "store 0x%x(0x%lx) in memory limit register 0\n", 1593 PCICFG_LOADDR(rlval), rlval); 1594 #else 1595 cardbus_err(dip, 8, 1596 "store 0x%x(0x%llx) in memory limit register 0\n", 1597 PCICFG_LOADDR(rlval), rlval); 1598 #endif 1599 pci_config_put32(handle, PCI_CBUS_MEM_LIMIT0, 1600 PCICFG_LOADDR(rlval)); 1601 } else { 1602 rlval = PCICFG_ROUND_DOWN(entry->memory_last - 1, 1603 PCICFG_MEMGRAN); 1604 #ifdef _LP64 1605 cardbus_err(dip, 8, 1606 "store 0x%x(0x%lx) in memory limit register\n", 1607 PCICFG_HIWORD(PCICFG_LOADDR(rlval)), 1608 rlval); 1609 #else 1610 cardbus_err(dip, 8, 1611 "store 0x%x(0x%llx) in memory limit register\n", 1612 PCICFG_HIWORD(PCICFG_LOADDR(rlval)), 1613 rlval); 1614 #endif 1615 pci_config_put16(handle, PCI_BCNF_MEM_LIMIT, 1616 PCICFG_HIWORD(PCICFG_LOADDR(rlval))); 1617 } 1618 word16 |= PCI_COMM_MAE; 1619 } 1620 1621 cardbus_err(dip, 6, 1622 "cardbus_update_bridge: I/O base 0x%x len 0x%x last 0x%x " 1623 "gran 0x%x gran_end 0x%lx\n", 1624 entry->io_base, entry->io_len, entry->io_last, entry->io_gran, 1625 PCICFG_ROUND_UP(entry->io_last, entry->io_gran)); 1626 1627 if (header_type == PCI_HEADER_CARDBUS) 1628 bridge_gran = CBCFG_IOGRAN; 1629 else 1630 bridge_gran = PCICFG_IOGRAN; 1631 1632 /* 1633 * Same as above for I/O space. Since this is a 1634 * bridge, the rest of this range will be responded 1635 * to by the bridge. We have to round up so no 1636 * other device claims it. 1637 */ 1638 length = PCICFG_ROUND_UP(entry->io_last + cardbus_min_spare_io, 1639 bridge_gran) - entry->io_last; 1640 if (length > 0) { 1641 (void) cardbus_get_io(dip, entry, length, NULL); 1642 cardbus_err(dip, 8, 1643 "Added [0x%x] at the top of the bridge (I/O)\n", length); 1644 } 1645 1646 /* 1647 * Program the I/O limit register with the end of the I/O range 1648 */ 1649 if (entry->io_len) { 1650 if (header_type == PCI_HEADER_CARDBUS) { 1651 rlval = PCICFG_ROUND_DOWN(entry->io_last - 1, 1652 CBCFG_IOGRAN); 1653 #ifdef _LP64 1654 cardbus_err(dip, 8, 1655 "store 0x%lx in IO limit register 0\n", rlval); 1656 #else 1657 cardbus_err(dip, 8, 1658 "store 0x%llx in IO limit register 0\n", rlval); 1659 #endif 1660 pci_config_put32(handle, PCI_CBUS_IO_LIMIT0, rlval); 1661 } else { 1662 rlval = PCICFG_ROUND_DOWN(entry->io_last - 1, 1663 PCICFG_IOGRAN); 1664 #ifdef _LP64 1665 cardbus_err(dip, 8, 1666 "store 0x%x/0x%x(0x%lx) in " 1667 "IO limit low/hi register\n", 1668 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(rlval))), 1669 PCICFG_HIWORD(PCICFG_LOADDR(rlval)), 1670 rlval); 1671 #else 1672 cardbus_err(dip, 8, 1673 "store 0x%x/0x%x(0x%llx) in " 1674 "IO limit low/hi register\n", 1675 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(rlval))), 1676 PCICFG_HIWORD(PCICFG_LOADDR(rlval)), 1677 rlval); 1678 #endif 1679 1680 pci_config_put8(handle, PCI_BCNF_IO_LIMIT_LOW, 1681 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(rlval)))); 1682 pci_config_put16(handle, PCI_BCNF_IO_LIMIT_HI, 1683 PCICFG_HIWORD(PCICFG_LOADDR(rlval))); 1684 } 1685 word16 |= PCI_COMM_IO; 1686 } 1687 1688 pci_config_put16(handle, PCI_CONF_COMM, word16); 1689 } 1690 1691 static void 1692 cardbus_get_mem(dev_info_t *dip, cardbus_phdl_t *entry, 1693 uint32_t length, uint64_t *ans) 1694 { 1695 uint32_t hole; 1696 1697 #ifdef _LP64 1698 cardbus_err(NULL, 6, 1699 "cardbus_get_mem: memory_last 0x%lx, length 0x%x, " 1700 "memory_base 0x%lx, memory_len 0x%lx ans=0x%p\n", 1701 entry->memory_last, length, 1702 entry->memory_base, entry->memory_len, (void *) ans); 1703 #else 1704 cardbus_err(NULL, 6, 1705 "cardbus_get_mem: memory_last 0x%llx, length 0x%x, " 1706 "memory_base 0x%llx, memory_len 0x%llx ans=0x%p\n", 1707 entry->memory_last, length, 1708 entry->memory_base, entry->memory_len, (void *) ans); 1709 #endif 1710 1711 if (ans) { 1712 /* 1713 * Round up the request to the "size" boundary 1714 */ 1715 hole = PCICFG_ROUND_UP(entry->memory_last, length) 1716 - entry->memory_last; 1717 if (hole != 0) { 1718 (void) cardbus_update_available_prop(dip, 1719 PCI_ADDR_MEM32, 1720 entry->memory_last, 1721 (uint64_t)hole); 1722 entry->memory_last += hole; 1723 1724 #ifdef _LP64 1725 cardbus_err(NULL, 6, 1726 "cardbus_get_mem: " 1727 "rounded memory_last up by 0x%x to 0x%lx, ", 1728 hole, entry->memory_last); 1729 #else 1730 cardbus_err(NULL, 6, 1731 "cardbus_get_mem: " 1732 "rounded memory_last up by 0x%x to 0x%llx, ", 1733 hole, entry->memory_last); 1734 #endif 1735 } 1736 } else 1737 (void) cardbus_update_available_prop(dip, PCI_ADDR_MEM32, 1738 entry->memory_last, 1739 (uint64_t)length); 1740 1741 /* 1742 * These routines should parcel out the memory 1743 * completely. There should never be a case of 1744 * over running the bounds. 1745 */ 1746 if ((entry->memory_last + length) > 1747 (entry->memory_base + entry->memory_len)) 1748 #ifdef _LP64 1749 cardbus_err(NULL, 1, 1750 "cardbus_get_mem: assert will fail %ld <= %ld," 1751 "(0x%lx + 0x%x) <= (0x%lx + 0x%lx)\n", 1752 #else 1753 cardbus_err(NULL, 1, 1754 "cardbus_get_mem: assert will fail %lld <= %lld, " 1755 "(0x%llx + 0x%x) <= (0x%llx + 0x%llx)\n", 1756 #endif 1757 entry->memory_last + length, 1758 entry->memory_base + entry->memory_len, 1759 entry->memory_last, 1760 length, 1761 entry->memory_base, 1762 entry->memory_len); 1763 1764 ASSERT((entry->memory_last + length) <= 1765 (entry->memory_base + entry->memory_len)); 1766 /* 1767 * If ans is NULL don't return anything, 1768 * they are just asking to reserve the memory. 1769 */ 1770 if (ans != NULL) 1771 *ans = entry->memory_last; 1772 1773 /* 1774 * Increment to the next location 1775 */ 1776 entry->memory_last += length; 1777 } 1778 1779 static void 1780 cardbus_get_io(dev_info_t *dip, cardbus_phdl_t *entry, 1781 uint32_t length, uint32_t *ans) 1782 { 1783 uint32_t hole; 1784 1785 cardbus_err(NULL, 6, 1786 "cardbus_get_io: io_last 0x%x, length 0x%x, " 1787 "io_base 0x%x, io_len 0x%x ans=0x%p\n", 1788 entry->io_last, length, 1789 entry->io_base, entry->io_len, (void *) ans); 1790 1791 if (ans) { 1792 /* 1793 * Round up the request to the "size" boundary 1794 */ 1795 hole = PCICFG_ROUND_UP(entry->io_last, length) - entry->io_last; 1796 if (hole != 0) { 1797 (void) cardbus_update_available_prop(dip, PCI_ADDR_IO, 1798 (uint64_t)entry->io_last, 1799 (uint64_t)hole); 1800 entry->io_last += hole; 1801 1802 cardbus_err(NULL, 6, 1803 "cardbus_get_io: " 1804 "rounded io_last up by 0x%x to 0x%x, ", 1805 hole, entry->io_last); 1806 } 1807 } else 1808 (void) cardbus_update_available_prop(dip, PCI_ADDR_IO, 1809 (uint64_t)entry->io_last, 1810 (uint64_t)length); 1811 /* 1812 * These routines should parcel out the memory 1813 * completely. There should never be a case of 1814 * over running the bounds. 1815 */ 1816 ASSERT((entry->io_last + length) <= 1817 (entry->io_base + entry->io_len)); 1818 1819 /* 1820 * If ans is NULL don't return anything, 1821 * they are just asking to reserve the memory. 1822 */ 1823 if (ans != NULL) 1824 *ans = entry->io_last; 1825 1826 /* 1827 * Increment to the next location 1828 */ 1829 entry->io_last += length; 1830 } 1831 1832 static int 1833 cardbus_sum_resources(dev_info_t *dip, void *hdl) 1834 { 1835 cardbus_phdl_t *entry = (cardbus_phdl_t *)hdl; 1836 pci_regspec_t *pci_rp; 1837 int length; 1838 int rcount; 1839 int i, ret; 1840 ndi_ra_request_t *mem_request; 1841 ndi_ra_request_t *io_request; 1842 uint8_t header_type, base_class; 1843 ddi_acc_handle_t handle; 1844 1845 /* 1846 * Ignore the attachment point and pcs. 1847 */ 1848 if (strcmp(ddi_binding_name(dip), "hp_attachment") == 0 || 1849 strcmp(ddi_binding_name(dip), "pcs") == 0) { 1850 cardbus_err(dip, 8, "cardbus_sum_resources: Ignoring\n"); 1851 return (DDI_WALK_CONTINUE); 1852 } 1853 1854 mem_request = &entry->mem_req; 1855 io_request = &entry->io_req; 1856 1857 if (cardbus_config_setup(dip, &handle) != DDI_SUCCESS) { 1858 cardbus_err(dip, 1, 1859 "cardbus_sum_resources: Failed to map config space!\n"); 1860 entry->error = PCICFG_FAILURE; 1861 return (DDI_WALK_TERMINATE); 1862 } 1863 1864 ret = DDI_WALK_CONTINUE; 1865 header_type = pci_config_get8(handle, PCI_CONF_HEADER); 1866 base_class = pci_config_get8(handle, PCI_CONF_BASCLASS); 1867 1868 /* 1869 * If its a bridge - just record the highest bus seen 1870 */ 1871 if (base_class == PCI_CLASS_BRIDGE) { 1872 uint8_t sub_class; 1873 1874 sub_class = pci_config_get8(handle, PCI_CONF_SUBCLASS); 1875 1876 switch (sub_class) { 1877 case PCI_BRIDGE_PCI: 1878 if ((header_type & PCI_HEADER_TYPE_M) 1879 == PCI_HEADER_PPB) { 1880 1881 if (entry->highest_bus < pci_config_get8(handle, 1882 PCI_BCNF_SECBUS)) { 1883 entry->highest_bus = pci_config_get8( 1884 handle, PCI_BCNF_SECBUS); 1885 } 1886 1887 (void) cardbus_config_teardown(&handle); 1888 #if defined(CARDBUS_DEBUG) 1889 if (mem_request->ra_len != 1890 PCICFG_ROUND_UP(mem_request->ra_len, 1891 PCICFG_MEMGRAN)) { 1892 1893 #ifdef _LP64 1894 cardbus_err(dip, 8, 1895 "Pre-align [0x%lx] to PCI bridge " 1896 "memory gran " 1897 "[0x%lx] -> [0x%lx]\n", 1898 PCICFG_ROUND_UP(mem_request->ra_len, 1899 PCICFG_MEMGRAN) - 1900 mem_request->ra_len, 1901 mem_request->ra_len, 1902 PCICFG_ROUND_UP(mem_request->ra_len, 1903 PCICFG_MEMGRAN)); 1904 #else 1905 cardbus_err(dip, 8, 1906 "Pre-align [0x%llx] to PCI bridge " 1907 "memory gran " 1908 "[0x%llx] -> [0x%lx]\n", 1909 PCICFG_ROUND_UP(mem_request->ra_len, 1910 PCICFG_MEMGRAN) - 1911 mem_request->ra_len, 1912 mem_request->ra_len, 1913 PCICFG_ROUND_UP(mem_request->ra_len, 1914 PCICFG_MEMGRAN)); 1915 #endif 1916 } 1917 1918 if (io_request->ra_len != 1919 PCICFG_ROUND_UP(io_request->ra_len, 1920 PCICFG_IOGRAN)) { 1921 1922 #ifdef _LP64 1923 cardbus_err(dip, 8, 1924 "Pre-align [0x%lx] to PCI bridge " 1925 "I/O gran " 1926 "[0x%lx] -> [0x%lx]\n", 1927 PCICFG_ROUND_UP(io_request->ra_len, 1928 PCICFG_IOGRAN) - 1929 io_request->ra_len, 1930 io_request->ra_len, 1931 PCICFG_ROUND_UP(io_request->ra_len, 1932 PCICFG_IOGRAN)); 1933 #else 1934 cardbus_err(dip, 8, 1935 "Pre-align [0x%llx] to PCI bridge " 1936 "I/O gran " 1937 "[0x%llx] -> [0x%lx]\n", 1938 PCICFG_ROUND_UP(io_request->ra_len, 1939 PCICFG_IOGRAN) - 1940 io_request->ra_len, 1941 io_request->ra_len, 1942 PCICFG_ROUND_UP(io_request->ra_len, 1943 PCICFG_IOGRAN)); 1944 #endif 1945 } 1946 1947 #endif 1948 mem_request->ra_len = PCICFG_ROUND_UP( 1949 mem_request->ra_len, 1950 PCICFG_MEMGRAN); 1951 io_request->ra_len = PCICFG_ROUND_UP( 1952 io_request->ra_len, 1953 PCICFG_IOGRAN); 1954 if (entry->memory_gran < PCICFG_MEMGRAN) 1955 entry->memory_gran = PCICFG_MEMGRAN; 1956 if (entry->io_gran < PCICFG_IOGRAN) 1957 entry->io_gran = PCICFG_IOGRAN; 1958 ddi_walk_devs(ddi_get_child(dip), 1959 cardbus_sum_resources, 1960 (void *)entry); 1961 #if defined(CARDBUS_DEBUG) 1962 if (mem_request->ra_len != 1963 PCICFG_ROUND_UP(mem_request->ra_len + 1964 cardbus_min_spare_mem, PCICFG_MEMGRAN)) { 1965 1966 #ifdef _LP64 1967 cardbus_err(dip, 8, 1968 "Post-align [0x%lx] to PCI bridge " 1969 "memory gran " 1970 "[0x%lx] -> [0x%lx]\n", 1971 PCICFG_ROUND_UP( 1972 mem_request->ra_len + 1973 cardbus_min_spare_mem, 1974 PCICFG_MEMGRAN) - 1975 mem_request->ra_len, 1976 mem_request->ra_len, 1977 PCICFG_ROUND_UP(mem_request->ra_len 1978 + cardbus_min_spare_mem, 1979 PCICFG_MEMGRAN)); 1980 #else 1981 cardbus_err(dip, 8, 1982 "Post-align [0x%llx] to PCI bridge " 1983 "memory gran " 1984 "[0x%llx] -> [0x%lx]\n", 1985 PCICFG_ROUND_UP( 1986 mem_request->ra_len + 1987 cardbus_min_spare_mem, 1988 PCICFG_MEMGRAN) - 1989 mem_request->ra_len, 1990 mem_request->ra_len, 1991 PCICFG_ROUND_UP(mem_request->ra_len 1992 + cardbus_min_spare_mem, 1993 PCICFG_MEMGRAN)); 1994 #endif 1995 } 1996 1997 if (io_request->ra_len != 1998 PCICFG_ROUND_UP(io_request->ra_len + 1999 cardbus_min_spare_io, 2000 PCICFG_IOGRAN)) { 2001 2002 #ifdef _LP64 2003 cardbus_err(dip, 8, 2004 "Post-align [0x%lx] to PCI bridge " 2005 "I/O gran " 2006 "[0x%lx] -> [0x%lx]\n", 2007 PCICFG_ROUND_UP(io_request->ra_len + 2008 cardbus_min_spare_io, 2009 PCICFG_IOGRAN) - 2010 io_request->ra_len, 2011 io_request->ra_len, 2012 PCICFG_ROUND_UP(io_request->ra_len + 2013 cardbus_min_spare_io, 2014 PCICFG_IOGRAN)); 2015 #else 2016 cardbus_err(dip, 8, 2017 "Post-align [0x%llx] to PCI bridge " 2018 "I/O gran " 2019 "[0x%llx] -> [0x%lx]\n", 2020 PCICFG_ROUND_UP(io_request->ra_len + 2021 cardbus_min_spare_io, 2022 PCICFG_IOGRAN) - 2023 io_request->ra_len, 2024 io_request->ra_len, 2025 PCICFG_ROUND_UP(io_request->ra_len + 2026 cardbus_min_spare_io, 2027 PCICFG_IOGRAN)); 2028 #endif 2029 } 2030 #endif 2031 mem_request->ra_len = PCICFG_ROUND_UP( 2032 mem_request->ra_len + 2033 cardbus_min_spare_mem, 2034 PCICFG_MEMGRAN); 2035 io_request->ra_len = PCICFG_ROUND_UP( 2036 io_request->ra_len + 2037 cardbus_min_spare_io, 2038 PCICFG_IOGRAN); 2039 } 2040 return (DDI_WALK_PRUNECHILD); 2041 2042 case PCI_BRIDGE_CARDBUS: 2043 /* 2044 * Cardbus has I/O registers. 2045 */ 2046 break; 2047 2048 case PCI_BRIDGE_ISA: 2049 /* 2050 * All the registers requirements for ISA 2051 * are stored in the reg structure of the bridge. 2052 * Children of ISA are not of type PCI 2053 * so must not come through here because 2054 * cardbus_config_setup() will fail. 2055 */ 2056 ret = DDI_WALK_PRUNECHILD; 2057 break; 2058 2059 default: 2060 /* 2061 * Treat other bridges as leaf nodes. 2062 */ 2063 break; 2064 } 2065 } 2066 2067 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2068 DDI_PROP_DONTPASS, "reg", (caddr_t)&pci_rp, 2069 &length) != DDI_PROP_SUCCESS) { 2070 /* 2071 * If one node in (the subtree of nodes) 2072 * does'nt have a "reg" property fail the 2073 * allocation. 2074 */ 2075 entry->memory_len = 0; 2076 entry->io_len = 0; 2077 entry->error = PCICFG_FAILURE; 2078 (void) cardbus_config_teardown(&handle); 2079 return (DDI_WALK_TERMINATE); 2080 } 2081 2082 /* 2083 * For each "reg" property with a length, add that to the 2084 * total memory (or I/O) to allocate. 2085 */ 2086 rcount = length / sizeof (pci_regspec_t); 2087 2088 for (i = 0; i < rcount; i++) { 2089 2090 switch (PCI_REG_ADDR_G(pci_rp[i].pci_phys_hi)) { 2091 2092 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 2093 mem_request->ra_len = 2094 pci_rp[i].pci_size_low + 2095 PCICFG_ROUND_UP(mem_request->ra_len, 2096 pci_rp[i].pci_size_low); 2097 2098 cardbus_err(dip, 8, 2099 "ADDING 32 --->0x%x for BAR@0x%x\n", 2100 pci_rp[i].pci_size_low, 2101 PCI_REG_REG_G(pci_rp[i].pci_phys_hi)); 2102 /* 2103 * the granualarity needs to be the larger of 2104 * the maximum amount of memory that we're going to 2105 * ask for, and the PCI-PCI bridge granularity (1M) 2106 */ 2107 if (pci_rp[i].pci_size_low > entry->memory_gran) 2108 entry->memory_gran = pci_rp[i].pci_size_low; 2109 break; 2110 2111 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 2112 mem_request->ra_len = 2113 pci_rp[i].pci_size_low + 2114 PCICFG_ROUND_UP(mem_request->ra_len, 2115 pci_rp[i].pci_size_low); 2116 cardbus_err(dip, 8, 2117 "ADDING 64 --->0x%x for BAR@0x%x\n", 2118 pci_rp[i].pci_size_low, 2119 PCI_REG_REG_G(pci_rp[i].pci_phys_hi)); 2120 2121 if (pci_rp[i].pci_size_low > entry->memory_gran) 2122 entry->memory_gran = pci_rp[i].pci_size_low; 2123 break; 2124 2125 case PCI_REG_ADDR_G(PCI_ADDR_IO): 2126 io_request->ra_len = 2127 pci_rp[i].pci_size_low + 2128 PCICFG_ROUND_UP(io_request->ra_len, 2129 pci_rp[i].pci_size_low); 2130 cardbus_err(dip, 8, 2131 "ADDING I/O --->0x%x for BAR@0x%x\n", 2132 pci_rp[i].pci_size_low, 2133 PCI_REG_REG_G(pci_rp[i].pci_phys_hi)); 2134 2135 if (pci_rp[i].pci_size_low > entry->io_gran) 2136 entry->io_gran = pci_rp[i].pci_size_low; 2137 break; 2138 2139 default: 2140 /* Config space register - not included */ 2141 break; 2142 } 2143 } 2144 2145 /* 2146 * free the memory allocated by ddi_getlongprop 2147 */ 2148 kmem_free(pci_rp, length); 2149 2150 /* 2151 * continue the walk to the next sibling to sum memory 2152 */ 2153 2154 (void) cardbus_config_teardown(&handle); 2155 2156 #ifdef _LP64 2157 cardbus_err(dip, 8, 2158 "Memory 0x%lx bytes, I/O 0x%lx bytes, " 2159 "Memgran 0x%x, IOgran 0x%x\n", 2160 mem_request->ra_len, io_request->ra_len, 2161 entry->memory_gran, entry->io_gran); 2162 #else 2163 cardbus_err(dip, 8, 2164 "Memory 0x%llx bytes, I/O 0x%llx bytes, " 2165 "Memgran 0x%x, IOgran 0x%x\n", 2166 mem_request->ra_len, io_request->ra_len, 2167 entry->memory_gran, entry->io_gran); 2168 #endif 2169 2170 return (ret); 2171 } 2172 2173 /* 2174 * Free resources allocated to a bridge. 2175 * Note that this routine does not call ndi_ra_free() to actually 2176 * free memory/IO/Bus. This is done as a single chunk for the entire 2177 * device tree in cardbus_free_chunk(). 2178 */ 2179 static int 2180 cardbus_free_bridge_resources(dev_info_t *dip) 2181 { 2182 cardbus_range_t *ranges; 2183 uint_t *bus; 2184 int k; 2185 int length; 2186 int i; 2187 2188 cardbus_err(dip, 6, "cardbus_free_bridge_resources\n"); 2189 2190 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2191 DDI_PROP_DONTPASS, "ranges", (caddr_t)&ranges, 2192 &length) == DDI_PROP_SUCCESS) { 2193 for (i = 0; i < length / sizeof (cardbus_range_t); i++) { 2194 if (ranges[i].size_lo != 0 || ranges[i].size_hi != 0) { 2195 switch (ranges[i].parent_hi & PCI_REG_ADDR_M) { 2196 case PCI_ADDR_IO: 2197 cardbus_err(dip, 6, 2198 "Need to Free I/O " 2199 "base/length = [0x%x]/[0x%x]\n", 2200 ranges[i].child_lo, 2201 ranges[i].size_lo); 2202 break; 2203 2204 case PCI_ADDR_MEM32: 2205 case PCI_ADDR_MEM64: 2206 cardbus_err(dip, 6, 2207 "Need to Free Memory base/length = " 2208 "[0x%x.%x]/[0x%x]\n", 2209 ranges[i].child_mid, 2210 ranges[i].child_lo, 2211 ranges[i].size_lo); 2212 break; 2213 2214 default: 2215 cardbus_err(dip, 6, 2216 "Unknown memory space\n"); 2217 break; 2218 } 2219 } 2220 } 2221 2222 kmem_free(ranges, length); 2223 (void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "ranges"); 2224 } else { 2225 cardbus_err(dip, 8, 2226 "cardbus_free_bridge_resources: Failed" 2227 "to read ranges property\n"); 2228 } 2229 2230 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2231 DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus, 2232 &k) != DDI_PROP_SUCCESS) { 2233 cardbus_err(dip, 6, "Failed to read bus-range property\n"); 2234 return (PCICFG_FAILURE); 2235 } 2236 2237 cardbus_err(dip, 6, 2238 "Need to free bus [%d] range [%d]\n", 2239 bus[0], bus[1] - bus[0] + 1); 2240 kmem_free(bus, k); 2241 (void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "available"); 2242 (void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "bus-range"); 2243 2244 return (PCICFG_SUCCESS); 2245 } 2246 2247 static int 2248 cardbus_free_device_resources(dev_info_t *dip) 2249 { 2250 pci_regspec_t *assigned; 2251 2252 int length; 2253 int acount; 2254 int i; 2255 2256 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2257 DDI_PROP_DONTPASS, "assigned-addresses", 2258 (caddr_t)&assigned, 2259 &length) != DDI_PROP_SUCCESS) { 2260 cardbus_err(dip, 1, 2261 "Failed to read assigned-addresses property\n"); 2262 return (PCICFG_FAILURE); 2263 } 2264 2265 /* 2266 * For each "assigned-addresses" property entry with a length, 2267 * call the memory allocation routines to return the 2268 * resource. 2269 */ 2270 acount = length / sizeof (pci_regspec_t); 2271 for (i = 0; i < acount; i++) { 2272 2273 /* 2274 * Free the resource if the size of it is not zero. 2275 */ 2276 if ((assigned[i].pci_size_low != 0)|| 2277 (assigned[i].pci_size_hi != 0)) { 2278 switch (PCI_REG_ADDR_G(assigned[i].pci_phys_hi)) { 2279 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 2280 cardbus_err(dip, 6, 2281 "Need to return 0x%x of 32 bit MEM space" 2282 " @ 0x%x from register 0x%x\n", 2283 assigned[i].pci_size_low, 2284 assigned[i].pci_phys_low, 2285 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2286 2287 break; 2288 2289 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 2290 cardbus_err(dip, 6, 2291 "Need to return 0x%x of 64 bit MEM space" 2292 " @ 0x%x.%x from register 0x%x\n", 2293 assigned[i].pci_size_low, 2294 assigned[i].pci_phys_mid, 2295 assigned[i].pci_phys_low, 2296 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2297 2298 break; 2299 2300 case PCI_REG_ADDR_G(PCI_ADDR_IO): 2301 cardbus_err(dip, 6, 2302 "Need to return 0x%x of IO space @ 0x%x" 2303 " from register 0x%x\n", 2304 assigned[i].pci_size_low, 2305 assigned[i].pci_phys_low, 2306 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2307 break; 2308 2309 default: 2310 cardbus_err(dip, 1, "Unknown register type\n"); 2311 kmem_free(assigned, length); 2312 return (PCICFG_FAILURE); 2313 } /* switch */ 2314 } 2315 } 2316 kmem_free(assigned, length); 2317 return (PCICFG_SUCCESS); 2318 } 2319 2320 static int 2321 cardbus_free_resources(dev_info_t *dip) 2322 { 2323 uint32_t classcode; 2324 2325 classcode = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2326 "class-code", -1); 2327 /* 2328 * A different algorithim is used for bridges and leaf devices. 2329 */ 2330 if (classcode != -1) { 2331 classcode = ((uint_t)classcode & 0xffff00) >> 8; 2332 if (classcode == 0x604 || classcode == 0x607) { 2333 if (cardbus_free_bridge_resources(dip) 2334 != PCICFG_SUCCESS) { 2335 cardbus_err(dip, 1, 2336 "Failed freeing up bridge resources\n"); 2337 return (PCICFG_FAILURE); 2338 } 2339 return (PCICFG_SUCCESS); 2340 } 2341 } 2342 2343 if (cardbus_free_device_resources(dip) != PCICFG_SUCCESS) { 2344 cardbus_err(dip, 1, "Failed freeing up device resources\n"); 2345 return (PCICFG_FAILURE); 2346 } 2347 return (PCICFG_SUCCESS); 2348 } 2349 2350 static int 2351 cardbus_probe_bridge(cbus_t *cbp, dev_info_t *attpt, uint_t bus, 2352 uint_t device, uint_t func) 2353 { 2354 /* Declairations */ 2355 cardbus_bus_range_t *bus_range; 2356 int i, j; 2357 uint8_t header_type; 2358 ddi_acc_handle_t config_handle; 2359 ndi_ra_request_t req; 2360 uint_t new_bus; 2361 uint64_t blen; 2362 uint64_t next_bus; 2363 int circ; 2364 2365 cardbus_err(cbp->cb_dip, 6, 2366 "cardbus_probe_bridge bus %d device %d func %d\n", 2367 bus, device, func); 2368 2369 ndi_devi_enter(cbp->cb_dip, &circ); 2370 if (pci_config_setup(cbp->cb_dip, &config_handle) != DDI_SUCCESS) { 2371 2372 cardbus_err(cbp->cb_dip, 1, 2373 "cardbus_probe_bridge(): Failed to setup config space\n"); 2374 2375 ndi_devi_exit(cbp->cb_dip, circ); 2376 return (PCICFG_FAILURE); 2377 } 2378 2379 header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 2380 2381 /* 2382 * As soon as we have access to config space, check device 2383 * is a bridge. 2384 */ 2385 if ((header_type & PCI_HEADER_TYPE_M) != PCI_HEADER_CARDBUS) 2386 goto failed; 2387 2388 cardbus_err(cbp->cb_dip, 8, 2389 "---Vendor ID = [0x%04x]\n", 2390 pci_config_get16(config_handle, PCI_CONF_VENID)); 2391 cardbus_err(cbp->cb_dip, 8, 2392 "---Device ID = [0x%04x]\n", 2393 pci_config_get16(config_handle, PCI_CONF_DEVID)); 2394 2395 /* say what type of header */ 2396 cardbus_err(cbp->cb_dip, 8, 2397 "--%s bridge found root bus [0x%x] device [0x%x] func [0x%x]\n", 2398 ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) ? 2399 "PCI-PCI" : "Cardbus", 2400 bus, device, func); 2401 2402 if (ddi_getlongprop(DDI_DEV_T_ANY, cbp->cb_dip, 0, "bus-range", 2403 (caddr_t)&bus_range, &i) != DDI_PROP_SUCCESS) 2404 cardbus_err(cbp->cb_dip, 1, 2405 "No bus-range property seems to have been set up\n"); 2406 else { 2407 cardbus_err(cbp->cb_dip, 8, 2408 "allowable bus range is %u->%u\n", 2409 bus_range->lo, bus_range->hi); 2410 kmem_free((caddr_t)bus_range, i); 2411 } 2412 2413 /* 2414 * Get next bus in sequence and program device. 2415 */ 2416 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 2417 req.ra_len = 1; 2418 2419 if (ndi_ra_alloc(cbp->cb_dip, &req, 2420 &next_bus, &blen, NDI_RA_TYPE_PCI_BUSNUM, 2421 NDI_RA_PASS) != NDI_SUCCESS) { 2422 cmn_err(CE_WARN, "Failed to get a bus number\n"); 2423 goto failed; 2424 } 2425 2426 new_bus = next_bus; 2427 cardbus_err(cbp->cb_dip, 8, 2428 "NEW bus found [%u]->[%u]\n", bus, new_bus); 2429 2430 (void) cardbus_set_bus_numbers(config_handle, bus, new_bus); 2431 2432 /* Enable it all */ 2433 enable_cardbus_bridge(cbp->cb_dip, config_handle); 2434 2435 /* 2436 * Probe all children devices 2437 */ 2438 for (i = 0; i < pcicfg_max_device; i++) 2439 for (j = 0; j < pcicfg_max_function; j++) 2440 switch (cardbus_probe_children(cbp, attpt, new_bus, i, 2441 j, &header_type)) { 2442 2443 case PCICFG_FAILURE: 2444 cardbus_err(cbp->cb_dip, 1, 2445 "Failed to configure bus " 2446 "[0x%x] device [0x%x] func [0x%x]\n", 2447 new_bus, i, j); 2448 disable_cardbus_bridge(cbp->cb_dip, 2449 config_handle); 2450 goto failed; 2451 2452 case PCICFG_NODEVICE: 2453 /* 2454 * if there's no function 0 2455 * there's no point in probing other 2456 * functions 2457 */ 2458 if (j != 0) 2459 break; 2460 /* FALLTHROUGH */ 2461 case PCICFG_NOMULTI: 2462 j = pcicfg_max_function; 2463 break; 2464 2465 default: 2466 break; 2467 } 2468 2469 (void) pci_config_teardown(&config_handle); 2470 (void) i_ndi_config_node(attpt, DS_LINKED, 0); 2471 ndi_devi_exit(cbp->cb_dip, circ); 2472 2473 return (PCICFG_SUCCESS); 2474 2475 failed: 2476 (void) pci_config_teardown(&config_handle); 2477 ndi_devi_exit(cbp->cb_dip, circ); 2478 2479 return (PCICFG_FAILURE); 2480 } 2481 2482 static struct isa_node isa_nodes[] = { 2483 {"dummy", {NULL, NULL, NULL, NULL, NULL}, "serial", "", 0x4e, 0x2} 2484 }; 2485 2486 static int 2487 cardbus_probe_children(cbus_t *cbp, dev_info_t *parent, uint_t bus, 2488 uint_t device, uint_t func, uint8_t *header_type) 2489 { 2490 dev_info_t *new_child; 2491 ddi_acc_handle_t config_handle; 2492 int i, j; 2493 ndi_ra_request_t req; 2494 uint64_t next_bus; 2495 uint64_t blen; 2496 uint32_t request; 2497 uint8_t base_class; 2498 uint_t new_bus; 2499 int ret; 2500 int circ; 2501 2502 cardbus_err(parent, 6, 2503 "cardbus_probe_children bus %d device %d func %d\n", 2504 bus, device, func); 2505 2506 /* 2507 * This node will be put immediately below 2508 * "parent". Allocate a blank device node. It will either 2509 * be filled in or freed up based on further probing. 2510 */ 2511 2512 ndi_devi_enter(parent, &circ); 2513 2514 if (ndi_devi_alloc(parent, DEVI_PSEUDO_NEXNAME, 2515 (pnode_t)DEVI_SID_NODEID, 2516 &new_child) != NDI_SUCCESS) { 2517 cardbus_err(parent, 1, 2518 "cardbus_probe_children(): Failed to alloc child node\n"); 2519 ndi_devi_exit(parent, circ); 2520 return (PCICFG_FAILURE); 2521 } 2522 2523 if (cardbus_add_config_reg(new_child, bus, 2524 device, func) != DDI_SUCCESS) { 2525 cardbus_err(parent, 1, 2526 "cardbus_probe_children(): Failed to add candidate REG\n"); 2527 goto failedconfig; 2528 } 2529 2530 if ((ret = cardbus_config_setup(new_child, &config_handle)) 2531 != PCICFG_SUCCESS) { 2532 2533 if (ret == PCICFG_NODEVICE) { 2534 (void) ndi_devi_free(new_child); 2535 return (ret); 2536 } 2537 cardbus_err(parent, 1, 2538 "cardbus_probe_children(): Failed to setup config space\n"); 2539 2540 goto failedconfig; 2541 } 2542 2543 base_class = pci_config_get8(config_handle, PCI_CONF_BASCLASS); 2544 2545 if (func == 0) { 2546 /* 2547 * Preserve the header type from function 0. 2548 * Additional functions may not preserve the PCI_HEADER_MULTI 2549 * bit. 2550 */ 2551 *header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 2552 } else if (!(*header_type & PCI_HEADER_MULTI) || 2553 ((*header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) || 2554 (base_class == PCI_CLASS_BRIDGE)) { 2555 2556 (void) cardbus_config_teardown(&config_handle); 2557 (void) ndi_devi_free(new_child); 2558 return (PCICFG_NOMULTI); 2559 } 2560 2561 /* 2562 * As soon as we have access to config space, 2563 * turn off device. It will get turned on 2564 * later (after memory is assigned). 2565 * not if it's a cardbus device. It may be OK to leave 2566 * it on - try LATER 2567 */ 2568 disable_cardbus_device(config_handle); 2569 2570 /* 2571 * Set 1275 properties common to all devices 2572 */ 2573 if (cardbus_set_standard_props(parent, new_child, 2574 config_handle) != PCICFG_SUCCESS) { 2575 cardbus_err(parent, 1, "Failed to set standard properties\n"); 2576 goto failedchild; 2577 } 2578 2579 /* 2580 * Child node properties NOTE: Both for PCI-PCI bridge and child node 2581 */ 2582 if (cardbus_set_childnode_props(new_child, 2583 config_handle) != PCICFG_SUCCESS) { 2584 goto failedchild; 2585 } 2586 2587 cardbus_err(parent, 8, 2588 "---Vendor ID = [0x%04x]\n", 2589 pci_config_get16(config_handle, PCI_CONF_VENID)); 2590 cardbus_err(parent, 8, 2591 "---Device ID = [0x%04x]\n", 2592 pci_config_get16(config_handle, PCI_CONF_DEVID)); 2593 2594 if (base_class == PCI_CLASS_BRIDGE) { 2595 uint8_t sub_class; 2596 2597 sub_class = pci_config_get8(config_handle, PCI_CONF_SUBCLASS); 2598 2599 switch (sub_class) { 2600 case PCI_BRIDGE_PCI: 2601 if ((*header_type & PCI_HEADER_TYPE_M) 2602 == PCI_HEADER_PPB) { 2603 cardbus_bus_range_t *bus_range; 2604 int k; 2605 2606 /* say what type of header */ 2607 cardbus_err(parent, 8, 2608 "-- Found PCI-PCI bridge @ " 2609 " bus [0x%x] device [0x%x] func [0x%x]\n", 2610 bus, device, func); 2611 2612 if (ddi_getlongprop(DDI_DEV_T_ANY, 2613 new_child, 0, "bus-range", 2614 (caddr_t)&bus_range, 2615 &k) != DDI_PROP_SUCCESS) 2616 cardbus_err(new_child, 1, 2617 "No bus-range property" 2618 " seems to have been set up\n"); 2619 else { 2620 cardbus_err(new_child, 8, 2621 "allowable bus range is %u->%u\n", 2622 bus_range->lo, bus_range->hi); 2623 kmem_free((caddr_t)bus_range, k); 2624 } 2625 2626 /* 2627 * Get next bus in sequence and program device. 2628 */ 2629 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 2630 req.ra_len = 1; 2631 2632 if (ndi_ra_alloc(new_child, &req, 2633 &next_bus, &blen, 2634 NDI_RA_TYPE_PCI_BUSNUM, 2635 NDI_RA_PASS) != NDI_SUCCESS) { 2636 cmn_err(CE_WARN, 2637 "Failed to get a bus number\n"); 2638 goto failedchild; 2639 } 2640 2641 new_bus = next_bus; 2642 2643 cardbus_err(new_child, 8, 2644 "NEW bus found [%u]->[%u]\n", bus, new_bus); 2645 2646 /* Enable it all */ 2647 enable_pci_pci_bridge(new_child, config_handle); 2648 (void) cardbus_set_bus_numbers(config_handle, 2649 bus, new_bus); 2650 2651 #if defined(CARDBUS_DEBUG) 2652 if (cardbus_debug >= 9) { 2653 cardbus_dump_config(config_handle); 2654 } 2655 #endif 2656 2657 /* 2658 * Set bus properties 2659 */ 2660 if (cardbus_set_busnode_props(new_child) 2661 != PCICFG_SUCCESS) { 2662 cardbus_err(new_child, 1, 2663 "Failed to set busnode props\n"); 2664 disable_pci_pci_bridge(new_child, 2665 config_handle); 2666 goto failedchild; 2667 } 2668 2669 /* 2670 * Probe all children devices 2671 */ 2672 for (i = 0; i < pcicfg_max_device; i++) 2673 for (j = 0; j < pcicfg_max_function; 2674 j++) 2675 switch (cardbus_probe_children( 2676 cbp, 2677 new_child, 2678 new_bus, i, 2679 j, header_type)) { 2680 case PCICFG_FAILURE: 2681 cardbus_err(parent, 1, 2682 "Failed to " 2683 "configure " 2684 "bus [0x%x] " 2685 "device [0x%x] " 2686 "func [0x%x]\n", 2687 new_bus, i, j); 2688 disable_pci_pci_bridge( 2689 new_child, 2690 config_handle); 2691 goto failedchild; 2692 2693 case PCICFG_NODEVICE: 2694 /* 2695 * if there's no 2696 * function 0 2697 * there's no point in 2698 * probing other 2699 * functions 2700 */ 2701 if (j != 0) 2702 break; 2703 /* FALLTHROUGH */ 2704 case PCICFG_NOMULTI: 2705 j = pcicfg_max_function; 2706 break; 2707 2708 default: 2709 break; 2710 } 2711 } 2712 break; 2713 2714 case PCI_BRIDGE_CARDBUS: 2715 cardbus_err(parent, 8, 2716 "--Found Cardbus bridge @ " 2717 "bus [0x%x] device [0x%x] func [0x%x]\n", 2718 bus, device, func); 2719 pci_config_put32(config_handle, 2720 PCI_CONF_BASE0, 0xffffffff); 2721 2722 request = pci_config_get32(config_handle, 2723 PCI_CONF_BASE0); 2724 2725 /* 2726 * If its a zero length, don't do 2727 * any programming. 2728 */ 2729 if (request != 0) { 2730 if (request == (uint32_t)0xffffffff) { 2731 cmn_err(CE_WARN, 2732 "cardbus_probe_children: " 2733 "can't access device"); 2734 goto failedchild; 2735 } 2736 /* 2737 * Add to the "reg" property 2738 */ 2739 if (cardbus_update_reg_prop(new_child, 2740 request, 2741 PCI_CONF_BASE0) != PCICFG_SUCCESS) { 2742 goto failedchild; 2743 } 2744 cardbus_err(parent, 8, 2745 "BASE register [0x%x] asks for " 2746 "[0x%x]=[0x%x](32)\n", 2747 PCI_CONF_BASE0, request, 2748 (~(PCI_BASE_M_ADDR_M & request))+1); 2749 } 2750 break; 2751 2752 case PCI_BRIDGE_ISA: 2753 cardbus_err(parent, 8, 2754 "--Found ISA bridge @ " 2755 "bus [0x%x] device [0x%x] func [0x%x]\n", 2756 bus, device, func); 2757 enable_pci_isa_bridge(new_child, config_handle); 2758 2759 #if defined(CARDBUS_DEBUG) 2760 if (cardbus_debug >= 4) { 2761 cardbus_dump_common_config(config_handle); 2762 cardbus_err(NULL, 1, 2763 " DDMA SlvCh0 = [0x%04x] " 2764 "DDMA SlvCh1 = [0x%04x]\n", 2765 pci_config_get16(config_handle, 0x40), 2766 pci_config_get16(config_handle, 0x42)); 2767 cardbus_err(NULL, 1, 2768 " DDMA SlvCh2 = [0x%04x] " 2769 "DDMA SlvCh3 = [0x%04x]\n", 2770 pci_config_get16(config_handle, 0x44), 2771 pci_config_get16(config_handle, 0x46)); 2772 cardbus_err(NULL, 1, 2773 " DDMA SlvCh5 = [0x%04x] " 2774 "DDMA SlvCh6 = [0x%04x]\n", 2775 pci_config_get16(config_handle, 0x4a), 2776 pci_config_get16(config_handle, 0x4c)); 2777 cardbus_err(NULL, 1, 2778 " DDMA SlvCh7 = [0x%04x] " 2779 "Misc Cntrl = [0x%02x]\n", 2780 pci_config_get16(config_handle, 0x4e), 2781 pci_config_get8(config_handle, 0x57)); 2782 cardbus_err(NULL, 1, 2783 " DMA Cntl = [0x%02x] " 2784 "DMA TyF Tim = [0x%02x]\n", 2785 pci_config_get8(config_handle, 0x48), 2786 pci_config_get8(config_handle, 0x49)); 2787 cardbus_err(NULL, 1, 2788 " TimCntrl = [0x%02x] " 2789 "MTOP = [0x%02x]\n", 2790 pci_config_get8(config_handle, 0x50), 2791 pci_config_get8(config_handle, 0x51)); 2792 cardbus_err(NULL, 1, 2793 " MDMA Access = [0x%02x] " 2794 "ROMCS = [0x%02x]\n", 2795 pci_config_get8(config_handle, 0x52), 2796 pci_config_get8(config_handle, 0x53)); 2797 cardbus_err(NULL, 1, 2798 " Dscrd Tmr = [0x%02x] " 2799 "Retry Tmr = [0x%02x]\n", 2800 pci_config_get8(config_handle, 0x55), 2801 pci_config_get8(config_handle, 0x54)); 2802 cardbus_err(NULL, 1, 2803 " I/O Spc 0 = [0x%08x] " 2804 "I/O Spc 1 = [0x%08x]\n", 2805 pci_config_get32(config_handle, 0x58), 2806 pci_config_get32(config_handle, 0x5c)); 2807 cardbus_err(NULL, 1, 2808 " I/O Spc 2 = [0x%08x] " 2809 "I/O Spc 3 = [0x%08x]\n", 2810 pci_config_get32(config_handle, 0x60), 2811 pci_config_get32(config_handle, 0x64)); 2812 cardbus_err(NULL, 1, 2813 " I/O Spc 4 = [0x%08x] " 2814 "I/O Spc 5 = [0x%08x]\n", 2815 pci_config_get32(config_handle, 0x68), 2816 pci_config_get32(config_handle, 0x6c)); 2817 cardbus_err(NULL, 1, 2818 " Mem Spc 0 = [0x%08x] " 2819 "Mem Spc 1 = [0x%08x]\n", 2820 pci_config_get32(config_handle, 0x70), 2821 pci_config_get32(config_handle, 0x74)); 2822 cardbus_err(NULL, 1, 2823 " Mem Spc 2 = [0x%08x] " 2824 "Mem Spc 3 = [0x%08x]\n", 2825 pci_config_get32(config_handle, 0x78), 2826 pci_config_get32(config_handle, 0x7c)); 2827 } 2828 #endif 2829 /* 2830 * Set bus properties 2831 */ 2832 if (cardbus_set_busnode_isaprops(new_child) 2833 != PCICFG_SUCCESS) { 2834 cardbus_err(new_child, 1, 2835 "Failed to set busnode props\n"); 2836 disable_cardbus_device(config_handle); 2837 goto failedchild; 2838 } 2839 2840 /* 2841 * Add to the "reg" property. 2842 * Simply grab 1K of I/O space. 2843 */ 2844 if (cardbus_update_reg_prop(new_child, 2845 0xfffffc00 | PCI_BASE_SPACE_IO, 2846 PCI_CONF_BASE0) != PCICFG_SUCCESS) { 2847 goto failedchild; 2848 } 2849 2850 /* 2851 * Probe all potential children devices. 2852 */ 2853 for (i = 0; 2854 i < sizeof (isa_nodes) / sizeof (isa_nodes[0]); 2855 i++) 2856 switch (cardbus_add_isa_node(cbp, new_child, 2857 &isa_nodes[i])) { 2858 case PCICFG_FAILURE: 2859 cardbus_err(parent, 1, 2860 "Failed to configure isa bus\n"); 2861 disable_cardbus_device(config_handle); 2862 goto failedchild; 2863 2864 case PCICFG_NODEVICE: 2865 continue; 2866 } 2867 2868 break; 2869 2870 case PCI_BRIDGE_OTHER: 2871 default: 2872 cardbus_err(parent, 8, 2873 "--Found unknown bridge, subclass 0x%x @ " 2874 "bus [0x%x] device [0x%x] func [0x%x]\n", 2875 sub_class, bus, device, func); 2876 goto leaf_node; 2877 } 2878 } else { 2879 cardbus_err(parent, 8, 2880 "--Leaf device found " 2881 "bus [0x%x] device [0x%x] func [0x%x]\n", 2882 bus, device, func); 2883 /* 2884 * Ethernet devices. 2885 */ 2886 if (strcmp(ddi_binding_name(new_child), "ethernet") == 0) { 2887 extern int localetheraddr(struct ether_addr *, 2888 struct ether_addr *); 2889 uchar_t mac[6]; 2890 2891 cardbus_force_stringprop(new_child, 2892 "device_type", "network"); 2893 2894 if (localetheraddr(NULL, (struct ether_addr *)mac)) { 2895 (void) ddi_prop_create(DDI_DEV_T_NONE, 2896 new_child, 2897 DDI_PROP_CANSLEEP, "local-mac-address", 2898 (caddr_t)mac, 6); 2899 } 2900 } 2901 leaf_node: 2902 if (cbp->cb_dsp) { 2903 struct cb_deviceset_props *cdsp = cbp->cb_dsp; 2904 uint16_t venid = pci_config_get16(config_handle, 2905 PCI_CONF_VENID); 2906 uint16_t devid = pci_config_get16(config_handle, 2907 PCI_CONF_DEVID); 2908 ddi_prop_t *propp; 2909 2910 for (cdsp = cbp->cb_dsp; cdsp; cdsp = cdsp->next) { 2911 if (cdsp->binding_name && 2912 strcmp(ddi_binding_name(new_child), 2913 cdsp->binding_name)) 2914 continue; 2915 if (cdsp->venid && (cdsp->venid != venid)) 2916 continue; 2917 if (cdsp->devid && (cdsp->devid != devid)) 2918 continue; 2919 if (cdsp->nodename) { 2920 if (ndi_devi_set_nodename(new_child, 2921 cdsp->nodename, 2922 0) != NDI_SUCCESS) 2923 cardbus_err(new_child, 1, 2924 "Failed to set nodename\n"); 2925 } 2926 for (propp = cdsp->prop_list; propp; 2927 propp = propp->prop_next) { 2928 switch (propp->prop_flags) { 2929 case DDI_PROP_TYPE_INT: 2930 cardbus_force_intprop( 2931 new_child, 2932 propp->prop_name, 2933 (int *)propp->prop_val, 2934 propp->prop_len); 2935 break; 2936 case DDI_PROP_TYPE_STRING: 2937 cardbus_force_stringprop( 2938 new_child, 2939 propp->prop_name, 2940 (char *)propp->prop_val); 2941 break; 2942 case DDI_PROP_TYPE_ANY: 2943 cardbus_force_boolprop( 2944 new_child, 2945 propp->prop_name); 2946 break; 2947 } 2948 } 2949 } 2950 } 2951 2952 #if defined(CARDBUS_DEBUG) 2953 if (cardbus_debug >= 9) { 2954 cardbus_dump_config(config_handle); 2955 } 2956 #endif 2957 2958 i = PCI_CONF_BASE0; 2959 2960 while (i <= PCI_CONF_BASE5) { 2961 pci_config_put32(config_handle, i, 0xffffffff); 2962 2963 request = pci_config_get32(config_handle, i); 2964 2965 /* 2966 * If its a zero length, don't do 2967 * any programming. 2968 */ 2969 if (request != 0) { 2970 if (request == (uint32_t)0xffffffff) { 2971 cmn_err(CE_WARN, 2972 "cardbus_probe_children: " 2973 "can't access device"); 2974 goto failedchild; 2975 } 2976 /* 2977 * Add to the "reg" property 2978 */ 2979 if (cardbus_update_reg_prop(new_child, 2980 request, i) != PCICFG_SUCCESS) { 2981 goto failedchild; 2982 } 2983 } else { 2984 cardbus_err(parent, 8, "All memory found\n"); 2985 break; 2986 } 2987 2988 /* 2989 * Increment by eight if it is 64 bit address space 2990 * only if memory space 2991 */ 2992 if (((PCI_BASE_TYPE_M & request) 2993 == PCI_BASE_TYPE_ALL) && 2994 ((PCI_BASE_SPACE_M & request) 2995 == PCI_BASE_SPACE_MEM)) { 2996 cardbus_err(parent, 8, 2997 "BASE register [0x%x] asks for " 2998 "[0x%x]=[0x%x] (64)\n", 2999 i, request, 3000 (~(PCI_BASE_M_ADDR_M & request))+1); 3001 i += 8; 3002 } else { 3003 cardbus_err(parent, 8, 3004 "BASE register [0x%x] asks for " 3005 "[0x%x]=[0x%x](32)\n", 3006 i, request, 3007 (~(PCI_BASE_M_ADDR_M & request))+1); 3008 i += 4; 3009 } 3010 } 3011 3012 /* 3013 * Get the ROM size and create register for it 3014 */ 3015 pci_config_put32(config_handle, PCI_CONF_ROM, 0xffffffff); 3016 3017 request = pci_config_get32(config_handle, PCI_CONF_ROM); 3018 /* 3019 * If its a zero length, don't do 3020 * any programming. 3021 */ 3022 3023 if (request != 0) { 3024 cardbus_err(parent, 9, 3025 "BASE register [0x%x] asks for " 3026 "[0x%x]=[0x%x] (ROM)\n", 3027 PCI_CONF_ROM, request, 3028 (~(PCI_BASE_ROM_ADDR_M & request))+1); 3029 /* 3030 * Add to the "reg" property 3031 */ 3032 if (cardbus_update_reg_prop(new_child, 3033 request, 3034 PCI_CONF_ROM) != PCICFG_SUCCESS) { 3035 goto failedchild; 3036 } 3037 } 3038 } 3039 3040 (void) cardbus_config_teardown(&config_handle); 3041 3042 /* 3043 * Attach the child to its parent 3044 */ 3045 (void) i_ndi_config_node(new_child, DS_LINKED, 0); 3046 ndi_devi_exit(parent, circ); 3047 3048 return (PCICFG_SUCCESS); 3049 failedchild: 3050 /* 3051 * check if it should be taken offline (if online) 3052 */ 3053 (void) cardbus_config_teardown(&config_handle); 3054 3055 failedconfig: 3056 3057 (void) ndi_devi_free(new_child); 3058 ndi_devi_exit(parent, circ); 3059 3060 return (PCICFG_FAILURE); 3061 } 3062 3063 static int 3064 cardbus_add_config_reg(dev_info_t *dip, 3065 uint_t bus, uint_t device, uint_t func) 3066 { 3067 int reg[10] = { PCI_ADDR_CONFIG, 0, 0, 0, 0}; 3068 3069 reg[0] = PCICFG_MAKE_REG_HIGH(bus, device, func, 0); 3070 3071 return (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 3072 "reg", reg, 5)); 3073 } 3074 3075 static int 3076 cardbus_add_isa_node(cbus_t *cbp, dev_info_t *parent, struct isa_node *node) 3077 { 3078 dev_info_t *new_child; 3079 int ret; 3080 uint32_t reg[3]; 3081 3082 _NOTE(ARGUNUSED(cbp)) 3083 3084 cardbus_err(parent, 6, "cardbus_add_isa_node\n"); 3085 3086 /* 3087 * This node will be put immediately below 3088 * "parent". Allocate a blank device node. 3089 */ 3090 if (ndi_devi_alloc(parent, DEVI_PSEUDO_NEXNAME, 3091 (pnode_t)DEVI_SID_NODEID, 3092 &new_child) != NDI_SUCCESS) { 3093 cardbus_err(parent, 1, 3094 "cardbus_add_isa_child(): Failed to alloc child node\n"); 3095 return (PCICFG_FAILURE); 3096 } 3097 3098 /* 3099 * Set properties common to ISA devices 3100 */ 3101 if (cardbus_set_isa_props(parent, new_child, node->name, 3102 node->compatible) != PCICFG_SUCCESS) { 3103 cardbus_err(parent, 1, "Failed to set ISA properties\n"); 3104 goto failed; 3105 } 3106 3107 cardbus_err(new_child, 8, "--Leaf ISA device\n"); 3108 3109 /* 3110 * Add the "reg" property. 3111 */ 3112 reg[0] = 0; 3113 reg[1] = node->reg; 3114 reg[2] = node->span; 3115 3116 ret = ndi_prop_update_int_array(DDI_DEV_T_NONE, new_child, 3117 "basereg", (int *)reg, 3); 3118 if (ret != DDI_SUCCESS) 3119 goto failed; 3120 3121 (void) i_ndi_config_node(new_child, DS_LINKED, 0); 3122 3123 return (PCICFG_SUCCESS); 3124 3125 failed: 3126 (void) ndi_devi_free(new_child); 3127 3128 return (PCICFG_FAILURE); 3129 } 3130 3131 static int 3132 cardbus_config_setup(dev_info_t *dip, ddi_acc_handle_t *handle) 3133 { 3134 caddr_t cfgaddr; 3135 ddi_device_acc_attr_t attr; 3136 dev_info_t *anode; 3137 int status; 3138 int rlen; 3139 pci_regspec_t *reg; 3140 int ret; 3141 #ifdef sparc 3142 int16_t val; 3143 #endif 3144 3145 cardbus_err(dip, 10, 3146 "cardbus_config_setup(dip=0x%p)\n", (void *) dip); 3147 3148 /* 3149 * Get the pci register spec from the node 3150 */ 3151 status = ddi_getlongprop(DDI_DEV_T_NONE, 3152 dip, DDI_PROP_DONTPASS, "reg", 3153 (caddr_t)®, &rlen); 3154 3155 cardbus_err(dip, 10, 3156 "cardbus_config_setup, reg = 0x%p\n", (void *) reg); 3157 3158 switch (status) { 3159 case DDI_PROP_SUCCESS: 3160 break; 3161 case DDI_PROP_NO_MEMORY: 3162 cardbus_err(dip, 1, "reg present, but unable to get memory\n"); 3163 return (PCICFG_FAILURE); 3164 default: 3165 cardbus_err(dip, 1, "no reg property\n"); 3166 return (PCICFG_FAILURE); 3167 } 3168 3169 anode = dip; 3170 3171 /* 3172 * Find the attachment point node 3173 */ 3174 while ((anode != NULL) && (strcmp(ddi_binding_name(anode), 3175 "hp_attachment") != 0)) { 3176 anode = ddi_get_parent(anode); 3177 } 3178 3179 if (anode == NULL) { 3180 cardbus_err(dip, 1, "Tree not in PROBE state\n"); 3181 kmem_free((caddr_t)reg, rlen); 3182 return (PCICFG_FAILURE); 3183 } 3184 3185 if ((ret = ndi_prop_update_int_array(DDI_DEV_T_NONE, anode, 3186 "reg", (int *)reg, 5)) != 0) { 3187 cardbus_err(dip, 1, 3188 "Failed to update reg property, error code %d\n", ret); 3189 kmem_free((caddr_t)reg, rlen); 3190 return (PCICFG_FAILURE); 3191 } 3192 3193 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 3194 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 3195 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 3196 3197 if (ddi_regs_map_setup(anode, 0, &cfgaddr, 3198 0, /* PCI_CONF_HDR_SIZE */ 3199 0, 3200 &attr, handle) != DDI_SUCCESS) { 3201 cardbus_err(dip, 1, 3202 "Failed to setup registers for [0x%x][0x%x][0x%x]\n", 3203 PCI_REG_BUS_G(reg->pci_phys_hi), 3204 PCI_REG_DEV_G(reg->pci_phys_hi), 3205 PCI_REG_FUNC_G(reg->pci_phys_hi)); 3206 kmem_free((caddr_t)reg, rlen); 3207 return (PCICFG_FAILURE); 3208 } 3209 3210 cardbus_err(dip, 9, 3211 "PROBING =>->->->->->-> [0x%x][0x%x][0x%x] 0x%x 0x%p\n", 3212 PCI_REG_BUS_G(reg->pci_phys_hi), 3213 PCI_REG_DEV_G(reg->pci_phys_hi), 3214 PCI_REG_FUNC_G(reg->pci_phys_hi), 3215 reg->pci_phys_hi, (void *) cfgaddr); 3216 3217 /* 3218 * must do peek16 otherwise the system crashes when probing 3219 * a non zero function on a non-multi-function card. 3220 */ 3221 #ifdef sparc 3222 if (ddi_peek16(anode, (int16_t *)cfgaddr, &val) != DDI_SUCCESS) { 3223 cardbus_err(dip, 8, 3224 "cardbus_config_setup peek failed\n"); 3225 ret = PCICFG_NODEVICE; 3226 } else if (ddi_get16(*handle, (uint16_t *)cfgaddr) == 0xffff) { 3227 cardbus_err(dip, 8, 3228 "cardbus_config_setup PCICFG_NODEVICE\n"); 3229 ret = PCICFG_NODEVICE; 3230 #elif defined(__x86) 3231 if (ddi_get16(*handle, (uint16_t *)cfgaddr) == 0xffff) { 3232 cardbus_err(dip, 8, 3233 "cardbus_config_setup PCICFG_NODEVICE\n"); 3234 ret = PCICFG_NODEVICE; 3235 #endif 3236 } else { 3237 cardbus_err(dip, 1, 3238 "cardbus_config_setup found device at:[0x%x][0x%x][0x%x]\n", 3239 PCI_REG_BUS_G(reg->pci_phys_hi), 3240 PCI_REG_DEV_G(reg->pci_phys_hi), 3241 PCI_REG_FUNC_G(reg->pci_phys_hi)); 3242 3243 ret = PCICFG_SUCCESS; 3244 } 3245 3246 kmem_free((caddr_t)reg, rlen); 3247 if (ret != PCICFG_SUCCESS) { 3248 cardbus_config_teardown(handle); 3249 } 3250 3251 cardbus_err(dip, 7, 3252 "cardbus_config_setup returning %d\n", ret); 3253 3254 return (ret); 3255 } 3256 3257 static void 3258 cardbus_config_teardown(ddi_acc_handle_t *handle) 3259 { 3260 (void) ddi_regs_map_free(handle); 3261 } 3262 3263 static void 3264 cardbus_reparent_children(dev_info_t *dip, dev_info_t *parent) 3265 { 3266 dev_info_t *child; 3267 int circ; 3268 3269 while (child = ddi_get_child(dip)) { 3270 ASSERT(i_ddi_node_state(child) <= DS_LINKED); 3271 /* 3272 * Unlink node from tree before reparenting 3273 */ 3274 ndi_devi_enter(dip, &circ); 3275 (void) i_ndi_unconfig_node(child, DS_PROTO, 0); 3276 ndi_devi_exit(dip, circ); 3277 DEVI(child)->devi_parent = DEVI(parent); 3278 DEVI(child)->devi_bus_ctl = DEVI(parent); 3279 ndi_devi_enter(parent, &circ); 3280 (void) i_ndi_config_node(child, DS_LINKED, 0); 3281 ndi_devi_exit(parent, circ); 3282 } 3283 } 3284 3285 static int 3286 cardbus_update_assigned_prop(dev_info_t *dip, pci_regspec_t *newone) 3287 { 3288 int alen; 3289 pci_regspec_t *assigned; 3290 caddr_t newreg; 3291 uint_t status; 3292 3293 status = ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 3294 "assigned-addresses", (caddr_t)&assigned, &alen); 3295 switch (status) { 3296 case DDI_PROP_SUCCESS: 3297 cardbus_err(dip, 5, 3298 "cardbus_update_assigned_prop: found prop len %d\n", 3299 alen); 3300 /* 3301 * Allocate memory for the existing 3302 * assigned-addresses(s) plus one and then 3303 * build it. 3304 */ 3305 newreg = kmem_zalloc(alen+sizeof (*newone), KM_SLEEP); 3306 3307 bcopy(assigned, newreg, alen); 3308 bcopy(newone, newreg + alen, sizeof (*newone)); 3309 break; 3310 3311 case DDI_PROP_NO_MEMORY: 3312 cardbus_err(dip, 1, 3313 "no memory for assigned-addresses property\n"); 3314 return (PCICFG_FAILURE); 3315 3316 default: 3317 cardbus_err(dip, 5, 3318 "cardbus_update_assigned_prop: creating prop\n"); 3319 alen = 0; 3320 newreg = (caddr_t)newone; 3321 break; 3322 } 3323 3324 /* 3325 * Write out the new "assigned-addresses" spec 3326 */ 3327 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 3328 "assigned-addresses", (int *)newreg, 3329 (alen + sizeof (*newone))/sizeof (int)); 3330 3331 if (status == DDI_PROP_SUCCESS) 3332 kmem_free((caddr_t)newreg, alen+sizeof (*newone)); 3333 3334 if (alen) 3335 kmem_free(assigned, alen); 3336 3337 return (PCICFG_SUCCESS); 3338 } 3339 3340 static int 3341 cardbus_update_available_prop(dev_info_t *dip, uint32_t hi_type, 3342 uint64_t base, uint64_t size) 3343 { 3344 int alen, rlen; 3345 pci_regspec_t *available, *reg; 3346 pci_regspec_t addition; 3347 caddr_t newreg; 3348 uint_t status; 3349 3350 cardbus_err(dip, 6, "cardbus_update_available_prop\n"); 3351 3352 status = ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 3353 "reg", (caddr_t)®, &rlen); 3354 3355 switch (status) { 3356 case DDI_PROP_SUCCESS: 3357 break; 3358 case DDI_PROP_NO_MEMORY: 3359 cardbus_err(dip, 1, "reg present, but unable to get memory\n"); 3360 return (PCICFG_FAILURE); 3361 default: 3362 cardbus_err(dip, 1, "no reg property\n"); 3363 return (PCICFG_FAILURE); 3364 } 3365 3366 status = ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 3367 "available", (caddr_t)&available, &alen); 3368 switch (status) { 3369 case DDI_PROP_SUCCESS: 3370 break; 3371 case DDI_PROP_NO_MEMORY: 3372 cardbus_err(dip, 1, "no memory for available property\n"); 3373 kmem_free((caddr_t)reg, rlen); 3374 return (PCICFG_FAILURE); 3375 default: 3376 alen = 0; 3377 } 3378 3379 /* 3380 * Allocate memory for the existing 3381 * available(s) plus one and then 3382 * build it. 3383 */ 3384 newreg = kmem_zalloc(alen + sizeof (pci_regspec_t), KM_SLEEP); 3385 3386 /* 3387 * Build the regspec, then add it to the existing one(s) 3388 */ 3389 addition.pci_phys_hi = hi_type | 3390 PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi), 3391 PCI_REG_DEV_G(reg->pci_phys_hi), 3392 PCI_REG_FUNC_G(reg->pci_phys_hi), 0); 3393 3394 addition.pci_phys_mid = (uint32_t)((base>>32) & 0xffffffff); 3395 addition.pci_phys_low = (uint32_t)(base & 0xffffffff); 3396 addition.pci_size_hi = (uint32_t)((size>>32) & 0xffffffff); 3397 addition.pci_size_low = (uint32_t)(size & 0xffffffff); 3398 3399 #ifdef DEBUG 3400 cardbus_dump_reg(dip, &addition, 1); 3401 #endif 3402 3403 if (alen) 3404 bcopy(available, newreg, alen); 3405 bcopy(&addition, newreg + alen, sizeof (pci_regspec_t)); 3406 3407 /* 3408 * Write out the new "available" spec 3409 */ 3410 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 3411 "available", (int *)newreg, 3412 (alen + sizeof (pci_regspec_t))/sizeof (int)); 3413 3414 if (alen) 3415 kmem_free((caddr_t)available, alen); 3416 kmem_free((caddr_t)reg, rlen); 3417 kmem_free((caddr_t)newreg, alen + sizeof (pci_regspec_t)); 3418 3419 return (PCICFG_SUCCESS); 3420 } 3421 3422 static int 3423 cardbus_update_ranges_prop(dev_info_t *dip, cardbus_range_t *addition) 3424 { 3425 int rlen; 3426 cardbus_range_t *ranges; 3427 caddr_t newreg; 3428 uint_t status; 3429 #if defined(CARDBUS_DEBUG) 3430 int i, nrange; 3431 const cardbus_range_t *nr; 3432 #endif 3433 3434 cardbus_err(dip, 6, "cardbus_update_ranges_prop\n"); 3435 3436 status = ddi_getlongprop(DDI_DEV_T_NONE, 3437 dip, DDI_PROP_DONTPASS, "ranges", 3438 (caddr_t)&ranges, &rlen); 3439 3440 switch (status) { 3441 case DDI_PROP_SUCCESS: 3442 break; 3443 case DDI_PROP_NO_MEMORY: 3444 cardbus_err(dip, 1, 3445 "ranges present, but unable to get memory\n"); 3446 return (PCICFG_FAILURE); 3447 default: 3448 cardbus_err(dip, 8, "no ranges property - creating one\n"); 3449 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, 3450 dip, "ranges", (int *)addition, 3451 sizeof (cardbus_range_t)/sizeof (int)) 3452 != DDI_SUCCESS) { 3453 cardbus_err(dip, 1, "Did'nt create ranges property\n"); 3454 return (PCICFG_FAILURE); 3455 } 3456 return (PCICFG_SUCCESS); 3457 } 3458 3459 /* 3460 * Allocate memory for the existing reg(s) plus one and then 3461 * build it. 3462 */ 3463 newreg = kmem_zalloc(rlen+sizeof (cardbus_range_t), KM_SLEEP); 3464 3465 bcopy(ranges, newreg, rlen); 3466 bcopy(addition, newreg + rlen, sizeof (cardbus_range_t)); 3467 3468 /* 3469 * Write out the new "ranges" property 3470 */ 3471 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 3472 dip, "ranges", (int *)newreg, 3473 (rlen + sizeof (cardbus_range_t))/sizeof (int)); 3474 3475 #if defined(CARDBUS_DEBUG) 3476 cardbus_err(dip, 8, "cardbus_update_ranges_prop ranges property:\n"); 3477 3478 nrange = rlen / sizeof (cardbus_range_t); 3479 nr = (cardbus_range_t *)newreg; 3480 for (i = 0; i <= nrange; i++) { 3481 /* nrange is one higher for new entry */ 3482 cardbus_err(dip, 9, 3483 "\trange parent addr 0x%x.0x%x.0x%x " 3484 "child addr 0x%x.0x%x.0x%x size 0x%x.0x%x\n", 3485 nr->parent_hi, 3486 nr->parent_mid, nr->parent_lo, 3487 nr->child_hi, 3488 nr->child_mid, nr->child_lo, 3489 nr->size_hi, nr->size_lo); 3490 nr++; 3491 } 3492 #endif 3493 3494 kmem_free((caddr_t)newreg, rlen+sizeof (cardbus_range_t)); 3495 kmem_free((caddr_t)ranges, rlen); 3496 3497 return (PCICFG_SUCCESS); 3498 } 3499 3500 static int 3501 cardbus_update_reg_prop(dev_info_t *dip, uint32_t regvalue, uint_t reg_offset) 3502 { 3503 int rlen; 3504 pci_regspec_t *reg; 3505 caddr_t newreg; 3506 uint32_t hiword; 3507 pci_regspec_t addition; 3508 uint32_t size; 3509 uint_t status; 3510 3511 status = ddi_getlongprop(DDI_DEV_T_NONE, 3512 dip, DDI_PROP_DONTPASS, "reg", (caddr_t)®, &rlen); 3513 3514 switch (status) { 3515 case DDI_PROP_SUCCESS: 3516 break; 3517 case DDI_PROP_NO_MEMORY: 3518 cardbus_err(dip, 1, "reg present, but unable to get memory\n"); 3519 return (PCICFG_FAILURE); 3520 default: 3521 cardbus_err(dip, 1, "no reg property\n"); 3522 return (PCICFG_FAILURE); 3523 } 3524 3525 /* 3526 * Allocate memory for the existing reg(s) plus one and then 3527 * build it. 3528 */ 3529 newreg = kmem_zalloc(rlen+sizeof (pci_regspec_t), KM_SLEEP); 3530 3531 /* 3532 * Build the regspec, then add it to the existing one(s) 3533 */ 3534 hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi), 3535 PCI_REG_DEV_G(reg->pci_phys_hi), 3536 PCI_REG_FUNC_G(reg->pci_phys_hi), 3537 reg_offset); 3538 3539 if (reg_offset == PCI_CONF_ROM) { 3540 size = (~(PCI_BASE_ROM_ADDR_M & regvalue))+1; 3541 hiword |= PCI_ADDR_MEM32; 3542 } else { 3543 size = (~(PCI_BASE_M_ADDR_M & regvalue))+1; 3544 3545 if ((PCI_BASE_SPACE_M & regvalue) == PCI_BASE_SPACE_MEM) { 3546 if ((PCI_BASE_TYPE_M & regvalue) == PCI_BASE_TYPE_MEM) { 3547 hiword |= PCI_ADDR_MEM32; 3548 } else if ((PCI_BASE_TYPE_M & regvalue) 3549 == PCI_BASE_TYPE_ALL) { 3550 /* 3551 * This is a 64 bit PCI memory space. 3552 * It needs to be allocated as 32 bit 3553 * for bus map purposes. 3554 */ 3555 hiword |= PCI_ADDR_MEM32; 3556 } 3557 } else { 3558 hiword |= PCI_ADDR_IO; 3559 } 3560 } 3561 3562 addition.pci_phys_hi = hiword; 3563 addition.pci_phys_mid = 0; 3564 addition.pci_phys_low = 0; 3565 addition.pci_size_hi = 0; 3566 addition.pci_size_low = size; 3567 3568 cardbus_err(dip, 8, 3569 "cardbus_update_reg_prop, phys_hi 0x%08x," 3570 " phys_mid 0x%08x, phys_low 0x%08x, size_hi 0x%08x," 3571 " size_low 0x%08x\n", hiword, 0, 0, 0, size); 3572 3573 bcopy(reg, newreg, rlen); 3574 bcopy(&addition, newreg + rlen, sizeof (pci_regspec_t)); 3575 3576 /* 3577 * Write out the new "reg" property 3578 */ 3579 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 3580 dip, "reg", (int *)newreg, 3581 (rlen + sizeof (pci_regspec_t))/sizeof (int)); 3582 3583 kmem_free((caddr_t)reg, rlen); 3584 kmem_free((caddr_t)newreg, rlen+sizeof (pci_regspec_t)); 3585 3586 return (PCICFG_SUCCESS); 3587 } 3588 3589 /* 3590 * Setup the basic 1275 properties based on information found in the config 3591 * header of the PCI device 3592 */ 3593 static int 3594 cardbus_set_standard_props(dev_info_t *parent, dev_info_t *dip, 3595 ddi_acc_handle_t config_handle) 3596 { 3597 int ret; 3598 uint16_t val; 3599 uint32_t wordval; 3600 uint8_t byteval; 3601 3602 /* These two exists only for non-bridges */ 3603 if ((pci_config_get8(config_handle, 3604 PCI_CONF_HEADER) & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 3605 byteval = pci_config_get8(config_handle, PCI_CONF_MIN_G); 3606 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3607 "min-grant", byteval)) != DDI_SUCCESS) { 3608 cardbus_err(dip, 1, "Failed to sent min-grant\n"); 3609 return (ret); 3610 } 3611 3612 byteval = pci_config_get8(config_handle, PCI_CONF_MAX_L); 3613 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3614 "max-latency", byteval)) != DDI_SUCCESS) { 3615 return (ret); 3616 } 3617 } 3618 3619 /* 3620 * These should always exist and have the value of the 3621 * corresponding register value 3622 */ 3623 val = pci_config_get16(config_handle, PCI_CONF_VENID); 3624 3625 /* 3626 * according to section 6.2.1 of revision 2 of the PCI local 3627 * bus specification - 0FFFFh is an invalid value for the vendor ID 3628 */ 3629 if (val == 0xffff) { 3630 cardbus_err(dip, 1, "Illegal vendor-id 0x%x\n", val); 3631 return (PCICFG_FAILURE); 3632 } 3633 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3634 "vendor-id", val)) != DDI_SUCCESS) { 3635 return (ret); 3636 } 3637 3638 val = pci_config_get16(config_handle, PCI_CONF_DEVID); 3639 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3640 "device-id", val)) != DDI_SUCCESS) { 3641 return (ret); 3642 } 3643 byteval = pci_config_get8(config_handle, PCI_CONF_REVID); 3644 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3645 "revision-id", byteval)) != DDI_SUCCESS) { 3646 return (ret); 3647 } 3648 3649 wordval = (pci_config_get16(config_handle, PCI_CONF_SUBCLASS)<< 8) | 3650 (pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 3651 3652 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3653 "class-code", wordval)) != DDI_SUCCESS) { 3654 return (ret); 3655 } 3656 val = (pci_config_get16(config_handle, 3657 PCI_CONF_STAT) & PCI_STAT_DEVSELT) >> 9; 3658 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3659 "devsel-speed", val)) != DDI_SUCCESS) { 3660 return (ret); 3661 } 3662 3663 /* 3664 * The next three are bits set in the status register. The property is 3665 * present (but with no value other than its own existence) if the bit 3666 * is set, non-existent otherwise 3667 */ 3668 if (ddi_prop_exists(DDI_DEV_T_ANY, parent, DDI_PROP_DONTPASS, 3669 "fast-back-to-back") && 3670 pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_FBBC) { 3671 3672 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3673 "fast-back-to-back", 0)) != DDI_SUCCESS) { 3674 return (ret); 3675 } 3676 } 3677 if (pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_66MHZ) { 3678 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3679 "66mhz-capable", 0)) != DDI_SUCCESS) { 3680 return (ret); 3681 } 3682 } 3683 if (pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_UDF) { 3684 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3685 "udf-supported", 0)) != DDI_SUCCESS) { 3686 return (ret); 3687 } 3688 } 3689 3690 /* 3691 * These next three are optional and are not present 3692 * if the corresponding register is zero. If the value 3693 * is non-zero then the property exists with the value 3694 * of the register. 3695 */ 3696 3697 /* look in the correct place for header type 2 */ 3698 byteval = pci_config_get8(config_handle, PCI_CONF_HEADER); 3699 if ((byteval & PCI_HEADER_TYPE_M) == PCI_HEADER_TWO) { 3700 if ((val = pci_config_get16(config_handle, 3701 PCI_CBUS_SUBVENID)) != 0) { 3702 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3703 "subsystem-vendor-id", val)) != DDI_SUCCESS) { 3704 return (ret); 3705 } 3706 } 3707 if ((val = pci_config_get16(config_handle, 3708 PCI_CBUS_SUBSYSID)) != 0) { 3709 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3710 "subsystem-id", val)) != DDI_SUCCESS) { 3711 return (ret); 3712 } 3713 } 3714 } else { 3715 if ((val = pci_config_get16(config_handle, 3716 PCI_CONF_SUBVENID)) != 0) { 3717 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3718 "subsystem-vendor-id", val)) != DDI_SUCCESS) { 3719 return (ret); 3720 } 3721 } 3722 if ((val = pci_config_get16(config_handle, 3723 PCI_CONF_SUBSYSID)) != 0) { 3724 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3725 "subsystem-id", val)) != DDI_SUCCESS) { 3726 return (ret); 3727 } 3728 } 3729 } 3730 3731 if ((val = pci_config_get8(config_handle, 3732 PCI_CONF_CACHE_LINESZ)) != 0) { 3733 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3734 "cache-line-size", val)) != DDI_SUCCESS) { 3735 return (ret); 3736 } 3737 } 3738 3739 /* 3740 * If the Interrupt Pin register is non-zero then the 3741 * interrupts property exists 3742 */ 3743 if ((byteval = pci_config_get8(config_handle, PCI_CONF_IPIN)) != 0) { 3744 /* 3745 * If interrupt pin is non-zero, 3746 * record the interrupt line used 3747 */ 3748 cardbus_err(dip, 8, "Adding interrupts property\n"); 3749 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3750 "interrupts", byteval)) != DDI_SUCCESS) { 3751 return (ret); 3752 } 3753 } 3754 return (PCICFG_SUCCESS); 3755 } 3756 3757 /* 3758 * Setup the basic properties required by the ISA node. 3759 */ 3760 static int 3761 cardbus_set_isa_props(dev_info_t *parent, dev_info_t *dip, 3762 char *name, char *compat[]) 3763 { 3764 int ret, n; 3765 3766 _NOTE(ARGUNUSED(parent)) 3767 3768 cardbus_err(dip, 8, "Adding interrupts property\n"); 3769 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3770 "interrupts", 1)) != DDI_SUCCESS) { 3771 return (ret); 3772 } 3773 3774 /* 3775 * The node name field needs to be filled in with the name 3776 */ 3777 if (ndi_devi_set_nodename(dip, name, 0) != NDI_SUCCESS) { 3778 cardbus_err(dip, 1, "Failed to set nodename for node\n"); 3779 return (PCICFG_FAILURE); 3780 } 3781 3782 /* 3783 * Create the compatible property as an array of pointers 3784 * to strings. Start with the buffer created above. 3785 */ 3786 n = 0; 3787 while (compat[n] != NULL) 3788 n++; 3789 3790 if (n != 0) 3791 if ((ret = ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 3792 "compatible", compat, n)) != DDI_SUCCESS) 3793 return (ret); 3794 3795 return (PCICFG_SUCCESS); 3796 } 3797 3798 static int 3799 cardbus_set_busnode_props(dev_info_t *dip) 3800 { 3801 cardbus_err(dip, 6, "cardbus_set_busnode_props\n"); 3802 3803 cardbus_force_stringprop(dip, "device_type", "pci"); 3804 3805 if (ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3806 "#address-cells", 3) != DDI_SUCCESS) { 3807 cardbus_err(dip, 4, "Failed to set #address-cells\n"); 3808 } 3809 if (ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3810 "#size-cells", 2) != DDI_SUCCESS) { 3811 cardbus_err(dip, 4, "Failed to set #size-cells\n"); 3812 } 3813 return (PCICFG_SUCCESS); 3814 } 3815 3816 static int 3817 cardbus_set_busnode_isaprops(dev_info_t *dip) 3818 { 3819 cardbus_err(dip, 6, "cardbus_set_busnode_props\n"); 3820 3821 cardbus_force_stringprop(dip, "device_type", "isa"); 3822 3823 if (ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3824 "#address-cells", 2) != DDI_SUCCESS) { 3825 cardbus_err(dip, 4, "Failed to set #address-cells\n"); 3826 } 3827 if (ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3828 "#size-cells", 1) != DDI_SUCCESS) { 3829 cardbus_err(dip, 4, "Failed to set #size-cells\n"); 3830 } 3831 return (PCICFG_SUCCESS); 3832 } 3833 3834 /* 3835 * Use cb%x,%x rather than pci%x,%x so that we can use specific cardbus 3836 * drivers in /etc/driver_aliases if required 3837 */ 3838 static int 3839 cardbus_set_childnode_props(dev_info_t *dip, ddi_acc_handle_t config_handle) 3840 { 3841 int ret; 3842 #ifndef _DONT_USE_1275_GENERIC_NAMES 3843 uint32_t wordval; 3844 #endif 3845 char *name; 3846 char buffer[64]; 3847 uint32_t classcode; 3848 char *compat[8]; 3849 int i, n; 3850 uint16_t subsysid, subvenid, devid, venid; 3851 uint8_t header_type; 3852 3853 /* 3854 * NOTE: These are for both a child and PCI-PCI bridge node 3855 */ 3856 #ifndef _DONT_USE_1275_GENERIC_NAMES 3857 wordval = (pci_config_get16(config_handle, PCI_CONF_SUBCLASS)<< 8) | 3858 (pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 3859 #endif 3860 3861 /* Cardbus support */ 3862 venid = pci_config_get16(config_handle, PCI_CONF_VENID); 3863 devid = pci_config_get16(config_handle, PCI_CONF_DEVID); 3864 3865 header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 3866 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_TWO) { 3867 subvenid = pci_config_get16(config_handle, PCI_CBUS_SUBVENID); 3868 subsysid = pci_config_get16(config_handle, PCI_CBUS_SUBSYSID); 3869 } else { 3870 subvenid = pci_config_get16(config_handle, PCI_CONF_SUBVENID); 3871 subsysid = pci_config_get16(config_handle, PCI_CONF_SUBSYSID); 3872 } 3873 3874 if (subsysid != 0) { 3875 (void) sprintf(buffer, "pci%x,%x", subvenid, subsysid); 3876 } else { 3877 (void) sprintf(buffer, "pci%x,%x", venid, devid); 3878 } 3879 3880 cardbus_err(dip, 8, "Childname is %s\n", buffer); 3881 3882 /* 3883 * In some environments, trying to use "generic" 1275 names is 3884 * not the convention. In those cases use the name as created 3885 * above. In all the rest of the cases, check to see if there 3886 * is a generic name first. 3887 */ 3888 #ifdef _DONT_USE_1275_GENERIC_NAMES 3889 name = buffer; 3890 #else 3891 if ((name = cardbus_get_class_name(wordval>>8)) == NULL) { 3892 /* 3893 * Set name to the above fabricated name 3894 */ 3895 name = buffer; 3896 } 3897 3898 cardbus_err(dip, 8, "Set nodename to %s\n", name); 3899 #endif 3900 3901 /* 3902 * The node name field needs to be filled in with the name 3903 */ 3904 if (ndi_devi_set_nodename(dip, name, 0) != NDI_SUCCESS) { 3905 cardbus_err(dip, 1, "Failed to set nodename for node\n"); 3906 return (PCICFG_FAILURE); 3907 } 3908 3909 /* 3910 * Create the compatible property as an array of pointers 3911 * to strings. Start with the cb name. 3912 */ 3913 n = 0; 3914 3915 if (subsysid != 0) { 3916 (void) sprintf(buffer, "cb%x,%x", subvenid, subsysid); 3917 } else { 3918 (void) sprintf(buffer, "cb%x,%x", venid, devid); 3919 } 3920 3921 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3922 (void) strcpy(compat[n++], buffer); 3923 3924 if (subsysid != 0) { 3925 /* 3926 * Add subsys numbers as pci compatible. 3927 */ 3928 (void) sprintf(buffer, "pci%x,%x", subvenid, subsysid); 3929 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3930 (void) strcpy(compat[n++], buffer); 3931 } 3932 3933 /* 3934 * Add in the VendorID/DeviceID compatible name. 3935 */ 3936 (void) sprintf(buffer, "pci%x,%x", venid, devid); 3937 3938 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3939 (void) strcpy(compat[n++], buffer); 3940 3941 classcode = (pci_config_get16(config_handle, PCI_CONF_SUBCLASS)<< 8) | 3942 (pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 3943 3944 /* 3945 * Add in the Classcode 3946 */ 3947 (void) sprintf(buffer, "pciclass,%06x", classcode); 3948 3949 cardbus_err(dip, 8, "class code %s\n", buffer); 3950 3951 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3952 (void) strcpy(compat[n++], buffer); 3953 3954 if ((ret = ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 3955 "compatible", (char **)compat, n)) != DDI_SUCCESS) { 3956 return (ret); 3957 } 3958 3959 for (i = 0; i < n; i++) { 3960 kmem_free(compat[i], strlen(compat[i]) + 1); 3961 } 3962 3963 return (PCICFG_SUCCESS); 3964 } 3965 3966 /* 3967 * Program the bus numbers into the bridge 3968 */ 3969 static void 3970 cardbus_set_bus_numbers(ddi_acc_handle_t config_handle, 3971 uint_t primary, uint_t secondary) 3972 { 3973 cardbus_err(NULL, 8, 3974 "cardbus_set_bus_numbers [%d->%d]\n", primary, secondary); 3975 3976 /* 3977 * Primary bus# 3978 */ 3979 pci_config_put8(config_handle, PCI_BCNF_PRIBUS, primary); 3980 3981 /* 3982 * Secondary bus# 3983 */ 3984 pci_config_put8(config_handle, PCI_BCNF_SECBUS, secondary); 3985 3986 /* 3987 * Set the subordinate bus number to ff in order to pass through any 3988 * type 1 cycle with a bus number higher than the secondary bus# 3989 * Note that this is reduced once the probe is complete in the 3990 * cardbus_setup_bridge() function. 3991 */ 3992 pci_config_put8(config_handle, PCI_BCNF_SUBBUS, 0xFF); 3993 } 3994 3995 static void 3996 enable_pci_isa_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 3997 { 3998 uint16_t comm, stat; 3999 4000 stat = pci_config_get16(config_handle, PCI_CONF_STAT); 4001 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4002 4003 /* 4004 * Enable memory, IO, bus mastership and error detection. 4005 */ 4006 comm |= (PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO | 4007 PCI_COMM_PARITY_DETECT | PCI_COMM_SERR_ENABLE); 4008 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 4009 "fast-back-to-back")) 4010 comm |= PCI_COMM_BACK2BACK_ENAB; 4011 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4012 cardbus_err(NULL, 8, 4013 "enable_pci_isa_bridge stat 0x%04x comm 0x%04x\n", stat, comm); 4014 4015 /* 4016 * ITE8888 Specific registers. 4017 */ 4018 pci_config_put8(config_handle, 0x50, 0x00); /* Timing Control */ 4019 pci_config_put8(config_handle, 0x52, 0x00); /* Master DMA Access */ 4020 pci_config_put8(config_handle, 0x53, 0x01); /* ROMCS */ 4021 } 4022 4023 static void 4024 enable_pci_pci_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 4025 { 4026 uint16_t comm, stat, bctrl; 4027 4028 stat = pci_config_get16(config_handle, PCI_CONF_STAT); 4029 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4030 bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL); 4031 4032 comm &= ~(PCI_COMM_IO | PCI_COMM_MAE); 4033 comm |= (PCI_COMM_ME | PCI_COMM_PARITY_DETECT | PCI_COMM_SERR_ENABLE); 4034 4035 /* 4036 * Enable back to back. 4037 */ 4038 if (stat & PCI_STAT_FBBC) 4039 comm |= PCI_COMM_BACK2BACK_ENAB; 4040 4041 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4042 4043 /* 4044 * Reset the sub-ordinate bus. 4045 */ 4046 if (!(bctrl & PCI_BCNF_BCNTRL_RESET)) 4047 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, 4048 bctrl | PCI_BCNF_BCNTRL_RESET); 4049 else 4050 bctrl &= ~PCI_BCNF_BCNTRL_RESET; 4051 4052 /* 4053 * Enable error reporting. 4054 */ 4055 bctrl |= (PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE | 4056 PCI_BCNF_BCNTRL_MAST_AB_MODE); 4057 4058 /* 4059 * Enable back to back on secondary bus. 4060 */ 4061 if (stat & PCI_STAT_FBBC) 4062 bctrl |= PCI_BCNF_BCNTRL_B2B_ENAB; 4063 4064 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl); 4065 cardbus_err(dip, 8, 4066 "enable_pci_pci_bridge stat 0x%04x comm 0x%04x bctrl 0x%04x\n", 4067 stat, comm, bctrl); 4068 } 4069 4070 static int cardbus_reset_wait = 20; 4071 4072 static void 4073 enable_cardbus_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 4074 { 4075 uint16_t comm, stat, bctrl; 4076 4077 stat = pci_config_get16(config_handle, PCI_CONF_STAT); 4078 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4079 bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL); 4080 4081 /* 4082 * Don't mess with the command register on the cardbus bridge 4083 * itself. This should have been done when it's parent 4084 * did the setup. Some devices *require* certain things to 4085 * disabled, this can be done using the "command-preserve" 4086 * property and if we mess with it here it breaks that. 4087 * 4088 * comm |= (PCI_COMM_ME | PCI_COMM_PARITY_DETECT | 4089 * PCI_COMM_SERR_ENABLE); 4090 */ 4091 4092 /* 4093 * Reset the sub-ordinate bus. 4094 */ 4095 if (!(bctrl & PCI_BCNF_BCNTRL_RESET)) 4096 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, 4097 bctrl | PCI_BCNF_BCNTRL_RESET); 4098 else 4099 bctrl &= ~PCI_BCNF_BCNTRL_RESET; 4100 4101 /* 4102 * Turn off pre-fetch. 4103 */ 4104 bctrl &= ~(CB_BCNF_BCNTRL_MEM0_PREF | CB_BCNF_BCNTRL_MEM1_PREF | 4105 PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE); 4106 4107 /* 4108 * Enable error reporting. 4109 */ 4110 bctrl |= (PCI_BCNF_BCNTRL_MAST_AB_MODE | CB_BCNF_BCNTRL_WRITE_POST); 4111 if (comm & PCI_COMM_PARITY_DETECT) 4112 bctrl |= PCI_BCNF_BCNTRL_PARITY_ENABLE; 4113 if (comm & PCI_COMM_SERR_ENABLE) 4114 bctrl |= PCI_BCNF_BCNTRL_SERR_ENABLE; 4115 4116 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl); 4117 pci_config_put8(config_handle, PCI_CBUS_LATENCY_TIMER, 4118 cardbus_latency_timer); 4119 4120 pci_config_put16(config_handle, PCI_CONF_STAT, stat); 4121 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4122 4123 cardbus_err(dip, 8, 4124 "enable_cardbus_bridge() stat 0x%04x comm 0x%04x bctrl 0x%04x\n", 4125 stat, comm, bctrl); 4126 4127 /* after resetting the bridge, wait for everything to stablize */ 4128 delay(drv_usectohz(cardbus_reset_wait * 1000)); 4129 4130 } 4131 4132 static void 4133 disable_pci_pci_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 4134 { 4135 uint16_t comm, bctrl; 4136 4137 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4138 bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL); 4139 4140 /* 4141 * Turn off subordinate bus access. 4142 */ 4143 pci_config_put8(config_handle, PCI_BCNF_SECBUS, 0); 4144 pci_config_put8(config_handle, PCI_BCNF_SUBBUS, 0); 4145 4146 /* 4147 * Disable error reporting. 4148 */ 4149 bctrl &= ~(PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE | 4150 PCI_BCNF_BCNTRL_MAST_AB_MODE); 4151 comm = 0; 4152 4153 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4154 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl); 4155 4156 cardbus_err(dip, 6, 4157 "disable_pci_pci_bridge() stat 0x%04x comm 0x%04x bctrl 0x%04x\n", 4158 pci_config_get16(config_handle, PCI_CONF_STAT), comm, bctrl); 4159 } 4160 4161 static void 4162 disable_cardbus_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 4163 { 4164 uint16_t comm, bctrl; 4165 4166 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4167 bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL); 4168 4169 /* 4170 * Turn off subordinate bus access. 4171 */ 4172 pci_config_put8(config_handle, PCI_BCNF_SECBUS, 0); 4173 pci_config_put8(config_handle, PCI_BCNF_SUBBUS, 0); 4174 4175 /* 4176 * Disable error reporting. 4177 */ 4178 bctrl &= ~(PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE | 4179 PCI_BCNF_BCNTRL_MAST_AB_MODE); 4180 4181 pci_config_put32(config_handle, PCI_CBUS_MEM_LIMIT0, 0); 4182 pci_config_put32(config_handle, PCI_CBUS_MEM_BASE0, 0); 4183 pci_config_put32(config_handle, PCI_CBUS_IO_LIMIT0, 0); 4184 pci_config_put32(config_handle, PCI_CBUS_IO_BASE0, 0); 4185 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4186 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl); 4187 4188 cardbus_err(dip, 6, 4189 "disable_cardbus_bridge() stat 0x%04x comm 0x%04x bctrl 0x%04x\n", 4190 pci_config_get16(config_handle, PCI_CONF_STAT), comm, bctrl); 4191 } 4192 4193 static void 4194 enable_cardbus_device(dev_info_t *dip, ddi_acc_handle_t config_handle) 4195 { 4196 uint16_t comm, stat; 4197 4198 stat = pci_config_get16(config_handle, PCI_CONF_STAT); 4199 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4200 4201 /* 4202 * Enable memory, IO, bus mastership and error detection. 4203 */ 4204 comm |= (PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO | 4205 PCI_COMM_PARITY_DETECT | PCI_COMM_SERR_ENABLE); 4206 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 4207 "fast-back-to-back")) 4208 comm |= PCI_COMM_BACK2BACK_ENAB; 4209 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4210 cardbus_err(NULL, 8, 4211 "enable_cardbus_device stat 0x%04x comm 0x%04x\n", stat, comm); 4212 } 4213 4214 static void 4215 disable_cardbus_device(ddi_acc_handle_t config_handle) 4216 { 4217 cardbus_err(NULL, 8, "disable_cardbus_device\n"); 4218 4219 /* 4220 * Turn off everything in the command register. 4221 */ 4222 pci_config_put16(config_handle, PCI_CONF_COMM, 0x0); 4223 } 4224 4225 #ifndef _DONT_USE_1275_GENERIC_NAMES 4226 static char * 4227 cardbus_get_class_name(uint32_t classcode) 4228 { 4229 struct cardbus_name_entry *ptr; 4230 4231 for (ptr = &cardbus_class_lookup[0]; ptr->name != NULL; ptr++) { 4232 if (ptr->class_code == classcode) { 4233 return (ptr->name); 4234 } 4235 } 4236 return (NULL); 4237 } 4238 #endif /* _DONT_USE_1275_GENERIC_NAMES */ 4239 4240 static void 4241 cardbus_force_boolprop(dev_info_t *dip, char *pname) 4242 { 4243 int ret; 4244 4245 if ((ret = ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 4246 pname)) != DDI_SUCCESS) { 4247 if (ret == DDI_PROP_NOT_FOUND) 4248 if (ddi_prop_create(DDI_DEV_T_NONE, dip, 4249 DDI_PROP_CANSLEEP, pname, 4250 (caddr_t)NULL, 0) != DDI_SUCCESS) 4251 cardbus_err(dip, 4, 4252 "Failed to set boolean property " 4253 "\"%s\"\n", pname); 4254 } 4255 } 4256 4257 static void 4258 cardbus_force_intprop(dev_info_t *dip, char *pname, int *pval, int len) 4259 { 4260 int ret; 4261 4262 if ((ret = ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 4263 pname, pval, len)) != DDI_SUCCESS) { 4264 if (ret == DDI_PROP_NOT_FOUND) 4265 if (ddi_prop_create(DDI_DEV_T_NONE, dip, 4266 DDI_PROP_CANSLEEP, pname, 4267 (caddr_t)pval, len*sizeof (int)) 4268 != DDI_SUCCESS) 4269 cardbus_err(dip, 4, 4270 "Failed to set int property \"%s\"\n", 4271 pname); 4272 } 4273 } 4274 4275 static void 4276 cardbus_force_stringprop(dev_info_t *dip, char *pname, char *pval) 4277 { 4278 int ret; 4279 4280 if ((ret = ndi_prop_update_string(DDI_DEV_T_NONE, dip, 4281 pname, pval)) != DDI_SUCCESS) { 4282 if (ret == DDI_PROP_NOT_FOUND) 4283 if (ddi_prop_create(DDI_DEV_T_NONE, dip, 4284 DDI_PROP_CANSLEEP, pname, 4285 pval, strlen(pval) + 1) != DDI_SUCCESS) 4286 cardbus_err(dip, 4, 4287 "Failed to set string property " 4288 "\"%s\" to \"%s\"\n", 4289 pname, pval); 4290 } 4291 } 4292 4293 static void 4294 split_addr(char *naddr, int *dev, int *func) 4295 { 4296 char c; 4297 int *ip = dev; 4298 4299 *dev = 0; 4300 *func = 0; 4301 4302 while (c = *naddr++) { 4303 if (c == ',') { 4304 ip = func; 4305 continue; 4306 } 4307 if (c >= '0' && c <= '9') { 4308 *ip = (*ip * 16) + (c - '0'); 4309 } else if (c >= 'a' && c <= 'f') { 4310 *ip = (*ip * 16) + 10 + (c - 'a'); 4311 } else 4312 break; 4313 } 4314 } 4315 4316 #ifdef DEBUG 4317 static void 4318 cardbus_dump_common_config(ddi_acc_handle_t config_handle) 4319 { 4320 cardbus_err(NULL, 1, 4321 " Vendor ID = [0x%04x] " 4322 "Device ID = [0x%04x]\n", 4323 pci_config_get16(config_handle, PCI_CONF_VENID), 4324 pci_config_get16(config_handle, PCI_CONF_DEVID)); 4325 cardbus_err(NULL, 1, 4326 " Command REG = [0x%04x] " 4327 "Status REG = [0x%04x]\n", 4328 pci_config_get16(config_handle, PCI_CONF_COMM), 4329 pci_config_get16(config_handle, PCI_CONF_STAT)); 4330 cardbus_err(NULL, 1, 4331 " Revision ID = [0x%02x] " 4332 "Prog Class = [0x%02x]\n", 4333 pci_config_get8(config_handle, PCI_CONF_REVID), 4334 pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 4335 cardbus_err(NULL, 1, 4336 " Dev Class = [0x%02x] " 4337 "Base Class = [0x%02x]\n", 4338 pci_config_get8(config_handle, PCI_CONF_SUBCLASS), 4339 pci_config_get8(config_handle, PCI_CONF_BASCLASS)); 4340 cardbus_err(NULL, 1, 4341 " Cache LnSz = [0x%02x] " 4342 "Latency Tmr = [0x%02x]\n", 4343 pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ), 4344 pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER)); 4345 cardbus_err(NULL, 1, 4346 " Header Type = [0x%02x] " 4347 "BIST = [0x%02x]\n", 4348 pci_config_get8(config_handle, PCI_CONF_HEADER), 4349 pci_config_get8(config_handle, PCI_CONF_BIST)); 4350 } 4351 4352 static void 4353 cardbus_dump_device_config(ddi_acc_handle_t config_handle) 4354 { 4355 cardbus_dump_common_config(config_handle); 4356 4357 cardbus_err(NULL, 1, 4358 " BASE 0 = [0x%08x] BASE 1 = [0x%08x]\n", 4359 pci_config_get32(config_handle, PCI_CONF_BASE0), 4360 pci_config_get32(config_handle, PCI_CONF_BASE1)); 4361 cardbus_err(NULL, 1, 4362 " BASE 2 = [0x%08x] BASE 3 = [0x%08x]\n", 4363 pci_config_get32(config_handle, PCI_CONF_BASE2), 4364 pci_config_get32(config_handle, PCI_CONF_BASE3)); 4365 cardbus_err(NULL, 1, 4366 " BASE 4 = [0x%08x] BASE 5 = [0x%08x]\n", 4367 pci_config_get32(config_handle, PCI_CONF_BASE4), 4368 pci_config_get32(config_handle, PCI_CONF_BASE5)); 4369 cardbus_err(NULL, 1, 4370 " Cardbus CIS = [0x%08x] ROM = [0x%08x]\n", 4371 pci_config_get32(config_handle, PCI_CONF_CIS), 4372 pci_config_get32(config_handle, PCI_CONF_ROM)); 4373 cardbus_err(NULL, 1, 4374 " Sub VID = [0x%04x] Sub SID = [0x%04x]\n", 4375 pci_config_get16(config_handle, PCI_CONF_SUBVENID), 4376 pci_config_get16(config_handle, PCI_CONF_SUBSYSID)); 4377 cardbus_err(NULL, 1, 4378 " I Line = [0x%02x] I Pin = [0x%02x]\n", 4379 pci_config_get8(config_handle, PCI_CONF_ILINE), 4380 pci_config_get8(config_handle, PCI_CONF_IPIN)); 4381 cardbus_err(NULL, 1, 4382 " Max Grant = [0x%02x] Max Latent = [0x%02x]\n", 4383 pci_config_get8(config_handle, PCI_CONF_MIN_G), 4384 pci_config_get8(config_handle, PCI_CONF_MAX_L)); 4385 } 4386 4387 static void 4388 cardbus_dump_bridge_config(ddi_acc_handle_t config_handle, 4389 uint8_t header_type) 4390 { 4391 if (header_type == PCI_HEADER_PPB) { 4392 cardbus_dump_common_config(config_handle); 4393 cardbus_err(NULL, 1, 4394 "........................................\n"); 4395 } else { 4396 cardbus_dump_common_config(config_handle); 4397 cardbus_err(NULL, 1, 4398 " Mem Base = [0x%08x] CBus Status = [0x%04x]\n", 4399 pci_config_get32(config_handle, PCI_CBUS_SOCK_REG), 4400 pci_config_get16(config_handle, PCI_CBUS_SEC_STATUS)); 4401 } 4402 4403 cardbus_err(NULL, 1, 4404 " Pri Bus = [0x%02x] Sec Bus = [0x%02x]\n", 4405 pci_config_get8(config_handle, PCI_BCNF_PRIBUS), 4406 pci_config_get8(config_handle, PCI_BCNF_SECBUS)); 4407 cardbus_err(NULL, 1, 4408 " Sub Bus = [0x%02x] Sec Latency = [0x%02x]\n", 4409 pci_config_get8(config_handle, PCI_BCNF_SUBBUS), 4410 pci_config_get8(config_handle, PCI_BCNF_LATENCY_TIMER)); 4411 4412 switch (header_type) { 4413 case PCI_HEADER_PPB: 4414 cardbus_err(NULL, 1, 4415 " I/O Base LO = [0x%02x] I/O Lim LO = [0x%02x]\n", 4416 pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW), 4417 pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW)); 4418 cardbus_err(NULL, 1, 4419 " Sec. Status = [0x%04x]\n", 4420 pci_config_get16(config_handle, PCI_BCNF_SEC_STATUS)); 4421 cardbus_err(NULL, 1, 4422 " Mem Base = [0x%04x] Mem Limit = [0x%04x]\n", 4423 pci_config_get16(config_handle, PCI_BCNF_MEM_BASE), 4424 pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT)); 4425 cardbus_err(NULL, 1, 4426 " PF Mem Base = [0x%04x] PF Mem Lim = [0x%04x]\n", 4427 pci_config_get16(config_handle, PCI_BCNF_PF_BASE_LOW), 4428 pci_config_get16(config_handle, PCI_BCNF_PF_LIMIT_LOW)); 4429 cardbus_err(NULL, 1, 4430 " PF Base HI = [0x%08x] PF Lim HI = [0x%08x]\n", 4431 pci_config_get32(config_handle, PCI_BCNF_PF_BASE_HIGH), 4432 pci_config_get32(config_handle, PCI_BCNF_PF_LIMIT_HIGH)); 4433 cardbus_err(NULL, 1, 4434 " I/O Base HI = [0x%04x] I/O Lim HI = [0x%04x]\n", 4435 pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI), 4436 pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI)); 4437 cardbus_err(NULL, 1, 4438 " ROM addr = [0x%08x]\n", 4439 pci_config_get32(config_handle, PCI_BCNF_ROM)); 4440 break; 4441 case PCI_HEADER_CARDBUS: 4442 cardbus_err(NULL, 1, 4443 " Mem Base 0 = [0x%08x] Mem Limit 0 = [0x%08x]\n", 4444 pci_config_get32(config_handle, PCI_CBUS_MEM_BASE0), 4445 pci_config_get32(config_handle, PCI_CBUS_MEM_LIMIT0)); 4446 cardbus_err(NULL, 1, 4447 " Mem Base 1 = [0x%08x] Mem Limit 1 = [0x%08x]\n", 4448 pci_config_get32(config_handle, PCI_CBUS_MEM_BASE1), 4449 pci_config_get32(config_handle, PCI_CBUS_MEM_LIMIT1)); 4450 cardbus_err(NULL, 1, 4451 " IO Base 0 = [0x%08x] IO Limit 0 = [0x%08x]\n", 4452 pci_config_get32(config_handle, PCI_CBUS_IO_BASE0), 4453 pci_config_get32(config_handle, PCI_CBUS_IO_LIMIT0)); 4454 cardbus_err(NULL, 1, 4455 " IO Base 1 = [0x%08x] IO Limit 1 = [0x%08x]\n", 4456 pci_config_get32(config_handle, PCI_CBUS_IO_BASE1), 4457 pci_config_get32(config_handle, PCI_CBUS_IO_LIMIT1)); 4458 break; 4459 } 4460 cardbus_err(NULL, 1, 4461 " Intr Line = [0x%02x] Intr Pin = [0x%02x]\n", 4462 pci_config_get8(config_handle, PCI_BCNF_ILINE), 4463 pci_config_get8(config_handle, PCI_BCNF_IPIN)); 4464 cardbus_err(NULL, 1, 4465 " Bridge Ctrl = [0x%04x]\n", 4466 pci_config_get16(config_handle, PCI_BCNF_BCNTRL)); 4467 4468 switch (header_type) { 4469 case PCI_HEADER_CARDBUS: 4470 cardbus_err(NULL, 1, 4471 " Sub VID = [0x%04x] Sub SID = [0x%04x]\n", 4472 pci_config_get16(config_handle, PCI_CBUS_SUBVENID), 4473 pci_config_get16(config_handle, PCI_CBUS_SUBSYSID)); 4474 /* LATER: TI1250 only */ 4475 cardbus_err(NULL, 1, 4476 " Sys Control = [0x%08x]\n", 4477 pci_config_get32(config_handle, 0x80)); 4478 } 4479 } 4480 4481 static void 4482 cardbus_dump_config(ddi_acc_handle_t config_handle) 4483 { 4484 uint8_t header_type = pci_config_get8(config_handle, 4485 PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 4486 4487 if (header_type == PCI_HEADER_PPB || header_type == PCI_HEADER_CARDBUS) 4488 cardbus_dump_bridge_config(config_handle, header_type); 4489 else 4490 cardbus_dump_device_config(config_handle); 4491 } 4492 4493 static void 4494 cardbus_dump_reg(dev_info_t *dip, const pci_regspec_t *regspec, int nelems) 4495 { 4496 /* int rlen = nelems * sizeof(pci_regspec_t); */ 4497 4498 cardbus_err(dip, 6, 4499 "cardbus_dump_reg: \"reg\" has %d elements\n", nelems); 4500 4501 #if defined(CARDBUS_DEBUG) 4502 if (cardbus_debug >= 1) { 4503 int i; 4504 uint32_t *regs = (uint32_t *)regspec; 4505 4506 for (i = 0; i < nelems; i++) { 4507 4508 cardbus_err(NULL, 6, 4509 "\t%d:%08x %08x %08x %08x %08x\n", 4510 i, regs[0], regs[1], regs[2], regs[3], regs[4]); 4511 } 4512 } 4513 #endif 4514 } 4515 4516 #endif 4517 4518 #if defined(CARDBUS_DEBUG) 4519 void 4520 cardbus_dump_children(dev_info_t *dip, int level) 4521 { 4522 dev_info_t *next; 4523 4524 cardbus_err(dip, 1, 4525 "\t%d: %s: 0x%p\n", level, ddi_node_name(dip), (void *) dip); 4526 for (next = ddi_get_child(dip); next; 4527 next = ddi_get_next_sibling(next)) 4528 cardbus_dump_children(next, level + 1); 4529 } 4530 4531 void 4532 cardbus_dump_family_tree(dev_info_t *dip) 4533 { 4534 cardbus_err(dip, 1, "0x%p family tree:\n", (void *) dip); 4535 cardbus_dump_children(dip, 1); 4536 } 4537 #endif 4538