1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2014 QLogic Corporation 24 * The contents of this file are subject to the terms of the 25 * QLogic End User License (the "License"). 26 * You may not use this file except in compliance with the License. 27 * 28 * You can obtain a copy of the License at 29 * http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/ 30 * QLogic_End_User_Software_License.txt 31 * See the License for the specific language governing permissions 32 * and limitations under the License. 33 */ 34 35 /* 36 * Copyright (c) 2002, 2011, Oracle and/or its affiliates. All rights reserved. 37 */ 38 39 #ifndef BNXE_H 40 #define BNXE_H 41 42 #include <sys/types.h> 43 #include <sys/stream.h> 44 #include <sys/stropts.h> 45 #include <sys/errno.h> 46 #include <sys/cred.h> 47 #include <sys/poll.h> 48 #include <sys/modctl.h> 49 #include <sys/mac.h> 50 #include <sys/mac_provider.h> 51 #include <sys/stat.h> 52 #include <sys/ddi.h> 53 #include <sys/sunddi.h> 54 #include <sys/sunndi.h> 55 #include <sys/ddifm.h> 56 #include <sys/fm/protocol.h> 57 #include <sys/fm/util.h> 58 #include <sys/fm/io/ddi.h> 59 #include <sys/pattr.h> 60 #include <sys/sysmacros.h> 61 #include <sys/ethernet.h> 62 //#include <sys/vlan.h> 63 #include <sys/strsun.h> 64 #include <sys/ksynch.h> 65 #include <sys/kstat.h> 66 #include <netinet/in.h> 67 #include <netinet/ip.h> 68 #include <netinet/udp.h> 69 #include <netinet/tcp.h> 70 #include <inet/common.h> 71 #include <inet/ip.h> 72 #include <inet/ip_if.h> 73 #include <sys/strsubr.h> 74 #include <sys/pci.h> 75 #include <sys/gld.h> 76 #include <sys/mac_ether.h> 77 78 /* 79 * This really ticks me off! We use 'u' for naming unions 80 * within structures. Why is 'u' a reserved word!?!?!? 81 * http://bugs.opensolaris.org/view_bug.do?bug_id=4340073 82 * This undef has been moved to bnxe_debug.h. 83 */ 84 //#undef u 85 86 #include "version.h" 87 #include "debug.h" 88 #include "bcmtype.h" 89 #include "lm_defs.h" 90 #include "listq.h" 91 #include "lm5710.h" 92 #include "lm.h" 93 #include "bd_chain.h" 94 #if !defined(__SunOS_MDB) 95 #include "command.h" 96 #endif 97 #include "bnxe_binding.h" 98 #if !defined(DBG) && !defined(__SunOS_MDB) 99 #include "bnxe_debug.h" /* wasn't included by debug.h */ 100 #endif 101 102 #ifndef VLAN_TAGSZ 103 #define VLAN_TAGSZ 4 104 #endif 105 106 #define BNXE_RINGS 107 #define RSS_ID_NONE -1 108 109 #define USER_OPTION_CKSUM_NONE 0x0 110 #define USER_OPTION_CKSUM_L3 0x1 111 #define USER_OPTION_CKSUM_L3_L4 0x2 112 #define USER_OPTION_CKSUM_DEFAULT USER_OPTION_CKSUM_L3_L4 113 114 #define USER_OPTION_MTU_MIN 60 115 #define USER_OPTION_MTU_MAX 9216 116 #define USER_OPTION_MTU_DEFAULT 1500 117 118 #define USER_OPTION_NUM_RINGS_MIN 0 119 #define USER_OPTION_NUM_RINGS_MAX MAX_RSS_CHAINS 120 #define USER_OPTION_NUM_RINGS_DEFAULT_MF 1 121 #define USER_OPTION_NUM_RINGS_DEFAULT_SF 4 122 #define USER_OPTION_NUM_RINGS_DEFAULT 0 123 124 #define USER_OPTION_RX_RING_GROUPS_MIN 1 125 #define USER_OPTION_RX_RING_GROUPS_MAX 1 126 #define USER_OPTION_RX_RING_GROUPS_DEFAULT 1 127 128 #define USER_OPTION_BDS_MIN 1 129 #define USER_OPTION_BDS_MAX 32767 130 #define USER_OPTION_RX_BDS_DEFAULT 1024 131 #define USER_OPTION_TX_BDS_DEFAULT 1024 132 #define USER_OPTION_MF_BDS_DIVISOR 4 133 134 #define USER_OPTION_INTR_COALESCE_MIN 10 /* usecs */ 135 #define USER_OPTION_INTR_COALESCE_MAX 1000 136 #define USER_OPTION_INTR_COALESCE_RX_DEFAULT 20 137 #define USER_OPTION_INTR_COALESCE_TX_DEFAULT 40 138 139 #define USER_OPTION_TX_MAX_FREE_DEFAULT 32 140 #define USER_OPTION_RX_MAX_FREE_DEFAULT 32 141 142 //#define USER_OPTION_RX_DCOPY_THRESH_DEFAULT 0xffffffff 143 #define USER_OPTION_RX_DCOPY_THRESH_DEFAULT 128 144 145 //#define USER_OPTION_TX_DCOPY_THRESH_DEFAULT 0 146 #define USER_OPTION_TX_DCOPY_THRESH_DEFAULT 512 147 148 //#define BNXE_IP_MAXLEN 65535 149 #define BNXE_IP_MAXLEN 32768 /* 32768 = PAGESIZE * (BNXE_MAX_DMA_FRAGS_PER_PKT - 2 ) */ 150 #define BNXE_OPTION_LEN 80 /* room for IP/TCP options (max 40 bytes each) */ 151 #define BNXE_PKTHDR_LEN (sizeof(struct ether_vlan_header) + sizeof(struct ip) + sizeof(struct tcphdr) + BNXE_OPTION_LEN) 152 #define BNXE_LSO_MAXLEN (BNXE_IP_MAXLEN + sizeof(struct ether_vlan_header) - BNXE_PKTHDR_LEN) /* maximum payload */ 153 154 #define BNXE_MAGIC 0x0feedead 155 #define BNXE_MEM_CHECK_LEN 16 156 #define BNXE_STR_SIZE 32 157 158 #define BNXEF_NAME "bnxef" 159 160 #define BNXE_FCOE(dev) ((um_device_t *)(dev))->do_fcoe 161 162 #ifdef __sparc 163 #define BNXE_DMA_ALIGNMENT 0x2000UL 164 #else 165 #define BNXE_DMA_ALIGNMENT 0x1000UL 166 #endif 167 168 /* 169 * Adding a two byte offset to the receive buffer aligns the IP header on a 170 * 16 byte boundary and it would put the TCP payload (assuming a 20 byte IP 171 * header and 20 byte TCP header) on an 8 byte boundary. 172 */ 173 #define BNXE_DMA_RX_OFFSET 2 174 175 /* 176 * The following two defines are used for defining limits on Tx packets. 177 * BNXE_MAX_DMA_HANDLES_PER_PKT is the maximum number of DMA handles that are 178 * pre-allocated for every Tx buffer descriptor. These DMA handles are used 179 * for mapping each mblk in the chain when not double copying the packet data 180 * into the copy buffer. BNXE_MAX_DMA_FRAGS_PER_PKT is based on the hardware 181 * and represents the maximum number of fragments an outgoing packet can have. 182 * Note that a single DMA handle can be comprised of multiple fragments which 183 * is very likely with LSO. 184 * 185 * As seen below BNXE_MAX_DMA_FRAGS_PER_PKT is set to 10. The actual firmware 186 * limit is 13 but 10 is chosen specifically for the case of LSO packets that 187 * are broken up across a long mblk chain. The firmware utilizes a sliding 188 * window on a packet's assigned buffer descriptors for LSO. The window is 10 189 * bds and each window (i.e. bds 1-10, 2-11, 3-12, etc), except the window 190 * containing the last bd, must contains at least MSS bytes. There are 'rare' 191 * cases where a packet sent down by the stack will not satisfy this window 192 * size requirement. Therefore, setting the frag limit to 10 results in any 193 * long chained packet (i.e. greater than 10 mblks), the trailing mblks will 194 * get double copied into a single copy buffer and will be pointed to by the 195 * last bd. This simple change will ensure the sliding window requirement is 196 * always satisfied. Note, LSO packets with long mblk chains are a rare 197 * occurance (nicdrv test01 can trigger it). 198 */ 199 #define BNXE_MAX_DMA_HANDLES_PER_PKT 11 /* go easy on DMA resources */ 200 #define BNXE_MAX_DMA_FRAGS_PER_PKT 10 /* set BNXE_IP_MAXLEN above accordingly */ 201 #define BNXE_MAX_DMA_SGLLEN 20 /* for partial dma mapping */ 202 203 #define BNXE_PDWM_THRESHOLD 8 204 205 #define BNXE_TX_RESOURCES_NO_CREDIT 0x01 206 #define BNXE_TX_RESOURCES_NO_DESC 0x02 207 #define BNXE_TX_RESOURCES_NO_DRV_DMA_RES 0x04 /* Out of Tx DMA handles */ 208 #define BNXE_TX_RESOURCES_NO_OS_DMA_RES 0x08 /* Unable to allocate DMA resources. (e.g. bind error) */ 209 #define BNXE_TX_RESOURCES_TOO_MANY_FRAGS 0x10 210 211 #define BNXE_TX_GOODXMIT 0 212 #define BNXE_TX_LINKDOWN 1 213 #define BNXE_TX_DEFERPKT 2 214 #define BNXE_TX_HDWRFULL 3 215 #define BNXE_TX_PKTERROR 4 216 217 #define BNXE_ROUTE_RING_NONE 0 218 #define BNXE_ROUTE_RING_TCPUDP 1 219 #define BNXE_ROUTE_RING_DEST_MAC 2 220 #define BNXE_ROUTE_RING_MSG_PRIO 3 221 222 #undef BNXE_DEBUG_DMA_LIST 223 224 extern ddi_device_acc_attr_t bnxeAccessAttribBAR; 225 extern ddi_device_acc_attr_t bnxeAccessAttribBUF; 226 227 typedef struct _BnxeDevParams 228 { 229 u32_t fw_ver; 230 231 u32_t mtu[LM_CLI_IDX_MAX]; 232 233 u32_t routeTxRingPolicy; 234 u32_t numRings; /* number of rings */ 235 u32_t numRxDesc[LM_CLI_IDX_MAX]; /* number of RX descriptors */ 236 u32_t numTxDesc[LM_CLI_IDX_MAX]; /* number of TX descriptors */ 237 u32_t maxRxFree; /* max free allowed before posting back */ 238 u32_t maxTxFree; /* max free allowed before posting back */ 239 240 boolean_t intrCoalesce; 241 u32_t intrRxPerSec; 242 u32_t intrTxPerSec; 243 boolean_t disableMsix; 244 245 boolean_t l2_fw_flow_ctrl; 246 boolean_t autogreeenEnable; 247 248 u32_t rxCopyThreshold; 249 u32_t txCopyThreshold; 250 251 lm_rx_mask_t rx_filter_mask[LM_CLI_IDX_MAX]; 252 253 int checksum; 254 lm_offload_t enabled_oflds; 255 256 boolean_t lsoEnable; 257 258 boolean_t logEnable; 259 260 boolean_t fcoeEnable; 261 262 boolean_t linkRemoteFaultDetect; 263 264 lm_status_t lastIndLink; 265 lm_medium_t lastIndMedium; 266 267 uint32_t debug_level; 268 } BnxeDevParams; 269 270 271 typedef struct _BnxeLinkCfg 272 { 273 boolean_t link_autoneg; 274 boolean_t param_20000fdx; 275 boolean_t param_10000fdx; 276 boolean_t param_2500fdx; 277 boolean_t param_1000fdx; 278 boolean_t param_100fdx; 279 boolean_t param_100hdx; 280 boolean_t param_10fdx; 281 boolean_t param_10hdx; 282 boolean_t param_txpause; 283 boolean_t param_rxpause; 284 } BnxeLinkCfg; 285 286 287 typedef struct _BnxePhyCfg 288 { 289 BnxeLinkCfg lnkcfg; 290 boolean_t flow_autoneg; 291 u32_t supported[ELINK_LINK_CONFIG_SIZE]; 292 u32_t phy_cfg_size; 293 } BnxePhyCfg; 294 295 296 typedef struct _BnxeProps 297 { 298 u32_t link_speed; 299 boolean_t link_duplex; 300 boolean_t link_txpause; 301 boolean_t link_rxpause; 302 time_t uptime; 303 } BnxeProps; 304 305 306 typedef struct _BnxeMemBlock 307 { 308 d_list_entry_t link; 309 u32_t size; 310 void * pBuf; 311 char fileName[128]; 312 u32_t fileLine; 313 } BnxeMemBlock; 314 315 316 typedef struct _BnxeMemDma 317 { 318 d_list_entry_t link; 319 u32_t size; 320 void * pDmaVirt; 321 ddi_dma_handle_t dmaHandle; 322 ddi_acc_handle_t dmaAccHandle; 323 lm_address_t physAddr; 324 char fileName[128]; 325 u32_t fileLine; 326 } BnxeMemDma; 327 328 329 typedef struct _BnxeMemRegion 330 { 331 d_list_entry_t link; 332 lm_address_t baseAddr; 333 u32_t regNumber; 334 offset_t offset; 335 u32_t size; 336 ddi_acc_handle_t regAccess; 337 caddr_t pRegAddr; 338 } BnxeMemRegion; 339 340 341 typedef struct _um_txpacket_t 342 { 343 lm_packet_t lm_pkt; /* must be the first entry */ 344 lm_pkt_tx_info_t tx_info; 345 346 mblk_t * pMblk; 347 348 ddi_dma_handle_t cbDmaHandle; /* cb = copy buffer */ 349 ddi_acc_handle_t cbDmaAccHandle; 350 caddr_t pCbBuf; 351 lm_address_t cbPhysAddr; 352 353 u32_t cbLength; 354 u32_t num_handles; /* number of handles used for pkt */ 355 ddi_dma_handle_t dmaHandles[BNXE_MAX_DMA_HANDLES_PER_PKT]; 356 357 lm_frag_list_t frag_list; 358 lm_frag_t frag_list_buffer[BNXE_MAX_DMA_FRAGS_PER_PKT]; 359 } um_txpacket_t; 360 361 362 typedef struct _TxQueue 363 { 364 void * pUM; /* backpointer to um_device_t */ 365 u32_t idx; /* this ring's index */ 366 367 mac_ring_handle_t ringHandle; 368 369 u32_t desc_cnt; /* number of Tx descriptors */ 370 371 u32_t txFailed; 372 u32_t txDiscards; 373 u32_t txRecycle; 374 u32_t txCopied; 375 u32_t txBlocked; 376 u32_t txWait; 377 u32_t txLowWater; 378 379 u32_t thresh_pdwm; /* low resource water marks */ 380 381 kmutex_t txMutex; 382 383 s_list_t sentTxQ; /* bds that have been sent and are ready to be freed */ 384 385 kmutex_t freeTxDescMutex; 386 s_list_t freeTxDescQ; /* bds that are free for use */ 387 388 s_list_t waitTxDescQ; /* bds that are setup and waiting for tx (lock w/ tx mutex) */ 389 390 u32_t noTxCredits; 391 } TxQueue; 392 393 394 typedef struct _um_rxpacket_t 395 { 396 lm_packet_t lm_pkt; /* must be first entry */ 397 lm_pkt_rx_info_t rx_info; 398 u32_t hash_value; 399 400 frtn_t freeRtn; 401 void * pUM; /* backpointer to um_device_t for free routine */ 402 int idx; /* chain index used by the free routine */ 403 404 u32_t signature; 405 406 ddi_dma_handle_t dmaHandle; 407 ddi_acc_handle_t dmaAccHandle; 408 } um_rxpacket_t; 409 410 411 typedef struct _RxQueue 412 { 413 void * pUM; /* backpointer to um_device_t */ 414 u32_t idx; /* this ring's index */ 415 416 mac_ring_handle_t ringHandle; 417 uint64_t genNumber; /* set by mac and passed up in mac_ring_rx */ 418 419 volatile u32_t inPollMode; 420 u8_t intrDisableCnt; 421 u8_t intrEnableCnt; 422 u8_t pollCnt; 423 424 u32_t rxDiscards; 425 u32_t rxCopied; 426 u32_t rxLowWater; 427 u32_t rxBufUpInStack; 428 429 kmutex_t rxMutex; 430 431 kmutex_t doneRxMutex; 432 s_list_t doneRxQ; /* free bds that are ready to be posted */ 433 434 s_list_t waitRxQ; /* packet waiting to be sent up */ 435 } RxQueue; 436 437 438 typedef struct _RxQueueGroup 439 { 440 void * pUM; /* backpointer to um_device_t */ 441 u32_t idx; /* this group's index */ 442 mac_group_handle_t groupHandle; 443 } RxQueueGroup; 444 445 446 typedef struct _KstatRingMap 447 { 448 u32_t idx; /* ring index */ 449 void * pUM; /* reference back to um_device_t */ 450 } KstatRingMap; 451 452 453 typedef struct _BnxeFcoeState 454 { 455 lm_fcoe_state_t lm_fcoe; 456 } BnxeFcoeState; 457 458 459 typedef struct _BnxeClientStats 460 { 461 u32_t initWqeTx; 462 u32_t initWqeTxErr; 463 u32_t initCqeRx; 464 u32_t initCqeRxErr; 465 u32_t offloadConnWqeTx; 466 u32_t offloadConnWqeTxErr; 467 u32_t offloadConnCqeRx; 468 u32_t offloadConnCqeRxErr; 469 u32_t enableConnWqeTx; 470 u32_t enableConnWqeTxErr; 471 u32_t enableConnCqeRx; 472 u32_t enableConnCqeRxErr; 473 u32_t disableConnWqeTx; 474 u32_t disableConnWqeTxErr; 475 u32_t disableConnCqeRx; 476 u32_t disableConnCqeRxErr; 477 u32_t destroyConnWqeTx; 478 u32_t destroyConnWqeTxErr; 479 u32_t destroyConnCqeRx; 480 u32_t destroyConnCqeRxErr; 481 u32_t destroyWqeTx; 482 u32_t destroyWqeTxErr; 483 u32_t destroyCqeRx; 484 u32_t destroyCqeRxErr; 485 u32_t compRequestCqeRx; 486 u32_t compRequestCqeRxErr; 487 u32_t statWqeTx; 488 u32_t statWqeTxErr; 489 u32_t statCqeRx; 490 u32_t statCqeRxErr; 491 } BnxeClientStats; 492 493 494 typedef struct _BnxeFcoeData 495 { 496 dev_info_t * pDev; 497 BnxeBinding bind; 498 BnxeClientStats stats; 499 BnxeWwnInfo wwn; 500 } BnxeFcoeData; 501 502 503 typedef struct _BnxeIntrBlock 504 { 505 int intrCount; 506 int intrCapability; 507 u32_t intrPriority; 508 u32_t intrHandleBlockSize; 509 ddi_intr_handle_t * pIntrHandleBlockAlloc; 510 ddi_intr_handle_t * pIntrHandleBlock; 511 } BnxeIntrBlock; 512 513 514 typedef struct _BnxeWorkQueueInstance 515 { 516 void * pUM; 517 518 char taskqName[BNXE_STR_SIZE]; 519 ddi_taskq_t * pTaskq; 520 kmutex_t workQueueMutex; 521 s_list_t workQueue; 522 523 u32_t workItemQueued; 524 u32_t workItemError; 525 u32_t workItemComplete; 526 u32_t highWater; 527 } BnxeWorkQueueInstance; 528 529 530 typedef struct _BnxeWorkQueues 531 { 532 BnxeWorkQueueInstance instq; /* instant, single thread serialized */ 533 BnxeWorkQueueInstance delayq; /* delayed, multi thread not serialized */ 534 } BnxeWorkQueues; 535 536 537 /* the following are used against the clientState variable in um_device_t */ 538 539 #define CLIENT_FLG_DEVI 0x001 540 #define CLIENT_FLG_BIND 0x002 541 #define CLIENT_FLG_HW 0x004 542 543 #define CLIENT_DEVI(pUM, client) \ 544 ((pUM)->clientState[(client)] & CLIENT_FLG_DEVI) 545 546 #define CLIENT_HW(pUM, client) \ 547 ((pUM)->clientState[(client)] & CLIENT_FLG_HW) 548 549 #define CLIENT_BOUND(pUM, client) \ 550 (((client) == LM_CLI_IDX_NDIS) ? \ 551 ((pUM)->clientState[(client)] & CLIENT_FLG_HW) : \ 552 ((pUM)->clientState[(client)] & CLIENT_FLG_BIND)) 553 554 #define CLIENT_DEVI_SET(pUM, client) \ 555 ((pUM)->clientState[(client)] |= CLIENT_FLG_DEVI) 556 557 #define CLIENT_DEVI_RESET(pUM, client) \ 558 ((pUM)->clientState[(client)] &= ~CLIENT_FLG_DEVI) 559 560 #define CLIENT_BIND_SET(pUM, client) \ 561 ((pUM)->clientState[(client)] |= CLIENT_FLG_BIND) 562 563 #define CLIENT_BIND_RESET(pUM, client) \ 564 ((pUM)->clientState[(client)] &= ~CLIENT_FLG_BIND) 565 566 #define CLIENT_HW_SET(pUM, client) \ 567 ((pUM)->clientState[(client)] |= CLIENT_FLG_HW) 568 569 #define CLIENT_HW_RESET(pUM, client) \ 570 ((pUM)->clientState[(client)] &= ~CLIENT_FLG_HW) 571 572 573 typedef struct _um_device 574 { 575 lm_device_t lm_dev; /* must be the first element */ 576 577 u32_t magic; 578 dev_info_t * pDev; 579 580 u32_t hwInitDone; 581 u32_t chipStarted; 582 u32_t clientState[LM_CLI_IDX_MAX]; 583 584 d_list_t memBlockList; 585 d_list_t memDmaList; 586 d_list_t memRegionList; 587 #ifdef BNXE_DEBUG_DMA_LIST 588 d_list_t memDmaListSaved; 589 #endif 590 591 int instance; 592 char devName[BNXE_STR_SIZE]; 593 char version[BNXE_STR_SIZE]; 594 char versionLM[BNXE_STR_SIZE]; 595 char versionFW[BNXE_STR_SIZE]; 596 char versionBC[BNXE_STR_SIZE]; 597 char chipName[BNXE_STR_SIZE]; 598 char chipID[BNXE_STR_SIZE]; 599 char intrAlloc[BNXE_STR_SIZE]; 600 char bus_dev_func[BNXE_STR_SIZE]; 601 char vendor_device[BNXE_STR_SIZE]; 602 603 volatile u32_t plumbed; 604 605 ddi_acc_handle_t pPciCfg; 606 607 kmutex_t intrMutex[MAX_RSS_CHAINS + 1]; 608 kmutex_t intrFlipMutex[MAX_RSS_CHAINS + 1]; 609 kmutex_t sbMutex[MAX_RSS_CHAINS + 1]; 610 kmutex_t ethConMutex; 611 kmutex_t mcpMutex; 612 kmutex_t phyMutex; 613 kmutex_t indMutex; 614 kmutex_t cidMutex; 615 kmutex_t spqMutex; /* slow path queue lock */ 616 kmutex_t spReqMutex; /* slow path request manager lock */ 617 kmutex_t rrReqMutex; /* ramrod request */ 618 kmutex_t islesCtrlMutex; 619 kmutex_t toeMutex; 620 kmutex_t memMutex; 621 kmutex_t offloadMutex; 622 kmutex_t hwInitMutex; 623 kmutex_t gldMutex; 624 krwlock_t gldTxMutex; 625 626 kmutex_t timerMutex; 627 volatile u32_t timerEnabled; 628 timeout_id_t timerID; 629 630 BnxeWorkQueues workqs; 631 632 BnxeMemDma * statusBlocks[MAX_RSS_CHAINS + 1]; 633 volatile u32_t intrEnabled; 634 u64_t intrFired; 635 /* the arrays below = LM_SB_CNT() + 1 = 17 */ 636 u64_t intrSbCnt[MAX_RSS_CHAINS + 1]; 637 u64_t intrSbNoChangeCnt[MAX_RSS_CHAINS + 1]; 638 u64_t intrSbPollCnt[MAX_RSS_CHAINS + 1]; 639 u64_t intrSbPollNoChangeCnt[MAX_RSS_CHAINS + 1]; 640 641 int intrType; 642 u32_t intrPriority; 643 BnxeIntrBlock defIntr; 644 BnxeIntrBlock rssIntr; 645 BnxeIntrBlock fcoeIntr; 646 647 BnxeDevParams devParams; 648 mac_handle_t pMac; 649 mac_resource_handle_t macRxResourceHandles[MAX_ETH_REG_CONS]; 650 u8_t gldMac[ETHERNET_ADDRESS_SIZE]; 651 652 d_list_t mcast_l2; 653 d_list_t mcast_fcoe; 654 655 u32_t ucastTableLen; /* number of ucast addrs in the table */ 656 #ifndef LM_MAX_UC_TABLE_SIZE 657 #define LM_MAX_UC_TABLE_SIZE 1 /* for now, fix needed to support multiple ucast addr */ 658 #endif 659 660 TxQueue txq[MAX_ETH_CONS]; 661 RxQueue rxq[MAX_ETH_CONS]; 662 RxQueueGroup rxqGroup[USER_OPTION_RX_RING_GROUPS_MAX]; 663 u32_t rxBufSignature[LM_CLI_IDX_MAX]; 664 u32_t txMsgPullUp; 665 666 BnxeProps props; 667 BnxePhyCfg hwinit; /* gathered by BnxeCfgInit */ 668 BnxePhyCfg curcfg; /* initialized from hwinit by BnxeCfgReset */ 669 BnxeLinkCfg remote; 670 u32_t phyInitialized; 671 672 kstat_t * kstats; 673 kstat_t * kstatsLink; 674 kstat_t * kstatsIntr; 675 kstat_t * kstatsL2Chip; 676 kstat_t * kstatsL2Driver; 677 kstat_t * kstatsL2Stats; 678 kstat_t * kstatsFcoe; 679 kstat_t * kstatsDcbx; 680 kstat_t * kstats_rxq[MAX_ETH_CONS]; 681 KstatRingMap kstats_rxq_map[MAX_ETH_CONS]; 682 kstat_t * kstats_txq[MAX_ETH_CONS]; 683 KstatRingMap kstats_txq_map[MAX_ETH_CONS]; 684 kmutex_t kstatMutex; 685 686 int fmCapabilities; /* FMA capabilities */ 687 688 boolean_t do_fcoe; 689 BnxeFcoeData fcoe; 690 iscsi_info_block_hdr_t iscsiInfo; 691 692 } um_device_t; 693 694 695 /* mioc[ack|nak] return values from ioctl subroutines */ 696 enum ioc_reply 697 { 698 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 699 IOC_DONE, /* OK, reply sent */ 700 IOC_ACK, /* OK, just send ACK */ 701 IOC_REPLY, /* OK, just send reply */ 702 IOC_RESTART_ACK, /* OK, restart & ACK */ 703 IOC_RESTART_REPLY /* OK, restart & reply */ 704 }; 705 706 707 #define BNXE_IOC_BASE ('X' << 8) 708 /* IOCTLs for get/set lldp and dcbx params */ 709 #define GIOCBNXELLDP (BNXE_IOC_BASE + 0) 710 #define GIOCBNXEDCBX (BNXE_IOC_BASE + 1) 711 #define SIOCBNXEDCBX (BNXE_IOC_BASE + 2) 712 /* IOCTLs for edebug and firmware upgrade */ 713 #define GIOCBNXEREG (BNXE_IOC_BASE + 3) 714 #define SIOCBNXEREG (BNXE_IOC_BASE + 4) 715 #define GIOCBNXENVRM (BNXE_IOC_BASE + 5) 716 #define SIOCBNXENVRM (BNXE_IOC_BASE + 6) 717 #define GIOCBNXEPCI (BNXE_IOC_BASE + 7) 718 #define GIOCBNXESTATS (BNXE_IOC_BASE + 8) 719 720 struct bnxe_reg_data 721 { 722 u32_t offset; 723 u32_t value; 724 }; 725 726 struct bnxe_nvram_data 727 { 728 u32_t offset; 729 u32_t num_of_u32; 730 u32_t value[1]; /* variable */ 731 }; 732 733 734 /* bnxe_cfg.c */ 735 void BnxeCfgInit(um_device_t * pUM); 736 void BnxeCfgReset(um_device_t * pUM); 737 738 /* bnxe_mm.c */ 739 void BnxeInitBdCnts(um_device_t * pUM, 740 int cli_idx); 741 742 /* bnxe_gld.c */ 743 boolean_t BnxeGldInit(um_device_t * pUM); 744 boolean_t BnxeGldFini(um_device_t * pUM); 745 void BnxeGldLink(um_device_t * pUM, 746 link_state_t state); 747 748 /* bnxe_hw.c */ 749 boolean_t BnxeEstablishHwConn(um_device_t * pUM, 750 int cid); 751 int BnxeHwStartFCOE(um_device_t * pUM); 752 int BnxeHwStartL2(um_device_t * pUM); 753 int BnxeHwStartCore(um_device_t * pUM); 754 void BnxeHwStopFCOE(um_device_t * pUM); 755 void BnxeHwStopL2(um_device_t * pUM); 756 void BnxeHwStopCore(um_device_t * pUM); 757 void BnxeUpdatePhy(um_device_t * pUM); 758 int BnxeMacAddress(um_device_t * pUM, 759 int cliIdx, 760 boolean_t flag, 761 const uint8_t * pMacAddr); 762 int BnxeMulticast(um_device_t * pUM, 763 int cliIdx, 764 boolean_t flag, 765 const uint8_t * pMcastAddr, 766 boolean_t hwSet); 767 int BnxeRxMask(um_device_t * pUM, 768 int cliIdx, 769 lm_rx_mask_t mask); 770 int BnxeHwResume(um_device_t * pUM); 771 int BnxeHwSuspend(um_device_t * pUM); 772 #if (DEVO_REV > 3) 773 int BnxeHwQuiesce(um_device_t * pUM); 774 #endif 775 776 /* bnxe_intr.c */ 777 void BnxeIntrIguSbEnable(um_device_t * pUM, 778 u32_t idx, 779 boolean_t fromISR); 780 void BnxeIntrIguSbDisable(um_device_t * pUM, 781 u32_t idx, 782 boolean_t fromISR); 783 void BnxePollRxRing(um_device_t * pUM, 784 u32_t idx, 785 boolean_t * pPktsRxed, 786 boolean_t * pPktsTxed); 787 void BnxePollRxRingFCOE(um_device_t * pUM); 788 int BnxeIntrEnable(um_device_t * pUM); 789 void BnxeIntrDisable(um_device_t * pUM); 790 boolean_t BnxeIntrInit(um_device_t * pUM); 791 void BnxeIntrFini(um_device_t * pUM); 792 793 /* bnxe_kstat.c */ 794 boolean_t BnxeKstatInit(um_device_t * pUM); 795 void BnxeKstatFini(um_device_t * pUM); 796 797 /* bnxe_rr.c */ 798 int BnxeRouteTxRing(um_device_t * pUM, 799 mblk_t * pMblk); 800 801 /* bnxe_rx.c */ 802 boolean_t BnxeWaitForPacketsFromClient(um_device_t * pUM, 803 int cliIdx); 804 mblk_t * BnxeRxRingProcess(um_device_t * pUM, 805 int idx, 806 boolean_t polling, 807 int numBytes); 808 void BnxeRxPktsAbort(um_device_t * pUM, 809 int cliIdx); 810 int BnxeRxPktsInitPostBuffers(um_device_t * pUM, 811 int cliIdx); 812 int BnxeRxPktsInit(um_device_t * pUM, 813 int cliIdx); 814 void BnxeRxPktsFini(um_device_t * pUM, 815 int cliIdx); 816 817 /* bnxe_tx.c */ 818 void BnxeTxPktsReclaim(um_device_t * pUM, 819 int idx, 820 s_list_t * pPktList); 821 void BnxeTxRingProcess(um_device_t * pUM, 822 int idx); 823 int BnxeTxSendMblk(um_device_t * pUM, 824 int idx, 825 mblk_t * pMblk, 826 u32_t flags, 827 u16_t vlan_tag); 828 void BnxeTxPktsAbort(um_device_t * pUM, 829 int cliIdx); 830 int BnxeTxPktsInit(um_device_t * pUM, 831 int cliIdx); 832 void BnxeTxPktsFini(um_device_t * pUM, 833 int cliIdx); 834 835 /* bnxe_timer.c */ 836 void BnxeTimerStart(um_device_t * pUM); 837 void BnxeTimerStop(um_device_t * pUM); 838 839 /* bnxe_workq.c */ 840 boolean_t BnxeWorkQueueInit(um_device_t * pUM); 841 void BnxeWorkQueueWaitAndDestroy(um_device_t * pUM); 842 void BnxeWorkQueueStartPending(um_device_t * pUM); 843 boolean_t BnxeWorkQueueAdd(um_device_t * pUM, 844 void (*pWorkCbk)(um_device_t *, void *, u32_t), 845 void * pWorkData, 846 u32_t workDataLen); 847 boolean_t BnxeWorkQueueAddNoCopy(um_device_t * pUM, 848 void (*pWorkCbk)(um_device_t *, void *), 849 void * pWorkData); 850 boolean_t BnxeWorkQueueAddGeneric(um_device_t * pUM, 851 void (*pWorkCbkGeneric)(um_device_t *)); 852 boolean_t BnxeWorkQueueAddDelay(um_device_t * pUM, 853 void (*pWorkCbk)(um_device_t *, void *, u32_t), 854 void * pWorkData, 855 u32_t workDataLen, 856 u32_t delayMs); 857 boolean_t BnxeWorkQueueAddDelayNoCopy(um_device_t * pUM, 858 void (*pWorkCbk)(um_device_t *, void *), 859 void * pWorkData, 860 u32_t delayMs); 861 boolean_t BnxeWorkQueueAddDelayGeneric(um_device_t * pUM, 862 void (*pWorkCbkGeneric)(um_device_t *), 863 u32_t delayMs); 864 865 /* bnxe_fcoe.c */ 866 boolean_t BnxeFcoeInitCqe(um_device_t * pUM, 867 struct fcoe_kcqe * kcqe); 868 boolean_t BnxeFcoeOffloadConnCqe(um_device_t * pUM, 869 BnxeFcoeState * pFcoeState, 870 struct fcoe_kcqe * kcqe); 871 boolean_t BnxeFcoeEnableConnCqe(um_device_t * pUM, 872 BnxeFcoeState * pFcoeState, 873 struct fcoe_kcqe * kcqe); 874 boolean_t BnxeFcoeDisableConnCqe(um_device_t * pUM, 875 BnxeFcoeState * pFcoeState, 876 struct fcoe_kcqe * kcqe); 877 boolean_t BnxeFcoeDestroyConnCqe(um_device_t * pUM, 878 BnxeFcoeState * pFcoeState, 879 struct fcoe_kcqe * kcqe); 880 boolean_t BnxeFcoeDestroyCqe(um_device_t * pUM, 881 struct fcoe_kcqe * kcqe); 882 boolean_t BnxeFcoeStatCqe(um_device_t * pUM, 883 struct fcoe_kcqe * kcqe); 884 boolean_t BnxeFcoeCompRequestCqe(um_device_t * pUM, 885 struct fcoe_kcqe * kcqes, 886 u32_t num_kcqes); 887 boolean_t BnxeFcoePrvCtl(dev_info_t * pDev, 888 int cmd, 889 void * pData, 890 int dataLen); 891 mblk_t * BnxeFcoePrvTx(dev_info_t * pDev, 892 mblk_t * pMblk, 893 u32_t flags, 894 u16_t vlan_tag); 895 boolean_t BnxeFcoePrvPoll(dev_info_t * pDev); 896 boolean_t BnxeFcoePrvSendWqes(dev_info_t * pDev, 897 void * wqes[], 898 int wqeCnt); 899 boolean_t BnxeFcoePrvMapMailboxq(dev_info_t * pDev, 900 u32_t cid, 901 void ** ppMap, 902 ddi_acc_handle_t * pAccHandle); 903 boolean_t BnxeFcoePrvUnmapMailboxq(dev_info_t * pDev, 904 u32_t cid, 905 void * pMap, 906 ddi_acc_handle_t accHandle); 907 int BnxeFcoeInit(um_device_t * pUM); 908 int BnxeFcoeFini(um_device_t * pUM); 909 void BnxeFcoeStartStop(um_device_t * pUM); 910 911 /* bnxe_main.c */ 912 u8_t BnxeInstance(void * pDev); 913 char * BnxeDevName(void * pDev); 914 boolean_t BnxeProtoSupport(um_device_t * pUM, int proto); 915 boolean_t BnxeProtoFcoeAfex(um_device_t * pUM); 916 int BnxeCheckAccHandle(ddi_acc_handle_t handle); 917 int BnxeCheckDmaHandle(ddi_dma_handle_t handle); 918 void BnxeFmErrorReport(um_device_t * pUM, char * detail); 919 920 /* bnxe_illumos.c */ 921 extern boolean_t bnxe_fill_transceiver(um_device_t *, void *); 922 extern mac_ether_media_t bnxe_phy_to_media(um_device_t *); 923 924 extern kmutex_t bnxeLoaderMutex; 925 extern u32_t bnxeNumPlumbed; 926 927 extern BnxeLinkCfg bnxeLinkCfg; 928 929 /* undefine this to help with dtrace analysis */ 930 #define BNXE_LOCKS_INLINE 931 932 #ifdef BNXE_LOCKS_INLINE 933 934 #define BNXE_LOCK_ENTER_INTR(pUM, idx) mutex_enter(&(pUM)->intrMutex[(idx)]) 935 #define BNXE_LOCK_EXIT_INTR(pUM, idx) mutex_exit(&(pUM)->intrMutex[(idx)]) 936 #define BNXE_LOCK_ENTER_INTR_FLIP(pUM, idx) mutex_enter(&(pUM)->intrFlipMutex[(idx)]) 937 #define BNXE_LOCK_EXIT_INTR_FLIP(pUM, idx) mutex_exit(&(pUM)->intrFlipMutex[(idx)]) 938 #define BNXE_LOCK_ENTER_TX(pUM, idx) mutex_enter(&(pUM)->txq[(idx)].txMutex) 939 #define BNXE_LOCK_EXIT_TX(pUM, idx) mutex_exit(&(pUM)->txq[(idx)].txMutex) 940 #define BNXE_LOCK_ENTER_FREETX(pUM, idx) mutex_enter(&(pUM)->txq[(idx)].freeTxDescMutex) 941 #define BNXE_LOCK_EXIT_FREETX(pUM, idx) mutex_exit(&(pUM)->txq[(idx)].freeTxDescMutex) 942 #define BNXE_LOCK_ENTER_RX(pUM, idx) mutex_enter(&(pUM)->rxq[(idx)].rxMutex) 943 #define BNXE_LOCK_EXIT_RX(pUM, idx) mutex_exit(&(pUM)->rxq[(idx)].rxMutex) 944 #define BNXE_LOCK_ENTER_DONERX(pUM, idx) mutex_enter(&(pUM)->rxq[(idx)].doneRxMutex) 945 #define BNXE_LOCK_EXIT_DONERX(pUM, idx) mutex_exit(&(pUM)->rxq[(idx)].doneRxMutex) 946 #define BNXE_LOCK_ENTER_SB(pUM, idx) mutex_enter(&(pUM)->sbMutex[(idx)]) 947 #define BNXE_LOCK_EXIT_SB(pUM, idx) mutex_exit(&(pUM)->sbMutex[(idx)]) 948 #define BNXE_LOCK_ENTER_ETH_CON(pUM) mutex_enter(&(pUM)->ethConMutex) 949 #define BNXE_LOCK_EXIT_ETH_CON(pUM) mutex_exit(&(pUM)->ethConMutex) 950 #define BNXE_LOCK_ENTER_MCP(pUM) mutex_enter(&(pUM)->mcpMutex) 951 #define BNXE_LOCK_EXIT_MCP(pUM) mutex_exit(&(pUM)->mcpMutex) 952 #define BNXE_LOCK_ENTER_PHY(pUM) mutex_enter(&(pUM)->phyMutex) 953 #define BNXE_LOCK_EXIT_PHY(pUM) mutex_exit(&(pUM)->phyMutex) 954 #define BNXE_LOCK_ENTER_IND(pUM) mutex_enter(&(pUM)->indMutex) 955 #define BNXE_LOCK_EXIT_IND(pUM) mutex_exit(&(pUM)->indMutex) 956 #define BNXE_LOCK_ENTER_CID(pUM) mutex_enter(&(pUM)->cidMutex) 957 #define BNXE_LOCK_EXIT_CID(pUM) mutex_exit(&(pUM)->cidMutex) 958 #define BNXE_LOCK_ENTER_SPQ(pUM) mutex_enter(&(pUM)->spqMutex) 959 #define BNXE_LOCK_EXIT_SPQ(pUM) mutex_exit(&(pUM)->spqMutex) 960 #define BNXE_LOCK_ENTER_SPREQ(pUM) mutex_enter(&(pUM)->spReqMutex) 961 #define BNXE_LOCK_EXIT_SPREQ(pUM) mutex_exit(&(pUM)->spReqMutex) 962 #define BNXE_LOCK_ENTER_RRREQ(pUM) mutex_enter(&(pUM)->rrReqMutex) 963 #define BNXE_LOCK_EXIT_RRREQ(pUM) mutex_exit(&(pUM)->rrReqMutex) 964 #define BNXE_LOCK_ENTER_ISLES_CONTROL(pUM) mutex_enter(&(pUM)->islesCtrlMutex) 965 #define BNXE_LOCK_EXIT_ISLES_CONTROL(pUM) mutex_exit(&(pUM)->islesCtrlMutex) 966 #define BNXE_LOCK_ENTER_TOE(pUM) mutex_enter(&(pUM)->toeMutex) 967 #define BNXE_LOCK_EXIT_TOE(pUM) mutex_exit(&(pUM)->toeMutex) 968 #define BNXE_LOCK_ENTER_MEM(pUM) mutex_enter(&(pUM)->memMutex) 969 #define BNXE_LOCK_EXIT_MEM(pUM) mutex_exit(&(pUM)->memMutex) 970 #define BNXE_LOCK_ENTER_OFFLOAD(pUM) mutex_enter(&(pUM)->offloadMutex) 971 #define BNXE_LOCK_EXIT_OFFLOAD(pUM) mutex_exit(&(pUM)->offloadMutex) 972 #define BNXE_LOCK_ENTER_HWINIT(pUM) mutex_enter(&(pUM)->hwInitMutex) 973 #define BNXE_LOCK_EXIT_HWINIT(pUM) mutex_exit(&(pUM)->hwInitMutex) 974 #define BNXE_LOCK_ENTER_GLD(pUM) mutex_enter(&(pUM)->gldMutex) 975 #define BNXE_LOCK_EXIT_GLD(pUM) mutex_exit(&(pUM)->gldMutex) 976 #define BNXE_LOCK_ENTER_GLDTX(pUM, rw) rw_enter(&(pUM)->gldTxMutex, (rw)) 977 #define BNXE_LOCK_EXIT_GLDTX(pUM) rw_exit(&(pUM)->gldTxMutex) 978 #define BNXE_LOCK_ENTER_TIMER(pUM) mutex_enter(&(pUM)->timerMutex) 979 #define BNXE_LOCK_EXIT_TIMER(pUM) mutex_exit(&(pUM)->timerMutex) 980 #define BNXE_LOCK_ENTER_STATS(pUM) mutex_enter(&(pUM)->kstatMutex) 981 #define BNXE_LOCK_EXIT_STATS(pUM) mutex_exit(&(pUM)->kstatMutex) 982 983 #else /* not BNXE_LOCKS_INLINE */ 984 985 void BNXE_LOCK_ENTER_INTR(um_device_t * pUM, int idx); 986 void BNXE_LOCK_EXIT_INTR(um_device_t * pUM, int idx); 987 void BNXE_LOCK_ENTER_INTR_FLIP(um_device_t * pUM, int idx); 988 void BNXE_LOCK_EXIT_INTR_FLIP(um_device_t * pUM, int idx); 989 void BNXE_LOCK_ENTER_TX(um_device_t * pUM, int idx); 990 void BNXE_LOCK_EXIT_TX(um_device_t * pUM, int idx); 991 void BNXE_LOCK_ENTER_FREETX(um_device_t * pUM, int idx); 992 void BNXE_LOCK_EXIT_FREETX(um_device_t * pUM, int idx); 993 void BNXE_LOCK_ENTER_RX(um_device_t * pUM, int idx); 994 void BNXE_LOCK_EXIT_RX(um_device_t * pUM, int idx); 995 void BNXE_LOCK_ENTER_DONERX(um_device_t * pUM, int idx); 996 void BNXE_LOCK_EXIT_DONERX(um_device_t * pUM, int idx); 997 void BNXE_LOCK_ENTER_SB(um_device_t * pUM, int idx); 998 void BNXE_LOCK_EXIT_SB(um_device_t * pUM, int idx); 999 void BNXE_LOCK_ENTER_ETH_CON(um_device_t * pUM); 1000 void BNXE_LOCK_EXIT_ETH_CON(um_device_t * pUM); 1001 void BNXE_LOCK_ENTER_MCP(um_device_t * pUM); 1002 void BNXE_LOCK_EXIT_MCP(um_device_t * pUM); 1003 void BNXE_LOCK_ENTER_PHY(um_device_t * pUM); 1004 void BNXE_LOCK_EXIT_PHY(um_device_t * pUM); 1005 void BNXE_LOCK_ENTER_IND(um_device_t * pUM); 1006 void BNXE_LOCK_EXIT_IND(um_device_t * pUM); 1007 void BNXE_LOCK_ENTER_CID(um_device_t * pUM); 1008 void BNXE_LOCK_EXIT_CID(um_device_t * pUM); 1009 void BNXE_LOCK_ENTER_SPQ(um_device_t * pUM); 1010 void BNXE_LOCK_EXIT_SPQ(um_device_t * pUM); 1011 void BNXE_LOCK_ENTER_SPREQ(um_device_t * pUM); 1012 void BNXE_LOCK_EXIT_SPREQ(um_device_t * pUM); 1013 void BNXE_LOCK_ENTER_RRREQ(um_device_t * pUM); 1014 void BNXE_LOCK_EXIT_RRREQ(um_device_t * pUM); 1015 void BNXE_LOCK_ENTER_ISLES_CONTROL(um_device_t * pUM); 1016 void BNXE_LOCK_EXIT_ISLES_CONTROL(um_device_t * pUM); 1017 void BNXE_LOCK_ENTER_MEM(um_device_t * pUM); 1018 void BNXE_LOCK_EXIT_MEM(um_device_t * pUM); 1019 void BNXE_LOCK_ENTER_GLD(um_device_t * pUM); 1020 void BNXE_LOCK_EXIT_GLD(um_device_t * pUM); 1021 void BNXE_LOCK_ENTER_GLDTX(um_device_t * pUM, krw_t rw); 1022 void BNXE_LOCK_EXIT_GLDTX(um_device_t * pUM); 1023 void BNXE_LOCK_ENTER_TIMER(um_device_t * pUM); 1024 void BNXE_LOCK_EXIT_TIMER(um_device_t * pUM); 1025 void BNXE_LOCK_ENTER_STATS(um_device_t * pUM); 1026 void BNXE_LOCK_EXIT_STATS(um_device_t * pUM); 1027 1028 #endif /* BNXE_LOCKS_INLINE */ 1029 1030 #define CATC_TRIGGER(lmdev, data) { \ 1031 REG_WR((lmdev), 0x2000, (data)); \ 1032 } 1033 #define CATC_TRIGGER_START(lmdev) CATC_TRIGGER((lmdev), 0xcafecafe) 1034 1035 void BnxeDumpMem(um_device_t * pUM, 1036 char * pTag, 1037 u8_t * pMem, 1038 u32_t len); 1039 void BnxeDumpPkt(um_device_t * pUM, 1040 char * pTag, 1041 mblk_t * pMblk, 1042 boolean_t contents); 1043 1044 /* XXX yuck (beware return strings lengths with kstat and mdb) */ 1045 1046 inline boolean_t BnxeIsClientBound(um_device_t * pUM) 1047 { 1048 return (CLIENT_HW(pUM, LM_CLI_IDX_NDIS) || 1049 CLIENT_BOUND(pUM, LM_CLI_IDX_FCOE)); 1050 } 1051 1052 inline char * BnxeClientsHw(um_device_t * pUM) 1053 { 1054 if (CLIENT_HW(pUM, LM_CLI_IDX_NDIS) && 1055 CLIENT_HW(pUM, LM_CLI_IDX_FCOE)) { return "L2,FCoE"; } 1056 else if (CLIENT_HW(pUM, LM_CLI_IDX_NDIS)) { return "L2"; } 1057 else if (CLIENT_HW(pUM, LM_CLI_IDX_FCOE)) { return "FCoE"; } 1058 else { return "None"; } 1059 } 1060 1061 inline char * BnxeClientsDevi(um_device_t * pUM) 1062 { 1063 if (CLIENT_DEVI(pUM, LM_CLI_IDX_FCOE)) { return "FCoE"; } 1064 else { return "None"; } 1065 } 1066 1067 inline char * BnxeClientsBound(um_device_t * pUM) 1068 { 1069 if (CLIENT_HW(pUM, LM_CLI_IDX_NDIS) && 1070 CLIENT_BOUND(pUM, LM_CLI_IDX_FCOE)) { return "L2,FCoE"; } 1071 else if (CLIENT_HW(pUM, LM_CLI_IDX_NDIS)) { return "L2"; } 1072 else if (CLIENT_BOUND(pUM, LM_CLI_IDX_FCOE)) { return "FCoE"; } 1073 else { return "None"; } 1074 } 1075 1076 #endif /* BNXE_H */ 1077 1078