1 2 /***************************************************************************** 3 * CDDL HEADER START 4 * 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 * 22 * Copyright 2014 QLogic Corporation 23 * The contents of this file are subject to the terms of the 24 * QLogic End User License (the "License"). 25 * You may not use this file except in compliance with the License. 26 * 27 * You can obtain a copy of the License at 28 * http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/ 29 * QLogic_End_User_Software_License.txt 30 * See the License for the specific language governing permissions 31 * and limitations under the License. 32 * 33 *****************************************************************************/ 34 35 #include <ntddk.h> 36 #include <ndis.h> 37 38 #ifndef __FILE_STRIPPED__ 39 #define __FILE_STRIPPED__ strrchr(__FILE__, '\\') ? strrchr(__FILE__, '\\') + 1 : __FILE__ 40 #endif 41 42 // portable integer type of the pointer size for current platform (64/32) 43 typedef ULONG_PTR mm_int_ptr_t; 44 45 typedef NDIS_SPIN_LOCK mm_spin_lock_t; 46 47 #if defined(NDIS31_MINIPORT) || defined(NDIS40_MINIPORT) || defined(NDIS50_MINIPORT) 48 49 #define mm_read_barrier_imp() 50 #define mm_write_barrier_imp() 51 #define mm_barrier_imp() 52 53 #else 54 55 #ifdef _IA64_ 56 #define mm_read_barrier_imp() KeMemoryBarrier() 57 #else 58 #define mm_read_barrier_imp() KeMemoryBarrierWithoutFence() 59 #endif 60 61 #define mm_write_barrier_imp() KeMemoryBarrier() 62 #define mm_barrier_imp() KeMemoryBarrier() 63 64 #endif 65 66 #define mm_atomic_set_imp(_p, _v) InterlockedExchange((long*)(_p), (long)(_v)) 67 68 #define mm_atomic_dec_imp(_p) InterlockedDecrement((long*)(_p)) 69 #define mm_atomic_inc_imp(_p) InterlockedIncrement((long*)(_p)) 70 71 #define mm_atomic_and_imp(_p, _v) InterlockedAnd((long*)(_p), (long)(_v)) 72 #define mm_atomic_long_and_imp(_p, _v) mm_atomic_and_imp((_p), (_v)) 73 74 #define mm_atomic_or_imp(_p, _v) InterlockedOr((long*)(_p), (long)(_v) ) 75 #define mm_atomic_long_or_imp(_p, _v) mm_atomic_or_imp((_p), (_v)) 76 77 #define mm_atomic_read_imp(_p) \ 78 InterlockedExchangeAdd((long*)(_p), (long)(0)) 79 #define mm_atomic_long_read_imp(_p) mm_atomic_read_imp((_p)) 80 81 #define mm_atomic_cmpxchg_imp(_p, _old_val, _new_val) \ 82 InterlockedCompareExchange(_p, (long)_new_val, (long)_old_val ) 83 84 85 #define MM_WRITE_DOORBELL_IMP(PDEV, BAR, CID, VAL) \ 86 LM_BAR_WR32_ADDRESS((PDEV), ((u8_t *)PFDEV(PDEV)->context_info->array[VF_TO_PF_CID((PDEV),(CID))].cid_resc.mapped_cid_bar_addr + (DPM_TRIGER_TYPE)), (VAL)) 87 88 #define MM_REGISTER_LPME_IMP(_pdev, _func, _b_fw_access, _b_queue_for_fw) \ 89 mm_register_lpme((_pdev), (_func), (_b_fw_access), (_b_queue_for_fw)) 90 91 u32_t 92 mm_dcb_mp_l2_is_enable(struct _lm_device_t *pdev); 93 #define MM_DCB_MP_L2_IS_ENABLE(_pdev) (mm_dcb_mp_l2_is_enable(pdev)) 94 95 void MM_ACQUIRE_SPQ_LOCK_IMP(struct _lm_device_t *_pdev); 96 void MM_RELEASE_SPQ_LOCK_IMP(struct _lm_device_t *_pdev); 97 void MM_ACQUIRE_SPQ_LOCK_DPC_IMP(struct _lm_device_t *_pdev); 98 void MM_RELEASE_SPQ_LOCK_DPC_IMP(struct _lm_device_t *_pdev); 99 100 void MM_ACQUIRE_CID_LOCK_IMP(struct _lm_device_t *_pdev); 101 void MM_RELEASE_CID_LOCK_IMP(struct _lm_device_t *_pdev); 102 103 void MM_ACQUIRE_REQUEST_LOCK_IMP(struct _lm_device_t *_pdev); 104 void MM_RELEASE_REQUEST_LOCK_IMP(struct _lm_device_t *_pdev); 105 106 #define MM_ACQUIRE_REQUEST_LOCK_DPC_IMP(pdev) 107 #define MM_RELEASE_REQUEST_LOCK_DPC_IMP(pdev) 108 109 void MM_ACQUIRE_PHY_LOCK_IMP(struct _lm_device_t * pDev); 110 void MM_RELEASE_PHY_LOCK_IMP(struct _lm_device_t * pDev); 111 void MM_ACQUIRE_PHY_LOCK_DPC_IMP(struct _lm_device_t * pDev); 112 void MM_RELEASE_PHY_LOCK_DPC_IMP(struct _lm_device_t * pDev); 113 114 void MM_ACQUIRE_ISLES_CONTROL_LOCK_IMP(struct _lm_device_t *_pdev); 115 void MM_RELEASE_ISLES_CONTROL_LOCK_IMP(struct _lm_device_t *_pdev); 116 void MM_ACQUIRE_ISLES_CONTROL_LOCK_DPC_IMP(struct _lm_device_t *_pdev); 117 void MM_RELEASE_ISLES_CONTROL_LOCK_DPC_IMP(struct _lm_device_t *_pdev); 118 119 #define MM_ACQUIRE_RAMROD_COMP_LOCK_IMP(_pdev) 120 #define MM_RELEASE_RAMROD_COMP_LOCK_IMP(_pdev) 121 122 void MM_ACQUIRE_MCP_LOCK_IMP(struct _lm_device_t *_pdev); 123 void MM_RELEASE_MCP_LOCK_IMP(struct _lm_device_t *_pdev); 124 125 void MM_ACQUIRE_ISLES_CONTROL_LOCK_IMP(struct _lm_device_t *_pdev); 126 void MM_RELEASE_ISLES_CONTROL_LOCK_IMP(struct _lm_device_t *_pdev); 127 void MM_ACQUIRE_ISLES_CONTROL_LOCK_DPC_IMP(struct _lm_device_t *_pdev); 128 void MM_RELEASE_ISLES_CONTROL_LOCK_DPC_IMP(struct _lm_device_t *_pdev); 129 130 void MM_ACQUIRE_IND_REG_LOCK_IMP(struct _lm_device_t *_pdev); 131 void MM_RELEASE_IND_REG_LOCK_IMP(struct _lm_device_t *_pdev); 132 133 void MM_ACQUIRE_LOADER_LOCK_IMP(); 134 void MM_RELEASE_LOADER_LOCK_IMP(); 135 136 void MM_ACQUIRE_SP_REQ_MGR_LOCK_IMP(struct _lm_device_t *_pdev); 137 void MM_RELEASE_SP_REQ_MGR_LOCK_IMP(struct _lm_device_t *_pdev); 138 139 void MM_ACQUIRE_SB_LOCK_IMP(struct _lm_device_t *_pdev, u8_t _sb_idx); 140 void MM_RELEASE_SB_LOCK_IMP(struct _lm_device_t *_pdev, u8_t _sb_idx); 141 142 void MM_ACQUIRE_ETH_CON_LOCK(struct _lm_device_t *_pdev); 143 void MM_RELEASE_ETH_CON_LOCK(struct _lm_device_t *_pdev); 144 145 #ifdef VF_INVOLVED 146 147 void MM_ACQUIRE_PF_LOCK_IMP(struct _lm_device_t *_pdev); 148 void MM_RELEASE_PF_LOCK_IMP(struct _lm_device_t *_pdev); 149 150 void MM_ACQUIRE_VFS_STATS_LOCK_IMP(struct _lm_device_t *_pdev); 151 void MM_RELEASE_VFS_STATS_LOCK_IMP(struct _lm_device_t *_pdev); 152 void MM_ACQUIRE_VFS_STATS_LOCK_DPC_IMP(struct _lm_device_t *_pdev); 153 void MM_RELEASE_VFS_STATS_LOCK_DPC_IMP(struct _lm_device_t *_pdev); 154 155 #endif /* VF_INVOLVED */ 156 157 #define mm_er_initiate_recovery_imp(pdev) \ 158 (LM_STATUS_FAILURE) 159 160 #define mm_register_dpc_imp(_pdev, _func) \ 161 (LM_STATUS_FAILURE) 162 163 void mm_empty_ramrod_received_imp(struct _lm_device_t *pdev, 164 const u32_t empty_data); 165 166 #define mm_dbus_start_if_enabled_imp(pdev) 167 #define mm_dbus_stop_if_started_imp(pdev) 168 169 170 #ifdef BIG_ENDIAN 171 // LE 172 #define mm_le16_to_cpu_imp(val) SWAP_BYTES16(val) 173 #define mm_cpu_to_le16_imp(val) SWAP_BYTES16(val) 174 #define mm_le32_to_cpu_imp(val) SWAP_BYTES32(val) 175 #define mm_cpu_to_le32_imp(val) SWAP_BYTES32(val) 176 // BE 177 #define mm_be32_to_cpu_imp(val) (val) 178 #define mm_cpu_to_be32_imp(val) (val) 179 #define mm_be16_to_cpu_imp(val) (val) 180 #define mm_cpu_to_be16_imp(val) (val) 181 #else /* LITTLE_ENDIAN */ 182 // LE 183 #define mm_le16_to_cpu_imp(val) (val) 184 #define mm_cpu_to_le16_imp(val) (val) 185 #define mm_le32_to_cpu_imp(val) (val) 186 #define mm_cpu_to_le32_imp(val) (val) 187 // BE 188 #define mm_be32_to_cpu_imp(val) SWAP_BYTES32(val) 189 #define mm_cpu_to_be32_imp(val) SWAP_BYTES32(val) 190 #define mm_be16_to_cpu_imp(val) SWAP_BYTES16(val) 191 #define mm_cpu_to_be16_imp(val) SWAP_BYTES16(val) 192 #endif /* ifdef BIG_ENDIAN */ 193 194 195 #define mm_get_bar_offset_imp(pdev, bar_num, bar_addr) \ 196 lm_get_bar_offset_direct(pdev, bar_num, bar_addr) 197 198 #define mm_get_bar_size_imp(pdev, bar_num, val_p) \ 199 lm_get_bar_size_direct(pdev, bar_num, val_p) 200 201