1 #ifdef __LINUX 2 #include <linux/kernel.h> 3 #include <linux/types.h> 4 #include <asm/byteorder.h> 5 #endif 6 #ifdef USER_LINUX 7 #include <stdio.h> 8 #include <unistd.h> 9 #include <sys/types.h> 10 #include <sys/socket.h> 11 #include <netinet/in.h> 12 #include <arpa/inet.h> 13 #include <sys/ioctl.h> 14 #include <net/if.h> 15 #include <linux/sockios.h> 16 #include <string.h> 17 #include <malloc.h> 18 #endif 19 #ifdef __FreeBSD__ 20 #include <sys/types.h> 21 #endif 22 #include "bcmtype.h" 23 #ifdef EDEBUG 24 #include "edebug_types.h" 25 #endif 26 #include "clc.h" 27 #include "grc_addr.h" 28 #include "bigmac_addresses.h" 29 #include "emac_reg_driver.h" 30 #include "misc_bits.h" 31 #include "57712_reg.h" 32 #include "clc_reg.h" 33 #include "dev_info.h" 34 #include "license.h" 35 #include "shmem.h" 36 #include "aeu_inputs.h" 37 38 typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy, 39 struct elink_params *params, 40 u8 dev_addr, u16 addr, u8 byte_cnt, 41 u8 *o_buf, u8); 42 /********************************************************/ 43 #define ELINK_ETH_HLEN 14 44 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 45 #define ELINK_ETH_OVREHEAD (ELINK_ETH_HLEN + 8 + 8) 46 #define ELINK_ETH_MIN_PACKET_SIZE 60 47 #define ELINK_ETH_MAX_PACKET_SIZE 1500 48 #define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600 49 #define ELINK_MDIO_ACCESS_TIMEOUT 1000 50 #define WC_LANE_MAX 4 51 #define I2C_SWITCH_WIDTH 2 52 #define I2C_BSC0 0 53 #define I2C_BSC1 1 54 #define I2C_WA_RETRY_CNT 3 55 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) 56 #define MCPR_IMC_COMMAND_READ_OP 1 57 #define MCPR_IMC_COMMAND_WRITE_OP 2 58 59 /* LED Blink rate that will achieve ~15.9Hz */ 60 #define LED_BLINK_RATE_VAL_E3 354 61 #define LED_BLINK_RATE_VAL_E1X_E2 480 62 /***********************************************************/ 63 /* Macros */ 64 /***********************************************************/ 65 #define MSLEEP(cb, ms) elink_cb_udelay(cb, 1000*ms) 66 #define USLEEP(cb, us) elink_cb_udelay(cb, us) 67 #define REG_RD(cb, reg) elink_cb_reg_read(cb, reg) 68 #define REG_WR(cb, reg, val) elink_cb_reg_write(cb, reg, val) 69 #define EMAC_RD(cb, reg) REG_RD(cb, emac_base + reg) 70 #define EMAC_WR(cb, reg, val) REG_WR(cb, emac_base + reg, val) 71 #define REG_WR_DMAE(cb, offset, wb_data, len) \ 72 elink_cb_reg_wb_write(cb, offset, wb_data, len) 73 #define REG_RD_DMAE(cb, offset, wb_data, len) \ 74 elink_cb_reg_wb_read(cb, offset, wb_data, len) 75 #define PATH_ID(cb) elink_cb_path_id(cb) 76 77 #define ELINK_SET_GPIO elink_cb_gpio_write 78 #define ELINK_SET_MULT_GPIO elink_cb_gpio_mult_write 79 #define ELINK_GET_GPIO elink_cb_gpio_read 80 #define ELINK_SET_GPIO_INT elink_cb_gpio_int_write 81 82 #ifndef OFFSETOF 83 #define OFFSETOF(_s, _m) ((u32) ((u8 *)(&((_s *) 0)->_m) - \ 84 (u8 *)((u8 *) 0))) 85 #endif 86 87 #define CHIP_REV_SHIFT 12 88 #define CHIP_REV_MASK (0xF<<CHIP_REV_SHIFT) 89 #define CHIP_REV(_chip_id) ((_chip_id) & CHIP_REV_MASK) 90 91 #define CHIP_REV_Ax (0x0<<CHIP_REV_SHIFT) 92 #define CHIP_REV_Bx (0x1<<CHIP_REV_SHIFT) 93 #define CHIP_REV_IS_SLOW(_chip_id) \ 94 (CHIP_REV(_chip_id) > 0x00005000) 95 #define CHIP_REV_IS_FPGA(_chip_id) \ 96 (CHIP_REV_IS_SLOW(_chip_id)&& \ 97 (CHIP_REV(_chip_id) & 0x00001000)) 98 #define CHIP_REV_IS_EMUL(_chip_id) \ 99 (CHIP_REV_IS_SLOW(_chip_id)&& \ 100 !(CHIP_REV(_chip_id) & 0x00001000)) 101 102 #define CHIP_NUM(_chip_id) (_chip_id >> 16) 103 #define CHIP_NUM_57710 0x164e 104 #define CHIP_NUM_57711 0x164f 105 #define CHIP_NUM_57711E 0x1650 106 #define CHIP_NUM_57712 0x1662 107 #define CHIP_NUM_57712E 0x1663 108 #define CHIP_NUM_57713 0x1651 109 #define CHIP_NUM_57713E 0x1652 110 #define CHIP_NUM_57840_OBSOLETE 0x168d 111 #define CHIP_NUM_57840_4_10 0x16a1 112 #define CHIP_NUM_57840_2_20 0x16a2 113 #define CHIP_NUM_57810 0x168e 114 #define CHIP_NUM_57800 0x168a 115 #define CHIP_NUM_57811 0x163d 116 #define CHIP_NUM_57811_MF 0x163e 117 #define CHIP_IS_E1(_chip_id) (CHIP_NUM(_chip_id) == \ 118 CHIP_NUM_57710) 119 #define CHIP_IS_E1X(_chip_id) ((CHIP_NUM(_chip_id) == \ 120 CHIP_NUM_57710) || \ 121 (CHIP_NUM(_chip_id) == \ 122 CHIP_NUM_57711) || \ 123 (CHIP_NUM(_chip_id) == \ 124 CHIP_NUM_57711E)) 125 126 #define CHIP_IS_E2(_chip_id) ((CHIP_NUM(_chip_id) == \ 127 CHIP_NUM_57712) || \ 128 (CHIP_NUM(_chip_id) == \ 129 CHIP_NUM_57712E) || \ 130 (CHIP_NUM(_chip_id) == \ 131 CHIP_NUM_57713) || \ 132 (CHIP_NUM(_chip_id) == \ 133 CHIP_NUM_57713E)) 134 135 #define CHIP_IS_57711(_chip_id) (CHIP_NUM(_chip_id) == \ 136 CHIP_NUM_57711) 137 #define CHIP_IS_57711E(_chip_id) (CHIP_NUM(_chip_id) == \ 138 CHIP_NUM_57711E) 139 #define DO_CHIP_IS_E3(_chip_family) ((_chip_family == 0x1630) || \ 140 (_chip_family == 0x1680) || \ 141 (_chip_family == 0x16a0)) 142 #define CHIP_IS_E3(_chip_id) (DO_CHIP_IS_E3(((CHIP_NUM(_chip_id)) & 0xfff0))) 143 144 145 /* For EMUL: Ax=0xE, Bx=0xC, Cx=0xA. For FPGA: Ax=0xF, Bx=0xD, 146 * Cx=0xB. 147 */ 148 #define CHIP_REV_SIM(_p) (((0xF - (CHIP_REV(_p) >> CHIP_REV_SHIFT)) \ 149 >>1) << CHIP_REV_SHIFT) 150 151 #define CHIP_IS_E3B0(_p) (CHIP_IS_E3(_p) && \ 152 ((CHIP_REV(_p) == CHIP_REV_Bx) || \ 153 (CHIP_REV_SIM(_p) == CHIP_REV_Bx))) 154 155 #define CHIP_IS_E3A0(_p) (CHIP_IS_E3(_p) && \ 156 ((CHIP_REV(_p) == CHIP_REV_Ax) || \ 157 (CHIP_REV_SIM(_p) == CHIP_REV_Ax))) 158 159 #define ELINK_USES_WARPCORE(_chip_id) (CHIP_IS_E3(_chip_id)) 160 161 #define SHMEM2_RD(cb, shmem2_base, _field) \ 162 REG_RD(cb, shmem2_base + \ 163 OFFSETOF(struct shmem2_region, \ 164 _field)) 165 166 #define SHMEM2_HAS(cb, shmem2_base, field) (shmem2_base && \ 167 (SHMEM2_RD(cb, shmem2_base, size) > \ 168 OFFSETOF(struct shmem2_region, field))) 169 #ifndef NULL 170 #define NULL ((void *) 0) 171 #endif 172 173 /***********************************************************/ 174 /* Shortcut definitions */ 175 /***********************************************************/ 176 177 #define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0 178 179 #define ELINK_NIG_STATUS_EMAC0_MI_INT \ 180 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT 181 #define ELINK_NIG_STATUS_XGXS0_LINK10G \ 182 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G 183 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \ 184 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS 185 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ 186 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 187 #define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \ 188 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS 189 #define ELINK_NIG_MASK_MI_INT \ 190 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT 191 #define ELINK_NIG_MASK_XGXS0_LINK10G \ 192 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G 193 #define ELINK_NIG_MASK_XGXS0_LINK_STATUS \ 194 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS 195 #define ELINK_NIG_MASK_SERDES0_LINK_STATUS \ 196 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS 197 198 #define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \ 199 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ 200 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) 201 202 #define ELINK_XGXS_RESET_BITS \ 203 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ 204 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ 205 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ 206 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ 207 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) 208 209 #define ELINK_SERDES_RESET_BITS \ 210 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ 211 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ 212 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ 213 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) 214 215 #define ELINK_AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 216 #define ELINK_AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 217 #define ELINK_AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM 218 #define ELINK_AUTONEG_PARALLEL \ 219 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 220 #define ELINK_AUTONEG_SGMII_FIBER_AUTODET \ 221 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 222 #define ELINK_AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 223 224 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ 225 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 226 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ 227 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 228 #define ELINK_GP_STATUS_SPEED_MASK \ 229 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 230 #define ELINK_GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 231 #define ELINK_GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 232 #define ELINK_GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 233 #define ELINK_GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 234 #define ELINK_GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 235 #define ELINK_GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 236 #define ELINK_GP_STATUS_10G_HIG \ 237 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 238 #define ELINK_GP_STATUS_10G_CX4 \ 239 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 240 #define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 241 #define ELINK_GP_STATUS_10G_KX4 \ 242 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 243 #define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 244 #define ELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 245 #define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 246 #define ELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 247 #define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 248 #define ELINK_LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD 249 #define ELINK_LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD 250 #define ELINK_LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD 251 #define ELINK_LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 252 #define ELINK_LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD 253 #define ELINK_LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD 254 #define ELINK_LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD 255 #define ELINK_LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD 256 #define ELINK_LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD 257 #define ELINK_LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD 258 #define ELINK_LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD 259 #define ELINK_LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD 260 #define ELINK_LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD 261 #define ELINK_LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD 262 #define ELINK_LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD 263 264 #define ELINK_LINK_UPDATE_MASK \ 265 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \ 266 LINK_STATUS_LINK_UP | \ 267 LINK_STATUS_PHYSICAL_LINK_FLAG | \ 268 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \ 269 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \ 270 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \ 271 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \ 272 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \ 273 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 274 275 #define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2 276 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0 277 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7 278 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 279 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 280 281 282 #define ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR 0x3 283 #define ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK (1<<4) 284 #define ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK (1<<5) 285 #define ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK (1<<6) 286 #define ELINK_SFP_EEPROM_10G_COMP_CODE_ER_MASK (1<<7) 287 288 #define ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR 0x6 289 #define ELINK_SFP_EEPROM_1G_COMP_CODE_SX (1<<0) 290 #define ELINK_SFP_EEPROM_1G_COMP_CODE_LX (1<<1) 291 #define ELINK_SFP_EEPROM_1G_COMP_CODE_CX (1<<2) 292 #define ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T (1<<3) 293 294 #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8 295 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 296 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 297 298 #define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40 299 #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 300 #define ELINK_SFP_EEPROM_OPTIONS_SIZE 2 301 302 #define ELINK_EDC_MODE_LINEAR 0x0022 303 #define ELINK_EDC_MODE_LIMITING 0x0044 304 #define ELINK_EDC_MODE_PASSIVE_DAC 0x0055 305 #define ELINK_EDC_MODE_ACTIVE_DAC 0x0066 306 307 /* ETS defines*/ 308 #define DCBX_INVALID_COS (0xFF) 309 310 #define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) 311 #define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) 312 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) 313 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) 314 #define ELINK_ETS_E3B0_PBF_MIN_W_VAL (10000) 315 316 #define ELINK_MAX_PACKET_SIZE (9700) 317 #ifdef INCLUDE_WARPCORE_UC_LOAD 318 #define ELINK_WC_UC_TIMEOUT 1000 319 #define ELINK_WC_RDY_TIMEOUT_MSEC 100 320 #endif 321 #define MAX_KR_LINK_RETRY 4 322 323 /**********************************************************/ 324 /* INTERFACE */ 325 /**********************************************************/ 326 327 #define CL22_WR_OVER_CL45(_cb, _phy, _bank, _addr, _val) \ 328 elink_cl45_write(_cb, _phy, \ 329 (_phy)->def_md_devad, \ 330 (_bank + (_addr & 0xf)), \ 331 _val) 332 333 #define CL22_RD_OVER_CL45(_cb, _phy, _bank, _addr, _val) \ 334 elink_cl45_read(_cb, _phy, \ 335 (_phy)->def_md_devad, \ 336 (_bank + (_addr & 0xf)), \ 337 _val) 338 339 #ifdef BNX2X_ADD /* BNX2X_ADD */ 340 static int elink_check_half_open_conn(struct elink_params *params, 341 struct elink_vars *vars, u8 notify); 342 static int elink_sfp_module_detection(struct elink_phy *phy, 343 struct elink_params *params); 344 #endif 345 346 static u32 elink_bits_en(struct elink_dev *cb, u32 reg, u32 bits) 347 { 348 u32 val = REG_RD(cb, reg); 349 350 val |= bits; 351 REG_WR(cb, reg, val); 352 return val; 353 } 354 355 static u32 elink_bits_dis(struct elink_dev *cb, u32 reg, u32 bits) 356 { 357 u32 val = REG_RD(cb, reg); 358 359 val &= ~bits; 360 REG_WR(cb, reg, val); 361 return val; 362 } 363 364 /* 365 * elink_check_lfa - This function checks if link reinitialization is required, 366 * or link flap can be avoided. 367 * 368 * @params: link parameters 369 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed 370 * condition code. 371 */ 372 #ifndef EXCLUDE_NON_COMMON_INIT 373 static int elink_check_lfa(struct elink_params *params) 374 { 375 u32 link_status, cfg_idx, lfa_mask, cfg_size; 376 u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config; 377 u32 saved_val, req_val, eee_status; 378 struct elink_dev *cb = params->cb; 379 380 additional_config = 381 REG_RD(cb, params->lfa_base + 382 OFFSETOF(struct shmem_lfa, additional_config)); 383 384 /* NOTE: must be first condition checked - 385 * to verify DCC bit is cleared in any case! 386 */ 387 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) { 388 ELINK_DEBUG_P0(cb, "No LFA due to DCC flap after clp exit\n"); 389 REG_WR(cb, params->lfa_base + 390 OFFSETOF(struct shmem_lfa, additional_config), 391 additional_config & ~NO_LFA_DUE_TO_DCC_MASK); 392 return LFA_DCC_LFA_DISABLED; 393 } 394 395 /* Verify that link is up */ 396 link_status = REG_RD(cb, params->shmem_base + 397 OFFSETOF(struct shmem_region, 398 port_mb[params->port].link_status)); 399 if (!(link_status & LINK_STATUS_LINK_UP)) 400 return LFA_LINK_DOWN; 401 402 /* if loaded after BOOT from SAN, don't flap the link in any case and 403 * rely on link set by preboot driver 404 */ 405 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN) 406 return 0; 407 408 /* Verify that loopback mode is not set */ 409 if (params->loopback_mode) 410 return LFA_LOOPBACK_ENABLED; 411 412 /* Verify that MFW supports LFA */ 413 if (!params->lfa_base) 414 return LFA_MFW_IS_TOO_OLD; 415 416 if (params->num_phys == 3) { 417 cfg_size = 2; 418 lfa_mask = 0xffffffff; 419 } else { 420 cfg_size = 1; 421 lfa_mask = 0xffff; 422 } 423 424 /* Compare Duplex */ 425 saved_val = REG_RD(cb, params->lfa_base + 426 OFFSETOF(struct shmem_lfa, req_duplex)); 427 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); 428 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 429 ELINK_DEBUG_P2(cb, "Duplex mismatch %x vs. %x\n", 430 (saved_val & lfa_mask), (req_val & lfa_mask)); 431 return LFA_DUPLEX_MISMATCH; 432 } 433 /* Compare Flow Control */ 434 saved_val = REG_RD(cb, params->lfa_base + 435 OFFSETOF(struct shmem_lfa, req_flow_ctrl)); 436 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); 437 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 438 ELINK_DEBUG_P2(cb, "Flow control mismatch %x vs. %x\n", 439 (saved_val & lfa_mask), (req_val & lfa_mask)); 440 return LFA_FLOW_CTRL_MISMATCH; 441 } 442 /* Compare Link Speed */ 443 saved_val = REG_RD(cb, params->lfa_base + 444 OFFSETOF(struct shmem_lfa, req_line_speed)); 445 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); 446 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 447 ELINK_DEBUG_P2(cb, "Link speed mismatch %x vs. %x\n", 448 (saved_val & lfa_mask), (req_val & lfa_mask)); 449 return LFA_LINK_SPEED_MISMATCH; 450 } 451 452 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) { 453 cur_speed_cap_mask = REG_RD(cb, params->lfa_base + 454 OFFSETOF(struct shmem_lfa, 455 speed_cap_mask[cfg_idx])); 456 457 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { 458 ELINK_DEBUG_P2(cb, "Speed Cap mismatch %x vs. %x\n", 459 cur_speed_cap_mask, 460 params->speed_cap_mask[cfg_idx]); 461 return LFA_SPEED_CAP_MISMATCH; 462 } 463 } 464 465 cur_req_fc_auto_adv = 466 REG_RD(cb, params->lfa_base + 467 OFFSETOF(struct shmem_lfa, additional_config)) & 468 REQ_FC_AUTO_ADV_MASK; 469 470 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) { 471 ELINK_DEBUG_P2(cb, "Flow Ctrl AN mismatch %x vs. %x\n", 472 cur_req_fc_auto_adv, params->req_fc_auto_adv); 473 return LFA_FLOW_CTRL_MISMATCH; 474 } 475 476 eee_status = REG_RD(cb, params->shmem2_base + 477 OFFSETOF(struct shmem2_region, 478 eee_status[params->port])); 479 480 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^ 481 (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) || 482 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^ 483 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) { 484 ELINK_DEBUG_P2(cb, "EEE mismatch %x vs. %x\n", params->eee_mode, 485 eee_status); 486 return LFA_EEE_MISMATCH; 487 } 488 489 /* LFA conditions are met */ 490 return 0; 491 } 492 #endif 493 /******************************************************************/ 494 /* EPIO/GPIO section */ 495 /******************************************************************/ 496 #if (!defined EXCLUDE_WARPCORE) 497 static void elink_get_epio(struct elink_dev *cb, u32 epio_pin, u32 *en) 498 { 499 u32 epio_mask, gp_oenable; 500 *en = 0; 501 /* Sanity check */ 502 if (epio_pin > 31) { 503 ELINK_DEBUG_P1(cb, "Invalid EPIO pin %d to get\n", epio_pin); 504 return; 505 } 506 507 epio_mask = 1 << epio_pin; 508 /* Set this EPIO to output */ 509 gp_oenable = REG_RD(cb, MCP_REG_MCPR_GP_OENABLE); 510 REG_WR(cb, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); 511 512 *en = (REG_RD(cb, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; 513 } 514 static void elink_set_epio(struct elink_dev *cb, u32 epio_pin, u32 en) 515 { 516 u32 epio_mask, gp_output, gp_oenable; 517 518 /* Sanity check */ 519 if (epio_pin > 31) { 520 ELINK_DEBUG_P1(cb, "Invalid EPIO pin %d to set\n", epio_pin); 521 return; 522 } 523 ELINK_DEBUG_P2(cb, "Setting EPIO pin %d to %d\n", epio_pin, en); 524 epio_mask = 1 << epio_pin; 525 /* Set this EPIO to output */ 526 gp_output = REG_RD(cb, MCP_REG_MCPR_GP_OUTPUTS); 527 if (en) 528 gp_output |= epio_mask; 529 else 530 gp_output &= ~epio_mask; 531 532 REG_WR(cb, MCP_REG_MCPR_GP_OUTPUTS, gp_output); 533 534 /* Set the value for this EPIO */ 535 gp_oenable = REG_RD(cb, MCP_REG_MCPR_GP_OENABLE); 536 REG_WR(cb, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); 537 } 538 539 static void elink_set_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 val) 540 { 541 if (pin_cfg == PIN_CFG_NA) 542 return; 543 if (pin_cfg >= PIN_CFG_EPIO0) { 544 elink_set_epio(cb, pin_cfg - PIN_CFG_EPIO0, val); 545 } else { 546 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 547 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 548 ELINK_SET_GPIO(cb, gpio_num, (u8)val, gpio_port); 549 } 550 } 551 552 static u32 elink_get_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 *val) 553 { 554 if (pin_cfg == PIN_CFG_NA) 555 return ELINK_STATUS_ERROR; 556 if (pin_cfg >= PIN_CFG_EPIO0) { 557 elink_get_epio(cb, pin_cfg - PIN_CFG_EPIO0, val); 558 } else { 559 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 560 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 561 *val = ELINK_GET_GPIO(cb, gpio_num, gpio_port); 562 } 563 return ELINK_STATUS_OK; 564 565 } 566 #endif /* (!defined EXCLUDE_WARPCORE) */ 567 /******************************************************************/ 568 /* ETS section */ 569 /******************************************************************/ 570 #ifdef ELINK_ENHANCEMENTS 571 static void elink_ets_e2e3a0_disabled(struct elink_params *params) 572 { 573 /* ETS disabled configuration*/ 574 struct elink_dev *cb = params->cb; 575 576 ELINK_DEBUG_P0(cb, "ETS E2E3 disabled configuration\n"); 577 578 /* mapping between entry priority to client number (0,1,2 -debug and 579 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 580 * 3bits client num. 581 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 582 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 583 */ 584 585 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); 586 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 587 * as strict. Bits 0,1,2 - debug and management entries, 3 - 588 * COS0 entry, 4 - COS1 entry. 589 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 590 * bit4 bit3 bit2 bit1 bit0 591 * MCP and debug are strict 592 */ 593 594 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 595 /* defines which entries (clients) are subjected to WFQ arbitration */ 596 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 597 /* For strict priority entries defines the number of consecutive 598 * slots for the highest priority. 599 */ 600 REG_WR(cb, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 601 /* mapping between the CREDIT_WEIGHT registers and actual client 602 * numbers 603 */ 604 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); 605 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); 606 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); 607 608 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); 609 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); 610 REG_WR(cb, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); 611 /* ETS mode disable */ 612 REG_WR(cb, PBF_REG_ETS_ENABLED, 0); 613 /* If ETS mode is enabled (there is no strict priority) defines a WFQ 614 * weight for COS0/COS1. 615 */ 616 REG_WR(cb, PBF_REG_COS0_WEIGHT, 0x2710); 617 REG_WR(cb, PBF_REG_COS1_WEIGHT, 0x2710); 618 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ 619 REG_WR(cb, PBF_REG_COS0_UPPER_BOUND, 0x989680); 620 REG_WR(cb, PBF_REG_COS1_UPPER_BOUND, 0x989680); 621 /* Defines the number of consecutive slots for the strict priority */ 622 REG_WR(cb, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 623 } 624 /****************************************************************************** 625 * Description: 626 * Getting min_w_val will be set according to line speed . 627 *. 628 ******************************************************************************/ 629 static u32 elink_ets_get_min_w_val_nig(const struct elink_vars *vars) 630 { 631 u32 min_w_val = 0; 632 /* Calculate min_w_val.*/ 633 if (vars->link_up) { 634 if (vars->line_speed == ELINK_SPEED_20000) 635 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 636 else 637 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; 638 } else 639 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 640 /* If the link isn't up (static configuration for example ) The 641 * link will be according to 20GBPS. 642 */ 643 return min_w_val; 644 } 645 /****************************************************************************** 646 * Description: 647 * Getting credit upper bound form min_w_val. 648 *. 649 ******************************************************************************/ 650 static u32 elink_ets_get_credit_upper_bound(const u32 min_w_val) 651 { 652 const u32 credit_upper_bound = (u32)ELINK_MAXVAL((150 * min_w_val), 653 ELINK_MAX_PACKET_SIZE); 654 return credit_upper_bound; 655 } 656 /****************************************************************************** 657 * Description: 658 * Set credit upper bound for NIG. 659 *. 660 ******************************************************************************/ 661 static void elink_ets_e3b0_set_credit_upper_bound_nig( 662 const struct elink_params *params, 663 const u32 min_w_val) 664 { 665 struct elink_dev *cb = params->cb; 666 const u8 port = params->port; 667 const u32 credit_upper_bound = 668 elink_ets_get_credit_upper_bound(min_w_val); 669 670 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : 671 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); 672 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : 673 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); 674 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : 675 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); 676 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : 677 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); 678 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : 679 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); 680 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : 681 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); 682 683 if (!port) { 684 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, 685 credit_upper_bound); 686 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, 687 credit_upper_bound); 688 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, 689 credit_upper_bound); 690 } 691 } 692 /****************************************************************************** 693 * Description: 694 * Will return the NIG ETS registers to init values.Except 695 * credit_upper_bound. 696 * That isn't used in this configuration (No WFQ is enabled) and will be 697 * configured acording to spec 698 *. 699 ******************************************************************************/ 700 static void elink_ets_e3b0_nig_disabled(const struct elink_params *params, 701 const struct elink_vars *vars) 702 { 703 struct elink_dev *cb = params->cb; 704 const u8 port = params->port; 705 const u32 min_w_val = elink_ets_get_min_w_val_nig(vars); 706 /* Mapping between entry priority to client number (0,1,2 -debug and 707 * management clients, 3 - COS0 client, 4 - COS1, ... 8 - 708 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by 709 * reset value or init tool 710 */ 711 if (port) { 712 REG_WR(cb, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); 713 REG_WR(cb, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); 714 } else { 715 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); 716 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); 717 } 718 /* For strict priority entries defines the number of consecutive 719 * slots for the highest priority. 720 */ 721 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : 722 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 723 /* Mapping between the CREDIT_WEIGHT registers and actual client 724 * numbers 725 */ 726 if (port) { 727 /*Port 1 has 6 COS*/ 728 REG_WR(cb, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); 729 REG_WR(cb, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); 730 } else { 731 /*Port 0 has 9 COS*/ 732 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 733 0x43210876); 734 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); 735 } 736 737 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 738 * as strict. Bits 0,1,2 - debug and management entries, 3 - 739 * COS0 entry, 4 - COS1 entry. 740 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 741 * bit4 bit3 bit2 bit1 bit0 742 * MCP and debug are strict 743 */ 744 if (port) 745 REG_WR(cb, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); 746 else 747 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); 748 /* defines which entries (clients) are subjected to WFQ arbitration */ 749 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 750 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 751 752 /* Please notice the register address are note continuous and a 753 * for here is note appropriate.In 2 port mode port0 only COS0-5 754 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 755 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT 756 * are never used for WFQ 757 */ 758 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 759 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); 760 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 761 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); 762 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 763 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); 764 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : 765 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); 766 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : 767 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); 768 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : 769 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); 770 if (!port) { 771 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); 772 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); 773 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); 774 } 775 776 elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); 777 } 778 /****************************************************************************** 779 * Description: 780 * Set credit upper bound for PBF. 781 *. 782 ******************************************************************************/ 783 static void elink_ets_e3b0_set_credit_upper_bound_pbf( 784 const struct elink_params *params, 785 const u32 min_w_val) 786 { 787 struct elink_dev *cb = params->cb; 788 const u32 credit_upper_bound = 789 elink_ets_get_credit_upper_bound(min_w_val); 790 const u8 port = params->port; 791 u32 base_upper_bound = 0; 792 u8 max_cos = 0; 793 u8 i = 0; 794 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 795 * port mode port1 has COS0-2 that can be used for WFQ. 796 */ 797 if (!port) { 798 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; 799 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 800 } else { 801 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; 802 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1; 803 } 804 805 for (i = 0; i < max_cos; i++) 806 REG_WR(cb, base_upper_bound + (i << 2), credit_upper_bound); 807 } 808 809 /****************************************************************************** 810 * Description: 811 * Will return the PBF ETS registers to init values.Except 812 * credit_upper_bound. 813 * That isn't used in this configuration (No WFQ is enabled) and will be 814 * configured acording to spec 815 *. 816 ******************************************************************************/ 817 static void elink_ets_e3b0_pbf_disabled(const struct elink_params *params) 818 { 819 struct elink_dev *cb = params->cb; 820 const u8 port = params->port; 821 const u32 min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL; 822 u8 i = 0; 823 u32 base_weight = 0; 824 u8 max_cos = 0; 825 826 /* Mapping between entry priority to client number 0 - COS0 827 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. 828 * TODO_ETS - Should be done by reset value or init tool 829 */ 830 if (port) 831 /* 0x688 (|011|0 10|00 1|000) */ 832 REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); 833 else 834 /* (10 1|100 |011|0 10|00 1|000) */ 835 REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); 836 837 /* TODO_ETS - Should be done by reset value or init tool */ 838 if (port) 839 /* 0x688 (|011|0 10|00 1|000)*/ 840 REG_WR(cb, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); 841 else 842 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ 843 REG_WR(cb, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); 844 845 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : 846 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); 847 848 849 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 850 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); 851 852 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 853 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); 854 /* In 2 port mode port0 has COS0-5 that can be used for WFQ. 855 * In 4 port mode port1 has COS0-2 that can be used for WFQ. 856 */ 857 if (!port) { 858 base_weight = PBF_REG_COS0_WEIGHT_P0; 859 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 860 } else { 861 base_weight = PBF_REG_COS0_WEIGHT_P1; 862 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1; 863 } 864 865 for (i = 0; i < max_cos; i++) 866 REG_WR(cb, base_weight + (0x4 * i), 0); 867 868 elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 869 } 870 /****************************************************************************** 871 * Description: 872 * E3B0 disable will return basicly the values to init values. 873 *. 874 ******************************************************************************/ 875 static elink_status_t elink_ets_e3b0_disabled(const struct elink_params *params, 876 const struct elink_vars *vars) 877 { 878 struct elink_dev *cb = params->cb; 879 880 if (!CHIP_IS_E3B0(params->chip_id)) { 881 ELINK_DEBUG_P0(cb, 882 "elink_ets_e3b0_disabled the chip isn't E3B0\n"); 883 return ELINK_STATUS_ERROR; 884 } 885 886 elink_ets_e3b0_nig_disabled(params, vars); 887 888 elink_ets_e3b0_pbf_disabled(params); 889 890 return ELINK_STATUS_OK; 891 } 892 893 /****************************************************************************** 894 * Description: 895 * Disable will return basicly the values to init values. 896 * 897 ******************************************************************************/ 898 elink_status_t elink_ets_disabled(struct elink_params *params, 899 struct elink_vars *vars) 900 { 901 struct elink_dev *cb = params->cb; 902 elink_status_t elink_status = ELINK_STATUS_OK; 903 904 if ((CHIP_IS_E2(params->chip_id)) || (CHIP_IS_E3A0(params->chip_id))) 905 elink_ets_e2e3a0_disabled(params); 906 else if (CHIP_IS_E3B0(params->chip_id)) 907 elink_status = elink_ets_e3b0_disabled(params, vars); 908 else { 909 ELINK_DEBUG_P0(cb, "elink_ets_disabled - chip not supported\n"); 910 return ELINK_STATUS_ERROR; 911 } 912 913 return elink_status; 914 } 915 916 /****************************************************************************** 917 * Description 918 * Set the COS mappimg to SP and BW until this point all the COS are not 919 * set as SP or BW. 920 ******************************************************************************/ 921 static elink_status_t elink_ets_e3b0_cli_map(const struct elink_params *params, 922 const struct elink_ets_params *ets_params, 923 const u8 cos_sp_bitmap, 924 const u8 cos_bw_bitmap) 925 { 926 struct elink_dev *cb = params->cb; 927 const u8 port = params->port; 928 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); 929 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap; 930 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; 931 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; 932 933 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : 934 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); 935 936 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 937 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap); 938 939 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 940 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 941 nig_cli_subject2wfq_bitmap); 942 943 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 944 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, 945 pbf_cli_subject2wfq_bitmap); 946 947 return ELINK_STATUS_OK; 948 } 949 950 /****************************************************************************** 951 * Description: 952 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 953 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 954 ******************************************************************************/ 955 static elink_status_t elink_ets_e3b0_set_cos_bw(struct elink_dev *cb, 956 const u8 cos_entry, 957 const u32 min_w_val_nig, 958 const u32 min_w_val_pbf, 959 const u16 total_bw, 960 const u8 bw, 961 const u8 port) 962 { 963 u32 nig_reg_adress_crd_weight = 0; 964 u32 pbf_reg_adress_crd_weight = 0; 965 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ 966 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; 967 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; 968 969 switch (cos_entry) { 970 case 0: 971 nig_reg_adress_crd_weight = 972 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 973 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; 974 pbf_reg_adress_crd_weight = (port) ? 975 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; 976 break; 977 case 1: 978 nig_reg_adress_crd_weight = (port) ? 979 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 980 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; 981 pbf_reg_adress_crd_weight = (port) ? 982 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; 983 break; 984 case 2: 985 nig_reg_adress_crd_weight = (port) ? 986 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 987 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; 988 989 pbf_reg_adress_crd_weight = (port) ? 990 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; 991 break; 992 case 3: 993 if (port) 994 return ELINK_STATUS_ERROR; 995 nig_reg_adress_crd_weight = 996 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; 997 pbf_reg_adress_crd_weight = 998 PBF_REG_COS3_WEIGHT_P0; 999 break; 1000 case 4: 1001 if (port) 1002 return ELINK_STATUS_ERROR; 1003 nig_reg_adress_crd_weight = 1004 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; 1005 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0; 1006 break; 1007 case 5: 1008 if (port) 1009 return ELINK_STATUS_ERROR; 1010 nig_reg_adress_crd_weight = 1011 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; 1012 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0; 1013 break; 1014 } 1015 1016 REG_WR(cb, nig_reg_adress_crd_weight, cos_bw_nig); 1017 1018 REG_WR(cb, pbf_reg_adress_crd_weight, cos_bw_pbf); 1019 1020 return ELINK_STATUS_OK; 1021 } 1022 /****************************************************************************** 1023 * Description: 1024 * Calculate the total BW.A value of 0 isn't legal. 1025 * 1026 ******************************************************************************/ 1027 static elink_status_t elink_ets_e3b0_get_total_bw( 1028 const struct elink_params *params, 1029 struct elink_ets_params *ets_params, 1030 u16 *total_bw) 1031 { 1032 struct elink_dev *cb = params->cb; 1033 u8 cos_idx = 0; 1034 u8 is_bw_cos_exist = 0; 1035 1036 *total_bw = 0 ; 1037 /* Calculate total BW requested */ 1038 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { 1039 if (ets_params->cos[cos_idx].state == elink_cos_state_bw) { 1040 is_bw_cos_exist = 1; 1041 if (!ets_params->cos[cos_idx].params.bw_params.bw) { 1042 ELINK_DEBUG_P0(cb, "elink_ets_E3B0_config BW" 1043 "was set to 0\n"); 1044 /* This is to prevent a state when ramrods 1045 * can't be sent 1046 */ 1047 ets_params->cos[cos_idx].params.bw_params.bw 1048 = 1; 1049 } 1050 *total_bw += 1051 ets_params->cos[cos_idx].params.bw_params.bw; 1052 } 1053 } 1054 1055 /* Check total BW is valid */ 1056 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { 1057 if (*total_bw == 0) { 1058 ELINK_DEBUG_P0(cb, 1059 "elink_ets_E3B0_config total BW shouldn't be 0\n"); 1060 return ELINK_STATUS_ERROR; 1061 } 1062 ELINK_DEBUG_P0(cb, 1063 "elink_ets_E3B0_config total BW should be 100\n"); 1064 /* We can handle a case whre the BW isn't 100 this can happen 1065 * if the TC are joined. 1066 */ 1067 } 1068 return ELINK_STATUS_OK; 1069 } 1070 1071 /****************************************************************************** 1072 * Description: 1073 * Invalidate all the sp_pri_to_cos. 1074 * 1075 ******************************************************************************/ 1076 static void elink_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos) 1077 { 1078 u8 pri = 0; 1079 for (pri = 0; pri < ELINK_DCBX_MAX_NUM_COS; pri++) 1080 sp_pri_to_cos[pri] = DCBX_INVALID_COS; 1081 } 1082 /****************************************************************************** 1083 * Description: 1084 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 1085 * according to sp_pri_to_cos. 1086 * 1087 ******************************************************************************/ 1088 static elink_status_t elink_ets_e3b0_sp_pri_to_cos_set(const struct elink_params *params, 1089 u8 *sp_pri_to_cos, const u8 pri, 1090 const u8 cos_entry) 1091 { 1092 struct elink_dev *cb = params->cb; 1093 const u8 port = params->port; 1094 const u8 max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 : 1095 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 1096 1097 if (pri >= max_num_of_cos) { 1098 ELINK_DEBUG_P0(cb, "elink_ets_e3b0_sp_pri_to_cos_set invalid " 1099 "parameter Illegal strict priority\n"); 1100 return ELINK_STATUS_ERROR; 1101 } 1102 1103 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { 1104 ELINK_DEBUG_P0(cb, "elink_ets_e3b0_sp_pri_to_cos_set invalid " 1105 "parameter There can't be two COS's with " 1106 "the same strict pri\n"); 1107 return ELINK_STATUS_ERROR; 1108 } 1109 1110 sp_pri_to_cos[pri] = cos_entry; 1111 return ELINK_STATUS_OK; 1112 1113 } 1114 1115 /****************************************************************************** 1116 * Description: 1117 * Returns the correct value according to COS and priority in 1118 * the sp_pri_cli register. 1119 * 1120 ******************************************************************************/ 1121 static u64 elink_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset, 1122 const u8 pri_set, 1123 const u8 pri_offset, 1124 const u8 entry_size) 1125 { 1126 u64 pri_cli_nig = 0; 1127 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size * 1128 (pri_set + pri_offset)); 1129 1130 return pri_cli_nig; 1131 } 1132 /****************************************************************************** 1133 * Description: 1134 * Returns the correct value according to COS and priority in the 1135 * sp_pri_cli register for NIG. 1136 * 1137 ******************************************************************************/ 1138 static u64 elink_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set) 1139 { 1140 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1141 const u8 nig_cos_offset = 3; 1142 const u8 nig_pri_offset = 3; 1143 1144 return elink_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, 1145 nig_pri_offset, 4); 1146 1147 } 1148 /****************************************************************************** 1149 * Description: 1150 * Returns the correct value according to COS and priority in the 1151 * sp_pri_cli register for PBF. 1152 * 1153 ******************************************************************************/ 1154 static u64 elink_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set) 1155 { 1156 const u8 pbf_cos_offset = 0; 1157 const u8 pbf_pri_offset = 0; 1158 1159 return elink_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, 1160 pbf_pri_offset, 3); 1161 1162 } 1163 1164 /****************************************************************************** 1165 * Description: 1166 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 1167 * according to sp_pri_to_cos.(which COS has higher priority) 1168 * 1169 ******************************************************************************/ 1170 static elink_status_t elink_ets_e3b0_sp_set_pri_cli_reg(const struct elink_params *params, 1171 u8 *sp_pri_to_cos) 1172 { 1173 struct elink_dev *cb = params->cb; 1174 u8 i = 0; 1175 const u8 port = params->port; 1176 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1177 u64 pri_cli_nig = 0x210; 1178 u32 pri_cli_pbf = 0x0; 1179 u8 pri_set = 0; 1180 u8 pri_bitmask = 0; 1181 const u8 max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 : 1182 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 1183 1184 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1; 1185 1186 /* Set all the strict priority first */ 1187 for (i = 0; i < max_num_of_cos; i++) { 1188 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { 1189 if (sp_pri_to_cos[i] >= ELINK_DCBX_MAX_NUM_COS) { 1190 ELINK_DEBUG_P0(cb, 1191 "elink_ets_e3b0_sp_set_pri_cli_reg " 1192 "invalid cos entry\n"); 1193 return ELINK_STATUS_ERROR; 1194 } 1195 1196 pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig( 1197 sp_pri_to_cos[i], pri_set); 1198 1199 pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf( 1200 sp_pri_to_cos[i], pri_set); 1201 pri_bitmask = 1 << sp_pri_to_cos[i]; 1202 /* COS is used remove it from bitmap.*/ 1203 if (!(pri_bitmask & cos_bit_to_set)) { 1204 ELINK_DEBUG_P0(cb, 1205 "elink_ets_e3b0_sp_set_pri_cli_reg " 1206 "invalid There can't be two COS's with" 1207 " the same strict pri\n"); 1208 return ELINK_STATUS_ERROR; 1209 } 1210 cos_bit_to_set &= ~pri_bitmask; 1211 pri_set++; 1212 } 1213 } 1214 1215 /* Set all the Non strict priority i= COS*/ 1216 for (i = 0; i < max_num_of_cos; i++) { 1217 pri_bitmask = 1 << i; 1218 /* Check if COS was already used for SP */ 1219 if (pri_bitmask & cos_bit_to_set) { 1220 /* COS wasn't used for SP */ 1221 pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig( 1222 i, pri_set); 1223 1224 pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf( 1225 i, pri_set); 1226 /* COS is used remove it from bitmap.*/ 1227 cos_bit_to_set &= ~pri_bitmask; 1228 pri_set++; 1229 } 1230 } 1231 1232 if (pri_set != max_num_of_cos) { 1233 ELINK_DEBUG_P0(cb, "elink_ets_e3b0_sp_set_pri_cli_reg not all " 1234 "entries were set\n"); 1235 return ELINK_STATUS_ERROR; 1236 } 1237 1238 if (port) { 1239 /* Only 6 usable clients*/ 1240 REG_WR(cb, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 1241 (u32)pri_cli_nig); 1242 1243 REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); 1244 } else { 1245 /* Only 9 usable clients*/ 1246 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig); 1247 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF); 1248 1249 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 1250 pri_cli_nig_lsb); 1251 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 1252 pri_cli_nig_msb); 1253 1254 REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); 1255 } 1256 return ELINK_STATUS_OK; 1257 } 1258 1259 /****************************************************************************** 1260 * Description: 1261 * Configure the COS to ETS according to BW and SP settings. 1262 ******************************************************************************/ 1263 elink_status_t elink_ets_e3b0_config(const struct elink_params *params, 1264 const struct elink_vars *vars, 1265 struct elink_ets_params *ets_params) 1266 { 1267 struct elink_dev *cb = params->cb; 1268 elink_status_t elink_status = ELINK_STATUS_OK; 1269 const u8 port = params->port; 1270 u16 total_bw = 0; 1271 const u32 min_w_val_nig = elink_ets_get_min_w_val_nig(vars); 1272 const u32 min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL; 1273 u8 cos_bw_bitmap = 0; 1274 u8 cos_sp_bitmap = 0; 1275 u8 sp_pri_to_cos[ELINK_DCBX_MAX_NUM_COS] = {0}; 1276 const u8 max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 : 1277 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 1278 u8 cos_entry = 0; 1279 1280 if (!CHIP_IS_E3B0(params->chip_id)) { 1281 ELINK_DEBUG_P0(cb, 1282 "elink_ets_e3b0_disabled the chip isn't E3B0\n"); 1283 return ELINK_STATUS_ERROR; 1284 } 1285 1286 if ((ets_params->num_of_cos > max_num_of_cos)) { 1287 ELINK_DEBUG_P0(cb, "elink_ets_E3B0_config the number of COS " 1288 "isn't supported\n"); 1289 return ELINK_STATUS_ERROR; 1290 } 1291 1292 /* Prepare sp strict priority parameters*/ 1293 elink_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); 1294 1295 /* Prepare BW parameters*/ 1296 elink_status = elink_ets_e3b0_get_total_bw(params, ets_params, 1297 &total_bw); 1298 if (elink_status != ELINK_STATUS_OK) { 1299 ELINK_DEBUG_P0(cb, 1300 "elink_ets_E3B0_config get_total_bw failed\n"); 1301 return ELINK_STATUS_ERROR; 1302 } 1303 1304 /* Upper bound is set according to current link speed (min_w_val 1305 * should be the same for upper bound and COS credit val). 1306 */ 1307 elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); 1308 elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 1309 1310 1311 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { 1312 if (elink_cos_state_bw == ets_params->cos[cos_entry].state) { 1313 cos_bw_bitmap |= (1 << cos_entry); 1314 /* The function also sets the BW in HW(not the mappin 1315 * yet) 1316 */ 1317 elink_status = elink_ets_e3b0_set_cos_bw( 1318 cb, cos_entry, min_w_val_nig, min_w_val_pbf, 1319 total_bw, 1320 ets_params->cos[cos_entry].params.bw_params.bw, 1321 port); 1322 } else if (elink_cos_state_strict == 1323 ets_params->cos[cos_entry].state){ 1324 cos_sp_bitmap |= (1 << cos_entry); 1325 1326 elink_status = elink_ets_e3b0_sp_pri_to_cos_set( 1327 params, 1328 sp_pri_to_cos, 1329 ets_params->cos[cos_entry].params.sp_params.pri, 1330 cos_entry); 1331 1332 } else { 1333 ELINK_DEBUG_P0(cb, 1334 "elink_ets_e3b0_config cos state not valid\n"); 1335 return ELINK_STATUS_ERROR; 1336 } 1337 if (elink_status != ELINK_STATUS_OK) { 1338 ELINK_DEBUG_P0(cb, 1339 "elink_ets_e3b0_config set cos bw failed\n"); 1340 return elink_status; 1341 } 1342 } 1343 1344 /* Set SP register (which COS has higher priority) */ 1345 elink_status = elink_ets_e3b0_sp_set_pri_cli_reg(params, 1346 sp_pri_to_cos); 1347 1348 if (elink_status != ELINK_STATUS_OK) { 1349 ELINK_DEBUG_P0(cb, 1350 "elink_ets_E3B0_config set_pri_cli_reg failed\n"); 1351 return elink_status; 1352 } 1353 1354 /* Set client mapping of BW and strict */ 1355 elink_status = elink_ets_e3b0_cli_map(params, ets_params, 1356 cos_sp_bitmap, 1357 cos_bw_bitmap); 1358 1359 if (elink_status != ELINK_STATUS_OK) { 1360 ELINK_DEBUG_P0(cb, "elink_ets_E3B0_config SP failed\n"); 1361 return elink_status; 1362 } 1363 return ELINK_STATUS_OK; 1364 } 1365 static void elink_ets_bw_limit_common(const struct elink_params *params) 1366 { 1367 /* ETS disabled configuration */ 1368 struct elink_dev *cb = params->cb; 1369 ELINK_DEBUG_P0(cb, "ETS enabled BW limit configuration\n"); 1370 /* Defines which entries (clients) are subjected to WFQ arbitration 1371 * COS0 0x8 1372 * COS1 0x10 1373 */ 1374 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); 1375 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual 1376 * client numbers (WEIGHT_0 does not actually have to represent 1377 * client 0) 1378 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1379 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 1380 */ 1381 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); 1382 1383 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 1384 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1385 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 1386 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1387 1388 /* ETS mode enabled*/ 1389 REG_WR(cb, PBF_REG_ETS_ENABLED, 1); 1390 1391 /* Defines the number of consecutive slots for the strict priority */ 1392 REG_WR(cb, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 1393 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1394 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 1395 * entry, 4 - COS1 entry. 1396 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1397 * bit4 bit3 bit2 bit1 bit0 1398 * MCP and debug are strict 1399 */ 1400 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 1401 1402 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ 1403 REG_WR(cb, PBF_REG_COS0_UPPER_BOUND, 1404 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1405 REG_WR(cb, PBF_REG_COS1_UPPER_BOUND, 1406 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1407 } 1408 1409 void elink_ets_bw_limit(const struct elink_params *params, const u32 cos0_bw, 1410 const u32 cos1_bw) 1411 { 1412 /* ETS disabled configuration*/ 1413 struct elink_dev *cb = params->cb; 1414 const u32 total_bw = cos0_bw + cos1_bw; 1415 u32 cos0_credit_weight = 0; 1416 u32 cos1_credit_weight = 0; 1417 1418 ELINK_DEBUG_P0(cb, "ETS enabled BW limit configuration\n"); 1419 1420 if ((!total_bw) || 1421 (!cos0_bw) || 1422 (!cos1_bw)) { 1423 ELINK_DEBUG_P0(cb, "Total BW can't be zero\n"); 1424 return; 1425 } 1426 1427 cos0_credit_weight = (cos0_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1428 total_bw; 1429 cos1_credit_weight = (cos1_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1430 total_bw; 1431 1432 elink_ets_bw_limit_common(params); 1433 1434 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); 1435 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); 1436 1437 REG_WR(cb, PBF_REG_COS0_WEIGHT, cos0_credit_weight); 1438 REG_WR(cb, PBF_REG_COS1_WEIGHT, cos1_credit_weight); 1439 } 1440 1441 elink_status_t elink_ets_strict(const struct elink_params *params, const u8 strict_cos) 1442 { 1443 /* ETS disabled configuration*/ 1444 struct elink_dev *cb = params->cb; 1445 u32 val = 0; 1446 1447 ELINK_DEBUG_P0(cb, "ETS enabled strict configuration\n"); 1448 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1449 * as strict. Bits 0,1,2 - debug and management entries, 1450 * 3 - COS0 entry, 4 - COS1 entry. 1451 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1452 * bit4 bit3 bit2 bit1 bit0 1453 * MCP and debug are strict 1454 */ 1455 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); 1456 /* For strict priority entries defines the number of consecutive slots 1457 * for the highest priority. 1458 */ 1459 REG_WR(cb, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 1460 /* ETS mode disable */ 1461 REG_WR(cb, PBF_REG_ETS_ENABLED, 0); 1462 /* Defines the number of consecutive slots for the strict priority */ 1463 REG_WR(cb, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); 1464 1465 /* Defines the number of consecutive slots for the strict priority */ 1466 REG_WR(cb, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); 1467 1468 /* Mapping between entry priority to client number (0,1,2 -debug and 1469 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 1470 * 3bits client num. 1471 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1472 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 1473 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 1474 */ 1475 val = (!strict_cos) ? 0x2318 : 0x22E0; 1476 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); 1477 1478 return ELINK_STATUS_OK; 1479 } 1480 #endif /* ELINK_ENHANCEMENTS */ 1481 1482 /******************************************************************/ 1483 /* PFC section */ 1484 /******************************************************************/ 1485 #ifndef EXCLUDE_NON_COMMON_INIT 1486 #ifndef EXCLUDE_WARPCORE 1487 static void elink_update_pfc_xmac(struct elink_params *params, 1488 struct elink_vars *vars, 1489 u8 is_lb) 1490 { 1491 struct elink_dev *cb = params->cb; 1492 u32 xmac_base; 1493 u32 pause_val, pfc0_val, pfc1_val; 1494 1495 /* XMAC base adrr */ 1496 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1497 1498 /* Initialize pause and pfc registers */ 1499 pause_val = 0x18000; 1500 pfc0_val = 0xFFFF8000; 1501 pfc1_val = 0x2; 1502 1503 /* No PFC support */ 1504 if (!(params->feature_config_flags & 1505 ELINK_FEATURE_CONFIG_PFC_ENABLED)) { 1506 1507 /* RX flow control - Process pause frame in receive direction 1508 */ 1509 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) 1510 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; 1511 1512 /* TX flow control - Send pause packet when buffer is full */ 1513 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) 1514 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; 1515 } else {/* PFC support */ 1516 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | 1517 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | 1518 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | 1519 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | 1520 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1521 /* Write pause and PFC registers */ 1522 REG_WR(cb, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1523 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1524 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1525 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1526 1527 } 1528 1529 /* Write pause and PFC registers */ 1530 REG_WR(cb, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1531 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1532 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1533 1534 1535 /* Set MAC address for source TX Pause/PFC frames */ 1536 REG_WR(cb, xmac_base + XMAC_REG_CTRL_SA_LO, 1537 ((params->mac_addr[2] << 24) | 1538 (params->mac_addr[3] << 16) | 1539 (params->mac_addr[4] << 8) | 1540 (params->mac_addr[5]))); 1541 REG_WR(cb, xmac_base + XMAC_REG_CTRL_SA_HI, 1542 ((params->mac_addr[0] << 8) | 1543 (params->mac_addr[1]))); 1544 1545 USLEEP(cb, 30); 1546 } 1547 1548 #endif // EXCLUDE_WARPCORE 1549 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 1550 #ifdef ELINK_ENHANCEMENTS 1551 #ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */ 1552 static void elink_emac_get_pfc_stat(struct elink_params *params, 1553 u32 pfc_frames_sent[2], 1554 u32 pfc_frames_received[2]) 1555 { 1556 /* Read pfc statistic */ 1557 struct elink_dev *cb = params->cb; 1558 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1559 u32 val_xon = 0; 1560 u32 val_xoff = 0; 1561 1562 ELINK_DEBUG_P0(cb, "pfc statistic read from EMAC\n"); 1563 1564 /* PFC received frames */ 1565 val_xoff = REG_RD(cb, emac_base + 1566 EMAC_REG_RX_PFC_STATS_XOFF_RCVD); 1567 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT; 1568 val_xon = REG_RD(cb, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD); 1569 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT; 1570 1571 pfc_frames_received[0] = val_xon + val_xoff; 1572 1573 /* PFC received sent */ 1574 val_xoff = REG_RD(cb, emac_base + 1575 EMAC_REG_RX_PFC_STATS_XOFF_SENT); 1576 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT; 1577 val_xon = REG_RD(cb, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT); 1578 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT; 1579 1580 pfc_frames_sent[0] = val_xon + val_xoff; 1581 } 1582 1583 /* Read pfc statistic*/ 1584 void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars, 1585 u32 pfc_frames_sent[2], 1586 u32 pfc_frames_received[2]) 1587 { 1588 /* Read pfc statistic */ 1589 struct elink_dev *cb = params->cb; 1590 1591 ELINK_DEBUG_P0(cb, "pfc statistic\n"); 1592 1593 if (!vars->link_up) 1594 return; 1595 1596 if (vars->mac_type == ELINK_MAC_TYPE_EMAC) { 1597 ELINK_DEBUG_P0(cb, "About to read PFC stats from EMAC\n"); 1598 elink_emac_get_pfc_stat(params, pfc_frames_sent, 1599 pfc_frames_received); 1600 } 1601 } 1602 #endif /* ! BNX2X_UPSTREAM */ 1603 #endif /* ELINK_ENHANCEMENTS */ 1604 /******************************************************************/ 1605 /* MAC/PBF section */ 1606 /******************************************************************/ 1607 static void elink_set_mdio_clk(struct elink_dev *cb, u32 chip_id, 1608 u32 emac_base) 1609 { 1610 u32 new_mode, cur_mode; 1611 u32 clc_cnt; 1612 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz 1613 * (a value of 49==0x31) and make sure that the AUTO poll is off 1614 */ 1615 cur_mode = REG_RD(cb, emac_base + EMAC_REG_EMAC_MDIO_MODE); 1616 1617 if (ELINK_USES_WARPCORE(chip_id)) 1618 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 1619 else 1620 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 1621 1622 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) && 1623 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45))) 1624 return; 1625 1626 new_mode = cur_mode & 1627 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); 1628 new_mode |= clc_cnt; 1629 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45); 1630 1631 ELINK_DEBUG_P2(cb, "Changing emac_mode from 0x%x to 0x%x\n", 1632 cur_mode, new_mode); 1633 REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); 1634 USLEEP(cb, 40); 1635 } 1636 1637 #ifndef EXCLUDE_WARPCORE 1638 static u8 elink_is_4_port_mode(struct elink_dev *cb) 1639 { 1640 u32 port4mode_ovwr_val; 1641 /* Check 4-port override enabled */ 1642 port4mode_ovwr_val = REG_RD(cb, MISC_REG_PORT4MODE_EN_OVWR); 1643 if (port4mode_ovwr_val & (1<<0)) { 1644 /* Return 4-port mode override value */ 1645 return ((port4mode_ovwr_val & (1<<1)) == (1<<1)); 1646 } 1647 /* Return 4-port mode from input pin */ 1648 return (u8)REG_RD(cb, MISC_REG_PORT4MODE_EN); 1649 } 1650 #endif 1651 1652 #ifndef EXCLUDE_NON_COMMON_INIT 1653 static void elink_set_mdio_emac_per_phy(struct elink_dev *cb, 1654 struct elink_params *params) 1655 { 1656 u8 phy_index; 1657 1658 /* Set mdio clock per phy */ 1659 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; 1660 phy_index++) 1661 elink_set_mdio_clk(cb, params->chip_id, 1662 params->phy[phy_index].mdio_ctrl); 1663 } 1664 1665 static void elink_emac_init(struct elink_params *params, 1666 struct elink_vars *vars) 1667 { 1668 /* reset and unreset the emac core */ 1669 struct elink_dev *cb = params->cb; 1670 u8 port = params->port; 1671 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1672 u32 val; 1673 u16 timeout; 1674 1675 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1676 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1677 USLEEP(cb, 5); 1678 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1679 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1680 1681 /* init emac - use read-modify-write */ 1682 /* self clear reset */ 1683 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE); 1684 EMAC_WR(cb, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); 1685 1686 timeout = 200; 1687 do { 1688 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE); 1689 ELINK_DEBUG_P1(cb, "EMAC reset reg is %u\n", val); 1690 if (!timeout) { 1691 ELINK_DEBUG_P0(cb, "EMAC timeout!\n"); 1692 return; 1693 } 1694 timeout--; 1695 } while (val & EMAC_MODE_RESET); 1696 1697 elink_set_mdio_emac_per_phy(cb, params); 1698 /* Set mac address */ 1699 val = ((params->mac_addr[0] << 8) | 1700 params->mac_addr[1]); 1701 EMAC_WR(cb, EMAC_REG_EMAC_MAC_MATCH, val); 1702 1703 val = ((params->mac_addr[2] << 24) | 1704 (params->mac_addr[3] << 16) | 1705 (params->mac_addr[4] << 8) | 1706 params->mac_addr[5]); 1707 EMAC_WR(cb, EMAC_REG_EMAC_MAC_MATCH + 4, val); 1708 } 1709 1710 #ifndef EXCLUDE_WARPCORE 1711 static void elink_set_xumac_nig(struct elink_params *params, 1712 u16 tx_pause_en, 1713 u8 enable) 1714 { 1715 struct elink_dev *cb = params->cb; 1716 1717 REG_WR(cb, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, 1718 enable); 1719 REG_WR(cb, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, 1720 enable); 1721 REG_WR(cb, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : 1722 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); 1723 } 1724 1725 static void elink_set_umac_rxtx(struct elink_params *params, u8 en) 1726 { 1727 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1728 u32 val; 1729 struct elink_dev *cb = params->cb; 1730 if (!(REG_RD(cb, MISC_REG_RESET_REG_2) & 1731 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) 1732 return; 1733 val = REG_RD(cb, umac_base + UMAC_REG_COMMAND_CONFIG); 1734 if (en) 1735 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA | 1736 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1737 else 1738 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA | 1739 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1740 /* Disable RX and TX */ 1741 REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1742 } 1743 1744 static void elink_umac_enable(struct elink_params *params, 1745 struct elink_vars *vars, u8 lb) 1746 { 1747 u32 val; 1748 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1749 struct elink_dev *cb = params->cb; 1750 /* Reset UMAC */ 1751 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1752 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1753 MSLEEP(cb, 1); 1754 1755 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1756 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1757 1758 ELINK_DEBUG_P0(cb, "enabling UMAC\n"); 1759 1760 /* This register opens the gate for the UMAC despite its name */ 1761 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 1762 1763 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | 1764 UMAC_COMMAND_CONFIG_REG_PAD_EN | 1765 UMAC_COMMAND_CONFIG_REG_SW_RESET | 1766 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; 1767 switch (vars->line_speed) { 1768 case ELINK_SPEED_10: 1769 val |= (0<<2); 1770 break; 1771 case ELINK_SPEED_100: 1772 val |= (1<<2); 1773 break; 1774 case ELINK_SPEED_1000: 1775 val |= (2<<2); 1776 break; 1777 case ELINK_SPEED_2500: 1778 val |= (3<<2); 1779 break; 1780 default: 1781 ELINK_DEBUG_P1(cb, "Invalid speed for UMAC %d\n", 1782 vars->line_speed); 1783 break; 1784 } 1785 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 1786 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; 1787 1788 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) 1789 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; 1790 1791 if (vars->duplex == DUPLEX_HALF) 1792 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; 1793 1794 REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1795 USLEEP(cb, 50); 1796 1797 /* Configure UMAC for EEE */ 1798 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1799 ELINK_DEBUG_P0(cb, "configured UMAC for EEE\n"); 1800 REG_WR(cb, umac_base + UMAC_REG_UMAC_EEE_CTRL, 1801 UMAC_UMAC_EEE_CTRL_REG_EEE_EN); 1802 REG_WR(cb, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); 1803 } else { 1804 REG_WR(cb, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); 1805 } 1806 1807 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ 1808 REG_WR(cb, umac_base + UMAC_REG_MAC_ADDR0, 1809 ((params->mac_addr[2] << 24) | 1810 (params->mac_addr[3] << 16) | 1811 (params->mac_addr[4] << 8) | 1812 (params->mac_addr[5]))); 1813 REG_WR(cb, umac_base + UMAC_REG_MAC_ADDR1, 1814 ((params->mac_addr[0] << 8) | 1815 (params->mac_addr[1]))); 1816 1817 /* Enable RX and TX */ 1818 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; 1819 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | 1820 UMAC_COMMAND_CONFIG_REG_RX_ENA; 1821 REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1822 USLEEP(cb, 50); 1823 1824 /* Remove SW Reset */ 1825 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; 1826 1827 /* Check loopback mode */ 1828 if (lb) 1829 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; 1830 REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1831 1832 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 1833 * length used by the MAC receive logic to check frames. 1834 */ 1835 REG_WR(cb, umac_base + UMAC_REG_MAXFR, 0x2710); 1836 elink_set_xumac_nig(params, 1837 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1); 1838 vars->mac_type = ELINK_MAC_TYPE_UMAC; 1839 1840 } 1841 1842 /* Define the XMAC mode */ 1843 static void elink_xmac_init(struct elink_params *params, u32 max_speed) 1844 { 1845 struct elink_dev *cb = params->cb; 1846 u32 is_port4mode = elink_is_4_port_mode(cb); 1847 1848 /* In 4-port mode, need to set the mode only once, so if XMAC is 1849 * already out of reset, it means the mode has already been set, 1850 * and it must not* reset the XMAC again, since it controls both 1851 * ports of the path 1852 */ 1853 1854 if (((CHIP_NUM(params->chip_id) == CHIP_NUM_57840_4_10) || 1855 (CHIP_NUM(params->chip_id) == CHIP_NUM_57840_2_20) || 1856 (CHIP_NUM(params->chip_id) == CHIP_NUM_57840_OBSOLETE)) && 1857 is_port4mode && 1858 (REG_RD(cb, MISC_REG_RESET_REG_2) & 1859 MISC_REGISTERS_RESET_REG_2_XMAC)) { 1860 ELINK_DEBUG_P0(cb, 1861 "XMAC already out of reset in 4-port mode\n"); 1862 return; 1863 } 1864 1865 /* Hard reset */ 1866 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1867 MISC_REGISTERS_RESET_REG_2_XMAC); 1868 MSLEEP(cb, 1); 1869 1870 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1871 MISC_REGISTERS_RESET_REG_2_XMAC); 1872 if (is_port4mode) { 1873 ELINK_DEBUG_P0(cb, "Init XMAC to 2 ports x 10G per path\n"); 1874 1875 /* Set the number of ports on the system side to up to 2 */ 1876 REG_WR(cb, MISC_REG_XMAC_CORE_PORT_MODE, 1); 1877 1878 /* Set the number of ports on the Warp Core to 10G */ 1879 REG_WR(cb, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1880 } else { 1881 /* Set the number of ports on the system side to 1 */ 1882 REG_WR(cb, MISC_REG_XMAC_CORE_PORT_MODE, 0); 1883 if (max_speed == ELINK_SPEED_10000) { 1884 ELINK_DEBUG_P0(cb, 1885 "Init XMAC to 10G x 1 port per path\n"); 1886 /* Set the number of ports on the Warp Core to 10G */ 1887 REG_WR(cb, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1888 } else { 1889 ELINK_DEBUG_P0(cb, 1890 "Init XMAC to 20G x 2 ports per path\n"); 1891 /* Set the number of ports on the Warp Core to 20G */ 1892 REG_WR(cb, MISC_REG_XMAC_PHY_PORT_MODE, 1); 1893 } 1894 } 1895 /* Soft reset */ 1896 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1897 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1898 MSLEEP(cb, 1); 1899 1900 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1901 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1902 1903 } 1904 1905 static void elink_set_xmac_rxtx(struct elink_params *params, u8 en) 1906 { 1907 u8 port = params->port; 1908 struct elink_dev *cb = params->cb; 1909 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1910 u32 val; 1911 1912 if (REG_RD(cb, MISC_REG_RESET_REG_2) & 1913 MISC_REGISTERS_RESET_REG_2_XMAC) { 1914 /* Send an indication to change the state in the NIG back to XON 1915 * Clearing this bit enables the next set of this bit to get 1916 * rising edge 1917 */ 1918 pfc_ctrl = REG_RD(cb, xmac_base + XMAC_REG_PFC_CTRL_HI); 1919 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI, 1920 (pfc_ctrl & ~(1<<1))); 1921 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI, 1922 (pfc_ctrl | (1<<1))); 1923 ELINK_DEBUG_P1(cb, "Disable XMAC on port %x\n", port); 1924 val = REG_RD(cb, xmac_base + XMAC_REG_CTRL); 1925 if (en) 1926 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1927 else 1928 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1929 REG_WR(cb, xmac_base + XMAC_REG_CTRL, val); 1930 } 1931 } 1932 1933 static elink_status_t elink_xmac_enable(struct elink_params *params, 1934 struct elink_vars *vars, u8 lb) 1935 { 1936 u32 val, xmac_base; 1937 struct elink_dev *cb = params->cb; 1938 ELINK_DEBUG_P0(cb, "enabling XMAC\n"); 1939 1940 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1941 1942 elink_xmac_init(params, vars->line_speed); 1943 1944 /* This register determines on which events the MAC will assert 1945 * error on the i/f to the NIG along w/ EOP. 1946 */ 1947 1948 /* This register tells the NIG whether to send traffic to UMAC 1949 * or XMAC 1950 */ 1951 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); 1952 1953 /* When XMAC is in XLGMII mode, disable sending idles for fault 1954 * detection. 1955 */ 1956 if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) { 1957 REG_WR(cb, xmac_base + XMAC_REG_RX_LSS_CTRL, 1958 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE | 1959 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE)); 1960 REG_WR(cb, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 1961 REG_WR(cb, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 1962 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 1963 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 1964 } 1965 /* Set Max packet size */ 1966 REG_WR(cb, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); 1967 1968 /* CRC append for Tx packets */ 1969 REG_WR(cb, xmac_base + XMAC_REG_TX_CTRL, 0xC800); 1970 1971 /* update PFC */ 1972 elink_update_pfc_xmac(params, vars, 0); 1973 1974 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1975 ELINK_DEBUG_P0(cb, "Setting XMAC for EEE\n"); 1976 REG_WR(cb, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); 1977 REG_WR(cb, xmac_base + XMAC_REG_EEE_CTRL, 0x1); 1978 } else { 1979 REG_WR(cb, xmac_base + XMAC_REG_EEE_CTRL, 0x0); 1980 } 1981 1982 /* Enable TX and RX */ 1983 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; 1984 1985 /* Set MAC in XLGMII mode for dual-mode */ 1986 if ((vars->line_speed == ELINK_SPEED_20000) && 1987 (params->phy[ELINK_INT_PHY].supported & 1988 ELINK_SUPPORTED_20000baseKR2_Full)) 1989 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB; 1990 1991 /* Check loopback mode */ 1992 if (lb) 1993 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; 1994 REG_WR(cb, xmac_base + XMAC_REG_CTRL, val); 1995 elink_set_xumac_nig(params, 1996 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1); 1997 1998 vars->mac_type = ELINK_MAC_TYPE_XMAC; 1999 2000 return ELINK_STATUS_OK; 2001 } 2002 #endif // EXCLUDE_WARPCORE 2003 2004 #ifndef EXCLUDE_EMAC 2005 static elink_status_t elink_emac_enable(struct elink_params *params, 2006 struct elink_vars *vars, u8 lb) 2007 { 2008 struct elink_dev *cb = params->cb; 2009 u8 port = params->port; 2010 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 2011 u32 val; 2012 2013 ELINK_DEBUG_P0(cb, "enabling EMAC\n"); 2014 2015 /* Disable BMAC */ 2016 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2017 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2018 2019 /* enable emac and not bmac */ 2020 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); 2021 2022 #ifdef ELINK_INCLUDE_EMUL 2023 /* for paladium */ 2024 if (CHIP_REV_IS_EMUL(params->chip_id)) { 2025 /* Use lane 1 (of lanes 0-3) */ 2026 REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1); 2027 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 2028 } 2029 /* for fpga */ 2030 else 2031 #endif 2032 #ifdef ELINK_INCLUDE_FPGA 2033 if (CHIP_REV_IS_FPGA(params->chip_id)) { 2034 /* Use lane 1 (of lanes 0-3) */ 2035 ELINK_DEBUG_P0(cb, "elink_emac_enable: Setting FPGA\n"); 2036 2037 REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1); 2038 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); 2039 } else 2040 #endif 2041 /* ASIC */ 2042 if (vars->phy_flags & PHY_XGXS_FLAG) { 2043 u32 ser_lane = ((params->lane_config & 2044 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 2045 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 2046 2047 ELINK_DEBUG_P0(cb, "XGXS\n"); 2048 /* select the master lanes (out of 0-3) */ 2049 REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); 2050 /* select XGXS */ 2051 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 2052 2053 } else { /* SerDes */ 2054 ELINK_DEBUG_P0(cb, "SerDes\n"); 2055 /* select SerDes */ 2056 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); 2057 } 2058 2059 elink_bits_en(cb, emac_base + EMAC_REG_EMAC_RX_MODE, 2060 EMAC_RX_MODE_RESET); 2061 elink_bits_en(cb, emac_base + EMAC_REG_EMAC_TX_MODE, 2062 EMAC_TX_MODE_RESET); 2063 2064 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) 2065 if (CHIP_REV_IS_SLOW(params->chip_id)) { 2066 /* config GMII mode */ 2067 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE); 2068 EMAC_WR(cb, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII)); 2069 } else { /* ASIC */ 2070 #endif /* defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)*/ 2071 /* pause enable/disable */ 2072 elink_bits_dis(cb, emac_base + EMAC_REG_EMAC_RX_MODE, 2073 EMAC_RX_MODE_FLOW_EN); 2074 2075 elink_bits_dis(cb, emac_base + EMAC_REG_EMAC_TX_MODE, 2076 (EMAC_TX_MODE_EXT_PAUSE_EN | 2077 EMAC_TX_MODE_FLOW_EN)); 2078 if (!(params->feature_config_flags & 2079 ELINK_FEATURE_CONFIG_PFC_ENABLED)) { 2080 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) 2081 elink_bits_en(cb, emac_base + 2082 EMAC_REG_EMAC_RX_MODE, 2083 EMAC_RX_MODE_FLOW_EN); 2084 2085 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) 2086 elink_bits_en(cb, emac_base + 2087 EMAC_REG_EMAC_TX_MODE, 2088 (EMAC_TX_MODE_EXT_PAUSE_EN | 2089 EMAC_TX_MODE_FLOW_EN)); 2090 } else 2091 elink_bits_en(cb, emac_base + EMAC_REG_EMAC_TX_MODE, 2092 EMAC_TX_MODE_FLOW_EN); 2093 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) 2094 } 2095 #endif /* defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) */ 2096 2097 /* KEEP_VLAN_TAG, promiscuous */ 2098 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_RX_MODE); 2099 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; 2100 2101 /* Setting this bit causes MAC control frames (except for pause 2102 * frames) to be passed on for processing. This setting has no 2103 * affect on the operation of the pause frames. This bit effects 2104 * all packets regardless of RX Parser packet sorting logic. 2105 * Turn the PFC off to make sure we are in Xon state before 2106 * enabling it. 2107 */ 2108 EMAC_WR(cb, EMAC_REG_RX_PFC_MODE, 0); 2109 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) { 2110 ELINK_DEBUG_P0(cb, "PFC is enabled\n"); 2111 /* Enable PFC again */ 2112 EMAC_WR(cb, EMAC_REG_RX_PFC_MODE, 2113 EMAC_REG_RX_PFC_MODE_RX_EN | 2114 EMAC_REG_RX_PFC_MODE_TX_EN | 2115 EMAC_REG_RX_PFC_MODE_PRIORITIES); 2116 2117 EMAC_WR(cb, EMAC_REG_RX_PFC_PARAM, 2118 ((0x0101 << 2119 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | 2120 (0x00ff << 2121 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); 2122 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; 2123 } 2124 EMAC_WR(cb, EMAC_REG_EMAC_RX_MODE, val); 2125 2126 /* Set Loopback */ 2127 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE); 2128 if (lb) 2129 val |= 0x810; 2130 else 2131 val &= ~0x810; 2132 EMAC_WR(cb, EMAC_REG_EMAC_MODE, val); 2133 2134 /* Enable emac */ 2135 REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 1); 2136 2137 #ifndef ELINK_AUX_POWER 2138 /* Enable emac for jumbo packets */ 2139 EMAC_WR(cb, EMAC_REG_EMAC_RX_MTU_SIZE, 2140 (EMAC_RX_MTU_SIZE_JUMBO_ENA | 2141 (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD))); 2142 #endif 2143 2144 /* Strip CRC */ 2145 REG_WR(cb, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); 2146 2147 /* Disable the NIG in/out to the bmac */ 2148 REG_WR(cb, NIG_REG_BMAC0_IN_EN + port*4, 0x0); 2149 REG_WR(cb, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); 2150 REG_WR(cb, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); 2151 2152 /* Enable the NIG in/out to the emac */ 2153 REG_WR(cb, NIG_REG_EMAC0_IN_EN + port*4, 0x1); 2154 val = 0; 2155 if ((params->feature_config_flags & 2156 ELINK_FEATURE_CONFIG_PFC_ENABLED) || 2157 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2158 val = 1; 2159 2160 REG_WR(cb, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); 2161 REG_WR(cb, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); 2162 2163 #ifdef ELINK_INCLUDE_EMUL 2164 if (CHIP_REV_IS_EMUL(params->chip_id)) { 2165 /* Take the BigMac out of reset */ 2166 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2167 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2168 2169 /* Enable access for bmac registers */ 2170 REG_WR(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 2171 } else 2172 #endif /* ELINK_INCLUDE_EMUL */ 2173 REG_WR(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); 2174 2175 vars->mac_type = ELINK_MAC_TYPE_EMAC; 2176 return ELINK_STATUS_OK; 2177 } 2178 2179 #endif //EXCLUDE_EMAC 2180 #ifndef EXCLUDE_BMAC1 2181 static void elink_update_pfc_bmac1(struct elink_params *params, 2182 struct elink_vars *vars) 2183 { 2184 u32 wb_data[2]; 2185 struct elink_dev *cb = params->cb; 2186 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 2187 NIG_REG_INGRESS_BMAC0_MEM; 2188 2189 u32 val = 0x14; 2190 if ((!(params->feature_config_flags & 2191 ELINK_FEATURE_CONFIG_PFC_ENABLED)) && 2192 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) 2193 /* Enable BigMAC to react on received Pause packets */ 2194 val |= (1<<5); 2195 wb_data[0] = val; 2196 wb_data[1] = 0; 2197 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); 2198 2199 /* TX control */ 2200 val = 0xc0; 2201 if (!(params->feature_config_flags & 2202 ELINK_FEATURE_CONFIG_PFC_ENABLED) && 2203 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2204 val |= 0x800000; 2205 wb_data[0] = val; 2206 wb_data[1] = 0; 2207 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); 2208 } 2209 #endif // EXCLUDE_BMAC1 2210 2211 #ifndef EXCLUDE_BMAC2 2212 static void elink_update_pfc_bmac2(struct elink_params *params, 2213 struct elink_vars *vars, 2214 u8 is_lb) 2215 { 2216 /* Set rx control: Strip CRC and enable BigMAC to relay 2217 * control packets to the system as well 2218 */ 2219 u32 wb_data[2]; 2220 struct elink_dev *cb = params->cb; 2221 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 2222 NIG_REG_INGRESS_BMAC0_MEM; 2223 u32 val = 0x14; 2224 2225 if ((!(params->feature_config_flags & 2226 ELINK_FEATURE_CONFIG_PFC_ENABLED)) && 2227 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) 2228 /* Enable BigMAC to react on received Pause packets */ 2229 val |= (1<<5); 2230 wb_data[0] = val; 2231 wb_data[1] = 0; 2232 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); 2233 USLEEP(cb, 30); 2234 2235 /* Tx control */ 2236 val = 0xc0; 2237 if (!(params->feature_config_flags & 2238 ELINK_FEATURE_CONFIG_PFC_ENABLED) && 2239 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2240 val |= 0x800000; 2241 wb_data[0] = val; 2242 wb_data[1] = 0; 2243 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); 2244 2245 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) { 2246 ELINK_DEBUG_P0(cb, "PFC is enabled\n"); 2247 /* Enable PFC RX & TX & STATS and set 8 COS */ 2248 wb_data[0] = 0x0; 2249 wb_data[0] |= (1<<0); /* RX */ 2250 wb_data[0] |= (1<<1); /* TX */ 2251 wb_data[0] |= (1<<2); /* Force initial Xon */ 2252 wb_data[0] |= (1<<3); /* 8 cos */ 2253 wb_data[0] |= (1<<5); /* STATS */ 2254 wb_data[1] = 0; 2255 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, 2256 wb_data, 2); 2257 /* Clear the force Xon */ 2258 wb_data[0] &= ~(1<<2); 2259 } else { 2260 ELINK_DEBUG_P0(cb, "PFC is disabled\n"); 2261 /* Disable PFC RX & TX & STATS and set 8 COS */ 2262 wb_data[0] = 0x8; 2263 wb_data[1] = 0; 2264 } 2265 2266 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); 2267 2268 /* Set Time (based unit is 512 bit time) between automatic 2269 * re-sending of PP packets amd enable automatic re-send of 2270 * Per-Priroity Packet as long as pp_gen is asserted and 2271 * pp_disable is low. 2272 */ 2273 val = 0x8000; 2274 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 2275 val |= (1<<16); /* enable automatic re-send */ 2276 2277 wb_data[0] = val; 2278 wb_data[1] = 0; 2279 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, 2280 wb_data, 2); 2281 2282 /* mac control */ 2283 val = 0x3; /* Enable RX and TX */ 2284 if (is_lb) { 2285 val |= 0x4; /* Local loopback */ 2286 ELINK_DEBUG_P0(cb, "enable bmac loopback\n"); 2287 } 2288 /* When PFC enabled, Pass pause frames towards the NIG. */ 2289 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 2290 val |= ((1<<6)|(1<<5)); 2291 2292 wb_data[0] = val; 2293 wb_data[1] = 0; 2294 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2295 } 2296 #endif // EXCLUDE_BMAC2 2297 #endif // EXCLUDE_NON_COMMON_INIT 2298 #ifdef ELINK_ENHANCEMENTS 2299 2300 /****************************************************************************** 2301 * Description: 2302 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 2303 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 2304 ******************************************************************************/ 2305 static elink_status_t elink_pfc_nig_rx_priority_mask(struct elink_dev *cb, 2306 u8 cos_entry, 2307 u32 priority_mask, u8 port) 2308 { 2309 u32 nig_reg_rx_priority_mask_add = 0; 2310 2311 switch (cos_entry) { 2312 case 0: 2313 nig_reg_rx_priority_mask_add = (port) ? 2314 NIG_REG_P1_RX_COS0_PRIORITY_MASK : 2315 NIG_REG_P0_RX_COS0_PRIORITY_MASK; 2316 break; 2317 case 1: 2318 nig_reg_rx_priority_mask_add = (port) ? 2319 NIG_REG_P1_RX_COS1_PRIORITY_MASK : 2320 NIG_REG_P0_RX_COS1_PRIORITY_MASK; 2321 break; 2322 case 2: 2323 nig_reg_rx_priority_mask_add = (port) ? 2324 NIG_REG_P1_RX_COS2_PRIORITY_MASK : 2325 NIG_REG_P0_RX_COS2_PRIORITY_MASK; 2326 break; 2327 case 3: 2328 if (port) 2329 return ELINK_STATUS_ERROR; 2330 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; 2331 break; 2332 case 4: 2333 if (port) 2334 return ELINK_STATUS_ERROR; 2335 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; 2336 break; 2337 case 5: 2338 if (port) 2339 return ELINK_STATUS_ERROR; 2340 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; 2341 break; 2342 } 2343 2344 REG_WR(cb, nig_reg_rx_priority_mask_add, priority_mask); 2345 2346 return ELINK_STATUS_OK; 2347 } 2348 #endif // ELINK_ENHANCEMENTS 2349 #ifndef EXCLUDE_NON_COMMON_INIT 2350 static void elink_update_mng(struct elink_params *params, u32 link_status) 2351 { 2352 struct elink_dev *cb = params->cb; 2353 2354 REG_WR(cb, params->shmem_base + 2355 OFFSETOF(struct shmem_region, 2356 port_mb[params->port].link_status), link_status); 2357 } 2358 2359 #ifdef ELINK_ENHANCEMENTS 2360 static void elink_update_pfc_nig(struct elink_params *params, 2361 struct elink_vars *vars, 2362 struct elink_nig_brb_pfc_port_params *nig_params) 2363 { 2364 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; 2365 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; 2366 u32 pkt_priority_to_cos = 0; 2367 struct elink_dev *cb = params->cb; 2368 u8 port = params->port; 2369 2370 int set_pfc = params->feature_config_flags & 2371 ELINK_FEATURE_CONFIG_PFC_ENABLED; 2372 ELINK_DEBUG_P0(cb, "updating pfc nig parameters\n"); 2373 2374 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set 2375 * MAC control frames (that are not pause packets) 2376 * will be forwarded to the XCM. 2377 */ 2378 xcm_mask = REG_RD(cb, port ? NIG_REG_LLH1_XCM_MASK : 2379 NIG_REG_LLH0_XCM_MASK); 2380 /* NIG params will override non PFC params, since it's possible to 2381 * do transition from PFC to SAFC 2382 */ 2383 if (set_pfc) { 2384 pause_enable = 0; 2385 llfc_out_en = 0; 2386 llfc_enable = 0; 2387 if (CHIP_IS_E3(params->chip_id)) 2388 ppp_enable = 0; 2389 else 2390 ppp_enable = 1; 2391 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2392 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2393 xcm_out_en = 0; 2394 hwpfc_enable = 1; 2395 } else { 2396 if (nig_params) { 2397 llfc_out_en = nig_params->llfc_out_en; 2398 llfc_enable = nig_params->llfc_enable; 2399 pause_enable = nig_params->pause_enable; 2400 } else /* Default non PFC mode - PAUSE */ 2401 pause_enable = 1; 2402 2403 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2404 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2405 xcm_out_en = 1; 2406 } 2407 2408 if (CHIP_IS_E3(params->chip_id)) 2409 REG_WR(cb, port ? NIG_REG_BRB1_PAUSE_IN_EN : 2410 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); 2411 REG_WR(cb, port ? NIG_REG_LLFC_OUT_EN_1 : 2412 NIG_REG_LLFC_OUT_EN_0, llfc_out_en); 2413 REG_WR(cb, port ? NIG_REG_LLFC_ENABLE_1 : 2414 NIG_REG_LLFC_ENABLE_0, llfc_enable); 2415 REG_WR(cb, port ? NIG_REG_PAUSE_ENABLE_1 : 2416 NIG_REG_PAUSE_ENABLE_0, pause_enable); 2417 2418 REG_WR(cb, port ? NIG_REG_PPP_ENABLE_1 : 2419 NIG_REG_PPP_ENABLE_0, ppp_enable); 2420 2421 REG_WR(cb, port ? NIG_REG_LLH1_XCM_MASK : 2422 NIG_REG_LLH0_XCM_MASK, xcm_mask); 2423 2424 REG_WR(cb, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : 2425 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); 2426 2427 /* Output enable for RX_XCM # IF */ 2428 REG_WR(cb, port ? NIG_REG_XCM1_OUT_EN : 2429 NIG_REG_XCM0_OUT_EN, xcm_out_en); 2430 2431 /* HW PFC TX enable */ 2432 REG_WR(cb, port ? NIG_REG_P1_HWPFC_ENABLE : 2433 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); 2434 2435 if (nig_params) { 2436 u8 i = 0; 2437 pkt_priority_to_cos = nig_params->pkt_priority_to_cos; 2438 2439 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) 2440 elink_pfc_nig_rx_priority_mask(cb, i, 2441 nig_params->rx_cos_priority_mask[i], port); 2442 2443 REG_WR(cb, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : 2444 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, 2445 nig_params->llfc_high_priority_classes); 2446 2447 REG_WR(cb, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : 2448 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, 2449 nig_params->llfc_low_priority_classes); 2450 } 2451 REG_WR(cb, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : 2452 NIG_REG_P0_PKT_PRIORITY_TO_COS, 2453 pkt_priority_to_cos); 2454 } 2455 2456 elink_status_t elink_update_pfc(struct elink_params *params, 2457 struct elink_vars *vars, 2458 struct elink_nig_brb_pfc_port_params *pfc_params) 2459 { 2460 /* The PFC and pause are orthogonal to one another, meaning when 2461 * PFC is enabled, the pause are disabled, and when PFC is 2462 * disabled, pause are set according to the pause result. 2463 */ 2464 u32 val; 2465 struct elink_dev *cb = params->cb; 2466 u8 bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC); 2467 2468 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 2469 vars->link_status |= LINK_STATUS_PFC_ENABLED; 2470 else 2471 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 2472 2473 elink_update_mng(params, vars->link_status); 2474 2475 /* Update NIG params */ 2476 elink_update_pfc_nig(params, vars, pfc_params); 2477 2478 if (!vars->link_up) 2479 return ELINK_STATUS_OK; 2480 2481 ELINK_DEBUG_P0(cb, "About to update PFC in BMAC\n"); 2482 2483 if (CHIP_IS_E3(params->chip_id)) { 2484 if (vars->mac_type == ELINK_MAC_TYPE_XMAC) 2485 elink_update_pfc_xmac(params, vars, 0); 2486 } else { 2487 val = REG_RD(cb, MISC_REG_RESET_REG_2); 2488 if ((val & 2489 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) 2490 == 0) { 2491 ELINK_DEBUG_P0(cb, "About to update PFC in EMAC\n"); 2492 elink_emac_enable(params, vars, 0); 2493 return ELINK_STATUS_OK; 2494 } 2495 if (CHIP_IS_E2(params->chip_id)) 2496 elink_update_pfc_bmac2(params, vars, bmac_loopback); 2497 else 2498 elink_update_pfc_bmac1(params, vars); 2499 2500 val = 0; 2501 if ((params->feature_config_flags & 2502 ELINK_FEATURE_CONFIG_PFC_ENABLED) || 2503 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2504 val = 1; 2505 REG_WR(cb, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); 2506 } 2507 return ELINK_STATUS_OK; 2508 } 2509 2510 #endif /* ELINK_ENHANCEMENTS */ 2511 #ifndef EXCLUDE_BMAC1 2512 static elink_status_t elink_bmac1_enable(struct elink_params *params, 2513 struct elink_vars *vars, 2514 u8 is_lb) 2515 { 2516 struct elink_dev *cb = params->cb; 2517 u8 port = params->port; 2518 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2519 NIG_REG_INGRESS_BMAC0_MEM; 2520 u32 wb_data[2]; 2521 u32 val; 2522 2523 ELINK_DEBUG_P0(cb, "Enabling BigMAC1\n"); 2524 2525 /* XGXS control */ 2526 wb_data[0] = 0x3c; 2527 wb_data[1] = 0; 2528 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, 2529 wb_data, 2); 2530 2531 /* TX MAC SA */ 2532 wb_data[0] = ((params->mac_addr[2] << 24) | 2533 (params->mac_addr[3] << 16) | 2534 (params->mac_addr[4] << 8) | 2535 params->mac_addr[5]); 2536 wb_data[1] = ((params->mac_addr[0] << 8) | 2537 params->mac_addr[1]); 2538 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); 2539 2540 /* MAC control */ 2541 val = 0x3; 2542 if (is_lb) { 2543 val |= 0x4; 2544 ELINK_DEBUG_P0(cb, "enable bmac loopback\n"); 2545 } 2546 wb_data[0] = val; 2547 wb_data[1] = 0; 2548 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); 2549 2550 /* Set rx mtu */ 2551 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 2552 wb_data[1] = 0; 2553 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); 2554 2555 elink_update_pfc_bmac1(params, vars); 2556 2557 /* Set tx mtu */ 2558 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 2559 wb_data[1] = 0; 2560 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); 2561 2562 /* Set cnt max size */ 2563 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 2564 wb_data[1] = 0; 2565 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2566 2567 /* Configure SAFC */ 2568 wb_data[0] = 0x1000200; 2569 wb_data[1] = 0; 2570 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, 2571 wb_data, 2); 2572 #ifdef ELINK_INCLUDE_EMUL 2573 /* Fix for emulation */ 2574 if (CHIP_REV_IS_EMUL(params->chip_id)) { 2575 wb_data[0] = 0xf000; 2576 wb_data[1] = 0; 2577 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD, 2578 wb_data, 2); 2579 } 2580 #endif /* ELINK_INCLUDE_EMUL */ 2581 2582 return ELINK_STATUS_OK; 2583 } 2584 #endif /* EXCLUDE_BMAC1 */ 2585 2586 #ifndef EXCLUDE_BMAC2 2587 static elink_status_t elink_bmac2_enable(struct elink_params *params, 2588 struct elink_vars *vars, 2589 u8 is_lb) 2590 { 2591 struct elink_dev *cb = params->cb; 2592 u8 port = params->port; 2593 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2594 NIG_REG_INGRESS_BMAC0_MEM; 2595 u32 wb_data[2]; 2596 2597 ELINK_DEBUG_P0(cb, "Enabling BigMAC2\n"); 2598 2599 wb_data[0] = 0; 2600 wb_data[1] = 0; 2601 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2602 USLEEP(cb, 30); 2603 2604 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ 2605 wb_data[0] = 0x3c; 2606 wb_data[1] = 0; 2607 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, 2608 wb_data, 2); 2609 2610 USLEEP(cb, 30); 2611 2612 /* TX MAC SA */ 2613 wb_data[0] = ((params->mac_addr[2] << 24) | 2614 (params->mac_addr[3] << 16) | 2615 (params->mac_addr[4] << 8) | 2616 params->mac_addr[5]); 2617 wb_data[1] = ((params->mac_addr[0] << 8) | 2618 params->mac_addr[1]); 2619 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, 2620 wb_data, 2); 2621 2622 USLEEP(cb, 30); 2623 2624 /* Configure SAFC */ 2625 wb_data[0] = 0x1000200; 2626 wb_data[1] = 0; 2627 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, 2628 wb_data, 2); 2629 USLEEP(cb, 30); 2630 2631 /* Set RX MTU */ 2632 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 2633 wb_data[1] = 0; 2634 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); 2635 USLEEP(cb, 30); 2636 2637 /* Set TX MTU */ 2638 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 2639 wb_data[1] = 0; 2640 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); 2641 USLEEP(cb, 30); 2642 /* Set cnt max size */ 2643 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2; 2644 wb_data[1] = 0; 2645 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2646 USLEEP(cb, 30); 2647 elink_update_pfc_bmac2(params, vars, is_lb); 2648 2649 return ELINK_STATUS_OK; 2650 } 2651 #endif /* EXCLUDE_BMAC2 */ 2652 2653 #if !defined(EXCLUDE_BMAC2) 2654 static elink_status_t elink_bmac_enable(struct elink_params *params, 2655 struct elink_vars *vars, 2656 u8 is_lb, u8 reset_bmac) 2657 { 2658 elink_status_t rc = ELINK_STATUS_OK; 2659 u8 port = params->port; 2660 struct elink_dev *cb = params->cb; 2661 u32 val; 2662 /* Reset and unreset the BigMac */ 2663 if (reset_bmac) { 2664 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2665 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2666 MSLEEP(cb, 1); 2667 } 2668 2669 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2670 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2671 2672 /* Enable access for bmac registers */ 2673 REG_WR(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 2674 2675 /* Enable BMAC according to BMAC type*/ 2676 #ifdef ELINK_ENHANCEMENTS 2677 if (CHIP_IS_E2(params->chip_id)) 2678 #endif 2679 #ifndef EXCLUDE_BMAC2 2680 rc = elink_bmac2_enable(params, vars, is_lb); 2681 #endif 2682 #ifdef ELINK_ENHANCEMENTS 2683 else 2684 #endif 2685 #ifndef EXCLUDE_BMAC1 2686 rc = elink_bmac1_enable(params, vars, is_lb); 2687 #endif 2688 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); 2689 REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); 2690 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); 2691 val = 0; 2692 if ((params->feature_config_flags & 2693 ELINK_FEATURE_CONFIG_PFC_ENABLED) || 2694 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2695 val = 1; 2696 REG_WR(cb, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); 2697 REG_WR(cb, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); 2698 REG_WR(cb, NIG_REG_EMAC0_IN_EN + port*4, 0x0); 2699 REG_WR(cb, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); 2700 REG_WR(cb, NIG_REG_BMAC0_IN_EN + port*4, 0x1); 2701 REG_WR(cb, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); 2702 2703 vars->mac_type = ELINK_MAC_TYPE_BMAC; 2704 return rc; 2705 } 2706 #endif /* #if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) */ 2707 2708 #if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) 2709 static void elink_set_bmac_rx(struct elink_dev *cb, u32 chip_id, u8 port, u8 en) 2710 { 2711 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2712 NIG_REG_INGRESS_BMAC0_MEM; 2713 u32 wb_data[2]; 2714 u32 nig_bmac_enable = REG_RD(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4); 2715 2716 if (CHIP_IS_E2(chip_id)) 2717 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL; 2718 else 2719 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL; 2720 /* Only if the bmac is out of reset */ 2721 if (REG_RD(cb, MISC_REG_RESET_REG_2) & 2722 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && 2723 nig_bmac_enable) { 2724 /* Clear Rx Enable bit in BMAC_CONTROL register */ 2725 REG_RD_DMAE(cb, bmac_addr, wb_data, 2); 2726 if (en) 2727 wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE; 2728 else 2729 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE; 2730 REG_WR_DMAE(cb, bmac_addr, wb_data, 2); 2731 MSLEEP(cb, 1); 2732 } 2733 } 2734 #endif /* !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) */ 2735 #endif // EXCLUDE_NON_COMMON_INIT 2736 2737 #ifndef ELINK_AUX_POWER 2738 static elink_status_t elink_pbf_update(struct elink_params *params, u32 flow_ctrl, 2739 u32 line_speed) 2740 { 2741 struct elink_dev *cb = params->cb; 2742 u8 port = params->port; 2743 u32 init_crd, crd; 2744 u32 count = 1000; 2745 2746 /* Disable port */ 2747 REG_WR(cb, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); 2748 2749 /* Wait for init credit */ 2750 init_crd = REG_RD(cb, PBF_REG_P0_INIT_CRD + port*4); 2751 crd = REG_RD(cb, PBF_REG_P0_CREDIT + port*8); 2752 ELINK_DEBUG_P2(cb, "init_crd 0x%x crd 0x%x\n", init_crd, crd); 2753 2754 while ((init_crd != crd) && count) { 2755 MSLEEP(cb, 5); 2756 crd = REG_RD(cb, PBF_REG_P0_CREDIT + port*8); 2757 count--; 2758 } 2759 crd = REG_RD(cb, PBF_REG_P0_CREDIT + port*8); 2760 if (init_crd != crd) { 2761 ELINK_DEBUG_P2(cb, "BUG! init_crd 0x%x != crd 0x%x\n", 2762 init_crd, crd); 2763 return ELINK_STATUS_ERROR; 2764 } 2765 2766 if (flow_ctrl & ELINK_FLOW_CTRL_RX || 2767 line_speed == ELINK_SPEED_10 || 2768 line_speed == ELINK_SPEED_100 || 2769 line_speed == ELINK_SPEED_1000 || 2770 line_speed == ELINK_SPEED_2500) { 2771 REG_WR(cb, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); 2772 /* Update threshold */ 2773 REG_WR(cb, PBF_REG_P0_ARB_THRSH + port*4, 0); 2774 /* Update init credit */ 2775 init_crd = 778; /* (800-18-4) */ 2776 2777 } else { 2778 u32 thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + 2779 ELINK_ETH_OVREHEAD)/16; 2780 REG_WR(cb, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 2781 /* Update threshold */ 2782 REG_WR(cb, PBF_REG_P0_ARB_THRSH + port*4, thresh); 2783 /* Update init credit */ 2784 switch (line_speed) { 2785 case ELINK_SPEED_10000: 2786 init_crd = thresh + 553 - 22; 2787 break; 2788 default: 2789 ELINK_DEBUG_P1(cb, "Invalid line_speed 0x%x\n", 2790 line_speed); 2791 return ELINK_STATUS_ERROR; 2792 } 2793 } 2794 REG_WR(cb, PBF_REG_P0_INIT_CRD + port*4, init_crd); 2795 ELINK_DEBUG_P2(cb, "PBF updated to speed %d credit %d\n", 2796 line_speed, init_crd); 2797 2798 /* Probe the credit changes */ 2799 REG_WR(cb, PBF_REG_INIT_P0 + port*4, 0x1); 2800 MSLEEP(cb, 5); 2801 REG_WR(cb, PBF_REG_INIT_P0 + port*4, 0x0); 2802 2803 /* Enable port */ 2804 REG_WR(cb, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); 2805 return ELINK_STATUS_OK; 2806 } 2807 #endif /* ELINK_AUX_POWER */ 2808 2809 #ifndef EXCLUDE_COMMON_INIT 2810 /** 2811 * elink_get_emac_base - retrive emac base address 2812 * 2813 * @bp: driver handle 2814 * @mdc_mdio_access: access type 2815 * @port: port id 2816 * 2817 * This function selects the MDC/MDIO access (through emac0 or 2818 * emac1) depend on the mdc_mdio_access, port, port swapped. Each 2819 * phy has a default access mode, which could also be overridden 2820 * by nvram configuration. This parameter, whether this is the 2821 * default phy configuration, or the nvram overrun 2822 * configuration, is passed here as mdc_mdio_access and selects 2823 * the emac_base for the CL45 read/writes operations 2824 */ 2825 static u32 elink_get_emac_base(struct elink_dev *cb, 2826 u32 mdc_mdio_access, u8 port) 2827 { 2828 u32 emac_base = 0; 2829 switch (mdc_mdio_access) { 2830 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: 2831 break; 2832 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: 2833 if (REG_RD(cb, NIG_REG_PORT_SWAP)) 2834 emac_base = GRCBASE_EMAC1; 2835 else 2836 emac_base = GRCBASE_EMAC0; 2837 break; 2838 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: 2839 if (REG_RD(cb, NIG_REG_PORT_SWAP)) 2840 emac_base = GRCBASE_EMAC0; 2841 else 2842 emac_base = GRCBASE_EMAC1; 2843 break; 2844 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: 2845 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 2846 break; 2847 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: 2848 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; 2849 break; 2850 default: 2851 break; 2852 } 2853 return emac_base; 2854 2855 } 2856 #endif /* EXCLUDE_COMMON_INIT */ 2857 2858 /******************************************************************/ 2859 /* CL22 access functions */ 2860 /******************************************************************/ 2861 #ifndef EXCLUDE_NON_COMMON_INIT 2862 #ifndef EXCLUDE_BCM54618SE 2863 static elink_status_t elink_cl22_write(struct elink_dev *cb, 2864 struct elink_phy *phy, 2865 u16 reg, u16 val) 2866 { 2867 u32 tmp, mode; 2868 u8 i; 2869 elink_status_t rc = ELINK_STATUS_OK; 2870 /* Switch to CL22 */ 2871 mode = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2872 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2873 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2874 2875 /* Address */ 2876 tmp = ((phy->addr << 21) | (reg << 16) | val | 2877 EMAC_MDIO_COMM_COMMAND_WRITE_22 | 2878 EMAC_MDIO_COMM_START_BUSY); 2879 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2880 2881 for (i = 0; i < 50; i++) { 2882 USLEEP(cb, 10); 2883 2884 tmp = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2885 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2886 USLEEP(cb, 5); 2887 break; 2888 } 2889 } 2890 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2891 ELINK_DEBUG_P0(cb, "write phy register failed\n"); 2892 rc = ELINK_STATUS_TIMEOUT; 2893 } 2894 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2895 return rc; 2896 } 2897 2898 static elink_status_t elink_cl22_read(struct elink_dev *cb, 2899 struct elink_phy *phy, 2900 u16 reg, u16 *ret_val) 2901 { 2902 u32 val, mode; 2903 u16 i; 2904 elink_status_t rc = ELINK_STATUS_OK; 2905 2906 /* Switch to CL22 */ 2907 mode = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2908 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2909 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2910 2911 /* Address */ 2912 val = ((phy->addr << 21) | (reg << 16) | 2913 EMAC_MDIO_COMM_COMMAND_READ_22 | 2914 EMAC_MDIO_COMM_START_BUSY); 2915 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2916 2917 for (i = 0; i < 50; i++) { 2918 USLEEP(cb, 10); 2919 2920 val = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2921 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2922 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2923 USLEEP(cb, 5); 2924 break; 2925 } 2926 } 2927 if (val & EMAC_MDIO_COMM_START_BUSY) { 2928 ELINK_DEBUG_P0(cb, "read phy register failed\n"); 2929 2930 *ret_val = 0; 2931 rc = ELINK_STATUS_TIMEOUT; 2932 } 2933 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2934 return rc; 2935 } 2936 #endif 2937 #endif /* EXCLUDE_NON_COMMON_INIT */ 2938 2939 /******************************************************************/ 2940 /* CL45 access functions */ 2941 /******************************************************************/ 2942 static elink_status_t elink_cl45_read(struct elink_dev *cb, struct elink_phy *phy, 2943 u8 devad, u16 reg, u16 *ret_val) 2944 { 2945 u32 val; 2946 u16 i; 2947 elink_status_t rc = ELINK_STATUS_OK; 2948 #ifndef ELINK_AUX_POWER 2949 u32 chip_id; 2950 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) { 2951 chip_id = (REG_RD(cb, MISC_REG_CHIP_NUM) << 16) | 2952 ((REG_RD(cb, MISC_REG_CHIP_REV) & 0xf) << 12); 2953 elink_set_mdio_clk(cb, chip_id, phy->mdio_ctrl); 2954 } 2955 #endif /* ELINK_AUX_POWER */ 2956 2957 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) 2958 elink_bits_en(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2959 EMAC_MDIO_STATUS_10MB); 2960 /* Address */ 2961 val = ((phy->addr << 21) | (devad << 16) | reg | 2962 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2963 EMAC_MDIO_COMM_START_BUSY); 2964 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2965 2966 for (i = 0; i < 50; i++) { 2967 USLEEP(cb, 10); 2968 2969 val = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2970 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2971 USLEEP(cb, 5); 2972 break; 2973 } 2974 } 2975 if (val & EMAC_MDIO_COMM_START_BUSY) { 2976 ELINK_DEBUG_P0(cb, "read phy register failed\n"); 2977 elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n" 2978 2979 *ret_val = 0; 2980 rc = ELINK_STATUS_TIMEOUT; 2981 } else { 2982 /* Data */ 2983 val = ((phy->addr << 21) | (devad << 16) | 2984 EMAC_MDIO_COMM_COMMAND_READ_45 | 2985 EMAC_MDIO_COMM_START_BUSY); 2986 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2987 2988 for (i = 0; i < 50; i++) { 2989 USLEEP(cb, 10); 2990 2991 val = REG_RD(cb, phy->mdio_ctrl + 2992 EMAC_REG_EMAC_MDIO_COMM); 2993 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2994 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2995 break; 2996 } 2997 } 2998 if (val & EMAC_MDIO_COMM_START_BUSY) { 2999 ELINK_DEBUG_P0(cb, "read phy register failed\n"); 3000 elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n" 3001 3002 *ret_val = 0; 3003 rc = ELINK_STATUS_TIMEOUT; 3004 } 3005 } 3006 /* Work around for E3 A0 */ 3007 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) { 3008 phy->flags ^= ELINK_FLAGS_DUMMY_READ; 3009 if (phy->flags & ELINK_FLAGS_DUMMY_READ) { 3010 u16 temp_val; 3011 elink_cl45_read(cb, phy, devad, 0xf, &temp_val); 3012 } 3013 } 3014 3015 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) 3016 elink_bits_dis(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 3017 EMAC_MDIO_STATUS_10MB); 3018 return rc; 3019 } 3020 3021 static elink_status_t elink_cl45_write(struct elink_dev *cb, struct elink_phy *phy, 3022 u8 devad, u16 reg, u16 val) 3023 { 3024 u32 tmp; 3025 u8 i; 3026 elink_status_t rc = ELINK_STATUS_OK; 3027 #ifndef ELINK_AUX_POWER 3028 u32 chip_id; 3029 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) { 3030 chip_id = (REG_RD(cb, MISC_REG_CHIP_NUM) << 16) | 3031 ((REG_RD(cb, MISC_REG_CHIP_REV) & 0xf) << 12); 3032 elink_set_mdio_clk(cb, chip_id, phy->mdio_ctrl); 3033 } 3034 #endif /* ELINK_AUX_POWER */ 3035 3036 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) 3037 elink_bits_en(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 3038 EMAC_MDIO_STATUS_10MB); 3039 3040 /* Address */ 3041 tmp = ((phy->addr << 21) | (devad << 16) | reg | 3042 EMAC_MDIO_COMM_COMMAND_ADDRESS | 3043 EMAC_MDIO_COMM_START_BUSY); 3044 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 3045 3046 for (i = 0; i < 50; i++) { 3047 USLEEP(cb, 10); 3048 3049 tmp = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 3050 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 3051 USLEEP(cb, 5); 3052 break; 3053 } 3054 } 3055 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 3056 ELINK_DEBUG_P0(cb, "write phy register failed\n"); 3057 elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n" 3058 3059 rc = ELINK_STATUS_TIMEOUT; 3060 } else { 3061 /* Data */ 3062 tmp = ((phy->addr << 21) | (devad << 16) | val | 3063 EMAC_MDIO_COMM_COMMAND_WRITE_45 | 3064 EMAC_MDIO_COMM_START_BUSY); 3065 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 3066 3067 for (i = 0; i < 50; i++) { 3068 USLEEP(cb, 10); 3069 3070 tmp = REG_RD(cb, phy->mdio_ctrl + 3071 EMAC_REG_EMAC_MDIO_COMM); 3072 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 3073 USLEEP(cb, 5); 3074 break; 3075 } 3076 } 3077 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 3078 ELINK_DEBUG_P0(cb, "write phy register failed\n"); 3079 elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n" 3080 3081 rc = ELINK_STATUS_TIMEOUT; 3082 } 3083 } 3084 /* Work around for E3 A0 */ 3085 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) { 3086 phy->flags ^= ELINK_FLAGS_DUMMY_READ; 3087 if (phy->flags & ELINK_FLAGS_DUMMY_READ) { 3088 u16 temp_val; 3089 elink_cl45_read(cb, phy, devad, 0xf, &temp_val); 3090 } 3091 } 3092 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) 3093 elink_bits_dis(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 3094 EMAC_MDIO_STATUS_10MB); 3095 return rc; 3096 } 3097 3098 /******************************************************************/ 3099 /* EEE section */ 3100 /******************************************************************/ 3101 #ifndef EXCLUDE_NON_COMMON_INIT 3102 #ifndef EXCLUDE_WARPCORE 3103 static u8 elink_eee_has_cap(struct elink_params *params) 3104 { 3105 struct elink_dev *cb = params->cb; 3106 3107 if (REG_RD(cb, params->shmem2_base) <= 3108 OFFSETOF(struct shmem2_region, eee_status[params->port])) 3109 return 0; 3110 3111 return 1; 3112 } 3113 3114 static elink_status_t elink_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer) 3115 { 3116 switch (nvram_mode) { 3117 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: 3118 *idle_timer = ELINK_EEE_MODE_NVRAM_BALANCED_TIME; 3119 break; 3120 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: 3121 *idle_timer = ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME; 3122 break; 3123 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: 3124 *idle_timer = ELINK_EEE_MODE_NVRAM_LATENCY_TIME; 3125 break; 3126 default: 3127 *idle_timer = 0; 3128 break; 3129 } 3130 3131 return ELINK_STATUS_OK; 3132 } 3133 3134 static elink_status_t elink_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode) 3135 { 3136 switch (idle_timer) { 3137 case ELINK_EEE_MODE_NVRAM_BALANCED_TIME: 3138 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; 3139 break; 3140 case ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME: 3141 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; 3142 break; 3143 case ELINK_EEE_MODE_NVRAM_LATENCY_TIME: 3144 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; 3145 break; 3146 default: 3147 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; 3148 break; 3149 } 3150 3151 return ELINK_STATUS_OK; 3152 } 3153 3154 static u32 elink_eee_calc_timer(struct elink_params *params) 3155 { 3156 u32 eee_mode, eee_idle; 3157 struct elink_dev *cb = params->cb; 3158 3159 if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) { 3160 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) { 3161 /* time value in eee_mode --> used directly*/ 3162 eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK; 3163 } else { 3164 /* hsi value in eee_mode --> time */ 3165 if (elink_eee_nvram_to_time(params->eee_mode & 3166 ELINK_EEE_MODE_NVRAM_MASK, 3167 &eee_idle)) 3168 return 0; 3169 } 3170 } else { 3171 /* hsi values in nvram --> time*/ 3172 eee_mode = ((REG_RD(cb, params->shmem_base + 3173 OFFSETOF(struct shmem_region, dev_info. 3174 port_feature_config[params->port]. 3175 eee_power_mode)) & 3176 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 3177 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 3178 3179 if (elink_eee_nvram_to_time(eee_mode, &eee_idle)) 3180 return 0; 3181 } 3182 3183 return eee_idle; 3184 } 3185 3186 static elink_status_t elink_eee_set_timers(struct elink_params *params, 3187 struct elink_vars *vars) 3188 { 3189 u32 eee_idle = 0, eee_mode; 3190 struct elink_dev *cb = params->cb; 3191 3192 eee_idle = elink_eee_calc_timer(params); 3193 3194 if (eee_idle) { 3195 REG_WR(cb, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), 3196 eee_idle); 3197 } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) && 3198 (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) && 3199 (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) { 3200 ELINK_DEBUG_P0(cb, "Error: Tx LPI is enabled with timer 0\n"); 3201 return ELINK_STATUS_ERROR; 3202 } 3203 3204 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); 3205 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) { 3206 /* eee_idle in 1u --> eee_status in 16u */ 3207 eee_idle >>= 4; 3208 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | 3209 SHMEM_EEE_TIME_OUTPUT_BIT; 3210 } else { 3211 if (elink_eee_time_to_nvram(eee_idle, &eee_mode)) 3212 return ELINK_STATUS_ERROR; 3213 vars->eee_status |= eee_mode; 3214 } 3215 3216 return ELINK_STATUS_OK; 3217 } 3218 3219 static elink_status_t elink_eee_initial_config(struct elink_params *params, 3220 struct elink_vars *vars, u8 mode) 3221 { 3222 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT; 3223 3224 /* Propogate params' bits --> vars (for migration exposure) */ 3225 if (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) 3226 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; 3227 else 3228 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; 3229 3230 if (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) 3231 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; 3232 else 3233 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; 3234 3235 return elink_eee_set_timers(params, vars); 3236 } 3237 3238 static elink_status_t elink_eee_disable(struct elink_phy *phy, 3239 struct elink_params *params, 3240 struct elink_vars *vars) 3241 { 3242 struct elink_dev *cb = params->cb; 3243 3244 /* Make Certain LPI is disabled */ 3245 REG_WR(cb, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); 3246 3247 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); 3248 3249 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 3250 3251 return ELINK_STATUS_OK; 3252 } 3253 3254 static elink_status_t elink_eee_advertise(struct elink_phy *phy, 3255 struct elink_params *params, 3256 struct elink_vars *vars, u8 modes) 3257 { 3258 struct elink_dev *cb = params->cb; 3259 u16 val = 0; 3260 3261 /* Mask events preventing LPI generation */ 3262 REG_WR(cb, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); 3263 3264 if (modes & SHMEM_EEE_10G_ADV) { 3265 ELINK_DEBUG_P0(cb, "Advertise 10GBase-T EEE\n"); 3266 val |= 0x8; 3267 } 3268 if (modes & SHMEM_EEE_1G_ADV) { 3269 ELINK_DEBUG_P0(cb, "Advertise 1GBase-T EEE\n"); 3270 val |= 0x4; 3271 } 3272 3273 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); 3274 3275 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 3276 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); 3277 3278 return ELINK_STATUS_OK; 3279 } 3280 3281 static void elink_update_mng_eee(struct elink_params *params, u32 eee_status) 3282 { 3283 struct elink_dev *cb = params->cb; 3284 3285 if (elink_eee_has_cap(params)) 3286 REG_WR(cb, params->shmem2_base + 3287 OFFSETOF(struct shmem2_region, 3288 eee_status[params->port]), eee_status); 3289 } 3290 3291 static void elink_eee_an_resolve(struct elink_phy *phy, 3292 struct elink_params *params, 3293 struct elink_vars *vars) 3294 { 3295 struct elink_dev *cb = params->cb; 3296 u16 adv = 0, lp = 0; 3297 u32 lp_adv = 0; 3298 u8 neg = 0; 3299 3300 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); 3301 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); 3302 3303 if (lp & 0x2) { 3304 lp_adv |= SHMEM_EEE_100M_ADV; 3305 if (adv & 0x2) { 3306 if (vars->line_speed == ELINK_SPEED_100) 3307 neg = 1; 3308 ELINK_DEBUG_P0(cb, "EEE negotiated - 100M\n"); 3309 } 3310 } 3311 if (lp & 0x14) { 3312 lp_adv |= SHMEM_EEE_1G_ADV; 3313 if (adv & 0x14) { 3314 if (vars->line_speed == ELINK_SPEED_1000) 3315 neg = 1; 3316 ELINK_DEBUG_P0(cb, "EEE negotiated - 1G\n"); 3317 } 3318 } 3319 if (lp & 0x68) { 3320 lp_adv |= SHMEM_EEE_10G_ADV; 3321 if (adv & 0x68) { 3322 if (vars->line_speed == ELINK_SPEED_10000) 3323 neg = 1; 3324 ELINK_DEBUG_P0(cb, "EEE negotiated - 10G\n"); 3325 } 3326 } 3327 3328 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; 3329 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); 3330 3331 if (neg) { 3332 ELINK_DEBUG_P0(cb, "EEE is active\n"); 3333 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; 3334 } 3335 } 3336 3337 /******************************************************************/ 3338 /* BSC access functions from E3 */ 3339 /******************************************************************/ 3340 static void elink_bsc_module_sel(struct elink_params *params) 3341 { 3342 int idx; 3343 u32 board_cfg, sfp_ctrl; 3344 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; 3345 struct elink_dev *cb = params->cb; 3346 u8 port = params->port; 3347 /* Read I2C output PINs */ 3348 board_cfg = REG_RD(cb, params->shmem_base + 3349 OFFSETOF(struct shmem_region, 3350 dev_info.shared_hw_config.board)); 3351 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; 3352 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> 3353 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; 3354 3355 /* Read I2C output value */ 3356 sfp_ctrl = REG_RD(cb, params->shmem_base + 3357 OFFSETOF(struct shmem_region, 3358 dev_info.port_hw_config[port].e3_cmn_pin_cfg)); 3359 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; 3360 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; 3361 ELINK_DEBUG_P0(cb, "Setting BSC switch\n"); 3362 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) 3363 elink_set_cfg_pin(cb, i2c_pins[idx], i2c_val[idx]); 3364 } 3365 3366 static elink_status_t elink_bsc_read(struct elink_params *params, 3367 struct elink_dev *cb, 3368 u8 sl_devid, 3369 u16 sl_addr, 3370 u8 lc_addr, 3371 u8 xfer_cnt, 3372 u32 *data_array) 3373 { 3374 u32 val, i; 3375 elink_status_t rc = ELINK_STATUS_OK; 3376 3377 if (xfer_cnt > 16) { 3378 ELINK_DEBUG_P1(cb, "invalid xfer_cnt %d. Max is 16 bytes\n", 3379 xfer_cnt); 3380 return ELINK_STATUS_ERROR; 3381 } 3382 if (params) 3383 elink_bsc_module_sel(params); 3384 3385 xfer_cnt = 16 - lc_addr; 3386 3387 /* Enable the engine */ 3388 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND); 3389 val |= MCPR_IMC_COMMAND_ENABLE; 3390 REG_WR(cb, MCP_REG_MCPR_IMC_COMMAND, val); 3391 3392 /* Program slave device ID */ 3393 val = (sl_devid << 16) | sl_addr; 3394 REG_WR(cb, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); 3395 3396 /* Start xfer with 0 byte to update the address pointer ???*/ 3397 val = (MCPR_IMC_COMMAND_ENABLE) | 3398 (MCPR_IMC_COMMAND_WRITE_OP << 3399 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3400 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); 3401 REG_WR(cb, MCP_REG_MCPR_IMC_COMMAND, val); 3402 3403 /* Poll for completion */ 3404 i = 0; 3405 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND); 3406 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3407 USLEEP(cb, 10); 3408 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND); 3409 if (i++ > 1000) { 3410 ELINK_DEBUG_P1(cb, "wr 0 byte timed out after %d try\n", 3411 i); 3412 rc = ELINK_STATUS_TIMEOUT; 3413 break; 3414 } 3415 } 3416 if (rc == ELINK_STATUS_TIMEOUT) 3417 return rc; 3418 3419 /* Start xfer with read op */ 3420 val = (MCPR_IMC_COMMAND_ENABLE) | 3421 (MCPR_IMC_COMMAND_READ_OP << 3422 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3423 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | 3424 (xfer_cnt); 3425 REG_WR(cb, MCP_REG_MCPR_IMC_COMMAND, val); 3426 3427 /* Poll for completion */ 3428 i = 0; 3429 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND); 3430 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3431 USLEEP(cb, 10); 3432 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND); 3433 if (i++ > 1000) { 3434 ELINK_DEBUG_P1(cb, "rd op timed out after %d try\n", i); 3435 rc = ELINK_STATUS_TIMEOUT; 3436 break; 3437 } 3438 } 3439 if (rc == ELINK_STATUS_TIMEOUT) 3440 return rc; 3441 3442 for (i = (lc_addr >> 2); i < 4; i++) { 3443 data_array[i] = REG_RD(cb, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); 3444 #ifdef BIG_ENDIAN 3445 data_array[i] = ((data_array[i] & 0x000000ff) << 24) | 3446 ((data_array[i] & 0x0000ff00) << 8) | 3447 ((data_array[i] & 0x00ff0000) >> 8) | 3448 ((data_array[i] & 0xff000000) >> 24); 3449 #endif 3450 } 3451 return rc; 3452 } 3453 3454 #endif /* EXCLUDE_WARPCORE */ 3455 #endif /* EXCLUDE_NON_COMMON_INIT */ 3456 #if !defined(EXCLUDE_NON_COMMON_INIT) || defined(INCLUDE_WARPCORE_UC_LOAD) 3457 static void elink_cl45_read_or_write(struct elink_dev *cb, struct elink_phy *phy, 3458 u8 devad, u16 reg, u16 or_val) 3459 { 3460 u16 val; 3461 elink_cl45_read(cb, phy, devad, reg, &val); 3462 elink_cl45_write(cb, phy, devad, reg, val | or_val); 3463 } 3464 3465 static void elink_cl45_read_and_write(struct elink_dev *cb, 3466 struct elink_phy *phy, 3467 u8 devad, u16 reg, u16 and_val) 3468 { 3469 u16 val; 3470 elink_cl45_read(cb, phy, devad, reg, &val); 3471 elink_cl45_write(cb, phy, devad, reg, val & and_val); 3472 } 3473 #endif 3474 3475 #ifdef ELINK_ENHANCEMENTS 3476 elink_status_t elink_phy_read(struct elink_params *params, u8 phy_addr, 3477 u8 devad, u16 reg, u16 *ret_val) 3478 { 3479 u8 phy_index; 3480 /* Probe for the phy according to the given phy_addr, and execute 3481 * the read request on it 3482 */ 3483 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3484 if (params->phy[phy_index].addr == phy_addr) { 3485 return elink_cl45_read(params->cb, 3486 ¶ms->phy[phy_index], devad, 3487 reg, ret_val); 3488 } 3489 } 3490 return ELINK_STATUS_ERROR; 3491 } 3492 3493 elink_status_t elink_phy_write(struct elink_params *params, u8 phy_addr, 3494 u8 devad, u16 reg, u16 val) 3495 { 3496 u8 phy_index; 3497 /* Probe for the phy according to the given phy_addr, and execute 3498 * the write request on it 3499 */ 3500 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3501 if (params->phy[phy_index].addr == phy_addr) { 3502 return elink_cl45_write(params->cb, 3503 ¶ms->phy[phy_index], devad, 3504 reg, val); 3505 } 3506 } 3507 return ELINK_STATUS_ERROR; 3508 } 3509 #endif // ELINK_ENHANCEMENTS 3510 3511 #if (!defined EXCLUDE_NON_COMMON_INIT) || (!defined EXCLUDE_WARPCORE) 3512 static u8 elink_get_warpcore_lane(struct elink_phy *phy, 3513 struct elink_params *params) 3514 { 3515 u8 lane = 0; 3516 #ifndef EXCLUDE_WARPCORE 3517 struct elink_dev *cb = params->cb; 3518 u32 path_swap, path_swap_ovr; 3519 u8 path, port; 3520 3521 path = PATH_ID(cb); 3522 port = params->port; 3523 3524 if (elink_is_4_port_mode(cb)) { 3525 u32 port_swap, port_swap_ovr; 3526 3527 /* Figure out path swap value */ 3528 path_swap_ovr = REG_RD(cb, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); 3529 if (path_swap_ovr & 0x1) 3530 path_swap = (path_swap_ovr & 0x2); 3531 else 3532 path_swap = REG_RD(cb, MISC_REG_FOUR_PORT_PATH_SWAP); 3533 3534 if (path_swap) 3535 path = path ^ 1; 3536 3537 /* Figure out port swap value */ 3538 port_swap_ovr = REG_RD(cb, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); 3539 if (port_swap_ovr & 0x1) 3540 port_swap = (port_swap_ovr & 0x2); 3541 else 3542 port_swap = REG_RD(cb, MISC_REG_FOUR_PORT_PORT_SWAP); 3543 3544 if (port_swap) 3545 port = port ^ 1; 3546 3547 lane = (port<<1) + path; 3548 } else { /* Two port mode - no port swap */ 3549 3550 /* Figure out path swap value */ 3551 path_swap_ovr = 3552 REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); 3553 if (path_swap_ovr & 0x1) { 3554 path_swap = (path_swap_ovr & 0x2); 3555 } else { 3556 path_swap = 3557 REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP); 3558 } 3559 if (path_swap) 3560 path = path ^ 1; 3561 3562 lane = path << 1 ; 3563 } 3564 #endif /* #ifndef EXCLUDE_WARPCORE */ 3565 return lane; 3566 } 3567 3568 3569 static void elink_set_aer_mmd(struct elink_params *params, 3570 struct elink_phy *phy) 3571 { 3572 u32 ser_lane; 3573 u16 offset, aer_val; 3574 struct elink_dev *cb = params->cb; 3575 ser_lane = ((params->lane_config & 3576 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 3577 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 3578 3579 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? 3580 (phy->addr + ser_lane) : 0; 3581 3582 if (ELINK_USES_WARPCORE(params->chip_id)) { 3583 aer_val = elink_get_warpcore_lane(phy, params); 3584 /* In Dual-lane mode, two lanes are joined together, 3585 * so in order to configure them, the AER broadcast method is 3586 * used here. 3587 * 0x200 is the broadcast address for lanes 0,1 3588 * 0x201 is the broadcast address for lanes 2,3 3589 */ 3590 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) 3591 aer_val = (aer_val >> 1) | 0x200; 3592 } else if (CHIP_IS_E2(params->chip_id)) 3593 aer_val = 0x3800 + offset - 1; 3594 else 3595 aer_val = 0x3800 + offset; 3596 3597 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 3598 MDIO_AER_BLOCK_AER_REG, aer_val); 3599 3600 } 3601 #endif 3602 #ifndef EXCLUDE_SERDES 3603 3604 /******************************************************************/ 3605 /* Internal phy section */ 3606 /******************************************************************/ 3607 3608 static void elink_set_serdes_access(struct elink_dev *cb, u8 port) 3609 { 3610 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 3611 3612 /* Set Clause 22 */ 3613 REG_WR(cb, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); 3614 REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); 3615 USLEEP(cb, 500); 3616 REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); 3617 USLEEP(cb, 500); 3618 /* Set Clause 45 */ 3619 REG_WR(cb, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); 3620 } 3621 3622 static void elink_serdes_deassert(struct elink_dev *cb, u8 port) 3623 { 3624 u32 val; 3625 3626 ELINK_DEBUG_P0(cb, "elink_serdes_deassert\n"); 3627 3628 val = ELINK_SERDES_RESET_BITS << (port*16); 3629 3630 /* Reset and unreset the SerDes/XGXS */ 3631 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3632 USLEEP(cb, 500); 3633 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3634 3635 elink_set_serdes_access(cb, port); 3636 3637 REG_WR(cb, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, 3638 ELINK_DEFAULT_PHY_DEV_ADDR); 3639 } 3640 #endif /* #ifndef EXCLUDE_SERDES */ 3641 3642 #ifndef EXCLUDE_NON_COMMON_INIT 3643 #ifndef EXCLUDE_XGXS 3644 static void elink_xgxs_specific_func(struct elink_phy *phy, 3645 struct elink_params *params, 3646 u32 action) 3647 { 3648 struct elink_dev *cb = params->cb; 3649 switch (action) { 3650 case ELINK_PHY_INIT: 3651 /* Set correct devad */ 3652 REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); 3653 REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, 3654 phy->def_md_devad); 3655 break; 3656 } 3657 } 3658 3659 static void elink_xgxs_deassert(struct elink_params *params) 3660 { 3661 struct elink_dev *cb = params->cb; 3662 u8 port; 3663 u32 val; 3664 ELINK_DEBUG_P0(cb, "elink_xgxs_deassert\n"); 3665 port = params->port; 3666 3667 val = ELINK_XGXS_RESET_BITS << (port*16); 3668 3669 /* Reset and unreset the SerDes/XGXS */ 3670 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3671 USLEEP(cb, 500); 3672 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3673 elink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params, 3674 ELINK_PHY_INIT); 3675 } 3676 #endif // EXCLUDE_XGXS 3677 3678 static void elink_calc_ieee_aneg_adv(struct elink_phy *phy, 3679 struct elink_params *params, u16 *ieee_fc) 3680 { 3681 #ifdef ELINK_DEBUG 3682 struct elink_dev *cb = params->cb; 3683 #endif 3684 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; 3685 /* Resolve pause mode and advertisement Please refer to Table 3686 * 28B-3 of the 802.3ab-1999 spec 3687 */ 3688 3689 switch (phy->req_flow_ctrl) { 3690 case ELINK_FLOW_CTRL_AUTO: 3691 switch (params->req_fc_auto_adv) { 3692 case ELINK_FLOW_CTRL_BOTH: 3693 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3694 break; 3695 case ELINK_FLOW_CTRL_RX: 3696 case ELINK_FLOW_CTRL_TX: 3697 *ieee_fc |= 3698 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3699 break; 3700 default: 3701 break; 3702 } 3703 break; 3704 case ELINK_FLOW_CTRL_TX: 3705 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3706 break; 3707 3708 case ELINK_FLOW_CTRL_RX: 3709 case ELINK_FLOW_CTRL_BOTH: 3710 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3711 break; 3712 3713 case ELINK_FLOW_CTRL_NONE: 3714 default: 3715 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; 3716 break; 3717 } 3718 ELINK_DEBUG_P1(cb, "ieee_fc = 0x%x\n", *ieee_fc); 3719 } 3720 #endif /* #ifndef EXCLUDE_NON_COMMON_INIT */ 3721 3722 static void set_phy_vars(struct elink_params *params, 3723 struct elink_vars *vars) 3724 { 3725 #ifdef ELINK_DEBUG 3726 struct elink_dev *cb = params->cb; 3727 #endif 3728 u8 actual_phy_idx, phy_index, link_cfg_idx; 3729 u8 phy_config_swapped = params->multi_phy_config & 3730 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 3731 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; 3732 phy_index++) { 3733 link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index); 3734 actual_phy_idx = phy_index; 3735 if (phy_config_swapped) { 3736 if (phy_index == ELINK_EXT_PHY1) 3737 actual_phy_idx = ELINK_EXT_PHY2; 3738 else if (phy_index == ELINK_EXT_PHY2) 3739 actual_phy_idx = ELINK_EXT_PHY1; 3740 } 3741 params->phy[actual_phy_idx].req_flow_ctrl = 3742 params->req_flow_ctrl[link_cfg_idx]; 3743 3744 params->phy[actual_phy_idx].req_line_speed = 3745 params->req_line_speed[link_cfg_idx]; 3746 3747 params->phy[actual_phy_idx].speed_cap_mask = 3748 params->speed_cap_mask[link_cfg_idx]; 3749 3750 params->phy[actual_phy_idx].req_duplex = 3751 params->req_duplex[link_cfg_idx]; 3752 3753 if (params->req_line_speed[link_cfg_idx] == 3754 ELINK_SPEED_AUTO_NEG) 3755 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 3756 3757 ELINK_DEBUG_P3(cb, "req_flow_ctrl %x, req_line_speed %x," 3758 " speed_cap_mask %x\n", 3759 params->phy[actual_phy_idx].req_flow_ctrl, 3760 params->phy[actual_phy_idx].req_line_speed, 3761 params->phy[actual_phy_idx].speed_cap_mask); 3762 } 3763 } 3764 3765 #ifndef EXCLUDE_NON_COMMON_INIT 3766 static void elink_ext_phy_set_pause(struct elink_params *params, 3767 struct elink_phy *phy, 3768 struct elink_vars *vars) 3769 { 3770 u16 val; 3771 struct elink_dev *cb = params->cb; 3772 /* Read modify write pause advertizing */ 3773 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); 3774 3775 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; 3776 3777 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 3778 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 3779 if ((vars->ieee_fc & 3780 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 3781 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 3782 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 3783 } 3784 if ((vars->ieee_fc & 3785 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 3786 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 3787 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 3788 } 3789 ELINK_DEBUG_P1(cb, "Ext phy AN advertize 0x%x\n", val); 3790 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); 3791 } 3792 3793 static void elink_pause_resolve(struct elink_vars *vars, u32 pause_result) 3794 { /* LD LP */ 3795 switch (pause_result) { /* ASYM P ASYM P */ 3796 case 0xb: /* 1 0 1 1 */ 3797 vars->flow_ctrl = ELINK_FLOW_CTRL_TX; 3798 break; 3799 3800 case 0xe: /* 1 1 1 0 */ 3801 vars->flow_ctrl = ELINK_FLOW_CTRL_RX; 3802 break; 3803 3804 case 0x5: /* 0 1 0 1 */ 3805 case 0x7: /* 0 1 1 1 */ 3806 case 0xd: /* 1 1 0 1 */ 3807 case 0xf: /* 1 1 1 1 */ 3808 vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH; 3809 break; 3810 3811 default: 3812 break; 3813 } 3814 if (pause_result & (1<<0)) 3815 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; 3816 if (pause_result & (1<<1)) 3817 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; 3818 3819 } 3820 3821 static void elink_ext_phy_update_adv_fc(struct elink_phy *phy, 3822 struct elink_params *params, 3823 struct elink_vars *vars) 3824 { 3825 u16 ld_pause; /* local */ 3826 u16 lp_pause; /* link partner */ 3827 u16 pause_result; 3828 struct elink_dev *cb = params->cb; 3829 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { 3830 #ifndef EXCLUDE_BCM54618SE 3831 elink_cl22_read(cb, phy, 0x4, &ld_pause); 3832 elink_cl22_read(cb, phy, 0x5, &lp_pause); 3833 #endif 3834 } else if (CHIP_IS_E3(params->chip_id) && 3835 ELINK_SINGLE_MEDIA_DIRECT(params)) { 3836 u8 lane = elink_get_warpcore_lane(phy, params); 3837 u16 gp_status, gp_mask; 3838 elink_cl45_read(cb, phy, 3839 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, 3840 &gp_status); 3841 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | 3842 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << 3843 lane; 3844 if ((gp_status & gp_mask) == gp_mask) { 3845 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 3846 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3847 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 3848 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3849 } else { 3850 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 3851 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 3852 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 3853 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 3854 ld_pause = ((ld_pause & 3855 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3856 << 3); 3857 lp_pause = ((lp_pause & 3858 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3859 << 3); 3860 } 3861 } else { 3862 elink_cl45_read(cb, phy, 3863 MDIO_AN_DEVAD, 3864 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3865 elink_cl45_read(cb, phy, 3866 MDIO_AN_DEVAD, 3867 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3868 } 3869 pause_result = (ld_pause & 3870 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; 3871 pause_result |= (lp_pause & 3872 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; 3873 ELINK_DEBUG_P1(cb, "Ext PHY pause result 0x%x\n", pause_result); 3874 elink_pause_resolve(vars, pause_result); 3875 3876 } 3877 3878 static u8 elink_ext_phy_resolve_fc(struct elink_phy *phy, 3879 struct elink_params *params, 3880 struct elink_vars *vars) 3881 { 3882 u8 ret = 0; 3883 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 3884 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) { 3885 /* Update the advertised flow-controled of LD/LP in AN */ 3886 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) 3887 elink_ext_phy_update_adv_fc(phy, params, vars); 3888 /* But set the flow-control result as the requested one */ 3889 vars->flow_ctrl = phy->req_flow_ctrl; 3890 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) 3891 vars->flow_ctrl = params->req_fc_auto_adv; 3892 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 3893 ret = 1; 3894 elink_ext_phy_update_adv_fc(phy, params, vars); 3895 } 3896 return ret; 3897 } 3898 #endif // EXCLUDE_NON_COMMON_INIT 3899 /******************************************************************/ 3900 /* Warpcore section */ 3901 /******************************************************************/ 3902 /* The init_internal_warpcore should mirror the xgxs, 3903 * i.e. reset the lane (if needed), set aer for the 3904 * init configuration, and set/clear SGMII flag. Internal 3905 * phy init is done purely in phy_init stage. 3906 */ 3907 #define WC_TX_DRIVER(post2, idriver, ipre) \ 3908 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \ 3909 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \ 3910 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)) 3911 3912 #define WC_TX_FIR(post, main, pre) \ 3913 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \ 3914 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \ 3915 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)) 3916 3917 #ifndef EXCLUDE_WARPCORE 3918 #ifndef EXCLUDE_NON_COMMON_INIT 3919 static void elink_update_link_attr(struct elink_params *params, u32 link_attr) 3920 { 3921 struct elink_dev *cb = params->cb; 3922 3923 if (SHMEM2_HAS(cb, params->shmem2_base, link_attr_sync)) 3924 REG_WR(cb, params->shmem2_base + 3925 OFFSETOF(struct shmem2_region, 3926 link_attr_sync[params->port]), link_attr); 3927 } 3928 3929 static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy, 3930 struct elink_params *params, 3931 struct elink_vars *vars) 3932 { 3933 struct elink_dev *cb = params->cb; 3934 u16 i; 3935 static struct elink_reg_set reg_set[] = { 3936 /* Step 1 - Program the TX/RX alignment markers */ 3937 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157}, 3938 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2}, 3939 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537}, 3940 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157}, 3941 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2}, 3942 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537}, 3943 /* Step 2 - Configure the NP registers */ 3944 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a}, 3945 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400}, 3946 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620}, 3947 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157}, 3948 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464}, 3949 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150}, 3950 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150}, 3951 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, 3952 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} 3953 }; 3954 ELINK_DEBUG_P0(cb, "Enabling 20G-KR2\n"); 3955 3956 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 3957 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6)); 3958 3959 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3960 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg, 3961 reg_set[i].val); 3962 3963 /* Start KR2 work-around timer which handles BCM8073 link-parner */ 3964 params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; 3965 elink_update_link_attr(params, params->link_attr_sync); 3966 } 3967 3968 static void elink_disable_kr2(struct elink_params *params, 3969 struct elink_vars *vars, 3970 struct elink_phy *phy) 3971 { 3972 struct elink_dev *cb = params->cb; 3973 int i; 3974 static struct elink_reg_set reg_set[] = { 3975 /* Step 1 - Program the TX/RX alignment markers */ 3976 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, 3977 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647}, 3978 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0}, 3979 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690}, 3980 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647}, 3981 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0}, 3982 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c}, 3983 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000}, 3984 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000}, 3985 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002}, 3986 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000}, 3987 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7}, 3988 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7}, 3989 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, 3990 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} 3991 }; 3992 ELINK_DEBUG_P0(cb, "Disabling 20G-KR2\n"); 3993 3994 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3995 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg, 3996 reg_set[i].val); 3997 params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; 3998 elink_update_link_attr(params, params->link_attr_sync); 3999 4000 vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT; 4001 } 4002 4003 static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy, 4004 struct elink_params *params) 4005 { 4006 struct elink_dev *cb = params->cb; 4007 4008 ELINK_DEBUG_P0(cb, "Configure WC for LPI pass through\n"); 4009 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4010 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); 4011 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4012 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); 4013 } 4014 4015 static void elink_warpcore_restart_AN_KR(struct elink_phy *phy, 4016 struct elink_params *params) 4017 { 4018 /* Restart autoneg on the leading lane only */ 4019 struct elink_dev *cb = params->cb; 4020 u16 lane = elink_get_warpcore_lane(phy, params); 4021 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4022 MDIO_AER_BLOCK_AER_REG, lane); 4023 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 4024 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 4025 4026 /* Restore AER */ 4027 elink_set_aer_mmd(params, phy); 4028 } 4029 4030 static void elink_warpcore_enable_AN_KR(struct elink_phy *phy, 4031 struct elink_params *params, 4032 struct elink_vars *vars) { 4033 u16 lane, i, cl72_ctrl, an_adv = 0, val; 4034 u32 wc_lane_config; 4035 struct elink_dev *cb = params->cb; 4036 static struct elink_reg_set reg_set[] = { 4037 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 4038 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, 4039 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, 4040 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, 4041 /* Disable Autoneg: re-enable it after adv is done. */ 4042 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}, 4043 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}, 4044 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, 4045 }; 4046 ELINK_DEBUG_P0(cb, "Enable Auto Negotiation for KR\n"); 4047 /* Set to default registers that may be overriden by 10G force */ 4048 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 4049 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg, 4050 reg_set[i].val); 4051 4052 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4053 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); 4054 cl72_ctrl &= 0x08ff; 4055 cl72_ctrl |= 0x3800; 4056 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4057 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); 4058 4059 /* Check adding advertisement for 1G KX */ 4060 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) && 4061 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 4062 (vars->line_speed == ELINK_SPEED_1000)) { 4063 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; 4064 an_adv |= (1<<5); 4065 4066 /* Enable CL37 1G Parallel Detect */ 4067 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, addr, 0x1); 4068 ELINK_DEBUG_P0(cb, "Advertize 1G\n"); 4069 } 4070 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) && 4071 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 4072 (vars->line_speed == ELINK_SPEED_10000)) { 4073 /* Check adding advertisement for 10G KR */ 4074 an_adv |= (1<<7); 4075 /* Enable 10G Parallel Detect */ 4076 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4077 MDIO_AER_BLOCK_AER_REG, 0); 4078 4079 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 4080 MDIO_WC_REG_PAR_DET_10G_CTRL, 1); 4081 elink_set_aer_mmd(params, phy); 4082 ELINK_DEBUG_P0(cb, "Advertize 10G\n"); 4083 } 4084 4085 /* Set Transmit PMD settings */ 4086 lane = elink_get_warpcore_lane(phy, params); 4087 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4088 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4089 WC_TX_DRIVER(0x02, 0x06, 0x09)); 4090 /* Configure the next lane if dual mode */ 4091 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) 4092 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4093 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1), 4094 WC_TX_DRIVER(0x02, 0x06, 0x09)); 4095 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4096 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 4097 0x03f0); 4098 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4099 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 4100 0x03f0); 4101 4102 /* Advertised speeds */ 4103 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 4104 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv); 4105 4106 /* Advertised and set FEC (Forward Error Correction) */ 4107 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 4108 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, 4109 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | 4110 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); 4111 4112 /* Enable CL37 BAM */ 4113 if (REG_RD(cb, params->shmem_base + 4114 OFFSETOF(struct shmem_region, dev_info. 4115 port_hw_config[params->port].default_cfg)) & 4116 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 4117 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4118 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, 4119 1); 4120 ELINK_DEBUG_P0(cb, "Enable CL37 BAM on KR\n"); 4121 } 4122 4123 /* Advertise pause */ 4124 elink_ext_phy_set_pause(params, phy, vars); 4125 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 4126 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4127 MDIO_WC_REG_DIGITAL5_MISC7, 0x100); 4128 4129 /* Over 1G - AN local device user page 1 */ 4130 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4131 MDIO_WC_REG_DIGITAL3_UP1, 0x1f); 4132 4133 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 4134 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || 4135 (phy->req_line_speed == ELINK_SPEED_20000)) { 4136 4137 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4138 MDIO_AER_BLOCK_AER_REG, lane); 4139 4140 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4141 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane), 4142 (1<<11)); 4143 4144 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4145 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); 4146 elink_set_aer_mmd(params, phy); 4147 4148 elink_warpcore_enable_AN_KR2(phy, params, vars); 4149 } else { 4150 /* Enable Auto-Detect to support 1G over CL37 as well */ 4151 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4152 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10); 4153 wc_lane_config = REG_RD(cb, params->shmem_base + 4154 OFFSETOF(struct shmem_region, dev_info. 4155 shared_hw_config.wc_lane_config)); 4156 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4157 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val); 4158 /* Force cl48 sync_status LOW to avoid getting stuck in CL73 4159 * parallel-detect loop when CL73 and CL37 are enabled. 4160 */ 4161 val |= 1 << 11; 4162 4163 /* Restore Polarity settings in case it was run over by 4164 * previous link owner 4165 */ 4166 if (wc_lane_config & 4167 (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane)) 4168 val |= 3 << 2; 4169 else 4170 val &= ~(3 << 2); 4171 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4172 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), 4173 val); 4174 4175 elink_disable_kr2(params, vars, phy); 4176 } 4177 4178 /* Enable Autoneg: only on the main lane */ 4179 elink_warpcore_restart_AN_KR(phy, params); 4180 } 4181 4182 static void elink_warpcore_set_10G_KR(struct elink_phy *phy, 4183 struct elink_params *params, 4184 struct elink_vars *vars) 4185 { 4186 struct elink_dev *cb = params->cb; 4187 u16 val16, i, lane; 4188 static struct elink_reg_set reg_set[] = { 4189 /* Disable Autoneg */ 4190 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 4191 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 4192 0x3f00}, 4193 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, 4194 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, 4195 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, 4196 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, 4197 /* Leave cl72 training enable, needed for KR */ 4198 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2} 4199 }; 4200 4201 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 4202 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg, 4203 reg_set[i].val); 4204 4205 lane = elink_get_warpcore_lane(phy, params); 4206 /* Global registers */ 4207 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4208 MDIO_AER_BLOCK_AER_REG, 0); 4209 /* Disable CL36 PCS Tx */ 4210 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4211 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 4212 val16 &= ~(0x0011 << lane); 4213 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4214 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 4215 4216 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4217 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 4218 val16 |= (0x0303 << (lane << 1)); 4219 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4220 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 4221 /* Restore AER */ 4222 elink_set_aer_mmd(params, phy); 4223 /* Set speed via PMA/PMD register */ 4224 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 4225 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); 4226 4227 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 4228 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); 4229 4230 /* Enable encoded forced speed */ 4231 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4232 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); 4233 4234 /* Turn TX scramble payload only the 64/66 scrambler */ 4235 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4236 MDIO_WC_REG_TX66_CONTROL, 0x9); 4237 4238 /* Turn RX scramble payload only the 64/66 scrambler */ 4239 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4240 MDIO_WC_REG_RX66_CONTROL, 0xF9); 4241 4242 /* Set and clear loopback to cause a reset to 64/66 decoder */ 4243 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4244 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); 4245 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4246 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); 4247 4248 } 4249 4250 static void elink_warpcore_set_10G_XFI(struct elink_phy *phy, 4251 struct elink_params *params, 4252 u8 is_xfi) 4253 { 4254 struct elink_dev *cb = params->cb; 4255 u16 misc1_val, tap_val, tx_driver_val, lane, val; 4256 u32 cfg_tap_val, tx_drv_brdct, tx_equal; 4257 4258 /* Hold rxSeqStart */ 4259 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4260 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); 4261 4262 /* Hold tx_fifo_reset */ 4263 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4264 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); 4265 4266 /* Disable CL73 AN */ 4267 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); 4268 4269 /* Disable 100FX Enable and Auto-Detect */ 4270 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4271 MDIO_WC_REG_FX100_CTRL1, 0xFFFA); 4272 4273 /* Disable 100FX Idle detect */ 4274 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4275 MDIO_WC_REG_FX100_CTRL3, 0x0080); 4276 4277 /* Set Block address to Remote PHY & Clear forced_speed[5] */ 4278 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4279 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F); 4280 4281 /* Turn off auto-detect & fiber mode */ 4282 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4283 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4284 0xFFEE); 4285 4286 /* Set filter_force_link, disable_false_link and parallel_detect */ 4287 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4288 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); 4289 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4290 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4291 ((val | 0x0006) & 0xFFFE)); 4292 4293 /* Set XFI / SFI */ 4294 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4295 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); 4296 4297 misc1_val &= ~(0x1f); 4298 4299 if (is_xfi) { 4300 misc1_val |= 0x5; 4301 tap_val = WC_TX_FIR(0x08, 0x37, 0x00); 4302 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03); 4303 } else { 4304 cfg_tap_val = REG_RD(cb, params->shmem_base + 4305 OFFSETOF(struct shmem_region, dev_info. 4306 port_hw_config[params->port]. 4307 sfi_tap_values)); 4308 4309 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK; 4310 4311 tx_drv_brdct = (cfg_tap_val & 4312 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >> 4313 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT; 4314 4315 misc1_val |= 0x9; 4316 4317 /* TAP values are controlled by nvram, if value there isn't 0 */ 4318 if (tx_equal) 4319 tap_val = (u16)tx_equal; 4320 else 4321 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02); 4322 4323 if (tx_drv_brdct) 4324 tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct, 4325 0x06); 4326 else 4327 tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06); 4328 } 4329 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4330 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); 4331 4332 /* Set Transmit PMD settings */ 4333 lane = elink_get_warpcore_lane(phy, params); 4334 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4335 MDIO_WC_REG_TX_FIR_TAP, 4336 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); 4337 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4338 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4339 tx_driver_val); 4340 4341 /* Enable fiber mode, enable and invert sig_det */ 4342 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4343 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); 4344 4345 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ 4346 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4347 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); 4348 4349 elink_warpcore_set_lpi_passthrough(phy, params); 4350 4351 /* 10G XFI Full Duplex */ 4352 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4353 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); 4354 4355 /* Release tx_fifo_reset */ 4356 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4357 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4358 0xFFFE); 4359 /* Release rxSeqStart */ 4360 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4361 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF); 4362 } 4363 #endif //EXCLUDE_NON_COMMON_INIT 4364 4365 #ifndef ELINK_AUX_POWER 4366 static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy, 4367 struct elink_params *params) 4368 { 4369 u16 val; 4370 struct elink_dev *cb = params->cb; 4371 /* Set global registers, so set AER lane to 0 */ 4372 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4373 MDIO_AER_BLOCK_AER_REG, 0); 4374 4375 /* Disable sequencer */ 4376 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4377 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13)); 4378 4379 elink_set_aer_mmd(params, phy); 4380 4381 elink_cl45_read_and_write(cb, phy, MDIO_PMA_DEVAD, 4382 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1)); 4383 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 4384 MDIO_AN_REG_CTRL, 0); 4385 /* Turn off CL73 */ 4386 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4387 MDIO_WC_REG_CL73_USERB0_CTRL, &val); 4388 val &= ~(1<<5); 4389 val |= (1<<6); 4390 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4391 MDIO_WC_REG_CL73_USERB0_CTRL, val); 4392 4393 /* Set 20G KR2 force speed */ 4394 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4395 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f); 4396 4397 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4398 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7)); 4399 4400 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4401 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val); 4402 val &= ~(3<<14); 4403 val |= (1<<15); 4404 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4405 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val); 4406 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4407 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A); 4408 4409 /* Enable sequencer (over lane 0) */ 4410 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4411 MDIO_AER_BLOCK_AER_REG, 0); 4412 4413 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4414 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13)); 4415 4416 elink_set_aer_mmd(params, phy); 4417 } 4418 #endif 4419 4420 #ifndef EXCLUDE_COMMON_INIT 4421 static void elink_warpcore_set_20G_DXGXS(struct elink_dev *cb, 4422 struct elink_phy *phy, 4423 u16 lane) 4424 { 4425 /* Rx0 anaRxControl1G */ 4426 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4427 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); 4428 4429 /* Rx2 anaRxControl1G */ 4430 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4431 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); 4432 4433 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4434 MDIO_WC_REG_RX66_SCW0, 0xE070); 4435 4436 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4437 MDIO_WC_REG_RX66_SCW1, 0xC0D0); 4438 4439 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4440 MDIO_WC_REG_RX66_SCW2, 0xA0B0); 4441 4442 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4443 MDIO_WC_REG_RX66_SCW3, 0x8090); 4444 4445 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4446 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); 4447 4448 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4449 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); 4450 4451 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4452 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); 4453 4454 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4455 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); 4456 4457 /* Serdes Digital Misc1 */ 4458 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4459 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); 4460 4461 /* Serdes Digital4 Misc3 */ 4462 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4463 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); 4464 4465 /* Set Transmit PMD settings */ 4466 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4467 MDIO_WC_REG_TX_FIR_TAP, 4468 (WC_TX_FIR(0x12, 0x2d, 0x00) | 4469 MDIO_WC_REG_TX_FIR_TAP_ENABLE)); 4470 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4471 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4472 WC_TX_DRIVER(0x02, 0x02, 0x02)); 4473 } 4474 #endif 4475 4476 #ifndef EXCLUDE_NON_COMMON_INIT 4477 static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy, 4478 struct elink_params *params, 4479 u8 fiber_mode, 4480 u8 always_autoneg) 4481 { 4482 struct elink_dev *cb = params->cb; 4483 u16 val16, digctrl_kx1, digctrl_kx2; 4484 4485 /* Clear XFI clock comp in non-10G single lane mode. */ 4486 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4487 MDIO_WC_REG_RX66_CONTROL, ~(3<<13)); 4488 4489 elink_warpcore_set_lpi_passthrough(phy, params); 4490 4491 if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { 4492 /* SGMII Autoneg */ 4493 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4494 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4495 0x1000); 4496 ELINK_DEBUG_P0(cb, "set SGMII AUTONEG\n"); 4497 } else { 4498 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4499 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4500 val16 &= 0xcebf; 4501 switch (phy->req_line_speed) { 4502 case ELINK_SPEED_10: 4503 break; 4504 case ELINK_SPEED_100: 4505 val16 |= 0x2000; 4506 break; 4507 case ELINK_SPEED_1000: 4508 val16 |= 0x0040; 4509 break; 4510 default: 4511 ELINK_DEBUG_P1(cb, 4512 "Speed not supported: 0x%x\n", phy->req_line_speed); 4513 return; 4514 } 4515 4516 if (phy->req_duplex == DUPLEX_FULL) 4517 val16 |= 0x0100; 4518 4519 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4520 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); 4521 4522 ELINK_DEBUG_P1(cb, "set SGMII force speed %d\n", 4523 phy->req_line_speed); 4524 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4525 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4526 ELINK_DEBUG_P1(cb, " (readback) %x\n", val16); 4527 } 4528 4529 /* SGMII Slave mode and disable signal detect */ 4530 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4531 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); 4532 if (fiber_mode) 4533 digctrl_kx1 = 1; 4534 else 4535 digctrl_kx1 &= 0xff4a; 4536 4537 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4538 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4539 digctrl_kx1); 4540 4541 /* Turn off parallel detect */ 4542 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4543 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); 4544 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4545 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4546 (digctrl_kx2 & ~(1<<2))); 4547 4548 /* Re-enable parallel detect */ 4549 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4550 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4551 (digctrl_kx2 | (1<<2))); 4552 4553 /* Enable autodet */ 4554 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4555 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4556 (digctrl_kx1 | 0x10)); 4557 } 4558 4559 #endif //EXCLUDE_NON_COMMON_INIT 4560 4561 static void elink_warpcore_reset_lane(struct elink_dev *cb, 4562 struct elink_phy *phy, 4563 u8 reset) 4564 { 4565 u16 val; 4566 /* Take lane out of reset after configuration is finished */ 4567 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4568 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4569 if (reset) 4570 val |= 0xC000; 4571 else 4572 val &= 0x3FFF; 4573 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4574 MDIO_WC_REG_DIGITAL5_MISC6, val); 4575 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4576 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4577 } 4578 4579 #ifndef EXCLUDE_NON_COMMON_INIT 4580 /* Clear SFI/XFI link settings registers */ 4581 static void elink_warpcore_clear_regs(struct elink_phy *phy, 4582 struct elink_params *params, 4583 u16 lane) 4584 { 4585 struct elink_dev *cb = params->cb; 4586 u16 i; 4587 static struct elink_reg_set wc_regs[] = { 4588 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, 4589 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, 4590 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, 4591 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, 4592 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4593 0x0195}, 4594 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4595 0x0007}, 4596 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4597 0x0002}, 4598 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, 4599 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, 4600 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, 4601 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} 4602 }; 4603 /* Set XFI clock comp as default. */ 4604 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4605 MDIO_WC_REG_RX66_CONTROL, (3<<13)); 4606 4607 for (i = 0; i < ARRAY_SIZE(wc_regs); i++) 4608 elink_cl45_write(cb, phy, wc_regs[i].devad, wc_regs[i].reg, 4609 wc_regs[i].val); 4610 4611 lane = elink_get_warpcore_lane(phy, params); 4612 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4613 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); 4614 4615 } 4616 4617 static elink_status_t elink_get_mod_abs_int_cfg(struct elink_dev *cb, 4618 u32 chip_id, 4619 u32 shmem_base, u8 port, 4620 u8 *gpio_num, u8 *gpio_port) 4621 { 4622 u32 cfg_pin; 4623 *gpio_num = 0; 4624 *gpio_port = 0; 4625 if (CHIP_IS_E3(chip_id)) { 4626 cfg_pin = (REG_RD(cb, shmem_base + 4627 OFFSETOF(struct shmem_region, 4628 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4629 PORT_HW_CFG_E3_MOD_ABS_MASK) >> 4630 PORT_HW_CFG_E3_MOD_ABS_SHIFT; 4631 4632 /* Should not happen. This function called upon interrupt 4633 * triggered by GPIO ( since EPIO can only generate interrupts 4634 * to MCP). 4635 * So if this function was called and none of the GPIOs was set, 4636 * it means the shit hit the fan. 4637 */ 4638 if ((cfg_pin < PIN_CFG_GPIO0_P0) || 4639 (cfg_pin > PIN_CFG_GPIO3_P1)) { 4640 ELINK_DEBUG_P1(cb, 4641 "No cfg pin %x for module detect indication\n", 4642 cfg_pin); 4643 return ELINK_STATUS_ERROR; 4644 } 4645 4646 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; 4647 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; 4648 } else { 4649 *gpio_num = MISC_REGISTERS_GPIO_3; 4650 *gpio_port = port; 4651 } 4652 4653 return ELINK_STATUS_OK; 4654 } 4655 4656 static int elink_is_sfp_module_plugged(struct elink_phy *phy, 4657 struct elink_params *params) 4658 { 4659 struct elink_dev *cb = params->cb; 4660 u8 gpio_num, gpio_port; 4661 u32 gpio_val; 4662 if (elink_get_mod_abs_int_cfg(cb, params->chip_id, 4663 params->shmem_base, params->port, 4664 &gpio_num, &gpio_port) != ELINK_STATUS_OK) 4665 return 0; 4666 gpio_val = ELINK_GET_GPIO(cb, gpio_num, gpio_port); 4667 4668 /* Call the handling function in case module is detected */ 4669 if (gpio_val == 0) 4670 return 1; 4671 else 4672 return 0; 4673 } 4674 int elink_warpcore_get_sigdet(struct elink_phy *phy, 4675 struct elink_params *params) 4676 { 4677 u16 gp2_status_reg0, lane; 4678 struct elink_dev *cb = params->cb; 4679 4680 lane = elink_get_warpcore_lane(phy, params); 4681 4682 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, 4683 &gp2_status_reg0); 4684 4685 return (gp2_status_reg0 >> (8+lane)) & 0x1; 4686 } 4687 4688 #ifndef ELINK_AUX_POWER 4689 static void elink_warpcore_config_runtime(struct elink_phy *phy, 4690 struct elink_params *params, 4691 struct elink_vars *vars) 4692 { 4693 struct elink_dev *cb = params->cb; 4694 u32 serdes_net_if; 4695 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0; 4696 4697 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; 4698 4699 if (!vars->turn_to_run_wc_rt) 4700 return; 4701 4702 if (vars->rx_tx_asic_rst) { 4703 u16 lane = elink_get_warpcore_lane(phy, params); 4704 serdes_net_if = (REG_RD(cb, params->shmem_base + 4705 OFFSETOF(struct shmem_region, dev_info. 4706 port_hw_config[params->port].default_cfg)) & 4707 PORT_HW_CFG_NET_SERDES_IF_MASK); 4708 4709 switch (serdes_net_if) { 4710 case PORT_HW_CFG_NET_SERDES_IF_KR: 4711 /* Do we get link yet? */ 4712 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 0x81d1, 4713 &gp_status1); 4714 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ 4715 /*10G KR*/ 4716 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; 4717 4718 if (lnkup_kr || lnkup) { 4719 vars->rx_tx_asic_rst = 0; 4720 } else { 4721 /* Reset the lane to see if link comes up.*/ 4722 elink_warpcore_reset_lane(cb, phy, 1); 4723 elink_warpcore_reset_lane(cb, phy, 0); 4724 4725 /* Restart Autoneg */ 4726 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 4727 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 4728 4729 vars->rx_tx_asic_rst--; 4730 ELINK_DEBUG_P1(cb, "0x%x retry left\n", 4731 vars->rx_tx_asic_rst); 4732 } 4733 break; 4734 4735 default: 4736 break; 4737 } 4738 4739 } /*params->rx_tx_asic_rst*/ 4740 4741 } 4742 #endif 4743 static void elink_warpcore_config_sfi(struct elink_phy *phy, 4744 struct elink_params *params) 4745 { 4746 u16 lane = elink_get_warpcore_lane(phy, params); 4747 #ifdef ELINK_DEBUG 4748 struct elink_dev *cb = params->cb; 4749 #endif 4750 elink_warpcore_clear_regs(phy, params, lane); 4751 if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] == 4752 ELINK_SPEED_10000) && 4753 (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) { 4754 ELINK_DEBUG_P0(cb, "Setting 10G SFI\n"); 4755 elink_warpcore_set_10G_XFI(phy, params, 0); 4756 } else { 4757 ELINK_DEBUG_P0(cb, "Setting 1G Fiber\n"); 4758 elink_warpcore_set_sgmii_speed(phy, params, 1, 0); 4759 } 4760 } 4761 4762 static void elink_sfp_e3_set_transmitter(struct elink_params *params, 4763 struct elink_phy *phy, 4764 u8 tx_en) 4765 { 4766 struct elink_dev *cb = params->cb; 4767 u32 cfg_pin; 4768 u8 port = params->port; 4769 4770 cfg_pin = REG_RD(cb, params->shmem_base + 4771 OFFSETOF(struct shmem_region, 4772 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4773 PORT_HW_CFG_E3_TX_LASER_MASK; 4774 /* Set the !tx_en since this pin is DISABLE_TX_LASER */ 4775 ELINK_DEBUG_P1(cb, "Setting WC TX to %d\n", tx_en); 4776 4777 /* For 20G, the expected pin to be used is 3 pins after the current */ 4778 elink_set_cfg_pin(cb, cfg_pin, tx_en ^ 1); 4779 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) 4780 elink_set_cfg_pin(cb, cfg_pin + 3, tx_en ^ 1); 4781 } 4782 4783 static elink_status_t 4784 elink_warpcore_config_init(struct elink_phy *phy, struct elink_params *params, 4785 struct elink_vars *vars) 4786 { 4787 struct elink_dev *cb = params->cb; 4788 u32 serdes_net_if; 4789 u8 fiber_mode; 4790 u16 lane = elink_get_warpcore_lane(phy, params); 4791 serdes_net_if = (REG_RD(cb, params->shmem_base + 4792 OFFSETOF(struct shmem_region, dev_info. 4793 port_hw_config[params->port].default_cfg)) & 4794 PORT_HW_CFG_NET_SERDES_IF_MASK); 4795 ELINK_DEBUG_P2(cb, "Begin Warpcore init, link_speed %d, " 4796 "serdes_net_if = 0x%x\n", 4797 vars->line_speed, serdes_net_if); 4798 elink_set_aer_mmd(params, phy); 4799 elink_warpcore_reset_lane(cb, phy, 1); 4800 vars->phy_flags |= PHY_XGXS_FLAG; 4801 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || 4802 (phy->req_line_speed && 4803 ((phy->req_line_speed == ELINK_SPEED_100) || 4804 (phy->req_line_speed == ELINK_SPEED_10)))) { 4805 vars->phy_flags |= PHY_SGMII_FLAG; 4806 ELINK_DEBUG_P0(cb, "Setting SGMII mode\n"); 4807 elink_warpcore_clear_regs(phy, params, lane); 4808 elink_warpcore_set_sgmii_speed(phy, params, 0, 1); 4809 } else { 4810 switch (serdes_net_if) { 4811 case PORT_HW_CFG_NET_SERDES_IF_KR: 4812 /* Enable KR Auto Neg */ 4813 if (params->loopback_mode != ELINK_LOOPBACK_EXT) 4814 elink_warpcore_enable_AN_KR(phy, params, vars); 4815 else { 4816 ELINK_DEBUG_P0(cb, "Setting KR 10G-Force\n"); 4817 elink_warpcore_set_10G_KR(phy, params, vars); 4818 } 4819 break; 4820 4821 case PORT_HW_CFG_NET_SERDES_IF_XFI: 4822 elink_warpcore_clear_regs(phy, params, lane); 4823 if (vars->line_speed == ELINK_SPEED_10000) { 4824 ELINK_DEBUG_P0(cb, "Setting 10G XFI\n"); 4825 elink_warpcore_set_10G_XFI(phy, params, 1); 4826 } else { 4827 if (ELINK_SINGLE_MEDIA_DIRECT(params)) { 4828 ELINK_DEBUG_P0(cb, "1G Fiber\n"); 4829 fiber_mode = 1; 4830 } else { 4831 ELINK_DEBUG_P0(cb, "10/100/1G SGMII\n"); 4832 fiber_mode = 0; 4833 } 4834 elink_warpcore_set_sgmii_speed(phy, 4835 params, 4836 fiber_mode, 4837 0); 4838 } 4839 4840 break; 4841 4842 case PORT_HW_CFG_NET_SERDES_IF_SFI: 4843 /* Issue Module detection if module is plugged, or 4844 * enabled transmitter to avoid current leakage in case 4845 * no module is connected 4846 */ 4847 if ((params->loopback_mode == ELINK_LOOPBACK_NONE) || 4848 (params->loopback_mode == ELINK_LOOPBACK_EXT)) { 4849 if (elink_is_sfp_module_plugged(phy, params)) 4850 elink_sfp_module_detection(phy, params); 4851 else 4852 elink_sfp_e3_set_transmitter(params, 4853 phy, 1); 4854 } 4855 4856 elink_warpcore_config_sfi(phy, params); 4857 break; 4858 4859 #ifndef ELINK_AUX_POWER 4860 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 4861 if (vars->line_speed != ELINK_SPEED_20000) { 4862 ELINK_DEBUG_P0(cb, "Speed not supported yet\n"); 4863 return (ELINK_STATUS_ERROR); 4864 } 4865 ELINK_DEBUG_P0(cb, "Setting 20G DXGXS\n"); 4866 elink_warpcore_set_20G_DXGXS(cb, phy, lane); 4867 /* Issue Module detection */ 4868 4869 elink_sfp_module_detection(phy, params); 4870 break; 4871 #endif 4872 case PORT_HW_CFG_NET_SERDES_IF_KR2: 4873 if (!params->loopback_mode) { 4874 elink_warpcore_enable_AN_KR(phy, params, vars); 4875 } else { 4876 #ifndef ELINK_AUX_POWER 4877 ELINK_DEBUG_P0(cb, "Setting KR 20G-Force\n"); 4878 elink_warpcore_set_20G_force_KR2(phy, params); 4879 #endif 4880 } 4881 break; 4882 default: 4883 ELINK_DEBUG_P1(cb, 4884 "Unsupported Serdes Net Interface 0x%x\n", 4885 serdes_net_if); 4886 return (ELINK_STATUS_ERROR); 4887 } 4888 } 4889 4890 /* Take lane out of reset after configuration is finished */ 4891 elink_warpcore_reset_lane(cb, phy, 0); 4892 ELINK_DEBUG_P0(cb, "Exit config init\n"); 4893 return (ELINK_STATUS_OK); 4894 } 4895 4896 static void elink_warpcore_link_reset(struct elink_phy *phy, 4897 struct elink_params *params) 4898 { 4899 #ifndef EXCLUDE_LINK_RESET 4900 struct elink_dev *cb = params->cb; 4901 u16 val16, lane; 4902 elink_sfp_e3_set_transmitter(params, phy, 0); 4903 elink_set_mdio_emac_per_phy(cb, params); 4904 elink_set_aer_mmd(params, phy); 4905 /* Global register */ 4906 elink_warpcore_reset_lane(cb, phy, 1); 4907 4908 /* Clear loopback settings (if any) */ 4909 /* 10G & 20G */ 4910 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4911 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF); 4912 4913 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4914 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe); 4915 4916 /* Update those 1-copy registers */ 4917 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4918 MDIO_AER_BLOCK_AER_REG, 0); 4919 /* Enable 1G MDIO (1-copy) */ 4920 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4921 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4922 ~0x10); 4923 4924 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4925 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); 4926 lane = elink_get_warpcore_lane(phy, params); 4927 /* Disable CL36 PCS Tx */ 4928 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4929 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 4930 val16 |= (0x11 << lane); 4931 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) 4932 val16 |= (0x22 << lane); 4933 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4934 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 4935 4936 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4937 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 4938 val16 &= ~(0x0303 << (lane << 1)); 4939 val16 |= (0x0101 << (lane << 1)); 4940 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) { 4941 val16 &= ~(0x0c0c << (lane << 1)); 4942 val16 |= (0x0404 << (lane << 1)); 4943 } 4944 4945 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4946 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 4947 /* Restore AER */ 4948 elink_set_aer_mmd(params, phy); 4949 #endif 4950 4951 } 4952 4953 static void elink_set_warpcore_loopback(struct elink_phy *phy, 4954 struct elink_params *params) 4955 { 4956 #ifdef ELINK_INCLUDE_LOOPBACK 4957 struct elink_dev *cb = params->cb; 4958 u16 val16; 4959 u32 lane; 4960 ELINK_DEBUG_P2(cb, "Setting Warpcore loopback type %x, speed %d\n", 4961 params->loopback_mode, phy->req_line_speed); 4962 4963 if (phy->req_line_speed < ELINK_SPEED_10000 || 4964 phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) { 4965 /* 10/100/1000/20G-KR2 */ 4966 4967 /* Update those 1-copy registers */ 4968 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4969 MDIO_AER_BLOCK_AER_REG, 0); 4970 /* Enable 1G MDIO (1-copy) */ 4971 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4972 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4973 0x10); 4974 /* Set 1G loopback based on lane (1-copy) */ 4975 lane = elink_get_warpcore_lane(phy, params); 4976 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4977 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); 4978 val16 |= (1<<lane); 4979 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) 4980 val16 |= (2<<lane); 4981 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4982 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 4983 val16); 4984 4985 /* Switch back to 4-copy registers */ 4986 elink_set_aer_mmd(params, phy); 4987 } else { 4988 /* 10G / 20G-DXGXS */ 4989 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4990 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4991 0x4000); 4992 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4993 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); 4994 } 4995 #endif // #ifdef ELINK_INCLUDE_LOOPBACK 4996 } 4997 #endif // EXCLUDE_NON_COMMON_INIT 4998 #endif // #ifndef EXCLUDE_WARPCORE 4999 5000 #ifdef INCLUDE_WARPCORE_UC_LOAD 5001 static void elink_warpcore_powerdown_secondport_lanes(struct elink_dev *cb, 5002 struct elink_phy *phy) 5003 { 5004 u16 path_swap_ovr, path_swap, i; 5005 u8 power_down_lanes[4]; 5006 5007 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5008 MDIO_WC_REG_XGXSBLK1_LANETEST0, 0); 5009 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5010 MDIO_WC_REG_XGXS_X2_CONTROL2, 0x29FB); 5011 5012 /* Figure out path swap value */ 5013 path_swap_ovr = REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); 5014 if (path_swap_ovr & 0x1) 5015 path_swap = (path_swap_ovr & 0x2); 5016 else 5017 path_swap = REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP); 5018 5019 /* Find which lanes to power down according to path swap value */ 5020 if (path_swap) { 5021 power_down_lanes[0] = 1; 5022 power_down_lanes[1] = 1; 5023 power_down_lanes[2] = 0; 5024 power_down_lanes[3] = 1; 5025 } else { 5026 power_down_lanes[0] = 0; 5027 power_down_lanes[1] = 1; 5028 power_down_lanes[2] = 1; 5029 power_down_lanes[3] = 1; 5030 } 5031 5032 /* Go through lanes which should be powered down */ 5033 for (i = 0; i < 4; i++) { 5034 if (power_down_lanes[i]) { 5035 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5036 MDIO_WC_REG_XGXSBLK1_LANECTRL3, 5037 (1 << i) | (1 << (4+i)) | 5038 (1 << 11)); 5039 5040 elink_cl45_read_and_write( 5041 cb, phy, MDIO_WC_DEVAD, 5042 MDIO_WC_REG_XGXSBLK1_LANECTRL0, 5043 ~((u16)((1 << i) | (1 << (4+i))))); 5044 } 5045 } 5046 } 5047 #endif //INCLUDE_WARPCORE_UC_LOAD 5048 5049 #ifdef INCLUDE_WARPCORE_UC_LOAD 5050 /** 5051 * elink_warpcore_sequencer 5052 * 5053 * @param cb 5054 * @param phy 5055 * @param enable - sequencer 5056 * 5057 * @return u32 5058 * 5059 * Before starting any of the specific speed/protocol flow, 5060 * there's need disable the sequencer and once all 5061 * configurations are made the sequencer will be enabled again. 5062 * That way it is guaranteed that improper link won't be 5063 * established during the init phase. 5064 */ 5065 static void elink_warpcore_sequencer(struct elink_dev *cb, 5066 struct elink_phy *phy, 5067 u8 enable){ 5068 5069 u16 val16; 5070 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5071 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, &val16); 5072 if(enable) 5073 val16 |= 0x2000; 5074 else 5075 val16 &= 0xDFFF; 5076 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5077 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, val16); 5078 } 5079 5080 static void elink_warpcore_set_lane_swap(struct elink_dev *cb, 5081 struct elink_phy *phy, 5082 u32 wc_lane_config) 5083 { 5084 u16 rx_lane_swap, tx_lane_swap, val16; 5085 rx_lane_swap = ((wc_lane_config & 5086 SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> 5087 SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); 5088 5089 tx_lane_swap = ((wc_lane_config & 5090 SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> 5091 SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); 5092 5093 /* Rx Lanes */ 5094 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5095 MDIO_WC_REG_XGXS_RX_LN_SWAP1, &val16); 5096 val16 &= 0xFF00; 5097 val16 |= rx_lane_swap; 5098 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5099 MDIO_WC_REG_XGXS_RX_LN_SWAP1, val16); 5100 5101 /* Tx Lanes */ 5102 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5103 MDIO_WC_REG_XGXS_TX_LN_SWAP1, &val16); 5104 val16 &= 0xFF00; 5105 val16 |= tx_lane_swap; 5106 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5107 MDIO_WC_REG_XGXS_TX_LN_SWAP1, val16); 5108 } 5109 5110 static void elink_warpcore_set_lane_polarity(struct elink_dev *cb, 5111 struct elink_phy *phy, 5112 u32 wc_lane_config) 5113 { 5114 /* Set RX polarity on all lanes; flip and enable the flip. */ 5115 if (wc_lane_config & SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED) 5116 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5117 MDIO_WC_REG_RX0_PCI_CTRL, (3<<2)); 5118 if (wc_lane_config & SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED) 5119 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5120 MDIO_WC_REG_RX1_PCI_CTRL, (3<<2)); 5121 if (wc_lane_config & SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED) 5122 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5123 MDIO_WC_REG_RX2_PCI_CTRL, (3<<2)); 5124 if (wc_lane_config & SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED) 5125 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5126 MDIO_WC_REG_RX3_PCI_CTRL, (3<<2)); 5127 /* Set TX polarity on all lanes */ 5128 if (wc_lane_config & SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED) 5129 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5130 MDIO_WC_REG_TX0_ANA_CTRL0, (1<<5)); 5131 if (wc_lane_config & SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED) 5132 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5133 MDIO_WC_REG_TX1_ANA_CTRL0, (1<<5)); 5134 if (wc_lane_config & SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED) 5135 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5136 MDIO_WC_REG_TX2_ANA_CTRL0, (1<<5)); 5137 if (wc_lane_config & SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED) 5138 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5139 MDIO_WC_REG_TX3_ANA_CTRL0, (1<<5)); 5140 } 5141 5142 static elink_status_t elink_reset_warpcore(struct elink_dev *cb) 5143 { 5144 u16 time; 5145 u32 pll_lock; 5146 ELINK_DEBUG_P0(cb, "Resetting Warpcore\n"); 5147 5148 REG_WR(cb, MISC_REG_WC0_RESET, 0xE); 5149 MSLEEP(cb, 1); 5150 REG_WR(cb, MISC_REG_WC0_RESET, 0xF); 5151 5152 for(time = 0; time < ELINK_MDIO_ACCESS_TIMEOUT; time++) { 5153 MSLEEP(cb, 1); 5154 pll_lock = REG_RD(cb, MISC_REG_WC0_PLL_LOCK); 5155 if (pll_lock & 0x1) { 5156 /* Flush all TX fifo */ 5157 REG_WR(cb, MISC_REG_WC0_RESET, 0x3FF); 5158 break; 5159 } 5160 } 5161 if (time == ELINK_MDIO_ACCESS_TIMEOUT) { 5162 ELINK_DEBUG_P0(cb, "BUG! WARPCORE is still in reset!\n"); 5163 return ELINK_STATUS_ERROR; 5164 } 5165 5166 return ELINK_STATUS_OK; 5167 } 5168 5169 5170 static void elink_warpcore_set_quad_mode(struct elink_dev *cb, 5171 struct elink_phy *phy) 5172 { 5173 u16 lane, val; 5174 /* Need to set lanes 0..3 */ 5175 for (lane = 0; lane < WC_LANE_MAX; lane++) { 5176 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 5177 MDIO_AER_BLOCK_AER_REG, lane); 5178 /* Reset Asic lane */ 5179 elink_warpcore_reset_lane(cb, phy, 1); 5180 // This access is required only for version 0xd101 of the WC FW 5181 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5182 MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL, 5183 &val); 5184 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5185 MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL, 5186 (val & 0xfe07) | 0x78); 5187 5188 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5189 MDIO_WC_REG_DSC_SMC, 0x8000); 5190 5191 /* Set on clock compensation in WC */ 5192 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5193 MDIO_WC_REG_RX66_CONTROL, 0x7415); 5194 5195 /* Set on clock compensation in WC 5196 * For WC/B0 programming register 0x8104 to value 0x8091 insures 5197 * that clock comensation in cl48 modes is enabled during 5198 * multi-port modes, and disabled during single port modes. 5199 */ 5200 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5201 MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G, 5202 0x8091); 5203 } 5204 } 5205 5206 static void elink_warpcore_set_dual_mode(struct elink_dev *cb, 5207 struct elink_phy *phy, 5208 u32 shmem_base) 5209 { 5210 u16 lane, val; 5211 u32 serdes_net_if; 5212 for (lane = 0; lane < WC_LANE_MAX; lane++) { 5213 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 5214 MDIO_AER_BLOCK_AER_REG, lane); 5215 5216 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5217 MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL, 5218 &val); 5219 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5220 MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL, 5221 (val & 0xfe07) | 0x50); 5222 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5223 MDIO_WC_REG_CL49_USERB0_CTRL, 5224 (3<<6)); 5225 5226 /* Set on clock compensation in WC 5227 * For WC/B0 programming register 0x8104 to value 0x8091 insures 5228 * that clock comensation in cl48 modes is enabled during 5229 * multi-port modes, and disabled during single port modes. 5230 */ 5231 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5232 MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G, 5233 0x8091); 5234 /* In dual port mode XFI compensation should be disabled by 5235 * setting 0x83C0[14:13] to 2'b00 for each port. 5236 */ 5237 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 5238 MDIO_WC_REG_RX66_CONTROL, ~(3<<13)); 5239 5240 /* This access is required only for version 0xd101 of the 5241 * WC FW 5242 */ 5243 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5244 MDIO_WC_REG_DSC_SMC, 0x8000); 5245 } 5246 5247 serdes_net_if = (REG_RD(cb, shmem_base + 5248 OFFSETOF(struct shmem_region, dev_info. 5249 port_hw_config[0].default_cfg)) & 5250 PORT_HW_CFG_NET_SERDES_IF_MASK); 5251 5252 /* Configure both ports to 20G to enable clock working on both ports */ 5253 for (lane = 0x200; lane <= 0x201; lane++) { 5254 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 5255 MDIO_AER_BLOCK_AER_REG, lane); 5256 elink_warpcore_reset_lane(cb, phy, 1); 5257 if (serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_DXGXS) 5258 elink_warpcore_set_20G_DXGXS(cb, phy, lane); 5259 } 5260 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5261 MDIO_WC_REG_RX1_PCI_CTRL, (1<<11)); 5262 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5263 MDIO_WC_REG_RX3_PCI_CTRL, (1<<11)); 5264 } 5265 5266 static elink_status_t elink_warpcore_load_uc(struct elink_dev *cb, 5267 struct elink_phy *phy) 5268 { 5269 u16 val, cnt; 5270 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 5271 MDIO_AER_BLOCK_AER_REG, 0); 5272 5273 /* Enable External memory access */ 5274 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5275 MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP, 0x0000); 5276 5277 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5278 MDIO_WC_REG_MICROBLK_CMD3, 0x0407); 5279 5280 /* Initialize ram memory prior to programming it */ 5281 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5282 MDIO_WC_REG_MICROBLK_CMD, 0x8000); 5283 5284 /* Wait for completion of memory initialization */ 5285 for (cnt = 0; cnt < ELINK_WC_UC_TIMEOUT; cnt++) { 5286 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5287 MDIO_WC_REG_MICROBLK_DL_STATUS , &val); 5288 if (val & 0x8000) 5289 break; 5290 USLEEP(cb, 1); 5291 } 5292 if (cnt >= ELINK_WC_UC_TIMEOUT) 5293 return ELINK_STATUS_TIMEOUT; 5294 5295 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, MDIO_WC_REG_UC_INFO_B1_CRC, 0); 5296 5297 /* Load Warpcore microcode for E3 and after */ 5298 elink_cb_load_warpcore_microcode(); 5299 5300 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5301 MDIO_WC_REG_MICROBLK_CMD3, 0x0404); 5302 5303 /* Turn off read_for_cmd bit, check for FW setting this later. */ 5304 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 5305 MDIO_WC_REG_DSC1B0_UC_CTRL, 5306 ~MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD); 5307 5308 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5309 MDIO_WC_REG_MICROBLK_CMD, 0x0810); 5310 for (cnt = 0; cnt < ELINK_WC_RDY_TIMEOUT_MSEC; cnt++) { 5311 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5312 MDIO_WC_REG_DSC1B0_UC_CTRL, &val); 5313 if (val & MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD) 5314 break; 5315 MSLEEP(cb, 1); 5316 } 5317 if (cnt >= ELINK_WC_RDY_TIMEOUT_MSEC) 5318 return ELINK_STATUS_TIMEOUT; 5319 5320 return ELINK_STATUS_OK; 5321 } 5322 #endif /* INCLUDE_WARPCORE_UC_LOAD */ 5323 5324 static void elink_sync_link(struct elink_params *params, 5325 struct elink_vars *vars) 5326 { 5327 #ifdef ELINK_DEBUG 5328 struct elink_dev *cb = params->cb; 5329 #endif 5330 u8 link_10g_plus; 5331 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 5332 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 5333 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); 5334 if (vars->link_up) { 5335 ELINK_DEBUG_P0(cb, "phy link up\n"); 5336 5337 vars->phy_link_up = 1; 5338 vars->duplex = DUPLEX_FULL; 5339 switch (vars->link_status & 5340 LINK_STATUS_SPEED_AND_DUPLEX_MASK) { 5341 case ELINK_LINK_10THD: 5342 vars->duplex = DUPLEX_HALF; 5343 /* Fall thru */ 5344 case ELINK_LINK_10TFD: 5345 vars->line_speed = ELINK_SPEED_10; 5346 break; 5347 5348 case ELINK_LINK_100TXHD: 5349 vars->duplex = DUPLEX_HALF; 5350 /* Fall thru */ 5351 case ELINK_LINK_100T4: 5352 case ELINK_LINK_100TXFD: 5353 vars->line_speed = ELINK_SPEED_100; 5354 break; 5355 5356 case ELINK_LINK_1000THD: 5357 vars->duplex = DUPLEX_HALF; 5358 /* Fall thru */ 5359 case ELINK_LINK_1000TFD: 5360 vars->line_speed = ELINK_SPEED_1000; 5361 break; 5362 5363 case ELINK_LINK_2500THD: 5364 vars->duplex = DUPLEX_HALF; 5365 /* Fall thru */ 5366 case ELINK_LINK_2500TFD: 5367 vars->line_speed = ELINK_SPEED_2500; 5368 break; 5369 5370 case ELINK_LINK_10GTFD: 5371 vars->line_speed = ELINK_SPEED_10000; 5372 break; 5373 case ELINK_LINK_20GTFD: 5374 vars->line_speed = ELINK_SPEED_20000; 5375 break; 5376 default: 5377 break; 5378 } 5379 vars->flow_ctrl = 0; 5380 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) 5381 vars->flow_ctrl |= ELINK_FLOW_CTRL_TX; 5382 5383 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) 5384 vars->flow_ctrl |= ELINK_FLOW_CTRL_RX; 5385 5386 if (!vars->flow_ctrl) 5387 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 5388 5389 if (vars->line_speed && 5390 ((vars->line_speed == ELINK_SPEED_10) || 5391 (vars->line_speed == ELINK_SPEED_100))) { 5392 vars->phy_flags |= PHY_SGMII_FLAG; 5393 } else { 5394 vars->phy_flags &= ~PHY_SGMII_FLAG; 5395 } 5396 #ifndef EXCLUDE_WARPCORE 5397 if (vars->line_speed && 5398 ELINK_USES_WARPCORE(params->chip_id) && 5399 (vars->line_speed == ELINK_SPEED_1000)) 5400 vars->phy_flags |= PHY_SGMII_FLAG; 5401 #endif /* #ifndef EXCLUDE_WARPCORE */ 5402 /* Anything 10 and over uses the bmac */ 5403 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000); 5404 5405 if (link_10g_plus) { 5406 if (ELINK_USES_WARPCORE(params->chip_id)) 5407 vars->mac_type = ELINK_MAC_TYPE_XMAC; 5408 else 5409 vars->mac_type = ELINK_MAC_TYPE_BMAC; 5410 } else { 5411 if (ELINK_USES_WARPCORE(params->chip_id)) 5412 vars->mac_type = ELINK_MAC_TYPE_UMAC; 5413 else 5414 vars->mac_type = ELINK_MAC_TYPE_EMAC; 5415 } 5416 } else { /* Link down */ 5417 ELINK_DEBUG_P0(cb, "phy link down\n"); 5418 5419 vars->phy_link_up = 0; 5420 5421 vars->line_speed = 0; 5422 vars->duplex = DUPLEX_FULL; 5423 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 5424 5425 /* Indicate no mac active */ 5426 vars->mac_type = ELINK_MAC_TYPE_NONE; 5427 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 5428 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 5429 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) 5430 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; 5431 } 5432 } 5433 5434 void elink_link_status_update(struct elink_params *params, 5435 struct elink_vars *vars) 5436 { 5437 struct elink_dev *cb = params->cb; 5438 u8 port = params->port; 5439 u32 sync_offset, media_types; 5440 /* Update PHY configuration */ 5441 set_phy_vars(params, vars); 5442 5443 vars->link_status = REG_RD(cb, params->shmem_base + 5444 OFFSETOF(struct shmem_region, 5445 port_mb[port].link_status)); 5446 5447 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */ 5448 if (params->loopback_mode != ELINK_LOOPBACK_NONE && 5449 params->loopback_mode != ELINK_LOOPBACK_EXT) 5450 vars->link_status |= LINK_STATUS_LINK_UP; 5451 5452 #ifndef EXCLUDE_NON_COMMON_INIT 5453 #ifndef EXCLUDE_WARPCORE 5454 if (elink_eee_has_cap(params)) 5455 vars->eee_status = REG_RD(cb, params->shmem2_base + 5456 OFFSETOF(struct shmem2_region, 5457 eee_status[params->port])); 5458 #endif 5459 #endif 5460 5461 vars->phy_flags = PHY_XGXS_FLAG; 5462 elink_sync_link(params, vars); 5463 /* Sync media type */ 5464 sync_offset = params->shmem_base + 5465 OFFSETOF(struct shmem_region, 5466 dev_info.port_hw_config[port].media_type); 5467 media_types = REG_RD(cb, sync_offset); 5468 5469 params->phy[ELINK_INT_PHY].media_type = 5470 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> 5471 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; 5472 params->phy[ELINK_EXT_PHY1].media_type = 5473 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> 5474 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; 5475 params->phy[ELINK_EXT_PHY2].media_type = 5476 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> 5477 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; 5478 ELINK_DEBUG_P1(cb, "media_types = 0x%x\n", media_types); 5479 5480 /* Sync AEU offset */ 5481 sync_offset = params->shmem_base + 5482 OFFSETOF(struct shmem_region, 5483 dev_info.port_hw_config[port].aeu_int_mask); 5484 5485 vars->aeu_int_mask = REG_RD(cb, sync_offset); 5486 5487 /* Sync PFC status */ 5488 if (vars->link_status & LINK_STATUS_PFC_ENABLED) 5489 params->feature_config_flags |= 5490 ELINK_FEATURE_CONFIG_PFC_ENABLED; 5491 else 5492 params->feature_config_flags &= 5493 ~ELINK_FEATURE_CONFIG_PFC_ENABLED; 5494 5495 if (SHMEM2_HAS(cb, params->shmem2_base, link_attr_sync)) 5496 params->link_attr_sync = SHMEM2_RD(cb, params->shmem2_base, 5497 link_attr_sync[params->port]); 5498 5499 ELINK_DEBUG_P3(cb, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", 5500 vars->link_status, vars->phy_link_up, vars->aeu_int_mask); 5501 ELINK_DEBUG_P3(cb, "line_speed %x duplex %x flow_ctrl 0x%x\n", 5502 vars->line_speed, vars->duplex, vars->flow_ctrl); 5503 } 5504 5505 #ifndef EXCLUDE_NON_COMMON_INIT 5506 #ifndef EXCLUDE_XGXS 5507 static void elink_set_master_ln(struct elink_params *params, 5508 struct elink_phy *phy) 5509 { 5510 struct elink_dev *cb = params->cb; 5511 u16 new_master_ln, ser_lane; 5512 ser_lane = ((params->lane_config & 5513 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 5514 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 5515 5516 /* Set the master_ln for AN */ 5517 CL22_RD_OVER_CL45(cb, phy, 5518 MDIO_REG_BANK_XGXS_BLOCK2, 5519 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 5520 &new_master_ln); 5521 5522 CL22_WR_OVER_CL45(cb, phy, 5523 MDIO_REG_BANK_XGXS_BLOCK2 , 5524 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 5525 (new_master_ln | ser_lane)); 5526 } 5527 5528 static elink_status_t elink_reset_unicore(struct elink_params *params, 5529 struct elink_phy *phy, 5530 u8 set_serdes) 5531 { 5532 struct elink_dev *cb = params->cb; 5533 u16 mii_control; 5534 u16 i; 5535 CL22_RD_OVER_CL45(cb, phy, 5536 MDIO_REG_BANK_COMBO_IEEE0, 5537 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); 5538 5539 /* Reset the unicore */ 5540 CL22_WR_OVER_CL45(cb, phy, 5541 MDIO_REG_BANK_COMBO_IEEE0, 5542 MDIO_COMBO_IEEE0_MII_CONTROL, 5543 (mii_control | 5544 MDIO_COMBO_IEEO_MII_CONTROL_RESET)); 5545 #ifndef EXCLUDE_SERDES 5546 if (set_serdes) 5547 elink_set_serdes_access(cb, params->port); 5548 #endif /* EXCLUDE_SERDES */ 5549 5550 /* Wait for the reset to self clear */ 5551 for (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) { 5552 USLEEP(cb, 5); 5553 5554 /* The reset erased the previous bank value */ 5555 CL22_RD_OVER_CL45(cb, phy, 5556 MDIO_REG_BANK_COMBO_IEEE0, 5557 MDIO_COMBO_IEEE0_MII_CONTROL, 5558 &mii_control); 5559 5560 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { 5561 USLEEP(cb, 5); 5562 return ELINK_STATUS_OK; 5563 } 5564 } 5565 5566 elink_cb_event_log(cb, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized," 5567 // " Port %d\n", 5568 5569 ELINK_DEBUG_P0(cb, "BUG! XGXS is still in reset!\n"); 5570 return ELINK_STATUS_ERROR; 5571 5572 } 5573 5574 static void elink_set_swap_lanes(struct elink_params *params, 5575 struct elink_phy *phy) 5576 { 5577 struct elink_dev *cb = params->cb; 5578 /* Each two bits represents a lane number: 5579 * No swap is 0123 => 0x1b no need to enable the swap 5580 */ 5581 u16 rx_lane_swap, tx_lane_swap; 5582 5583 rx_lane_swap = ((params->lane_config & 5584 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> 5585 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); 5586 tx_lane_swap = ((params->lane_config & 5587 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> 5588 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); 5589 5590 if (rx_lane_swap != 0x1b) { 5591 CL22_WR_OVER_CL45(cb, phy, 5592 MDIO_REG_BANK_XGXS_BLOCK2, 5593 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 5594 (rx_lane_swap | 5595 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | 5596 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); 5597 } else { 5598 CL22_WR_OVER_CL45(cb, phy, 5599 MDIO_REG_BANK_XGXS_BLOCK2, 5600 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); 5601 } 5602 5603 if (tx_lane_swap != 0x1b) { 5604 CL22_WR_OVER_CL45(cb, phy, 5605 MDIO_REG_BANK_XGXS_BLOCK2, 5606 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 5607 (tx_lane_swap | 5608 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); 5609 } else { 5610 CL22_WR_OVER_CL45(cb, phy, 5611 MDIO_REG_BANK_XGXS_BLOCK2, 5612 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); 5613 } 5614 } 5615 5616 static void elink_set_parallel_detection(struct elink_phy *phy, 5617 struct elink_params *params) 5618 { 5619 struct elink_dev *cb = params->cb; 5620 u16 control2; 5621 CL22_RD_OVER_CL45(cb, phy, 5622 MDIO_REG_BANK_SERDES_DIGITAL, 5623 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 5624 &control2); 5625 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 5626 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 5627 else 5628 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 5629 ELINK_DEBUG_P2(cb, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", 5630 phy->speed_cap_mask, control2); 5631 CL22_WR_OVER_CL45(cb, phy, 5632 MDIO_REG_BANK_SERDES_DIGITAL, 5633 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 5634 control2); 5635 5636 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 5637 (phy->speed_cap_mask & 5638 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 5639 ELINK_DEBUG_P0(cb, "XGXS\n"); 5640 5641 CL22_WR_OVER_CL45(cb, phy, 5642 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5643 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, 5644 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); 5645 5646 CL22_RD_OVER_CL45(cb, phy, 5647 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5648 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 5649 &control2); 5650 5651 5652 control2 |= 5653 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; 5654 5655 CL22_WR_OVER_CL45(cb, phy, 5656 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5657 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 5658 control2); 5659 5660 /* Disable parallel detection of HiG */ 5661 CL22_WR_OVER_CL45(cb, phy, 5662 MDIO_REG_BANK_XGXS_BLOCK2, 5663 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, 5664 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | 5665 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); 5666 } 5667 } 5668 5669 static void elink_set_autoneg(struct elink_phy *phy, 5670 struct elink_params *params, 5671 struct elink_vars *vars, 5672 u8 enable_cl73) 5673 { 5674 struct elink_dev *cb = params->cb; 5675 u16 reg_val; 5676 5677 /* CL37 Autoneg */ 5678 CL22_RD_OVER_CL45(cb, phy, 5679 MDIO_REG_BANK_COMBO_IEEE0, 5680 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 5681 5682 /* CL37 Autoneg Enabled */ 5683 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) 5684 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; 5685 else /* CL37 Autoneg Disabled */ 5686 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5687 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); 5688 5689 CL22_WR_OVER_CL45(cb, phy, 5690 MDIO_REG_BANK_COMBO_IEEE0, 5691 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5692 5693 /* Enable/Disable Autodetection */ 5694 5695 CL22_RD_OVER_CL45(cb, phy, 5696 MDIO_REG_BANK_SERDES_DIGITAL, 5697 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); 5698 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | 5699 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); 5700 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; 5701 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) 5702 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5703 else 5704 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5705 5706 CL22_WR_OVER_CL45(cb, phy, 5707 MDIO_REG_BANK_SERDES_DIGITAL, 5708 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); 5709 5710 /* Enable TetonII and BAM autoneg */ 5711 CL22_RD_OVER_CL45(cb, phy, 5712 MDIO_REG_BANK_BAM_NEXT_PAGE, 5713 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5714 ®_val); 5715 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) { 5716 /* Enable BAM aneg Mode and TetonII aneg Mode */ 5717 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5718 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5719 } else { 5720 /* TetonII and BAM Autoneg Disabled */ 5721 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5722 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5723 } 5724 CL22_WR_OVER_CL45(cb, phy, 5725 MDIO_REG_BANK_BAM_NEXT_PAGE, 5726 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5727 reg_val); 5728 5729 if (enable_cl73) { 5730 /* Enable Cl73 FSM status bits */ 5731 CL22_WR_OVER_CL45(cb, phy, 5732 MDIO_REG_BANK_CL73_USERB0, 5733 MDIO_CL73_USERB0_CL73_UCTRL, 5734 0xe); 5735 5736 /* Enable BAM Station Manager*/ 5737 CL22_WR_OVER_CL45(cb, phy, 5738 MDIO_REG_BANK_CL73_USERB0, 5739 MDIO_CL73_USERB0_CL73_BAM_CTRL1, 5740 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | 5741 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | 5742 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); 5743 5744 /* Advertise CL73 link speeds */ 5745 CL22_RD_OVER_CL45(cb, phy, 5746 MDIO_REG_BANK_CL73_IEEEB1, 5747 MDIO_CL73_IEEEB1_AN_ADV2, 5748 ®_val); 5749 if (phy->speed_cap_mask & 5750 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5751 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; 5752 if (phy->speed_cap_mask & 5753 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 5754 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; 5755 5756 CL22_WR_OVER_CL45(cb, phy, 5757 MDIO_REG_BANK_CL73_IEEEB1, 5758 MDIO_CL73_IEEEB1_AN_ADV2, 5759 reg_val); 5760 5761 /* CL73 Autoneg Enabled */ 5762 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; 5763 5764 } else /* CL73 Autoneg Disabled */ 5765 reg_val = 0; 5766 5767 CL22_WR_OVER_CL45(cb, phy, 5768 MDIO_REG_BANK_CL73_IEEEB0, 5769 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); 5770 } 5771 5772 /* Program SerDes, forced speed */ 5773 static void elink_program_serdes(struct elink_phy *phy, 5774 struct elink_params *params, 5775 struct elink_vars *vars) 5776 { 5777 struct elink_dev *cb = params->cb; 5778 u16 reg_val; 5779 5780 /* Program duplex, disable autoneg and sgmii*/ 5781 CL22_RD_OVER_CL45(cb, phy, 5782 MDIO_REG_BANK_COMBO_IEEE0, 5783 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 5784 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | 5785 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5786 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); 5787 if (phy->req_duplex == DUPLEX_FULL) 5788 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5789 CL22_WR_OVER_CL45(cb, phy, 5790 MDIO_REG_BANK_COMBO_IEEE0, 5791 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5792 5793 /* Program speed 5794 * - needed only if the speed is greater than 1G (2.5G or 10G) 5795 */ 5796 CL22_RD_OVER_CL45(cb, phy, 5797 MDIO_REG_BANK_SERDES_DIGITAL, 5798 MDIO_SERDES_DIGITAL_MISC1, ®_val); 5799 /* Clearing the speed value before setting the right speed */ 5800 ELINK_DEBUG_P1(cb, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); 5801 5802 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | 5803 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5804 5805 if (!((vars->line_speed == ELINK_SPEED_1000) || 5806 (vars->line_speed == ELINK_SPEED_100) || 5807 (vars->line_speed == ELINK_SPEED_10))) { 5808 5809 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | 5810 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5811 if (vars->line_speed == ELINK_SPEED_10000) 5812 reg_val |= 5813 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; 5814 } 5815 5816 CL22_WR_OVER_CL45(cb, phy, 5817 MDIO_REG_BANK_SERDES_DIGITAL, 5818 MDIO_SERDES_DIGITAL_MISC1, reg_val); 5819 5820 } 5821 5822 static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy, 5823 struct elink_params *params) 5824 { 5825 struct elink_dev *cb = params->cb; 5826 u16 val = 0; 5827 5828 /* Set extended capabilities */ 5829 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) 5830 val |= MDIO_OVER_1G_UP1_2_5G; 5831 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5832 val |= MDIO_OVER_1G_UP1_10G; 5833 CL22_WR_OVER_CL45(cb, phy, 5834 MDIO_REG_BANK_OVER_1G, 5835 MDIO_OVER_1G_UP1, val); 5836 5837 CL22_WR_OVER_CL45(cb, phy, 5838 MDIO_REG_BANK_OVER_1G, 5839 MDIO_OVER_1G_UP3, 0x400); 5840 } 5841 5842 static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy, 5843 struct elink_params *params, 5844 u16 ieee_fc) 5845 { 5846 struct elink_dev *cb = params->cb; 5847 u16 val; 5848 /* For AN, we are always publishing full duplex */ 5849 5850 CL22_WR_OVER_CL45(cb, phy, 5851 MDIO_REG_BANK_COMBO_IEEE0, 5852 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); 5853 CL22_RD_OVER_CL45(cb, phy, 5854 MDIO_REG_BANK_CL73_IEEEB1, 5855 MDIO_CL73_IEEEB1_AN_ADV1, &val); 5856 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; 5857 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); 5858 CL22_WR_OVER_CL45(cb, phy, 5859 MDIO_REG_BANK_CL73_IEEEB1, 5860 MDIO_CL73_IEEEB1_AN_ADV1, val); 5861 } 5862 5863 static void elink_restart_autoneg(struct elink_phy *phy, 5864 struct elink_params *params, 5865 u8 enable_cl73) 5866 { 5867 struct elink_dev *cb = params->cb; 5868 u16 mii_control; 5869 5870 ELINK_DEBUG_P0(cb, "elink_restart_autoneg\n"); 5871 /* Enable and restart BAM/CL37 aneg */ 5872 5873 if (enable_cl73) { 5874 CL22_RD_OVER_CL45(cb, phy, 5875 MDIO_REG_BANK_CL73_IEEEB0, 5876 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5877 &mii_control); 5878 5879 CL22_WR_OVER_CL45(cb, phy, 5880 MDIO_REG_BANK_CL73_IEEEB0, 5881 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5882 (mii_control | 5883 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | 5884 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); 5885 } else { 5886 5887 CL22_RD_OVER_CL45(cb, phy, 5888 MDIO_REG_BANK_COMBO_IEEE0, 5889 MDIO_COMBO_IEEE0_MII_CONTROL, 5890 &mii_control); 5891 ELINK_DEBUG_P1(cb, 5892 "elink_restart_autoneg mii_control before = 0x%x\n", 5893 mii_control); 5894 CL22_WR_OVER_CL45(cb, phy, 5895 MDIO_REG_BANK_COMBO_IEEE0, 5896 MDIO_COMBO_IEEE0_MII_CONTROL, 5897 (mii_control | 5898 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5899 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); 5900 } 5901 } 5902 5903 static void elink_initialize_sgmii_process(struct elink_phy *phy, 5904 struct elink_params *params, 5905 struct elink_vars *vars) 5906 { 5907 struct elink_dev *cb = params->cb; 5908 u16 control1; 5909 5910 /* In SGMII mode, the unicore is always slave */ 5911 5912 CL22_RD_OVER_CL45(cb, phy, 5913 MDIO_REG_BANK_SERDES_DIGITAL, 5914 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5915 &control1); 5916 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; 5917 /* Set sgmii mode (and not fiber) */ 5918 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | 5919 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | 5920 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); 5921 CL22_WR_OVER_CL45(cb, phy, 5922 MDIO_REG_BANK_SERDES_DIGITAL, 5923 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5924 control1); 5925 5926 /* If forced speed */ 5927 if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) { 5928 /* Set speed, disable autoneg */ 5929 u16 mii_control; 5930 5931 CL22_RD_OVER_CL45(cb, phy, 5932 MDIO_REG_BANK_COMBO_IEEE0, 5933 MDIO_COMBO_IEEE0_MII_CONTROL, 5934 &mii_control); 5935 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5936 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| 5937 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); 5938 5939 switch (vars->line_speed) { 5940 case ELINK_SPEED_100: 5941 mii_control |= 5942 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; 5943 break; 5944 case ELINK_SPEED_1000: 5945 mii_control |= 5946 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; 5947 break; 5948 case ELINK_SPEED_10: 5949 /* There is nothing to set for 10M */ 5950 break; 5951 default: 5952 /* Invalid speed for SGMII */ 5953 ELINK_DEBUG_P1(cb, "Invalid line_speed 0x%x\n", 5954 vars->line_speed); 5955 break; 5956 } 5957 5958 /* Setting the full duplex */ 5959 if (phy->req_duplex == DUPLEX_FULL) 5960 mii_control |= 5961 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5962 CL22_WR_OVER_CL45(cb, phy, 5963 MDIO_REG_BANK_COMBO_IEEE0, 5964 MDIO_COMBO_IEEE0_MII_CONTROL, 5965 mii_control); 5966 5967 } else { /* AN mode */ 5968 /* Enable and restart AN */ 5969 elink_restart_autoneg(phy, params, 0); 5970 } 5971 } 5972 5973 /* Link management 5974 */ 5975 static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy, 5976 struct elink_params *params) 5977 { 5978 struct elink_dev *cb = params->cb; 5979 u16 pd_10g, status2_1000x; 5980 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) 5981 return ELINK_STATUS_OK; 5982 CL22_RD_OVER_CL45(cb, phy, 5983 MDIO_REG_BANK_SERDES_DIGITAL, 5984 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5985 &status2_1000x); 5986 CL22_RD_OVER_CL45(cb, phy, 5987 MDIO_REG_BANK_SERDES_DIGITAL, 5988 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5989 &status2_1000x); 5990 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { 5991 ELINK_DEBUG_P1(cb, "1G parallel detect link on port %d\n", 5992 params->port); 5993 return 1; 5994 } 5995 5996 CL22_RD_OVER_CL45(cb, phy, 5997 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5998 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, 5999 &pd_10g); 6000 6001 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { 6002 ELINK_DEBUG_P1(cb, "10G parallel detect link on port %d\n", 6003 params->port); 6004 return 1; 6005 } 6006 return ELINK_STATUS_OK; 6007 } 6008 6009 static void elink_update_adv_fc(struct elink_phy *phy, 6010 struct elink_params *params, 6011 struct elink_vars *vars, 6012 u32 gp_status) 6013 { 6014 u16 ld_pause; /* local driver */ 6015 u16 lp_pause; /* link partner */ 6016 u16 pause_result; 6017 struct elink_dev *cb = params->cb; 6018 if ((gp_status & 6019 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 6020 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == 6021 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 6022 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { 6023 6024 CL22_RD_OVER_CL45(cb, phy, 6025 MDIO_REG_BANK_CL73_IEEEB1, 6026 MDIO_CL73_IEEEB1_AN_ADV1, 6027 &ld_pause); 6028 CL22_RD_OVER_CL45(cb, phy, 6029 MDIO_REG_BANK_CL73_IEEEB1, 6030 MDIO_CL73_IEEEB1_AN_LP_ADV1, 6031 &lp_pause); 6032 pause_result = (ld_pause & 6033 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; 6034 pause_result |= (lp_pause & 6035 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; 6036 ELINK_DEBUG_P1(cb, "pause_result CL73 0x%x\n", pause_result); 6037 } else { 6038 CL22_RD_OVER_CL45(cb, phy, 6039 MDIO_REG_BANK_COMBO_IEEE0, 6040 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, 6041 &ld_pause); 6042 CL22_RD_OVER_CL45(cb, phy, 6043 MDIO_REG_BANK_COMBO_IEEE0, 6044 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, 6045 &lp_pause); 6046 pause_result = (ld_pause & 6047 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; 6048 pause_result |= (lp_pause & 6049 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; 6050 ELINK_DEBUG_P1(cb, "pause_result CL37 0x%x\n", pause_result); 6051 } 6052 elink_pause_resolve(vars, pause_result); 6053 6054 } 6055 6056 static void elink_flow_ctrl_resolve(struct elink_phy *phy, 6057 struct elink_params *params, 6058 struct elink_vars *vars, 6059 u32 gp_status) 6060 { 6061 #ifdef ELINK_DEBUG 6062 struct elink_dev *cb = params->cb; 6063 #endif 6064 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 6065 6066 /* Resolve from gp_status in case of AN complete and not sgmii */ 6067 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) { 6068 /* Update the advertised flow-controled of LD/LP in AN */ 6069 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) 6070 elink_update_adv_fc(phy, params, vars, gp_status); 6071 /* But set the flow-control result as the requested one */ 6072 vars->flow_ctrl = phy->req_flow_ctrl; 6073 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) 6074 vars->flow_ctrl = params->req_fc_auto_adv; 6075 else if ((gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) && 6076 (!(vars->phy_flags & PHY_SGMII_FLAG))) { 6077 if (elink_direct_parallel_detect_used(phy, params)) { 6078 vars->flow_ctrl = params->req_fc_auto_adv; 6079 return; 6080 } 6081 elink_update_adv_fc(phy, params, vars, gp_status); 6082 } 6083 ELINK_DEBUG_P1(cb, "flow_ctrl 0x%x\n", vars->flow_ctrl); 6084 } 6085 6086 static void elink_check_fallback_to_cl37(struct elink_phy *phy, 6087 struct elink_params *params) 6088 { 6089 struct elink_dev *cb = params->cb; 6090 u16 rx_status, ustat_val, cl37_fsm_received; 6091 ELINK_DEBUG_P0(cb, "elink_check_fallback_to_cl37\n"); 6092 /* Step 1: Make sure signal is detected */ 6093 CL22_RD_OVER_CL45(cb, phy, 6094 MDIO_REG_BANK_RX0, 6095 MDIO_RX0_RX_STATUS, 6096 &rx_status); 6097 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != 6098 (MDIO_RX0_RX_STATUS_SIGDET)) { 6099 ELINK_DEBUG_P1(cb, "Signal is not detected. Restoring CL73." 6100 "rx_status(0x80b0) = 0x%x\n", rx_status); 6101 CL22_WR_OVER_CL45(cb, phy, 6102 MDIO_REG_BANK_CL73_IEEEB0, 6103 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 6104 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); 6105 return; 6106 } 6107 /* Step 2: Check CL73 state machine */ 6108 CL22_RD_OVER_CL45(cb, phy, 6109 MDIO_REG_BANK_CL73_USERB0, 6110 MDIO_CL73_USERB0_CL73_USTAT1, 6111 &ustat_val); 6112 if ((ustat_val & 6113 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 6114 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != 6115 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 6116 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { 6117 ELINK_DEBUG_P1(cb, "CL73 state-machine is not stable. " 6118 "ustat_val(0x8371) = 0x%x\n", ustat_val); 6119 return; 6120 } 6121 /* Step 3: Check CL37 Message Pages received to indicate LP 6122 * supports only CL37 6123 */ 6124 CL22_RD_OVER_CL45(cb, phy, 6125 MDIO_REG_BANK_REMOTE_PHY, 6126 MDIO_REMOTE_PHY_MISC_RX_STATUS, 6127 &cl37_fsm_received); 6128 if ((cl37_fsm_received & 6129 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 6130 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != 6131 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 6132 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { 6133 ELINK_DEBUG_P1(cb, "No CL37 FSM were received. " 6134 "misc_rx_status(0x8330) = 0x%x\n", 6135 cl37_fsm_received); 6136 return; 6137 } 6138 /* The combined cl37/cl73 fsm state information indicating that 6139 * we are connected to a device which does not support cl73, but 6140 * does support cl37 BAM. In this case we disable cl73 and 6141 * restart cl37 auto-neg 6142 */ 6143 6144 /* Disable CL73 */ 6145 CL22_WR_OVER_CL45(cb, phy, 6146 MDIO_REG_BANK_CL73_IEEEB0, 6147 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 6148 0); 6149 /* Restart CL37 autoneg */ 6150 elink_restart_autoneg(phy, params, 0); 6151 ELINK_DEBUG_P0(cb, "Disabling CL73, and restarting CL37 autoneg\n"); 6152 } 6153 6154 static void elink_xgxs_an_resolve(struct elink_phy *phy, 6155 struct elink_params *params, 6156 struct elink_vars *vars, 6157 u32 gp_status) 6158 { 6159 if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) 6160 vars->link_status |= 6161 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 6162 6163 if (elink_direct_parallel_detect_used(phy, params)) 6164 vars->link_status |= 6165 LINK_STATUS_PARALLEL_DETECTION_USED; 6166 } 6167 #endif /* EXCLUDE_XGXS */ 6168 static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy, 6169 struct elink_params *params, 6170 struct elink_vars *vars, 6171 u16 is_link_up, 6172 u16 speed_mask, 6173 u16 is_duplex) 6174 { 6175 #ifdef ELINK_DEBUG 6176 struct elink_dev *cb = params->cb; 6177 #endif 6178 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) 6179 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 6180 if (is_link_up) { 6181 ELINK_DEBUG_P0(cb, "phy link up\n"); 6182 6183 vars->phy_link_up = 1; 6184 vars->link_status |= LINK_STATUS_LINK_UP; 6185 6186 switch (speed_mask) { 6187 case ELINK_GP_STATUS_10M: 6188 vars->line_speed = ELINK_SPEED_10; 6189 if (is_duplex == DUPLEX_FULL) 6190 vars->link_status |= ELINK_LINK_10TFD; 6191 else 6192 vars->link_status |= ELINK_LINK_10THD; 6193 break; 6194 6195 case ELINK_GP_STATUS_100M: 6196 vars->line_speed = ELINK_SPEED_100; 6197 if (is_duplex == DUPLEX_FULL) 6198 vars->link_status |= ELINK_LINK_100TXFD; 6199 else 6200 vars->link_status |= ELINK_LINK_100TXHD; 6201 break; 6202 6203 case ELINK_GP_STATUS_1G: 6204 case ELINK_GP_STATUS_1G_KX: 6205 vars->line_speed = ELINK_SPEED_1000; 6206 if (is_duplex == DUPLEX_FULL) 6207 vars->link_status |= ELINK_LINK_1000TFD; 6208 else 6209 vars->link_status |= ELINK_LINK_1000THD; 6210 break; 6211 6212 case ELINK_GP_STATUS_2_5G: 6213 vars->line_speed = ELINK_SPEED_2500; 6214 if (is_duplex == DUPLEX_FULL) 6215 vars->link_status |= ELINK_LINK_2500TFD; 6216 else 6217 vars->link_status |= ELINK_LINK_2500THD; 6218 break; 6219 6220 case ELINK_GP_STATUS_5G: 6221 case ELINK_GP_STATUS_6G: 6222 ELINK_DEBUG_P1(cb, 6223 "link speed unsupported gp_status 0x%x\n", 6224 speed_mask); 6225 return ELINK_STATUS_ERROR; 6226 6227 case ELINK_GP_STATUS_10G_KX4: 6228 case ELINK_GP_STATUS_10G_HIG: 6229 case ELINK_GP_STATUS_10G_CX4: 6230 case ELINK_GP_STATUS_10G_KR: 6231 case ELINK_GP_STATUS_10G_SFI: 6232 case ELINK_GP_STATUS_10G_XFI: 6233 vars->line_speed = ELINK_SPEED_10000; 6234 vars->link_status |= ELINK_LINK_10GTFD; 6235 break; 6236 case ELINK_GP_STATUS_20G_DXGXS: 6237 case ELINK_GP_STATUS_20G_KR2: 6238 vars->line_speed = ELINK_SPEED_20000; 6239 vars->link_status |= ELINK_LINK_20GTFD; 6240 break; 6241 default: 6242 ELINK_DEBUG_P1(cb, 6243 "link speed unsupported gp_status 0x%x\n", 6244 speed_mask); 6245 return ELINK_STATUS_ERROR; 6246 } 6247 } else { /* link_down */ 6248 ELINK_DEBUG_P0(cb, "phy link down\n"); 6249 6250 vars->phy_link_up = 0; 6251 6252 vars->duplex = DUPLEX_FULL; 6253 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 6254 vars->mac_type = ELINK_MAC_TYPE_NONE; 6255 } 6256 ELINK_DEBUG_P2(cb, " phy_link_up %x line_speed %d\n", 6257 vars->phy_link_up, vars->line_speed); 6258 return ELINK_STATUS_OK; 6259 } 6260 6261 #ifndef EXCLUDE_XGXS 6262 static elink_status_t 6263 elink_link_settings_status(struct elink_phy *phy, struct elink_params *params, 6264 struct elink_vars *vars) 6265 { 6266 struct elink_dev *cb = params->cb; 6267 6268 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; 6269 elink_status_t rc = ELINK_STATUS_OK; 6270 6271 /* Read gp_status */ 6272 CL22_RD_OVER_CL45(cb, phy, 6273 MDIO_REG_BANK_GP_STATUS, 6274 MDIO_GP_STATUS_TOP_AN_STATUS1, 6275 &gp_status); 6276 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) 6277 duplex = DUPLEX_FULL; 6278 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) 6279 link_up = 1; 6280 speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK; 6281 ELINK_DEBUG_P3(cb, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", 6282 gp_status, link_up, speed_mask); 6283 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, 6284 duplex); 6285 if (rc == ELINK_STATUS_ERROR) 6286 return rc; 6287 6288 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { 6289 if (ELINK_SINGLE_MEDIA_DIRECT(params)) { 6290 vars->duplex = duplex; 6291 elink_flow_ctrl_resolve(phy, params, vars, gp_status); 6292 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) 6293 elink_xgxs_an_resolve(phy, params, vars, 6294 gp_status); 6295 } 6296 } else { /* Link_down */ 6297 if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 6298 ELINK_SINGLE_MEDIA_DIRECT(params)) { 6299 /* Check signal is detected */ 6300 elink_check_fallback_to_cl37(phy, params); 6301 } 6302 } 6303 6304 /* Read LP advertised speeds*/ 6305 if (ELINK_SINGLE_MEDIA_DIRECT(params) && 6306 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { 6307 u16 val; 6308 6309 CL22_RD_OVER_CL45(cb, phy, MDIO_REG_BANK_CL73_IEEEB1, 6310 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); 6311 6312 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 6313 vars->link_status |= 6314 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 6315 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 6316 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 6317 vars->link_status |= 6318 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 6319 6320 CL22_RD_OVER_CL45(cb, phy, MDIO_REG_BANK_OVER_1G, 6321 MDIO_OVER_1G_LP_UP1, &val); 6322 6323 if (val & MDIO_OVER_1G_UP1_2_5G) 6324 vars->link_status |= 6325 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 6326 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 6327 vars->link_status |= 6328 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 6329 } 6330 6331 ELINK_DEBUG_P3(cb, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 6332 vars->duplex, vars->flow_ctrl, vars->link_status); 6333 return rc; 6334 } 6335 #endif // EXCLUDE_XGXS 6336 6337 #ifndef EXCLUDE_WARPCORE 6338 static elink_status_t 6339 elink_warpcore_read_status(struct elink_phy *phy, struct elink_params *params, 6340 struct elink_vars *vars) 6341 { 6342 struct elink_dev *cb = params->cb; 6343 u8 lane; 6344 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; 6345 elink_status_t rc = ELINK_STATUS_OK; 6346 lane = elink_get_warpcore_lane(phy, params); 6347 /* Read gp_status */ 6348 if ((params->loopback_mode) && 6349 (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) { 6350 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6351 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 6352 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6353 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 6354 link_up &= 0x1; 6355 } else if ((phy->req_line_speed > ELINK_SPEED_10000) && 6356 (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) { 6357 u16 temp_link_up; 6358 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6359 1, &temp_link_up); 6360 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6361 1, &link_up); 6362 ELINK_DEBUG_P2(cb, "PCS RX link status = 0x%x-->0x%x\n", 6363 temp_link_up, link_up); 6364 link_up &= (1<<2); 6365 if (link_up) 6366 elink_ext_phy_resolve_fc(phy, params, vars); 6367 } else { 6368 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6369 MDIO_WC_REG_GP2_STATUS_GP_2_1, 6370 &gp_status1); 6371 ELINK_DEBUG_P1(cb, "0x81d1 = 0x%x\n", gp_status1); 6372 /* Check for either KR, 1G, or AN up. */ 6373 link_up = ((gp_status1 >> 8) | 6374 (gp_status1 >> 12) | 6375 (gp_status1)) & 6376 (1 << lane); 6377 if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) { 6378 u16 an_link; 6379 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 6380 MDIO_AN_REG_STATUS, &an_link); 6381 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 6382 MDIO_AN_REG_STATUS, &an_link); 6383 link_up |= (an_link & (1<<2)); 6384 } 6385 if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) { 6386 u16 pd, gp_status4; 6387 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { 6388 /* Check Autoneg complete */ 6389 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6390 MDIO_WC_REG_GP2_STATUS_GP_2_4, 6391 &gp_status4); 6392 if (gp_status4 & ((1<<12)<<lane)) 6393 vars->link_status |= 6394 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 6395 6396 /* Check parallel detect used */ 6397 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6398 MDIO_WC_REG_PAR_DET_10G_STATUS, 6399 &pd); 6400 if (pd & (1<<15)) 6401 vars->link_status |= 6402 LINK_STATUS_PARALLEL_DETECTION_USED; 6403 } 6404 elink_ext_phy_resolve_fc(phy, params, vars); 6405 vars->duplex = duplex; 6406 } 6407 } 6408 6409 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && 6410 ELINK_SINGLE_MEDIA_DIRECT(params)) { 6411 u16 val; 6412 6413 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 6414 MDIO_AN_REG_LP_AUTO_NEG2, &val); 6415 6416 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 6417 vars->link_status |= 6418 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 6419 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 6420 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 6421 vars->link_status |= 6422 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 6423 6424 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6425 MDIO_WC_REG_DIGITAL3_LP_UP1, &val); 6426 6427 if (val & MDIO_OVER_1G_UP1_2_5G) 6428 vars->link_status |= 6429 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 6430 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 6431 vars->link_status |= 6432 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 6433 6434 } 6435 6436 6437 if (lane < 2) { 6438 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6439 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); 6440 } else { 6441 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6442 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); 6443 } 6444 ELINK_DEBUG_P2(cb, "lane %d gp_speed 0x%x\n", lane, gp_speed); 6445 6446 if ((lane & 1) == 0) 6447 gp_speed <<= 8; 6448 gp_speed &= 0x3f00; 6449 link_up = !!link_up; 6450 6451 /* Reset the TX FIFO to fix SGMII issue */ 6452 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, 6453 duplex); 6454 6455 /* In case of KR link down, start up the recovering procedure */ 6456 if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) && 6457 (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE))) 6458 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 6459 6460 ELINK_DEBUG_P3(cb, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 6461 vars->duplex, vars->flow_ctrl, vars->link_status); 6462 return rc; 6463 } 6464 #endif /* #ifndef EXCLUDE_WARPCORE */ 6465 #ifndef EXCLUDE_XGXS 6466 static void elink_set_gmii_tx_driver(struct elink_params *params) 6467 { 6468 struct elink_dev *cb = params->cb; 6469 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; 6470 u16 lp_up2; 6471 u16 tx_driver; 6472 u16 bank; 6473 6474 /* Read precomp */ 6475 CL22_RD_OVER_CL45(cb, phy, 6476 MDIO_REG_BANK_OVER_1G, 6477 MDIO_OVER_1G_LP_UP2, &lp_up2); 6478 6479 /* Bits [10:7] at lp_up2, positioned at [15:12] */ 6480 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> 6481 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << 6482 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); 6483 6484 if (lp_up2 == 0) 6485 return; 6486 6487 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; 6488 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { 6489 CL22_RD_OVER_CL45(cb, phy, 6490 bank, 6491 MDIO_TX0_TX_DRIVER, &tx_driver); 6492 6493 /* Replace tx_driver bits [15:12] */ 6494 if (lp_up2 != 6495 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { 6496 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; 6497 tx_driver |= lp_up2; 6498 CL22_WR_OVER_CL45(cb, phy, 6499 bank, 6500 MDIO_TX0_TX_DRIVER, tx_driver); 6501 } 6502 } 6503 } 6504 6505 static elink_status_t elink_emac_program(struct elink_params *params, 6506 struct elink_vars *vars) 6507 { 6508 struct elink_dev *cb = params->cb; 6509 u8 port = params->port; 6510 u16 mode = 0; 6511 6512 ELINK_DEBUG_P0(cb, "setting link speed & duplex\n"); 6513 elink_bits_dis(cb, GRCBASE_EMAC0 + port*0x400 + 6514 EMAC_REG_EMAC_MODE, 6515 (EMAC_MODE_25G_MODE | 6516 EMAC_MODE_PORT_MII_10M | 6517 EMAC_MODE_HALF_DUPLEX)); 6518 switch (vars->line_speed) { 6519 case ELINK_SPEED_10: 6520 mode |= EMAC_MODE_PORT_MII_10M; 6521 break; 6522 6523 case ELINK_SPEED_100: 6524 mode |= EMAC_MODE_PORT_MII; 6525 break; 6526 6527 case ELINK_SPEED_1000: 6528 mode |= EMAC_MODE_PORT_GMII; 6529 break; 6530 6531 case ELINK_SPEED_2500: 6532 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); 6533 break; 6534 6535 default: 6536 /* 10G not valid for EMAC */ 6537 ELINK_DEBUG_P1(cb, "Invalid line_speed 0x%x\n", 6538 vars->line_speed); 6539 return ELINK_STATUS_ERROR; 6540 } 6541 6542 if (vars->duplex == DUPLEX_HALF) 6543 mode |= EMAC_MODE_HALF_DUPLEX; 6544 elink_bits_en(cb, 6545 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, 6546 mode); 6547 6548 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed); 6549 return ELINK_STATUS_OK; 6550 } 6551 6552 static void elink_set_preemphasis(struct elink_phy *phy, 6553 struct elink_params *params) 6554 { 6555 6556 u16 bank, i = 0; 6557 struct elink_dev *cb = params->cb; 6558 6559 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; 6560 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { 6561 CL22_WR_OVER_CL45(cb, phy, 6562 bank, 6563 MDIO_RX0_RX_EQ_BOOST, 6564 phy->rx_preemphasis[i]); 6565 } 6566 6567 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; 6568 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { 6569 CL22_WR_OVER_CL45(cb, phy, 6570 bank, 6571 MDIO_TX0_TX_DRIVER, 6572 phy->tx_preemphasis[i]); 6573 } 6574 } 6575 6576 static elink_status_t 6577 elink_xgxs_config_init(struct elink_phy *phy, struct elink_params *params, 6578 struct elink_vars *vars) 6579 { 6580 #ifdef ELINK_DEBUG 6581 struct elink_dev *cb = params->cb; 6582 #endif 6583 u8 enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) || 6584 (params->loopback_mode == ELINK_LOOPBACK_XGXS)); 6585 if (!(vars->phy_flags & PHY_SGMII_FLAG)) { 6586 if (ELINK_SINGLE_MEDIA_DIRECT(params) && 6587 (params->feature_config_flags & 6588 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) 6589 elink_set_preemphasis(phy, params); 6590 6591 /* Forced speed requested? */ 6592 if (vars->line_speed != ELINK_SPEED_AUTO_NEG || 6593 (ELINK_SINGLE_MEDIA_DIRECT(params) && 6594 params->loopback_mode == ELINK_LOOPBACK_EXT)) { 6595 ELINK_DEBUG_P0(cb, "not SGMII, no AN\n"); 6596 6597 /* Disable autoneg */ 6598 elink_set_autoneg(phy, params, vars, 0); 6599 6600 /* Program speed and duplex */ 6601 elink_program_serdes(phy, params, vars); 6602 6603 } else { /* AN_mode */ 6604 ELINK_DEBUG_P0(cb, "not SGMII, AN\n"); 6605 6606 /* AN enabled */ 6607 elink_set_brcm_cl37_advertisement(phy, params); 6608 6609 /* Program duplex & pause advertisement (for aneg) */ 6610 elink_set_ieee_aneg_advertisement(phy, params, 6611 vars->ieee_fc); 6612 6613 /* Enable autoneg */ 6614 elink_set_autoneg(phy, params, vars, enable_cl73); 6615 6616 /* Enable and restart AN */ 6617 elink_restart_autoneg(phy, params, enable_cl73); 6618 } 6619 6620 } else { /* SGMII mode */ 6621 ELINK_DEBUG_P0(cb, "SGMII\n"); 6622 6623 elink_initialize_sgmii_process(phy, params, vars); 6624 } 6625 return (ELINK_STATUS_OK); 6626 } 6627 6628 static elink_status_t elink_prepare_xgxs(struct elink_phy *phy, 6629 struct elink_params *params, 6630 struct elink_vars *vars) 6631 { 6632 elink_status_t rc; 6633 vars->phy_flags |= PHY_XGXS_FLAG; 6634 if ((phy->req_line_speed && 6635 ((phy->req_line_speed == ELINK_SPEED_100) || 6636 (phy->req_line_speed == ELINK_SPEED_10))) || 6637 (!phy->req_line_speed && 6638 (phy->speed_cap_mask >= 6639 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 6640 (phy->speed_cap_mask < 6641 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 6642 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) 6643 vars->phy_flags |= PHY_SGMII_FLAG; 6644 else 6645 vars->phy_flags &= ~PHY_SGMII_FLAG; 6646 6647 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 6648 elink_set_aer_mmd(params, phy); 6649 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 6650 elink_set_master_ln(params, phy); 6651 6652 rc = elink_reset_unicore(params, phy, 0); 6653 /* Reset the SerDes and wait for reset bit return low */ 6654 if (rc != ELINK_STATUS_OK) 6655 return rc; 6656 6657 elink_set_aer_mmd(params, phy); 6658 /* Setting the masterLn_def again after the reset */ 6659 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { 6660 elink_set_master_ln(params, phy); 6661 elink_set_swap_lanes(params, phy); 6662 } 6663 6664 return rc; 6665 } 6666 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 6667 #endif /* EXCLUDE_XGXS */ 6668 6669 #ifndef EXCLUDE_NON_COMMON_INIT 6670 #ifndef ELINK_EMUL_ONLY 6671 static u16 elink_wait_reset_complete(struct elink_dev *cb, 6672 struct elink_phy *phy, 6673 struct elink_params *params) 6674 { 6675 u16 cnt, ctrl; 6676 /* Wait for soft reset to get cleared up to 1 sec */ 6677 for (cnt = 0; cnt < 1000; cnt++) { 6678 #ifndef EXCLUDE_BCM54618SE 6679 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 6680 elink_cl22_read(cb, phy, 6681 MDIO_PMA_REG_CTRL, &ctrl); 6682 else 6683 #endif 6684 elink_cl45_read(cb, phy, 6685 MDIO_PMA_DEVAD, 6686 MDIO_PMA_REG_CTRL, &ctrl); 6687 if (!(ctrl & (1<<15))) 6688 break; 6689 MSLEEP(cb, 1); 6690 } 6691 6692 if (cnt == 1000) 6693 elink_cb_event_log(cb, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized," 6694 // " Port %d\n", 6695 6696 ELINK_DEBUG_P2(cb, "control reg 0x%x (after %d ms)\n", ctrl, cnt); 6697 return cnt; 6698 } 6699 #endif /* ELINK_EMUL_ONLY */ 6700 6701 static void elink_link_int_enable(struct elink_params *params) 6702 { 6703 u8 port = params->port; 6704 u32 mask; 6705 struct elink_dev *cb = params->cb; 6706 6707 /* Setting the status to report on link up for either XGXS or SerDes */ 6708 if (CHIP_IS_E3(params->chip_id)) { 6709 mask = ELINK_NIG_MASK_XGXS0_LINK_STATUS; 6710 if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) 6711 mask |= ELINK_NIG_MASK_MI_INT; 6712 } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) { 6713 mask = (ELINK_NIG_MASK_XGXS0_LINK10G | 6714 ELINK_NIG_MASK_XGXS0_LINK_STATUS); 6715 ELINK_DEBUG_P0(cb, "enabled XGXS interrupt\n"); 6716 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && 6717 params->phy[ELINK_INT_PHY].type != 6718 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { 6719 mask |= ELINK_NIG_MASK_MI_INT; 6720 ELINK_DEBUG_P0(cb, "enabled external phy int\n"); 6721 } 6722 6723 } else { /* SerDes */ 6724 mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS; 6725 ELINK_DEBUG_P0(cb, "enabled SerDes interrupt\n"); 6726 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && 6727 params->phy[ELINK_INT_PHY].type != 6728 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { 6729 mask |= ELINK_NIG_MASK_MI_INT; 6730 ELINK_DEBUG_P0(cb, "enabled external phy int\n"); 6731 } 6732 } 6733 elink_bits_en(cb, 6734 NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 6735 mask); 6736 6737 ELINK_DEBUG_P3(cb, "port %x, is_xgxs %x, int_status 0x%x\n", port, 6738 (params->switch_cfg == ELINK_SWITCH_CFG_10G), 6739 REG_RD(cb, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 6740 ELINK_DEBUG_P3(cb, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", 6741 REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 6742 REG_RD(cb, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), 6743 REG_RD(cb, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); 6744 ELINK_DEBUG_P2(cb, " 10G %x, XGXS_LINK %x\n", 6745 REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6746 REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6747 } 6748 6749 static void elink_rearm_latch_signal(struct elink_dev *cb, u8 port, 6750 u8 exp_mi_int) 6751 { 6752 u32 latch_status = 0; 6753 6754 /* Disable the MI INT ( external phy int ) by writing 1 to the 6755 * status register. Link down indication is high-active-signal, 6756 * so in this case we need to write the status to clear the XOR 6757 */ 6758 /* Read Latched signals */ 6759 latch_status = REG_RD(cb, 6760 NIG_REG_LATCH_STATUS_0 + port*8); 6761 ELINK_DEBUG_P1(cb, "latch_status = 0x%x\n", latch_status); 6762 /* Handle only those with latched-signal=up.*/ 6763 if (exp_mi_int) 6764 elink_bits_en(cb, 6765 NIG_REG_STATUS_INTERRUPT_PORT0 6766 + port*4, 6767 ELINK_NIG_STATUS_EMAC0_MI_INT); 6768 else 6769 elink_bits_dis(cb, 6770 NIG_REG_STATUS_INTERRUPT_PORT0 6771 + port*4, 6772 ELINK_NIG_STATUS_EMAC0_MI_INT); 6773 6774 if (latch_status & 1) { 6775 6776 /* For all latched-signal=up : Re-Arm Latch signals */ 6777 REG_WR(cb, NIG_REG_LATCH_STATUS_0 + port*8, 6778 (latch_status & 0xfffe) | (latch_status & 1)); 6779 } 6780 /* For all latched-signal=up,Write original_signal to status */ 6781 } 6782 6783 static void elink_link_int_ack(struct elink_params *params, 6784 struct elink_vars *vars, u8 is_10g_plus) 6785 { 6786 struct elink_dev *cb = params->cb; 6787 u8 port = params->port; 6788 u32 mask; 6789 /* First reset all status we assume only one line will be 6790 * change at a time 6791 */ 6792 elink_bits_dis(cb, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6793 (ELINK_NIG_STATUS_XGXS0_LINK10G | 6794 ELINK_NIG_STATUS_XGXS0_LINK_STATUS | 6795 ELINK_NIG_STATUS_SERDES0_LINK_STATUS)); 6796 if (vars->phy_link_up) { 6797 if (ELINK_USES_WARPCORE(params->chip_id)) 6798 mask = ELINK_NIG_STATUS_XGXS0_LINK_STATUS; 6799 else { 6800 if (is_10g_plus) 6801 mask = ELINK_NIG_STATUS_XGXS0_LINK10G; 6802 else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) { 6803 /* Disable the link interrupt by writing 1 to 6804 * the relevant lane in the status register 6805 */ 6806 u32 ser_lane = 6807 ((params->lane_config & 6808 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 6809 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 6810 mask = ((1 << ser_lane) << 6811 ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE); 6812 } else 6813 mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS; 6814 } 6815 ELINK_DEBUG_P1(cb, "Ack link up interrupt with mask 0x%x\n", 6816 mask); 6817 elink_bits_en(cb, 6818 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6819 mask); 6820 } 6821 } 6822 6823 #if !defined(ELINK_EMUL_ONLY) && (!defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_SFX7101) || !defined(EXCLUDE_BCM8705) || !defined(EXCLUDE_BCM87x6)) 6824 static elink_status_t 6825 elink_format_ver(u32 num, u8 *str, u16 *len) 6826 { 6827 #ifdef ELINK_ENHANCEMENTS 6828 u8 *str_ptr = str; 6829 u32 mask = 0xf0000000; 6830 u8 shift = 8*4; 6831 u8 digit; 6832 u8 remove_leading_zeros = 1; 6833 if (*len < 10) { 6834 /* Need more than 10chars for this format */ 6835 *str_ptr = '\0'; 6836 (*len)--; 6837 return ELINK_STATUS_ERROR; 6838 } 6839 while (shift > 0) { 6840 6841 shift -= 4; 6842 digit = ((num & mask) >> shift); 6843 if (digit == 0 && remove_leading_zeros) { 6844 mask = mask >> 4; 6845 continue; 6846 } else if (digit < 0xa) 6847 *str_ptr = digit + '0'; 6848 else 6849 *str_ptr = digit - 0xa + 'a'; 6850 remove_leading_zeros = 0; 6851 str_ptr++; 6852 (*len)--; 6853 mask = mask >> 4; 6854 if (shift == 4*4) { 6855 *str_ptr = '.'; 6856 str_ptr++; 6857 (*len)--; 6858 remove_leading_zeros = 1; 6859 } 6860 } 6861 #endif /* ELINK_ENHANCEMENTS */ 6862 return ELINK_STATUS_OK; 6863 } 6864 #endif /* ELINK_EMUL_ONLY */ 6865 6866 6867 #ifndef EXCLUDE_BCM8705 6868 static elink_status_t 6869 elink_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) 6870 { 6871 #ifdef ELINK_ENHANCEMENTS 6872 str[0] = '\0'; 6873 (*len)--; 6874 #endif // ELINK_ENHANCEMENTS 6875 return ELINK_STATUS_OK; 6876 } 6877 #endif // EXCLUDE_BCM8705 6878 6879 #ifdef ELINK_ENHANCEMENTS 6880 elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, u8 *version, 6881 u16 len) 6882 { 6883 struct elink_dev *cb; 6884 u32 spirom_ver = 0; 6885 elink_status_t status = ELINK_STATUS_OK; 6886 u8 *ver_p = version; 6887 u16 remain_len = len; 6888 if (version == NULL || params == NULL) 6889 return ELINK_STATUS_ERROR; 6890 cb = params->cb; 6891 6892 /* Extract first external phy*/ 6893 version[0] = '\0'; 6894 spirom_ver = REG_RD(cb, params->phy[ELINK_EXT_PHY1].ver_addr); 6895 6896 if (params->phy[ELINK_EXT_PHY1].format_fw_ver) { 6897 status |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver, 6898 ver_p, 6899 &remain_len); 6900 ver_p += (len - remain_len); 6901 } 6902 if ((params->num_phys == ELINK_MAX_PHYS) && 6903 (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) { 6904 spirom_ver = REG_RD(cb, params->phy[ELINK_EXT_PHY2].ver_addr); 6905 if (params->phy[ELINK_EXT_PHY2].format_fw_ver) { 6906 *ver_p = '/'; 6907 ver_p++; 6908 remain_len--; 6909 status |= params->phy[ELINK_EXT_PHY2].format_fw_ver( 6910 spirom_ver, 6911 ver_p, 6912 &remain_len); 6913 ver_p = version + (len - remain_len); 6914 } 6915 } 6916 *ver_p = '\0'; 6917 return status; 6918 } 6919 #endif // ELINK_ENHANCEMENTS 6920 6921 #ifndef EXCLUDE_XGXS 6922 static void elink_set_xgxs_loopback(struct elink_phy *phy, 6923 struct elink_params *params) 6924 { 6925 #ifdef ELINK_INCLUDE_LOOPBACK 6926 u8 port = params->port; 6927 struct elink_dev *cb = params->cb; 6928 6929 if (phy->req_line_speed != ELINK_SPEED_1000) { 6930 u32 md_devad = 0; 6931 6932 ELINK_DEBUG_P0(cb, "XGXS 10G loopback enable\n"); 6933 6934 if (!CHIP_IS_E3(params->chip_id)) { 6935 /* Change the uni_phy_addr in the nig */ 6936 md_devad = REG_RD(cb, (NIG_REG_XGXS0_CTRL_MD_DEVAD + 6937 port*0x18)); 6938 6939 REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6940 0x5); 6941 } 6942 6943 elink_cl45_write(cb, phy, 6944 5, 6945 (MDIO_REG_BANK_AER_BLOCK + 6946 (MDIO_AER_BLOCK_AER_REG & 0xf)), 6947 0x2800); 6948 6949 elink_cl45_write(cb, phy, 6950 5, 6951 (MDIO_REG_BANK_CL73_IEEEB0 + 6952 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), 6953 0x6041); 6954 MSLEEP(cb, 200); 6955 /* Set aer mmd back */ 6956 elink_set_aer_mmd(params, phy); 6957 6958 if (!CHIP_IS_E3(params->chip_id)) { 6959 /* And md_devad */ 6960 REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6961 md_devad); 6962 } 6963 } else { 6964 u16 mii_ctrl; 6965 ELINK_DEBUG_P0(cb, "XGXS 1G loopback enable\n"); 6966 elink_cl45_read(cb, phy, 5, 6967 (MDIO_REG_BANK_COMBO_IEEE0 + 6968 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6969 &mii_ctrl); 6970 elink_cl45_write(cb, phy, 5, 6971 (MDIO_REG_BANK_COMBO_IEEE0 + 6972 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6973 mii_ctrl | 6974 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); 6975 } 6976 #endif // ELINK_INCLUDE_LOOPBACK 6977 } 6978 #endif /* EXCLUDE_XGXS */ 6979 6980 elink_status_t elink_set_led(struct elink_params *params, 6981 struct elink_vars *vars, u8 mode, u32 speed) 6982 { 6983 u8 port = params->port; 6984 u16 hw_led_mode = params->hw_led_mode; 6985 elink_status_t rc = ELINK_STATUS_OK; 6986 u8 phy_idx; 6987 u32 tmp; 6988 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 6989 struct elink_dev *cb = params->cb; 6990 ELINK_DEBUG_P2(cb, "elink_set_led: port %x, mode %d\n", port, mode); 6991 ELINK_DEBUG_P2(cb, "speed 0x%x, hw_led_mode 0x%x\n", 6992 speed, hw_led_mode); 6993 /* In case */ 6994 for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 6995 if (params->phy[phy_idx].set_link_led) { 6996 params->phy[phy_idx].set_link_led( 6997 ¶ms->phy[phy_idx], params, mode); 6998 } 6999 } 7000 #ifdef ELINK_INCLUDE_EMUL 7001 if (params->feature_config_flags & 7002 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC) 7003 return rc; 7004 #endif 7005 7006 switch (mode) { 7007 case ELINK_LED_MODE_FRONT_PANEL_OFF: 7008 case ELINK_LED_MODE_OFF: 7009 REG_WR(cb, NIG_REG_LED_10G_P0 + port*4, 0); 7010 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 7011 SHARED_HW_CFG_LED_MAC1); 7012 7013 tmp = EMAC_RD(cb, EMAC_REG_EMAC_LED); 7014 if (params->phy[ELINK_EXT_PHY1].type == 7015 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 7016 tmp &= ~(EMAC_LED_1000MB_OVERRIDE | 7017 EMAC_LED_100MB_OVERRIDE | 7018 EMAC_LED_10MB_OVERRIDE); 7019 else 7020 tmp |= EMAC_LED_OVERRIDE; 7021 7022 EMAC_WR(cb, EMAC_REG_EMAC_LED, tmp); 7023 break; 7024 7025 case ELINK_LED_MODE_OPER: 7026 /* For all other phys, OPER mode is same as ON, so in case 7027 * link is down, do nothing 7028 */ 7029 if (!vars->link_up) 7030 break; 7031 /* FALLTHROUGH */ 7032 case ELINK_LED_MODE_ON: 7033 if (((params->phy[ELINK_EXT_PHY1].type == 7034 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || 7035 (params->phy[ELINK_EXT_PHY1].type == 7036 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && 7037 CHIP_IS_E2(params->chip_id) && params->num_phys == 2) { 7038 /* This is a work-around for E2+8727 Configurations */ 7039 if (mode == ELINK_LED_MODE_ON || 7040 speed == ELINK_SPEED_10000){ 7041 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 0); 7042 REG_WR(cb, NIG_REG_LED_10G_P0 + port*4, 1); 7043 7044 tmp = EMAC_RD(cb, EMAC_REG_EMAC_LED); 7045 EMAC_WR(cb, EMAC_REG_EMAC_LED, 7046 (tmp | EMAC_LED_OVERRIDE)); 7047 /* Return here without enabling traffic 7048 * LED blink and setting rate in ON mode. 7049 * In oper mode, enabling LED blink 7050 * and setting rate is needed. 7051 */ 7052 if (mode == ELINK_LED_MODE_ON) 7053 return rc; 7054 } 7055 } else if (ELINK_SINGLE_MEDIA_DIRECT(params)) { 7056 /* This is a work-around for HW issue found when link 7057 * is up in CL73 7058 */ 7059 if ((!CHIP_IS_E3(params->chip_id)) || 7060 (CHIP_IS_E3(params->chip_id) && 7061 mode == ELINK_LED_MODE_ON)) 7062 REG_WR(cb, NIG_REG_LED_10G_P0 + port*4, 1); 7063 7064 if (CHIP_IS_E1X(params->chip_id) || 7065 CHIP_IS_E2(params->chip_id) || 7066 (mode == ELINK_LED_MODE_ON)) 7067 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 0); 7068 else 7069 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 7070 hw_led_mode); 7071 } else if ((params->phy[ELINK_EXT_PHY1].type == 7072 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && 7073 (mode == ELINK_LED_MODE_ON)) { 7074 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 0); 7075 tmp = EMAC_RD(cb, EMAC_REG_EMAC_LED); 7076 EMAC_WR(cb, EMAC_REG_EMAC_LED, tmp | 7077 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); 7078 /* Break here; otherwise, it'll disable the 7079 * intended override. 7080 */ 7081 break; 7082 } else { 7083 u32 nig_led_mode = ((params->hw_led_mode << 7084 SHARED_HW_CFG_LED_MODE_SHIFT) == 7085 SHARED_HW_CFG_LED_EXTPHY2) ? 7086 (SHARED_HW_CFG_LED_PHY1 >> 7087 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode; 7088 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 7089 nig_led_mode); 7090 } 7091 7092 REG_WR(cb, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); 7093 /* Set blinking rate to ~15.9Hz */ 7094 if (CHIP_IS_E3(params->chip_id)) 7095 REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 7096 LED_BLINK_RATE_VAL_E3); 7097 else 7098 REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 7099 LED_BLINK_RATE_VAL_E1X_E2); 7100 REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + 7101 port*4, 1); 7102 tmp = EMAC_RD(cb, EMAC_REG_EMAC_LED); 7103 EMAC_WR(cb, EMAC_REG_EMAC_LED, 7104 (tmp & (~EMAC_LED_OVERRIDE))); 7105 7106 #ifndef ELINK_AUX_POWER 7107 if (CHIP_IS_E1(params->chip_id) && 7108 ((speed == ELINK_SPEED_2500) || 7109 (speed == ELINK_SPEED_1000) || 7110 (speed == ELINK_SPEED_100) || 7111 (speed == ELINK_SPEED_10))) { 7112 /* For speeds less than 10G LED scheme is different */ 7113 REG_WR(cb, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 7114 + port*4, 1); 7115 REG_WR(cb, NIG_REG_LED_CONTROL_TRAFFIC_P0 + 7116 port*4, 0); 7117 REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + 7118 port*4, 1); 7119 } 7120 #endif // ELINK_AUX_POWER 7121 break; 7122 7123 default: 7124 rc = ELINK_STATUS_ERROR; 7125 ELINK_DEBUG_P1(cb, "elink_set_led: Invalid led mode %d\n", 7126 mode); 7127 break; 7128 } 7129 return rc; 7130 7131 } 7132 7133 #endif // EXCLUDE_NON_COMMON_INIT 7134 #ifdef ELINK_ENHANCEMENTS 7135 /* This function comes to reflect the actual link state read DIRECTLY from the 7136 * HW 7137 */ 7138 elink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars, 7139 u8 is_serdes) 7140 { 7141 struct elink_dev *cb = params->cb; 7142 u16 gp_status = 0, phy_index = 0; 7143 u8 ext_phy_link_up = 0, serdes_phy_type; 7144 struct elink_vars temp_vars; 7145 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY]; 7146 #ifdef ELINK_INCLUDE_FPGA 7147 if (CHIP_REV_IS_FPGA(params->chip_id)) 7148 return ELINK_STATUS_OK; 7149 #endif /* ELINK_INCLUDE_FPGA */ 7150 #ifdef ELINK_INCLUDE_EMUL 7151 if (CHIP_REV_IS_EMUL(params->chip_id)) 7152 return ELINK_STATUS_OK; 7153 #endif /* ELINK_INCLUDE_EMUL */ 7154 7155 if (CHIP_IS_E3(params->chip_id)) { 7156 u16 link_up; 7157 if (params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] 7158 > ELINK_SPEED_10000) { 7159 /* Check 20G link */ 7160 elink_cl45_read(cb, int_phy, MDIO_WC_DEVAD, 7161 1, &link_up); 7162 elink_cl45_read(cb, int_phy, MDIO_WC_DEVAD, 7163 1, &link_up); 7164 link_up &= (1<<2); 7165 } else { 7166 /* Check 10G link and below*/ 7167 u8 lane = elink_get_warpcore_lane(int_phy, params); 7168 elink_cl45_read(cb, int_phy, MDIO_WC_DEVAD, 7169 MDIO_WC_REG_GP2_STATUS_GP_2_1, 7170 &gp_status); 7171 gp_status = ((gp_status >> 8) & 0xf) | 7172 ((gp_status >> 12) & 0xf); 7173 link_up = gp_status & (1 << lane); 7174 } 7175 if (!link_up) 7176 return ELINK_STATUS_NO_LINK; 7177 } else { 7178 CL22_RD_OVER_CL45(cb, int_phy, 7179 MDIO_REG_BANK_GP_STATUS, 7180 MDIO_GP_STATUS_TOP_AN_STATUS1, 7181 &gp_status); 7182 /* Link is up only if both local phy and external phy are up */ 7183 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) 7184 return ELINK_STATUS_NO_LINK; 7185 } 7186 /* In XGXS loopback mode, do not check external PHY */ 7187 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) 7188 return ELINK_STATUS_OK; 7189 7190 switch (params->num_phys) { 7191 case 1: 7192 /* No external PHY */ 7193 return ELINK_STATUS_OK; 7194 case 2: 7195 ext_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status( 7196 ¶ms->phy[ELINK_EXT_PHY1], 7197 params, &temp_vars); 7198 break; 7199 case 3: /* Dual Media */ 7200 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 7201 phy_index++) { 7202 serdes_phy_type = ((params->phy[phy_index].media_type == 7203 ELINK_ETH_PHY_SFPP_10G_FIBER) || 7204 (params->phy[phy_index].media_type == 7205 ELINK_ETH_PHY_SFP_1G_FIBER) || 7206 (params->phy[phy_index].media_type == 7207 ELINK_ETH_PHY_XFP_FIBER) || 7208 (params->phy[phy_index].media_type == 7209 ELINK_ETH_PHY_DA_TWINAX)); 7210 7211 if (is_serdes != serdes_phy_type) 7212 continue; 7213 if (params->phy[phy_index].read_status) { 7214 ext_phy_link_up |= 7215 params->phy[phy_index].read_status( 7216 ¶ms->phy[phy_index], 7217 params, &temp_vars); 7218 } 7219 } 7220 break; 7221 } 7222 if (ext_phy_link_up) 7223 return ELINK_STATUS_OK; 7224 return ELINK_STATUS_NO_LINK; 7225 } 7226 #endif // ELINK_ENHANCEMENT 7227 7228 #ifndef EXCLUDE_NON_COMMON_INIT 7229 static elink_status_t elink_link_initialize(struct elink_params *params, 7230 struct elink_vars *vars) 7231 { 7232 u8 phy_index, non_ext_phy; 7233 struct elink_dev *cb = params->cb; 7234 /* In case of external phy existence, the line speed would be the 7235 * line speed linked up by the external phy. In case it is direct 7236 * only, then the line_speed during initialization will be 7237 * equal to the req_line_speed 7238 */ 7239 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed; 7240 7241 /* Initialize the internal phy in case this is a direct board 7242 * (no external phys), or this board has external phy which requires 7243 * to first. 7244 */ 7245 #ifndef EXCLUDE_XGXS 7246 if (!ELINK_USES_WARPCORE(params->chip_id)) 7247 elink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars); 7248 #endif // EXCLUDE_XGXS 7249 /* init ext phy and enable link state int */ 7250 non_ext_phy = (ELINK_SINGLE_MEDIA_DIRECT(params) || 7251 (params->loopback_mode == ELINK_LOOPBACK_XGXS)); 7252 7253 if (non_ext_phy || 7254 (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) || 7255 (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) { 7256 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; 7257 #ifndef EXCLUDE_XGXS 7258 if (vars->line_speed == ELINK_SPEED_AUTO_NEG && 7259 (CHIP_IS_E1X(params->chip_id) || 7260 CHIP_IS_E2(params->chip_id))) 7261 elink_set_parallel_detection(phy, params); 7262 #endif // EXCLUDE_XGXS 7263 if (params->phy[ELINK_INT_PHY].config_init) 7264 params->phy[ELINK_INT_PHY].config_init(phy, params, vars); 7265 } 7266 7267 /* Re-read this value in case it was changed inside config_init due to 7268 * limitations of optic module 7269 */ 7270 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed; 7271 7272 /* Init external phy*/ 7273 if (non_ext_phy) { 7274 if (params->phy[ELINK_INT_PHY].supported & 7275 ELINK_SUPPORTED_FIBRE) 7276 vars->link_status |= LINK_STATUS_SERDES_LINK; 7277 } else { 7278 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 7279 phy_index++) { 7280 /* No need to initialize second phy in case of first 7281 * phy only selection. In case of second phy, we do 7282 * need to initialize the first phy, since they are 7283 * connected. 7284 */ 7285 if (params->phy[phy_index].supported & 7286 ELINK_SUPPORTED_FIBRE) 7287 vars->link_status |= LINK_STATUS_SERDES_LINK; 7288 7289 if (phy_index == ELINK_EXT_PHY2 && 7290 (elink_phy_selection(params) == 7291 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { 7292 ELINK_DEBUG_P0(cb, 7293 "Not initializing second phy\n"); 7294 continue; 7295 } 7296 params->phy[phy_index].config_init( 7297 ¶ms->phy[phy_index], 7298 params, vars); 7299 } 7300 } 7301 /* Reset the interrupt indication after phy was initialized */ 7302 elink_bits_dis(cb, NIG_REG_STATUS_INTERRUPT_PORT0 + 7303 params->port*4, 7304 (ELINK_NIG_STATUS_XGXS0_LINK10G | 7305 ELINK_NIG_STATUS_XGXS0_LINK_STATUS | 7306 ELINK_NIG_STATUS_SERDES0_LINK_STATUS | 7307 ELINK_NIG_MASK_MI_INT)); 7308 return ELINK_STATUS_OK; 7309 } 7310 7311 #ifndef EXCLUDE_XGXS 7312 static void elink_int_link_reset(struct elink_phy *phy, 7313 struct elink_params *params) 7314 { 7315 #ifndef EXCLUDE_LINK_RESET 7316 /* Reset the SerDes/XGXS */ 7317 REG_WR(params->cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, 7318 (0x1ff << (params->port*16))); 7319 #endif // EXCLUDE_LINK_RESET 7320 } 7321 #endif // EXCLUDE_XGXS 7322 7323 #if (!defined ELINK_EMUL_ONLY) && ((!defined EXCLUDE_BCM87x6) || (!defined EXCLUDE_SFX7101) || (!defined EXCLUDE_BCM8705)) 7324 static void elink_common_ext_link_reset(struct elink_phy *phy, 7325 struct elink_params *params) 7326 { 7327 #ifndef EXCLUDE_LINK_RESET 7328 struct elink_dev *cb = params->cb; 7329 u8 gpio_port; 7330 /* HW reset */ 7331 if (CHIP_IS_E2(params->chip_id)) 7332 gpio_port = PATH_ID(cb); 7333 else 7334 gpio_port = params->port; 7335 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1, 7336 MISC_REGISTERS_GPIO_OUTPUT_LOW, 7337 gpio_port); 7338 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 7339 MISC_REGISTERS_GPIO_OUTPUT_LOW, 7340 gpio_port); 7341 ELINK_DEBUG_P0(cb, "reset external PHY\n"); 7342 #endif /* EXCLUDE_LINK_RESET */ 7343 } 7344 #endif /* ELINK_EMUL_ONLY */ 7345 7346 static elink_status_t elink_update_link_down(struct elink_params *params, 7347 struct elink_vars *vars) 7348 { 7349 struct elink_dev *cb = params->cb; 7350 u8 port = params->port; 7351 7352 ELINK_DEBUG_P1(cb, "Port %x: Link is down\n", port); 7353 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0); 7354 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; 7355 /* Indicate no mac active */ 7356 vars->mac_type = ELINK_MAC_TYPE_NONE; 7357 7358 /* Update shared memory */ 7359 vars->link_status &= ~ELINK_LINK_UPDATE_MASK; 7360 vars->line_speed = 0; 7361 elink_update_mng(params, vars->link_status); 7362 7363 /* Activate nig drain */ 7364 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 7365 7366 /* Disable emac */ 7367 if (!CHIP_IS_E3(params->chip_id)) 7368 REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 0); 7369 7370 MSLEEP(cb, 10); 7371 #if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) 7372 /* Reset BigMac/Xmac */ 7373 if (CHIP_IS_E1X(params->chip_id) || 7374 CHIP_IS_E2(params->chip_id)) 7375 elink_set_bmac_rx(cb, params->chip_id, params->port, 0); 7376 #endif // #if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) 7377 7378 #ifndef EXCLUDE_WARPCORE 7379 if (CHIP_IS_E3(params->chip_id)) { 7380 /* Prevent LPI Generation by chip */ 7381 REG_WR(cb, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 7382 0); 7383 REG_WR(cb, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), 7384 0); 7385 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 7386 SHMEM_EEE_ACTIVE_BIT); 7387 7388 elink_update_mng_eee(params, vars->eee_status); 7389 elink_set_xmac_rxtx(params, 0); 7390 elink_set_umac_rxtx(params, 0); 7391 } 7392 #endif // EXCLUDE_WARPCORE 7393 7394 return ELINK_STATUS_OK; 7395 } 7396 7397 static elink_status_t elink_update_link_up(struct elink_params *params, 7398 struct elink_vars *vars, 7399 u8 link_10g) 7400 { 7401 struct elink_dev *cb = params->cb; 7402 u8 phy_idx, port = params->port; 7403 elink_status_t rc = ELINK_STATUS_OK; 7404 7405 vars->link_status |= (LINK_STATUS_LINK_UP | 7406 LINK_STATUS_PHYSICAL_LINK_FLAG); 7407 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 7408 7409 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) 7410 vars->link_status |= 7411 LINK_STATUS_TX_FLOW_CONTROL_ENABLED; 7412 7413 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) 7414 vars->link_status |= 7415 LINK_STATUS_RX_FLOW_CONTROL_ENABLED; 7416 #ifndef EXCLUDE_WARPCORE 7417 if (ELINK_USES_WARPCORE(params->chip_id)) { 7418 if (link_10g) { 7419 if (elink_xmac_enable(params, vars, 0) == 7420 ELINK_STATUS_NO_LINK) { 7421 ELINK_DEBUG_P0(cb, "Found errors on XMAC\n"); 7422 vars->link_up = 0; 7423 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 7424 vars->link_status &= ~LINK_STATUS_LINK_UP; 7425 } 7426 } else 7427 elink_umac_enable(params, vars, 0); 7428 elink_set_led(params, vars, 7429 ELINK_LED_MODE_OPER, vars->line_speed); 7430 7431 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && 7432 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { 7433 ELINK_DEBUG_P0(cb, "Enabling LPI assertion\n"); 7434 REG_WR(cb, MISC_REG_CPMU_LP_FW_ENABLE_P0 + 7435 (params->port << 2), 1); 7436 REG_WR(cb, MISC_REG_CPMU_LP_DR_ENABLE, 1); 7437 REG_WR(cb, MISC_REG_CPMU_LP_MASK_ENT_P0 + 7438 (params->port << 2), 0xfc20); 7439 } 7440 } 7441 #endif // EXCLUDE_WARPCORE 7442 #ifndef EXCLUDE_XGXS 7443 if ((CHIP_IS_E1X(params->chip_id) || 7444 CHIP_IS_E2(params->chip_id))) { 7445 if (link_10g) { 7446 if (elink_bmac_enable(params, vars, 0, 1) == 7447 ELINK_STATUS_NO_LINK) { 7448 ELINK_DEBUG_P0(cb, "Found errors on BMAC\n"); 7449 vars->link_up = 0; 7450 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 7451 vars->link_status &= ~LINK_STATUS_LINK_UP; 7452 } 7453 7454 elink_set_led(params, vars, 7455 ELINK_LED_MODE_OPER, ELINK_SPEED_10000); 7456 } else { 7457 rc = elink_emac_program(params, vars); 7458 elink_emac_enable(params, vars, 0); 7459 7460 /* AN complete? */ 7461 if ((vars->link_status & 7462 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) 7463 && (!(vars->phy_flags & PHY_SGMII_FLAG)) && 7464 ELINK_SINGLE_MEDIA_DIRECT(params)) 7465 elink_set_gmii_tx_driver(params); 7466 } 7467 } 7468 #endif // EXCLUDE_XGXS 7469 7470 #ifndef ELINK_AUX_POWER 7471 /* PBF - link up */ 7472 if (CHIP_IS_E1X(params->chip_id)) 7473 rc |= elink_pbf_update(params, vars->flow_ctrl, 7474 vars->line_speed); 7475 #endif /* ELINK_AUX_POWER */ 7476 7477 /* Disable drain */ 7478 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); 7479 7480 /* Update shared memory */ 7481 elink_update_mng(params, vars->link_status); 7482 #ifndef EXCLUDE_WARPCORE 7483 elink_update_mng_eee(params, vars->eee_status); 7484 #endif /* #ifndef EXCLUDE_WARPCORE */ 7485 /* Check remote fault */ 7486 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 7487 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) { 7488 elink_check_half_open_conn(params, vars, 0); 7489 break; 7490 } 7491 } 7492 MSLEEP(cb, 20); 7493 return rc; 7494 } 7495 7496 static void elink_chng_link_count(struct elink_params *params, u8 clear) 7497 { 7498 struct elink_dev *cb = params->cb; 7499 u32 addr, val; 7500 7501 /* Verify the link_change_count is supported by the MFW */ 7502 if (!(SHMEM2_HAS(cb, params->shmem2_base, link_change_count))) 7503 return; 7504 7505 addr = params->shmem2_base + 7506 OFFSETOF(struct shmem2_region, link_change_count[params->port]); 7507 if (clear) 7508 val = 0; 7509 else 7510 val = REG_RD(cb, addr) + 1; 7511 REG_WR(cb, addr, val); 7512 } 7513 7514 /* The elink_link_update function should be called upon link 7515 * interrupt. 7516 * Link is considered up as follows: 7517 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs 7518 * to be up 7519 * - SINGLE_MEDIA - The link between the 577xx and the external 7520 * phy (XGXS) need to up as well as the external link of the 7521 * phy (PHY_EXT1) 7522 * - DUAL_MEDIA - The link between the 577xx and the first 7523 * external phy needs to be up, and at least one of the 2 7524 * external phy link must be up. 7525 */ 7526 elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars) 7527 { 7528 struct elink_dev *cb = params->cb; 7529 struct elink_vars phy_vars[ELINK_MAX_PHYS]; 7530 u8 port = params->port; 7531 u8 link_10g_plus, phy_index; 7532 u32 prev_link_status = vars->link_status; 7533 u8 ext_phy_link_up = 0, cur_link_up; 7534 elink_status_t rc = ELINK_STATUS_OK; 7535 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; 7536 u8 active_external_phy = ELINK_INT_PHY; 7537 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; 7538 vars->link_status &= ~ELINK_LINK_UPDATE_MASK; 7539 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; 7540 phy_index++) { 7541 phy_vars[phy_index].flow_ctrl = 0; 7542 phy_vars[phy_index].link_status = 0; 7543 phy_vars[phy_index].line_speed = 0; 7544 phy_vars[phy_index].duplex = DUPLEX_FULL; 7545 phy_vars[phy_index].phy_link_up = 0; 7546 phy_vars[phy_index].link_up = 0; 7547 phy_vars[phy_index].fault_detected = 0; 7548 /* different consideration, since vars holds inner state */ 7549 phy_vars[phy_index].eee_status = vars->eee_status; 7550 } 7551 7552 if (ELINK_USES_WARPCORE(params->chip_id)) 7553 elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]); 7554 7555 ELINK_DEBUG_P3(cb, "port %x, XGXS?%x, int_status 0x%x\n", 7556 port, (vars->phy_flags & PHY_XGXS_FLAG), 7557 REG_RD(cb, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 7558 7559 ELINK_DEBUG_P3(cb, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", 7560 REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 7561 REG_RD(cb, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18) > 0, 7562 REG_RD(cb, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); 7563 7564 ELINK_DEBUG_P2(cb, " 10G %x, XGXS_LINK %x\n", 7565 REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 7566 REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 7567 7568 /* Disable emac */ 7569 if (!CHIP_IS_E3(params->chip_id)) 7570 REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 0); 7571 7572 /* Step 1: 7573 * Check external link change only for external phys, and apply 7574 * priority selection between them in case the link on both phys 7575 * is up. Note that instead of the common vars, a temporary 7576 * vars argument is used since each phy may have different link/ 7577 * speed/duplex result 7578 */ 7579 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 7580 phy_index++) { 7581 struct elink_phy *phy = ¶ms->phy[phy_index]; 7582 if (!phy->read_status) 7583 continue; 7584 /* Read link status and params of this ext phy */ 7585 cur_link_up = phy->read_status(phy, params, 7586 &phy_vars[phy_index]); 7587 if (cur_link_up) { 7588 ELINK_DEBUG_P1(cb, "phy in index %d link is up\n", 7589 phy_index); 7590 } else { 7591 ELINK_DEBUG_P1(cb, "phy in index %d link is down\n", 7592 phy_index); 7593 continue; 7594 } 7595 7596 if (!ext_phy_link_up) { 7597 ext_phy_link_up = 1; 7598 active_external_phy = phy_index; 7599 } else { 7600 switch (elink_phy_selection(params)) { 7601 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 7602 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 7603 /* In this option, the first PHY makes sure to pass the 7604 * traffic through itself only. 7605 * Its not clear how to reset the link on the second phy 7606 */ 7607 active_external_phy = ELINK_EXT_PHY1; 7608 break; 7609 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 7610 /* In this option, the first PHY makes sure to pass the 7611 * traffic through the second PHY. 7612 */ 7613 active_external_phy = ELINK_EXT_PHY2; 7614 break; 7615 default: 7616 /* Link indication on both PHYs with the following cases 7617 * is invalid: 7618 * - FIRST_PHY means that second phy wasn't initialized, 7619 * hence its link is expected to be down 7620 * - SECOND_PHY means that first phy should not be able 7621 * to link up by itself (using configuration) 7622 * - DEFAULT should be overriden during initialiazation 7623 */ 7624 ELINK_DEBUG_P1(cb, "Invalid link indication" 7625 "mpc=0x%x. DISABLING LINK !!!\n", 7626 params->multi_phy_config); 7627 ext_phy_link_up = 0; 7628 break; 7629 } 7630 } 7631 } 7632 prev_line_speed = vars->line_speed; 7633 /* Step 2: 7634 * Read the status of the internal phy. In case of 7635 * DIRECT_SINGLE_MEDIA board, this link is the external link, 7636 * otherwise this is the link between the 577xx and the first 7637 * external phy 7638 */ 7639 if (params->phy[ELINK_INT_PHY].read_status) 7640 params->phy[ELINK_INT_PHY].read_status( 7641 ¶ms->phy[ELINK_INT_PHY], 7642 params, vars); 7643 /* The INT_PHY flow control reside in the vars. This include the 7644 * case where the speed or flow control are not set to AUTO. 7645 * Otherwise, the active external phy flow control result is set 7646 * to the vars. The ext_phy_line_speed is needed to check if the 7647 * speed is different between the internal phy and external phy. 7648 * This case may be result of intermediate link speed change. 7649 */ 7650 if (active_external_phy > ELINK_INT_PHY) { 7651 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; 7652 /* Link speed is taken from the XGXS. AN and FC result from 7653 * the external phy. 7654 */ 7655 vars->link_status |= phy_vars[active_external_phy].link_status; 7656 7657 /* if active_external_phy is first PHY and link is up - disable 7658 * disable TX on second external PHY 7659 */ 7660 if (active_external_phy == ELINK_EXT_PHY1) { 7661 if (params->phy[ELINK_EXT_PHY2].phy_specific_func) { 7662 ELINK_DEBUG_P0(cb, 7663 "Disabling TX on EXT_PHY2\n"); 7664 params->phy[ELINK_EXT_PHY2].phy_specific_func( 7665 ¶ms->phy[ELINK_EXT_PHY2], 7666 params, ELINK_DISABLE_TX); 7667 } 7668 } 7669 7670 ext_phy_line_speed = phy_vars[active_external_phy].line_speed; 7671 vars->duplex = phy_vars[active_external_phy].duplex; 7672 if (params->phy[active_external_phy].supported & 7673 ELINK_SUPPORTED_FIBRE) 7674 vars->link_status |= LINK_STATUS_SERDES_LINK; 7675 else 7676 vars->link_status &= ~LINK_STATUS_SERDES_LINK; 7677 7678 vars->eee_status = phy_vars[active_external_phy].eee_status; 7679 7680 ELINK_DEBUG_P1(cb, "Active external phy selected: %x\n", 7681 active_external_phy); 7682 } 7683 7684 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 7685 phy_index++) { 7686 if (params->phy[phy_index].flags & 7687 ELINK_FLAGS_REARM_LATCH_SIGNAL) { 7688 elink_rearm_latch_signal(cb, port, 7689 phy_index == 7690 active_external_phy); 7691 break; 7692 } 7693 } 7694 ELINK_DEBUG_P3(cb, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," 7695 " ext_phy_line_speed = %d\n", vars->flow_ctrl, 7696 vars->link_status, ext_phy_line_speed); 7697 /* Upon link speed change set the NIG into drain mode. Comes to 7698 * deals with possible FIFO glitch due to clk change when speed 7699 * is decreased without link down indicator 7700 */ 7701 7702 if (vars->phy_link_up) { 7703 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && 7704 (ext_phy_line_speed != vars->line_speed)) { 7705 ELINK_DEBUG_P2(cb, "Internal link speed %d is" 7706 " different than the external" 7707 " link speed %d\n", vars->line_speed, 7708 ext_phy_line_speed); 7709 vars->phy_link_up = 0; 7710 } else if (prev_line_speed != vars->line_speed) { 7711 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 7712 0); 7713 MSLEEP(cb, 1); 7714 } 7715 } 7716 7717 /* Anything 10 and over uses the bmac */ 7718 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000); 7719 7720 elink_link_int_ack(params, vars, link_10g_plus); 7721 7722 /* In case external phy link is up, and internal link is down 7723 * (not initialized yet probably after link initialization, it 7724 * needs to be initialized. 7725 * Note that after link down-up as result of cable plug, the xgxs 7726 * link would probably become up again without the need 7727 * initialize it 7728 */ 7729 if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) { 7730 ELINK_DEBUG_P3(cb, "ext_phy_link_up = %d, int_link_up = %d," 7731 " init_preceding = %d\n", ext_phy_link_up, 7732 vars->phy_link_up, 7733 params->phy[ELINK_EXT_PHY1].flags & 7734 ELINK_FLAGS_INIT_XGXS_FIRST); 7735 if (!(params->phy[ELINK_EXT_PHY1].flags & 7736 ELINK_FLAGS_INIT_XGXS_FIRST) 7737 && ext_phy_link_up && !vars->phy_link_up) { 7738 vars->line_speed = ext_phy_line_speed; 7739 if (vars->line_speed < ELINK_SPEED_1000) 7740 vars->phy_flags |= PHY_SGMII_FLAG; 7741 else 7742 vars->phy_flags &= ~PHY_SGMII_FLAG; 7743 7744 if (params->phy[ELINK_INT_PHY].config_init) 7745 params->phy[ELINK_INT_PHY].config_init( 7746 ¶ms->phy[ELINK_INT_PHY], params, 7747 vars); 7748 } 7749 } 7750 /* Link is up only if both local phy and external phy (in case of 7751 * non-direct board) are up and no fault detected on active PHY. 7752 */ 7753 vars->link_up = (vars->phy_link_up && 7754 (ext_phy_link_up || 7755 ELINK_SINGLE_MEDIA_DIRECT(params)) && 7756 (phy_vars[active_external_phy].fault_detected == 0)); 7757 7758 /* Update the PFC configuration in case it was changed */ 7759 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 7760 vars->link_status |= LINK_STATUS_PFC_ENABLED; 7761 else 7762 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 7763 7764 if (vars->link_up) 7765 rc = elink_update_link_up(params, vars, link_10g_plus); 7766 else 7767 rc = elink_update_link_down(params, vars); 7768 7769 if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP) 7770 elink_chng_link_count(params, 0); 7771 7772 #ifndef ELINK_AUX_POWER 7773 /* Update MCP link status was changed */ 7774 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX) 7775 elink_cb_fw_command(cb, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); 7776 #endif // ELINK_AUX_POWER 7777 7778 return rc; 7779 } 7780 7781 #endif // EXCLUDE_NON_COMMON_INIT 7782 #ifndef ELINK_EMUL_ONLY 7783 /*****************************************************************************/ 7784 /* External Phy section */ 7785 /*****************************************************************************/ 7786 void elink_ext_phy_hw_reset(struct elink_dev *cb, u8 port) 7787 { 7788 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1, 7789 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 7790 MSLEEP(cb, 1); 7791 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1, 7792 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); 7793 } 7794 7795 #if !defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_SFX7101) || !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833) || !defined(EXCLUDE_SFX7101) || !defined(EXCLUDE_BCM8705) || !defined(EXCLUDE_BCM87x6) 7796 static void elink_save_spirom_version(struct elink_dev *cb, u8 port, 7797 u32 spirom_ver, u32 ver_addr) 7798 { 7799 ELINK_DEBUG_P3(cb, "FW version 0x%x:0x%x for port %d\n", 7800 (u16)(spirom_ver>>16), (u16)spirom_ver, port); 7801 7802 if (ver_addr) 7803 REG_WR(cb, ver_addr, spirom_ver); 7804 } 7805 7806 #if (!defined EXCLUDE_XGXS) && (!defined EXCLUDE_COMMON_INIT) 7807 static void elink_save_bcm_spirom_ver(struct elink_dev *cb, 7808 struct elink_phy *phy, 7809 u8 port) 7810 { 7811 u16 fw_ver1, fw_ver2; 7812 7813 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 7814 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7815 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 7816 MDIO_PMA_REG_ROM_VER2, &fw_ver2); 7817 elink_save_spirom_version(cb, port, (u32)(fw_ver1<<16 | fw_ver2), 7818 phy->ver_addr); 7819 } 7820 #endif // EXCLUDE_XGXS 7821 7822 #ifndef EXCLUDE_NON_COMMON_INIT 7823 static void elink_ext_phy_10G_an_resolve(struct elink_dev *cb, 7824 struct elink_phy *phy, 7825 struct elink_vars *vars) 7826 { 7827 u16 val; 7828 elink_cl45_read(cb, phy, 7829 MDIO_AN_DEVAD, 7830 MDIO_AN_REG_STATUS, &val); 7831 elink_cl45_read(cb, phy, 7832 MDIO_AN_DEVAD, 7833 MDIO_AN_REG_STATUS, &val); 7834 if (val & (1<<5)) 7835 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 7836 if ((val & (1<<0)) == 0) 7837 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; 7838 } 7839 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 7840 #endif // #if !defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833) || !defined(EXCLUDE_SFX7101) 7841 7842 /******************************************************************/ 7843 /* common BCM8073/BCM8727 PHY SECTION */ 7844 /******************************************************************/ 7845 #ifndef EXCLUDE_BCM8727_BCM8073 7846 #ifndef EXCLUDE_NON_COMMON_INIT 7847 static void elink_8073_resolve_fc(struct elink_phy *phy, 7848 struct elink_params *params, 7849 struct elink_vars *vars) 7850 { 7851 struct elink_dev *cb = params->cb; 7852 if (phy->req_line_speed == ELINK_SPEED_10 || 7853 phy->req_line_speed == ELINK_SPEED_100) { 7854 vars->flow_ctrl = phy->req_flow_ctrl; 7855 return; 7856 } 7857 7858 if (elink_ext_phy_resolve_fc(phy, params, vars) && 7859 (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) { 7860 u16 pause_result; 7861 u16 ld_pause; /* local */ 7862 u16 lp_pause; /* link partner */ 7863 elink_cl45_read(cb, phy, 7864 MDIO_AN_DEVAD, 7865 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 7866 7867 elink_cl45_read(cb, phy, 7868 MDIO_AN_DEVAD, 7869 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 7870 pause_result = (ld_pause & 7871 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; 7872 pause_result |= (lp_pause & 7873 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; 7874 7875 elink_pause_resolve(vars, pause_result); 7876 ELINK_DEBUG_P1(cb, "Ext PHY CL37 pause result 0x%x\n", 7877 pause_result); 7878 } 7879 } 7880 #endif // EXCLUDE_NON_COMMON_INIT 7881 #ifndef EXCLUDE_COMMON_INIT 7882 static elink_status_t elink_8073_8727_external_rom_boot(struct elink_dev *cb, 7883 struct elink_phy *phy, 7884 u8 port) 7885 { 7886 u32 count = 0; 7887 u16 fw_ver1, fw_msgout; 7888 elink_status_t rc = ELINK_STATUS_OK; 7889 7890 /* Boot port from external ROM */ 7891 /* EDC grst */ 7892 elink_cl45_write(cb, phy, 7893 MDIO_PMA_DEVAD, 7894 MDIO_PMA_REG_GEN_CTRL, 7895 0x0001); 7896 7897 /* Ucode reboot and rst */ 7898 elink_cl45_write(cb, phy, 7899 MDIO_PMA_DEVAD, 7900 MDIO_PMA_REG_GEN_CTRL, 7901 0x008c); 7902 7903 elink_cl45_write(cb, phy, 7904 MDIO_PMA_DEVAD, 7905 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 7906 7907 /* Reset internal microprocessor */ 7908 elink_cl45_write(cb, phy, 7909 MDIO_PMA_DEVAD, 7910 MDIO_PMA_REG_GEN_CTRL, 7911 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 7912 7913 /* Release srst bit */ 7914 elink_cl45_write(cb, phy, 7915 MDIO_PMA_DEVAD, 7916 MDIO_PMA_REG_GEN_CTRL, 7917 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 7918 7919 /* Delay 100ms per the PHY specifications */ 7920 MSLEEP(cb, 100); 7921 7922 /* 8073 sometimes taking longer to download */ 7923 do { 7924 count++; 7925 if (count > 300) { 7926 ELINK_DEBUG_P2(cb, 7927 "elink_8073_8727_external_rom_boot port %x:" 7928 "Download failed. fw version = 0x%x\n", 7929 port, fw_ver1); 7930 rc = ELINK_STATUS_ERROR; 7931 break; 7932 } 7933 7934 elink_cl45_read(cb, phy, 7935 MDIO_PMA_DEVAD, 7936 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7937 elink_cl45_read(cb, phy, 7938 MDIO_PMA_DEVAD, 7939 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); 7940 7941 MSLEEP(cb, 1); 7942 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || 7943 ((fw_msgout & 0xff) != 0x03 && (phy->type == 7944 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); 7945 7946 /* Clear ser_boot_ctl bit */ 7947 elink_cl45_write(cb, phy, 7948 MDIO_PMA_DEVAD, 7949 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 7950 elink_save_bcm_spirom_ver(cb, phy, port); 7951 7952 ELINK_DEBUG_P2(cb, 7953 "elink_8073_8727_external_rom_boot port %x:" 7954 "Download complete. fw version = 0x%x\n", 7955 port, fw_ver1); 7956 7957 return rc; 7958 } 7959 #endif // EXCLUDE_COMMON_INIT 7960 7961 /******************************************************************/ 7962 /* BCM8073 PHY SECTION */ 7963 /******************************************************************/ 7964 #ifndef EXCLUDE_NON_COMMON_INIT 7965 static elink_status_t elink_8073_is_snr_needed(struct elink_dev *cb, struct elink_phy *phy) 7966 { 7967 /* This is only required for 8073A1, version 102 only */ 7968 u16 val; 7969 7970 /* Read 8073 HW revision*/ 7971 elink_cl45_read(cb, phy, 7972 MDIO_PMA_DEVAD, 7973 MDIO_PMA_REG_8073_CHIP_REV, &val); 7974 7975 if (val != 1) { 7976 /* No need to workaround in 8073 A1 */ 7977 return ELINK_STATUS_OK; 7978 } 7979 7980 elink_cl45_read(cb, phy, 7981 MDIO_PMA_DEVAD, 7982 MDIO_PMA_REG_ROM_VER2, &val); 7983 7984 /* SNR should be applied only for version 0x102 */ 7985 if (val != 0x102) 7986 return ELINK_STATUS_OK; 7987 7988 return 1; 7989 } 7990 7991 static elink_status_t elink_8073_xaui_wa(struct elink_dev *cb, struct elink_phy *phy) 7992 { 7993 u16 val, cnt, cnt1 ; 7994 7995 elink_cl45_read(cb, phy, 7996 MDIO_PMA_DEVAD, 7997 MDIO_PMA_REG_8073_CHIP_REV, &val); 7998 7999 if (val > 0) { 8000 /* No need to workaround in 8073 A1 */ 8001 return ELINK_STATUS_OK; 8002 } 8003 /* XAUI workaround in 8073 A0: */ 8004 8005 /* After loading the boot ROM and restarting Autoneg, poll 8006 * Dev1, Reg $C820: 8007 */ 8008 8009 for (cnt = 0; cnt < 1000; cnt++) { 8010 elink_cl45_read(cb, phy, 8011 MDIO_PMA_DEVAD, 8012 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 8013 &val); 8014 /* If bit [14] = 0 or bit [13] = 0, continue on with 8015 * system initialization (XAUI work-around not required, as 8016 * these bits indicate 2.5G or 1G link up). 8017 */ 8018 if (!(val & (1<<14)) || !(val & (1<<13))) { 8019 ELINK_DEBUG_P0(cb, "XAUI work-around not required\n"); 8020 return ELINK_STATUS_OK; 8021 } else if (!(val & (1<<15))) { 8022 ELINK_DEBUG_P0(cb, "bit 15 went off\n"); 8023 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's 8024 * MSB (bit15) goes to 1 (indicating that the XAUI 8025 * workaround has completed), then continue on with 8026 * system initialization. 8027 */ 8028 for (cnt1 = 0; cnt1 < 1000; cnt1++) { 8029 elink_cl45_read(cb, phy, 8030 MDIO_PMA_DEVAD, 8031 MDIO_PMA_REG_8073_XAUI_WA, &val); 8032 if (val & (1<<15)) { 8033 ELINK_DEBUG_P0(cb, 8034 "XAUI workaround has completed\n"); 8035 return ELINK_STATUS_OK; 8036 } 8037 MSLEEP(cb, 3); 8038 } 8039 break; 8040 } 8041 MSLEEP(cb, 3); 8042 } 8043 ELINK_DEBUG_P0(cb, "Warning: XAUI work-around timeout !!!\n"); 8044 return ELINK_STATUS_ERROR; 8045 } 8046 8047 #ifdef ELINK_INCLUDE_LOOPBACK 8048 static void elink_807x_force_10G(struct elink_dev *cb, struct elink_phy *phy) 8049 { 8050 /* Force KR or KX */ 8051 elink_cl45_write(cb, phy, 8052 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 8053 elink_cl45_write(cb, phy, 8054 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); 8055 elink_cl45_write(cb, phy, 8056 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); 8057 elink_cl45_write(cb, phy, 8058 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 8059 } 8060 #endif // ELINK_INCLUDE_LOOPBACK 8061 8062 static void elink_8073_set_pause_cl37(struct elink_params *params, 8063 struct elink_phy *phy, 8064 struct elink_vars *vars) 8065 { 8066 u16 cl37_val; 8067 struct elink_dev *cb = params->cb; 8068 elink_cl45_read(cb, phy, 8069 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); 8070 8071 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 8072 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 8073 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 8074 if ((vars->ieee_fc & 8075 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == 8076 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { 8077 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; 8078 } 8079 if ((vars->ieee_fc & 8080 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 8081 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 8082 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 8083 } 8084 if ((vars->ieee_fc & 8085 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 8086 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 8087 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 8088 } 8089 ELINK_DEBUG_P1(cb, 8090 "Ext phy AN advertize cl37 0x%x\n", cl37_val); 8091 8092 elink_cl45_write(cb, phy, 8093 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); 8094 #ifndef ELINK_AUX_POWER 8095 MSLEEP(cb, 500); 8096 #endif // ELINK_AUX_POWER 8097 } 8098 8099 static void elink_8073_specific_func(struct elink_phy *phy, 8100 struct elink_params *params, 8101 u32 action) 8102 { 8103 struct elink_dev *cb = params->cb; 8104 switch (action) { 8105 case ELINK_PHY_INIT: 8106 /* Enable LASI */ 8107 elink_cl45_write(cb, phy, 8108 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); 8109 elink_cl45_write(cb, phy, 8110 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); 8111 break; 8112 } 8113 } 8114 8115 static elink_status_t elink_8073_config_init(struct elink_phy *phy, 8116 struct elink_params *params, 8117 struct elink_vars *vars) 8118 { 8119 struct elink_dev *cb = params->cb; 8120 u16 val = 0, tmp1; 8121 u8 gpio_port; 8122 ELINK_DEBUG_P0(cb, "Init 8073\n"); 8123 8124 if (CHIP_IS_E2(params->chip_id)) 8125 gpio_port = PATH_ID(cb); 8126 else 8127 gpio_port = params->port; 8128 /* Restore normal power mode*/ 8129 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 8130 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 8131 8132 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1, 8133 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 8134 8135 elink_8073_specific_func(phy, params, ELINK_PHY_INIT); 8136 elink_8073_set_pause_cl37(params, phy, vars); 8137 8138 elink_cl45_read(cb, phy, 8139 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 8140 8141 elink_cl45_read(cb, phy, 8142 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 8143 8144 ELINK_DEBUG_P1(cb, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); 8145 8146 /* Swap polarity if required - Must be done only in non-1G mode */ 8147 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 8148 /* Configure the 8073 to swap _P and _N of the KR lines */ 8149 ELINK_DEBUG_P0(cb, "Swapping polarity for the 8073\n"); 8150 /* 10G Rx/Tx and 1G Tx signal polarity swap */ 8151 elink_cl45_read(cb, phy, 8152 MDIO_PMA_DEVAD, 8153 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); 8154 elink_cl45_write(cb, phy, 8155 MDIO_PMA_DEVAD, 8156 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, 8157 (val | (3<<9))); 8158 } 8159 8160 8161 /* Enable CL37 BAM */ 8162 if (REG_RD(cb, params->shmem_base + 8163 OFFSETOF(struct shmem_region, dev_info. 8164 port_hw_config[params->port].default_cfg)) & 8165 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 8166 8167 elink_cl45_read(cb, phy, 8168 MDIO_AN_DEVAD, 8169 MDIO_AN_REG_8073_BAM, &val); 8170 elink_cl45_write(cb, phy, 8171 MDIO_AN_DEVAD, 8172 MDIO_AN_REG_8073_BAM, val | 1); 8173 ELINK_DEBUG_P0(cb, "Enable CL37 BAM on KR\n"); 8174 } 8175 #ifdef ELINK_INCLUDE_LOOPBACK 8176 if (params->loopback_mode == ELINK_LOOPBACK_EXT) { 8177 elink_807x_force_10G(cb, phy); 8178 ELINK_DEBUG_P0(cb, "Forced speed 10G on 807X\n"); 8179 return ELINK_STATUS_OK; 8180 } else { 8181 elink_cl45_write(cb, phy, 8182 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); 8183 } 8184 #endif // ELINK_INCLUDE_LOOPBACK 8185 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) { 8186 if (phy->req_line_speed == ELINK_SPEED_10000) { 8187 val = (1<<7); 8188 } else if (phy->req_line_speed == ELINK_SPEED_2500) { 8189 val = (1<<5); 8190 /* Note that 2.5G works only when used with 1G 8191 * advertisement 8192 */ 8193 } else 8194 val = (1<<5); 8195 } else { 8196 val = 0; 8197 if (phy->speed_cap_mask & 8198 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 8199 val |= (1<<7); 8200 8201 /* Note that 2.5G works only when used with 1G advertisement */ 8202 if (phy->speed_cap_mask & 8203 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | 8204 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 8205 val |= (1<<5); 8206 ELINK_DEBUG_P1(cb, "807x autoneg val = 0x%x\n", val); 8207 } 8208 8209 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); 8210 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); 8211 8212 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && 8213 (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) || 8214 (phy->req_line_speed == ELINK_SPEED_2500)) { 8215 u16 phy_ver; 8216 /* Allow 2.5G for A1 and above */ 8217 elink_cl45_read(cb, phy, 8218 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, 8219 &phy_ver); 8220 ELINK_DEBUG_P0(cb, "Add 2.5G\n"); 8221 if (phy_ver > 0) 8222 tmp1 |= 1; 8223 else 8224 tmp1 &= 0xfffe; 8225 } else { 8226 ELINK_DEBUG_P0(cb, "Disable 2.5G\n"); 8227 tmp1 &= 0xfffe; 8228 } 8229 8230 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); 8231 /* Add support for CL37 (passive mode) II */ 8232 8233 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); 8234 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 8235 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? 8236 0x20 : 0x40))); 8237 8238 /* Add support for CL37 (passive mode) III */ 8239 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 8240 8241 /* The SNR will improve about 2db by changing BW and FEE main 8242 * tap. Rest commands are executed after link is up 8243 * Change FFE main cursor to 5 in EDC register 8244 */ 8245 if (elink_8073_is_snr_needed(cb, phy)) 8246 elink_cl45_write(cb, phy, 8247 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, 8248 0xFB0C); 8249 8250 /* Enable FEC (Forware Error Correction) Request in the AN */ 8251 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); 8252 tmp1 |= (1<<15); 8253 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); 8254 8255 elink_ext_phy_set_pause(params, phy, vars); 8256 8257 /* Restart autoneg */ 8258 MSLEEP(cb, 500); 8259 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 8260 ELINK_DEBUG_P2(cb, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", 8261 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); 8262 return ELINK_STATUS_OK; 8263 } 8264 8265 static elink_status_t 8266 elink_8073_read_status(struct elink_phy *phy, struct elink_params *params, 8267 struct elink_vars *vars) 8268 { 8269 struct elink_dev *cb = params->cb; 8270 u8 link_up = 0; 8271 u16 val1, val2; 8272 u16 link_status = 0; 8273 u16 an1000_status = 0; 8274 8275 elink_cl45_read(cb, phy, 8276 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 8277 8278 ELINK_DEBUG_P1(cb, "8703 LASI status 0x%x\n", val1); 8279 8280 /* Clear the interrupt LASI status register */ 8281 elink_cl45_read(cb, phy, 8282 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 8283 elink_cl45_read(cb, phy, 8284 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); 8285 ELINK_DEBUG_P2(cb, "807x PCS status 0x%x->0x%x\n", val2, val1); 8286 /* Clear MSG-OUT */ 8287 elink_cl45_read(cb, phy, 8288 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 8289 8290 /* Check the LASI */ 8291 elink_cl45_read(cb, phy, 8292 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 8293 8294 ELINK_DEBUG_P1(cb, "KR 0x9003 0x%x\n", val2); 8295 8296 /* Check the link status */ 8297 elink_cl45_read(cb, phy, 8298 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 8299 ELINK_DEBUG_P1(cb, "KR PCS status 0x%x\n", val2); 8300 8301 elink_cl45_read(cb, phy, 8302 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 8303 elink_cl45_read(cb, phy, 8304 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 8305 link_up = ((val1 & 4) == 4); 8306 ELINK_DEBUG_P1(cb, "PMA_REG_STATUS=0x%x\n", val1); 8307 8308 if (link_up && 8309 ((phy->req_line_speed != ELINK_SPEED_10000))) { 8310 if (elink_8073_xaui_wa(cb, phy) != 0) 8311 return 0; 8312 } 8313 elink_cl45_read(cb, phy, 8314 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 8315 elink_cl45_read(cb, phy, 8316 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 8317 8318 /* Check the link status on 1.1.2 */ 8319 elink_cl45_read(cb, phy, 8320 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 8321 elink_cl45_read(cb, phy, 8322 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 8323 ELINK_DEBUG_P3(cb, "KR PMA status 0x%x->0x%x," 8324 "an_link_status=0x%x\n", val2, val1, an1000_status); 8325 8326 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); 8327 if (link_up && elink_8073_is_snr_needed(cb, phy)) { 8328 /* The SNR will improve about 2dbby changing the BW and FEE main 8329 * tap. The 1st write to change FFE main tap is set before 8330 * restart AN. Change PLL Bandwidth in EDC register 8331 */ 8332 elink_cl45_write(cb, phy, 8333 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, 8334 0x26BC); 8335 8336 /* Change CDR Bandwidth in EDC register */ 8337 elink_cl45_write(cb, phy, 8338 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, 8339 0x0333); 8340 } 8341 elink_cl45_read(cb, phy, 8342 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 8343 &link_status); 8344 8345 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ 8346 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 8347 link_up = 1; 8348 vars->line_speed = ELINK_SPEED_10000; 8349 ELINK_DEBUG_P1(cb, "port %x: External link up in 10G\n", 8350 params->port); 8351 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { 8352 link_up = 1; 8353 vars->line_speed = ELINK_SPEED_2500; 8354 ELINK_DEBUG_P1(cb, "port %x: External link up in 2.5G\n", 8355 params->port); 8356 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 8357 link_up = 1; 8358 vars->line_speed = ELINK_SPEED_1000; 8359 ELINK_DEBUG_P1(cb, "port %x: External link up in 1G\n", 8360 params->port); 8361 } else { 8362 link_up = 0; 8363 ELINK_DEBUG_P1(cb, "port %x: External link is down\n", 8364 params->port); 8365 } 8366 8367 if (link_up) { 8368 /* Swap polarity if required */ 8369 if (params->lane_config & 8370 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 8371 /* Configure the 8073 to swap P and N of the KR lines */ 8372 elink_cl45_read(cb, phy, 8373 MDIO_XS_DEVAD, 8374 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); 8375 /* Set bit 3 to invert Rx in 1G mode and clear this bit 8376 * when it`s in 10G mode. 8377 */ 8378 if (vars->line_speed == ELINK_SPEED_1000) { 8379 ELINK_DEBUG_P0(cb, "Swapping 1G polarity for" 8380 "the 8073\n"); 8381 val1 |= (1<<3); 8382 } else 8383 val1 &= ~(1<<3); 8384 8385 elink_cl45_write(cb, phy, 8386 MDIO_XS_DEVAD, 8387 MDIO_XS_REG_8073_RX_CTRL_PCIE, 8388 val1); 8389 } 8390 elink_ext_phy_10G_an_resolve(cb, phy, vars); 8391 elink_8073_resolve_fc(phy, params, vars); 8392 vars->duplex = DUPLEX_FULL; 8393 } 8394 8395 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 8396 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 8397 MDIO_AN_REG_LP_AUTO_NEG2, &val1); 8398 8399 if (val1 & (1<<5)) 8400 vars->link_status |= 8401 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 8402 if (val1 & (1<<7)) 8403 vars->link_status |= 8404 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 8405 } 8406 8407 return link_up; 8408 } 8409 8410 static void elink_8073_link_reset(struct elink_phy *phy, 8411 struct elink_params *params) 8412 { 8413 #ifndef EXCLUDE_LINK_RESET 8414 struct elink_dev *cb = params->cb; 8415 u8 gpio_port; 8416 if (CHIP_IS_E2(params->chip_id)) 8417 gpio_port = PATH_ID(cb); 8418 else 8419 gpio_port = params->port; 8420 ELINK_DEBUG_P1(cb, "Setting 8073 port %d into low power mode\n", 8421 gpio_port); 8422 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 8423 MISC_REGISTERS_GPIO_OUTPUT_LOW, 8424 gpio_port); 8425 #endif // EXCLUDE_LINK_RESET 8426 } 8427 #endif // EXCLUDE_NON_COMMON_INIT 8428 #endif // EXCLUDE_BCM8727_BCM8073 8429 8430 /******************************************************************/ 8431 /* BCM8705 PHY SECTION */ 8432 /******************************************************************/ 8433 #ifndef EXCLUDE_BCM8705 8434 static elink_status_t elink_8705_config_init(struct elink_phy *phy, 8435 struct elink_params *params, 8436 struct elink_vars *vars) 8437 { 8438 struct elink_dev *cb = params->cb; 8439 ELINK_DEBUG_P0(cb, "init 8705\n"); 8440 /* Restore normal power mode*/ 8441 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 8442 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 8443 /* HW reset */ 8444 elink_ext_phy_hw_reset(cb, params->port); 8445 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 8446 elink_wait_reset_complete(cb, phy, params); 8447 8448 elink_cl45_write(cb, phy, 8449 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); 8450 elink_cl45_write(cb, phy, 8451 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); 8452 elink_cl45_write(cb, phy, 8453 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); 8454 elink_cl45_write(cb, phy, 8455 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); 8456 /* BCM8705 doesn't have microcode, hence the 0 */ 8457 elink_save_spirom_version(cb, params->port, params->shmem_base, 0); 8458 return ELINK_STATUS_OK; 8459 } 8460 8461 static elink_status_t 8462 elink_8705_read_status(struct elink_phy *phy, struct elink_params *params, 8463 struct elink_vars *vars) 8464 { 8465 u8 link_up = 0; 8466 u16 val1, rx_sd; 8467 struct elink_dev *cb = params->cb; 8468 ELINK_DEBUG_P0(cb, "read status 8705\n"); 8469 elink_cl45_read(cb, phy, 8470 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 8471 ELINK_DEBUG_P1(cb, "8705 LASI status 0x%x\n", val1); 8472 8473 elink_cl45_read(cb, phy, 8474 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 8475 ELINK_DEBUG_P1(cb, "8705 LASI status 0x%x\n", val1); 8476 8477 elink_cl45_read(cb, phy, 8478 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 8479 8480 elink_cl45_read(cb, phy, 8481 MDIO_PMA_DEVAD, 0xc809, &val1); 8482 elink_cl45_read(cb, phy, 8483 MDIO_PMA_DEVAD, 0xc809, &val1); 8484 8485 ELINK_DEBUG_P1(cb, "8705 1.c809 val=0x%x\n", val1); 8486 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); 8487 if (link_up) { 8488 vars->line_speed = ELINK_SPEED_10000; 8489 elink_ext_phy_resolve_fc(phy, params, vars); 8490 } 8491 return link_up; 8492 } 8493 8494 #endif /* EXCLUDE_BCM8705 */ 8495 /******************************************************************/ 8496 /* SFP+ module Section */ 8497 /******************************************************************/ 8498 #ifndef EXCLUDE_NON_COMMON_INIT 8499 #ifndef EXCLUDE_BCM8727_BCM8073 8500 static void elink_set_disable_pmd_transmit(struct elink_params *params, 8501 struct elink_phy *phy, 8502 u8 pmd_dis) 8503 { 8504 struct elink_dev *cb = params->cb; 8505 /* Disable transmitter only for bootcodes which can enable it afterwards 8506 * (for D3 link) 8507 */ 8508 if (pmd_dis) { 8509 if (params->feature_config_flags & 8510 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) { 8511 ELINK_DEBUG_P0(cb, "Disabling PMD transmitter\n"); 8512 } else { 8513 ELINK_DEBUG_P0(cb, "NOT disabling PMD transmitter\n"); 8514 return; 8515 } 8516 } else 8517 ELINK_DEBUG_P0(cb, "Enabling PMD transmitter\n"); 8518 elink_cl45_write(cb, phy, 8519 MDIO_PMA_DEVAD, 8520 MDIO_PMA_REG_TX_DISABLE, pmd_dis); 8521 } 8522 #endif // EXCLUDE_BCM8727_BCM8073 8523 8524 #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) 8525 static u8 elink_get_gpio_port(struct elink_params *params) 8526 { 8527 u8 gpio_port; 8528 u32 swap_val, swap_override; 8529 struct elink_dev *cb = params->cb; 8530 if (CHIP_IS_E2(params->chip_id)) 8531 gpio_port = PATH_ID(cb); 8532 else 8533 gpio_port = params->port; 8534 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP); 8535 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE); 8536 return gpio_port ^ (swap_val && swap_override); 8537 } 8538 8539 static void elink_sfp_e1e2_set_transmitter(struct elink_params *params, 8540 struct elink_phy *phy, 8541 u8 tx_en) 8542 { 8543 u16 val; 8544 u8 port = params->port; 8545 struct elink_dev *cb = params->cb; 8546 u32 tx_en_mode; 8547 8548 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ 8549 tx_en_mode = REG_RD(cb, params->shmem_base + 8550 OFFSETOF(struct shmem_region, 8551 dev_info.port_hw_config[port].sfp_ctrl)) & 8552 PORT_HW_CFG_TX_LASER_MASK; 8553 ELINK_DEBUG_P3(cb, "Setting transmitter tx_en=%x for port %x " 8554 "mode = %x\n", tx_en, port, tx_en_mode); 8555 switch (tx_en_mode) { 8556 case PORT_HW_CFG_TX_LASER_MDIO: 8557 8558 elink_cl45_read(cb, phy, 8559 MDIO_PMA_DEVAD, 8560 MDIO_PMA_REG_PHY_IDENTIFIER, 8561 &val); 8562 8563 if (tx_en) 8564 val &= ~(1<<15); 8565 else 8566 val |= (1<<15); 8567 8568 elink_cl45_write(cb, phy, 8569 MDIO_PMA_DEVAD, 8570 MDIO_PMA_REG_PHY_IDENTIFIER, 8571 val); 8572 break; 8573 case PORT_HW_CFG_TX_LASER_GPIO0: 8574 case PORT_HW_CFG_TX_LASER_GPIO1: 8575 case PORT_HW_CFG_TX_LASER_GPIO2: 8576 case PORT_HW_CFG_TX_LASER_GPIO3: 8577 { 8578 u16 gpio_pin; 8579 u8 gpio_port, gpio_mode; 8580 if (tx_en) 8581 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; 8582 else 8583 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; 8584 8585 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; 8586 gpio_port = elink_get_gpio_port(params); 8587 ELINK_SET_GPIO(cb, gpio_pin, gpio_mode, gpio_port); 8588 break; 8589 } 8590 default: 8591 ELINK_DEBUG_P1(cb, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); 8592 break; 8593 } 8594 } 8595 #endif /* !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) */ 8596 8597 static void elink_sfp_set_transmitter(struct elink_params *params, 8598 struct elink_phy *phy, 8599 u8 tx_en) 8600 { 8601 #ifdef ELINK_ENHANCEMENTS 8602 struct elink_dev *cb = params->cb; 8603 ELINK_DEBUG_P1(cb, "Setting SFP+ transmitter to %d\n", tx_en); 8604 #endif // ELINK_ENHANCEMENTS 8605 #ifndef EXCLUDE_WARPCORE 8606 if (CHIP_IS_E3(params->chip_id)) 8607 elink_sfp_e3_set_transmitter(params, phy, tx_en); 8608 #endif // EXCLUDE_WARPCORE 8609 #ifdef ELINK_ENHANCEMENTS 8610 else 8611 #endif // ELINK_ENHANCEMENTS 8612 #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) 8613 elink_sfp_e1e2_set_transmitter(params, phy, tx_en); 8614 #endif 8615 } 8616 8617 static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy, 8618 struct elink_params *params, 8619 u8 dev_addr, u16 addr, u8 byte_cnt, 8620 u8 *o_buf, u8 is_init) 8621 { 8622 #ifndef EXCLUDE_BCM87x6 8623 struct elink_dev *cb = params->cb; 8624 u16 val = 0; 8625 u16 i; 8626 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { 8627 ELINK_DEBUG_P0(cb, 8628 "Reading from eeprom is limited to 0xf\n"); 8629 return ELINK_STATUS_ERROR; 8630 } 8631 /* Set the read command byte count */ 8632 elink_cl45_write(cb, phy, 8633 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 8634 (byte_cnt | (dev_addr << 8))); 8635 8636 /* Set the read command address */ 8637 elink_cl45_write(cb, phy, 8638 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 8639 addr); 8640 8641 /* Activate read command */ 8642 elink_cl45_write(cb, phy, 8643 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 8644 0x2c0f); 8645 8646 /* Wait up to 500us for command complete status */ 8647 for (i = 0; i < 100; i++) { 8648 elink_cl45_read(cb, phy, 8649 MDIO_PMA_DEVAD, 8650 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8651 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8652 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 8653 break; 8654 USLEEP(cb, 5); 8655 } 8656 8657 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 8658 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 8659 ELINK_DEBUG_P1(cb, 8660 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 8661 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 8662 return ELINK_STATUS_ERROR; 8663 } 8664 8665 /* Read the buffer */ 8666 for (i = 0; i < byte_cnt; i++) { 8667 elink_cl45_read(cb, phy, 8668 MDIO_PMA_DEVAD, 8669 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); 8670 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); 8671 } 8672 8673 for (i = 0; i < 100; i++) { 8674 elink_cl45_read(cb, phy, 8675 MDIO_PMA_DEVAD, 8676 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8677 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8678 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 8679 return ELINK_STATUS_OK; 8680 MSLEEP(cb, 1); 8681 } 8682 #endif // EXCLUDE_BCM87x6 8683 return ELINK_STATUS_ERROR; 8684 } 8685 8686 #ifndef EXCLUDE_WARPCORE 8687 #ifndef EXCLUDE_NON_COMMON_INIT 8688 static void elink_warpcore_power_module(struct elink_params *params, 8689 u8 power) 8690 { 8691 u32 pin_cfg; 8692 struct elink_dev *cb = params->cb; 8693 8694 pin_cfg = (REG_RD(cb, params->shmem_base + 8695 OFFSETOF(struct shmem_region, 8696 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & 8697 PORT_HW_CFG_E3_PWR_DIS_MASK) >> 8698 PORT_HW_CFG_E3_PWR_DIS_SHIFT; 8699 8700 if (pin_cfg == PIN_CFG_NA) 8701 return; 8702 ELINK_DEBUG_P2(cb, "Setting SFP+ module power to %d using pin cfg %d\n", 8703 power, pin_cfg); 8704 /* Low ==> corresponding SFP+ module is powered 8705 * high ==> the SFP+ module is powered down 8706 */ 8707 elink_set_cfg_pin(cb, pin_cfg, power ^ 1); 8708 } 8709 #endif 8710 static elink_status_t elink_warpcore_read_sfp_module_eeprom(struct elink_phy *phy, 8711 struct elink_params *params, 8712 u8 dev_addr, 8713 u16 addr, u8 byte_cnt, 8714 u8 *o_buf, u8 is_init) 8715 { 8716 elink_status_t rc = ELINK_STATUS_OK; 8717 u8 i, j = 0, cnt = 0; 8718 u32 data_array[4]; 8719 u16 addr32; 8720 struct elink_dev *cb = params->cb; 8721 8722 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { 8723 ELINK_DEBUG_P0(cb, 8724 "Reading from eeprom is limited to 16 bytes\n"); 8725 return ELINK_STATUS_ERROR; 8726 } 8727 8728 /* 4 byte aligned address */ 8729 addr32 = addr & (~0x3); 8730 do { 8731 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) { 8732 elink_warpcore_power_module(params, 0); 8733 /* Note that 100us are not enough here */ 8734 MSLEEP(cb, 1); 8735 elink_warpcore_power_module(params, 1); 8736 } 8737 rc = elink_bsc_read(params, cb, dev_addr, addr32, 0, byte_cnt, 8738 data_array); 8739 } while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT)); 8740 8741 if (rc == ELINK_STATUS_OK) { 8742 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { 8743 o_buf[j] = *((u8 *)data_array + i); 8744 j++; 8745 } 8746 } 8747 8748 return rc; 8749 } 8750 #endif /* EXCLUDE_WARPCORE */ 8751 8752 #ifndef EXCLUDE_BCM8727_BCM8073 8753 static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy, 8754 struct elink_params *params, 8755 u8 dev_addr, u16 addr, u8 byte_cnt, 8756 u8 *o_buf, u8 is_init) 8757 { 8758 struct elink_dev *cb = params->cb; 8759 u16 val, i; 8760 8761 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { 8762 ELINK_DEBUG_P0(cb, 8763 "Reading from eeprom is limited to 0xf\n"); 8764 return ELINK_STATUS_ERROR; 8765 } 8766 8767 /* Set 2-wire transfer rate of SFP+ module EEPROM 8768 * to 100Khz since some DACs(direct attached cables) do 8769 * not work at 400Khz. 8770 */ 8771 elink_cl45_write(cb, phy, 8772 MDIO_PMA_DEVAD, 8773 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, 8774 ((dev_addr << 8) | 1)); 8775 8776 /* Need to read from 1.8000 to clear it */ 8777 elink_cl45_read(cb, phy, 8778 MDIO_PMA_DEVAD, 8779 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 8780 &val); 8781 8782 /* Set the read command byte count */ 8783 elink_cl45_write(cb, phy, 8784 MDIO_PMA_DEVAD, 8785 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 8786 ((byte_cnt < 2) ? 2 : byte_cnt)); 8787 8788 /* Set the read command address */ 8789 elink_cl45_write(cb, phy, 8790 MDIO_PMA_DEVAD, 8791 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 8792 addr); 8793 /* Set the destination address */ 8794 elink_cl45_write(cb, phy, 8795 MDIO_PMA_DEVAD, 8796 0x8004, 8797 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); 8798 8799 /* Activate read command */ 8800 elink_cl45_write(cb, phy, 8801 MDIO_PMA_DEVAD, 8802 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 8803 0x8002); 8804 /* Wait appropriate time for two-wire command to finish before 8805 * polling the status register 8806 */ 8807 MSLEEP(cb, 1); 8808 8809 /* Wait up to 500us for command complete status */ 8810 for (i = 0; i < 100; i++) { 8811 elink_cl45_read(cb, phy, 8812 MDIO_PMA_DEVAD, 8813 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8814 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8815 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 8816 break; 8817 USLEEP(cb, 5); 8818 } 8819 8820 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 8821 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 8822 ELINK_DEBUG_P1(cb, 8823 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 8824 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 8825 return ELINK_STATUS_TIMEOUT; 8826 } 8827 8828 /* Read the buffer */ 8829 for (i = 0; i < byte_cnt; i++) { 8830 elink_cl45_read(cb, phy, 8831 MDIO_PMA_DEVAD, 8832 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); 8833 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); 8834 } 8835 8836 for (i = 0; i < 100; i++) { 8837 elink_cl45_read(cb, phy, 8838 MDIO_PMA_DEVAD, 8839 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8840 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8841 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 8842 return ELINK_STATUS_OK; 8843 MSLEEP(cb, 1); 8844 } 8845 8846 return ELINK_STATUS_ERROR; 8847 } 8848 #endif /* EXCLUDE_BCM8727_BCM8073 */ 8849 #endif /* #ifndef EXCLUDE_NON_COMMON_INIT */ 8850 #endif /* ELINK_EMUL_ONLY */ 8851 #ifndef EXCLUDE_FROM_BNX2X 8852 elink_status_t elink_validate_cc_dmi(u8 *sfp_a2_buf) 8853 { 8854 u8 i, checksum = 0; 8855 for (i = 0; i < ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE; i++) 8856 checksum += sfp_a2_buf[i]; 8857 if (checksum == sfp_a2_buf[ELINK_SFP_EEPROM_A2_CC_DMI_ADDR]) 8858 return ELINK_STATUS_OK; 8859 8860 return ELINK_STATUS_ERROR; 8861 } 8862 #endif 8863 #ifndef EXCLUDE_NON_COMMON_INIT 8864 elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy, 8865 struct elink_params *params, u8 dev_addr, 8866 u16 addr, u16 byte_cnt, u8 *o_buf) 8867 { 8868 elink_status_t rc = 0; 8869 #ifdef ELINK_DEBUG 8870 struct elink_dev *cb = params->cb; 8871 #endif 8872 u8 xfer_size; 8873 u8 *user_data = o_buf; 8874 read_sfp_module_eeprom_func_p read_func; 8875 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) { 8876 ELINK_DEBUG_P1(cb, "invalid dev_addr 0x%x\n", dev_addr); 8877 return ELINK_STATUS_ERROR; 8878 } 8879 8880 #ifndef ELINK_EMUL_ONLY 8881 switch (phy->type) { 8882 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 8883 read_func = elink_8726_read_sfp_module_eeprom; 8884 break; 8885 #ifndef EXCLUDE_BCM8727_BCM8073 8886 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8887 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8888 read_func = elink_8727_read_sfp_module_eeprom; 8889 break; 8890 #endif 8891 #ifndef EXCLUDE_WARPCORE 8892 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8893 read_func = elink_warpcore_read_sfp_module_eeprom; 8894 break; 8895 #endif /* EXCLUDE_WARPCORE */ 8896 default: 8897 return ELINK_OP_NOT_SUPPORTED; 8898 } 8899 8900 while (!rc && (byte_cnt > 0)) { 8901 xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ? 8902 ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt; 8903 rc = read_func(phy, params, dev_addr, addr, xfer_size, 8904 user_data, 0); 8905 byte_cnt -= xfer_size; 8906 user_data += xfer_size; 8907 addr += xfer_size; 8908 } 8909 #endif /* ELINK_EMUL_ONLY */ 8910 return rc; 8911 } 8912 #endif // EXCLUDE_NON_COMMON_INIT 8913 #ifndef ELINK_EMUL_ONLY 8914 8915 #ifndef EXCLUDE_NON_COMMON_INIT 8916 static void elink_set_sfp_media(struct elink_phy *phy, 8917 const u8 val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1]) 8918 { 8919 switch (val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]) { 8920 case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER: { 8921 u8 copper_module_type; 8922 /* 8923 * Check if it's active cable (includes SFP+ module) 8924 * or a passive cable. 8925 */ 8926 copper_module_type = val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR]; 8927 if (copper_module_type & 8928 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { 8929 phy->sfp_media = ELINK_ETH_SFP_ACC; 8930 } else { 8931 if (copper_module_type & 8932 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { 8933 phy->sfp_media = ELINK_ETH_SFP_DAC; 8934 } 8935 } 8936 break; 8937 } 8938 case ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN: 8939 case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC: 8940 case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45: 8941 /* 8942 * Some SFP+ modules may support 1 Gbit and 10 Gbit operation. 8943 * We assign something a 1 Gbit designation if it does not 8944 * support any 10 Gbit modes. 8945 */ 8946 if ((val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] & 8947 (ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK | 8948 ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK | 8949 ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK | 8950 ELINK_SFP_EEPROM_10G_COMP_CODE_ER_MASK)) == 0) { 8951 if (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] & 8952 ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T) { 8953 phy->sfp_media = ELINK_ETH_SFP_1GBASE_T; 8954 } else if (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] & 8955 ELINK_SFP_EEPROM_1G_COMP_CODE_SX) { 8956 phy->sfp_media = ELINK_ETH_SFP_1GBASE_SX; 8957 } else if (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] & 8958 ELINK_SFP_EEPROM_1G_COMP_CODE_LX) { 8959 phy->sfp_media = ELINK_ETH_SFP_1GBASE_LX; 8960 } else if (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] & 8961 ELINK_SFP_EEPROM_1G_COMP_CODE_CX) { 8962 phy->sfp_media = ELINK_ETH_SFP_1GBASE_CX; 8963 } 8964 } else { 8965 if (val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] & 8966 ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK) { 8967 phy->sfp_media = ELINK_ETH_SFP_10GBASE_SR; 8968 } else if (val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] & 8969 ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK) { 8970 phy->sfp_media = ELINK_ETH_SFP_10GBASE_LR; 8971 } else if (val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] & 8972 ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK) { 8973 phy->sfp_media = ELINK_ETH_SFP_10GBASE_LRM; 8974 } else if (val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] & 8975 ELINK_SFP_EEPROM_10G_COMP_CODE_ER_MASK) { 8976 phy->sfp_media = ELINK_ETH_SFP_10GBASE_ER; 8977 } 8978 } 8979 break; 8980 default: 8981 break; 8982 } 8983 } 8984 8985 #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_WARPCORE) 8986 static elink_status_t elink_get_edc_mode(struct elink_phy *phy, 8987 struct elink_params *params, 8988 u16 *edc_mode) 8989 { 8990 struct elink_dev *cb = params->cb; 8991 u32 sync_offset = 0, phy_idx, media_types; 8992 u8 val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0; 8993 *edc_mode = ELINK_EDC_MODE_LIMITING; 8994 phy->media_type = ELINK_ETH_PHY_UNSPECIFIED; 8995 phy->sfp_media = ELINK_ETH_SFP_UNKNOWN; 8996 /* First check for copper cable */ 8997 if (elink_read_sfp_module_eeprom(phy, 8998 params, 8999 ELINK_I2C_DEV_ADDR_A0, 9000 0, 9001 ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1, 9002 (u8 *)val) != 0) { 9003 ELINK_DEBUG_P0(cb, "Failed to read from SFP+ module EEPROM\n"); 9004 return ELINK_STATUS_ERROR; 9005 } 9006 #ifndef EXCLUDE_WARPCORE 9007 params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK; 9008 params->link_attr_sync |= val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] << 9009 LINK_SFP_EEPROM_COMP_CODE_SHIFT; 9010 elink_update_link_attr(params, params->link_attr_sync); 9011 #endif 9012 switch (val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]) { 9013 case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER: 9014 { 9015 u8 copper_module_type; 9016 phy->media_type = ELINK_ETH_PHY_DA_TWINAX; 9017 /* Check if it's active cable (includes SFP+ module) 9018 * or a passive cable. 9019 */ 9020 copper_module_type = val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR]; 9021 if (copper_module_type & 9022 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { 9023 ELINK_DEBUG_P0(cb, "Active Copper cable detected\n"); 9024 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 9025 *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC; 9026 else 9027 check_limiting_mode = 1; 9028 } else { 9029 *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC; 9030 /* Even in case PASSIVE_DAC indication is not set, 9031 * treat it as a passive DAC cable, since some cables 9032 * don't have this indication. 9033 */ 9034 if (copper_module_type & 9035 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { 9036 ELINK_DEBUG_P0(cb, 9037 "Passive Copper cable detected\n"); 9038 } else { 9039 ELINK_DEBUG_P0(cb, 9040 "Unknown copper-cable-type\n"); 9041 } 9042 } 9043 break; 9044 } 9045 case ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN: 9046 case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC: 9047 case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45: 9048 check_limiting_mode = 1; 9049 /* 9050 * Some SFP+ modules may support 1 Gbit and 10 Gbit operation. 9051 * We assign something a 1 Gbit designation if it does not 9052 * support any 10 Gbit modes. 9053 */ 9054 if ((val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] & 9055 (ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK | 9056 ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK | 9057 ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK | 9058 ELINK_SFP_EEPROM_10G_COMP_CODE_ER_MASK)) == 0) { 9059 ELINK_DEBUG_P0(cb, "1G SFP module detected\n"); 9060 phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER; 9061 if (phy->req_line_speed != ELINK_SPEED_1000) { 9062 #ifndef ELINK_AUX_POWER 9063 u8 gport = params->port; 9064 #endif 9065 phy->req_line_speed = ELINK_SPEED_1000; 9066 #ifndef ELINK_AUX_POWER 9067 if (!CHIP_IS_E1X(params->chip_id)) { 9068 gport = PATH_ID(cb) + 9069 (params->port << 1); 9070 } 9071 elink_cb_event_log(cb, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps." 9072 // " Current SFP module in port %d is not" 9073 // " compliant with 10G Ethernet\n", 9074 #endif 9075 } 9076 9077 if (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] & 9078 ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T) { 9079 /* Some 1G-baseT modules will not link up, 9080 * unless TX_EN is toggled with long delay in 9081 * between. 9082 */ 9083 elink_sfp_set_transmitter(params, phy, 0); 9084 MSLEEP(cb, 40); 9085 elink_sfp_set_transmitter(params, phy, 1); 9086 } 9087 } else { 9088 int idx, cfg_idx = 0; 9089 ELINK_DEBUG_P0(cb, "10G Optic module detected\n"); 9090 for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) { 9091 if (params->phy[idx].type == phy->type) { 9092 cfg_idx = ELINK_LINK_CONFIG_IDX(idx); 9093 break; 9094 } 9095 } 9096 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER; 9097 phy->req_line_speed = params->req_line_speed[cfg_idx]; 9098 } 9099 break; 9100 default: 9101 ELINK_DEBUG_P1(cb, "Unable to determine module type 0x%x !!!\n", 9102 val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]); 9103 return ELINK_STATUS_ERROR; 9104 } 9105 elink_set_sfp_media(phy, val); 9106 sync_offset = params->shmem_base + 9107 OFFSETOF(struct shmem_region, 9108 dev_info.port_hw_config[params->port].media_type); 9109 media_types = REG_RD(cb, sync_offset); 9110 /* Update media type for non-PMF sync */ 9111 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 9112 if (&(params->phy[phy_idx]) == phy) { 9113 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 9114 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 9115 media_types |= ((phy->media_type & 9116 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 9117 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 9118 break; 9119 } 9120 } 9121 REG_WR(cb, sync_offset, media_types); 9122 if (check_limiting_mode) { 9123 u8 options[ELINK_SFP_EEPROM_OPTIONS_SIZE]; 9124 if (elink_read_sfp_module_eeprom(phy, 9125 params, 9126 ELINK_I2C_DEV_ADDR_A0, 9127 ELINK_SFP_EEPROM_OPTIONS_ADDR, 9128 ELINK_SFP_EEPROM_OPTIONS_SIZE, 9129 options) != 0) { 9130 ELINK_DEBUG_P0(cb, 9131 "Failed to read Option field from module EEPROM\n"); 9132 return ELINK_STATUS_ERROR; 9133 } 9134 if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) 9135 *edc_mode = ELINK_EDC_MODE_LINEAR; 9136 else 9137 *edc_mode = ELINK_EDC_MODE_LIMITING; 9138 } 9139 ELINK_DEBUG_P1(cb, "EDC mode is set to 0x%x\n", *edc_mode); 9140 return ELINK_STATUS_OK; 9141 } 9142 #ifdef ELINK_ENHANCEMENTS 9143 9144 /* 9145 * This function determines the type of media that is present in the SFP module 9146 * for us to cache and use as part of the illumos MAC media information. This is 9147 * done because elink_get_edc_mode() isn't aways actually called. 9148 */ 9149 static elink_status_t elink_determine_sfp_media(struct elink_phy *phy, 9150 struct elink_params *params) 9151 { 9152 struct elink_dev *cb = params->cb; 9153 u8 val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1]; 9154 9155 phy->sfp_media = ELINK_ETH_SFP_UNKNOWN; 9156 if (elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0, 9157 0, ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1, (u8 *)val) != 0) { 9158 ELINK_DEBUG_P0(cb, "Failed to read from SFP+ module EEPROM\n"); 9159 return ELINK_STATUS_ERROR; 9160 } 9161 9162 elink_set_sfp_media(phy, val); 9163 9164 return ELINK_STATUS_OK; 9165 } 9166 9167 /* This function read the relevant field from the module (SFP+), and verify it 9168 * is compliant with this board 9169 */ 9170 static elink_status_t elink_verify_sfp_module(struct elink_phy *phy, 9171 struct elink_params *params) 9172 { 9173 struct elink_dev *cb = params->cb; 9174 u32 val, cmd; 9175 u32 fw_resp, fw_cmd_param; 9176 char vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE+1]; 9177 char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE+1]; 9178 phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED; 9179 val = REG_RD(cb, params->shmem_base + 9180 OFFSETOF(struct shmem_region, dev_info. 9181 port_feature_config[params->port].config)); 9182 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9183 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { 9184 ELINK_DEBUG_P0(cb, "NOT enforcing module verification\n"); 9185 return ELINK_STATUS_OK; 9186 } 9187 9188 if (params->feature_config_flags & 9189 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { 9190 /* Use specific phy request */ 9191 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; 9192 } else if (params->feature_config_flags & 9193 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { 9194 /* Use first phy request only in case of non-dual media*/ 9195 if (ELINK_DUAL_MEDIA(params)) { 9196 ELINK_DEBUG_P0(cb, 9197 "FW does not support OPT MDL verification\n"); 9198 return ELINK_STATUS_ERROR; 9199 } 9200 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; 9201 } else { 9202 /* No support in OPT MDL detection */ 9203 ELINK_DEBUG_P0(cb, 9204 "FW does not support OPT MDL verification\n"); 9205 return ELINK_STATUS_ERROR; 9206 } 9207 9208 fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); 9209 fw_resp = elink_cb_fw_command(cb, cmd, fw_cmd_param); 9210 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { 9211 ELINK_DEBUG_P0(cb, "Approved module\n"); 9212 return ELINK_STATUS_OK; 9213 } 9214 9215 /* Format the warning message */ 9216 if (elink_read_sfp_module_eeprom(phy, 9217 params, 9218 ELINK_I2C_DEV_ADDR_A0, 9219 ELINK_SFP_EEPROM_VENDOR_NAME_ADDR, 9220 ELINK_SFP_EEPROM_VENDOR_NAME_SIZE, 9221 (u8 *)vendor_name)) 9222 vendor_name[0] = '\0'; 9223 else 9224 vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; 9225 if (elink_read_sfp_module_eeprom(phy, 9226 params, 9227 ELINK_I2C_DEV_ADDR_A0, 9228 ELINK_SFP_EEPROM_PART_NO_ADDR, 9229 ELINK_SFP_EEPROM_PART_NO_SIZE, 9230 (u8 *)vendor_pn)) 9231 vendor_pn[0] = '\0'; 9232 else 9233 vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0'; 9234 9235 elink_cb_event_log(cb, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected," 9236 // " Port %d from %s part number %s\n", 9237 9238 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != 9239 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) 9240 phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED; 9241 return ELINK_STATUS_ERROR; 9242 } 9243 #endif /* ELINK_ENHANCEMENTS */ 9244 9245 #ifndef EXCLUDE_BCM8727_BCM8073 9246 static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy *phy, 9247 struct elink_params *params) 9248 9249 { 9250 u8 val; 9251 elink_status_t rc; 9252 struct elink_dev *cb = params->cb; 9253 u16 timeout; 9254 /* Initialization time after hot-plug may take up to 300ms for 9255 * some phys type ( e.g. JDSU ) 9256 */ 9257 9258 for (timeout = 0; timeout < 60; timeout++) { 9259 #ifndef EXCLUDE_WARPCORE 9260 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 9261 rc = elink_warpcore_read_sfp_module_eeprom( 9262 phy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val, 9263 1); 9264 else 9265 #endif 9266 rc = elink_read_sfp_module_eeprom(phy, params, 9267 ELINK_I2C_DEV_ADDR_A0, 9268 1, 1, &val); 9269 if (rc == 0) { 9270 ELINK_DEBUG_P1(cb, 9271 "SFP+ module initialization took %d ms\n", 9272 timeout * 5); 9273 return ELINK_STATUS_OK; 9274 } 9275 MSLEEP(cb, 5); 9276 } 9277 rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0, 9278 1, 1, &val); 9279 return rc; 9280 } 9281 #endif /* EXCLUDE_BCM8727_BCM8073 */ 9282 #endif /* #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_WARPCORE) */ 9283 9284 #ifndef EXCLUDE_BCM8727_BCM8073 9285 static void elink_8727_power_module(struct elink_dev *cb, 9286 struct elink_phy *phy, 9287 u8 is_power_up) { 9288 /* Make sure GPIOs are not using for LED mode */ 9289 u16 val; 9290 /* In the GPIO register, bit 4 is use to determine if the GPIOs are 9291 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for 9292 * output 9293 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 9294 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 9295 * where the 1st bit is the over-current(only input), and 2nd bit is 9296 * for power( only output ) 9297 * 9298 * In case of NOC feature is disabled and power is up, set GPIO control 9299 * as input to enable listening of over-current indication 9300 */ 9301 if (phy->flags & ELINK_FLAGS_NOC) 9302 return; 9303 if (is_power_up) 9304 val = (1<<4); 9305 else 9306 /* Set GPIO control to OUTPUT, and set the power bit 9307 * to according to the is_power_up 9308 */ 9309 val = (1<<1); 9310 9311 elink_cl45_write(cb, phy, 9312 MDIO_PMA_DEVAD, 9313 MDIO_PMA_REG_8727_GPIO_CTRL, 9314 val); 9315 } 9316 #endif /* EXCLUDE_BCM8727_BCM8073 */ 9317 9318 #ifndef EXCLUDE_BCM87x6 9319 static elink_status_t elink_8726_set_limiting_mode(struct elink_dev *cb, 9320 struct elink_phy *phy, 9321 u16 edc_mode) 9322 { 9323 u16 cur_limiting_mode; 9324 9325 elink_cl45_read(cb, phy, 9326 MDIO_PMA_DEVAD, 9327 MDIO_PMA_REG_ROM_VER2, 9328 &cur_limiting_mode); 9329 ELINK_DEBUG_P1(cb, "Current Limiting mode is 0x%x\n", 9330 cur_limiting_mode); 9331 9332 if (edc_mode == ELINK_EDC_MODE_LIMITING) { 9333 ELINK_DEBUG_P0(cb, "Setting LIMITING MODE\n"); 9334 elink_cl45_write(cb, phy, 9335 MDIO_PMA_DEVAD, 9336 MDIO_PMA_REG_ROM_VER2, 9337 ELINK_EDC_MODE_LIMITING); 9338 } else { /* LRM mode ( default )*/ 9339 9340 ELINK_DEBUG_P0(cb, "Setting LRM MODE\n"); 9341 9342 /* Changing to LRM mode takes quite few seconds. So do it only 9343 * if current mode is limiting (default is LRM) 9344 */ 9345 if (cur_limiting_mode != ELINK_EDC_MODE_LIMITING) 9346 return ELINK_STATUS_OK; 9347 9348 elink_cl45_write(cb, phy, 9349 MDIO_PMA_DEVAD, 9350 MDIO_PMA_REG_LRM_MODE, 9351 0); 9352 elink_cl45_write(cb, phy, 9353 MDIO_PMA_DEVAD, 9354 MDIO_PMA_REG_ROM_VER2, 9355 0x128); 9356 elink_cl45_write(cb, phy, 9357 MDIO_PMA_DEVAD, 9358 MDIO_PMA_REG_MISC_CTRL0, 9359 0x4008); 9360 elink_cl45_write(cb, phy, 9361 MDIO_PMA_DEVAD, 9362 MDIO_PMA_REG_LRM_MODE, 9363 0xaaaa); 9364 } 9365 return ELINK_STATUS_OK; 9366 } 9367 #endif /* #ifndef EXCLUDE_BCM87x6 */ 9368 9369 #ifndef EXCLUDE_BCM8727_BCM8073 9370 static elink_status_t elink_8727_set_limiting_mode(struct elink_dev *cb, 9371 struct elink_phy *phy, 9372 u16 edc_mode) 9373 { 9374 u16 phy_identifier; 9375 u16 rom_ver2_val; 9376 elink_cl45_read(cb, phy, 9377 MDIO_PMA_DEVAD, 9378 MDIO_PMA_REG_PHY_IDENTIFIER, 9379 &phy_identifier); 9380 9381 elink_cl45_write(cb, phy, 9382 MDIO_PMA_DEVAD, 9383 MDIO_PMA_REG_PHY_IDENTIFIER, 9384 (phy_identifier & ~(1<<9))); 9385 9386 elink_cl45_read(cb, phy, 9387 MDIO_PMA_DEVAD, 9388 MDIO_PMA_REG_ROM_VER2, 9389 &rom_ver2_val); 9390 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ 9391 elink_cl45_write(cb, phy, 9392 MDIO_PMA_DEVAD, 9393 MDIO_PMA_REG_ROM_VER2, 9394 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); 9395 9396 elink_cl45_write(cb, phy, 9397 MDIO_PMA_DEVAD, 9398 MDIO_PMA_REG_PHY_IDENTIFIER, 9399 (phy_identifier | (1<<9))); 9400 9401 return ELINK_STATUS_OK; 9402 } 9403 9404 static void elink_8727_specific_func(struct elink_phy *phy, 9405 struct elink_params *params, 9406 u32 action) 9407 { 9408 struct elink_dev *cb = params->cb; 9409 u16 val; 9410 switch (action) { 9411 case ELINK_DISABLE_TX: 9412 elink_sfp_set_transmitter(params, phy, 0); 9413 break; 9414 case ELINK_ENABLE_TX: 9415 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) 9416 elink_sfp_set_transmitter(params, phy, 1); 9417 break; 9418 case ELINK_PHY_INIT: 9419 elink_cl45_write(cb, phy, 9420 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9421 (1<<2) | (1<<5)); 9422 elink_cl45_write(cb, phy, 9423 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 9424 0); 9425 elink_cl45_write(cb, phy, 9426 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); 9427 /* Make MOD_ABS give interrupt on change */ 9428 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 9429 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9430 &val); 9431 val |= (1<<12); 9432 if (phy->flags & ELINK_FLAGS_NOC) 9433 val |= (3<<5); 9434 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 9435 * status which reflect SFP+ module over-current 9436 */ 9437 if (!(phy->flags & ELINK_FLAGS_NOC)) 9438 val &= 0xff8f; /* Reset bits 4-6 */ 9439 elink_cl45_write(cb, phy, 9440 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9441 val); 9442 break; 9443 default: 9444 ELINK_DEBUG_P1(cb, "Function 0x%x not supported by 8727\n", 9445 action); 9446 return; 9447 } 9448 } 9449 9450 #ifdef ELINK_ENHANCEMENTS 9451 static void elink_set_e1e2_module_fault_led(struct elink_params *params, 9452 u8 gpio_mode) 9453 { 9454 struct elink_dev *cb = params->cb; 9455 9456 u32 fault_led_gpio = REG_RD(cb, params->shmem_base + 9457 OFFSETOF(struct shmem_region, 9458 dev_info.port_hw_config[params->port].sfp_ctrl)) & 9459 PORT_HW_CFG_FAULT_MODULE_LED_MASK; 9460 switch (fault_led_gpio) { 9461 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: 9462 return; 9463 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: 9464 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: 9465 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: 9466 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: 9467 { 9468 u8 gpio_port = elink_get_gpio_port(params); 9469 u16 gpio_pin = fault_led_gpio - 9470 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; 9471 ELINK_DEBUG_P3(cb, "Set fault module-detected led " 9472 "pin %x port %x mode %x\n", 9473 gpio_pin, gpio_port, gpio_mode); 9474 ELINK_SET_GPIO(cb, gpio_pin, gpio_mode, gpio_port); 9475 } 9476 break; 9477 default: 9478 ELINK_DEBUG_P1(cb, "Error: Invalid fault led mode 0x%x\n", 9479 fault_led_gpio); 9480 } 9481 } 9482 #endif /* #ifdef ELINK_ENHANCEMENTS */ 9483 #endif // EXCLUDE_BCM8727_BCM8073 9484 #endif // EXCLUDE_NON_COMMON_INIT 9485 9486 #ifdef ELINK_ENHANCEMENTS 9487 static void elink_set_e3_module_fault_led(struct elink_params *params, 9488 u8 gpio_mode) 9489 { 9490 u32 pin_cfg; 9491 u8 port = params->port; 9492 struct elink_dev *cb = params->cb; 9493 pin_cfg = (REG_RD(cb, params->shmem_base + 9494 OFFSETOF(struct shmem_region, 9495 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 9496 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> 9497 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; 9498 ELINK_DEBUG_P2(cb, "Setting Fault LED to %d using pin cfg %d\n", 9499 gpio_mode, pin_cfg); 9500 elink_set_cfg_pin(cb, pin_cfg, gpio_mode); 9501 } 9502 9503 static void elink_set_sfp_module_fault_led(struct elink_params *params, 9504 u8 gpio_mode) 9505 { 9506 struct elink_dev *cb = params->cb; 9507 ELINK_DEBUG_P1(cb, "Setting SFP+ module fault LED to %d\n", gpio_mode); 9508 if (CHIP_IS_E3(params->chip_id)) { 9509 /* Low ==> if SFP+ module is supported otherwise 9510 * High ==> if SFP+ module is not on the approved vendor list 9511 */ 9512 elink_set_e3_module_fault_led(params, gpio_mode); 9513 } else 9514 elink_set_e1e2_module_fault_led(params, gpio_mode); 9515 } 9516 #endif /* #ifdef ELINK_ENHANCEMENTS */ 9517 9518 #ifndef EXCLUDE_WARPCORE 9519 #ifndef EXCLUDE_NON_COMMON_INIT 9520 static void elink_warpcore_hw_reset(struct elink_phy *phy, 9521 struct elink_params *params) 9522 { 9523 struct elink_dev *cb = params->cb; 9524 elink_warpcore_power_module(params, 0); 9525 /* Put Warpcore in low power mode */ 9526 REG_WR(cb, MISC_REG_WC0_RESET, 0x0c0e); 9527 9528 /* Put LCPLL in low power mode */ 9529 REG_WR(cb, MISC_REG_LCPLL_E40_PWRDWN, 1); 9530 REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_ANA, 0); 9531 REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_DIG, 0); 9532 } 9533 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 9534 #endif // #ifndef EXCLUDE_WARPCORE 9535 9536 #ifndef EXCLUDE_NON_COMMON_INIT 9537 static void elink_power_sfp_module(struct elink_params *params, 9538 struct elink_phy *phy, 9539 u8 power) 9540 { 9541 #ifdef ELINK_DEBUG 9542 struct elink_dev *cb = params->cb; 9543 #endif /* ELINK_DEBUG */ 9544 ELINK_DEBUG_P1(cb, "Setting SFP+ power to %x\n", power); 9545 9546 switch (phy->type) { 9547 #ifndef EXCLUDE_BCM8727_BCM8073 9548 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 9549 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 9550 elink_8727_power_module(params->cb, phy, power); 9551 break; 9552 #endif // EXCLUDE_BCM8727_BCM8073 9553 #ifndef EXCLUDE_WARPCORE 9554 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 9555 elink_warpcore_power_module(params, power); 9556 break; 9557 #endif // EXCLUDE_WARPCORE 9558 default: 9559 break; 9560 } 9561 } 9562 #ifndef EXCLUDE_WARPCORE 9563 static void elink_warpcore_set_limiting_mode(struct elink_params *params, 9564 struct elink_phy *phy, 9565 u16 edc_mode) 9566 { 9567 u16 val = 0; 9568 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 9569 struct elink_dev *cb = params->cb; 9570 9571 u8 lane = elink_get_warpcore_lane(phy, params); 9572 /* This is a global register which controls all lanes */ 9573 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 9574 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 9575 val &= ~(0xf << (lane << 2)); 9576 9577 switch (edc_mode) { 9578 case ELINK_EDC_MODE_LINEAR: 9579 case ELINK_EDC_MODE_LIMITING: 9580 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 9581 break; 9582 case ELINK_EDC_MODE_PASSIVE_DAC: 9583 case ELINK_EDC_MODE_ACTIVE_DAC: 9584 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; 9585 break; 9586 default: 9587 break; 9588 } 9589 9590 val |= (mode << (lane << 2)); 9591 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 9592 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); 9593 /* A must read */ 9594 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 9595 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 9596 9597 /* Restart microcode to re-read the new mode */ 9598 elink_warpcore_reset_lane(cb, phy, 1); 9599 elink_warpcore_reset_lane(cb, phy, 0); 9600 9601 } 9602 #endif // EXCLUDE_WARPCORE 9603 9604 static void elink_set_limiting_mode(struct elink_params *params, 9605 struct elink_phy *phy, 9606 u16 edc_mode) 9607 { 9608 switch (phy->type) { 9609 #ifndef EXCLUDE_BCM87x6 9610 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 9611 elink_8726_set_limiting_mode(params->cb, phy, edc_mode); 9612 break; 9613 #endif /* #ifndef EXCLUDE_BCM87x6 */ 9614 #ifndef EXCLUDE_BCM8727_BCM8073 9615 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 9616 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 9617 elink_8727_set_limiting_mode(params->cb, phy, edc_mode); 9618 break; 9619 #endif // EXCLUDE_BCM8727_BCM8073 9620 #ifndef EXCLUDE_WARPCORE 9621 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 9622 elink_warpcore_set_limiting_mode(params, phy, edc_mode); 9623 break; 9624 #endif // EXCLUDE_WARPCORE 9625 } 9626 } 9627 9628 elink_status_t elink_sfp_module_detection(struct elink_phy *phy, 9629 struct elink_params *params) 9630 { 9631 struct elink_dev *cb = params->cb; 9632 u16 edc_mode; 9633 elink_status_t rc = ELINK_STATUS_OK; 9634 9635 u32 val = REG_RD(cb, params->shmem_base + 9636 OFFSETOF(struct shmem_region, dev_info. 9637 port_feature_config[params->port].config)); 9638 /* Enabled transmitter by default */ 9639 elink_sfp_set_transmitter(params, phy, 1); 9640 ELINK_DEBUG_P1(cb, "SFP+ module plugged in/out detected on port %d\n", 9641 params->port); 9642 /* Power up module */ 9643 elink_power_sfp_module(params, phy, 1); 9644 if (elink_get_edc_mode(phy, params, &edc_mode) != 0) { 9645 ELINK_DEBUG_P0(cb, "Failed to get valid module type\n"); 9646 return ELINK_STATUS_ERROR; 9647 #ifdef ELINK_ENHANCEMENTS 9648 } else if (elink_verify_sfp_module(phy, params) != 0) { 9649 /* Check SFP+ module compatibility */ 9650 ELINK_DEBUG_P0(cb, "Module verification failed!!\n"); 9651 rc = ELINK_STATUS_ERROR; 9652 /* Turn on fault module-detected led */ 9653 elink_set_sfp_module_fault_led(params, 9654 MISC_REGISTERS_GPIO_HIGH); 9655 9656 /* Check if need to power down the SFP+ module */ 9657 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9658 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { 9659 ELINK_DEBUG_P0(cb, "Shutdown SFP+ module!!\n"); 9660 elink_power_sfp_module(params, phy, 0); 9661 return rc; 9662 } 9663 } else { 9664 /* Turn off fault module-detected led */ 9665 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); 9666 #endif // ELINK_ENHANCEMENTS 9667 } 9668 9669 /* Check and set limiting mode / LRM mode on 8726. On 8727 it 9670 * is done automatically 9671 */ 9672 elink_set_limiting_mode(params, phy, edc_mode); 9673 9674 /* Disable transmit for this module if the module is not approved, and 9675 * laser needs to be disabled. 9676 */ 9677 if ((rc != 0) && 9678 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9679 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)) 9680 elink_sfp_set_transmitter(params, phy, 0); 9681 9682 return rc; 9683 } 9684 #endif // EXCLUDE_NON_COMMON_INIT 9685 9686 #ifdef ELINK_ENHANCEMENTS 9687 void elink_handle_module_detect_int(struct elink_params *params) 9688 { 9689 struct elink_dev *cb = params->cb; 9690 struct elink_phy *phy; 9691 u32 gpio_val; 9692 u8 gpio_num, gpio_port; 9693 if (CHIP_IS_E3(params->chip_id)) { 9694 phy = ¶ms->phy[ELINK_INT_PHY]; 9695 /* Always enable TX laser,will be disabled in case of fault */ 9696 elink_sfp_set_transmitter(params, phy, 1); 9697 } else { 9698 phy = ¶ms->phy[ELINK_EXT_PHY1]; 9699 } 9700 if (elink_get_mod_abs_int_cfg(cb, params->chip_id, params->shmem_base, 9701 params->port, &gpio_num, &gpio_port) == 9702 ELINK_STATUS_ERROR) { 9703 ELINK_DEBUG_P0(cb, "Failed to get MOD_ABS interrupt config\n"); 9704 return; 9705 } 9706 9707 /* Set valid module led off */ 9708 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); 9709 9710 /* Get current gpio val reflecting module plugged in / out*/ 9711 gpio_val = ELINK_GET_GPIO(cb, gpio_num, gpio_port); 9712 9713 /* Call the handling function in case module is detected */ 9714 if (gpio_val == 0) { 9715 #ifdef ELINK_AUX_POWER 9716 phy->flags |= ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC; 9717 #endif 9718 elink_set_mdio_emac_per_phy(cb, params); 9719 elink_set_aer_mmd(params, phy); 9720 9721 elink_power_sfp_module(params, phy, 1); 9722 ELINK_SET_GPIO_INT(cb, gpio_num, 9723 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, 9724 gpio_port); 9725 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) { 9726 elink_sfp_module_detection(phy, params); 9727 if (CHIP_IS_E3(params->chip_id)) { 9728 u16 rx_tx_in_reset; 9729 /* In case WC is out of reset, reconfigure the 9730 * link speed while taking into account 1G 9731 * module limitation. 9732 */ 9733 elink_cl45_read(cb, phy, 9734 MDIO_WC_DEVAD, 9735 MDIO_WC_REG_DIGITAL5_MISC6, 9736 &rx_tx_in_reset); 9737 if ((!rx_tx_in_reset) && 9738 (params->link_flags & 9739 ELINK_PHY_INITIALIZED)) { 9740 elink_warpcore_reset_lane(cb, phy, 1); 9741 elink_warpcore_config_sfi(phy, params); 9742 elink_warpcore_reset_lane(cb, phy, 0); 9743 } 9744 } 9745 } else { 9746 ELINK_DEBUG_P0(cb, "SFP+ module is not initialized\n"); 9747 } 9748 } else { 9749 #ifdef ELINK_AUX_POWER 9750 phy->flags &= ~ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC; 9751 #endif 9752 ELINK_SET_GPIO_INT(cb, gpio_num, 9753 MISC_REGISTERS_GPIO_INT_OUTPUT_SET, 9754 gpio_port); 9755 /* Module was plugged out. 9756 * Disable transmit for this module 9757 */ 9758 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT; 9759 } 9760 } 9761 #endif // ELINK_ENHANCEMENTS 9762 9763 /******************************************************************/ 9764 /* Used by 8706 and 8727 */ 9765 /******************************************************************/ 9766 #ifndef EXCLUDE_NON_COMMON_INIT 9767 #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) 9768 static void elink_sfp_mask_fault(struct elink_dev *cb, 9769 struct elink_phy *phy, 9770 u16 alarm_status_offset, 9771 u16 alarm_ctrl_offset) 9772 { 9773 u16 alarm_status, val; 9774 elink_cl45_read(cb, phy, 9775 MDIO_PMA_DEVAD, alarm_status_offset, 9776 &alarm_status); 9777 elink_cl45_read(cb, phy, 9778 MDIO_PMA_DEVAD, alarm_status_offset, 9779 &alarm_status); 9780 /* Mask or enable the fault event. */ 9781 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); 9782 if (alarm_status & (1<<0)) 9783 val &= ~(1<<0); 9784 else 9785 val |= (1<<0); 9786 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); 9787 } 9788 #endif // #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073 9789 /******************************************************************/ 9790 /* common BCM8706/BCM8726 PHY SECTION */ 9791 /******************************************************************/ 9792 #ifndef EXCLUDE_BCM87x6 9793 static u8 elink_8706_8726_read_status(struct elink_phy *phy, 9794 struct elink_params *params, 9795 struct elink_vars *vars) 9796 { 9797 u8 link_up = 0; 9798 u16 val1, val2, rx_sd, pcs_status; 9799 struct elink_dev *cb = params->cb; 9800 ELINK_DEBUG_P0(cb, "XGXS 8706/8726\n"); 9801 /* Clear RX Alarm*/ 9802 elink_cl45_read(cb, phy, 9803 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 9804 9805 elink_sfp_mask_fault(cb, phy, MDIO_PMA_LASI_TXSTAT, 9806 MDIO_PMA_LASI_TXCTRL); 9807 9808 /* Clear LASI indication*/ 9809 elink_cl45_read(cb, phy, 9810 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 9811 elink_cl45_read(cb, phy, 9812 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 9813 ELINK_DEBUG_P2(cb, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); 9814 9815 elink_cl45_read(cb, phy, 9816 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 9817 elink_cl45_read(cb, phy, 9818 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); 9819 elink_cl45_read(cb, phy, 9820 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 9821 elink_cl45_read(cb, phy, 9822 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 9823 9824 ELINK_DEBUG_P3(cb, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" 9825 " link_status 0x%x\n", rx_sd, pcs_status, val2); 9826 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status 9827 * are set, or if the autoneg bit 1 is set 9828 */ 9829 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); 9830 if (link_up) { 9831 if (val2 & (1<<1)) 9832 vars->line_speed = ELINK_SPEED_1000; 9833 else 9834 vars->line_speed = ELINK_SPEED_10000; 9835 elink_ext_phy_resolve_fc(phy, params, vars); 9836 vars->duplex = DUPLEX_FULL; 9837 } 9838 9839 /* Capture 10G link fault. Read twice to clear stale value. */ 9840 if (vars->line_speed == ELINK_SPEED_10000) { 9841 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 9842 MDIO_PMA_LASI_TXSTAT, &val1); 9843 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 9844 MDIO_PMA_LASI_TXSTAT, &val1); 9845 if (val1 & (1<<0)) 9846 vars->fault_detected = 1; 9847 } 9848 9849 return link_up; 9850 } 9851 9852 /******************************************************************/ 9853 /* BCM8706 PHY SECTION */ 9854 /******************************************************************/ 9855 static elink_status_t 9856 elink_8706_config_init(struct elink_phy *phy, struct elink_params *params, 9857 struct elink_vars *vars) 9858 { 9859 u32 tx_en_mode; 9860 u16 cnt, val, tmp1; 9861 struct elink_dev *cb = params->cb; 9862 9863 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 9864 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 9865 /* HW reset */ 9866 elink_ext_phy_hw_reset(cb, params->port); 9867 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 9868 elink_wait_reset_complete(cb, phy, params); 9869 9870 /* Wait until fw is loaded */ 9871 for (cnt = 0; cnt < 100; cnt++) { 9872 elink_cl45_read(cb, phy, 9873 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); 9874 if (val) 9875 break; 9876 MSLEEP(cb, 10); 9877 } 9878 ELINK_DEBUG_P1(cb, "XGXS 8706 is initialized after %d ms\n", cnt); 9879 if ((params->feature_config_flags & 9880 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 9881 u8 i; 9882 u16 reg; 9883 for (i = 0; i < 4; i++) { 9884 reg = MDIO_XS_8706_REG_BANK_RX0 + 9885 i*(MDIO_XS_8706_REG_BANK_RX1 - 9886 MDIO_XS_8706_REG_BANK_RX0); 9887 elink_cl45_read(cb, phy, MDIO_XS_DEVAD, reg, &val); 9888 /* Clear first 3 bits of the control */ 9889 val &= ~0x7; 9890 /* Set control bits according to configuration */ 9891 val |= (phy->rx_preemphasis[i] & 0x7); 9892 ELINK_DEBUG_P2(cb, "Setting RX Equalizer to BCM8706" 9893 " reg 0x%x <-- val 0x%x\n", reg, val); 9894 elink_cl45_write(cb, phy, MDIO_XS_DEVAD, reg, val); 9895 } 9896 } 9897 /* Force speed */ 9898 if (phy->req_line_speed == ELINK_SPEED_10000) { 9899 ELINK_DEBUG_P0(cb, "XGXS 8706 force 10Gbps\n"); 9900 9901 elink_cl45_write(cb, phy, 9902 MDIO_PMA_DEVAD, 9903 MDIO_PMA_REG_DIGITAL_CTRL, 0x400); 9904 elink_cl45_write(cb, phy, 9905 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 9906 0); 9907 /* Arm LASI for link and Tx fault. */ 9908 elink_cl45_write(cb, phy, 9909 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); 9910 } else { 9911 /* Force 1Gbps using autoneg with 1G advertisement */ 9912 9913 /* Allow CL37 through CL73 */ 9914 ELINK_DEBUG_P0(cb, "XGXS 8706 AutoNeg\n"); 9915 elink_cl45_write(cb, phy, 9916 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 9917 9918 /* Enable Full-Duplex advertisement on CL37 */ 9919 elink_cl45_write(cb, phy, 9920 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); 9921 /* Enable CL37 AN */ 9922 elink_cl45_write(cb, phy, 9923 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 9924 /* 1G support */ 9925 elink_cl45_write(cb, phy, 9926 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); 9927 9928 /* Enable clause 73 AN */ 9929 elink_cl45_write(cb, phy, 9930 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 9931 elink_cl45_write(cb, phy, 9932 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9933 0x0400); 9934 elink_cl45_write(cb, phy, 9935 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 9936 0x0004); 9937 } 9938 elink_save_bcm_spirom_ver(cb, phy, params->port); 9939 9940 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 9941 * power mode, if TX Laser is disabled 9942 */ 9943 9944 tx_en_mode = REG_RD(cb, params->shmem_base + 9945 OFFSETOF(struct shmem_region, 9946 dev_info.port_hw_config[params->port].sfp_ctrl)) 9947 & PORT_HW_CFG_TX_LASER_MASK; 9948 9949 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 9950 ELINK_DEBUG_P0(cb, "Enabling TXONOFF_PWRDN_DIS\n"); 9951 elink_cl45_read(cb, phy, 9952 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); 9953 tmp1 |= 0x1; 9954 elink_cl45_write(cb, phy, 9955 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); 9956 } 9957 9958 return ELINK_STATUS_OK; 9959 } 9960 9961 static elink_status_t 9962 elink_8706_read_status(struct elink_phy *phy, struct elink_params *params, 9963 struct elink_vars *vars) 9964 { 9965 return elink_8706_8726_read_status(phy, params, vars); 9966 } 9967 9968 /******************************************************************/ 9969 /* BCM8726 PHY SECTION */ 9970 /******************************************************************/ 9971 static void elink_8726_config_loopback(struct elink_phy *phy, 9972 struct elink_params *params) 9973 { 9974 struct elink_dev *cb = params->cb; 9975 ELINK_DEBUG_P0(cb, "PMA/PMD ext_phy_loopback: 8726\n"); 9976 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); 9977 } 9978 9979 static void elink_8726_external_rom_boot(struct elink_phy *phy, 9980 struct elink_params *params) 9981 { 9982 struct elink_dev *cb = params->cb; 9983 /* Need to wait 100ms after reset */ 9984 MSLEEP(cb, 100); 9985 9986 /* Micro controller re-boot */ 9987 elink_cl45_write(cb, phy, 9988 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); 9989 9990 /* Set soft reset */ 9991 elink_cl45_write(cb, phy, 9992 MDIO_PMA_DEVAD, 9993 MDIO_PMA_REG_GEN_CTRL, 9994 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 9995 9996 elink_cl45_write(cb, phy, 9997 MDIO_PMA_DEVAD, 9998 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 9999 10000 elink_cl45_write(cb, phy, 10001 MDIO_PMA_DEVAD, 10002 MDIO_PMA_REG_GEN_CTRL, 10003 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 10004 10005 /* Wait for 150ms for microcode load */ 10006 MSLEEP(cb, 150); 10007 10008 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ 10009 elink_cl45_write(cb, phy, 10010 MDIO_PMA_DEVAD, 10011 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 10012 10013 MSLEEP(cb, 200); 10014 elink_save_bcm_spirom_ver(cb, phy, params->port); 10015 } 10016 10017 static elink_status_t 10018 elink_8726_read_status(struct elink_phy *phy, struct elink_params *params, 10019 struct elink_vars *vars) 10020 { 10021 struct elink_dev *cb = params->cb; 10022 u16 val1; 10023 u8 link_up = elink_8706_8726_read_status(phy, params, vars); 10024 if (link_up) { 10025 elink_cl45_read(cb, phy, 10026 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 10027 &val1); 10028 if (val1 & (1<<15)) { 10029 ELINK_DEBUG_P0(cb, "Tx is disabled\n"); 10030 link_up = 0; 10031 vars->line_speed = 0; 10032 } 10033 } 10034 return link_up; 10035 } 10036 10037 10038 static elink_status_t 10039 elink_8726_config_init(struct elink_phy *phy, struct elink_params *params, 10040 struct elink_vars *vars) 10041 { 10042 struct elink_dev *cb = params->cb; 10043 ELINK_DEBUG_P0(cb, "Initializing BCM8726\n"); 10044 10045 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 10046 elink_wait_reset_complete(cb, phy, params); 10047 10048 elink_8726_external_rom_boot(phy, params); 10049 10050 /* Need to call module detected on initialization since the module 10051 * detection triggered by actual module insertion might occur before 10052 * driver is loaded, and when driver is loaded, it reset all 10053 * registers, including the transmitter 10054 */ 10055 elink_sfp_module_detection(phy, params); 10056 10057 if (phy->req_line_speed == ELINK_SPEED_1000) { 10058 ELINK_DEBUG_P0(cb, "Setting 1G force\n"); 10059 elink_cl45_write(cb, phy, 10060 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 10061 elink_cl45_write(cb, phy, 10062 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 10063 elink_cl45_write(cb, phy, 10064 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); 10065 elink_cl45_write(cb, phy, 10066 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 10067 0x400); 10068 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 10069 (phy->speed_cap_mask & 10070 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && 10071 ((phy->speed_cap_mask & 10072 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 10073 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 10074 ELINK_DEBUG_P0(cb, "Setting 1G clause37\n"); 10075 /* Set Flow control */ 10076 elink_ext_phy_set_pause(params, phy, vars); 10077 elink_cl45_write(cb, phy, 10078 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); 10079 elink_cl45_write(cb, phy, 10080 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 10081 elink_cl45_write(cb, phy, 10082 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); 10083 elink_cl45_write(cb, phy, 10084 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 10085 elink_cl45_write(cb, phy, 10086 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 10087 /* Enable RX-ALARM control to receive interrupt for 1G speed 10088 * change 10089 */ 10090 elink_cl45_write(cb, phy, 10091 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); 10092 elink_cl45_write(cb, phy, 10093 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 10094 0x400); 10095 10096 } else { /* Default 10G. Set only LASI control */ 10097 elink_cl45_write(cb, phy, 10098 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); 10099 } 10100 10101 /* Set TX PreEmphasis if needed */ 10102 if ((params->feature_config_flags & 10103 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 10104 ELINK_DEBUG_P2(cb, 10105 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 10106 phy->tx_preemphasis[0], 10107 phy->tx_preemphasis[1]); 10108 elink_cl45_write(cb, phy, 10109 MDIO_PMA_DEVAD, 10110 MDIO_PMA_REG_8726_TX_CTRL1, 10111 phy->tx_preemphasis[0]); 10112 10113 elink_cl45_write(cb, phy, 10114 MDIO_PMA_DEVAD, 10115 MDIO_PMA_REG_8726_TX_CTRL2, 10116 phy->tx_preemphasis[1]); 10117 } 10118 10119 return ELINK_STATUS_OK; 10120 10121 } 10122 10123 static void elink_8726_link_reset(struct elink_phy *phy, 10124 struct elink_params *params) 10125 { 10126 #ifndef EXCLUDE_LINK_RESET 10127 struct elink_dev *cb = params->cb; 10128 ELINK_DEBUG_P1(cb, "elink_8726_link_reset port %d\n", params->port); 10129 /* Set serial boot control for external load */ 10130 elink_cl45_write(cb, phy, 10131 MDIO_PMA_DEVAD, 10132 MDIO_PMA_REG_GEN_CTRL, 0x0001); 10133 #endif // EXCLUDE_LINK_RESET 10134 } 10135 #endif /* #ifndef EXCLUDE_BCM87x6 */ 10136 10137 /******************************************************************/ 10138 /* BCM8727 PHY SECTION */ 10139 /******************************************************************/ 10140 10141 #ifndef EXCLUDE_BCM8727_BCM8073 10142 static void elink_8727_set_link_led(struct elink_phy *phy, 10143 struct elink_params *params, u8 mode) 10144 { 10145 struct elink_dev *cb = params->cb; 10146 u16 led_mode_bitmask = 0; 10147 u16 gpio_pins_bitmask = 0; 10148 u16 val; 10149 /* Only NOC flavor requires to set the LED specifically */ 10150 if (!(phy->flags & ELINK_FLAGS_NOC)) 10151 return; 10152 switch (mode) { 10153 case ELINK_LED_MODE_FRONT_PANEL_OFF: 10154 case ELINK_LED_MODE_OFF: 10155 led_mode_bitmask = 0; 10156 gpio_pins_bitmask = 0x03; 10157 break; 10158 case ELINK_LED_MODE_ON: 10159 led_mode_bitmask = 0; 10160 gpio_pins_bitmask = 0x02; 10161 break; 10162 case ELINK_LED_MODE_OPER: 10163 led_mode_bitmask = 0x60; 10164 gpio_pins_bitmask = 0x11; 10165 break; 10166 } 10167 elink_cl45_read(cb, phy, 10168 MDIO_PMA_DEVAD, 10169 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 10170 &val); 10171 val &= 0xff8f; 10172 val |= led_mode_bitmask; 10173 elink_cl45_write(cb, phy, 10174 MDIO_PMA_DEVAD, 10175 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 10176 val); 10177 elink_cl45_read(cb, phy, 10178 MDIO_PMA_DEVAD, 10179 MDIO_PMA_REG_8727_GPIO_CTRL, 10180 &val); 10181 val &= 0xffe0; 10182 val |= gpio_pins_bitmask; 10183 elink_cl45_write(cb, phy, 10184 MDIO_PMA_DEVAD, 10185 MDIO_PMA_REG_8727_GPIO_CTRL, 10186 val); 10187 } 10188 static void elink_8727_hw_reset(struct elink_phy *phy, 10189 struct elink_params *params) { 10190 u32 swap_val, swap_override; 10191 u8 port; 10192 /* The PHY reset is controlled by GPIO 1. Fake the port number 10193 * to cancel the swap done in set_gpio() 10194 */ 10195 struct elink_dev *cb = params->cb; 10196 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP); 10197 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE); 10198 port = (swap_val && swap_override) ^ 1; 10199 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1, 10200 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 10201 } 10202 10203 static void elink_8727_config_speed(struct elink_phy *phy, 10204 struct elink_params *params) 10205 { 10206 struct elink_dev *cb = params->cb; 10207 u16 tmp1, val; 10208 /* Set option 1G speed */ 10209 if ((phy->req_line_speed == ELINK_SPEED_1000) || 10210 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) { 10211 ELINK_DEBUG_P0(cb, "Setting 1G force\n"); 10212 elink_cl45_write(cb, phy, 10213 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 10214 elink_cl45_write(cb, phy, 10215 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 10216 elink_cl45_read(cb, phy, 10217 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); 10218 ELINK_DEBUG_P1(cb, "1.7 = 0x%x\n", tmp1); 10219 /* Power down the XAUI until link is up in case of dual-media 10220 * and 1G 10221 */ 10222 if (ELINK_DUAL_MEDIA(params)) { 10223 elink_cl45_read(cb, phy, 10224 MDIO_PMA_DEVAD, 10225 MDIO_PMA_REG_8727_PCS_GP, &val); 10226 val |= (3<<10); 10227 elink_cl45_write(cb, phy, 10228 MDIO_PMA_DEVAD, 10229 MDIO_PMA_REG_8727_PCS_GP, val); 10230 } 10231 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 10232 ((phy->speed_cap_mask & 10233 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && 10234 ((phy->speed_cap_mask & 10235 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 10236 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 10237 10238 ELINK_DEBUG_P0(cb, "Setting 1G clause37\n"); 10239 elink_cl45_write(cb, phy, 10240 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); 10241 elink_cl45_write(cb, phy, 10242 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); 10243 } else { 10244 /* Since the 8727 has only single reset pin, need to set the 10G 10245 * registers although it is default 10246 */ 10247 elink_cl45_write(cb, phy, 10248 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 10249 0x0020); 10250 elink_cl45_write(cb, phy, 10251 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); 10252 elink_cl45_write(cb, phy, 10253 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 10254 elink_cl45_write(cb, phy, 10255 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 10256 0x0008); 10257 } 10258 } 10259 10260 static elink_status_t 10261 elink_8727_config_init(struct elink_phy *phy, struct elink_params *params, 10262 struct elink_vars *vars) 10263 { 10264 u32 tx_en_mode; 10265 u16 tmp1, mod_abs, tmp2; 10266 struct elink_dev *cb = params->cb; 10267 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ 10268 10269 elink_wait_reset_complete(cb, phy, params); 10270 10271 ELINK_DEBUG_P0(cb, "Initializing BCM8727\n"); 10272 10273 elink_8727_specific_func(phy, params, ELINK_PHY_INIT); 10274 /* Initially configure MOD_ABS to interrupt when module is 10275 * presence( bit 8) 10276 */ 10277 elink_cl45_read(cb, phy, 10278 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 10279 /* Set EDC off by setting OPTXLOS signal input to low (bit 9). 10280 * When the EDC is off it locks onto a reference clock and avoids 10281 * becoming 'lost' 10282 */ 10283 mod_abs &= ~(1<<8); 10284 if (!(phy->flags & ELINK_FLAGS_NOC)) 10285 mod_abs &= ~(1<<9); 10286 elink_cl45_write(cb, phy, 10287 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 10288 10289 /* Enable/Disable PHY transmitter output */ 10290 elink_set_disable_pmd_transmit(params, phy, 0); 10291 10292 elink_8727_power_module(cb, phy, 1); 10293 10294 elink_cl45_read(cb, phy, 10295 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 10296 10297 elink_cl45_read(cb, phy, 10298 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 10299 10300 elink_8727_config_speed(phy, params); 10301 10302 10303 /* Set TX PreEmphasis if needed */ 10304 if ((params->feature_config_flags & 10305 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 10306 ELINK_DEBUG_P2(cb, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 10307 phy->tx_preemphasis[0], 10308 phy->tx_preemphasis[1]); 10309 elink_cl45_write(cb, phy, 10310 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, 10311 phy->tx_preemphasis[0]); 10312 10313 elink_cl45_write(cb, phy, 10314 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, 10315 phy->tx_preemphasis[1]); 10316 } 10317 10318 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 10319 * power mode, if TX Laser is disabled 10320 */ 10321 tx_en_mode = REG_RD(cb, params->shmem_base + 10322 OFFSETOF(struct shmem_region, 10323 dev_info.port_hw_config[params->port].sfp_ctrl)) 10324 & PORT_HW_CFG_TX_LASER_MASK; 10325 10326 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 10327 10328 ELINK_DEBUG_P0(cb, "Enabling TXONOFF_PWRDN_DIS\n"); 10329 elink_cl45_read(cb, phy, 10330 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); 10331 tmp2 |= 0x1000; 10332 tmp2 &= 0xFFEF; 10333 elink_cl45_write(cb, phy, 10334 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); 10335 elink_cl45_read(cb, phy, 10336 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 10337 &tmp2); 10338 elink_cl45_write(cb, phy, 10339 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 10340 (tmp2 & 0x7fff)); 10341 } 10342 10343 return ELINK_STATUS_OK; 10344 } 10345 10346 static void elink_8727_handle_mod_abs(struct elink_phy *phy, 10347 struct elink_params *params) 10348 { 10349 struct elink_dev *cb = params->cb; 10350 u16 mod_abs, rx_alarm_status; 10351 u32 val = REG_RD(cb, params->shmem_base + 10352 OFFSETOF(struct shmem_region, dev_info. 10353 port_feature_config[params->port]. 10354 config)); 10355 elink_cl45_read(cb, phy, 10356 MDIO_PMA_DEVAD, 10357 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 10358 if (mod_abs & (1<<8)) { 10359 10360 /* Module is absent */ 10361 ELINK_DEBUG_P0(cb, 10362 "MOD_ABS indication show module is absent\n"); 10363 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT; 10364 /* 1. Set mod_abs to detect next module 10365 * presence event 10366 * 2. Set EDC off by setting OPTXLOS signal input to low 10367 * (bit 9). 10368 * When the EDC is off it locks onto a reference clock and 10369 * avoids becoming 'lost'. 10370 */ 10371 mod_abs &= ~(1<<8); 10372 if (!(phy->flags & ELINK_FLAGS_NOC)) 10373 mod_abs &= ~(1<<9); 10374 elink_cl45_write(cb, phy, 10375 MDIO_PMA_DEVAD, 10376 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 10377 10378 /* Clear RX alarm since it stays up as long as 10379 * the mod_abs wasn't changed 10380 */ 10381 elink_cl45_read(cb, phy, 10382 MDIO_PMA_DEVAD, 10383 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 10384 10385 } else { 10386 /* Module is present */ 10387 ELINK_DEBUG_P0(cb, 10388 "MOD_ABS indication show module is present\n"); 10389 /* First disable transmitter, and if the module is ok, the 10390 * module_detection will enable it 10391 * 1. Set mod_abs to detect next module absent event ( bit 8) 10392 * 2. Restore the default polarity of the OPRXLOS signal and 10393 * this signal will then correctly indicate the presence or 10394 * absence of the Rx signal. (bit 9) 10395 */ 10396 mod_abs |= (1<<8); 10397 if (!(phy->flags & ELINK_FLAGS_NOC)) 10398 mod_abs |= (1<<9); 10399 elink_cl45_write(cb, phy, 10400 MDIO_PMA_DEVAD, 10401 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 10402 10403 /* Clear RX alarm since it stays up as long as the mod_abs 10404 * wasn't changed. This is need to be done before calling the 10405 * module detection, otherwise it will clear* the link update 10406 * alarm 10407 */ 10408 elink_cl45_read(cb, phy, 10409 MDIO_PMA_DEVAD, 10410 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 10411 10412 10413 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 10414 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) 10415 elink_sfp_set_transmitter(params, phy, 0); 10416 10417 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) 10418 elink_sfp_module_detection(phy, params); 10419 else 10420 ELINK_DEBUG_P0(cb, "SFP+ module is not initialized\n"); 10421 10422 /* Reconfigure link speed based on module type limitations */ 10423 elink_8727_config_speed(phy, params); 10424 } 10425 10426 ELINK_DEBUG_P1(cb, "8727 RX_ALARM_STATUS 0x%x\n", 10427 rx_alarm_status); 10428 /* No need to check link status in case of module plugged in/out */ 10429 } 10430 10431 static elink_status_t 10432 elink_8727_read_status(struct elink_phy *phy, struct elink_params *params, 10433 struct elink_vars *vars) 10434 { 10435 struct elink_dev *cb = params->cb; 10436 u8 link_up = 0; 10437 u16 link_status = 0; 10438 u16 rx_alarm_status, lasi_ctrl, val1; 10439 10440 /* If PHY is not initialized, do not check link status */ 10441 elink_cl45_read(cb, phy, 10442 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 10443 &lasi_ctrl); 10444 if (!lasi_ctrl) 10445 return 0; 10446 10447 /* Check the LASI on Rx */ 10448 elink_cl45_read(cb, phy, 10449 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, 10450 &rx_alarm_status); 10451 vars->line_speed = 0; 10452 ELINK_DEBUG_P1(cb, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); 10453 10454 elink_sfp_mask_fault(cb, phy, MDIO_PMA_LASI_TXSTAT, 10455 MDIO_PMA_LASI_TXCTRL); 10456 10457 elink_cl45_read(cb, phy, 10458 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 10459 10460 ELINK_DEBUG_P1(cb, "8727 LASI status 0x%x\n", val1); 10461 10462 /* Clear MSG-OUT */ 10463 elink_cl45_read(cb, phy, 10464 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 10465 10466 /* If a module is present and there is need to check 10467 * for over current 10468 */ 10469 if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { 10470 /* Check over-current using 8727 GPIO0 input*/ 10471 elink_cl45_read(cb, phy, 10472 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, 10473 &val1); 10474 10475 if ((val1 & (1<<8)) == 0) { 10476 #ifndef ELINK_AUX_POWER 10477 u8 oc_port = params->port; 10478 if (!CHIP_IS_E1X(params->chip_id)) 10479 oc_port = PATH_ID(cb) + (params->port << 1); 10480 ELINK_DEBUG_P1(cb, 10481 "8727 Power fault has been detected on port %d\n", 10482 oc_port); 10483 elink_cb_event_log(cb, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has " 10484 // "been detected and the power to " 10485 // "that SFP+ module has been removed " 10486 // "to prevent failure of the card. " 10487 // "Please remove the SFP+ module and " 10488 // "restart the system to clear this " 10489 // "error.\n", 10490 #endif 10491 /* Disable all RX_ALARMs except for mod_abs */ 10492 elink_cl45_write(cb, phy, 10493 MDIO_PMA_DEVAD, 10494 MDIO_PMA_LASI_RXCTRL, (1<<5)); 10495 10496 elink_cl45_read(cb, phy, 10497 MDIO_PMA_DEVAD, 10498 MDIO_PMA_REG_PHY_IDENTIFIER, &val1); 10499 /* Wait for module_absent_event */ 10500 val1 |= (1<<8); 10501 elink_cl45_write(cb, phy, 10502 MDIO_PMA_DEVAD, 10503 MDIO_PMA_REG_PHY_IDENTIFIER, val1); 10504 /* Clear RX alarm */ 10505 elink_cl45_read(cb, phy, 10506 MDIO_PMA_DEVAD, 10507 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 10508 elink_8727_power_module(params->cb, phy, 0); 10509 return 0; 10510 } 10511 } /* Over current check */ 10512 10513 /* When module absent bit is set, check module */ 10514 if (rx_alarm_status & (1<<5)) { 10515 elink_8727_handle_mod_abs(phy, params); 10516 /* Enable all mod_abs and link detection bits */ 10517 elink_cl45_write(cb, phy, 10518 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 10519 ((1<<5) | (1<<2))); 10520 } 10521 10522 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) { 10523 ELINK_DEBUG_P0(cb, "Enabling 8727 TX laser\n"); 10524 elink_sfp_set_transmitter(params, phy, 1); 10525 } else { 10526 ELINK_DEBUG_P0(cb, "Tx is disabled\n"); 10527 return 0; 10528 } 10529 10530 elink_cl45_read(cb, phy, 10531 MDIO_PMA_DEVAD, 10532 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); 10533 10534 /* Bits 0..2 --> speed detected, 10535 * Bits 13..15--> link is down 10536 */ 10537 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 10538 link_up = 1; 10539 vars->line_speed = ELINK_SPEED_10000; 10540 ELINK_DEBUG_P1(cb, "port %x: External link up in 10G\n", 10541 params->port); 10542 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 10543 link_up = 1; 10544 vars->line_speed = ELINK_SPEED_1000; 10545 ELINK_DEBUG_P1(cb, "port %x: External link up in 1G\n", 10546 params->port); 10547 } else { 10548 link_up = 0; 10549 ELINK_DEBUG_P1(cb, "port %x: External link is down\n", 10550 params->port); 10551 } 10552 10553 /* Capture 10G link fault. */ 10554 if (vars->line_speed == ELINK_SPEED_10000) { 10555 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 10556 MDIO_PMA_LASI_TXSTAT, &val1); 10557 10558 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 10559 MDIO_PMA_LASI_TXSTAT, &val1); 10560 10561 if (val1 & (1<<0)) { 10562 vars->fault_detected = 1; 10563 } 10564 } 10565 10566 if (link_up) { 10567 elink_ext_phy_resolve_fc(phy, params, vars); 10568 vars->duplex = DUPLEX_FULL; 10569 ELINK_DEBUG_P1(cb, "duplex = 0x%x\n", vars->duplex); 10570 } 10571 10572 if ((ELINK_DUAL_MEDIA(params)) && 10573 (phy->req_line_speed == ELINK_SPEED_1000)) { 10574 elink_cl45_read(cb, phy, 10575 MDIO_PMA_DEVAD, 10576 MDIO_PMA_REG_8727_PCS_GP, &val1); 10577 /* In case of dual-media board and 1G, power up the XAUI side, 10578 * otherwise power it down. For 10G it is done automatically 10579 */ 10580 if (link_up) 10581 val1 &= ~(3<<10); 10582 else 10583 val1 |= (3<<10); 10584 elink_cl45_write(cb, phy, 10585 MDIO_PMA_DEVAD, 10586 MDIO_PMA_REG_8727_PCS_GP, val1); 10587 } 10588 return link_up; 10589 } 10590 10591 static void elink_8727_link_reset(struct elink_phy *phy, 10592 struct elink_params *params) 10593 { 10594 #ifndef EXCLUDE_LINK_RESET 10595 struct elink_dev *cb = params->cb; 10596 10597 /* Enable/Disable PHY transmitter output */ 10598 elink_set_disable_pmd_transmit(params, phy, 1); 10599 10600 /* Disable Transmitter */ 10601 elink_sfp_set_transmitter(params, phy, 0); 10602 /* Clear LASI */ 10603 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); 10604 10605 #endif // EXCLUDE_LINK_RESET 10606 } 10607 #endif /* EXCLUDE_BCM8727_BCM8073 */ 10608 #endif // EXCLUDE_NON_COMMON_INIT 10609 10610 /******************************************************************/ 10611 /* BCM8481/BCM84823/BCM84833 PHY SECTION */ 10612 /******************************************************************/ 10613 #if !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833) 10614 static void elink_save_848xx_spirom_version(struct elink_phy *phy, 10615 struct elink_dev *cb, 10616 u8 port) 10617 { 10618 #ifndef EXCLUDE_BCM8481 10619 u16 val, fw_ver2, cnt, i; 10620 static struct elink_reg_set reg_set[] = { 10621 {MDIO_PMA_DEVAD, 0xA819, 0x0014}, 10622 {MDIO_PMA_DEVAD, 0xA81A, 0xc200}, 10623 {MDIO_PMA_DEVAD, 0xA81B, 0x0000}, 10624 {MDIO_PMA_DEVAD, 0xA81C, 0x0300}, 10625 {MDIO_PMA_DEVAD, 0xA817, 0x0009} 10626 }; 10627 #endif 10628 u16 fw_ver1; 10629 10630 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10631 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10632 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); 10633 elink_save_spirom_version(cb, port, fw_ver1 & 0xfff, 10634 phy->ver_addr); 10635 } else { 10636 #ifndef EXCLUDE_BCM8481 10637 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ 10638 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ 10639 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 10640 elink_cl45_write(cb, phy, reg_set[i].devad, 10641 reg_set[i].reg, reg_set[i].val); 10642 10643 for (cnt = 0; cnt < 100; cnt++) { 10644 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA818, &val); 10645 if (val & 1) 10646 break; 10647 USLEEP(cb, 5); 10648 } 10649 if (cnt == 100) { 10650 ELINK_DEBUG_P0(cb, "Unable to read 848xx " 10651 "phy fw version(1)\n"); 10652 elink_save_spirom_version(cb, port, 0, 10653 phy->ver_addr); 10654 return; 10655 } 10656 10657 10658 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ 10659 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); 10660 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); 10661 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); 10662 for (cnt = 0; cnt < 100; cnt++) { 10663 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA818, &val); 10664 if (val & 1) 10665 break; 10666 USLEEP(cb, 5); 10667 } 10668 if (cnt == 100) { 10669 ELINK_DEBUG_P0(cb, "Unable to read 848xx phy fw " 10670 "version(2)\n"); 10671 elink_save_spirom_version(cb, port, 0, 10672 phy->ver_addr); 10673 return; 10674 } 10675 10676 /* lower 16 bits of the register SPI_FW_STATUS */ 10677 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); 10678 /* upper 16 bits of register SPI_FW_STATUS */ 10679 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); 10680 10681 elink_save_spirom_version(cb, port, (fw_ver2<<16) | fw_ver1, 10682 phy->ver_addr); 10683 #endif /* EXCLUDE_BCM8481 */ 10684 } 10685 10686 } 10687 #ifndef EXCLUDE_NON_COMMON_INIT 10688 static void elink_848xx_set_led(struct elink_dev *cb, 10689 struct elink_phy *phy) 10690 { 10691 u16 val, offset, i; 10692 static struct elink_reg_set reg_set[] = { 10693 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080}, 10694 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018}, 10695 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006}, 10696 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000}, 10697 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, 10698 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ}, 10699 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} 10700 }; 10701 /* PHYC_CTL_LED_CTL */ 10702 elink_cl45_read(cb, phy, 10703 MDIO_PMA_DEVAD, 10704 MDIO_PMA_REG_8481_LINK_SIGNAL, &val); 10705 val &= 0xFE00; 10706 val |= 0x0092; 10707 10708 elink_cl45_write(cb, phy, 10709 MDIO_PMA_DEVAD, 10710 MDIO_PMA_REG_8481_LINK_SIGNAL, val); 10711 10712 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 10713 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg, 10714 reg_set[i].val); 10715 10716 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10717 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) 10718 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; 10719 else 10720 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; 10721 10722 /* stretch_en for LED3*/ 10723 elink_cl45_read_or_write(cb, phy, 10724 MDIO_PMA_DEVAD, offset, 10725 MDIO_PMA_REG_84823_LED3_STRETCH_EN); 10726 } 10727 10728 static void elink_848xx_specific_func(struct elink_phy *phy, 10729 struct elink_params *params, 10730 u32 action) 10731 { 10732 struct elink_dev *cb = params->cb; 10733 switch (action) { 10734 case ELINK_PHY_INIT: 10735 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 10736 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10737 /* Save spirom version */ 10738 elink_save_848xx_spirom_version(phy, cb, params->port); 10739 } 10740 /* This phy uses the NIG latch mechanism since link indication 10741 * arrives through its LED4 and not via its LASI signal, so we 10742 * get steady signal instead of clear on read 10743 */ 10744 elink_bits_en(cb, NIG_REG_LATCH_BC_0 + params->port*4, 10745 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT); 10746 10747 elink_848xx_set_led(cb, phy); 10748 break; 10749 } 10750 } 10751 10752 static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy, 10753 struct elink_params *params, 10754 struct elink_vars *vars) 10755 { 10756 struct elink_dev *cb = params->cb; 10757 u16 autoneg_val, an_1000_val, an_10_100_val; 10758 10759 elink_848xx_specific_func(phy, params, ELINK_PHY_INIT); 10760 elink_cl45_write(cb, phy, 10761 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); 10762 10763 /* set 1000 speed advertisement */ 10764 elink_cl45_read(cb, phy, 10765 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 10766 &an_1000_val); 10767 10768 elink_ext_phy_set_pause(params, phy, vars); 10769 elink_cl45_read(cb, phy, 10770 MDIO_AN_DEVAD, 10771 MDIO_AN_REG_8481_LEGACY_AN_ADV, 10772 &an_10_100_val); 10773 elink_cl45_read(cb, phy, 10774 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, 10775 &autoneg_val); 10776 /* Disable forced speed */ 10777 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 10778 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); 10779 10780 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 10781 (phy->speed_cap_mask & 10782 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 10783 (phy->req_line_speed == ELINK_SPEED_1000)) { 10784 an_1000_val |= (1<<8); 10785 autoneg_val |= (1<<9 | 1<<12); 10786 if (phy->req_duplex == DUPLEX_FULL) 10787 an_1000_val |= (1<<9); 10788 ELINK_DEBUG_P0(cb, "Advertising 1G\n"); 10789 } else 10790 an_1000_val &= ~((1<<8) | (1<<9)); 10791 10792 elink_cl45_write(cb, phy, 10793 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 10794 an_1000_val); 10795 10796 /* Set 10/100 speed advertisement */ 10797 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { 10798 if (phy->speed_cap_mask & 10799 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { 10800 /* Enable autoneg and restart autoneg for legacy speeds 10801 */ 10802 autoneg_val |= (1<<9 | 1<<12); 10803 an_10_100_val |= (1<<8); 10804 ELINK_DEBUG_P0(cb, "Advertising 100M-FD\n"); 10805 } 10806 10807 if (phy->speed_cap_mask & 10808 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { 10809 /* Enable autoneg and restart autoneg for legacy speeds 10810 */ 10811 autoneg_val |= (1<<9 | 1<<12); 10812 an_10_100_val |= (1<<7); 10813 ELINK_DEBUG_P0(cb, "Advertising 100M-HD\n"); 10814 } 10815 10816 if ((phy->speed_cap_mask & 10817 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 10818 (phy->supported & ELINK_SUPPORTED_10baseT_Full)) { 10819 an_10_100_val |= (1<<6); 10820 autoneg_val |= (1<<9 | 1<<12); 10821 ELINK_DEBUG_P0(cb, "Advertising 10M-FD\n"); 10822 } 10823 10824 if ((phy->speed_cap_mask & 10825 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) && 10826 (phy->supported & ELINK_SUPPORTED_10baseT_Half)) { 10827 an_10_100_val |= (1<<5); 10828 autoneg_val |= (1<<9 | 1<<12); 10829 ELINK_DEBUG_P0(cb, "Advertising 10M-HD\n"); 10830 } 10831 } 10832 10833 /* Only 10/100 are allowed to work in FORCE mode */ 10834 if ((phy->req_line_speed == ELINK_SPEED_100) && 10835 (phy->supported & 10836 (ELINK_SUPPORTED_100baseT_Half | 10837 ELINK_SUPPORTED_100baseT_Full))) { 10838 autoneg_val |= (1<<13); 10839 /* Enabled AUTO-MDIX when autoneg is disabled */ 10840 elink_cl45_write(cb, phy, 10841 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 10842 (1<<15 | 1<<9 | 7<<0)); 10843 /* The PHY needs this set even for forced link. */ 10844 an_10_100_val |= (1<<8) | (1<<7); 10845 ELINK_DEBUG_P0(cb, "Setting 100M force\n"); 10846 } 10847 if ((phy->req_line_speed == ELINK_SPEED_10) && 10848 (phy->supported & 10849 (ELINK_SUPPORTED_10baseT_Half | 10850 ELINK_SUPPORTED_10baseT_Full))) { 10851 /* Enabled AUTO-MDIX when autoneg is disabled */ 10852 elink_cl45_write(cb, phy, 10853 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 10854 (1<<15 | 1<<9 | 7<<0)); 10855 ELINK_DEBUG_P0(cb, "Setting 10M force\n"); 10856 } 10857 10858 elink_cl45_write(cb, phy, 10859 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, 10860 an_10_100_val); 10861 10862 if (phy->req_duplex == DUPLEX_FULL) 10863 autoneg_val |= (1<<8); 10864 10865 /* Always write this if this is not 84833/4. 10866 * For 84833/4, write it only when it's a forced speed. 10867 */ 10868 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 10869 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) || 10870 ((autoneg_val & (1<<12)) == 0)) 10871 elink_cl45_write(cb, phy, 10872 MDIO_AN_DEVAD, 10873 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); 10874 10875 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 10876 (phy->speed_cap_mask & 10877 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 10878 (phy->req_line_speed == ELINK_SPEED_10000)) { 10879 ELINK_DEBUG_P0(cb, "Advertising 10G\n"); 10880 /* Restart autoneg for 10G*/ 10881 10882 elink_cl45_read_or_write( 10883 cb, phy, 10884 MDIO_AN_DEVAD, 10885 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 10886 0x1000); 10887 elink_cl45_write(cb, phy, 10888 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 10889 0x3200); 10890 } else 10891 elink_cl45_write(cb, phy, 10892 MDIO_AN_DEVAD, 10893 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 10894 1); 10895 10896 return ELINK_STATUS_OK; 10897 } 10898 #endif // EXCLUDE_NON_COMMON_INIT 10899 #endif // #if !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833) 10900 10901 #ifndef EXCLUDE_BCM8481 10902 #ifndef EXCLUDE_NON_COMMON_INIT 10903 static elink_status_t 10904 elink_8481_config_init(struct elink_phy *phy, struct elink_params *params, 10905 struct elink_vars *vars) 10906 { 10907 struct elink_dev *cb = params->cb; 10908 /* Restore normal power mode*/ 10909 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 10910 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 10911 10912 /* HW reset */ 10913 elink_ext_phy_hw_reset(cb, params->port); 10914 elink_wait_reset_complete(cb, phy, params); 10915 10916 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 10917 return elink_848xx_cmn_config_init(phy, params, vars); 10918 } 10919 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 10920 #endif // EXCLUDE_BCM8481 10921 10922 #ifndef EXCLUDE_BCM84833 10923 #define PHY84833_CMDHDLR_WAIT 300 10924 #define PHY84833_CMDHDLR_MAX_ARGS 5 10925 static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy, 10926 struct elink_params *params, u16 fw_cmd, 10927 u16 cmd_args[], int argc) 10928 { 10929 int idx; 10930 u16 val; 10931 struct elink_dev *cb = params->cb; 10932 /* Write CMD_OPEN_OVERRIDE to STATUS reg */ 10933 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD, 10934 MDIO_84833_CMD_HDLR_STATUS, 10935 PHY84833_STATUS_CMD_OPEN_OVERRIDE); 10936 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 10937 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 10938 MDIO_84833_CMD_HDLR_STATUS, &val); 10939 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) 10940 break; 10941 MSLEEP(cb, 1); 10942 } 10943 if (idx >= PHY84833_CMDHDLR_WAIT) { 10944 ELINK_DEBUG_P0(cb, "FW cmd: FW not ready.\n"); 10945 return ELINK_STATUS_ERROR; 10946 } 10947 10948 /* Prepare argument(s) and issue command */ 10949 for (idx = 0; idx < argc; idx++) { 10950 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD, 10951 MDIO_84833_CMD_HDLR_DATA1 + idx, 10952 cmd_args[idx]); 10953 } 10954 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD, 10955 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); 10956 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 10957 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 10958 MDIO_84833_CMD_HDLR_STATUS, &val); 10959 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || 10960 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) 10961 break; 10962 MSLEEP(cb, 1); 10963 } 10964 if ((idx >= PHY84833_CMDHDLR_WAIT) || 10965 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { 10966 ELINK_DEBUG_P0(cb, "FW cmd failed.\n"); 10967 return ELINK_STATUS_ERROR; 10968 } 10969 /* Gather returning data */ 10970 for (idx = 0; idx < argc; idx++) { 10971 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 10972 MDIO_84833_CMD_HDLR_DATA1 + idx, 10973 &cmd_args[idx]); 10974 } 10975 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD, 10976 MDIO_84833_CMD_HDLR_STATUS, 10977 PHY84833_STATUS_CMD_CLEAR_COMPLETE); 10978 return ELINK_STATUS_OK; 10979 } 10980 10981 #ifndef EXCLUDE_NON_COMMON_INIT 10982 static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy, 10983 struct elink_params *params, 10984 struct elink_vars *vars) 10985 { 10986 u32 pair_swap; 10987 u16 data[PHY84833_CMDHDLR_MAX_ARGS]; 10988 elink_status_t status; 10989 struct elink_dev *cb = params->cb; 10990 10991 /* Check for configuration. */ 10992 pair_swap = REG_RD(cb, params->shmem_base + 10993 OFFSETOF(struct shmem_region, 10994 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & 10995 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; 10996 10997 if (pair_swap == 0) 10998 return ELINK_STATUS_OK; 10999 11000 /* Only the second argument is used for this command */ 11001 data[1] = (u16)pair_swap; 11002 11003 status = elink_84833_cmd_hdlr(phy, params, 11004 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS); 11005 if (status == ELINK_STATUS_OK) 11006 ELINK_DEBUG_P1(cb, "Pairswap OK, val=0x%x\n", data[1]); 11007 11008 return status; 11009 } 11010 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 11011 11012 static u8 elink_84833_get_reset_gpios(struct elink_dev *cb, 11013 u32 shmem_base_path[], 11014 u32 chip_id) 11015 { 11016 u32 reset_pin[2]; 11017 u32 idx; 11018 u8 reset_gpios; 11019 if (CHIP_IS_E3(chip_id)) { 11020 /* Assume that these will be GPIOs, not EPIOs. */ 11021 for (idx = 0; idx < 2; idx++) { 11022 /* Map config param to register bit. */ 11023 reset_pin[idx] = REG_RD(cb, shmem_base_path[idx] + 11024 OFFSETOF(struct shmem_region, 11025 dev_info.port_hw_config[0].e3_cmn_pin_cfg)); 11026 reset_pin[idx] = (reset_pin[idx] & 11027 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 11028 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 11029 reset_pin[idx] -= PIN_CFG_GPIO0_P0; 11030 reset_pin[idx] = (1 << reset_pin[idx]); 11031 } 11032 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 11033 } else { 11034 /* E2, look from diff place of shmem. */ 11035 for (idx = 0; idx < 2; idx++) { 11036 reset_pin[idx] = REG_RD(cb, shmem_base_path[idx] + 11037 OFFSETOF(struct shmem_region, 11038 dev_info.port_hw_config[0].default_cfg)); 11039 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; 11040 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; 11041 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; 11042 reset_pin[idx] = (1 << reset_pin[idx]); 11043 } 11044 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 11045 } 11046 11047 return reset_gpios; 11048 } 11049 11050 #ifndef EXCLUDE_NON_COMMON_INIT 11051 static void 11052 elink_84833_hw_reset_phy(struct elink_phy *phy, 11053 struct elink_params *params) 11054 { 11055 struct elink_dev *cb = params->cb; 11056 u8 reset_gpios; 11057 u32 other_shmem_base_addr = REG_RD(cb, params->shmem2_base + 11058 OFFSETOF(struct shmem2_region, 11059 other_shmem_base_addr)); 11060 11061 u32 shmem_base_path[2]; 11062 11063 /* Work around for 84833 LED failure inside RESET status */ 11064 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 11065 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 11066 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); 11067 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 11068 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, 11069 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); 11070 11071 shmem_base_path[0] = params->shmem_base; 11072 shmem_base_path[1] = other_shmem_base_addr; 11073 11074 reset_gpios = elink_84833_get_reset_gpios(cb, shmem_base_path, 11075 params->chip_id); 11076 11077 #ifndef EDEBUG 11078 ELINK_SET_MULT_GPIO(cb, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 11079 USLEEP(cb, 10); 11080 ELINK_DEBUG_P1(cb, "84833 hw reset on pin values 0x%x\n", 11081 reset_gpios); 11082 #endif // EDEBUG 11083 } 11084 #endif // EXCLUDE_NON_COMMON_INIT 11085 #endif // #ifndef EXCLUDE_BCM84833 11086 11087 #ifndef EXCLUDE_NON_COMMON_INIT 11088 #ifndef EXCLUDE_WARPCORE 11089 static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy, 11090 struct elink_params *params, 11091 struct elink_vars *vars) 11092 { 11093 elink_status_t rc; 11094 #if defined(ELINK_DEBUG) 11095 struct elink_dev *cb = params->cb; 11096 #endif 11097 u16 cmd_args = 0; 11098 11099 ELINK_DEBUG_P0(cb, "Don't Advertise 10GBase-T EEE\n"); 11100 11101 /* Prevent Phy from working in EEE and advertising it */ 11102 rc = elink_84833_cmd_hdlr(phy, params, 11103 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 11104 if (rc != ELINK_STATUS_OK) { 11105 ELINK_DEBUG_P0(cb, "EEE disable failed.\n"); 11106 return rc; 11107 } 11108 11109 return elink_eee_disable(phy, params, vars); 11110 } 11111 11112 static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy, 11113 struct elink_params *params, 11114 struct elink_vars *vars) 11115 { 11116 elink_status_t rc; 11117 #ifdef ELINK_DEBUG 11118 struct elink_dev *cb = params->cb; 11119 #endif 11120 u16 cmd_args = 1; 11121 11122 rc = elink_84833_cmd_hdlr(phy, params, 11123 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 11124 if (rc != ELINK_STATUS_OK) { 11125 ELINK_DEBUG_P0(cb, "EEE enable failed.\n"); 11126 return rc; 11127 } 11128 11129 return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); 11130 } 11131 #endif /* #ifndef EXCLUDE_WARPCORE */ 11132 11133 #if !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833) 11134 #define PHY84833_CONSTANT_LATENCY 1193 11135 static elink_status_t 11136 elink_848x3_config_init(struct elink_phy *phy, struct elink_params *params, 11137 struct elink_vars *vars) 11138 { 11139 struct elink_dev *cb = params->cb; 11140 u8 port, initialize = 1; 11141 u16 val; 11142 u32 actual_phy_selection; 11143 #ifndef EXCLUDE_BCM84833 11144 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; 11145 #endif // EXCLUDE_BCM84833 11146 elink_status_t rc = ELINK_STATUS_OK; 11147 11148 MSLEEP(cb, 1); 11149 11150 if (!(CHIP_IS_E1X(params->chip_id))) 11151 port = PATH_ID(cb); 11152 else 11153 port = params->port; 11154 11155 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 11156 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_3, 11157 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 11158 port); 11159 } else { 11160 /* MDIO reset */ 11161 elink_cl45_write(cb, phy, 11162 MDIO_PMA_DEVAD, 11163 MDIO_PMA_REG_CTRL, 0x8000); 11164 } 11165 11166 elink_wait_reset_complete(cb, phy, params); 11167 11168 /* Wait for GPHY to come out of reset */ 11169 MSLEEP(cb, 50); 11170 #ifndef EXCLUDE_BCM84833 11171 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 11172 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 11173 #endif // EXCLUDE_BCM84833 11174 #ifndef EXCLUDE_BCM8481 11175 /* BCM84823 requires that XGXS links up first @ 10G for normal 11176 * behavior. 11177 */ 11178 u16 temp; 11179 temp = vars->line_speed; 11180 vars->line_speed = ELINK_SPEED_10000; 11181 elink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0); 11182 elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars); 11183 vars->line_speed = temp; 11184 #endif // EXCLUDE_BCM8481 11185 #ifndef EXCLUDE_BCM84833 11186 } 11187 #endif /* Set dual-media configuration according to configuration */ 11188 11189 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 11190 MDIO_CTL_REG_84823_MEDIA, &val); 11191 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 11192 MDIO_CTL_REG_84823_MEDIA_LINE_MASK | 11193 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | 11194 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | 11195 MDIO_CTL_REG_84823_MEDIA_FIBER_1G); 11196 11197 if (CHIP_IS_E3(params->chip_id)) { 11198 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 11199 MDIO_CTL_REG_84823_MEDIA_LINE_MASK); 11200 } else { 11201 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | 11202 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); 11203 } 11204 11205 actual_phy_selection = elink_phy_selection(params); 11206 11207 switch (actual_phy_selection) { 11208 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 11209 /* Do nothing. Essentially this is like the priority copper */ 11210 break; 11211 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 11212 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; 11213 break; 11214 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 11215 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; 11216 break; 11217 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 11218 /* Do nothing here. The first PHY won't be initialized at all */ 11219 break; 11220 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 11221 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; 11222 initialize = 0; 11223 break; 11224 } 11225 if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000) 11226 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; 11227 11228 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD, 11229 MDIO_CTL_REG_84823_MEDIA, val); 11230 ELINK_DEBUG_P2(cb, "Multi_phy config = 0x%x, Media control = 0x%x\n", 11231 params->multi_phy_config, val); 11232 11233 #ifndef EXCLUDE_BCM84833 11234 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 11235 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 11236 elink_84833_pair_swap_cfg(phy, params, vars); 11237 11238 /* Keep AutogrEEEn disabled. */ 11239 cmd_args[0] = 0x0; 11240 cmd_args[1] = 0x0; 11241 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; 11242 cmd_args[3] = PHY84833_CONSTANT_LATENCY; 11243 rc = elink_84833_cmd_hdlr(phy, params, 11244 PHY84833_CMD_SET_EEE_MODE, cmd_args, 11245 PHY84833_CMDHDLR_MAX_ARGS); 11246 if (rc != ELINK_STATUS_OK) 11247 ELINK_DEBUG_P0(cb, "Cfg AutogrEEEn failed.\n"); 11248 } 11249 #endif // #ifndef EXCLUDE_BCM84833 11250 if (initialize) 11251 rc = elink_848xx_cmn_config_init(phy, params, vars); 11252 #ifdef ELINK_ENHANCEMENTS 11253 else 11254 elink_save_848xx_spirom_version(phy, cb, params->port); 11255 #endif // ELINK_ENHANCEMENTS 11256 /* 84833 PHY has a better feature and doesn't need to support this. */ 11257 #ifndef EXCLUDE_BCM8481 11258 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 11259 u32 cms_enable = REG_RD(cb, params->shmem_base + 11260 OFFSETOF(struct shmem_region, 11261 dev_info.port_hw_config[params->port].default_cfg)) & 11262 PORT_HW_CFG_ENABLE_CMS_MASK; 11263 11264 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 11265 MDIO_CTL_REG_84823_USER_CTRL_REG, &val); 11266 if (cms_enable) 11267 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; 11268 else 11269 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; 11270 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD, 11271 MDIO_CTL_REG_84823_USER_CTRL_REG, val); 11272 } 11273 #endif /* EXCLUDE_BCM8481 */ 11274 11275 #ifndef EXCLUDE_WARPCORE 11276 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 11277 MDIO_84833_TOP_CFG_FW_REV, &val); 11278 11279 /* Configure EEE support */ 11280 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && 11281 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && 11282 elink_eee_has_cap(params)) { 11283 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); 11284 if (rc != ELINK_STATUS_OK) { 11285 ELINK_DEBUG_P0(cb, "Failed to configure EEE timers\n"); 11286 elink_8483x_disable_eee(phy, params, vars); 11287 return rc; 11288 } 11289 11290 if ((phy->req_duplex == DUPLEX_FULL) && 11291 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) && 11292 (elink_eee_calc_timer(params) || 11293 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) 11294 rc = elink_8483x_enable_eee(phy, params, vars); 11295 else 11296 rc = elink_8483x_disable_eee(phy, params, vars); 11297 if (rc != ELINK_STATUS_OK) { 11298 ELINK_DEBUG_P0(cb, "Failed to set EEE advertisement\n"); 11299 return rc; 11300 } 11301 } else { 11302 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; 11303 } 11304 #endif /* #ifndef EXCLUDE_WARPCORE */ 11305 11306 #ifndef EXCLUDE_BCM84833 11307 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 11308 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 11309 /* Bring PHY out of super isolate mode as the final step. */ 11310 elink_cl45_read_and_write(cb, phy, 11311 MDIO_CTL_DEVAD, 11312 MDIO_84833_TOP_CFG_XGPHY_STRAP1, 11313 (u16)~MDIO_84833_SUPER_ISOLATE); 11314 } 11315 #endif /* #ifndef EXCLUDE_BCM84833 */ 11316 return rc; 11317 } 11318 11319 static elink_status_t 11320 elink_848xx_read_status(struct elink_phy *phy, struct elink_params *params, 11321 struct elink_vars *vars) 11322 { 11323 struct elink_dev *cb = params->cb; 11324 u16 val, val1, val2; 11325 u8 link_up = 0; 11326 11327 11328 /* Check 10G-BaseT link status */ 11329 /* Check PMD signal ok */ 11330 elink_cl45_read(cb, phy, 11331 MDIO_AN_DEVAD, 0xFFFA, &val1); 11332 elink_cl45_read(cb, phy, 11333 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, 11334 &val2); 11335 ELINK_DEBUG_P1(cb, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); 11336 11337 /* Check link 10G */ 11338 if (val2 & (1<<11)) { 11339 vars->line_speed = ELINK_SPEED_10000; 11340 vars->duplex = DUPLEX_FULL; 11341 link_up = 1; 11342 elink_ext_phy_10G_an_resolve(cb, phy, vars); 11343 } else { /* Check Legacy speed link */ 11344 u16 legacy_status, legacy_speed; 11345 11346 /* Enable expansion register 0x42 (Operation mode status) */ 11347 elink_cl45_write(cb, phy, 11348 MDIO_AN_DEVAD, 11349 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); 11350 11351 /* Get legacy speed operation status */ 11352 elink_cl45_read(cb, phy, 11353 MDIO_AN_DEVAD, 11354 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, 11355 &legacy_status); 11356 11357 ELINK_DEBUG_P1(cb, "Legacy speed status = 0x%x\n", 11358 legacy_status); 11359 link_up = ((legacy_status & (1<<11)) == (1<<11)); 11360 legacy_speed = (legacy_status & (3<<9)); 11361 if (legacy_speed == (0<<9)) 11362 vars->line_speed = ELINK_SPEED_10; 11363 else if (legacy_speed == (1<<9)) 11364 vars->line_speed = ELINK_SPEED_100; 11365 else if (legacy_speed == (2<<9)) 11366 vars->line_speed = ELINK_SPEED_1000; 11367 else { /* Should not happen: Treat as link down */ 11368 vars->line_speed = 0; 11369 link_up = 0; 11370 } 11371 11372 #ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */ 11373 if (params->feature_config_flags & 11374 ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) { 11375 u16 mii_ctrl; 11376 11377 elink_cl45_read(cb, phy, 11378 MDIO_AN_DEVAD, 11379 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 11380 &mii_ctrl); 11381 /* For IEEE testing, check for a fake link. */ 11382 link_up |= ((mii_ctrl & 0x3040) == 0x40); 11383 } 11384 #endif 11385 11386 if (link_up) { 11387 if (legacy_status & (1<<8)) 11388 vars->duplex = DUPLEX_FULL; 11389 else 11390 vars->duplex = DUPLEX_HALF; 11391 11392 ELINK_DEBUG_P2(cb, 11393 "Link is up in %dMbps, is_duplex_full= %d\n", 11394 vars->line_speed, 11395 (vars->duplex == DUPLEX_FULL)); 11396 /* Check legacy speed AN resolution */ 11397 elink_cl45_read(cb, phy, 11398 MDIO_AN_DEVAD, 11399 MDIO_AN_REG_8481_LEGACY_MII_STATUS, 11400 &val); 11401 if (val & (1<<5)) 11402 vars->link_status |= 11403 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 11404 elink_cl45_read(cb, phy, 11405 MDIO_AN_DEVAD, 11406 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, 11407 &val); 11408 if ((val & (1<<0)) == 0) 11409 vars->link_status |= 11410 LINK_STATUS_PARALLEL_DETECTION_USED; 11411 } 11412 } 11413 if (link_up) { 11414 ELINK_DEBUG_P1(cb, "BCM848x3: link speed is %d\n", 11415 vars->line_speed); 11416 elink_ext_phy_resolve_fc(phy, params, vars); 11417 11418 /* Read LP advertised speeds */ 11419 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 11420 MDIO_AN_REG_CL37_FC_LP, &val); 11421 if (val & (1<<5)) 11422 vars->link_status |= 11423 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 11424 if (val & (1<<6)) 11425 vars->link_status |= 11426 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 11427 if (val & (1<<7)) 11428 vars->link_status |= 11429 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 11430 if (val & (1<<8)) 11431 vars->link_status |= 11432 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 11433 if (val & (1<<9)) 11434 vars->link_status |= 11435 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 11436 11437 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 11438 MDIO_AN_REG_1000T_STATUS, &val); 11439 11440 if (val & (1<<10)) 11441 vars->link_status |= 11442 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 11443 if (val & (1<<11)) 11444 vars->link_status |= 11445 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 11446 11447 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 11448 MDIO_AN_REG_MASTER_STATUS, &val); 11449 11450 if (val & (1<<11)) 11451 vars->link_status |= 11452 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 11453 11454 #if (!defined EXCLUDE_BCM84833) && (!defined EXCLUDE_WARPCORE) 11455 /* Determine if EEE was negotiated */ 11456 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 11457 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) 11458 elink_eee_an_resolve(phy, params, vars); 11459 #endif /* #ifndef EXCLUDE_WARPCORE */ 11460 } 11461 11462 return link_up; 11463 } 11464 11465 static elink_status_t 11466 elink_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) 11467 { 11468 elink_status_t status = ELINK_STATUS_OK; 11469 #ifdef ELINK_ENHANCEMENTS 11470 u32 spirom_ver; 11471 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); 11472 status = elink_format_ver(spirom_ver, str, len); 11473 #endif // ELINK_ENHANCEMENTS 11474 return status; 11475 } 11476 11477 #ifndef EXCLUDE_BCM8481 11478 static void elink_8481_hw_reset(struct elink_phy *phy, 11479 struct elink_params *params) 11480 { 11481 ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_1, 11482 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); 11483 ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_1, 11484 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); 11485 } 11486 11487 static void elink_8481_link_reset(struct elink_phy *phy, 11488 struct elink_params *params) 11489 { 11490 #ifndef EXCLUDE_LINK_RESET 11491 elink_cl45_write(params->cb, phy, 11492 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 11493 elink_cl45_write(params->cb, phy, 11494 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); 11495 #endif // EXCLUDE_LINK_RESET 11496 } 11497 #endif // #ifndef EXCLUDE_8481 11498 11499 static void elink_848x3_link_reset(struct elink_phy *phy, 11500 struct elink_params *params) 11501 { 11502 struct elink_dev *cb = params->cb; 11503 u8 port; 11504 u16 val16; 11505 11506 if (!(CHIP_IS_E1X(params->chip_id))) 11507 port = PATH_ID(cb); 11508 else 11509 port = params->port; 11510 11511 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 11512 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_3, 11513 MISC_REGISTERS_GPIO_OUTPUT_LOW, 11514 port); 11515 } else { 11516 elink_cl45_read(cb, phy, 11517 MDIO_CTL_DEVAD, 11518 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); 11519 val16 |= MDIO_84833_SUPER_ISOLATE; 11520 elink_cl45_write(cb, phy, 11521 MDIO_CTL_DEVAD, 11522 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); 11523 } 11524 } 11525 11526 static void elink_848xx_set_link_led(struct elink_phy *phy, 11527 struct elink_params *params, u8 mode) 11528 { 11529 struct elink_dev *cb = params->cb; 11530 u16 val; 11531 #ifndef ELINK_AUX_POWER 11532 u8 port; 11533 11534 if (!(CHIP_IS_E1X(params->chip_id))) 11535 port = PATH_ID(cb); 11536 else 11537 port = params->port; 11538 #endif 11539 switch (mode) { 11540 case ELINK_LED_MODE_OFF: 11541 11542 ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE OFF\n", port); 11543 11544 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 11545 SHARED_HW_CFG_LED_EXTPHY1) { 11546 11547 /* Set LED masks */ 11548 elink_cl45_write(cb, phy, 11549 MDIO_PMA_DEVAD, 11550 MDIO_PMA_REG_8481_LED1_MASK, 11551 0x0); 11552 11553 elink_cl45_write(cb, phy, 11554 MDIO_PMA_DEVAD, 11555 MDIO_PMA_REG_8481_LED2_MASK, 11556 0x0); 11557 11558 elink_cl45_write(cb, phy, 11559 MDIO_PMA_DEVAD, 11560 MDIO_PMA_REG_8481_LED3_MASK, 11561 0x0); 11562 11563 elink_cl45_write(cb, phy, 11564 MDIO_PMA_DEVAD, 11565 MDIO_PMA_REG_8481_LED5_MASK, 11566 0x0); 11567 11568 } else { 11569 elink_cl45_write(cb, phy, 11570 MDIO_PMA_DEVAD, 11571 MDIO_PMA_REG_8481_LED1_MASK, 11572 0x0); 11573 } 11574 break; 11575 case ELINK_LED_MODE_FRONT_PANEL_OFF: 11576 11577 ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE FRONT PANEL OFF\n", 11578 port); 11579 11580 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 11581 SHARED_HW_CFG_LED_EXTPHY1) { 11582 11583 /* Set LED masks */ 11584 elink_cl45_write(cb, phy, 11585 MDIO_PMA_DEVAD, 11586 MDIO_PMA_REG_8481_LED1_MASK, 11587 0x0); 11588 11589 elink_cl45_write(cb, phy, 11590 MDIO_PMA_DEVAD, 11591 MDIO_PMA_REG_8481_LED2_MASK, 11592 0x0); 11593 11594 elink_cl45_write(cb, phy, 11595 MDIO_PMA_DEVAD, 11596 MDIO_PMA_REG_8481_LED3_MASK, 11597 0x0); 11598 11599 elink_cl45_write(cb, phy, 11600 MDIO_PMA_DEVAD, 11601 MDIO_PMA_REG_8481_LED5_MASK, 11602 0x20); 11603 11604 } else { 11605 elink_cl45_write(cb, phy, 11606 MDIO_PMA_DEVAD, 11607 MDIO_PMA_REG_8481_LED1_MASK, 11608 0x0); 11609 if (phy->type == 11610 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 11611 /* Disable MI_INT interrupt before setting LED4 11612 * source to constant off. 11613 */ 11614 if (REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 + 11615 params->port*4) & 11616 ELINK_NIG_MASK_MI_INT) { 11617 params->link_flags |= 11618 ELINK_LINK_FLAGS_INT_DISABLED; 11619 11620 elink_bits_dis( 11621 cb, 11622 NIG_REG_MASK_INTERRUPT_PORT0 + 11623 params->port*4, 11624 ELINK_NIG_MASK_MI_INT); 11625 } 11626 elink_cl45_write(cb, phy, 11627 MDIO_PMA_DEVAD, 11628 MDIO_PMA_REG_8481_SIGNAL_MASK, 11629 0x0); 11630 } 11631 } 11632 break; 11633 case ELINK_LED_MODE_ON: 11634 11635 ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE ON\n", port); 11636 11637 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 11638 SHARED_HW_CFG_LED_EXTPHY1) { 11639 /* Set control reg */ 11640 elink_cl45_read(cb, phy, 11641 MDIO_PMA_DEVAD, 11642 MDIO_PMA_REG_8481_LINK_SIGNAL, 11643 &val); 11644 val &= 0x8000; 11645 val |= 0x2492; 11646 11647 elink_cl45_write(cb, phy, 11648 MDIO_PMA_DEVAD, 11649 MDIO_PMA_REG_8481_LINK_SIGNAL, 11650 val); 11651 11652 /* Set LED masks */ 11653 elink_cl45_write(cb, phy, 11654 MDIO_PMA_DEVAD, 11655 MDIO_PMA_REG_8481_LED1_MASK, 11656 0x0); 11657 11658 elink_cl45_write(cb, phy, 11659 MDIO_PMA_DEVAD, 11660 MDIO_PMA_REG_8481_LED2_MASK, 11661 0x20); 11662 11663 elink_cl45_write(cb, phy, 11664 MDIO_PMA_DEVAD, 11665 MDIO_PMA_REG_8481_LED3_MASK, 11666 0x20); 11667 11668 elink_cl45_write(cb, phy, 11669 MDIO_PMA_DEVAD, 11670 MDIO_PMA_REG_8481_LED5_MASK, 11671 0x0); 11672 } else { 11673 elink_cl45_write(cb, phy, 11674 MDIO_PMA_DEVAD, 11675 MDIO_PMA_REG_8481_LED1_MASK, 11676 0x20); 11677 if (phy->type == 11678 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 11679 /* Disable MI_INT interrupt before setting LED4 11680 * source to constant on. 11681 */ 11682 if (REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 + 11683 params->port*4) & 11684 ELINK_NIG_MASK_MI_INT) { 11685 params->link_flags |= 11686 ELINK_LINK_FLAGS_INT_DISABLED; 11687 11688 elink_bits_dis( 11689 cb, 11690 NIG_REG_MASK_INTERRUPT_PORT0 + 11691 params->port*4, 11692 ELINK_NIG_MASK_MI_INT); 11693 } 11694 elink_cl45_write(cb, phy, 11695 MDIO_PMA_DEVAD, 11696 MDIO_PMA_REG_8481_SIGNAL_MASK, 11697 0x20); 11698 } 11699 } 11700 break; 11701 11702 case ELINK_LED_MODE_OPER: 11703 11704 ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE OPER\n", port); 11705 11706 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 11707 SHARED_HW_CFG_LED_EXTPHY1) { 11708 11709 /* Set control reg */ 11710 elink_cl45_read(cb, phy, 11711 MDIO_PMA_DEVAD, 11712 MDIO_PMA_REG_8481_LINK_SIGNAL, 11713 &val); 11714 11715 if (!((val & 11716 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) 11717 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { 11718 ELINK_DEBUG_P0(cb, "Setting LINK_SIGNAL\n"); 11719 elink_cl45_write(cb, phy, 11720 MDIO_PMA_DEVAD, 11721 MDIO_PMA_REG_8481_LINK_SIGNAL, 11722 0xa492); 11723 } 11724 11725 /* Set LED masks */ 11726 elink_cl45_write(cb, phy, 11727 MDIO_PMA_DEVAD, 11728 MDIO_PMA_REG_8481_LED1_MASK, 11729 0x10); 11730 11731 elink_cl45_write(cb, phy, 11732 MDIO_PMA_DEVAD, 11733 MDIO_PMA_REG_8481_LED2_MASK, 11734 0x80); 11735 11736 elink_cl45_write(cb, phy, 11737 MDIO_PMA_DEVAD, 11738 MDIO_PMA_REG_8481_LED3_MASK, 11739 0x98); 11740 11741 elink_cl45_write(cb, phy, 11742 MDIO_PMA_DEVAD, 11743 MDIO_PMA_REG_8481_LED5_MASK, 11744 0x40); 11745 11746 } else { 11747 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED 11748 * sources are all wired through LED1, rather than only 11749 * 10G in other modes. 11750 */ 11751 val = ((params->hw_led_mode << 11752 SHARED_HW_CFG_LED_MODE_SHIFT) == 11753 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80; 11754 11755 elink_cl45_write(cb, phy, 11756 MDIO_PMA_DEVAD, 11757 MDIO_PMA_REG_8481_LED1_MASK, 11758 val); 11759 11760 /* Tell LED3 to blink on source */ 11761 elink_cl45_read(cb, phy, 11762 MDIO_PMA_DEVAD, 11763 MDIO_PMA_REG_8481_LINK_SIGNAL, 11764 &val); 11765 val &= ~(7<<6); 11766 val |= (1<<6); /* A83B[8:6]= 1 */ 11767 elink_cl45_write(cb, phy, 11768 MDIO_PMA_DEVAD, 11769 MDIO_PMA_REG_8481_LINK_SIGNAL, 11770 val); 11771 if (phy->type == 11772 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 11773 /* Restore LED4 source to external link, 11774 * and re-enable interrupts. 11775 */ 11776 elink_cl45_write(cb, phy, 11777 MDIO_PMA_DEVAD, 11778 MDIO_PMA_REG_8481_SIGNAL_MASK, 11779 0x40); 11780 if (params->link_flags & 11781 ELINK_LINK_FLAGS_INT_DISABLED) { 11782 elink_link_int_enable(params); 11783 params->link_flags &= 11784 ~ELINK_LINK_FLAGS_INT_DISABLED; 11785 } 11786 } 11787 } 11788 break; 11789 } 11790 11791 /* This is a workaround for E3+84833 until autoneg 11792 * restart is fixed in f/w 11793 */ 11794 if (CHIP_IS_E3(params->chip_id)) { 11795 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 11796 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); 11797 } 11798 } 11799 #endif /* EXCLUDE_BCM8481 / EXCLUDE_BCM8481 */ 11800 #endif // EXCLUDE_NON_COMMON_INIT 11801 11802 /******************************************************************/ 11803 /* 54618SE PHY SECTION */ 11804 /******************************************************************/ 11805 #if (!defined EXCLUDE_NON_COMMON_INIT) && (!defined EXCLUDE_BCM54618SE) 11806 #ifdef ELINK_AUX_POWER 11807 static int elink_54618se_init_required(struct elink_phy *phy, 11808 struct elink_params *params) 11809 { 11810 u16 autoneg_val, an_1000_val, an_10_100_val, ctrl, legacy_status; 11811 struct elink_dev *cb = params->cb; 11812 /* read all advertisement */ 11813 elink_cl22_read(cb, phy, 11814 MDIO_PMA_REG_CTRL, &ctrl); 11815 /* In case PHY is in reset */ 11816 if (ctrl & (1<<15)) 11817 return 1; 11818 11819 elink_cl22_read(cb, phy, 11820 0x09, 11821 &an_1000_val); 11822 elink_cl22_read(cb, phy, 11823 0x04, 11824 &an_10_100_val); 11825 elink_cl22_read(cb, phy, 11826 MDIO_PMA_REG_CTRL, 11827 &autoneg_val); 11828 elink_cl22_read(cb, phy, 11829 0x19, 11830 &legacy_status); 11831 /* Check conditions to avoid link reset in case link was 11832 * already initialized and up 11833 */ 11834 if ((an_1000_val & 0x300) && 11835 (an_10_100_val & 0x1e0) && 11836 (autoneg_val & 0x1000) && 11837 (legacy_status & (1<<2))) 11838 return 0; 11839 return 1; 11840 } 11841 #endif // ELINK_AUX_POWER 11842 static void elink_54618se_specific_func(struct elink_phy *phy, 11843 struct elink_params *params, 11844 u32 action) 11845 { 11846 struct elink_dev *cb = params->cb; 11847 u16 temp; 11848 switch (action) { 11849 case ELINK_PHY_INIT: 11850 /* Configure LED4: set to INTR (0x6). */ 11851 /* Accessing shadow register 0xe. */ 11852 elink_cl22_write(cb, phy, 11853 MDIO_REG_GPHY_SHADOW, 11854 MDIO_REG_GPHY_SHADOW_LED_SEL2); 11855 elink_cl22_read(cb, phy, 11856 MDIO_REG_GPHY_SHADOW, 11857 &temp); 11858 temp &= ~(0xf << 4); 11859 temp |= (0x6 << 4); 11860 elink_cl22_write(cb, phy, 11861 MDIO_REG_GPHY_SHADOW, 11862 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 11863 /* Configure INTR based on link status change. */ 11864 elink_cl22_write(cb, phy, 11865 MDIO_REG_INTR_MASK, 11866 ~MDIO_REG_INTR_MASK_LINK_STATUS); 11867 break; 11868 } 11869 } 11870 11871 static elink_status_t 11872 elink_54618se_config_init(struct elink_phy *phy, 11873 struct elink_params *params, struct elink_vars *vars) 11874 { 11875 struct elink_dev *cb = params->cb; 11876 u8 port; 11877 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; 11878 u32 cfg_pin; 11879 #ifdef ELINK_AUX_POWER 11880 u32 link_init_required = 1; 11881 if (!elink_54618se_init_required(phy, params)) 11882 link_init_required = 0; 11883 if (link_init_required) { 11884 #endif 11885 11886 ELINK_DEBUG_P0(cb, "54618SE cfg init\n"); 11887 MSLEEP(cb, 1); 11888 11889 /* This works with E3 only, no need to check the chip 11890 * before determining the port. 11891 */ 11892 port = params->port; 11893 11894 cfg_pin = (REG_RD(cb, params->shmem_base + 11895 OFFSETOF(struct shmem_region, 11896 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 11897 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 11898 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 11899 11900 /* Drive pin high to bring the GPHY out of reset. */ 11901 elink_set_cfg_pin(cb, cfg_pin, 1); 11902 11903 /* wait for GPHY to reset */ 11904 MSLEEP(cb, 50); 11905 11906 /* reset phy */ 11907 elink_cl22_write(cb, phy, 11908 MDIO_PMA_REG_CTRL, 0x8000); 11909 elink_wait_reset_complete(cb, phy, params); 11910 11911 /* Wait for GPHY to reset */ 11912 MSLEEP(cb, 50); 11913 11914 #ifdef ELINK_AUX_POWER 11915 } // If init required 11916 #endif 11917 11918 elink_54618se_specific_func(phy, params, ELINK_PHY_INIT); 11919 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ 11920 elink_cl22_write(cb, phy, 11921 MDIO_REG_GPHY_SHADOW, 11922 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); 11923 elink_cl22_read(cb, phy, 11924 MDIO_REG_GPHY_SHADOW, 11925 &temp); 11926 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; 11927 elink_cl22_write(cb, phy, 11928 MDIO_REG_GPHY_SHADOW, 11929 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 11930 11931 /* Set up fc */ 11932 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 11933 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 11934 #ifdef ELINK_AUX_POWER 11935 if (!link_init_required) 11936 return ELINK_STATUS_OK; 11937 #endif 11938 fc_val = 0; 11939 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 11940 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) 11941 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 11942 11943 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 11944 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 11945 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 11946 11947 /* Read all advertisement */ 11948 elink_cl22_read(cb, phy, 11949 0x09, 11950 &an_1000_val); 11951 11952 elink_cl22_read(cb, phy, 11953 0x04, 11954 &an_10_100_val); 11955 11956 elink_cl22_read(cb, phy, 11957 MDIO_PMA_REG_CTRL, 11958 &autoneg_val); 11959 11960 /* Disable forced speed */ 11961 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 11962 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | 11963 (1<<11)); 11964 11965 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 11966 (phy->speed_cap_mask & 11967 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 11968 (phy->req_line_speed == ELINK_SPEED_1000)) { 11969 an_1000_val |= (1<<8); 11970 autoneg_val |= (1<<9 | 1<<12); 11971 if (phy->req_duplex == DUPLEX_FULL) 11972 an_1000_val |= (1<<9); 11973 ELINK_DEBUG_P0(cb, "Advertising 1G\n"); 11974 } else 11975 an_1000_val &= ~((1<<8) | (1<<9)); 11976 11977 elink_cl22_write(cb, phy, 11978 0x09, 11979 an_1000_val); 11980 elink_cl22_read(cb, phy, 11981 0x09, 11982 &an_1000_val); 11983 11984 /* Advertise 10/100 link speed */ 11985 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { 11986 if (phy->speed_cap_mask & 11987 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { 11988 an_10_100_val |= (1<<5); 11989 autoneg_val |= (1<<9 | 1<<12); 11990 ELINK_DEBUG_P0(cb, "Advertising 10M-HD\n"); 11991 } 11992 if (phy->speed_cap_mask & 11993 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) { 11994 an_10_100_val |= (1<<6); 11995 autoneg_val |= (1<<9 | 1<<12); 11996 ELINK_DEBUG_P0(cb, "Advertising 10M-FD\n"); 11997 } 11998 if (phy->speed_cap_mask & 11999 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { 12000 an_10_100_val |= (1<<7); 12001 autoneg_val |= (1<<9 | 1<<12); 12002 ELINK_DEBUG_P0(cb, "Advertising 100M-HD\n"); 12003 } 12004 if (phy->speed_cap_mask & 12005 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { 12006 an_10_100_val |= (1<<8); 12007 autoneg_val |= (1<<9 | 1<<12); 12008 ELINK_DEBUG_P0(cb, "Advertising 100M-FD\n"); 12009 } 12010 } 12011 12012 /* Only 10/100 are allowed to work in FORCE mode */ 12013 if (phy->req_line_speed == ELINK_SPEED_100) { 12014 autoneg_val |= (1<<13); 12015 /* Enabled AUTO-MDIX when autoneg is disabled */ 12016 elink_cl22_write(cb, phy, 12017 0x18, 12018 (1<<15 | 1<<9 | 7<<0)); 12019 ELINK_DEBUG_P0(cb, "Setting 100M force\n"); 12020 } 12021 if (phy->req_line_speed == ELINK_SPEED_10) { 12022 /* Enabled AUTO-MDIX when autoneg is disabled */ 12023 elink_cl22_write(cb, phy, 12024 0x18, 12025 (1<<15 | 1<<9 | 7<<0)); 12026 ELINK_DEBUG_P0(cb, "Setting 10M force\n"); 12027 } 12028 12029 if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) { 12030 elink_status_t rc; 12031 12032 elink_cl22_write(cb, phy, MDIO_REG_GPHY_EXP_ACCESS, 12033 MDIO_REG_GPHY_EXP_ACCESS_TOP | 12034 MDIO_REG_GPHY_EXP_TOP_2K_BUF); 12035 elink_cl22_read(cb, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); 12036 temp &= 0xfffe; 12037 elink_cl22_write(cb, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); 12038 12039 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); 12040 if (rc != ELINK_STATUS_OK) { 12041 ELINK_DEBUG_P0(cb, "Failed to configure EEE timers\n"); 12042 elink_eee_disable(phy, params, vars); 12043 } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) && 12044 (phy->req_duplex == DUPLEX_FULL) && 12045 (elink_eee_calc_timer(params) || 12046 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) { 12047 /* Need to advertise EEE only when requested, 12048 * and either no LPI assertion was requested, 12049 * or it was requested and a valid timer was set. 12050 * Also notice full duplex is required for EEE. 12051 */ 12052 elink_eee_advertise(phy, params, vars, 12053 SHMEM_EEE_1G_ADV); 12054 } else { 12055 ELINK_DEBUG_P0(cb, "Don't Advertise 1GBase-T EEE\n"); 12056 elink_eee_disable(phy, params, vars); 12057 } 12058 } else { 12059 vars->eee_status &= ~SHMEM_EEE_1G_ADV << 12060 SHMEM_EEE_SUPPORTED_SHIFT; 12061 12062 if (phy->flags & ELINK_FLAGS_EEE) { 12063 /* Handle legacy auto-grEEEn */ 12064 if (params->feature_config_flags & 12065 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) { 12066 temp = 6; 12067 ELINK_DEBUG_P0(cb, "Enabling Auto-GrEEEn\n"); 12068 } else { 12069 temp = 0; 12070 ELINK_DEBUG_P0(cb, "Don't Adv. EEE\n"); 12071 } 12072 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 12073 MDIO_AN_REG_EEE_ADV, temp); 12074 } 12075 } 12076 12077 elink_cl22_write(cb, phy, 12078 0x04, 12079 an_10_100_val | fc_val); 12080 12081 if (phy->req_duplex == DUPLEX_FULL) 12082 autoneg_val |= (1<<8); 12083 12084 elink_cl22_write(cb, phy, 12085 MDIO_PMA_REG_CTRL, autoneg_val); 12086 12087 return ELINK_STATUS_OK; 12088 } 12089 12090 12091 static void elink_5461x_set_link_led(struct elink_phy *phy, 12092 struct elink_params *params, u8 mode) 12093 { 12094 #ifdef ELINK_ENHANCEMENTS 12095 struct elink_dev *cb = params->cb; 12096 u16 temp; 12097 12098 elink_cl22_write(cb, phy, 12099 MDIO_REG_GPHY_SHADOW, 12100 MDIO_REG_GPHY_SHADOW_LED_SEL1); 12101 elink_cl22_read(cb, phy, 12102 MDIO_REG_GPHY_SHADOW, 12103 &temp); 12104 temp &= 0xff00; 12105 12106 ELINK_DEBUG_P1(cb, "54618x set link led (mode=%x)\n", mode); 12107 switch (mode) { 12108 case ELINK_LED_MODE_FRONT_PANEL_OFF: 12109 case ELINK_LED_MODE_OFF: 12110 temp |= 0x00ee; 12111 break; 12112 case ELINK_LED_MODE_OPER: 12113 temp |= 0x0001; 12114 break; 12115 case ELINK_LED_MODE_ON: 12116 temp |= 0x00ff; 12117 break; 12118 default: 12119 break; 12120 } 12121 elink_cl22_write(cb, phy, 12122 MDIO_REG_GPHY_SHADOW, 12123 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 12124 return; 12125 #endif // ELINK_ENHANCEMENTS 12126 } 12127 12128 12129 static void elink_54618se_link_reset(struct elink_phy *phy, 12130 struct elink_params *params) 12131 { 12132 struct elink_dev *cb = params->cb; 12133 u32 cfg_pin; 12134 u8 port; 12135 12136 #ifdef ELINK_AUX_POWER 12137 if (!elink_54618se_init_required(phy, params)) 12138 return; 12139 #endif // ELINK_AUX_POWER 12140 /* In case of no EPIO routed to reset the GPHY, put it 12141 * in low power mode. 12142 */ 12143 elink_cl22_write(cb, phy, MDIO_PMA_REG_CTRL, 0x800); 12144 /* This works with E3 only, no need to check the chip 12145 * before determining the port. 12146 */ 12147 port = params->port; 12148 cfg_pin = (REG_RD(cb, params->shmem_base + 12149 OFFSETOF(struct shmem_region, 12150 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 12151 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 12152 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 12153 12154 /* Drive pin low to put GPHY in reset. */ 12155 elink_set_cfg_pin(cb, cfg_pin, 0); 12156 } 12157 12158 static elink_status_t 12159 elink_54618se_read_status(struct elink_phy *phy, struct elink_params *params, 12160 struct elink_vars *vars) 12161 { 12162 struct elink_dev *cb = params->cb; 12163 u16 val; 12164 u8 link_up = 0; 12165 u16 legacy_status, legacy_speed; 12166 12167 /* Get speed operation status */ 12168 elink_cl22_read(cb, phy, 12169 MDIO_REG_GPHY_AUX_STATUS, 12170 &legacy_status); 12171 ELINK_DEBUG_P1(cb, "54618SE read_status: 0x%x\n", legacy_status); 12172 12173 /* Read status to clear the PHY interrupt. */ 12174 elink_cl22_read(cb, phy, 12175 MDIO_REG_INTR_STATUS, 12176 &val); 12177 12178 link_up = ((legacy_status & (1<<2)) == (1<<2)); 12179 12180 if (link_up) { 12181 legacy_speed = (legacy_status & (7<<8)); 12182 if (legacy_speed == (7<<8)) { 12183 vars->line_speed = ELINK_SPEED_1000; 12184 vars->duplex = DUPLEX_FULL; 12185 } else if (legacy_speed == (6<<8)) { 12186 vars->line_speed = ELINK_SPEED_1000; 12187 vars->duplex = DUPLEX_HALF; 12188 } else if (legacy_speed == (5<<8)) { 12189 vars->line_speed = ELINK_SPEED_100; 12190 vars->duplex = DUPLEX_FULL; 12191 } 12192 /* Omitting 100Base-T4 for now */ 12193 else if (legacy_speed == (3<<8)) { 12194 vars->line_speed = ELINK_SPEED_100; 12195 vars->duplex = DUPLEX_HALF; 12196 } else if (legacy_speed == (2<<8)) { 12197 vars->line_speed = ELINK_SPEED_10; 12198 vars->duplex = DUPLEX_FULL; 12199 } else if (legacy_speed == (1<<8)) { 12200 vars->line_speed = ELINK_SPEED_10; 12201 vars->duplex = DUPLEX_HALF; 12202 } else /* Should not happen */ 12203 vars->line_speed = 0; 12204 12205 ELINK_DEBUG_P2(cb, 12206 "Link is up in %dMbps, is_duplex_full= %d\n", 12207 vars->line_speed, 12208 (vars->duplex == DUPLEX_FULL)); 12209 12210 /* Check legacy speed AN resolution */ 12211 elink_cl22_read(cb, phy, 12212 0x01, 12213 &val); 12214 if (val & (1<<5)) 12215 vars->link_status |= 12216 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 12217 elink_cl22_read(cb, phy, 12218 0x06, 12219 &val); 12220 if ((val & (1<<0)) == 0) 12221 vars->link_status |= 12222 LINK_STATUS_PARALLEL_DETECTION_USED; 12223 12224 ELINK_DEBUG_P1(cb, "BCM54618SE: link speed is %d\n", 12225 vars->line_speed); 12226 12227 elink_ext_phy_resolve_fc(phy, params, vars); 12228 12229 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 12230 /* Report LP advertised speeds */ 12231 elink_cl22_read(cb, phy, 0x5, &val); 12232 12233 if (val & (1<<5)) 12234 vars->link_status |= 12235 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 12236 if (val & (1<<6)) 12237 vars->link_status |= 12238 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 12239 if (val & (1<<7)) 12240 vars->link_status |= 12241 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 12242 if (val & (1<<8)) 12243 vars->link_status |= 12244 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 12245 if (val & (1<<9)) 12246 vars->link_status |= 12247 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 12248 12249 elink_cl22_read(cb, phy, 0xa, &val); 12250 if (val & (1<<10)) 12251 vars->link_status |= 12252 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 12253 if (val & (1<<11)) 12254 vars->link_status |= 12255 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 12256 12257 if ((phy->flags & ELINK_FLAGS_EEE) && 12258 elink_eee_has_cap(params)) 12259 elink_eee_an_resolve(phy, params, vars); 12260 } 12261 } 12262 return link_up; 12263 } 12264 12265 static void elink_54618se_config_loopback(struct elink_phy *phy, 12266 struct elink_params *params) 12267 { 12268 #ifdef ELINK_INCLUDE_LOOPBACK 12269 struct elink_dev *cb = params->cb; 12270 u16 val; 12271 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 12272 12273 ELINK_DEBUG_P0(cb, "2PMA/PMD ext_phy_loopback: 54618se\n"); 12274 12275 /* Enable master/slave manual mmode and set to master */ 12276 /* mii write 9 [bits set 11 12] */ 12277 elink_cl22_write(cb, phy, 0x09, 3<<11); 12278 12279 /* forced 1G and disable autoneg */ 12280 /* set val [mii read 0] */ 12281 /* set val [expr $val & [bits clear 6 12 13]] */ 12282 /* set val [expr $val | [bits set 6 8]] */ 12283 /* mii write 0 $val */ 12284 elink_cl22_read(cb, phy, 0x00, &val); 12285 val &= ~((1<<6) | (1<<12) | (1<<13)); 12286 val |= (1<<6) | (1<<8); 12287 elink_cl22_write(cb, phy, 0x00, val); 12288 12289 /* Set external loopback and Tx using 6dB coding */ 12290 /* mii write 0x18 7 */ 12291 /* set val [mii read 0x18] */ 12292 /* mii write 0x18 [expr $val | [bits set 10 15]] */ 12293 elink_cl22_write(cb, phy, 0x18, 7); 12294 elink_cl22_read(cb, phy, 0x18, &val); 12295 elink_cl22_write(cb, phy, 0x18, val | (1<<10) | (1<<15)); 12296 12297 /* This register opens the gate for the UMAC despite its name */ 12298 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 12299 12300 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 12301 * length used by the MAC receive logic to check frames. 12302 */ 12303 REG_WR(cb, umac_base + UMAC_REG_MAXFR, 0x2710); 12304 #endif // ELINK_INCLUDE_LOOPBACK 12305 } 12306 12307 #endif // (!defined EXCLUDE_NON_COMMON_INIT) && (!defined EXCLUDE_BCM54618SE) 12308 /******************************************************************/ 12309 /* SFX7101 PHY SECTION */ 12310 /******************************************************************/ 12311 #ifndef EXCLUDE_SFX7101 12312 static void elink_7101_config_loopback(struct elink_phy *phy, 12313 struct elink_params *params) 12314 { 12315 struct elink_dev *cb = params->cb; 12316 /* SFX7101_XGXS_TEST1 */ 12317 elink_cl45_write(cb, phy, 12318 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); 12319 } 12320 12321 static elink_status_t elink_7101_config_init(struct elink_phy *phy, 12322 struct elink_params *params, 12323 struct elink_vars *vars) 12324 { 12325 u16 fw_ver1, fw_ver2, val; 12326 struct elink_dev *cb = params->cb; 12327 ELINK_DEBUG_P0(cb, "Setting the SFX7101 LASI indication\n"); 12328 12329 /* Restore normal power mode*/ 12330 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 12331 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 12332 /* HW reset */ 12333 elink_ext_phy_hw_reset(cb, params->port); 12334 elink_wait_reset_complete(cb, phy, params); 12335 12336 elink_cl45_write(cb, phy, 12337 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); 12338 ELINK_DEBUG_P0(cb, "Setting the SFX7101 LED to blink on traffic\n"); 12339 elink_cl45_write(cb, phy, 12340 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); 12341 12342 elink_ext_phy_set_pause(params, phy, vars); 12343 /* Restart autoneg */ 12344 elink_cl45_read(cb, phy, 12345 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); 12346 val |= 0x200; 12347 elink_cl45_write(cb, phy, 12348 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); 12349 12350 /* Save spirom version */ 12351 elink_cl45_read(cb, phy, 12352 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); 12353 12354 elink_cl45_read(cb, phy, 12355 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); 12356 elink_save_spirom_version(cb, params->port, 12357 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); 12358 return ELINK_STATUS_OK; 12359 } 12360 12361 static elink_status_t 12362 elink_7101_read_status(struct elink_phy *phy, struct elink_params *params, 12363 struct elink_vars *vars) 12364 { 12365 struct elink_dev *cb = params->cb; 12366 u8 link_up; 12367 u16 val1, val2; 12368 elink_cl45_read(cb, phy, 12369 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 12370 elink_cl45_read(cb, phy, 12371 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 12372 ELINK_DEBUG_P2(cb, "10G-base-T LASI status 0x%x->0x%x\n", 12373 val2, val1); 12374 elink_cl45_read(cb, phy, 12375 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 12376 elink_cl45_read(cb, phy, 12377 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 12378 ELINK_DEBUG_P2(cb, "10G-base-T PMA status 0x%x->0x%x\n", 12379 val2, val1); 12380 link_up = ((val1 & 4) == 4); 12381 /* If link is up print the AN outcome of the SFX7101 PHY */ 12382 if (link_up) { 12383 elink_cl45_read(cb, phy, 12384 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, 12385 &val2); 12386 vars->line_speed = ELINK_SPEED_10000; 12387 vars->duplex = DUPLEX_FULL; 12388 ELINK_DEBUG_P2(cb, "SFX7101 AN status 0x%x->Master=%x\n", 12389 val2, (val2 & (1<<14))); 12390 elink_ext_phy_10G_an_resolve(cb, phy, vars); 12391 elink_ext_phy_resolve_fc(phy, params, vars); 12392 12393 /* Read LP advertised speeds */ 12394 if (val2 & (1<<11)) 12395 vars->link_status |= 12396 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 12397 } 12398 return link_up; 12399 } 12400 12401 static elink_status_t 12402 elink_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) 12403 { 12404 if (*len < 5) 12405 return ELINK_STATUS_ERROR; 12406 str[0] = (spirom_ver & 0xFF); 12407 str[1] = (spirom_ver & 0xFF00) >> 8; 12408 str[2] = (spirom_ver & 0xFF0000) >> 16; 12409 str[3] = (spirom_ver & 0xFF000000) >> 24; 12410 str[4] = '\0'; 12411 *len -= 5; 12412 return ELINK_STATUS_OK; 12413 } 12414 12415 void elink_sfx7101_sp_sw_reset(struct elink_dev *cb, struct elink_phy *phy) 12416 { 12417 u16 val, cnt; 12418 12419 elink_cl45_read(cb, phy, 12420 MDIO_PMA_DEVAD, 12421 MDIO_PMA_REG_7101_RESET, &val); 12422 12423 for (cnt = 0; cnt < 10; cnt++) { 12424 MSLEEP(cb, 50); 12425 /* Writes a self-clearing reset */ 12426 elink_cl45_write(cb, phy, 12427 MDIO_PMA_DEVAD, 12428 MDIO_PMA_REG_7101_RESET, 12429 (val | (1<<15))); 12430 /* Wait for clear */ 12431 elink_cl45_read(cb, phy, 12432 MDIO_PMA_DEVAD, 12433 MDIO_PMA_REG_7101_RESET, &val); 12434 12435 if ((val & (1<<15)) == 0) 12436 break; 12437 } 12438 } 12439 12440 static void elink_7101_hw_reset(struct elink_phy *phy, 12441 struct elink_params *params) { 12442 #ifdef ELINK_ENHANCEMENTS 12443 /* Low power mode is controlled by GPIO 2 */ 12444 ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_2, 12445 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 12446 /* The PHY reset is controlled by GPIO 1 */ 12447 ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_1, 12448 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 12449 #endif // ELINK_ENHANCEMENTS 12450 } 12451 12452 static void elink_7101_set_link_led(struct elink_phy *phy, 12453 struct elink_params *params, u8 mode) 12454 { 12455 u16 val = 0; 12456 struct elink_dev *cb = params->cb; 12457 switch (mode) { 12458 case ELINK_LED_MODE_FRONT_PANEL_OFF: 12459 case ELINK_LED_MODE_OFF: 12460 val = 2; 12461 break; 12462 case ELINK_LED_MODE_ON: 12463 val = 1; 12464 break; 12465 case ELINK_LED_MODE_OPER: 12466 val = 0; 12467 break; 12468 } 12469 elink_cl45_write(cb, phy, 12470 MDIO_PMA_DEVAD, 12471 MDIO_PMA_REG_7107_LINK_LED_CNTL, 12472 val); 12473 } 12474 #endif /* EXCLUDE_SFX7101 */ 12475 #endif /* ELINK_EMUL_ONLY */ 12476 12477 /******************************************************************/ 12478 /* STATIC PHY DECLARATION */ 12479 /******************************************************************/ 12480 12481 static const struct elink_phy phy_null = { 12482 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, 12483 /*.addr = */0, 12484 /*.def_md_devad = */0, 12485 /*.flags = */ELINK_FLAGS_INIT_XGXS_FIRST, 12486 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12487 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12488 /*.mdio_ctrl = */0, 12489 /*.supported = */0, 12490 /*.media_type = */ELINK_ETH_PHY_NOT_PRESENT, 12491 /*.sfp_media = */ELINK_ETH_SFP_UNKNOWN, 12492 /*.ver_addr = */0, 12493 /*.req_flow_ctrl = */0, 12494 /*.req_line_speed = */0, 12495 /*.speed_cap_mask = */0, 12496 /*.req_duplex = */0, 12497 /*.rsrv = */0, 12498 /*.config_init = */(config_init_t)NULL, 12499 /*.read_status = */(read_status_t)NULL, 12500 /*.link_reset = */(link_reset_t)NULL, 12501 /*.config_loopback = */(config_loopback_t)NULL, 12502 /*.format_fw_ver = */(format_fw_ver_t)NULL, 12503 /*.hw_reset = */(hw_reset_t)NULL, 12504 /*.set_link_led = */(set_link_led_t)NULL, 12505 /*.phy_specific_func = */(phy_specific_func_t)NULL 12506 }; 12507 12508 #ifndef EXCLUDE_SERDES 12509 static const struct elink_phy phy_serdes = { 12510 /*.type = */PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, 12511 /*.addr = */0xff, 12512 /*.def_md_devad = */0, 12513 /*.flags = */0, 12514 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12515 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12516 /*.mdio_ctrl = */0, 12517 /*.supported = */(ELINK_SUPPORTED_10baseT_Half | 12518 ELINK_SUPPORTED_10baseT_Full | 12519 ELINK_SUPPORTED_100baseT_Half | 12520 ELINK_SUPPORTED_100baseT_Full | 12521 ELINK_SUPPORTED_1000baseT_Full | 12522 ELINK_SUPPORTED_2500baseX_Full | 12523 ELINK_SUPPORTED_TP | 12524 ELINK_SUPPORTED_Autoneg | 12525 ELINK_SUPPORTED_Pause | 12526 ELINK_SUPPORTED_Asym_Pause), 12527 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12528 /*.sfp_media = */ELINK_ETH_SFP_UNKNOWN, 12529 /*.ver_addr = */0, 12530 /*.req_flow_ctrl = */0, 12531 /*.req_line_speed = */0, 12532 /*.speed_cap_mask = */0, 12533 /*.req_duplex = */0, 12534 /*.rsrv = */0, 12535 /*.config_init = */elink_xgxs_config_init, 12536 /*.read_status = */elink_link_settings_status, 12537 /*.link_reset = */elink_int_link_reset, 12538 /*.config_loopback = */(config_loopback_t)NULL, 12539 /*.format_fw_ver = */(format_fw_ver_t)NULL, 12540 /*.hw_reset = */(hw_reset_t)NULL, 12541 /*.set_link_led = */(set_link_led_t)NULL, 12542 /*.phy_specific_func = */(phy_specific_func_t)NULL 12543 }; 12544 12545 #endif /* #ifndef EXCLUDE_SERDES */ 12546 #ifndef EXCLUDE_XGXS 12547 static const struct elink_phy phy_xgxs = { 12548 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 12549 /*.addr = */0xff, 12550 /*.def_md_devad = */0, 12551 /*.flags = */0, 12552 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12553 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12554 /*.mdio_ctrl = */0, 12555 /*.supported = */(ELINK_SUPPORTED_10baseT_Half | 12556 ELINK_SUPPORTED_10baseT_Full | 12557 ELINK_SUPPORTED_100baseT_Half | 12558 ELINK_SUPPORTED_100baseT_Full | 12559 ELINK_SUPPORTED_1000baseT_Full | 12560 ELINK_SUPPORTED_2500baseX_Full | 12561 ELINK_SUPPORTED_10000baseT_Full | 12562 ELINK_SUPPORTED_FIBRE | 12563 ELINK_SUPPORTED_Autoneg | 12564 ELINK_SUPPORTED_Pause | 12565 ELINK_SUPPORTED_Asym_Pause), 12566 /*.media_type = */ELINK_ETH_PHY_CX4, 12567 /*.sfp_media = */ELINK_ETH_SFP_UNKNOWN, 12568 /*.ver_addr = */0, 12569 /*.req_flow_ctrl = */0, 12570 /*.req_line_speed = */0, 12571 /*.speed_cap_mask = */0, 12572 /*.req_duplex = */0, 12573 /*.rsrv = */0, 12574 #ifndef EXCLUDE_NON_COMMON_INIT 12575 /*.config_init = */elink_xgxs_config_init, 12576 /*.read_status = */elink_link_settings_status, 12577 /*.link_reset = */elink_int_link_reset, 12578 /*.config_loopback = */elink_set_xgxs_loopback, 12579 /*.format_fw_ver= */(format_fw_ver_t)NULL, 12580 /*.hw_reset = */(hw_reset_t)NULL, 12581 /*.set_link_led = */(set_link_led_t)NULL, 12582 /*.phy_specific_func = */elink_xgxs_specific_func 12583 #endif 12584 }; 12585 #endif 12586 #ifndef EXCLUDE_WARPCORE 12587 static const struct elink_phy phy_warpcore = { 12588 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 12589 /*.addr = */0xff, 12590 /*.def_md_devad = */0, 12591 /*.flags = */ELINK_FLAGS_TX_ERROR_CHECK, 12592 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12593 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12594 /*.mdio_ctrl = */0, 12595 /*.supported = */(ELINK_SUPPORTED_10baseT_Half | 12596 ELINK_SUPPORTED_10baseT_Full | 12597 ELINK_SUPPORTED_100baseT_Half | 12598 ELINK_SUPPORTED_100baseT_Full | 12599 ELINK_SUPPORTED_1000baseT_Full | 12600 ELINK_SUPPORTED_10000baseT_Full | 12601 ELINK_SUPPORTED_20000baseKR2_Full | 12602 ELINK_SUPPORTED_20000baseMLD2_Full | 12603 ELINK_SUPPORTED_FIBRE | 12604 ELINK_SUPPORTED_Autoneg | 12605 ELINK_SUPPORTED_Pause | 12606 ELINK_SUPPORTED_Asym_Pause), 12607 /*.media_type = */ELINK_ETH_PHY_UNSPECIFIED, 12608 /*.sfp_media = */ELINK_ETH_SFP_UNKNOWN, 12609 /*.ver_addr = */0, 12610 /*.req_flow_ctrl = */0, 12611 /*.req_line_speed = */0, 12612 /*.speed_cap_mask = */0, 12613 /* req_duplex = */0, 12614 /* rsrv = */0, 12615 #ifndef EXCLUDE_NON_COMMON_INIT 12616 /*.config_init = */elink_warpcore_config_init, 12617 /*.read_status = */elink_warpcore_read_status, 12618 /*.link_reset = */elink_warpcore_link_reset, 12619 /*.config_loopback = */elink_set_warpcore_loopback, 12620 /*.format_fw_ver= */(format_fw_ver_t)NULL, 12621 /*.hw_reset = */elink_warpcore_hw_reset, 12622 /*.set_link_led = */(set_link_led_t)NULL, 12623 /*.phy_specific_func = */(phy_specific_func_t)NULL 12624 #endif 12625 }; 12626 12627 #endif /* #ifndef EXCLUDE_WARPCORE */ 12628 12629 #ifndef ELINK_EMUL_ONLY 12630 #ifndef EXCLUDE_SFX7101 12631 static const struct elink_phy phy_7101 = { 12632 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, 12633 /*.addr = */0xff, 12634 /*.def_md_devad = */0, 12635 /*.flags = */ELINK_FLAGS_FAN_FAILURE_DET_REQ, 12636 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12637 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12638 /*.mdio_ctrl = */0, 12639 /*.supported = */(ELINK_SUPPORTED_10000baseT_Full | 12640 ELINK_SUPPORTED_TP | 12641 ELINK_SUPPORTED_Autoneg | 12642 ELINK_SUPPORTED_Pause | 12643 ELINK_SUPPORTED_Asym_Pause), 12644 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12645 /*.sfp_media = */ELINK_ETH_SFP_UNKNOWN, 12646 /*.ver_addr = */0, 12647 /*.req_flow_ctrl = */0, 12648 /*.req_line_speed = */0, 12649 /*.speed_cap_mask = */0, 12650 /*.req_duplex = */0, 12651 /*.rsrv = */0, 12652 /*.config_init = */elink_7101_config_init, 12653 /*.read_status = */elink_7101_read_status, 12654 /*.link_reset = */elink_common_ext_link_reset, 12655 /*.config_loopback = */elink_7101_config_loopback, 12656 /*.format_fw_ver= */elink_7101_format_ver, 12657 /*.hw_reset = */elink_7101_hw_reset, 12658 /*.set_link_led = */elink_7101_set_link_led, 12659 /*.phy_specific_func = */(phy_specific_func_t)NULL 12660 }; 12661 #endif /* EXCLUDE_SFX7101 */ 12662 #ifndef EXCLUDE_BCM8727_BCM8073 12663 static const struct elink_phy phy_8073 = { 12664 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 12665 /*.addr = */0xff, 12666 /*.def_md_devad = */0, 12667 /*.flags = */0, 12668 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12669 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12670 /*.mdio_ctrl = */0, 12671 /*.supported = */(ELINK_SUPPORTED_10000baseT_Full | 12672 ELINK_SUPPORTED_2500baseX_Full | 12673 ELINK_SUPPORTED_1000baseT_Full | 12674 ELINK_SUPPORTED_FIBRE | 12675 ELINK_SUPPORTED_Autoneg | 12676 ELINK_SUPPORTED_Pause | 12677 ELINK_SUPPORTED_Asym_Pause), 12678 /*.media_type = */ELINK_ETH_PHY_KR, 12679 /*.sfp_media = */ELINK_ETH_SFP_UNKNOWN, 12680 /*.ver_addr = */0, 12681 /*.req_flow_ctrl = */0, 12682 /*.req_line_speed = */0, 12683 /*.speed_cap_mask = */0, 12684 /*.req_duplex = */0, 12685 /*.rsrv = */0, 12686 #ifndef EXCLUDE_NON_COMMON_INIT 12687 /*.config_init = */elink_8073_config_init, 12688 /*.read_status = */elink_8073_read_status, 12689 /*.link_reset = */elink_8073_link_reset, 12690 /*.config_loopback = */(config_loopback_t)NULL, 12691 /*.format_fw_ver= */elink_format_ver, 12692 /*.hw_reset = */(hw_reset_t)NULL, 12693 /*.set_link_led = */(set_link_led_t)NULL, 12694 /*.phy_specific_func = */elink_8073_specific_func 12695 #endif 12696 }; 12697 #endif 12698 #ifndef EXCLUDE_BCM8705 12699 static const struct elink_phy phy_8705 = { 12700 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, 12701 /*.addr = */0xff, 12702 /*.def_md_devad = */0, 12703 /*.flags = */ELINK_FLAGS_INIT_XGXS_FIRST, 12704 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12705 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12706 /*.mdio_ctrl = */0, 12707 /*.supported = */(ELINK_SUPPORTED_10000baseT_Full | 12708 ELINK_SUPPORTED_FIBRE | 12709 ELINK_SUPPORTED_Pause | 12710 ELINK_SUPPORTED_Asym_Pause), 12711 /*.media_type = */ELINK_ETH_PHY_XFP_FIBER, 12712 /*.sfp_media = */ELINK_ETH_SFP_UNKNOWN, 12713 /*.ver_addr = */0, 12714 /*.req_flow_ctrl = */0, 12715 /*.req_line_speed = */0, 12716 /*.speed_cap_mask = */0, 12717 /*.req_duplex = */0, 12718 /*.rsrv = */0, 12719 /*.config_init = */elink_8705_config_init, 12720 /*.read_status = */elink_8705_read_status, 12721 /*.link_reset = */elink_common_ext_link_reset, 12722 /*.config_loopback = */(config_loopback_t)NULL, 12723 /*.format_fw_ver= */elink_null_format_ver, 12724 /*.hw_reset = */(hw_reset_t)NULL, 12725 /*.set_link_led = */(set_link_led_t)NULL, 12726 /*.phy_specific_func = */(phy_specific_func_t)NULL 12727 }; 12728 #endif /* EXCLUDE_BCM8705 */ 12729 #ifndef EXCLUDE_BCM87x6 12730 static const struct elink_phy phy_8706 = { 12731 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, 12732 /*.addr = */0xff, 12733 /*.def_md_devad = */0, 12734 /*.flags = */ELINK_FLAGS_INIT_XGXS_FIRST, 12735 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12736 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12737 /*.mdio_ctrl = */0, 12738 /*.supported = */(ELINK_SUPPORTED_10000baseT_Full | 12739 ELINK_SUPPORTED_1000baseT_Full | 12740 ELINK_SUPPORTED_FIBRE | 12741 ELINK_SUPPORTED_Pause | 12742 ELINK_SUPPORTED_Asym_Pause), 12743 /*.media_type = */ELINK_ETH_PHY_SFPP_10G_FIBER, 12744 /*.sfp_media = */ELINK_ETH_SFP_UNKNOWN, 12745 /*.ver_addr = */0, 12746 /*.req_flow_ctrl = */0, 12747 /*.req_line_speed = */0, 12748 /*.speed_cap_mask = */0, 12749 /*.req_duplex = */0, 12750 /*.rsrv = */0, 12751 /*.config_init = */elink_8706_config_init, 12752 /*.read_status = */elink_8706_read_status, 12753 /*.link_reset = */elink_common_ext_link_reset, 12754 /*.config_loopback = */(config_loopback_t)NULL, 12755 /*.format_fw_ver= */elink_format_ver, 12756 /*.hw_reset = */(hw_reset_t)NULL, 12757 /*.set_link_led = */(set_link_led_t)NULL, 12758 /*.phy_specific_func = */(phy_specific_func_t)NULL 12759 }; 12760 12761 static const struct elink_phy phy_8726 = { 12762 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, 12763 /*.addr = */0xff, 12764 /*.def_md_devad = */0, 12765 /*.flags = */(ELINK_FLAGS_INIT_XGXS_FIRST | 12766 ELINK_FLAGS_TX_ERROR_CHECK), 12767 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12768 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12769 /*.mdio_ctrl = */0, 12770 /*.supported = */(ELINK_SUPPORTED_10000baseT_Full | 12771 ELINK_SUPPORTED_1000baseT_Full | 12772 ELINK_SUPPORTED_Autoneg | 12773 ELINK_SUPPORTED_FIBRE | 12774 ELINK_SUPPORTED_Pause | 12775 ELINK_SUPPORTED_Asym_Pause), 12776 /*.media_type = */ELINK_ETH_PHY_NOT_PRESENT, 12777 /*.sfp_media = */ELINK_ETH_SFP_UNKNOWN, 12778 /*.ver_addr = */0, 12779 /*.req_flow_ctrl = */0, 12780 /*.req_line_speed = */0, 12781 /*.speed_cap_mask = */0, 12782 /*.req_duplex = */0, 12783 /*.rsrv = */0, 12784 /*.config_init = */elink_8726_config_init, 12785 /*.read_status = */elink_8726_read_status, 12786 /*.link_reset = */elink_8726_link_reset, 12787 /*.config_loopback = */elink_8726_config_loopback, 12788 /*.format_fw_ver= */elink_format_ver, 12789 /*.hw_reset = */(hw_reset_t)NULL, 12790 /*.set_link_led = */(set_link_led_t)NULL, 12791 /*.phy_specific_func = */(phy_specific_func_t)NULL 12792 }; 12793 #endif /* #ifndef EXCLUDE_BCM87x6 */ 12794 12795 #ifndef EXCLUDE_BCM8727_BCM8073 12796 static const struct elink_phy phy_8727 = { 12797 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, 12798 /*.addr = */0xff, 12799 /*.def_md_devad = */0, 12800 /*.flags = */(ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12801 ELINK_FLAGS_TX_ERROR_CHECK), 12802 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12803 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12804 /*.mdio_ctrl = */0, 12805 /*.supported = */(ELINK_SUPPORTED_10000baseT_Full | 12806 ELINK_SUPPORTED_1000baseT_Full | 12807 ELINK_SUPPORTED_FIBRE | 12808 ELINK_SUPPORTED_Pause | 12809 ELINK_SUPPORTED_Asym_Pause), 12810 /*.media_type = */ELINK_ETH_PHY_NOT_PRESENT, 12811 /*.sfp_media = */ELINK_ETH_SFP_UNKNOWN, 12812 /*.ver_addr = */0, 12813 /*.req_flow_ctrl = */0, 12814 /*.req_line_speed = */0, 12815 /*.speed_cap_mask = */0, 12816 /*.req_duplex = */0, 12817 /*.rsrv = */0, 12818 #ifndef EXCLUDE_NON_COMMON_INIT 12819 /*.config_init = */elink_8727_config_init, 12820 /*.read_status = */elink_8727_read_status, 12821 /*.link_reset = */elink_8727_link_reset, 12822 /*.config_loopback = */(config_loopback_t)NULL, 12823 /*.format_fw_ver= */elink_format_ver, 12824 /*.hw_reset = */elink_8727_hw_reset, 12825 /*.set_link_led = */elink_8727_set_link_led, 12826 /*.phy_specific_func = */elink_8727_specific_func 12827 #endif 12828 }; 12829 #endif 12830 #ifndef EXCLUDE_BCM8481 12831 static const struct elink_phy phy_8481 = { 12832 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, 12833 /*.addr = */0xff, 12834 /*.def_md_devad = */0, 12835 /*.flags = */ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12836 ELINK_FLAGS_REARM_LATCH_SIGNAL, 12837 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12838 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12839 /*.mdio_ctrl = */0, 12840 /*.supported = */(ELINK_SUPPORTED_10baseT_Half | 12841 ELINK_SUPPORTED_10baseT_Full | 12842 ELINK_SUPPORTED_100baseT_Half | 12843 ELINK_SUPPORTED_100baseT_Full | 12844 ELINK_SUPPORTED_1000baseT_Full | 12845 ELINK_SUPPORTED_10000baseT_Full | 12846 ELINK_SUPPORTED_TP | 12847 ELINK_SUPPORTED_Autoneg | 12848 ELINK_SUPPORTED_Pause | 12849 ELINK_SUPPORTED_Asym_Pause), 12850 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12851 /*.sfp_media = */ELINK_ETH_SFP_UNKNOWN, 12852 /*.ver_addr = */0, 12853 /*.req_flow_ctrl = */0, 12854 /*.req_line_speed = */0, 12855 /*.speed_cap_mask = */0, 12856 /*.req_duplex = */0, 12857 /*.rsrv = */0, 12858 #ifndef EXCLUDE_NON_COMMON_INIT 12859 /*.config_init = */elink_8481_config_init, 12860 /*.read_status = */elink_848xx_read_status, 12861 /*.link_reset = */elink_8481_link_reset, 12862 /*.config_loopback = */(config_loopback_t)NULL, 12863 /*.format_fw_ver= */elink_848xx_format_ver, 12864 /*.hw_reset = */elink_8481_hw_reset, 12865 /*.set_link_led = */elink_848xx_set_link_led, 12866 /*.phy_specific_func = */(phy_specific_func_t)NULL 12867 #endif 12868 }; 12869 12870 static const struct elink_phy phy_84823 = { 12871 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, 12872 /*.addr = */0xff, 12873 /*.def_md_devad = */0, 12874 /*.flags = */(ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12875 ELINK_FLAGS_REARM_LATCH_SIGNAL | 12876 ELINK_FLAGS_TX_ERROR_CHECK), 12877 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12878 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12879 /*.mdio_ctrl = */0, 12880 /*.supported = */(ELINK_SUPPORTED_10baseT_Half | 12881 ELINK_SUPPORTED_10baseT_Full | 12882 ELINK_SUPPORTED_100baseT_Half | 12883 ELINK_SUPPORTED_100baseT_Full | 12884 ELINK_SUPPORTED_1000baseT_Full | 12885 ELINK_SUPPORTED_10000baseT_Full | 12886 ELINK_SUPPORTED_TP | 12887 ELINK_SUPPORTED_Autoneg | 12888 ELINK_SUPPORTED_Pause | 12889 ELINK_SUPPORTED_Asym_Pause), 12890 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12891 /*.sfp_media = */ELINK_ETH_SFP_UNKNOWN, 12892 /*.ver_addr = */0, 12893 /*.req_flow_ctrl = */0, 12894 /*.req_line_speed = */0, 12895 /*.speed_cap_mask = */0, 12896 /*.req_duplex = */0, 12897 /*.rsrv = */0, 12898 #ifndef EXCLUDE_NON_COMMON_INIT 12899 /*.config_init = */elink_848x3_config_init, 12900 /*.read_status = */elink_848xx_read_status, 12901 /*.link_reset = */elink_848x3_link_reset, 12902 /*.config_loopback = */(config_loopback_t)NULL, 12903 /*.format_fw_ver= */elink_848xx_format_ver, 12904 /*.hw_reset = */(hw_reset_t)NULL, 12905 /*.set_link_led = */elink_848xx_set_link_led, 12906 /*.phy_specific_func = */elink_848xx_specific_func 12907 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 12908 }; 12909 #endif /* EXCLUDE_BCM8481 */ 12910 12911 #ifndef EXCLUDE_BCM84833 12912 static const struct elink_phy phy_84833 = { 12913 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, 12914 /*.addr = */0xff, 12915 /*.def_md_devad = */0, 12916 /*.flags = */(ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12917 ELINK_FLAGS_REARM_LATCH_SIGNAL | 12918 ELINK_FLAGS_TX_ERROR_CHECK | 12919 ELINK_FLAGS_TEMPERATURE), 12920 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12921 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12922 /*.mdio_ctrl = */0, 12923 /*.supported = */(ELINK_SUPPORTED_100baseT_Half | 12924 ELINK_SUPPORTED_100baseT_Full | 12925 ELINK_SUPPORTED_1000baseT_Full | 12926 ELINK_SUPPORTED_10000baseT_Full | 12927 ELINK_SUPPORTED_TP | 12928 ELINK_SUPPORTED_Autoneg | 12929 ELINK_SUPPORTED_Pause | 12930 ELINK_SUPPORTED_Asym_Pause), 12931 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12932 /*.sfp_media = */ELINK_ETH_SFP_UNKNOWN, 12933 /*.ver_addr = */0, 12934 /*.req_flow_ctrl = */0, 12935 /*.req_line_speed = */0, 12936 /*.speed_cap_mask = */0, 12937 /*.req_duplex = */0, 12938 /*.rsrv = */0, 12939 #ifndef EXCLUDE_NON_COMMON_INIT 12940 /*.config_init = */elink_848x3_config_init, 12941 /*.read_status = */elink_848xx_read_status, 12942 /*.link_reset = */elink_848x3_link_reset, 12943 /*.config_loopback = */(config_loopback_t)NULL, 12944 /*.format_fw_ver= */elink_848xx_format_ver, 12945 /*.hw_reset = */elink_84833_hw_reset_phy, 12946 /*.set_link_led = */elink_848xx_set_link_led, 12947 /*.phy_specific_func = */elink_848xx_specific_func 12948 #endif 12949 }; 12950 12951 static const struct elink_phy phy_84834 = { 12952 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834, 12953 /*.addr = */0xff, 12954 /*.def_md_devad = */0, 12955 /*.flags = */ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12956 ELINK_FLAGS_REARM_LATCH_SIGNAL, 12957 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12958 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12959 /*.mdio_ctrl = */0, 12960 /*.supported = */(ELINK_SUPPORTED_100baseT_Half | 12961 ELINK_SUPPORTED_100baseT_Full | 12962 ELINK_SUPPORTED_1000baseT_Full | 12963 ELINK_SUPPORTED_10000baseT_Full | 12964 ELINK_SUPPORTED_TP | 12965 ELINK_SUPPORTED_Autoneg | 12966 ELINK_SUPPORTED_Pause | 12967 ELINK_SUPPORTED_Asym_Pause), 12968 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12969 /*.sfp_media = */ELINK_ETH_SFP_UNKNOWN, 12970 /*.ver_addr = */0, 12971 /*.req_flow_ctrl = */0, 12972 /*.req_line_speed = */0, 12973 /*.speed_cap_mask = */0, 12974 /*.req_duplex = */0, 12975 /*.rsrv = */0, 12976 #ifndef EXCLUDE_NON_COMMON_INIT 12977 /*.config_init = */elink_848x3_config_init, 12978 /*.read_status = */elink_848xx_read_status, 12979 /*.link_reset = */elink_848x3_link_reset, 12980 /*.config_loopback = */(config_loopback_t)NULL, 12981 /*.format_fw_ver= */elink_848xx_format_ver, 12982 /*.hw_reset = */elink_84833_hw_reset_phy, 12983 /*.set_link_led = */elink_848xx_set_link_led, 12984 /*.phy_specific_func = */elink_848xx_specific_func 12985 #endif 12986 }; 12987 #endif // #ifndef EXCLUDE_BCM84833 12988 12989 #ifndef EXCLUDE_BCM54618SE 12990 static const struct elink_phy phy_54618se = { 12991 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, 12992 /*.addr = */0xff, 12993 /*.def_md_devad = */0, 12994 /*.flags = */ELINK_FLAGS_INIT_XGXS_FIRST, 12995 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12996 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12997 /*.mdio_ctrl = */0, 12998 /*.supported = */(ELINK_SUPPORTED_10baseT_Half | 12999 ELINK_SUPPORTED_10baseT_Full | 13000 ELINK_SUPPORTED_100baseT_Half | 13001 ELINK_SUPPORTED_100baseT_Full | 13002 ELINK_SUPPORTED_1000baseT_Full | 13003 ELINK_SUPPORTED_TP | 13004 ELINK_SUPPORTED_Autoneg | 13005 ELINK_SUPPORTED_Pause | 13006 ELINK_SUPPORTED_Asym_Pause), 13007 /*.media_type = */ELINK_ETH_PHY_BASE_T, 13008 /*.sfp_media = */ELINK_ETH_SFP_UNKNOWN, 13009 /*.ver_addr = */0, 13010 /*.req_flow_ctrl = */0, 13011 /*.req_line_speed = */0, 13012 /*.speed_cap_mask = */0, 13013 /* req_duplex = */0, 13014 /* rsrv = */0, 13015 #ifndef EXCLUDE_NON_COMMON_INIT 13016 /*.config_init = */elink_54618se_config_init, 13017 /*.read_status = */elink_54618se_read_status, 13018 /*.link_reset = */elink_54618se_link_reset, 13019 /*.config_loopback = */elink_54618se_config_loopback, 13020 /*.format_fw_ver= */(format_fw_ver_t)NULL, 13021 /*.hw_reset = */(hw_reset_t)NULL, 13022 /*.set_link_led = */elink_5461x_set_link_led, 13023 /*.phy_specific_func = */elink_54618se_specific_func 13024 #endif 13025 }; 13026 #endif 13027 #endif /* ELINK_EMUL_ONLY */ 13028 /*****************************************************************/ 13029 /* */ 13030 /* Populate the phy according. Main function: elink_populate_phy */ 13031 /* */ 13032 /*****************************************************************/ 13033 13034 #ifndef EXCLUDE_COMMON_INIT 13035 static void elink_populate_preemphasis(struct elink_dev *cb, u32 shmem_base, 13036 struct elink_phy *phy, u8 port, 13037 u8 phy_index) 13038 { 13039 /* Get the 4 lanes xgxs config rx and tx */ 13040 u32 rx = 0, tx = 0, i; 13041 for (i = 0; i < 2; i++) { 13042 /* INT_PHY and ELINK_EXT_PHY1 share the same value location in 13043 * the shmem. When num_phys is greater than 1, than this value 13044 * applies only to ELINK_EXT_PHY1 13045 */ 13046 if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) { 13047 rx = REG_RD(cb, shmem_base + 13048 OFFSETOF(struct shmem_region, 13049 dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); 13050 13051 tx = REG_RD(cb, shmem_base + 13052 OFFSETOF(struct shmem_region, 13053 dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); 13054 } else { 13055 rx = REG_RD(cb, shmem_base + 13056 OFFSETOF(struct shmem_region, 13057 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 13058 13059 tx = REG_RD(cb, shmem_base + 13060 OFFSETOF(struct shmem_region, 13061 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 13062 } 13063 13064 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); 13065 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); 13066 13067 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); 13068 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); 13069 } 13070 } 13071 13072 #ifndef ELINK_EMUL_ONLY 13073 static u32 elink_get_ext_phy_config(struct elink_dev *cb, u32 shmem_base, 13074 u8 phy_index, u8 port) 13075 { 13076 u32 ext_phy_config = 0; 13077 switch (phy_index) { 13078 case ELINK_EXT_PHY1: 13079 ext_phy_config = REG_RD(cb, shmem_base + 13080 OFFSETOF(struct shmem_region, 13081 dev_info.port_hw_config[port].external_phy_config)); 13082 break; 13083 case ELINK_EXT_PHY2: 13084 ext_phy_config = REG_RD(cb, shmem_base + 13085 OFFSETOF(struct shmem_region, 13086 dev_info.port_hw_config[port].external_phy_config2)); 13087 break; 13088 default: 13089 ELINK_DEBUG_P1(cb, "Invalid phy_index %d\n", phy_index); 13090 return ELINK_STATUS_ERROR; 13091 } 13092 13093 return ext_phy_config; 13094 } 13095 #endif /* ELINK_EMUL_ONLY */ 13096 static elink_status_t elink_populate_int_phy(struct elink_dev *cb, u32 shmem_base, u8 port, 13097 struct elink_phy *phy) 13098 { 13099 u32 phy_addr; 13100 u32 chip_id; 13101 u32 switch_cfg = (REG_RD(cb, shmem_base + 13102 OFFSETOF(struct shmem_region, 13103 dev_info.port_feature_config[port].link_config)) & 13104 PORT_FEATURE_CONNECTED_SWITCH_MASK); 13105 chip_id = (REG_RD(cb, MISC_REG_CHIP_NUM) << 16) | 13106 ((REG_RD(cb, MISC_REG_CHIP_REV) & 0xf) << 12); 13107 13108 ELINK_DEBUG_P1(cb, ":chip_id = 0x%x\n", chip_id); 13109 #ifndef EXCLUDE_WARPCORE 13110 if (ELINK_USES_WARPCORE(chip_id)) { 13111 u32 serdes_net_if; 13112 phy_addr = REG_RD(cb, 13113 MISC_REG_WC0_CTRL_PHY_ADDR); 13114 *phy = phy_warpcore; 13115 if (REG_RD(cb, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) 13116 phy->flags |= ELINK_FLAGS_4_PORT_MODE; 13117 else 13118 phy->flags &= ~ELINK_FLAGS_4_PORT_MODE; 13119 /* Check Dual mode */ 13120 serdes_net_if = (REG_RD(cb, shmem_base + 13121 OFFSETOF(struct shmem_region, dev_info. 13122 port_hw_config[port].default_cfg)) & 13123 PORT_HW_CFG_NET_SERDES_IF_MASK); 13124 /* Set the appropriate supported and flags indications per 13125 * interface type of the chip 13126 */ 13127 switch (serdes_net_if) { 13128 case PORT_HW_CFG_NET_SERDES_IF_SGMII: 13129 phy->supported &= (ELINK_SUPPORTED_10baseT_Half | 13130 ELINK_SUPPORTED_10baseT_Full | 13131 ELINK_SUPPORTED_100baseT_Half | 13132 ELINK_SUPPORTED_100baseT_Full | 13133 ELINK_SUPPORTED_1000baseT_Full | 13134 ELINK_SUPPORTED_FIBRE | 13135 ELINK_SUPPORTED_Autoneg | 13136 ELINK_SUPPORTED_Pause | 13137 ELINK_SUPPORTED_Asym_Pause); 13138 phy->media_type = ELINK_ETH_PHY_BASE_T; 13139 break; 13140 case PORT_HW_CFG_NET_SERDES_IF_XFI: 13141 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | 13142 ELINK_SUPPORTED_10000baseT_Full | 13143 ELINK_SUPPORTED_FIBRE | 13144 ELINK_SUPPORTED_Pause | 13145 ELINK_SUPPORTED_Asym_Pause); 13146 phy->media_type = ELINK_ETH_PHY_XFP_FIBER; 13147 break; 13148 case PORT_HW_CFG_NET_SERDES_IF_SFI: 13149 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | 13150 ELINK_SUPPORTED_10000baseT_Full | 13151 ELINK_SUPPORTED_FIBRE | 13152 ELINK_SUPPORTED_Pause | 13153 ELINK_SUPPORTED_Asym_Pause); 13154 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER; 13155 break; 13156 case PORT_HW_CFG_NET_SERDES_IF_KR: 13157 phy->media_type = ELINK_ETH_PHY_KR; 13158 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | 13159 ELINK_SUPPORTED_10000baseT_Full | 13160 ELINK_SUPPORTED_FIBRE | 13161 ELINK_SUPPORTED_Autoneg | 13162 ELINK_SUPPORTED_Pause | 13163 ELINK_SUPPORTED_Asym_Pause); 13164 break; 13165 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 13166 phy->media_type = ELINK_ETH_PHY_KR; 13167 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE; 13168 phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full | 13169 ELINK_SUPPORTED_FIBRE | 13170 ELINK_SUPPORTED_Pause | 13171 ELINK_SUPPORTED_Asym_Pause); 13172 break; 13173 case PORT_HW_CFG_NET_SERDES_IF_KR2: 13174 phy->media_type = ELINK_ETH_PHY_KR; 13175 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE; 13176 phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full | 13177 ELINK_SUPPORTED_10000baseT_Full | 13178 ELINK_SUPPORTED_1000baseT_Full | 13179 ELINK_SUPPORTED_Autoneg | 13180 ELINK_SUPPORTED_FIBRE | 13181 ELINK_SUPPORTED_Pause | 13182 ELINK_SUPPORTED_Asym_Pause); 13183 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK; 13184 break; 13185 default: 13186 ELINK_DEBUG_P1(cb, "Unknown WC interface type 0x%x\n", 13187 serdes_net_if); 13188 break; 13189 } 13190 13191 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC 13192 * was not set as expected. For B0, ECO will be enabled so there 13193 * won't be an issue there 13194 */ 13195 if (CHIP_REV(chip_id) == CHIP_REV_Ax) 13196 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA; 13197 else 13198 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0; 13199 } else 13200 #endif 13201 { 13202 switch (switch_cfg) { 13203 #ifndef EXCLUDE_SERDES 13204 case ELINK_SWITCH_CFG_1G: 13205 phy_addr = REG_RD(cb, 13206 NIG_REG_SERDES0_CTRL_PHY_ADDR + 13207 port * 0x10); 13208 *phy = phy_serdes; 13209 break; 13210 #endif /* #ifndef EXCLUDE_SERDES */ 13211 #ifndef EXCLUDE_XGXS 13212 case ELINK_SWITCH_CFG_10G: 13213 phy_addr = REG_RD(cb, 13214 NIG_REG_XGXS0_CTRL_PHY_ADDR + 13215 port * 0x18); 13216 *phy = phy_xgxs; 13217 break; 13218 #endif /* EXCLUDE_XGXS */ 13219 default: 13220 ELINK_DEBUG_P0(cb, "Invalid switch_cfg\n"); 13221 return ELINK_STATUS_ERROR; 13222 } 13223 } 13224 phy->addr = (u8)phy_addr; 13225 phy->mdio_ctrl = elink_get_emac_base(cb, 13226 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, 13227 port); 13228 if (CHIP_IS_E2(chip_id)) 13229 phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR; 13230 else 13231 phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR; 13232 13233 ELINK_DEBUG_P3(cb, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", 13234 port, phy->addr, phy->mdio_ctrl); 13235 13236 elink_populate_preemphasis(cb, shmem_base, phy, port, ELINK_INT_PHY); 13237 return ELINK_STATUS_OK; 13238 } 13239 13240 #ifndef ELINK_EMUL_ONLY 13241 static elink_status_t elink_populate_ext_phy(struct elink_dev *cb, 13242 u8 phy_index, 13243 u32 shmem_base, 13244 u32 shmem2_base, 13245 u8 port, 13246 struct elink_phy *phy) 13247 { 13248 u32 ext_phy_config, phy_type, config2; 13249 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; 13250 ext_phy_config = elink_get_ext_phy_config(cb, shmem_base, 13251 phy_index, port); 13252 phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config); 13253 /* Select the phy type */ 13254 switch (phy_type) { 13255 #ifndef EXCLUDE_BCM8727_BCM8073 13256 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 13257 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; 13258 *phy = phy_8073; 13259 break; 13260 #endif 13261 #ifndef EXCLUDE_BCM8705 13262 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 13263 *phy = phy_8705; 13264 break; 13265 #endif 13266 #ifndef EXCLUDE_BCM87x6 13267 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 13268 *phy = phy_8706; 13269 break; 13270 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 13271 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 13272 *phy = phy_8726; 13273 break; 13274 #endif /* EXCLUDE_BCM87x6 */ 13275 #ifndef EXCLUDE_BCM8727_BCM8073 13276 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 13277 /* BCM8727_NOC => BCM8727 no over current */ 13278 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 13279 *phy = phy_8727; 13280 phy->flags |= ELINK_FLAGS_NOC; 13281 break; 13282 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 13283 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 13284 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 13285 *phy = phy_8727; 13286 break; 13287 #endif 13288 #ifndef EXCLUDE_BCM8481 13289 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 13290 *phy = phy_8481; 13291 break; 13292 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 13293 *phy = phy_84823; 13294 break; 13295 #endif 13296 #ifndef EXCLUDE_BCM84833 13297 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 13298 *phy = phy_84833; 13299 break; 13300 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 13301 *phy = phy_84834; 13302 break; 13303 #endif 13304 #ifndef EXCLUDE_BCM54618SE 13305 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616: 13306 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: 13307 *phy = phy_54618se; 13308 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 13309 phy->flags |= ELINK_FLAGS_EEE; 13310 break; 13311 #endif 13312 #ifndef EXCLUDE_SFX7101 13313 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 13314 *phy = phy_7101; 13315 break; 13316 #endif 13317 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 13318 *phy = phy_null; 13319 return ELINK_STATUS_ERROR; 13320 default: 13321 *phy = phy_null; 13322 /* In case external PHY wasn't found */ 13323 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 13324 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 13325 return ELINK_STATUS_ERROR; 13326 return ELINK_STATUS_OK; 13327 } 13328 13329 phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config); 13330 elink_populate_preemphasis(cb, shmem_base, phy, port, phy_index); 13331 13332 /* The shmem address of the phy version is located on different 13333 * structures. In case this structure is too old, do not set 13334 * the address 13335 */ 13336 config2 = REG_RD(cb, shmem_base + OFFSETOF(struct shmem_region, 13337 dev_info.shared_hw_config.config2)); 13338 if (phy_index == ELINK_EXT_PHY1) { 13339 phy->ver_addr = shmem_base + OFFSETOF(struct shmem_region, 13340 port_mb[port].ext_phy_fw_version); 13341 13342 /* Check specific mdc mdio settings */ 13343 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) 13344 mdc_mdio_access = config2 & 13345 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; 13346 } else { 13347 u32 size = REG_RD(cb, shmem2_base); 13348 13349 if (size > 13350 OFFSETOF(struct shmem2_region, ext_phy_fw_version2)) { 13351 phy->ver_addr = shmem2_base + 13352 OFFSETOF(struct shmem2_region, 13353 ext_phy_fw_version2[port]); 13354 } 13355 /* Check specific mdc mdio settings */ 13356 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) 13357 mdc_mdio_access = (config2 & 13358 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> 13359 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - 13360 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); 13361 } 13362 phy->mdio_ctrl = elink_get_emac_base(cb, mdc_mdio_access, port); 13363 13364 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 13365 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) && 13366 (phy->ver_addr)) { 13367 /* Remove 100Mb link supported for BCM84833/4 when phy fw 13368 * version lower than or equal to 1.39 13369 */ 13370 u32 raw_ver = REG_RD(cb, phy->ver_addr); 13371 if (((raw_ver & 0x7F) <= 39) && 13372 (((raw_ver & 0xF80) >> 7) <= 1)) 13373 phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half | 13374 ELINK_SUPPORTED_100baseT_Full); 13375 } 13376 13377 ELINK_DEBUG_P3(cb, "phy_type 0x%x port %d found in index %d\n", 13378 phy_type, port, phy_index); 13379 ELINK_DEBUG_P2(cb, " addr=0x%x, mdio_ctl=0x%x\n", 13380 phy->addr, phy->mdio_ctrl); 13381 return ELINK_STATUS_OK; 13382 } 13383 #endif /* ELINK_EMUL_ONLY */ 13384 13385 static elink_status_t elink_populate_phy(struct elink_dev *cb, u8 phy_index, u32 shmem_base, 13386 u32 shmem2_base, u8 port, struct elink_phy *phy) 13387 { 13388 elink_status_t status = ELINK_STATUS_OK; 13389 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; 13390 if (phy_index == ELINK_INT_PHY) 13391 return elink_populate_int_phy(cb, shmem_base, port, phy); 13392 #ifndef ELINK_EMUL_ONLY 13393 status = elink_populate_ext_phy(cb, phy_index, shmem_base, shmem2_base, 13394 port, phy); 13395 #endif /* ELINK_EMUL_ONLY */ 13396 return status; 13397 } 13398 13399 static void elink_phy_def_cfg(struct elink_params *params, 13400 struct elink_phy *phy, 13401 u8 phy_index) 13402 { 13403 struct elink_dev *cb = params->cb; 13404 u32 link_config; 13405 /* Populate the default phy configuration for MF mode */ 13406 if (phy_index == ELINK_EXT_PHY2) { 13407 link_config = REG_RD(cb, params->shmem_base + 13408 OFFSETOF(struct shmem_region, dev_info. 13409 port_feature_config[params->port].link_config2)); 13410 phy->speed_cap_mask = REG_RD(cb, params->shmem_base + 13411 OFFSETOF(struct shmem_region, 13412 dev_info. 13413 port_hw_config[params->port].speed_capability_mask2)); 13414 } else { 13415 link_config = REG_RD(cb, params->shmem_base + 13416 OFFSETOF(struct shmem_region, dev_info. 13417 port_feature_config[params->port].link_config)); 13418 phy->speed_cap_mask = REG_RD(cb, params->shmem_base + 13419 OFFSETOF(struct shmem_region, 13420 dev_info. 13421 port_hw_config[params->port].speed_capability_mask)); 13422 } 13423 ELINK_DEBUG_P3(cb, 13424 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", 13425 phy_index, link_config, phy->speed_cap_mask); 13426 13427 phy->req_duplex = DUPLEX_FULL; 13428 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 13429 case PORT_FEATURE_LINK_SPEED_10M_HALF: 13430 phy->req_duplex = DUPLEX_HALF; 13431 /* FALLTHROUGH */ 13432 case PORT_FEATURE_LINK_SPEED_10M_FULL: 13433 phy->req_line_speed = ELINK_SPEED_10; 13434 break; 13435 case PORT_FEATURE_LINK_SPEED_100M_HALF: 13436 phy->req_duplex = DUPLEX_HALF; 13437 /* FALLTHROUGH */ 13438 case PORT_FEATURE_LINK_SPEED_100M_FULL: 13439 phy->req_line_speed = ELINK_SPEED_100; 13440 break; 13441 case PORT_FEATURE_LINK_SPEED_1G: 13442 phy->req_line_speed = ELINK_SPEED_1000; 13443 break; 13444 case PORT_FEATURE_LINK_SPEED_2_5G: 13445 phy->req_line_speed = ELINK_SPEED_2500; 13446 break; 13447 case PORT_FEATURE_LINK_SPEED_10G_CX4: 13448 phy->req_line_speed = ELINK_SPEED_10000; 13449 break; 13450 default: 13451 phy->req_line_speed = ELINK_SPEED_AUTO_NEG; 13452 break; 13453 } 13454 13455 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { 13456 case PORT_FEATURE_FLOW_CONTROL_AUTO: 13457 phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO; 13458 break; 13459 case PORT_FEATURE_FLOW_CONTROL_TX: 13460 phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX; 13461 break; 13462 case PORT_FEATURE_FLOW_CONTROL_RX: 13463 phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX; 13464 break; 13465 case PORT_FEATURE_FLOW_CONTROL_BOTH: 13466 phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH; 13467 break; 13468 default: 13469 phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE; 13470 break; 13471 } 13472 } 13473 #endif /* EXCLUDE_COMMON_INIT */ 13474 13475 u32 elink_phy_selection(struct elink_params *params) 13476 { 13477 u32 phy_config_swapped, prio_cfg; 13478 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; 13479 13480 phy_config_swapped = params->multi_phy_config & 13481 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 13482 13483 prio_cfg = params->multi_phy_config & 13484 PORT_HW_CFG_PHY_SELECTION_MASK; 13485 13486 if (phy_config_swapped) { 13487 switch (prio_cfg) { 13488 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 13489 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; 13490 break; 13491 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 13492 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; 13493 break; 13494 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 13495 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 13496 break; 13497 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 13498 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 13499 break; 13500 } 13501 } else 13502 return_cfg = prio_cfg; 13503 13504 return return_cfg; 13505 } 13506 13507 #ifndef EXCLUDE_COMMON_INIT 13508 elink_status_t elink_phy_probe(struct elink_params *params) 13509 { 13510 u8 phy_index, actual_phy_idx; 13511 u32 phy_config_swapped, sync_offset, media_types; 13512 struct elink_dev *cb = params->cb; 13513 struct elink_phy *phy; 13514 params->num_phys = 0; 13515 ELINK_DEBUG_P0(cb, "Begin phy probe\n"); 13516 #ifdef ELINK_INCLUDE_EMUL 13517 if (CHIP_REV_IS_EMUL(params->chip_id)) 13518 return ELINK_STATUS_OK; 13519 #endif 13520 phy_config_swapped = params->multi_phy_config & 13521 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 13522 13523 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; 13524 phy_index++) { 13525 actual_phy_idx = phy_index; 13526 if (phy_config_swapped) { 13527 if (phy_index == ELINK_EXT_PHY1) 13528 actual_phy_idx = ELINK_EXT_PHY2; 13529 else if (phy_index == ELINK_EXT_PHY2) 13530 actual_phy_idx = ELINK_EXT_PHY1; 13531 } 13532 ELINK_DEBUG_P3(cb, "phy_config_swapped %x, phy_index %x," 13533 " actual_phy_idx %x\n", phy_config_swapped, 13534 phy_index, actual_phy_idx); 13535 phy = ¶ms->phy[actual_phy_idx]; 13536 if (elink_populate_phy(cb, phy_index, params->shmem_base, 13537 params->shmem2_base, params->port, 13538 phy) != ELINK_STATUS_OK) { 13539 params->num_phys = 0; 13540 ELINK_DEBUG_P1(cb, "phy probe failed in phy index %d\n", 13541 phy_index); 13542 for (phy_index = ELINK_INT_PHY; 13543 phy_index < ELINK_MAX_PHYS; 13544 phy_index++) 13545 *phy = phy_null; 13546 return ELINK_STATUS_ERROR; 13547 } 13548 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) 13549 break; 13550 13551 if (params->feature_config_flags & 13552 ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) 13553 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK; 13554 13555 if (!(params->feature_config_flags & 13556 ELINK_FEATURE_CONFIG_MT_SUPPORT)) 13557 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G; 13558 13559 sync_offset = params->shmem_base + 13560 OFFSETOF(struct shmem_region, 13561 dev_info.port_hw_config[params->port].media_type); 13562 media_types = REG_RD(cb, sync_offset); 13563 13564 /* Update media type for non-PMF sync only for the first time 13565 * In case the media type changes afterwards, it will be updated 13566 * using the update_status function 13567 */ 13568 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 13569 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 13570 actual_phy_idx))) == 0) { 13571 media_types |= ((phy->media_type & 13572 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 13573 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 13574 actual_phy_idx)); 13575 } 13576 REG_WR(cb, sync_offset, media_types); 13577 13578 elink_phy_def_cfg(params, phy, phy_index); 13579 params->num_phys++; 13580 } 13581 13582 ELINK_DEBUG_P1(cb, "End phy probe. #phys found %x\n", params->num_phys); 13583 return ELINK_STATUS_OK; 13584 } 13585 #endif /* EXCLUDE_COMMON_INIT */ 13586 13587 #ifdef ELINK_AUX_POWER 13588 u8 elink_phy_is_temperature_support(struct elink_params *params) 13589 { 13590 u8 phy_index; 13591 struct elink_phy *phy; 13592 13593 /* This function check that at least one of the phy's supports 13594 * temperature read. 13595 */ 13596 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; 13597 phy_index++) { 13598 phy = ¶ms->phy[phy_index]; 13599 if (phy->flags & ELINK_FLAGS_TEMPERATURE) 13600 return 1; 13601 } 13602 return 0; 13603 } 13604 #endif /* ELINK_AUX_POWER */ 13605 #ifdef ELINK_INCLUDE_EMUL 13606 static elink_status_t elink_init_e3_emul_mac(struct elink_params *params, 13607 struct elink_vars *vars) 13608 { 13609 struct elink_dev *cb = params->cb; 13610 vars->line_speed = params->req_line_speed[0]; 13611 /* In case link speed is auto, set speed the highest as possible */ 13612 if (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) { 13613 if (params->feature_config_flags & 13614 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) 13615 vars->line_speed = ELINK_SPEED_2500; 13616 else if (elink_is_4_port_mode(cb)) 13617 vars->line_speed = ELINK_SPEED_10000; 13618 else 13619 vars->line_speed = ELINK_SPEED_20000; 13620 } 13621 if (vars->line_speed < ELINK_SPEED_10000) { 13622 if ((params->feature_config_flags & 13623 ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC)) { 13624 ELINK_DEBUG_P1(cb, "Invalid line speed %d while UMAC is" 13625 " disabled!\n", params->req_line_speed[0]); 13626 return ELINK_STATUS_ERROR; 13627 } 13628 switch (vars->line_speed) { 13629 case ELINK_SPEED_10: 13630 vars->link_status = ELINK_LINK_10TFD; 13631 break; 13632 case ELINK_SPEED_100: 13633 vars->link_status = ELINK_LINK_100TXFD; 13634 break; 13635 case ELINK_SPEED_1000: 13636 vars->link_status = ELINK_LINK_1000TFD; 13637 break; 13638 case ELINK_SPEED_2500: 13639 vars->link_status = ELINK_LINK_2500TFD; 13640 break; 13641 default: 13642 ELINK_DEBUG_P1(cb, "Invalid line speed %d for UMAC\n", 13643 vars->line_speed); 13644 return ELINK_STATUS_ERROR; 13645 } 13646 vars->link_status |= LINK_STATUS_LINK_UP; 13647 13648 if (params->loopback_mode == ELINK_LOOPBACK_UMAC) 13649 elink_umac_enable(params, vars, 1); 13650 else 13651 elink_umac_enable(params, vars, 0); 13652 } else { 13653 /* Link speed >= 10000 requires XMAC enabled */ 13654 if (params->feature_config_flags & 13655 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) { 13656 ELINK_DEBUG_P1(cb, "Invalid line speed %d while XMAC is" 13657 " disabled!\n", params->req_line_speed[0]); 13658 return ELINK_STATUS_ERROR; 13659 } 13660 /* Check link speed */ 13661 switch (vars->line_speed) { 13662 case ELINK_SPEED_10000: 13663 vars->link_status = ELINK_LINK_10GTFD; 13664 break; 13665 case ELINK_SPEED_20000: 13666 vars->link_status = ELINK_LINK_20GTFD; 13667 break; 13668 default: 13669 ELINK_DEBUG_P1(cb, "Invalid line speed %d for XMAC\n", 13670 vars->line_speed); 13671 return ELINK_STATUS_ERROR; 13672 } 13673 vars->link_status |= LINK_STATUS_LINK_UP; 13674 if (params->loopback_mode == ELINK_LOOPBACK_XMAC) 13675 elink_xmac_enable(params, vars, 1); 13676 else 13677 elink_xmac_enable(params, vars, 0); 13678 } 13679 return ELINK_STATUS_OK; 13680 } 13681 13682 static elink_status_t elink_init_emul(struct elink_params *params, 13683 struct elink_vars *vars) 13684 { 13685 struct elink_dev *cb = params->cb; 13686 if (CHIP_IS_E3(params->chip_id)) { 13687 if (elink_init_e3_emul_mac(params, vars) != 13688 ELINK_STATUS_OK) 13689 return ELINK_STATUS_ERROR; 13690 } else { 13691 if (params->feature_config_flags & 13692 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC) { 13693 vars->line_speed = ELINK_SPEED_1000; 13694 vars->link_status = (LINK_STATUS_LINK_UP | 13695 ELINK_LINK_1000XFD); 13696 if (params->loopback_mode == 13697 ELINK_LOOPBACK_EMAC) 13698 elink_emac_enable(params, vars, 1); 13699 else 13700 elink_emac_enable(params, vars, 0); 13701 } else { 13702 vars->line_speed = ELINK_SPEED_10000; 13703 vars->link_status = (LINK_STATUS_LINK_UP | 13704 ELINK_LINK_10GTFD); 13705 if (params->loopback_mode == 13706 ELINK_LOOPBACK_BMAC) 13707 elink_bmac_enable(params, vars, 1, 1); 13708 else 13709 elink_bmac_enable(params, vars, 0, 1); 13710 } 13711 } 13712 vars->link_up = 1; 13713 vars->duplex = DUPLEX_FULL; 13714 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13715 13716 #ifndef ELINK_AUX_POWER 13717 if (CHIP_IS_E1X(params->chip_id)) 13718 elink_pbf_update(params, vars->flow_ctrl, 13719 vars->line_speed); 13720 #endif /* ELINK_AUX_POWER */ 13721 /* Disable drain */ 13722 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13723 13724 /* update shared memory */ 13725 elink_update_mng(params, vars->link_status); 13726 return ELINK_STATUS_OK; 13727 } 13728 #endif // ELINK_INCLUDE_EMUL 13729 #ifdef ELINK_INCLUDE_FPGA 13730 static elink_status_t elink_init_fpga(struct elink_params *params, 13731 struct elink_vars *vars) 13732 { 13733 /* Enable on E1.5 FPGA */ 13734 struct elink_dev *cb = params->cb; 13735 vars->duplex = DUPLEX_FULL; 13736 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13737 if (!(CHIP_IS_E1(params->chip_id))) { 13738 vars->flow_ctrl = (ELINK_FLOW_CTRL_TX | 13739 ELINK_FLOW_CTRL_RX); 13740 vars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED | 13741 LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 13742 } 13743 if (CHIP_IS_E3(params->chip_id)) { 13744 vars->line_speed = params->req_line_speed[0]; 13745 switch (vars->line_speed) { 13746 case ELINK_SPEED_AUTO_NEG: 13747 vars->line_speed = ELINK_SPEED_2500; 13748 case ELINK_SPEED_2500: 13749 vars->link_status = ELINK_LINK_2500TFD; 13750 break; 13751 case ELINK_SPEED_1000: 13752 vars->link_status = ELINK_LINK_1000XFD; 13753 break; 13754 case ELINK_SPEED_100: 13755 vars->link_status = ELINK_LINK_100TXFD; 13756 break; 13757 case ELINK_SPEED_10: 13758 vars->link_status = ELINK_LINK_10TFD; 13759 break; 13760 default: 13761 ELINK_DEBUG_P1(cb, "Invalid link speed %d\n", 13762 params->req_line_speed[0]); 13763 return ELINK_STATUS_ERROR; 13764 } 13765 vars->link_status |= LINK_STATUS_LINK_UP; 13766 if (params->loopback_mode == ELINK_LOOPBACK_UMAC) 13767 elink_umac_enable(params, vars, 1); 13768 else 13769 elink_umac_enable(params, vars, 0); 13770 } else { 13771 vars->line_speed = ELINK_SPEED_10000; 13772 vars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD); 13773 if (params->loopback_mode == ELINK_LOOPBACK_EMAC) 13774 elink_emac_enable(params, vars, 1); 13775 else 13776 elink_emac_enable(params, vars, 0); 13777 } 13778 vars->link_up = 1; 13779 13780 #ifndef ELINK_AUX_POWER 13781 if (CHIP_IS_E1X(params->chip_id)) 13782 elink_pbf_update(params, vars->flow_ctrl, 13783 vars->line_speed); 13784 #endif /* ELINK_AUX_POWER */ 13785 /* Disable drain */ 13786 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13787 13788 /* Update shared memory */ 13789 elink_update_mng(params, vars->link_status); 13790 return ELINK_STATUS_OK; 13791 } 13792 #endif // #ifdef ELINK_INCLUDE_FPGA 13793 #ifdef ELINK_INCLUDE_LOOPBACK 13794 static void elink_init_bmac_loopback(struct elink_params *params, 13795 struct elink_vars *vars) 13796 { 13797 struct elink_dev *cb = params->cb; 13798 vars->link_up = 1; 13799 vars->line_speed = ELINK_SPEED_10000; 13800 vars->duplex = DUPLEX_FULL; 13801 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13802 vars->mac_type = ELINK_MAC_TYPE_BMAC; 13803 13804 vars->phy_flags = PHY_XGXS_FLAG; 13805 13806 elink_xgxs_deassert(params); 13807 13808 /* Set bmac loopback */ 13809 elink_bmac_enable(params, vars, 1, 1); 13810 13811 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13812 } 13813 13814 static void elink_init_emac_loopback(struct elink_params *params, 13815 struct elink_vars *vars) 13816 { 13817 struct elink_dev *cb = params->cb; 13818 vars->link_up = 1; 13819 vars->line_speed = ELINK_SPEED_1000; 13820 vars->duplex = DUPLEX_FULL; 13821 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13822 vars->mac_type = ELINK_MAC_TYPE_EMAC; 13823 13824 vars->phy_flags = PHY_XGXS_FLAG; 13825 13826 elink_xgxs_deassert(params); 13827 /* Set bmac loopback */ 13828 elink_emac_enable(params, vars, 1); 13829 elink_emac_program(params, vars); 13830 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13831 } 13832 13833 static void elink_init_xmac_loopback(struct elink_params *params, 13834 struct elink_vars *vars) 13835 { 13836 struct elink_dev *cb = params->cb; 13837 vars->link_up = 1; 13838 if (!params->req_line_speed[0]) 13839 vars->line_speed = ELINK_SPEED_10000; 13840 else 13841 vars->line_speed = params->req_line_speed[0]; 13842 vars->duplex = DUPLEX_FULL; 13843 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13844 vars->mac_type = ELINK_MAC_TYPE_XMAC; 13845 vars->phy_flags = PHY_XGXS_FLAG; 13846 /* Set WC to loopback mode since link is required to provide clock 13847 * to the XMAC in 20G mode 13848 */ 13849 elink_set_aer_mmd(params, ¶ms->phy[0]); 13850 elink_warpcore_reset_lane(cb, ¶ms->phy[0], 0); 13851 params->phy[ELINK_INT_PHY].config_loopback( 13852 ¶ms->phy[ELINK_INT_PHY], 13853 params); 13854 13855 elink_xmac_enable(params, vars, 1); 13856 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13857 } 13858 13859 static void elink_init_umac_loopback(struct elink_params *params, 13860 struct elink_vars *vars) 13861 { 13862 struct elink_dev *cb = params->cb; 13863 vars->link_up = 1; 13864 vars->line_speed = ELINK_SPEED_1000; 13865 vars->duplex = DUPLEX_FULL; 13866 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13867 vars->mac_type = ELINK_MAC_TYPE_UMAC; 13868 vars->phy_flags = PHY_XGXS_FLAG; 13869 elink_umac_enable(params, vars, 1); 13870 13871 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13872 } 13873 13874 static void elink_init_xgxs_loopback(struct elink_params *params, 13875 struct elink_vars *vars) 13876 { 13877 struct elink_dev *cb = params->cb; 13878 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY]; 13879 vars->link_up = 1; 13880 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13881 vars->duplex = DUPLEX_FULL; 13882 if (params->req_line_speed[0] == ELINK_SPEED_1000) 13883 vars->line_speed = ELINK_SPEED_1000; 13884 else if ((params->req_line_speed[0] == ELINK_SPEED_20000) || 13885 (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) 13886 vars->line_speed = ELINK_SPEED_20000; 13887 else 13888 vars->line_speed = ELINK_SPEED_10000; 13889 13890 if (!ELINK_USES_WARPCORE(params->chip_id)) 13891 elink_xgxs_deassert(params); 13892 elink_link_initialize(params, vars); 13893 13894 if (params->req_line_speed[0] == ELINK_SPEED_1000) { 13895 if (ELINK_USES_WARPCORE(params->chip_id)) 13896 elink_umac_enable(params, vars, 0); 13897 else { 13898 elink_emac_program(params, vars); 13899 elink_emac_enable(params, vars, 0); 13900 } 13901 } else { 13902 if (ELINK_USES_WARPCORE(params->chip_id)) 13903 elink_xmac_enable(params, vars, 0); 13904 else 13905 elink_bmac_enable(params, vars, 0, 1); 13906 } 13907 13908 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) { 13909 /* Set 10G XGXS loopback */ 13910 int_phy->config_loopback(int_phy, params); 13911 } else { 13912 /* Set external phy loopback */ 13913 u8 phy_index; 13914 for (phy_index = ELINK_EXT_PHY1; 13915 phy_index < params->num_phys; phy_index++) 13916 if (params->phy[phy_index].config_loopback) 13917 params->phy[phy_index].config_loopback( 13918 ¶ms->phy[phy_index], 13919 params); 13920 } 13921 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13922 13923 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed); 13924 } 13925 #endif // #ifdef ELINK_INCLUDE_LOOPBACK 13926 13927 #ifdef ELINK_ENHANCEMENTS 13928 void elink_set_rx_filter(struct elink_params *params, u8 en) 13929 { 13930 struct elink_dev *cb = params->cb; 13931 u8 val = en * 0x1F; 13932 13933 /* Open / close the gate between the NIG and the BRB */ 13934 if (!CHIP_IS_E1X(params->chip_id)) 13935 val |= en * 0x20; 13936 REG_WR(cb, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); 13937 13938 if (!CHIP_IS_E1(params->chip_id)) { 13939 REG_WR(cb, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, 13940 en*0x3); 13941 } 13942 13943 REG_WR(cb, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : 13944 NIG_REG_LLH0_BRB1_NOT_MCP), en); 13945 } 13946 #endif /* #ifdef ELINK_ENHANCEMENTS */ 13947 #ifndef EXCLUDE_NON_COMMON_INIT 13948 static elink_status_t elink_avoid_link_flap(struct elink_params *params, 13949 struct elink_vars *vars) 13950 { 13951 u32 phy_idx; 13952 u32 dont_clear_stat, lfa_sts; 13953 struct elink_dev *cb = params->cb; 13954 13955 elink_set_mdio_emac_per_phy(cb, params); 13956 /* Sync the link parameters */ 13957 elink_link_status_update(params, vars); 13958 13959 /* 13960 * The module verification was already done by previous link owner, 13961 * so this call is meant only to get warning message 13962 */ 13963 13964 for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) { 13965 struct elink_phy *phy = ¶ms->phy[phy_idx]; 13966 if (phy->phy_specific_func) { 13967 ELINK_DEBUG_P0(cb, "Calling PHY specific func\n"); 13968 phy->phy_specific_func(phy, params, ELINK_PHY_INIT); 13969 } 13970 #ifdef ELINK_ENHANCEMENTS 13971 if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) || 13972 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) || 13973 (phy->media_type == ELINK_ETH_PHY_DA_TWINAX)) { 13974 elink_determine_sfp_media(phy, params); 13975 elink_verify_sfp_module(phy, params); 13976 } 13977 #endif 13978 } 13979 lfa_sts = REG_RD(cb, params->lfa_base + 13980 OFFSETOF(struct shmem_lfa, 13981 lfa_sts)); 13982 13983 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT; 13984 13985 /* Re-enable the NIG/MAC */ 13986 if (CHIP_IS_E3(params->chip_id)) { 13987 #ifndef EXCLUDE_WARPCORE 13988 if (!dont_clear_stat) { 13989 REG_WR(cb, GRCBASE_MISC + 13990 MISC_REGISTERS_RESET_REG_2_CLEAR, 13991 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 13992 params->port)); 13993 REG_WR(cb, GRCBASE_MISC + 13994 MISC_REGISTERS_RESET_REG_2_SET, 13995 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 13996 params->port)); 13997 } 13998 if (vars->line_speed < ELINK_SPEED_10000) 13999 elink_umac_enable(params, vars, 0); 14000 else 14001 elink_xmac_enable(params, vars, 0); 14002 #endif 14003 } else { 14004 #ifndef EXCLUDE_BMAC2 14005 if (vars->line_speed < ELINK_SPEED_10000) 14006 elink_emac_enable(params, vars, 0); 14007 else 14008 elink_bmac_enable(params, vars, 0, !dont_clear_stat); 14009 #endif 14010 } 14011 14012 /* Increment LFA count */ 14013 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) | 14014 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >> 14015 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff) 14016 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET)); 14017 /* Clear link flap reason */ 14018 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 14019 14020 REG_WR(cb, params->lfa_base + 14021 OFFSETOF(struct shmem_lfa, lfa_sts), lfa_sts); 14022 14023 /* Disable NIG DRAIN */ 14024 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 14025 14026 /* Enable interrupts */ 14027 elink_link_int_enable(params); 14028 return ELINK_STATUS_OK; 14029 } 14030 14031 static void elink_cannot_avoid_link_flap(struct elink_params *params, 14032 struct elink_vars *vars, 14033 int lfa_status) 14034 { 14035 u32 lfa_sts, cfg_idx, tmp_val; 14036 struct elink_dev *cb = params->cb; 14037 14038 elink_link_reset(params, vars, 1); 14039 14040 if (!params->lfa_base) 14041 return; 14042 /* Store the new link parameters */ 14043 REG_WR(cb, params->lfa_base + 14044 OFFSETOF(struct shmem_lfa, req_duplex), 14045 params->req_duplex[0] | (params->req_duplex[1] << 16)); 14046 14047 REG_WR(cb, params->lfa_base + 14048 OFFSETOF(struct shmem_lfa, req_flow_ctrl), 14049 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); 14050 14051 REG_WR(cb, params->lfa_base + 14052 OFFSETOF(struct shmem_lfa, req_line_speed), 14053 params->req_line_speed[0] | (params->req_line_speed[1] << 16)); 14054 14055 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) { 14056 REG_WR(cb, params->lfa_base + 14057 OFFSETOF(struct shmem_lfa, 14058 speed_cap_mask[cfg_idx]), 14059 params->speed_cap_mask[cfg_idx]); 14060 } 14061 14062 tmp_val = REG_RD(cb, params->lfa_base + 14063 OFFSETOF(struct shmem_lfa, additional_config)); 14064 tmp_val &= ~REQ_FC_AUTO_ADV_MASK; 14065 tmp_val |= params->req_fc_auto_adv; 14066 14067 REG_WR(cb, params->lfa_base + 14068 OFFSETOF(struct shmem_lfa, additional_config), tmp_val); 14069 14070 lfa_sts = REG_RD(cb, params->lfa_base + 14071 OFFSETOF(struct shmem_lfa, lfa_sts)); 14072 14073 /* Clear the "Don't Clear Statistics" bit, and set reason */ 14074 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT; 14075 14076 /* Set link flap reason */ 14077 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 14078 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) << 14079 LFA_LINK_FLAP_REASON_OFFSET); 14080 14081 /* Increment link flap counter */ 14082 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) | 14083 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >> 14084 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff) 14085 << LINK_FLAP_COUNT_OFFSET)); 14086 REG_WR(cb, params->lfa_base + 14087 OFFSETOF(struct shmem_lfa, lfa_sts), lfa_sts); 14088 /* Proceed with regular link initialization */ 14089 } 14090 14091 elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars) 14092 { 14093 int lfa_status; 14094 struct elink_dev *cb = params->cb; 14095 ELINK_DEBUG_P0(cb, "Phy Initialization started\n"); 14096 ELINK_DEBUG_P2(cb, "(1) req_speed %d, req_flowctrl %d\n", 14097 params->req_line_speed[0], params->req_flow_ctrl[0]); 14098 ELINK_DEBUG_P2(cb, "(2) req_speed %d, req_flowctrl %d\n", 14099 params->req_line_speed[1], params->req_flow_ctrl[1]); 14100 ELINK_DEBUG_P1(cb, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv); 14101 vars->link_status = 0; 14102 vars->phy_link_up = 0; 14103 vars->link_up = 0; 14104 vars->line_speed = 0; 14105 vars->duplex = DUPLEX_FULL; 14106 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 14107 vars->mac_type = ELINK_MAC_TYPE_NONE; 14108 vars->phy_flags = 0; 14109 vars->check_kr2_recovery_cnt = 0; 14110 params->link_flags = ELINK_PHY_INITIALIZED; 14111 #ifdef ELINK_ENHANCEMENTS 14112 /* Driver opens NIG-BRB filters */ 14113 elink_set_rx_filter(params, 1); 14114 #endif 14115 elink_chng_link_count(params, 1); 14116 /* Check if link flap can be avoided */ 14117 lfa_status = elink_check_lfa(params); 14118 14119 if (lfa_status == 0) { 14120 ELINK_DEBUG_P0(cb, "Link Flap Avoidance in progress\n"); 14121 return elink_avoid_link_flap(params, vars); 14122 } 14123 14124 ELINK_DEBUG_P1(cb, "Cannot avoid link flap lfa_sta=0x%x\n", 14125 lfa_status); 14126 elink_cannot_avoid_link_flap(params, vars, lfa_status); 14127 14128 /* Disable attentions */ 14129 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 14130 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 14131 ELINK_NIG_MASK_XGXS0_LINK10G | 14132 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 14133 ELINK_NIG_MASK_MI_INT)); 14134 #ifdef ELINK_INCLUDE_EMUL 14135 if (!(params->feature_config_flags & 14136 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC)) 14137 #endif //ELINK_INCLUDE_EMUL 14138 14139 elink_emac_init(params, vars); 14140 14141 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 14142 vars->link_status |= LINK_STATUS_PFC_ENABLED; 14143 14144 if ((params->num_phys == 0) && 14145 !CHIP_REV_IS_SLOW(params->chip_id)) { 14146 ELINK_DEBUG_P0(cb, "No phy found for initialization !!\n"); 14147 return ELINK_STATUS_ERROR; 14148 } 14149 set_phy_vars(params, vars); 14150 14151 ELINK_DEBUG_P1(cb, "Num of phys on board: %d\n", params->num_phys); 14152 #ifdef ELINK_INCLUDE_FPGA 14153 if (CHIP_REV_IS_FPGA(params->chip_id)) { 14154 return elink_init_fpga(params, vars); 14155 } else 14156 #endif /* ELINK_INCLUDE_FPGA */ 14157 #ifdef ELINK_INCLUDE_EMUL 14158 if (CHIP_REV_IS_EMUL(params->chip_id)) { 14159 return elink_init_emul(params, vars); 14160 } else 14161 #endif /* ELINK_INCLUDE_EMUL */ 14162 #ifdef ELINK_INCLUDE_LOOPBACK 14163 switch (params->loopback_mode) { 14164 case ELINK_LOOPBACK_BMAC: 14165 elink_init_bmac_loopback(params, vars); 14166 break; 14167 case ELINK_LOOPBACK_EMAC: 14168 elink_init_emac_loopback(params, vars); 14169 break; 14170 case ELINK_LOOPBACK_XMAC: 14171 elink_init_xmac_loopback(params, vars); 14172 break; 14173 case ELINK_LOOPBACK_UMAC: 14174 elink_init_umac_loopback(params, vars); 14175 break; 14176 case ELINK_LOOPBACK_XGXS: 14177 case ELINK_LOOPBACK_EXT_PHY: 14178 elink_init_xgxs_loopback(params, vars); 14179 break; 14180 default: 14181 #endif /* ELINK_INCLUDE_LOOPBACK */ 14182 #ifndef EXCLUDE_XGXS 14183 if (!CHIP_IS_E3(params->chip_id)) { 14184 if (params->switch_cfg == ELINK_SWITCH_CFG_10G) 14185 elink_xgxs_deassert(params); 14186 #ifndef EXCLUDE_SERDES 14187 else 14188 elink_serdes_deassert(cb, params->port); 14189 #endif // EXCLUDE_SERDES 14190 } 14191 #endif /* EXCLUDE_XGXS */ 14192 elink_link_initialize(params, vars); 14193 MSLEEP(cb, 30); 14194 elink_link_int_enable(params); 14195 #ifdef ELINK_INCLUDE_LOOPBACK 14196 break; 14197 } 14198 #endif // ELINK_INCLUDE_LOOPBACK 14199 elink_update_mng(params, vars->link_status); 14200 14201 #ifndef EXCLUDE_WARPCORE 14202 elink_update_mng_eee(params, vars->eee_status); 14203 #endif /* #ifndef EXCLUDE_BCM84833 */ 14204 return ELINK_STATUS_OK; 14205 } 14206 14207 #ifndef EXCLUDE_LINK_RESET 14208 elink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars, 14209 u8 reset_ext_phy) 14210 { 14211 struct elink_dev *cb = params->cb; 14212 u8 phy_index, port = params->port, clear_latch_ind = 0; 14213 ELINK_DEBUG_P1(cb, "Resetting the link of port %d\n", port); 14214 /* Disable attentions */ 14215 vars->link_status = 0; 14216 elink_chng_link_count(params, 1); 14217 elink_update_mng(params, vars->link_status); 14218 #ifndef EXCLUDE_WARPCORE 14219 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 14220 SHMEM_EEE_ACTIVE_BIT); 14221 elink_update_mng_eee(params, vars->eee_status); 14222 #endif /* #ifndef EXCLUDE_BCM84833 */ 14223 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 14224 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 14225 ELINK_NIG_MASK_XGXS0_LINK10G | 14226 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 14227 ELINK_NIG_MASK_MI_INT)); 14228 14229 /* Activate nig drain */ 14230 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 14231 14232 /* Disable nig egress interface */ 14233 if (!CHIP_IS_E3(params->chip_id)) { 14234 REG_WR(cb, NIG_REG_BMAC0_OUT_EN + port*4, 0); 14235 REG_WR(cb, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); 14236 } 14237 14238 #ifdef ELINK_INCLUDE_EMUL 14239 /* Stop BigMac rx */ 14240 if (!(params->feature_config_flags & 14241 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC)) 14242 #endif // ELINK_INCLUDE_EMUL 14243 #if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) 14244 if (!CHIP_IS_E3(params->chip_id)) 14245 elink_set_bmac_rx(cb, params->chip_id, port, 0); 14246 #endif // !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) 14247 #ifndef EXCLUDE_WARPCORE 14248 #ifdef ELINK_INCLUDE_EMUL 14249 /* Stop XMAC/UMAC rx */ 14250 if (!(params->feature_config_flags & 14251 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC)) 14252 #endif // ELINK_INCLUDE_EMUL 14253 if (CHIP_IS_E3(params->chip_id) && 14254 !CHIP_REV_IS_FPGA(params->chip_id)) { 14255 elink_set_xmac_rxtx(params, 0); 14256 elink_set_umac_rxtx(params, 0); 14257 } 14258 #endif // EXCLUDE_WARPCORE 14259 /* Disable emac */ 14260 if (!CHIP_IS_E3(params->chip_id)) 14261 REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 0); 14262 14263 MSLEEP(cb, 10); 14264 /* The PHY reset is controlled by GPIO 1 14265 * Hold it as vars low 14266 */ 14267 /* Clear link led */ 14268 elink_set_mdio_emac_per_phy(cb, params); 14269 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0); 14270 14271 if (reset_ext_phy && (!CHIP_REV_IS_SLOW(params->chip_id))) { 14272 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 14273 phy_index++) { 14274 if (params->phy[phy_index].link_reset) { 14275 elink_set_aer_mmd(params, 14276 ¶ms->phy[phy_index]); 14277 params->phy[phy_index].link_reset( 14278 ¶ms->phy[phy_index], 14279 params); 14280 } 14281 if (params->phy[phy_index].flags & 14282 ELINK_FLAGS_REARM_LATCH_SIGNAL) 14283 clear_latch_ind = 1; 14284 } 14285 } 14286 14287 if (clear_latch_ind) { 14288 /* Clear latching indication */ 14289 elink_rearm_latch_signal(cb, port, 0); 14290 elink_bits_dis(cb, NIG_REG_LATCH_BC_0 + port*4, 14291 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT); 14292 } 14293 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) 14294 if (!CHIP_REV_IS_SLOW(params->chip_id)) 14295 #endif 14296 if (params->phy[ELINK_INT_PHY].link_reset) 14297 params->phy[ELINK_INT_PHY].link_reset( 14298 ¶ms->phy[ELINK_INT_PHY], params); 14299 14300 /* Disable nig ingress interface */ 14301 if (!CHIP_IS_E3(params->chip_id)) { 14302 /* Reset BigMac */ 14303 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 14304 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 14305 REG_WR(cb, NIG_REG_BMAC0_IN_EN + port*4, 0); 14306 REG_WR(cb, NIG_REG_EMAC0_IN_EN + port*4, 0); 14307 } else { 14308 #ifndef EXCLUDE_WARPCORE 14309 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 14310 elink_set_xumac_nig(params, 0, 0); 14311 if (REG_RD(cb, MISC_REG_RESET_REG_2) & 14312 MISC_REGISTERS_RESET_REG_2_XMAC) 14313 REG_WR(cb, xmac_base + XMAC_REG_CTRL, 14314 XMAC_CTRL_REG_SOFT_RESET); 14315 #endif // EXCLUDE_WARPCORE 14316 } 14317 vars->link_up = 0; 14318 vars->phy_flags = 0; 14319 return ELINK_STATUS_OK; 14320 } 14321 #endif // EXCLUDE_LINK_RESET 14322 #ifndef ELINK_AUX_POWER 14323 elink_status_t elink_lfa_reset(struct elink_params *params, 14324 struct elink_vars *vars) 14325 { 14326 struct elink_dev *cb = params->cb; 14327 vars->link_up = 0; 14328 vars->phy_flags = 0; 14329 params->link_flags &= ~ELINK_PHY_INITIALIZED; 14330 if (!params->lfa_base) 14331 return elink_link_reset(params, vars, 1); 14332 /* 14333 * Activate NIG drain so that during this time the device won't send 14334 * anything while it is unable to response. 14335 */ 14336 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 14337 14338 /* 14339 * Close gracefully the gate from BMAC to NIG such that no half packets 14340 * are passed. 14341 */ 14342 if (!CHIP_IS_E3(params->chip_id)) 14343 elink_set_bmac_rx(cb, params->chip_id, params->port, 0); 14344 14345 if (CHIP_IS_E3(params->chip_id)) { 14346 elink_set_xmac_rxtx(params, 0); 14347 elink_set_umac_rxtx(params, 0); 14348 } 14349 /* Wait 10ms for the pipe to clean up*/ 14350 MSLEEP(cb, 10); 14351 14352 #ifdef ELINK_ENHANCEMENTS 14353 /* Clean the NIG-BRB using the network filters in a way that will 14354 * not cut a packet in the middle. 14355 */ 14356 elink_set_rx_filter(params, 0); 14357 #endif 14358 14359 /* 14360 * Re-open the gate between the BMAC and the NIG, after verifying the 14361 * gate to the BRB is closed, otherwise packets may arrive to the 14362 * firmware before driver had initialized it. The target is to achieve 14363 * minimum management protocol down time. 14364 */ 14365 if (!CHIP_IS_E3(params->chip_id)) 14366 elink_set_bmac_rx(cb, params->chip_id, params->port, 1); 14367 14368 if (CHIP_IS_E3(params->chip_id)) { 14369 elink_set_xmac_rxtx(params, 1); 14370 elink_set_umac_rxtx(params, 1); 14371 } 14372 /* Disable NIG drain */ 14373 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 14374 return ELINK_STATUS_OK; 14375 } 14376 #endif /* ELINK_AUX_POWER */ 14377 #endif // EXCLUDE_NON_COMMON_INIT 14378 14379 /****************************************************************************/ 14380 /* Common function */ 14381 /****************************************************************************/ 14382 #ifndef EXCLUDE_COMMON_INIT 14383 #ifndef ELINK_EMUL_ONLY 14384 #ifndef EXCLUDE_BCM8727_BCM8073 14385 static elink_status_t elink_8073_common_init_phy(struct elink_dev *cb, 14386 u32 shmem_base_path[], 14387 u32 shmem2_base_path[], u8 phy_index, 14388 u32 chip_id) 14389 { 14390 struct elink_phy phy[PORT_MAX]; 14391 struct elink_phy *phy_blk[PORT_MAX]; 14392 u16 val; 14393 s8 port = 0; 14394 s8 port_of_path = 0; 14395 u32 swap_val, swap_override; 14396 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP); 14397 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE); 14398 port ^= (swap_val && swap_override); 14399 elink_ext_phy_hw_reset(cb, port); 14400 /* PART1 - Reset both phys */ 14401 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 14402 u32 shmem_base, shmem2_base; 14403 /* In E2, same phy is using for port0 of the two paths */ 14404 if (CHIP_IS_E1X(chip_id)) { 14405 shmem_base = shmem_base_path[0]; 14406 shmem2_base = shmem2_base_path[0]; 14407 port_of_path = port; 14408 } else { 14409 shmem_base = shmem_base_path[port]; 14410 shmem2_base = shmem2_base_path[port]; 14411 port_of_path = 0; 14412 } 14413 14414 /* Extract the ext phy address for the port */ 14415 if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base, 14416 port_of_path, &phy[port]) != 14417 ELINK_STATUS_OK) { 14418 ELINK_DEBUG_P0(cb, "populate_phy failed\n"); 14419 return ELINK_STATUS_ERROR; 14420 } 14421 /* Disable attentions */ 14422 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + 14423 port_of_path*4, 14424 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 14425 ELINK_NIG_MASK_XGXS0_LINK10G | 14426 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 14427 ELINK_NIG_MASK_MI_INT)); 14428 14429 /* Need to take the phy out of low power mode in order 14430 * to write to access its registers 14431 */ 14432 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 14433 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 14434 port); 14435 14436 /* Reset the phy */ 14437 elink_cl45_write(cb, &phy[port], 14438 MDIO_PMA_DEVAD, 14439 MDIO_PMA_REG_CTRL, 14440 1<<15); 14441 } 14442 14443 /* Add delay of 150ms after reset */ 14444 MSLEEP(cb, 150); 14445 14446 if (phy[PORT_0].addr & 0x1) { 14447 phy_blk[PORT_0] = &(phy[PORT_1]); 14448 phy_blk[PORT_1] = &(phy[PORT_0]); 14449 } else { 14450 phy_blk[PORT_0] = &(phy[PORT_0]); 14451 phy_blk[PORT_1] = &(phy[PORT_1]); 14452 } 14453 14454 /* PART2 - Download firmware to both phys */ 14455 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 14456 if (CHIP_IS_E1X(chip_id)) 14457 port_of_path = port; 14458 else 14459 port_of_path = 0; 14460 14461 ELINK_DEBUG_P1(cb, "Loading spirom for phy address 0x%x\n", 14462 phy_blk[port]->addr); 14463 if (elink_8073_8727_external_rom_boot(cb, phy_blk[port], 14464 port_of_path)) 14465 return ELINK_STATUS_ERROR; 14466 14467 /* Only set bit 10 = 1 (Tx power down) */ 14468 elink_cl45_read(cb, phy_blk[port], 14469 MDIO_PMA_DEVAD, 14470 MDIO_PMA_REG_TX_POWER_DOWN, &val); 14471 14472 /* Phase1 of TX_POWER_DOWN reset */ 14473 elink_cl45_write(cb, phy_blk[port], 14474 MDIO_PMA_DEVAD, 14475 MDIO_PMA_REG_TX_POWER_DOWN, 14476 (val | 1<<10)); 14477 } 14478 14479 /* Toggle Transmitter: Power down and then up with 600ms delay 14480 * between 14481 */ 14482 MSLEEP(cb, 600); 14483 14484 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ 14485 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 14486 /* Phase2 of POWER_DOWN_RESET */ 14487 /* Release bit 10 (Release Tx power down) */ 14488 elink_cl45_read(cb, phy_blk[port], 14489 MDIO_PMA_DEVAD, 14490 MDIO_PMA_REG_TX_POWER_DOWN, &val); 14491 14492 elink_cl45_write(cb, phy_blk[port], 14493 MDIO_PMA_DEVAD, 14494 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); 14495 MSLEEP(cb, 15); 14496 14497 /* Read modify write the SPI-ROM version select register */ 14498 elink_cl45_read(cb, phy_blk[port], 14499 MDIO_PMA_DEVAD, 14500 MDIO_PMA_REG_EDC_FFE_MAIN, &val); 14501 elink_cl45_write(cb, phy_blk[port], 14502 MDIO_PMA_DEVAD, 14503 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); 14504 14505 /* set GPIO2 back to LOW */ 14506 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 14507 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 14508 } 14509 return ELINK_STATUS_OK; 14510 } 14511 #endif /* EXCLUDE_BCM8727_BCM8073 */ 14512 #ifndef EXCLUDE_BCM87x6 14513 static elink_status_t elink_8726_common_init_phy(struct elink_dev *cb, 14514 u32 shmem_base_path[], 14515 u32 shmem2_base_path[], u8 phy_index, 14516 u32 chip_id) 14517 { 14518 u32 val; 14519 s8 port; 14520 struct elink_phy phy; 14521 /* Use port1 because of the static port-swap */ 14522 /* Enable the module detection interrupt */ 14523 val = REG_RD(cb, MISC_REG_GPIO_EVENT_EN); 14524 val |= ((1<<MISC_REGISTERS_GPIO_3)| 14525 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); 14526 REG_WR(cb, MISC_REG_GPIO_EVENT_EN, val); 14527 14528 elink_ext_phy_hw_reset(cb, 0); 14529 MSLEEP(cb, 5); 14530 for (port = 0; port < PORT_MAX; port++) { 14531 u32 shmem_base, shmem2_base; 14532 14533 /* In E2, same phy is using for port0 of the two paths */ 14534 if (CHIP_IS_E1X(chip_id)) { 14535 shmem_base = shmem_base_path[0]; 14536 shmem2_base = shmem2_base_path[0]; 14537 } else { 14538 shmem_base = shmem_base_path[port]; 14539 shmem2_base = shmem2_base_path[port]; 14540 } 14541 /* Extract the ext phy address for the port */ 14542 if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base, 14543 port, &phy) != 14544 ELINK_STATUS_OK) { 14545 ELINK_DEBUG_P0(cb, "populate phy failed\n"); 14546 return ELINK_STATUS_ERROR; 14547 } 14548 14549 /* Reset phy*/ 14550 elink_cl45_write(cb, &phy, 14551 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); 14552 14553 14554 /* Set fault module detected LED on */ 14555 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_0, 14556 MISC_REGISTERS_GPIO_HIGH, 14557 port); 14558 } 14559 14560 return ELINK_STATUS_OK; 14561 } 14562 #endif /* #ifndef EXCLUDE_BCM87x6 */ 14563 #ifndef EXCLUDE_BCM8727_BCM8073 14564 static void elink_get_ext_phy_reset_gpio(struct elink_dev *cb, u32 shmem_base, 14565 u8 *io_gpio, u8 *io_port) 14566 { 14567 14568 u32 phy_gpio_reset = REG_RD(cb, shmem_base + 14569 OFFSETOF(struct shmem_region, 14570 dev_info.port_hw_config[PORT_0].default_cfg)); 14571 switch (phy_gpio_reset) { 14572 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: 14573 *io_gpio = 0; 14574 *io_port = 0; 14575 break; 14576 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: 14577 *io_gpio = 1; 14578 *io_port = 0; 14579 break; 14580 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: 14581 *io_gpio = 2; 14582 *io_port = 0; 14583 break; 14584 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: 14585 *io_gpio = 3; 14586 *io_port = 0; 14587 break; 14588 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: 14589 *io_gpio = 0; 14590 *io_port = 1; 14591 break; 14592 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: 14593 *io_gpio = 1; 14594 *io_port = 1; 14595 break; 14596 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: 14597 *io_gpio = 2; 14598 *io_port = 1; 14599 break; 14600 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: 14601 *io_gpio = 3; 14602 *io_port = 1; 14603 break; 14604 default: 14605 /* Don't override the io_gpio and io_port */ 14606 break; 14607 } 14608 } 14609 14610 static elink_status_t elink_8727_common_init_phy(struct elink_dev *cb, 14611 u32 shmem_base_path[], 14612 u32 shmem2_base_path[], u8 phy_index, 14613 u32 chip_id) 14614 { 14615 s8 port, reset_gpio; 14616 u32 swap_val, swap_override; 14617 struct elink_phy phy[PORT_MAX]; 14618 struct elink_phy *phy_blk[PORT_MAX]; 14619 s8 port_of_path; 14620 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP); 14621 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE); 14622 14623 reset_gpio = MISC_REGISTERS_GPIO_1; 14624 port = 1; 14625 14626 /* Retrieve the reset gpio/port which control the reset. 14627 * Default is GPIO1, PORT1 14628 */ 14629 elink_get_ext_phy_reset_gpio(cb, shmem_base_path[0], 14630 (u8 *)&reset_gpio, (u8 *)&port); 14631 14632 /* Calculate the port based on port swap */ 14633 port ^= (swap_val && swap_override); 14634 14635 /* Initiate PHY reset*/ 14636 ELINK_SET_GPIO(cb, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, 14637 port); 14638 MSLEEP(cb, 1); 14639 ELINK_SET_GPIO(cb, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, 14640 port); 14641 14642 MSLEEP(cb, 5); 14643 14644 /* PART1 - Reset both phys */ 14645 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 14646 u32 shmem_base, shmem2_base; 14647 14648 /* In E2, same phy is using for port0 of the two paths */ 14649 if (CHIP_IS_E1X(chip_id)) { 14650 shmem_base = shmem_base_path[0]; 14651 shmem2_base = shmem2_base_path[0]; 14652 port_of_path = port; 14653 } else { 14654 shmem_base = shmem_base_path[port]; 14655 shmem2_base = shmem2_base_path[port]; 14656 port_of_path = 0; 14657 } 14658 14659 /* Extract the ext phy address for the port */ 14660 if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base, 14661 port_of_path, &phy[port]) != 14662 ELINK_STATUS_OK) { 14663 ELINK_DEBUG_P0(cb, "populate phy failed\n"); 14664 return ELINK_STATUS_ERROR; 14665 } 14666 /* disable attentions */ 14667 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + 14668 port_of_path*4, 14669 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 14670 ELINK_NIG_MASK_XGXS0_LINK10G | 14671 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 14672 ELINK_NIG_MASK_MI_INT)); 14673 14674 14675 /* Reset the phy */ 14676 elink_cl45_write(cb, &phy[port], 14677 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 14678 } 14679 14680 /* Add delay of 150ms after reset */ 14681 MSLEEP(cb, 150); 14682 if (phy[PORT_0].addr & 0x1) { 14683 phy_blk[PORT_0] = &(phy[PORT_1]); 14684 phy_blk[PORT_1] = &(phy[PORT_0]); 14685 } else { 14686 phy_blk[PORT_0] = &(phy[PORT_0]); 14687 phy_blk[PORT_1] = &(phy[PORT_1]); 14688 } 14689 /* PART2 - Download firmware to both phys */ 14690 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 14691 if (CHIP_IS_E1X(chip_id)) 14692 port_of_path = port; 14693 else 14694 port_of_path = 0; 14695 ELINK_DEBUG_P1(cb, "Loading spirom for phy address 0x%x\n", 14696 phy_blk[port]->addr); 14697 if (elink_8073_8727_external_rom_boot(cb, phy_blk[port], 14698 port_of_path)) 14699 return ELINK_STATUS_ERROR; 14700 /* Disable PHY transmitter output */ 14701 elink_cl45_write(cb, phy_blk[port], 14702 MDIO_PMA_DEVAD, 14703 MDIO_PMA_REG_TX_DISABLE, 1); 14704 14705 } 14706 return ELINK_STATUS_OK; 14707 } 14708 #endif /* EXCLUDE_BCM8727_BCM8073 */ 14709 14710 #ifndef EXCLUDE_BCM84833 14711 static elink_status_t elink_84833_common_init_phy(struct elink_dev *cb, 14712 u32 shmem_base_path[], 14713 u32 shmem2_base_path[], 14714 u8 phy_index, 14715 u32 chip_id) 14716 { 14717 u8 reset_gpios; 14718 reset_gpios = elink_84833_get_reset_gpios(cb, shmem_base_path, chip_id); 14719 #ifndef EDEBUG 14720 ELINK_SET_MULT_GPIO(cb, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 14721 USLEEP(cb, 10); 14722 ELINK_SET_MULT_GPIO(cb, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); 14723 ELINK_DEBUG_P1(cb, "84833 reset pulse on pin values 0x%x\n", 14724 reset_gpios); 14725 #endif 14726 return ELINK_STATUS_OK; 14727 } 14728 #ifndef EXCLUDE_FROM_BNX2X 14729 static elink_status_t elink_84833_pre_init_phy(struct elink_dev *cb, 14730 struct elink_phy *phy, 14731 u8 port) 14732 { 14733 u16 val, cnt; 14734 /* Wait for FW completing its initialization. */ 14735 for (cnt = 0; cnt < 1500; cnt++) { 14736 elink_cl45_read(cb, phy, 14737 MDIO_PMA_DEVAD, 14738 MDIO_PMA_REG_CTRL, &val); 14739 if (!(val & (1<<15))) 14740 break; 14741 MSLEEP(cb, 1); 14742 } 14743 if (cnt >= 1500) { 14744 ELINK_DEBUG_P0(cb, "84833 reset timeout\n"); 14745 return ELINK_STATUS_ERROR; 14746 } 14747 14748 /* Put the port in super isolate mode. */ 14749 elink_cl45_read(cb, phy, 14750 MDIO_CTL_DEVAD, 14751 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val); 14752 val |= MDIO_84833_SUPER_ISOLATE; 14753 elink_cl45_write(cb, phy, 14754 MDIO_CTL_DEVAD, 14755 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val); 14756 14757 /* Save spirom version */ 14758 elink_save_848xx_spirom_version(phy, cb, port); 14759 return ELINK_STATUS_OK; 14760 } 14761 14762 elink_status_t elink_pre_init_phy(struct elink_dev *cb, 14763 u32 shmem_base, 14764 u32 shmem2_base, 14765 u32 chip_id, 14766 u8 port) 14767 { 14768 elink_status_t rc = ELINK_STATUS_OK; 14769 struct elink_phy phy; 14770 if (elink_populate_phy(cb, ELINK_EXT_PHY1, shmem_base, shmem2_base, 14771 port, &phy) != ELINK_STATUS_OK) { 14772 ELINK_DEBUG_P0(cb, "populate_phy failed\n"); 14773 return ELINK_STATUS_ERROR; 14774 } 14775 elink_set_mdio_clk(cb, chip_id, phy.mdio_ctrl); 14776 switch (phy.type) { 14777 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 14778 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 14779 rc = elink_84833_pre_init_phy(cb, &phy, port); 14780 break; 14781 default: 14782 break; 14783 } 14784 return rc; 14785 } 14786 #endif /* EXCLUDE_FROM_BNX2X */ 14787 #endif /* EXCLUDE_BCM84833 */ 14788 static elink_status_t elink_ext_phy_common_init(struct elink_dev *cb, u32 shmem_base_path[], 14789 u32 shmem2_base_path[], u8 phy_index, 14790 u32 ext_phy_type, u32 chip_id) 14791 { 14792 elink_status_t rc = ELINK_STATUS_OK; 14793 14794 switch (ext_phy_type) { 14795 #ifndef EXCLUDE_BCM8727_BCM8073 14796 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 14797 rc = elink_8073_common_init_phy(cb, shmem_base_path, 14798 shmem2_base_path, 14799 phy_index, chip_id); 14800 break; 14801 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 14802 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 14803 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 14804 rc = elink_8727_common_init_phy(cb, shmem_base_path, 14805 shmem2_base_path, 14806 phy_index, chip_id); 14807 break; 14808 14809 #endif 14810 #ifndef EXCLUDE_BCM87x6 14811 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 14812 /* GPIO1 affects both ports, so there's need to pull 14813 * it for single port alone 14814 */ 14815 rc = elink_8726_common_init_phy(cb, shmem_base_path, 14816 shmem2_base_path, 14817 phy_index, chip_id); 14818 break; 14819 #endif /* #ifndef EXCLUDE_BCM87x6 */ 14820 #ifndef EXCLUDE_BCM84833 14821 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 14822 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 14823 /* GPIO3's are linked, and so both need to be toggled 14824 * to obtain required 2us pulse. 14825 */ 14826 rc = elink_84833_common_init_phy(cb, shmem_base_path, 14827 shmem2_base_path, 14828 phy_index, chip_id); 14829 break; 14830 #endif 14831 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 14832 rc = ELINK_STATUS_ERROR; 14833 break; 14834 default: 14835 ELINK_DEBUG_P1(cb, 14836 "ext_phy 0x%x common init not required\n", 14837 ext_phy_type); 14838 break; 14839 } 14840 14841 if (rc != ELINK_STATUS_OK) 14842 elink_cb_event_log(cb, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized," 14843 // " Port %d\n", 14844 14845 return rc; 14846 } 14847 14848 #ifdef INCLUDE_WARPCORE_UC_LOAD 14849 static elink_status_t elink_warpcore_common_init(struct elink_dev *cb, 14850 u32 shmem_base_path[], 14851 u32 shmem2_base_path[], 14852 u8 phy_index, 14853 u32 chip_id, 14854 u8 one_port_enabled) 14855 { 14856 struct elink_phy phy; 14857 u32 wc_lane_config; 14858 u16 val; 14859 elink_status_t rc; 14860 14861 REG_WR(cb, MISC_REG_LCPLL_E40_PWRDWN, 0); 14862 /* Procedure to bring the LCPLL out of reset. */ 14863 MSLEEP(cb, 1); 14864 REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_ANA, 1); 14865 MSLEEP(cb, 1); 14866 REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_DIG, 1); 14867 14868 ELINK_DEBUG_P0(cb, "Resetting Warpcore\n"); 14869 14870 if (elink_reset_warpcore(cb) != ELINK_STATUS_OK) 14871 return ELINK_STATUS_ERROR; 14872 14873 /* Extract the ext phy address for the port */ 14874 if (elink_populate_phy(cb, phy_index, shmem_base_path[0], 14875 shmem2_base_path[0], 14876 0, &phy) != ELINK_STATUS_OK) { 14877 ELINK_DEBUG_P0(cb, "populate phy failed\n"); 14878 return ELINK_STATUS_ERROR; 14879 } 14880 14881 /* Set WC to use CL45 */ 14882 REG_WR(cb, MISC_REG_WC0_CTRL_MD_ST, 0); 14883 /* Set swap lanes and polarity */ 14884 wc_lane_config = REG_RD(cb, shmem_base_path[0] + 14885 OFFSETOF(struct shmem_region, dev_info. 14886 shared_hw_config.wc_lane_config)); 14887 14888 /* Power down warpcore lanes */ 14889 if (one_port_enabled) 14890 elink_warpcore_powerdown_secondport_lanes(cb, &phy); 14891 14892 /* Disable sequencer */ 14893 elink_warpcore_sequencer(cb, &phy, 0); 14894 14895 elink_warpcore_set_lane_swap(cb, &phy, wc_lane_config); 14896 elink_warpcore_set_lane_polarity(cb, &phy, wc_lane_config); 14897 14898 if (phy.flags & ELINK_FLAGS_WC_DUAL_MODE) 14899 elink_warpcore_set_dual_mode(cb, &phy, shmem_base_path[0]); 14900 else 14901 elink_warpcore_set_quad_mode(cb, &phy); 14902 14903 /* Load Warpcore microcode */ 14904 rc = elink_warpcore_load_uc(cb, &phy); 14905 if (rc != ELINK_STATUS_OK) 14906 return rc; 14907 14908 /* RX traffic and TX traffic requires clock sync. 14909 * When transmiting we send data + clock to the Warpcore. 14910 * This clock is provided by lane 0 of the Warpcore. 14911 * So we need to configure this lane to supply us the correct clock 14912 * which will be use for transmit on all lanes 14913 */ 14914 14915 CL22_WR_OVER_CL45(cb, &phy, MDIO_REG_BANK_AER_BLOCK, 14916 MDIO_AER_BLOCK_AER_REG, 0); 14917 elink_cl45_read(cb, &phy, MDIO_WC_DEVAD, 14918 MDIO_WC_REG_XGXS_X2_CONTROL2, &val); 14919 val &= 0xDE1F; 14920 if (phy.flags & ELINK_FLAGS_WC_DUAL_MODE) { 14921 val |= (1<<11); 14922 val |= (9<<5); 14923 /* To force tx_wclk33 to txckp[0] */ 14924 if (phy.supported & ELINK_SUPPORTED_20000baseKR2_Full) 14925 val |= (1<<13); 14926 14927 /* Dual mode - lanes 0,1 use same clocks/resets - from lane 0 14928 * Lanes 2,3 use same clocks/resets - from lane 2 14929 */ 14930 elink_cl45_write(cb, &phy, MDIO_WC_DEVAD, 14931 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); 14932 } else 14933 val |= 0x2800; 14934 14935 elink_cl45_write(cb, &phy, MDIO_WC_DEVAD, 14936 MDIO_WC_REG_XGXS_X2_CONTROL2, val); 14937 14938 /* Enable sequencer */ 14939 elink_warpcore_sequencer(cb, &phy, 1); 14940 14941 return ELINK_STATUS_OK; 14942 } 14943 14944 #endif /* INCLUDE_WARPCORE_UC_LOAD */ 14945 #endif /* ELINK_EMUL_ONLY */ 14946 elink_status_t elink_common_init_phy(struct elink_dev *cb, u32 shmem_base_path[], 14947 u32 shmem2_base_path[], u32 chip_id, 14948 u8 one_port_enabled) 14949 { 14950 elink_status_t rc = ELINK_STATUS_OK; 14951 u32 phy_ver, val; 14952 #ifndef ELINK_EMUL_ONLY 14953 u8 phy_index = 0; 14954 u32 ext_phy_type, ext_phy_config; 14955 #endif 14956 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) 14957 if (CHIP_REV_IS_EMUL(chip_id) || CHIP_REV_IS_FPGA(chip_id)) 14958 return ELINK_STATUS_OK; 14959 #endif 14960 14961 elink_set_mdio_clk(cb, chip_id, GRCBASE_EMAC0); 14962 elink_set_mdio_clk(cb, chip_id, GRCBASE_EMAC1); 14963 ELINK_DEBUG_P0(cb, "Begin common phy init\n"); 14964 if (CHIP_IS_E3(chip_id)) { 14965 /* Enable EPIO */ 14966 val = REG_RD(cb, MISC_REG_GEN_PURP_HWG); 14967 REG_WR(cb, MISC_REG_GEN_PURP_HWG, val | 1); 14968 } 14969 #ifndef ELINK_EMUL_ONLY 14970 /* Check if common init was already done */ 14971 phy_ver = REG_RD(cb, shmem_base_path[0] + 14972 OFFSETOF(struct shmem_region, 14973 port_mb[PORT_0].ext_phy_fw_version)); 14974 if (phy_ver) { 14975 ELINK_DEBUG_P1(cb, "Not doing common init; phy ver is 0x%x\n", 14976 phy_ver); 14977 return ELINK_STATUS_OK; 14978 } 14979 14980 #ifdef INCLUDE_WARPCORE_UC_LOAD 14981 if (ELINK_USES_WARPCORE(chip_id)) { 14982 rc |= elink_warpcore_common_init(cb, shmem_base_path, 14983 shmem2_base_path, phy_index, 14984 chip_id, one_port_enabled); 14985 } 14986 #endif 14987 /* Read the ext_phy_type for arbitrary port(0) */ 14988 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; 14989 phy_index++) { 14990 ext_phy_config = elink_get_ext_phy_config(cb, 14991 shmem_base_path[0], 14992 phy_index, 0); 14993 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config); 14994 rc |= elink_ext_phy_common_init(cb, shmem_base_path, 14995 shmem2_base_path, 14996 phy_index, ext_phy_type, 14997 chip_id); 14998 } 14999 #endif /* ELINK_EMUL_ONLY */ 15000 return rc; 15001 } 15002 #endif // #ifndef EXCLUDE_COMMON_INIT 15003 15004 #ifndef EXCLUDE_NON_COMMON_INIT 15005 #ifndef EXCLUDE_WARPCORE 15006 static void elink_check_over_curr(struct elink_params *params, 15007 struct elink_vars *vars) 15008 { 15009 struct elink_dev *cb = params->cb; 15010 u32 cfg_pin; 15011 u8 port = params->port; 15012 u32 pin_val; 15013 15014 cfg_pin = (REG_RD(cb, params->shmem_base + 15015 OFFSETOF(struct shmem_region, 15016 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & 15017 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> 15018 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; 15019 15020 /* Ignore check if no external input PIN available */ 15021 if (elink_get_cfg_pin(cb, cfg_pin, &pin_val) != ELINK_STATUS_OK) 15022 return; 15023 15024 if (!pin_val) { 15025 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { 15026 #ifndef ELINK_AUX_POWER 15027 elink_cb_event_log(cb, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has" 15028 // " been detected and the power to " 15029 // "that SFP+ module has been removed" 15030 // " to prevent failure of the card." 15031 // " Please remove the SFP+ module and" 15032 // " restart the system to clear this" 15033 // " error.\n", 15034 #endif /* ELINK_AUX_POWER */ 15035 vars->phy_flags |= PHY_OVER_CURRENT_FLAG; 15036 elink_warpcore_power_module(params, 0); 15037 } 15038 } else 15039 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; 15040 } 15041 #endif // EXCLUDE_WARPCORE 15042 15043 /* Returns 0 if no change occured since last check; 1 otherwise. */ 15044 static u8 elink_analyze_link_error(struct elink_params *params, 15045 struct elink_vars *vars, u32 status, 15046 u32 phy_flag, u32 link_flag, u8 notify) 15047 { 15048 struct elink_dev *cb = params->cb; 15049 /* Compare new value with previous value */ 15050 u8 led_mode; 15051 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0; 15052 15053 if ((status ^ old_status) == 0) 15054 return 0; 15055 15056 /* If values differ */ 15057 switch (phy_flag) { 15058 case PHY_HALF_OPEN_CONN_FLAG: 15059 ELINK_DEBUG_P0(cb, "Analyze Remote Fault\n"); 15060 break; 15061 case PHY_SFP_TX_FAULT_FLAG: 15062 ELINK_DEBUG_P0(cb, "Analyze TX Fault\n"); 15063 break; 15064 default: 15065 ELINK_DEBUG_P0(cb, "Analyze UNKNOWN\n"); 15066 } 15067 ELINK_DEBUG_P3(cb, "Link changed:[%x %x]->%x\n", vars->link_up, 15068 old_status, status); 15069 15070 /* Do not touch the link in case physical link down */ 15071 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) 15072 return 1; 15073 15074 /* a. Update shmem->link_status accordingly 15075 * b. Update elink_vars->link_up 15076 */ 15077 if (status) { 15078 vars->link_status &= ~LINK_STATUS_LINK_UP; 15079 vars->link_status |= link_flag; 15080 vars->link_up = 0; 15081 vars->phy_flags |= phy_flag; 15082 15083 /* activate nig drain */ 15084 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 15085 /* Set LED mode to off since the PHY doesn't know about these 15086 * errors 15087 */ 15088 led_mode = ELINK_LED_MODE_OFF; 15089 } else { 15090 vars->link_status |= LINK_STATUS_LINK_UP; 15091 vars->link_status &= ~link_flag; 15092 vars->link_up = 1; 15093 vars->phy_flags &= ~phy_flag; 15094 led_mode = ELINK_LED_MODE_OPER; 15095 15096 /* Clear nig drain */ 15097 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 15098 } 15099 #ifndef ELINK_AUX_POWER 15100 #ifdef ELINK_57711E_SUPPORT 15101 elink_sync_link(params, vars); 15102 #endif // ELINK_57711E_SUPPORT 15103 #endif // ELINK_AUX_POWER 15104 /* Update the LED according to the link state */ 15105 elink_set_led(params, vars, led_mode, ELINK_SPEED_10000); 15106 15107 /* Update link status in the shared memory */ 15108 elink_update_mng(params, vars->link_status); 15109 15110 /* C. Trigger General Attention */ 15111 vars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT; 15112 #ifndef EDEBUG 15113 if (notify) 15114 elink_cb_notify_link_changed(cb); 15115 #endif // EDEBUG 15116 15117 return 1; 15118 } 15119 15120 /****************************************************************************** 15121 * Description: 15122 * This function checks for half opened connection change indication. 15123 * When such change occurs, it calls the elink_analyze_link_error 15124 * to check if Remote Fault is set or cleared. Reception of remote fault 15125 * status message in the MAC indicates that the peer's MAC has detected 15126 * a fault, for example, due to break in the TX side of fiber. 15127 * 15128 ******************************************************************************/ 15129 #ifdef BNX2X_ADD /* BNX2X_ADD */ 15130 static 15131 #endif 15132 elink_status_t elink_check_half_open_conn(struct elink_params *params, 15133 struct elink_vars *vars, 15134 u8 notify) 15135 { 15136 struct elink_dev *cb = params->cb; 15137 u32 lss_status = 0; 15138 u32 mac_base; 15139 /* In case link status is physically up @ 10G do */ 15140 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || 15141 (REG_RD(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) 15142 return ELINK_STATUS_OK; 15143 15144 if (CHIP_IS_E3(params->chip_id) && 15145 (REG_RD(cb, MISC_REG_RESET_REG_2) & 15146 (MISC_REGISTERS_RESET_REG_2_XMAC))) { 15147 /* Check E3 XMAC */ 15148 /* Note that link speed cannot be queried here, since it may be 15149 * zero while link is down. In case UMAC is active, LSS will 15150 * simply not be set 15151 */ 15152 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 15153 15154 /* Clear stick bits (Requires rising edge) */ 15155 REG_WR(cb, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 15156 REG_WR(cb, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 15157 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 15158 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 15159 if (REG_RD(cb, mac_base + XMAC_REG_RX_LSS_STATUS)) 15160 lss_status = 1; 15161 15162 elink_analyze_link_error(params, vars, lss_status, 15163 PHY_HALF_OPEN_CONN_FLAG, 15164 LINK_STATUS_NONE, notify); 15165 } else if (REG_RD(cb, MISC_REG_RESET_REG_2) & 15166 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { 15167 /* Check E1X / E2 BMAC */ 15168 u32 lss_status_reg; 15169 u32 wb_data[2]; 15170 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 15171 NIG_REG_INGRESS_BMAC0_MEM; 15172 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ 15173 if (CHIP_IS_E2(params->chip_id)) 15174 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; 15175 else 15176 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; 15177 15178 REG_RD_DMAE(cb, mac_base + lss_status_reg, wb_data, 2); 15179 lss_status = (wb_data[0] > 0); 15180 15181 elink_analyze_link_error(params, vars, lss_status, 15182 PHY_HALF_OPEN_CONN_FLAG, 15183 LINK_STATUS_NONE, notify); 15184 } 15185 return ELINK_STATUS_OK; 15186 } 15187 #ifdef ELINK_ENHANCEMENTS 15188 static void elink_sfp_tx_fault_detection(struct elink_phy *phy, 15189 struct elink_params *params, 15190 struct elink_vars *vars) 15191 { 15192 struct elink_dev *cb = params->cb; 15193 u32 cfg_pin, value = 0; 15194 u8 led_change, port = params->port; 15195 15196 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ 15197 cfg_pin = (REG_RD(cb, params->shmem_base + OFFSETOF(struct shmem_region, 15198 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 15199 PORT_HW_CFG_E3_TX_FAULT_MASK) >> 15200 PORT_HW_CFG_E3_TX_FAULT_SHIFT; 15201 15202 if (elink_get_cfg_pin(cb, cfg_pin, &value)) { 15203 ELINK_DEBUG_P1(cb, "Failed to read pin 0x%02x\n", cfg_pin); 15204 return; 15205 } 15206 15207 led_change = elink_analyze_link_error(params, vars, value, 15208 PHY_SFP_TX_FAULT_FLAG, 15209 LINK_STATUS_SFP_TX_FAULT, 1); 15210 15211 if (led_change) { 15212 /* Change TX_Fault led, set link status for further syncs */ 15213 u8 led_mode; 15214 15215 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { 15216 led_mode = MISC_REGISTERS_GPIO_HIGH; 15217 vars->link_status |= LINK_STATUS_SFP_TX_FAULT; 15218 } else { 15219 led_mode = MISC_REGISTERS_GPIO_LOW; 15220 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 15221 } 15222 15223 /* If module is unapproved, led should be on regardless */ 15224 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) { 15225 ELINK_DEBUG_P1(cb, "Change TX_Fault LED: ->%x\n", 15226 led_mode); 15227 elink_set_e3_module_fault_led(params, led_mode); 15228 } 15229 } 15230 } 15231 #endif 15232 #ifndef EXCLUDE_WARPCORE 15233 static void elink_kr2_recovery(struct elink_params *params, 15234 struct elink_vars *vars, 15235 struct elink_phy *phy) 15236 { 15237 #ifdef ELINK_DEBUG 15238 struct elink_dev *cb = params->cb; 15239 ELINK_DEBUG_P0(cb, "KR2 recovery\n"); 15240 #endif // ELINK_DEBUG 15241 elink_warpcore_enable_AN_KR2(phy, params, vars); 15242 elink_warpcore_restart_AN_KR(phy, params); 15243 } 15244 15245 static void elink_check_kr2_wa(struct elink_params *params, 15246 struct elink_vars *vars, 15247 struct elink_phy *phy) 15248 { 15249 struct elink_dev *cb = params->cb; 15250 u16 base_page, next_page, not_kr2_device, lane; 15251 int sigdet; 15252 15253 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery 15254 * Since some switches tend to reinit the AN process and clear the 15255 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled 15256 * and recovered many times 15257 */ 15258 if (vars->check_kr2_recovery_cnt > 0) { 15259 vars->check_kr2_recovery_cnt--; 15260 return; 15261 } 15262 15263 sigdet = elink_warpcore_get_sigdet(phy, params); 15264 if (!sigdet) { 15265 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 15266 elink_kr2_recovery(params, vars, phy); 15267 ELINK_DEBUG_P0(cb, "No sigdet\n"); 15268 } 15269 return; 15270 } 15271 15272 lane = elink_get_warpcore_lane(phy, params); 15273 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 15274 MDIO_AER_BLOCK_AER_REG, lane); 15275 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 15276 MDIO_AN_REG_LP_AUTO_NEG, &base_page); 15277 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 15278 MDIO_AN_REG_LP_AUTO_NEG2, &next_page); 15279 elink_set_aer_mmd(params, phy); 15280 15281 /* CL73 has not begun yet */ 15282 if (base_page == 0) { 15283 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 15284 elink_kr2_recovery(params, vars, phy); 15285 ELINK_DEBUG_P0(cb, "No BP\n"); 15286 } 15287 return; 15288 } 15289 15290 /* In case NP bit is not set in the BasePage, or it is set, 15291 * but only KX is advertised, declare this link partner as non-KR2 15292 * device. 15293 */ 15294 not_kr2_device = (((base_page & 0x8000) == 0) || 15295 (((base_page & 0x8000) && 15296 ((next_page & 0xe0) == 0x20)))); 15297 15298 /* In case KR2 is already disabled, check if we need to re-enable it */ 15299 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 15300 if (!not_kr2_device) { 15301 ELINK_DEBUG_P2(cb, "BP=0x%x, NP=0x%x\n", base_page, 15302 next_page); 15303 elink_kr2_recovery(params, vars, phy); 15304 } 15305 return; 15306 } 15307 /* KR2 is enabled, but not KR2 device */ 15308 if (not_kr2_device) { 15309 /* Disable KR2 on both lanes */ 15310 ELINK_DEBUG_P2(cb, "BP=0x%x, NP=0x%x\n", base_page, next_page); 15311 elink_disable_kr2(params, vars, phy); 15312 /* Restart AN on leading lane */ 15313 elink_warpcore_restart_AN_KR(phy, params); 15314 return; 15315 } 15316 } 15317 #endif 15318 15319 void elink_period_func(struct elink_params *params, struct elink_vars *vars) 15320 { 15321 u16 phy_idx; 15322 #if defined(ELINK_DEBUG) || defined(ELINK_ENHANCEMENTS) 15323 struct elink_dev *cb = params->cb; 15324 #endif 15325 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 15326 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) { 15327 elink_set_aer_mmd(params, ¶ms->phy[phy_idx]); 15328 if (elink_check_half_open_conn(params, vars, 1) != 15329 ELINK_STATUS_OK) 15330 ELINK_DEBUG_P0(cb, "Fault detection failed\n"); 15331 break; 15332 } 15333 } 15334 15335 #ifndef EXCLUDE_WARPCORE 15336 if (CHIP_IS_E3(params->chip_id)) { 15337 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; 15338 elink_set_aer_mmd(params, phy); 15339 if ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) && 15340 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) 15341 elink_check_kr2_wa(params, vars, phy); 15342 #ifdef ELINK_AUX_POWER 15343 if ((phy->flags & ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC) == 0) { 15344 if (elink_is_sfp_module_plugged(phy, params)) { 15345 phy->flags |= 15346 ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC; 15347 elink_sfp_module_detection(phy, params); 15348 } 15349 } else { 15350 if (!elink_is_sfp_module_plugged(phy, params)) { 15351 elink_sfp_set_transmitter(params, phy, 1); 15352 phy->flags &= 15353 ~ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC; 15354 } 15355 } 15356 #endif // ELINK_AUX_POWER 15357 elink_check_over_curr(params, vars); 15358 #ifdef ELINK_ENHANCEMENTS 15359 if (vars->rx_tx_asic_rst) 15360 elink_warpcore_config_runtime(phy, params, vars); 15361 15362 if ((REG_RD(cb, params->shmem_base + 15363 OFFSETOF(struct shmem_region, dev_info. 15364 port_hw_config[params->port].default_cfg)) 15365 & PORT_HW_CFG_NET_SERDES_IF_MASK) == 15366 PORT_HW_CFG_NET_SERDES_IF_SFI) { 15367 if (elink_is_sfp_module_plugged(phy, params)) { 15368 elink_sfp_tx_fault_detection(phy, params, vars); 15369 } else if (vars->link_status & 15370 LINK_STATUS_SFP_TX_FAULT) { 15371 /* Clean trail, interrupt corrects the leds */ 15372 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 15373 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; 15374 /* Update link status in the shared memory */ 15375 elink_update_mng(params, vars->link_status); 15376 } 15377 } 15378 #endif // ELINK_ENHANCEMENTS 15379 } 15380 #endif /* EXCLUDE_WARPCORE */ 15381 } 15382 15383 #ifdef ELINK_ENHANCEMENTS 15384 u8 elink_fan_failure_det_req(struct elink_dev *cb, 15385 u32 shmem_base, 15386 u32 shmem2_base, 15387 u8 port) 15388 { 15389 u8 phy_index, fan_failure_det_req = 0; 15390 struct elink_phy phy; 15391 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; 15392 phy_index++) { 15393 if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base, 15394 port, &phy) 15395 != ELINK_STATUS_OK) { 15396 ELINK_DEBUG_P0(cb, "populate phy failed\n"); 15397 return 0; 15398 } 15399 fan_failure_det_req |= (phy.flags & 15400 ELINK_FLAGS_FAN_FAILURE_DET_REQ); 15401 } 15402 return fan_failure_det_req; 15403 } 15404 #endif // ELINK_ENHANCEMENTS 15405 #ifdef ELINK_AUX_POWER 15406 void elink_enable_pmd_tx(struct elink_params *params) 15407 { 15408 u8 phy_index; 15409 elink_set_mdio_emac_per_phy(params->cb, params); 15410 15411 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; 15412 phy_index++) { 15413 switch (params->phy[phy_index].type) { 15414 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 15415 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 15416 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 15417 elink_cl45_write(params->cb, ¶ms->phy[phy_index], 15418 MDIO_PMA_DEVAD, 15419 MDIO_PMA_REG_TX_DISABLE, 0); 15420 default: 15421 break; 15422 } 15423 } 15424 } 15425 #endif // ELINK_AUX_POWER 15426 15427 void elink_hw_reset_phy(struct elink_params *params) 15428 { 15429 u8 phy_index; 15430 struct elink_dev *cb = params->cb; 15431 elink_update_mng(params, 0); 15432 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 15433 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 15434 ELINK_NIG_MASK_XGXS0_LINK10G | 15435 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 15436 ELINK_NIG_MASK_MI_INT)); 15437 15438 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; 15439 phy_index++) { 15440 if (params->phy[phy_index].hw_reset) { 15441 params->phy[phy_index].hw_reset( 15442 ¶ms->phy[phy_index], 15443 params); 15444 params->phy[phy_index] = phy_null; 15445 } 15446 } 15447 } 15448 15449 #ifdef ELINK_ENHANCEMENTS 15450 void elink_init_mod_abs_int(struct elink_dev *cb, struct elink_vars *vars, 15451 u32 chip_id, u32 shmem_base, u32 shmem2_base, 15452 u8 port) 15453 { 15454 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index; 15455 u32 val; 15456 u32 offset, aeu_mask, swap_val, swap_override, sync_offset; 15457 if (CHIP_IS_E3(chip_id)) { 15458 if (elink_get_mod_abs_int_cfg(cb, chip_id, 15459 shmem_base, 15460 port, 15461 &gpio_num, 15462 &gpio_port) != ELINK_STATUS_OK) 15463 return; 15464 } else { 15465 struct elink_phy phy; 15466 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; 15467 phy_index++) { 15468 if (elink_populate_phy(cb, phy_index, shmem_base, 15469 shmem2_base, port, &phy) 15470 != ELINK_STATUS_OK) { 15471 ELINK_DEBUG_P0(cb, "populate phy failed\n"); 15472 return; 15473 } 15474 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { 15475 gpio_num = MISC_REGISTERS_GPIO_3; 15476 gpio_port = port; 15477 break; 15478 } 15479 } 15480 } 15481 15482 if (gpio_num == 0xff) 15483 return; 15484 15485 /* Set GPIO3 to trigger SFP+ module insertion/removal */ 15486 ELINK_SET_GPIO(cb, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); 15487 15488 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP); 15489 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE); 15490 gpio_port ^= (swap_val && swap_override); 15491 15492 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << 15493 (gpio_num + (gpio_port << 2)); 15494 15495 sync_offset = shmem_base + 15496 OFFSETOF(struct shmem_region, 15497 dev_info.port_hw_config[port].aeu_int_mask); 15498 REG_WR(cb, sync_offset, vars->aeu_int_mask); 15499 15500 ELINK_DEBUG_P3(cb, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", 15501 gpio_num, gpio_port, vars->aeu_int_mask); 15502 15503 if (port == 0) 15504 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; 15505 else 15506 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; 15507 15508 /* Open appropriate AEU for interrupts */ 15509 aeu_mask = REG_RD(cb, offset); 15510 aeu_mask |= vars->aeu_int_mask; 15511 REG_WR(cb, offset, aeu_mask); 15512 15513 /* Enable the GPIO to trigger interrupt */ 15514 val = REG_RD(cb, MISC_REG_GPIO_EVENT_EN); 15515 val |= 1 << (gpio_num + (gpio_port << 2)); 15516 REG_WR(cb, MISC_REG_GPIO_EVENT_EN, val); 15517 } 15518 #endif // ELINK_ENHANCEMENTS 15519 #endif // EXCLUDE_NON_COMMON_INIT 15520 15521 #ifdef ELINK_AUX_POWER 15522 void elink_adjust_phy_func_ptr(struct elink_params *params) 15523 { 15524 u32 phy_idx; 15525 struct elink_phy phy, *cur_phy; 15526 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 15527 cur_phy = ¶ms->phy[phy_idx]; 15528 /* Select the phy type */ 15529 switch (cur_phy->type) { 15530 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 15531 #ifndef EXCLUDE_WARPCORE 15532 phy = phy_warpcore; 15533 #else 15534 phy = phy_xgxs; 15535 #endif 15536 break; 15537 #ifndef EXCLUDE_BCM8727_BCM8073 15538 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 15539 phy = phy_8073; 15540 break; 15541 #endif 15542 #ifndef EXCLUDE_BCM8705 15543 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 15544 phy = phy_8705; 15545 break; 15546 #endif 15547 #ifndef EXCLUDE_BCM87x6 15548 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 15549 phy = phy_8706; 15550 break; 15551 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 15552 phy = phy_8726; 15553 break; 15554 #endif /* EXCLUDE_BCM87x6 */ 15555 #ifndef EXCLUDE_BCM8727_BCM8073 15556 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 15557 phy = phy_8727; 15558 break; 15559 #endif 15560 #ifndef EXCLUDE_BCM8481 15561 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 15562 phy = phy_8481; 15563 break; 15564 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 15565 phy = phy_84823; 15566 break; 15567 #endif 15568 #ifndef EXCLUDE_BCM84833 15569 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 15570 phy = phy_84833; 15571 break; 15572 #endif 15573 #ifndef EXCLUDE_BCM54618SE 15574 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: 15575 phy = phy_54618se; 15576 break; 15577 #endif 15578 #ifndef EXCLUDE_SFX7101 15579 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 15580 phy = phy_7101; 15581 break; 15582 #endif 15583 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 15584 phy = phy_null; 15585 return; 15586 default: 15587 phy = phy_null; 15588 continue; 15589 } 15590 cur_phy->config_init = phy.config_init; 15591 cur_phy->read_status = phy.read_status; 15592 cur_phy->link_reset = phy.link_reset; 15593 cur_phy->config_loopback = phy.config_loopback; 15594 cur_phy->format_fw_ver = phy.format_fw_ver; 15595 cur_phy->hw_reset = phy.hw_reset; 15596 cur_phy->set_link_led = phy.set_link_led; 15597 cur_phy->phy_specific_func = phy.phy_specific_func; 15598 } 15599 } 15600 15601 #ifndef EXCLUDE_COMMON_INIT 15602 elink_status_t elink_get_phy_temperature(struct elink_params *params, 15603 u32 *temp_reading, u8 path, u8 port) 15604 { 15605 /* The temperature returned from this function is expected 15606 * to be degree C. Any conversion from hardware value to 15607 * degree C will be performed here. 15608 */ 15609 15610 struct elink_phy *phy; 15611 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; 15612 elink_status_t rc; 15613 u8 idx; 15614 15615 for (idx = 0; idx < PHY84833_CMDHDLR_MAX_ARGS; idx++) 15616 cmd_args[idx] = 0; 15617 for (idx = 0; idx < params->num_phys; idx++) { 15618 phy = ¶ms->phy[idx]; 15619 if (phy->flags & ELINK_FLAGS_TEMPERATURE) { 15620 rc = elink_84833_cmd_hdlr(phy, params, 15621 PHY84833_CMD_GET_CURRENT_TEMP, 15622 cmd_args, 15623 PHY84833_CMDHDLR_MAX_ARGS); 15624 if ((path == 0) && (cmd_args[1] == 0)) 15625 cmd_args[1] = cmd_args[0] + 5; 15626 if (cmd_args[0] > cmd_args[1]) 15627 *temp_reading = (u32)cmd_args[0]; 15628 else 15629 *temp_reading = (u32)cmd_args[1]; 15630 15631 return rc; 15632 } 15633 } 15634 15635 return ELINK_STATUS_ERROR; 15636 } 15637 #ifndef EXCLUDE_WARPCORE 15638 void set_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 val) 15639 { 15640 elink_set_cfg_pin(cb, pin_cfg, val); 15641 } 15642 int get_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 *val) 15643 { 15644 return elink_get_cfg_pin(cb, pin_cfg, val); 15645 } 15646 15647 void elink_force_link(struct elink_params *params, int enable) { 15648 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; 15649 struct elink_dev *cb = params->cb; 15650 u8 lane = elink_get_warpcore_lane(phy, params); 15651 u16 val; 15652 15653 /* Global register - operate on lane 0 */ 15654 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 15655 MDIO_AER_BLOCK_AER_REG, 0); 15656 15657 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 15658 MDIO_WC_REG_XGXSBLK2_LANE_RESET, &val); 15659 if (enable) 15660 val &= ~(0x11 << lane); 15661 else 15662 val |= (0x11 << lane); 15663 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 15664 MDIO_WC_REG_XGXSBLK2_LANE_RESET, 15665 val); 15666 15667 /* Restore AER */ 15668 elink_set_aer_mmd(params, phy); 15669 } 15670 15671 #endif /* EXCLUDE_WARPCORE */ 15672 #endif /* #ifndef EXCLUDE_COMMON_INIT */ 15673 #endif 15674