1 #ifdef __LINUX 2 #include <linux/kernel.h> 3 #include <linux/types.h> 4 #include <asm/byteorder.h> 5 #endif 6 #ifdef USER_LINUX 7 #include <stdio.h> 8 #include <unistd.h> 9 #include <sys/types.h> 10 #include <sys/socket.h> 11 #include <netinet/in.h> 12 #include <arpa/inet.h> 13 #include <sys/ioctl.h> 14 #include <net/if.h> 15 #include <linux/sockios.h> 16 #include <string.h> 17 #include <malloc.h> 18 #endif 19 #ifdef __FreeBSD__ 20 #include <sys/types.h> 21 #endif 22 #include "bcmtype.h" 23 #ifdef EDEBUG 24 #include "edebug_types.h" 25 #endif 26 #include "clc.h" 27 #include "grc_addr.h" 28 #include "bigmac_addresses.h" 29 #include "emac_reg_driver.h" 30 #include "misc_bits.h" 31 #include "57712_reg.h" 32 #include "clc_reg.h" 33 #include "dev_info.h" 34 #include "license.h" 35 #include "shmem.h" 36 #include "aeu_inputs.h" 37 38 typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy, 39 struct elink_params *params, 40 u8 dev_addr, u16 addr, u8 byte_cnt, 41 u8 *o_buf, u8); 42 /********************************************************/ 43 #define ELINK_ETH_HLEN 14 44 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 45 #define ELINK_ETH_OVREHEAD (ELINK_ETH_HLEN + 8 + 8) 46 #define ELINK_ETH_MIN_PACKET_SIZE 60 47 #define ELINK_ETH_MAX_PACKET_SIZE 1500 48 #define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600 49 #define ELINK_MDIO_ACCESS_TIMEOUT 1000 50 #define WC_LANE_MAX 4 51 #define I2C_SWITCH_WIDTH 2 52 #define I2C_BSC0 0 53 #define I2C_BSC1 1 54 #define I2C_WA_RETRY_CNT 3 55 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) 56 #define MCPR_IMC_COMMAND_READ_OP 1 57 #define MCPR_IMC_COMMAND_WRITE_OP 2 58 59 /* LED Blink rate that will achieve ~15.9Hz */ 60 #define LED_BLINK_RATE_VAL_E3 354 61 #define LED_BLINK_RATE_VAL_E1X_E2 480 62 /***********************************************************/ 63 /* Macros */ 64 /***********************************************************/ 65 #define MSLEEP(cb, ms) elink_cb_udelay(cb, 1000*ms) 66 #define USLEEP(cb, us) elink_cb_udelay(cb, us) 67 #define REG_RD(cb, reg) elink_cb_reg_read(cb, reg) 68 #define REG_WR(cb, reg, val) elink_cb_reg_write(cb, reg, val) 69 #define EMAC_RD(cb, reg) REG_RD(cb, emac_base + reg) 70 #define EMAC_WR(cb, reg, val) REG_WR(cb, emac_base + reg, val) 71 #define REG_WR_DMAE(cb, offset, wb_data, len) \ 72 elink_cb_reg_wb_write(cb, offset, wb_data, len) 73 #define REG_RD_DMAE(cb, offset, wb_data, len) \ 74 elink_cb_reg_wb_read(cb, offset, wb_data, len) 75 #define PATH_ID(cb) elink_cb_path_id(cb) 76 77 #define ELINK_SET_GPIO elink_cb_gpio_write 78 #define ELINK_SET_MULT_GPIO elink_cb_gpio_mult_write 79 #define ELINK_GET_GPIO elink_cb_gpio_read 80 #define ELINK_SET_GPIO_INT elink_cb_gpio_int_write 81 82 #ifndef OFFSETOF 83 #define OFFSETOF(_s, _m) ((u32) ((u8 *)(&((_s *) 0)->_m) - \ 84 (u8 *)((u8 *) 0))) 85 #endif 86 87 #define CHIP_REV_SHIFT 12 88 #define CHIP_REV_MASK (0xF<<CHIP_REV_SHIFT) 89 #define CHIP_REV(_chip_id) ((_chip_id) & CHIP_REV_MASK) 90 91 #define CHIP_REV_Ax (0x0<<CHIP_REV_SHIFT) 92 #define CHIP_REV_Bx (0x1<<CHIP_REV_SHIFT) 93 #define CHIP_REV_IS_SLOW(_chip_id) \ 94 (CHIP_REV(_chip_id) > 0x00005000) 95 #define CHIP_REV_IS_FPGA(_chip_id) \ 96 (CHIP_REV_IS_SLOW(_chip_id)&& \ 97 (CHIP_REV(_chip_id) & 0x00001000)) 98 #define CHIP_REV_IS_EMUL(_chip_id) \ 99 (CHIP_REV_IS_SLOW(_chip_id)&& \ 100 !(CHIP_REV(_chip_id) & 0x00001000)) 101 102 #define CHIP_NUM(_chip_id) (_chip_id >> 16) 103 #define CHIP_NUM_57710 0x164e 104 #define CHIP_NUM_57711 0x164f 105 #define CHIP_NUM_57711E 0x1650 106 #define CHIP_NUM_57712 0x1662 107 #define CHIP_NUM_57712E 0x1663 108 #define CHIP_NUM_57713 0x1651 109 #define CHIP_NUM_57713E 0x1652 110 #define CHIP_NUM_57840_OBSOLETE 0x168d 111 #define CHIP_NUM_57840_4_10 0x16a1 112 #define CHIP_NUM_57840_2_20 0x16a2 113 #define CHIP_NUM_57810 0x168e 114 #define CHIP_NUM_57800 0x168a 115 #define CHIP_NUM_57811 0x163d 116 #define CHIP_NUM_57811_MF 0x163e 117 #define CHIP_IS_E1(_chip_id) (CHIP_NUM(_chip_id) == \ 118 CHIP_NUM_57710) 119 #define CHIP_IS_E1X(_chip_id) ((CHIP_NUM(_chip_id) == \ 120 CHIP_NUM_57710) || \ 121 (CHIP_NUM(_chip_id) == \ 122 CHIP_NUM_57711) || \ 123 (CHIP_NUM(_chip_id) == \ 124 CHIP_NUM_57711E)) 125 126 #define CHIP_IS_E2(_chip_id) ((CHIP_NUM(_chip_id) == \ 127 CHIP_NUM_57712) || \ 128 (CHIP_NUM(_chip_id) == \ 129 CHIP_NUM_57712E) || \ 130 (CHIP_NUM(_chip_id) == \ 131 CHIP_NUM_57713) || \ 132 (CHIP_NUM(_chip_id) == \ 133 CHIP_NUM_57713E)) 134 135 #define CHIP_IS_57711(_chip_id) (CHIP_NUM(_chip_id) == \ 136 CHIP_NUM_57711) 137 #define CHIP_IS_57711E(_chip_id) (CHIP_NUM(_chip_id) == \ 138 CHIP_NUM_57711E) 139 #define DO_CHIP_IS_E3(_chip_family) ((_chip_family == 0x1630) || \ 140 (_chip_family == 0x1680) || \ 141 (_chip_family == 0x16a0)) 142 #define CHIP_IS_E3(_chip_id) (DO_CHIP_IS_E3(((CHIP_NUM(_chip_id)) & 0xfff0))) 143 144 145 /* For EMUL: Ax=0xE, Bx=0xC, Cx=0xA. For FPGA: Ax=0xF, Bx=0xD, 146 * Cx=0xB. 147 */ 148 #define CHIP_REV_SIM(_p) (((0xF - (CHIP_REV(_p) >> CHIP_REV_SHIFT)) \ 149 >>1) << CHIP_REV_SHIFT) 150 151 #define CHIP_IS_E3B0(_p) (CHIP_IS_E3(_p) && \ 152 ((CHIP_REV(_p) == CHIP_REV_Bx) || \ 153 (CHIP_REV_SIM(_p) == CHIP_REV_Bx))) 154 155 #define CHIP_IS_E3A0(_p) (CHIP_IS_E3(_p) && \ 156 ((CHIP_REV(_p) == CHIP_REV_Ax) || \ 157 (CHIP_REV_SIM(_p) == CHIP_REV_Ax))) 158 159 #define ELINK_USES_WARPCORE(_chip_id) (CHIP_IS_E3(_chip_id)) 160 161 #define SHMEM2_RD(cb, shmem2_base, _field) \ 162 REG_RD(cb, shmem2_base + \ 163 OFFSETOF(struct shmem2_region, \ 164 _field)) 165 166 #define SHMEM2_HAS(cb, shmem2_base, field) (shmem2_base && \ 167 (SHMEM2_RD(cb, shmem2_base, size) > \ 168 OFFSETOF(struct shmem2_region, field))) 169 #ifndef NULL 170 #define NULL ((void *) 0) 171 #endif 172 173 /***********************************************************/ 174 /* Shortcut definitions */ 175 /***********************************************************/ 176 177 #define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0 178 179 #define ELINK_NIG_STATUS_EMAC0_MI_INT \ 180 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT 181 #define ELINK_NIG_STATUS_XGXS0_LINK10G \ 182 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G 183 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \ 184 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS 185 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ 186 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 187 #define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \ 188 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS 189 #define ELINK_NIG_MASK_MI_INT \ 190 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT 191 #define ELINK_NIG_MASK_XGXS0_LINK10G \ 192 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G 193 #define ELINK_NIG_MASK_XGXS0_LINK_STATUS \ 194 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS 195 #define ELINK_NIG_MASK_SERDES0_LINK_STATUS \ 196 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS 197 198 #define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \ 199 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ 200 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) 201 202 #define ELINK_XGXS_RESET_BITS \ 203 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ 204 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ 205 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ 206 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ 207 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) 208 209 #define ELINK_SERDES_RESET_BITS \ 210 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ 211 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ 212 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ 213 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) 214 215 #define ELINK_AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 216 #define ELINK_AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 217 #define ELINK_AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM 218 #define ELINK_AUTONEG_PARALLEL \ 219 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 220 #define ELINK_AUTONEG_SGMII_FIBER_AUTODET \ 221 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 222 #define ELINK_AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 223 224 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ 225 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 226 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ 227 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 228 #define ELINK_GP_STATUS_SPEED_MASK \ 229 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 230 #define ELINK_GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 231 #define ELINK_GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 232 #define ELINK_GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 233 #define ELINK_GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 234 #define ELINK_GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 235 #define ELINK_GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 236 #define ELINK_GP_STATUS_10G_HIG \ 237 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 238 #define ELINK_GP_STATUS_10G_CX4 \ 239 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 240 #define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 241 #define ELINK_GP_STATUS_10G_KX4 \ 242 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 243 #define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 244 #define ELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 245 #define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 246 #define ELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 247 #define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 248 #define ELINK_LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD 249 #define ELINK_LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD 250 #define ELINK_LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD 251 #define ELINK_LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 252 #define ELINK_LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD 253 #define ELINK_LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD 254 #define ELINK_LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD 255 #define ELINK_LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD 256 #define ELINK_LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD 257 #define ELINK_LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD 258 #define ELINK_LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD 259 #define ELINK_LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD 260 #define ELINK_LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD 261 #define ELINK_LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD 262 #define ELINK_LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD 263 264 #define ELINK_LINK_UPDATE_MASK \ 265 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \ 266 LINK_STATUS_LINK_UP | \ 267 LINK_STATUS_PHYSICAL_LINK_FLAG | \ 268 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \ 269 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \ 270 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \ 271 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \ 272 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \ 273 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 274 275 #define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2 276 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0 277 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7 278 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 279 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 280 281 282 #define ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR 0x3 283 #define ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK (1<<4) 284 #define ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK (1<<5) 285 #define ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK (1<<6) 286 287 #define ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR 0x6 288 #define ELINK_SFP_EEPROM_1G_COMP_CODE_SX (1<<0) 289 #define ELINK_SFP_EEPROM_1G_COMP_CODE_LX (1<<1) 290 #define ELINK_SFP_EEPROM_1G_COMP_CODE_CX (1<<2) 291 #define ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T (1<<3) 292 293 #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8 294 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 295 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 296 297 #define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40 298 #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 299 #define ELINK_SFP_EEPROM_OPTIONS_SIZE 2 300 301 #define ELINK_EDC_MODE_LINEAR 0x0022 302 #define ELINK_EDC_MODE_LIMITING 0x0044 303 #define ELINK_EDC_MODE_PASSIVE_DAC 0x0055 304 #define ELINK_EDC_MODE_ACTIVE_DAC 0x0066 305 306 /* ETS defines*/ 307 #define DCBX_INVALID_COS (0xFF) 308 309 #define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) 310 #define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) 311 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) 312 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) 313 #define ELINK_ETS_E3B0_PBF_MIN_W_VAL (10000) 314 315 #define ELINK_MAX_PACKET_SIZE (9700) 316 #ifdef INCLUDE_WARPCORE_UC_LOAD 317 #define ELINK_WC_UC_TIMEOUT 1000 318 #define ELINK_WC_RDY_TIMEOUT_MSEC 100 319 #endif 320 #define MAX_KR_LINK_RETRY 4 321 322 /**********************************************************/ 323 /* INTERFACE */ 324 /**********************************************************/ 325 326 #define CL22_WR_OVER_CL45(_cb, _phy, _bank, _addr, _val) \ 327 elink_cl45_write(_cb, _phy, \ 328 (_phy)->def_md_devad, \ 329 (_bank + (_addr & 0xf)), \ 330 _val) 331 332 #define CL22_RD_OVER_CL45(_cb, _phy, _bank, _addr, _val) \ 333 elink_cl45_read(_cb, _phy, \ 334 (_phy)->def_md_devad, \ 335 (_bank + (_addr & 0xf)), \ 336 _val) 337 338 #ifdef BNX2X_ADD /* BNX2X_ADD */ 339 static int elink_check_half_open_conn(struct elink_params *params, 340 struct elink_vars *vars, u8 notify); 341 static int elink_sfp_module_detection(struct elink_phy *phy, 342 struct elink_params *params); 343 #endif 344 345 static u32 elink_bits_en(struct elink_dev *cb, u32 reg, u32 bits) 346 { 347 u32 val = REG_RD(cb, reg); 348 349 val |= bits; 350 REG_WR(cb, reg, val); 351 return val; 352 } 353 354 static u32 elink_bits_dis(struct elink_dev *cb, u32 reg, u32 bits) 355 { 356 u32 val = REG_RD(cb, reg); 357 358 val &= ~bits; 359 REG_WR(cb, reg, val); 360 return val; 361 } 362 363 /* 364 * elink_check_lfa - This function checks if link reinitialization is required, 365 * or link flap can be avoided. 366 * 367 * @params: link parameters 368 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed 369 * condition code. 370 */ 371 #ifndef EXCLUDE_NON_COMMON_INIT 372 static int elink_check_lfa(struct elink_params *params) 373 { 374 u32 link_status, cfg_idx, lfa_mask, cfg_size; 375 u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config; 376 u32 saved_val, req_val, eee_status; 377 struct elink_dev *cb = params->cb; 378 379 additional_config = 380 REG_RD(cb, params->lfa_base + 381 OFFSETOF(struct shmem_lfa, additional_config)); 382 383 /* NOTE: must be first condition checked - 384 * to verify DCC bit is cleared in any case! 385 */ 386 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) { 387 ELINK_DEBUG_P0(cb, "No LFA due to DCC flap after clp exit\n"); 388 REG_WR(cb, params->lfa_base + 389 OFFSETOF(struct shmem_lfa, additional_config), 390 additional_config & ~NO_LFA_DUE_TO_DCC_MASK); 391 return LFA_DCC_LFA_DISABLED; 392 } 393 394 /* Verify that link is up */ 395 link_status = REG_RD(cb, params->shmem_base + 396 OFFSETOF(struct shmem_region, 397 port_mb[params->port].link_status)); 398 if (!(link_status & LINK_STATUS_LINK_UP)) 399 return LFA_LINK_DOWN; 400 401 /* if loaded after BOOT from SAN, don't flap the link in any case and 402 * rely on link set by preboot driver 403 */ 404 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN) 405 return 0; 406 407 /* Verify that loopback mode is not set */ 408 if (params->loopback_mode) 409 return LFA_LOOPBACK_ENABLED; 410 411 /* Verify that MFW supports LFA */ 412 if (!params->lfa_base) 413 return LFA_MFW_IS_TOO_OLD; 414 415 if (params->num_phys == 3) { 416 cfg_size = 2; 417 lfa_mask = 0xffffffff; 418 } else { 419 cfg_size = 1; 420 lfa_mask = 0xffff; 421 } 422 423 /* Compare Duplex */ 424 saved_val = REG_RD(cb, params->lfa_base + 425 OFFSETOF(struct shmem_lfa, req_duplex)); 426 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); 427 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 428 ELINK_DEBUG_P2(cb, "Duplex mismatch %x vs. %x\n", 429 (saved_val & lfa_mask), (req_val & lfa_mask)); 430 return LFA_DUPLEX_MISMATCH; 431 } 432 /* Compare Flow Control */ 433 saved_val = REG_RD(cb, params->lfa_base + 434 OFFSETOF(struct shmem_lfa, req_flow_ctrl)); 435 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); 436 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 437 ELINK_DEBUG_P2(cb, "Flow control mismatch %x vs. %x\n", 438 (saved_val & lfa_mask), (req_val & lfa_mask)); 439 return LFA_FLOW_CTRL_MISMATCH; 440 } 441 /* Compare Link Speed */ 442 saved_val = REG_RD(cb, params->lfa_base + 443 OFFSETOF(struct shmem_lfa, req_line_speed)); 444 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); 445 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 446 ELINK_DEBUG_P2(cb, "Link speed mismatch %x vs. %x\n", 447 (saved_val & lfa_mask), (req_val & lfa_mask)); 448 return LFA_LINK_SPEED_MISMATCH; 449 } 450 451 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) { 452 cur_speed_cap_mask = REG_RD(cb, params->lfa_base + 453 OFFSETOF(struct shmem_lfa, 454 speed_cap_mask[cfg_idx])); 455 456 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { 457 ELINK_DEBUG_P2(cb, "Speed Cap mismatch %x vs. %x\n", 458 cur_speed_cap_mask, 459 params->speed_cap_mask[cfg_idx]); 460 return LFA_SPEED_CAP_MISMATCH; 461 } 462 } 463 464 cur_req_fc_auto_adv = 465 REG_RD(cb, params->lfa_base + 466 OFFSETOF(struct shmem_lfa, additional_config)) & 467 REQ_FC_AUTO_ADV_MASK; 468 469 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) { 470 ELINK_DEBUG_P2(cb, "Flow Ctrl AN mismatch %x vs. %x\n", 471 cur_req_fc_auto_adv, params->req_fc_auto_adv); 472 return LFA_FLOW_CTRL_MISMATCH; 473 } 474 475 eee_status = REG_RD(cb, params->shmem2_base + 476 OFFSETOF(struct shmem2_region, 477 eee_status[params->port])); 478 479 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^ 480 (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) || 481 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^ 482 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) { 483 ELINK_DEBUG_P2(cb, "EEE mismatch %x vs. %x\n", params->eee_mode, 484 eee_status); 485 return LFA_EEE_MISMATCH; 486 } 487 488 /* LFA conditions are met */ 489 return 0; 490 } 491 #endif 492 /******************************************************************/ 493 /* EPIO/GPIO section */ 494 /******************************************************************/ 495 #if (!defined EXCLUDE_WARPCORE) 496 static void elink_get_epio(struct elink_dev *cb, u32 epio_pin, u32 *en) 497 { 498 u32 epio_mask, gp_oenable; 499 *en = 0; 500 /* Sanity check */ 501 if (epio_pin > 31) { 502 ELINK_DEBUG_P1(cb, "Invalid EPIO pin %d to get\n", epio_pin); 503 return; 504 } 505 506 epio_mask = 1 << epio_pin; 507 /* Set this EPIO to output */ 508 gp_oenable = REG_RD(cb, MCP_REG_MCPR_GP_OENABLE); 509 REG_WR(cb, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); 510 511 *en = (REG_RD(cb, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; 512 } 513 static void elink_set_epio(struct elink_dev *cb, u32 epio_pin, u32 en) 514 { 515 u32 epio_mask, gp_output, gp_oenable; 516 517 /* Sanity check */ 518 if (epio_pin > 31) { 519 ELINK_DEBUG_P1(cb, "Invalid EPIO pin %d to set\n", epio_pin); 520 return; 521 } 522 ELINK_DEBUG_P2(cb, "Setting EPIO pin %d to %d\n", epio_pin, en); 523 epio_mask = 1 << epio_pin; 524 /* Set this EPIO to output */ 525 gp_output = REG_RD(cb, MCP_REG_MCPR_GP_OUTPUTS); 526 if (en) 527 gp_output |= epio_mask; 528 else 529 gp_output &= ~epio_mask; 530 531 REG_WR(cb, MCP_REG_MCPR_GP_OUTPUTS, gp_output); 532 533 /* Set the value for this EPIO */ 534 gp_oenable = REG_RD(cb, MCP_REG_MCPR_GP_OENABLE); 535 REG_WR(cb, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); 536 } 537 538 static void elink_set_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 val) 539 { 540 if (pin_cfg == PIN_CFG_NA) 541 return; 542 if (pin_cfg >= PIN_CFG_EPIO0) { 543 elink_set_epio(cb, pin_cfg - PIN_CFG_EPIO0, val); 544 } else { 545 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 546 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 547 ELINK_SET_GPIO(cb, gpio_num, (u8)val, gpio_port); 548 } 549 } 550 551 static u32 elink_get_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 *val) 552 { 553 if (pin_cfg == PIN_CFG_NA) 554 return ELINK_STATUS_ERROR; 555 if (pin_cfg >= PIN_CFG_EPIO0) { 556 elink_get_epio(cb, pin_cfg - PIN_CFG_EPIO0, val); 557 } else { 558 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 559 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 560 *val = ELINK_GET_GPIO(cb, gpio_num, gpio_port); 561 } 562 return ELINK_STATUS_OK; 563 564 } 565 #endif /* (!defined EXCLUDE_WARPCORE) */ 566 /******************************************************************/ 567 /* ETS section */ 568 /******************************************************************/ 569 #ifdef ELINK_ENHANCEMENTS 570 static void elink_ets_e2e3a0_disabled(struct elink_params *params) 571 { 572 /* ETS disabled configuration*/ 573 struct elink_dev *cb = params->cb; 574 575 ELINK_DEBUG_P0(cb, "ETS E2E3 disabled configuration\n"); 576 577 /* mapping between entry priority to client number (0,1,2 -debug and 578 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 579 * 3bits client num. 580 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 581 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 582 */ 583 584 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); 585 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 586 * as strict. Bits 0,1,2 - debug and management entries, 3 - 587 * COS0 entry, 4 - COS1 entry. 588 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 589 * bit4 bit3 bit2 bit1 bit0 590 * MCP and debug are strict 591 */ 592 593 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 594 /* defines which entries (clients) are subjected to WFQ arbitration */ 595 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 596 /* For strict priority entries defines the number of consecutive 597 * slots for the highest priority. 598 */ 599 REG_WR(cb, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 600 /* mapping between the CREDIT_WEIGHT registers and actual client 601 * numbers 602 */ 603 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); 604 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); 605 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); 606 607 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); 608 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); 609 REG_WR(cb, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); 610 /* ETS mode disable */ 611 REG_WR(cb, PBF_REG_ETS_ENABLED, 0); 612 /* If ETS mode is enabled (there is no strict priority) defines a WFQ 613 * weight for COS0/COS1. 614 */ 615 REG_WR(cb, PBF_REG_COS0_WEIGHT, 0x2710); 616 REG_WR(cb, PBF_REG_COS1_WEIGHT, 0x2710); 617 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ 618 REG_WR(cb, PBF_REG_COS0_UPPER_BOUND, 0x989680); 619 REG_WR(cb, PBF_REG_COS1_UPPER_BOUND, 0x989680); 620 /* Defines the number of consecutive slots for the strict priority */ 621 REG_WR(cb, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 622 } 623 /****************************************************************************** 624 * Description: 625 * Getting min_w_val will be set according to line speed . 626 *. 627 ******************************************************************************/ 628 static u32 elink_ets_get_min_w_val_nig(const struct elink_vars *vars) 629 { 630 u32 min_w_val = 0; 631 /* Calculate min_w_val.*/ 632 if (vars->link_up) { 633 if (vars->line_speed == ELINK_SPEED_20000) 634 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 635 else 636 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; 637 } else 638 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 639 /* If the link isn't up (static configuration for example ) The 640 * link will be according to 20GBPS. 641 */ 642 return min_w_val; 643 } 644 /****************************************************************************** 645 * Description: 646 * Getting credit upper bound form min_w_val. 647 *. 648 ******************************************************************************/ 649 static u32 elink_ets_get_credit_upper_bound(const u32 min_w_val) 650 { 651 const u32 credit_upper_bound = (u32)ELINK_MAXVAL((150 * min_w_val), 652 ELINK_MAX_PACKET_SIZE); 653 return credit_upper_bound; 654 } 655 /****************************************************************************** 656 * Description: 657 * Set credit upper bound for NIG. 658 *. 659 ******************************************************************************/ 660 static void elink_ets_e3b0_set_credit_upper_bound_nig( 661 const struct elink_params *params, 662 const u32 min_w_val) 663 { 664 struct elink_dev *cb = params->cb; 665 const u8 port = params->port; 666 const u32 credit_upper_bound = 667 elink_ets_get_credit_upper_bound(min_w_val); 668 669 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : 670 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); 671 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : 672 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); 673 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : 674 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); 675 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : 676 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); 677 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : 678 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); 679 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : 680 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); 681 682 if (!port) { 683 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, 684 credit_upper_bound); 685 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, 686 credit_upper_bound); 687 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, 688 credit_upper_bound); 689 } 690 } 691 /****************************************************************************** 692 * Description: 693 * Will return the NIG ETS registers to init values.Except 694 * credit_upper_bound. 695 * That isn't used in this configuration (No WFQ is enabled) and will be 696 * configured acording to spec 697 *. 698 ******************************************************************************/ 699 static void elink_ets_e3b0_nig_disabled(const struct elink_params *params, 700 const struct elink_vars *vars) 701 { 702 struct elink_dev *cb = params->cb; 703 const u8 port = params->port; 704 const u32 min_w_val = elink_ets_get_min_w_val_nig(vars); 705 /* Mapping between entry priority to client number (0,1,2 -debug and 706 * management clients, 3 - COS0 client, 4 - COS1, ... 8 - 707 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by 708 * reset value or init tool 709 */ 710 if (port) { 711 REG_WR(cb, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); 712 REG_WR(cb, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); 713 } else { 714 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); 715 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); 716 } 717 /* For strict priority entries defines the number of consecutive 718 * slots for the highest priority. 719 */ 720 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : 721 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 722 /* Mapping between the CREDIT_WEIGHT registers and actual client 723 * numbers 724 */ 725 if (port) { 726 /*Port 1 has 6 COS*/ 727 REG_WR(cb, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); 728 REG_WR(cb, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); 729 } else { 730 /*Port 0 has 9 COS*/ 731 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 732 0x43210876); 733 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); 734 } 735 736 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 737 * as strict. Bits 0,1,2 - debug and management entries, 3 - 738 * COS0 entry, 4 - COS1 entry. 739 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 740 * bit4 bit3 bit2 bit1 bit0 741 * MCP and debug are strict 742 */ 743 if (port) 744 REG_WR(cb, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); 745 else 746 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); 747 /* defines which entries (clients) are subjected to WFQ arbitration */ 748 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 749 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 750 751 /* Please notice the register address are note continuous and a 752 * for here is note appropriate.In 2 port mode port0 only COS0-5 753 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 754 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT 755 * are never used for WFQ 756 */ 757 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 758 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); 759 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 760 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); 761 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 762 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); 763 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : 764 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); 765 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : 766 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); 767 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : 768 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); 769 if (!port) { 770 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); 771 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); 772 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); 773 } 774 775 elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); 776 } 777 /****************************************************************************** 778 * Description: 779 * Set credit upper bound for PBF. 780 *. 781 ******************************************************************************/ 782 static void elink_ets_e3b0_set_credit_upper_bound_pbf( 783 const struct elink_params *params, 784 const u32 min_w_val) 785 { 786 struct elink_dev *cb = params->cb; 787 const u32 credit_upper_bound = 788 elink_ets_get_credit_upper_bound(min_w_val); 789 const u8 port = params->port; 790 u32 base_upper_bound = 0; 791 u8 max_cos = 0; 792 u8 i = 0; 793 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 794 * port mode port1 has COS0-2 that can be used for WFQ. 795 */ 796 if (!port) { 797 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; 798 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 799 } else { 800 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; 801 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1; 802 } 803 804 for (i = 0; i < max_cos; i++) 805 REG_WR(cb, base_upper_bound + (i << 2), credit_upper_bound); 806 } 807 808 /****************************************************************************** 809 * Description: 810 * Will return the PBF ETS registers to init values.Except 811 * credit_upper_bound. 812 * That isn't used in this configuration (No WFQ is enabled) and will be 813 * configured acording to spec 814 *. 815 ******************************************************************************/ 816 static void elink_ets_e3b0_pbf_disabled(const struct elink_params *params) 817 { 818 struct elink_dev *cb = params->cb; 819 const u8 port = params->port; 820 const u32 min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL; 821 u8 i = 0; 822 u32 base_weight = 0; 823 u8 max_cos = 0; 824 825 /* Mapping between entry priority to client number 0 - COS0 826 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. 827 * TODO_ETS - Should be done by reset value or init tool 828 */ 829 if (port) 830 /* 0x688 (|011|0 10|00 1|000) */ 831 REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); 832 else 833 /* (10 1|100 |011|0 10|00 1|000) */ 834 REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); 835 836 /* TODO_ETS - Should be done by reset value or init tool */ 837 if (port) 838 /* 0x688 (|011|0 10|00 1|000)*/ 839 REG_WR(cb, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); 840 else 841 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ 842 REG_WR(cb, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); 843 844 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : 845 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); 846 847 848 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 849 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); 850 851 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 852 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); 853 /* In 2 port mode port0 has COS0-5 that can be used for WFQ. 854 * In 4 port mode port1 has COS0-2 that can be used for WFQ. 855 */ 856 if (!port) { 857 base_weight = PBF_REG_COS0_WEIGHT_P0; 858 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 859 } else { 860 base_weight = PBF_REG_COS0_WEIGHT_P1; 861 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1; 862 } 863 864 for (i = 0; i < max_cos; i++) 865 REG_WR(cb, base_weight + (0x4 * i), 0); 866 867 elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 868 } 869 /****************************************************************************** 870 * Description: 871 * E3B0 disable will return basicly the values to init values. 872 *. 873 ******************************************************************************/ 874 static elink_status_t elink_ets_e3b0_disabled(const struct elink_params *params, 875 const struct elink_vars *vars) 876 { 877 struct elink_dev *cb = params->cb; 878 879 if (!CHIP_IS_E3B0(params->chip_id)) { 880 ELINK_DEBUG_P0(cb, 881 "elink_ets_e3b0_disabled the chip isn't E3B0\n"); 882 return ELINK_STATUS_ERROR; 883 } 884 885 elink_ets_e3b0_nig_disabled(params, vars); 886 887 elink_ets_e3b0_pbf_disabled(params); 888 889 return ELINK_STATUS_OK; 890 } 891 892 /****************************************************************************** 893 * Description: 894 * Disable will return basicly the values to init values. 895 * 896 ******************************************************************************/ 897 elink_status_t elink_ets_disabled(struct elink_params *params, 898 struct elink_vars *vars) 899 { 900 struct elink_dev *cb = params->cb; 901 elink_status_t elink_status = ELINK_STATUS_OK; 902 903 if ((CHIP_IS_E2(params->chip_id)) || (CHIP_IS_E3A0(params->chip_id))) 904 elink_ets_e2e3a0_disabled(params); 905 else if (CHIP_IS_E3B0(params->chip_id)) 906 elink_status = elink_ets_e3b0_disabled(params, vars); 907 else { 908 ELINK_DEBUG_P0(cb, "elink_ets_disabled - chip not supported\n"); 909 return ELINK_STATUS_ERROR; 910 } 911 912 return elink_status; 913 } 914 915 /****************************************************************************** 916 * Description 917 * Set the COS mappimg to SP and BW until this point all the COS are not 918 * set as SP or BW. 919 ******************************************************************************/ 920 static elink_status_t elink_ets_e3b0_cli_map(const struct elink_params *params, 921 const struct elink_ets_params *ets_params, 922 const u8 cos_sp_bitmap, 923 const u8 cos_bw_bitmap) 924 { 925 struct elink_dev *cb = params->cb; 926 const u8 port = params->port; 927 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); 928 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap; 929 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; 930 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; 931 932 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : 933 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); 934 935 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 936 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap); 937 938 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 939 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 940 nig_cli_subject2wfq_bitmap); 941 942 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 943 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, 944 pbf_cli_subject2wfq_bitmap); 945 946 return ELINK_STATUS_OK; 947 } 948 949 /****************************************************************************** 950 * Description: 951 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 952 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 953 ******************************************************************************/ 954 static elink_status_t elink_ets_e3b0_set_cos_bw(struct elink_dev *cb, 955 const u8 cos_entry, 956 const u32 min_w_val_nig, 957 const u32 min_w_val_pbf, 958 const u16 total_bw, 959 const u8 bw, 960 const u8 port) 961 { 962 u32 nig_reg_adress_crd_weight = 0; 963 u32 pbf_reg_adress_crd_weight = 0; 964 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ 965 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; 966 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; 967 968 switch (cos_entry) { 969 case 0: 970 nig_reg_adress_crd_weight = 971 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 972 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; 973 pbf_reg_adress_crd_weight = (port) ? 974 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; 975 break; 976 case 1: 977 nig_reg_adress_crd_weight = (port) ? 978 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 979 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; 980 pbf_reg_adress_crd_weight = (port) ? 981 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; 982 break; 983 case 2: 984 nig_reg_adress_crd_weight = (port) ? 985 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 986 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; 987 988 pbf_reg_adress_crd_weight = (port) ? 989 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; 990 break; 991 case 3: 992 if (port) 993 return ELINK_STATUS_ERROR; 994 nig_reg_adress_crd_weight = 995 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; 996 pbf_reg_adress_crd_weight = 997 PBF_REG_COS3_WEIGHT_P0; 998 break; 999 case 4: 1000 if (port) 1001 return ELINK_STATUS_ERROR; 1002 nig_reg_adress_crd_weight = 1003 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; 1004 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0; 1005 break; 1006 case 5: 1007 if (port) 1008 return ELINK_STATUS_ERROR; 1009 nig_reg_adress_crd_weight = 1010 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; 1011 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0; 1012 break; 1013 } 1014 1015 REG_WR(cb, nig_reg_adress_crd_weight, cos_bw_nig); 1016 1017 REG_WR(cb, pbf_reg_adress_crd_weight, cos_bw_pbf); 1018 1019 return ELINK_STATUS_OK; 1020 } 1021 /****************************************************************************** 1022 * Description: 1023 * Calculate the total BW.A value of 0 isn't legal. 1024 * 1025 ******************************************************************************/ 1026 static elink_status_t elink_ets_e3b0_get_total_bw( 1027 const struct elink_params *params, 1028 struct elink_ets_params *ets_params, 1029 u16 *total_bw) 1030 { 1031 struct elink_dev *cb = params->cb; 1032 u8 cos_idx = 0; 1033 u8 is_bw_cos_exist = 0; 1034 1035 *total_bw = 0 ; 1036 /* Calculate total BW requested */ 1037 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { 1038 if (ets_params->cos[cos_idx].state == elink_cos_state_bw) { 1039 is_bw_cos_exist = 1; 1040 if (!ets_params->cos[cos_idx].params.bw_params.bw) { 1041 ELINK_DEBUG_P0(cb, "elink_ets_E3B0_config BW" 1042 "was set to 0\n"); 1043 /* This is to prevent a state when ramrods 1044 * can't be sent 1045 */ 1046 ets_params->cos[cos_idx].params.bw_params.bw 1047 = 1; 1048 } 1049 *total_bw += 1050 ets_params->cos[cos_idx].params.bw_params.bw; 1051 } 1052 } 1053 1054 /* Check total BW is valid */ 1055 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { 1056 if (*total_bw == 0) { 1057 ELINK_DEBUG_P0(cb, 1058 "elink_ets_E3B0_config total BW shouldn't be 0\n"); 1059 return ELINK_STATUS_ERROR; 1060 } 1061 ELINK_DEBUG_P0(cb, 1062 "elink_ets_E3B0_config total BW should be 100\n"); 1063 /* We can handle a case whre the BW isn't 100 this can happen 1064 * if the TC are joined. 1065 */ 1066 } 1067 return ELINK_STATUS_OK; 1068 } 1069 1070 /****************************************************************************** 1071 * Description: 1072 * Invalidate all the sp_pri_to_cos. 1073 * 1074 ******************************************************************************/ 1075 static void elink_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos) 1076 { 1077 u8 pri = 0; 1078 for (pri = 0; pri < ELINK_DCBX_MAX_NUM_COS; pri++) 1079 sp_pri_to_cos[pri] = DCBX_INVALID_COS; 1080 } 1081 /****************************************************************************** 1082 * Description: 1083 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 1084 * according to sp_pri_to_cos. 1085 * 1086 ******************************************************************************/ 1087 static elink_status_t elink_ets_e3b0_sp_pri_to_cos_set(const struct elink_params *params, 1088 u8 *sp_pri_to_cos, const u8 pri, 1089 const u8 cos_entry) 1090 { 1091 struct elink_dev *cb = params->cb; 1092 const u8 port = params->port; 1093 const u8 max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 : 1094 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 1095 1096 if (pri >= max_num_of_cos) { 1097 ELINK_DEBUG_P0(cb, "elink_ets_e3b0_sp_pri_to_cos_set invalid " 1098 "parameter Illegal strict priority\n"); 1099 return ELINK_STATUS_ERROR; 1100 } 1101 1102 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { 1103 ELINK_DEBUG_P0(cb, "elink_ets_e3b0_sp_pri_to_cos_set invalid " 1104 "parameter There can't be two COS's with " 1105 "the same strict pri\n"); 1106 return ELINK_STATUS_ERROR; 1107 } 1108 1109 sp_pri_to_cos[pri] = cos_entry; 1110 return ELINK_STATUS_OK; 1111 1112 } 1113 1114 /****************************************************************************** 1115 * Description: 1116 * Returns the correct value according to COS and priority in 1117 * the sp_pri_cli register. 1118 * 1119 ******************************************************************************/ 1120 static u64 elink_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset, 1121 const u8 pri_set, 1122 const u8 pri_offset, 1123 const u8 entry_size) 1124 { 1125 u64 pri_cli_nig = 0; 1126 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size * 1127 (pri_set + pri_offset)); 1128 1129 return pri_cli_nig; 1130 } 1131 /****************************************************************************** 1132 * Description: 1133 * Returns the correct value according to COS and priority in the 1134 * sp_pri_cli register for NIG. 1135 * 1136 ******************************************************************************/ 1137 static u64 elink_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set) 1138 { 1139 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1140 const u8 nig_cos_offset = 3; 1141 const u8 nig_pri_offset = 3; 1142 1143 return elink_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, 1144 nig_pri_offset, 4); 1145 1146 } 1147 /****************************************************************************** 1148 * Description: 1149 * Returns the correct value according to COS and priority in the 1150 * sp_pri_cli register for PBF. 1151 * 1152 ******************************************************************************/ 1153 static u64 elink_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set) 1154 { 1155 const u8 pbf_cos_offset = 0; 1156 const u8 pbf_pri_offset = 0; 1157 1158 return elink_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, 1159 pbf_pri_offset, 3); 1160 1161 } 1162 1163 /****************************************************************************** 1164 * Description: 1165 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 1166 * according to sp_pri_to_cos.(which COS has higher priority) 1167 * 1168 ******************************************************************************/ 1169 static elink_status_t elink_ets_e3b0_sp_set_pri_cli_reg(const struct elink_params *params, 1170 u8 *sp_pri_to_cos) 1171 { 1172 struct elink_dev *cb = params->cb; 1173 u8 i = 0; 1174 const u8 port = params->port; 1175 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1176 u64 pri_cli_nig = 0x210; 1177 u32 pri_cli_pbf = 0x0; 1178 u8 pri_set = 0; 1179 u8 pri_bitmask = 0; 1180 const u8 max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 : 1181 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 1182 1183 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1; 1184 1185 /* Set all the strict priority first */ 1186 for (i = 0; i < max_num_of_cos; i++) { 1187 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { 1188 if (sp_pri_to_cos[i] >= ELINK_DCBX_MAX_NUM_COS) { 1189 ELINK_DEBUG_P0(cb, 1190 "elink_ets_e3b0_sp_set_pri_cli_reg " 1191 "invalid cos entry\n"); 1192 return ELINK_STATUS_ERROR; 1193 } 1194 1195 pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig( 1196 sp_pri_to_cos[i], pri_set); 1197 1198 pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf( 1199 sp_pri_to_cos[i], pri_set); 1200 pri_bitmask = 1 << sp_pri_to_cos[i]; 1201 /* COS is used remove it from bitmap.*/ 1202 if (!(pri_bitmask & cos_bit_to_set)) { 1203 ELINK_DEBUG_P0(cb, 1204 "elink_ets_e3b0_sp_set_pri_cli_reg " 1205 "invalid There can't be two COS's with" 1206 " the same strict pri\n"); 1207 return ELINK_STATUS_ERROR; 1208 } 1209 cos_bit_to_set &= ~pri_bitmask; 1210 pri_set++; 1211 } 1212 } 1213 1214 /* Set all the Non strict priority i= COS*/ 1215 for (i = 0; i < max_num_of_cos; i++) { 1216 pri_bitmask = 1 << i; 1217 /* Check if COS was already used for SP */ 1218 if (pri_bitmask & cos_bit_to_set) { 1219 /* COS wasn't used for SP */ 1220 pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig( 1221 i, pri_set); 1222 1223 pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf( 1224 i, pri_set); 1225 /* COS is used remove it from bitmap.*/ 1226 cos_bit_to_set &= ~pri_bitmask; 1227 pri_set++; 1228 } 1229 } 1230 1231 if (pri_set != max_num_of_cos) { 1232 ELINK_DEBUG_P0(cb, "elink_ets_e3b0_sp_set_pri_cli_reg not all " 1233 "entries were set\n"); 1234 return ELINK_STATUS_ERROR; 1235 } 1236 1237 if (port) { 1238 /* Only 6 usable clients*/ 1239 REG_WR(cb, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 1240 (u32)pri_cli_nig); 1241 1242 REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); 1243 } else { 1244 /* Only 9 usable clients*/ 1245 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig); 1246 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF); 1247 1248 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 1249 pri_cli_nig_lsb); 1250 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 1251 pri_cli_nig_msb); 1252 1253 REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); 1254 } 1255 return ELINK_STATUS_OK; 1256 } 1257 1258 /****************************************************************************** 1259 * Description: 1260 * Configure the COS to ETS according to BW and SP settings. 1261 ******************************************************************************/ 1262 elink_status_t elink_ets_e3b0_config(const struct elink_params *params, 1263 const struct elink_vars *vars, 1264 struct elink_ets_params *ets_params) 1265 { 1266 struct elink_dev *cb = params->cb; 1267 elink_status_t elink_status = ELINK_STATUS_OK; 1268 const u8 port = params->port; 1269 u16 total_bw = 0; 1270 const u32 min_w_val_nig = elink_ets_get_min_w_val_nig(vars); 1271 const u32 min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL; 1272 u8 cos_bw_bitmap = 0; 1273 u8 cos_sp_bitmap = 0; 1274 u8 sp_pri_to_cos[ELINK_DCBX_MAX_NUM_COS] = {0}; 1275 const u8 max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 : 1276 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 1277 u8 cos_entry = 0; 1278 1279 if (!CHIP_IS_E3B0(params->chip_id)) { 1280 ELINK_DEBUG_P0(cb, 1281 "elink_ets_e3b0_disabled the chip isn't E3B0\n"); 1282 return ELINK_STATUS_ERROR; 1283 } 1284 1285 if ((ets_params->num_of_cos > max_num_of_cos)) { 1286 ELINK_DEBUG_P0(cb, "elink_ets_E3B0_config the number of COS " 1287 "isn't supported\n"); 1288 return ELINK_STATUS_ERROR; 1289 } 1290 1291 /* Prepare sp strict priority parameters*/ 1292 elink_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); 1293 1294 /* Prepare BW parameters*/ 1295 elink_status = elink_ets_e3b0_get_total_bw(params, ets_params, 1296 &total_bw); 1297 if (elink_status != ELINK_STATUS_OK) { 1298 ELINK_DEBUG_P0(cb, 1299 "elink_ets_E3B0_config get_total_bw failed\n"); 1300 return ELINK_STATUS_ERROR; 1301 } 1302 1303 /* Upper bound is set according to current link speed (min_w_val 1304 * should be the same for upper bound and COS credit val). 1305 */ 1306 elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); 1307 elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 1308 1309 1310 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { 1311 if (elink_cos_state_bw == ets_params->cos[cos_entry].state) { 1312 cos_bw_bitmap |= (1 << cos_entry); 1313 /* The function also sets the BW in HW(not the mappin 1314 * yet) 1315 */ 1316 elink_status = elink_ets_e3b0_set_cos_bw( 1317 cb, cos_entry, min_w_val_nig, min_w_val_pbf, 1318 total_bw, 1319 ets_params->cos[cos_entry].params.bw_params.bw, 1320 port); 1321 } else if (elink_cos_state_strict == 1322 ets_params->cos[cos_entry].state){ 1323 cos_sp_bitmap |= (1 << cos_entry); 1324 1325 elink_status = elink_ets_e3b0_sp_pri_to_cos_set( 1326 params, 1327 sp_pri_to_cos, 1328 ets_params->cos[cos_entry].params.sp_params.pri, 1329 cos_entry); 1330 1331 } else { 1332 ELINK_DEBUG_P0(cb, 1333 "elink_ets_e3b0_config cos state not valid\n"); 1334 return ELINK_STATUS_ERROR; 1335 } 1336 if (elink_status != ELINK_STATUS_OK) { 1337 ELINK_DEBUG_P0(cb, 1338 "elink_ets_e3b0_config set cos bw failed\n"); 1339 return elink_status; 1340 } 1341 } 1342 1343 /* Set SP register (which COS has higher priority) */ 1344 elink_status = elink_ets_e3b0_sp_set_pri_cli_reg(params, 1345 sp_pri_to_cos); 1346 1347 if (elink_status != ELINK_STATUS_OK) { 1348 ELINK_DEBUG_P0(cb, 1349 "elink_ets_E3B0_config set_pri_cli_reg failed\n"); 1350 return elink_status; 1351 } 1352 1353 /* Set client mapping of BW and strict */ 1354 elink_status = elink_ets_e3b0_cli_map(params, ets_params, 1355 cos_sp_bitmap, 1356 cos_bw_bitmap); 1357 1358 if (elink_status != ELINK_STATUS_OK) { 1359 ELINK_DEBUG_P0(cb, "elink_ets_E3B0_config SP failed\n"); 1360 return elink_status; 1361 } 1362 return ELINK_STATUS_OK; 1363 } 1364 static void elink_ets_bw_limit_common(const struct elink_params *params) 1365 { 1366 /* ETS disabled configuration */ 1367 struct elink_dev *cb = params->cb; 1368 ELINK_DEBUG_P0(cb, "ETS enabled BW limit configuration\n"); 1369 /* Defines which entries (clients) are subjected to WFQ arbitration 1370 * COS0 0x8 1371 * COS1 0x10 1372 */ 1373 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); 1374 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual 1375 * client numbers (WEIGHT_0 does not actually have to represent 1376 * client 0) 1377 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1378 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 1379 */ 1380 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); 1381 1382 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 1383 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1384 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 1385 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1386 1387 /* ETS mode enabled*/ 1388 REG_WR(cb, PBF_REG_ETS_ENABLED, 1); 1389 1390 /* Defines the number of consecutive slots for the strict priority */ 1391 REG_WR(cb, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 1392 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1393 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 1394 * entry, 4 - COS1 entry. 1395 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1396 * bit4 bit3 bit2 bit1 bit0 1397 * MCP and debug are strict 1398 */ 1399 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 1400 1401 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ 1402 REG_WR(cb, PBF_REG_COS0_UPPER_BOUND, 1403 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1404 REG_WR(cb, PBF_REG_COS1_UPPER_BOUND, 1405 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1406 } 1407 1408 void elink_ets_bw_limit(const struct elink_params *params, const u32 cos0_bw, 1409 const u32 cos1_bw) 1410 { 1411 /* ETS disabled configuration*/ 1412 struct elink_dev *cb = params->cb; 1413 const u32 total_bw = cos0_bw + cos1_bw; 1414 u32 cos0_credit_weight = 0; 1415 u32 cos1_credit_weight = 0; 1416 1417 ELINK_DEBUG_P0(cb, "ETS enabled BW limit configuration\n"); 1418 1419 if ((!total_bw) || 1420 (!cos0_bw) || 1421 (!cos1_bw)) { 1422 ELINK_DEBUG_P0(cb, "Total BW can't be zero\n"); 1423 return; 1424 } 1425 1426 cos0_credit_weight = (cos0_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1427 total_bw; 1428 cos1_credit_weight = (cos1_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1429 total_bw; 1430 1431 elink_ets_bw_limit_common(params); 1432 1433 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); 1434 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); 1435 1436 REG_WR(cb, PBF_REG_COS0_WEIGHT, cos0_credit_weight); 1437 REG_WR(cb, PBF_REG_COS1_WEIGHT, cos1_credit_weight); 1438 } 1439 1440 elink_status_t elink_ets_strict(const struct elink_params *params, const u8 strict_cos) 1441 { 1442 /* ETS disabled configuration*/ 1443 struct elink_dev *cb = params->cb; 1444 u32 val = 0; 1445 1446 ELINK_DEBUG_P0(cb, "ETS enabled strict configuration\n"); 1447 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1448 * as strict. Bits 0,1,2 - debug and management entries, 1449 * 3 - COS0 entry, 4 - COS1 entry. 1450 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1451 * bit4 bit3 bit2 bit1 bit0 1452 * MCP and debug are strict 1453 */ 1454 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); 1455 /* For strict priority entries defines the number of consecutive slots 1456 * for the highest priority. 1457 */ 1458 REG_WR(cb, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 1459 /* ETS mode disable */ 1460 REG_WR(cb, PBF_REG_ETS_ENABLED, 0); 1461 /* Defines the number of consecutive slots for the strict priority */ 1462 REG_WR(cb, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); 1463 1464 /* Defines the number of consecutive slots for the strict priority */ 1465 REG_WR(cb, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); 1466 1467 /* Mapping between entry priority to client number (0,1,2 -debug and 1468 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 1469 * 3bits client num. 1470 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1471 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 1472 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 1473 */ 1474 val = (!strict_cos) ? 0x2318 : 0x22E0; 1475 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); 1476 1477 return ELINK_STATUS_OK; 1478 } 1479 #endif /* ELINK_ENHANCEMENTS */ 1480 1481 /******************************************************************/ 1482 /* PFC section */ 1483 /******************************************************************/ 1484 #ifndef EXCLUDE_NON_COMMON_INIT 1485 #ifndef EXCLUDE_WARPCORE 1486 static void elink_update_pfc_xmac(struct elink_params *params, 1487 struct elink_vars *vars, 1488 u8 is_lb) 1489 { 1490 struct elink_dev *cb = params->cb; 1491 u32 xmac_base; 1492 u32 pause_val, pfc0_val, pfc1_val; 1493 1494 /* XMAC base adrr */ 1495 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1496 1497 /* Initialize pause and pfc registers */ 1498 pause_val = 0x18000; 1499 pfc0_val = 0xFFFF8000; 1500 pfc1_val = 0x2; 1501 1502 /* No PFC support */ 1503 if (!(params->feature_config_flags & 1504 ELINK_FEATURE_CONFIG_PFC_ENABLED)) { 1505 1506 /* RX flow control - Process pause frame in receive direction 1507 */ 1508 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) 1509 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; 1510 1511 /* TX flow control - Send pause packet when buffer is full */ 1512 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) 1513 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; 1514 } else {/* PFC support */ 1515 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | 1516 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | 1517 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | 1518 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | 1519 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1520 /* Write pause and PFC registers */ 1521 REG_WR(cb, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1522 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1523 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1524 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1525 1526 } 1527 1528 /* Write pause and PFC registers */ 1529 REG_WR(cb, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1530 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1531 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1532 1533 1534 /* Set MAC address for source TX Pause/PFC frames */ 1535 REG_WR(cb, xmac_base + XMAC_REG_CTRL_SA_LO, 1536 ((params->mac_addr[2] << 24) | 1537 (params->mac_addr[3] << 16) | 1538 (params->mac_addr[4] << 8) | 1539 (params->mac_addr[5]))); 1540 REG_WR(cb, xmac_base + XMAC_REG_CTRL_SA_HI, 1541 ((params->mac_addr[0] << 8) | 1542 (params->mac_addr[1]))); 1543 1544 USLEEP(cb, 30); 1545 } 1546 1547 #endif // EXCLUDE_WARPCORE 1548 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 1549 #ifdef ELINK_ENHANCEMENTS 1550 #ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */ 1551 static void elink_emac_get_pfc_stat(struct elink_params *params, 1552 u32 pfc_frames_sent[2], 1553 u32 pfc_frames_received[2]) 1554 { 1555 /* Read pfc statistic */ 1556 struct elink_dev *cb = params->cb; 1557 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1558 u32 val_xon = 0; 1559 u32 val_xoff = 0; 1560 1561 ELINK_DEBUG_P0(cb, "pfc statistic read from EMAC\n"); 1562 1563 /* PFC received frames */ 1564 val_xoff = REG_RD(cb, emac_base + 1565 EMAC_REG_RX_PFC_STATS_XOFF_RCVD); 1566 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT; 1567 val_xon = REG_RD(cb, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD); 1568 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT; 1569 1570 pfc_frames_received[0] = val_xon + val_xoff; 1571 1572 /* PFC received sent */ 1573 val_xoff = REG_RD(cb, emac_base + 1574 EMAC_REG_RX_PFC_STATS_XOFF_SENT); 1575 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT; 1576 val_xon = REG_RD(cb, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT); 1577 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT; 1578 1579 pfc_frames_sent[0] = val_xon + val_xoff; 1580 } 1581 1582 /* Read pfc statistic*/ 1583 void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars, 1584 u32 pfc_frames_sent[2], 1585 u32 pfc_frames_received[2]) 1586 { 1587 /* Read pfc statistic */ 1588 struct elink_dev *cb = params->cb; 1589 1590 ELINK_DEBUG_P0(cb, "pfc statistic\n"); 1591 1592 if (!vars->link_up) 1593 return; 1594 1595 if (vars->mac_type == ELINK_MAC_TYPE_EMAC) { 1596 ELINK_DEBUG_P0(cb, "About to read PFC stats from EMAC\n"); 1597 elink_emac_get_pfc_stat(params, pfc_frames_sent, 1598 pfc_frames_received); 1599 } 1600 } 1601 #endif /* ! BNX2X_UPSTREAM */ 1602 #endif /* ELINK_ENHANCEMENTS */ 1603 /******************************************************************/ 1604 /* MAC/PBF section */ 1605 /******************************************************************/ 1606 static void elink_set_mdio_clk(struct elink_dev *cb, u32 chip_id, 1607 u32 emac_base) 1608 { 1609 u32 new_mode, cur_mode; 1610 u32 clc_cnt; 1611 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz 1612 * (a value of 49==0x31) and make sure that the AUTO poll is off 1613 */ 1614 cur_mode = REG_RD(cb, emac_base + EMAC_REG_EMAC_MDIO_MODE); 1615 1616 if (ELINK_USES_WARPCORE(chip_id)) 1617 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 1618 else 1619 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 1620 1621 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) && 1622 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45))) 1623 return; 1624 1625 new_mode = cur_mode & 1626 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); 1627 new_mode |= clc_cnt; 1628 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45); 1629 1630 ELINK_DEBUG_P2(cb, "Changing emac_mode from 0x%x to 0x%x\n", 1631 cur_mode, new_mode); 1632 REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); 1633 USLEEP(cb, 40); 1634 } 1635 1636 #ifndef EXCLUDE_WARPCORE 1637 static u8 elink_is_4_port_mode(struct elink_dev *cb) 1638 { 1639 u32 port4mode_ovwr_val; 1640 /* Check 4-port override enabled */ 1641 port4mode_ovwr_val = REG_RD(cb, MISC_REG_PORT4MODE_EN_OVWR); 1642 if (port4mode_ovwr_val & (1<<0)) { 1643 /* Return 4-port mode override value */ 1644 return ((port4mode_ovwr_val & (1<<1)) == (1<<1)); 1645 } 1646 /* Return 4-port mode from input pin */ 1647 return (u8)REG_RD(cb, MISC_REG_PORT4MODE_EN); 1648 } 1649 #endif 1650 1651 #ifndef EXCLUDE_NON_COMMON_INIT 1652 static void elink_set_mdio_emac_per_phy(struct elink_dev *cb, 1653 struct elink_params *params) 1654 { 1655 u8 phy_index; 1656 1657 /* Set mdio clock per phy */ 1658 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; 1659 phy_index++) 1660 elink_set_mdio_clk(cb, params->chip_id, 1661 params->phy[phy_index].mdio_ctrl); 1662 } 1663 1664 static void elink_emac_init(struct elink_params *params, 1665 struct elink_vars *vars) 1666 { 1667 /* reset and unreset the emac core */ 1668 struct elink_dev *cb = params->cb; 1669 u8 port = params->port; 1670 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1671 u32 val; 1672 u16 timeout; 1673 1674 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1675 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1676 USLEEP(cb, 5); 1677 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1678 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1679 1680 /* init emac - use read-modify-write */ 1681 /* self clear reset */ 1682 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE); 1683 EMAC_WR(cb, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); 1684 1685 timeout = 200; 1686 do { 1687 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE); 1688 ELINK_DEBUG_P1(cb, "EMAC reset reg is %u\n", val); 1689 if (!timeout) { 1690 ELINK_DEBUG_P0(cb, "EMAC timeout!\n"); 1691 return; 1692 } 1693 timeout--; 1694 } while (val & EMAC_MODE_RESET); 1695 1696 elink_set_mdio_emac_per_phy(cb, params); 1697 /* Set mac address */ 1698 val = ((params->mac_addr[0] << 8) | 1699 params->mac_addr[1]); 1700 EMAC_WR(cb, EMAC_REG_EMAC_MAC_MATCH, val); 1701 1702 val = ((params->mac_addr[2] << 24) | 1703 (params->mac_addr[3] << 16) | 1704 (params->mac_addr[4] << 8) | 1705 params->mac_addr[5]); 1706 EMAC_WR(cb, EMAC_REG_EMAC_MAC_MATCH + 4, val); 1707 } 1708 1709 #ifndef EXCLUDE_WARPCORE 1710 static void elink_set_xumac_nig(struct elink_params *params, 1711 u16 tx_pause_en, 1712 u8 enable) 1713 { 1714 struct elink_dev *cb = params->cb; 1715 1716 REG_WR(cb, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, 1717 enable); 1718 REG_WR(cb, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, 1719 enable); 1720 REG_WR(cb, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : 1721 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); 1722 } 1723 1724 static void elink_set_umac_rxtx(struct elink_params *params, u8 en) 1725 { 1726 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1727 u32 val; 1728 struct elink_dev *cb = params->cb; 1729 if (!(REG_RD(cb, MISC_REG_RESET_REG_2) & 1730 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) 1731 return; 1732 val = REG_RD(cb, umac_base + UMAC_REG_COMMAND_CONFIG); 1733 if (en) 1734 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA | 1735 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1736 else 1737 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA | 1738 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1739 /* Disable RX and TX */ 1740 REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1741 } 1742 1743 static void elink_umac_enable(struct elink_params *params, 1744 struct elink_vars *vars, u8 lb) 1745 { 1746 u32 val; 1747 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1748 struct elink_dev *cb = params->cb; 1749 /* Reset UMAC */ 1750 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1751 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1752 MSLEEP(cb, 1); 1753 1754 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1755 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1756 1757 ELINK_DEBUG_P0(cb, "enabling UMAC\n"); 1758 1759 /* This register opens the gate for the UMAC despite its name */ 1760 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 1761 1762 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | 1763 UMAC_COMMAND_CONFIG_REG_PAD_EN | 1764 UMAC_COMMAND_CONFIG_REG_SW_RESET | 1765 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; 1766 switch (vars->line_speed) { 1767 case ELINK_SPEED_10: 1768 val |= (0<<2); 1769 break; 1770 case ELINK_SPEED_100: 1771 val |= (1<<2); 1772 break; 1773 case ELINK_SPEED_1000: 1774 val |= (2<<2); 1775 break; 1776 case ELINK_SPEED_2500: 1777 val |= (3<<2); 1778 break; 1779 default: 1780 ELINK_DEBUG_P1(cb, "Invalid speed for UMAC %d\n", 1781 vars->line_speed); 1782 break; 1783 } 1784 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 1785 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; 1786 1787 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) 1788 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; 1789 1790 if (vars->duplex == DUPLEX_HALF) 1791 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; 1792 1793 REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1794 USLEEP(cb, 50); 1795 1796 /* Configure UMAC for EEE */ 1797 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1798 ELINK_DEBUG_P0(cb, "configured UMAC for EEE\n"); 1799 REG_WR(cb, umac_base + UMAC_REG_UMAC_EEE_CTRL, 1800 UMAC_UMAC_EEE_CTRL_REG_EEE_EN); 1801 REG_WR(cb, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); 1802 } else { 1803 REG_WR(cb, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); 1804 } 1805 1806 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ 1807 REG_WR(cb, umac_base + UMAC_REG_MAC_ADDR0, 1808 ((params->mac_addr[2] << 24) | 1809 (params->mac_addr[3] << 16) | 1810 (params->mac_addr[4] << 8) | 1811 (params->mac_addr[5]))); 1812 REG_WR(cb, umac_base + UMAC_REG_MAC_ADDR1, 1813 ((params->mac_addr[0] << 8) | 1814 (params->mac_addr[1]))); 1815 1816 /* Enable RX and TX */ 1817 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; 1818 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | 1819 UMAC_COMMAND_CONFIG_REG_RX_ENA; 1820 REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1821 USLEEP(cb, 50); 1822 1823 /* Remove SW Reset */ 1824 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; 1825 1826 /* Check loopback mode */ 1827 if (lb) 1828 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; 1829 REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1830 1831 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 1832 * length used by the MAC receive logic to check frames. 1833 */ 1834 REG_WR(cb, umac_base + UMAC_REG_MAXFR, 0x2710); 1835 elink_set_xumac_nig(params, 1836 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1); 1837 vars->mac_type = ELINK_MAC_TYPE_UMAC; 1838 1839 } 1840 1841 /* Define the XMAC mode */ 1842 static void elink_xmac_init(struct elink_params *params, u32 max_speed) 1843 { 1844 struct elink_dev *cb = params->cb; 1845 u32 is_port4mode = elink_is_4_port_mode(cb); 1846 1847 /* In 4-port mode, need to set the mode only once, so if XMAC is 1848 * already out of reset, it means the mode has already been set, 1849 * and it must not* reset the XMAC again, since it controls both 1850 * ports of the path 1851 */ 1852 1853 if (((CHIP_NUM(params->chip_id) == CHIP_NUM_57840_4_10) || 1854 (CHIP_NUM(params->chip_id) == CHIP_NUM_57840_2_20) || 1855 (CHIP_NUM(params->chip_id) == CHIP_NUM_57840_OBSOLETE)) && 1856 is_port4mode && 1857 (REG_RD(cb, MISC_REG_RESET_REG_2) & 1858 MISC_REGISTERS_RESET_REG_2_XMAC)) { 1859 ELINK_DEBUG_P0(cb, 1860 "XMAC already out of reset in 4-port mode\n"); 1861 return; 1862 } 1863 1864 /* Hard reset */ 1865 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1866 MISC_REGISTERS_RESET_REG_2_XMAC); 1867 MSLEEP(cb, 1); 1868 1869 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1870 MISC_REGISTERS_RESET_REG_2_XMAC); 1871 if (is_port4mode) { 1872 ELINK_DEBUG_P0(cb, "Init XMAC to 2 ports x 10G per path\n"); 1873 1874 /* Set the number of ports on the system side to up to 2 */ 1875 REG_WR(cb, MISC_REG_XMAC_CORE_PORT_MODE, 1); 1876 1877 /* Set the number of ports on the Warp Core to 10G */ 1878 REG_WR(cb, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1879 } else { 1880 /* Set the number of ports on the system side to 1 */ 1881 REG_WR(cb, MISC_REG_XMAC_CORE_PORT_MODE, 0); 1882 if (max_speed == ELINK_SPEED_10000) { 1883 ELINK_DEBUG_P0(cb, 1884 "Init XMAC to 10G x 1 port per path\n"); 1885 /* Set the number of ports on the Warp Core to 10G */ 1886 REG_WR(cb, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1887 } else { 1888 ELINK_DEBUG_P0(cb, 1889 "Init XMAC to 20G x 2 ports per path\n"); 1890 /* Set the number of ports on the Warp Core to 20G */ 1891 REG_WR(cb, MISC_REG_XMAC_PHY_PORT_MODE, 1); 1892 } 1893 } 1894 /* Soft reset */ 1895 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1896 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1897 MSLEEP(cb, 1); 1898 1899 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1900 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1901 1902 } 1903 1904 static void elink_set_xmac_rxtx(struct elink_params *params, u8 en) 1905 { 1906 u8 port = params->port; 1907 struct elink_dev *cb = params->cb; 1908 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1909 u32 val; 1910 1911 if (REG_RD(cb, MISC_REG_RESET_REG_2) & 1912 MISC_REGISTERS_RESET_REG_2_XMAC) { 1913 /* Send an indication to change the state in the NIG back to XON 1914 * Clearing this bit enables the next set of this bit to get 1915 * rising edge 1916 */ 1917 pfc_ctrl = REG_RD(cb, xmac_base + XMAC_REG_PFC_CTRL_HI); 1918 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI, 1919 (pfc_ctrl & ~(1<<1))); 1920 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI, 1921 (pfc_ctrl | (1<<1))); 1922 ELINK_DEBUG_P1(cb, "Disable XMAC on port %x\n", port); 1923 val = REG_RD(cb, xmac_base + XMAC_REG_CTRL); 1924 if (en) 1925 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1926 else 1927 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1928 REG_WR(cb, xmac_base + XMAC_REG_CTRL, val); 1929 } 1930 } 1931 1932 static elink_status_t elink_xmac_enable(struct elink_params *params, 1933 struct elink_vars *vars, u8 lb) 1934 { 1935 u32 val, xmac_base; 1936 struct elink_dev *cb = params->cb; 1937 ELINK_DEBUG_P0(cb, "enabling XMAC\n"); 1938 1939 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1940 1941 elink_xmac_init(params, vars->line_speed); 1942 1943 /* This register determines on which events the MAC will assert 1944 * error on the i/f to the NIG along w/ EOP. 1945 */ 1946 1947 /* This register tells the NIG whether to send traffic to UMAC 1948 * or XMAC 1949 */ 1950 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); 1951 1952 /* When XMAC is in XLGMII mode, disable sending idles for fault 1953 * detection. 1954 */ 1955 if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) { 1956 REG_WR(cb, xmac_base + XMAC_REG_RX_LSS_CTRL, 1957 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE | 1958 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE)); 1959 REG_WR(cb, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 1960 REG_WR(cb, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 1961 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 1962 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 1963 } 1964 /* Set Max packet size */ 1965 REG_WR(cb, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); 1966 1967 /* CRC append for Tx packets */ 1968 REG_WR(cb, xmac_base + XMAC_REG_TX_CTRL, 0xC800); 1969 1970 /* update PFC */ 1971 elink_update_pfc_xmac(params, vars, 0); 1972 1973 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1974 ELINK_DEBUG_P0(cb, "Setting XMAC for EEE\n"); 1975 REG_WR(cb, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); 1976 REG_WR(cb, xmac_base + XMAC_REG_EEE_CTRL, 0x1); 1977 } else { 1978 REG_WR(cb, xmac_base + XMAC_REG_EEE_CTRL, 0x0); 1979 } 1980 1981 /* Enable TX and RX */ 1982 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; 1983 1984 /* Set MAC in XLGMII mode for dual-mode */ 1985 if ((vars->line_speed == ELINK_SPEED_20000) && 1986 (params->phy[ELINK_INT_PHY].supported & 1987 ELINK_SUPPORTED_20000baseKR2_Full)) 1988 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB; 1989 1990 /* Check loopback mode */ 1991 if (lb) 1992 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; 1993 REG_WR(cb, xmac_base + XMAC_REG_CTRL, val); 1994 elink_set_xumac_nig(params, 1995 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1); 1996 1997 vars->mac_type = ELINK_MAC_TYPE_XMAC; 1998 1999 return ELINK_STATUS_OK; 2000 } 2001 #endif // EXCLUDE_WARPCORE 2002 2003 #ifndef EXCLUDE_EMAC 2004 static elink_status_t elink_emac_enable(struct elink_params *params, 2005 struct elink_vars *vars, u8 lb) 2006 { 2007 struct elink_dev *cb = params->cb; 2008 u8 port = params->port; 2009 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 2010 u32 val; 2011 2012 ELINK_DEBUG_P0(cb, "enabling EMAC\n"); 2013 2014 /* Disable BMAC */ 2015 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2016 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2017 2018 /* enable emac and not bmac */ 2019 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); 2020 2021 #ifdef ELINK_INCLUDE_EMUL 2022 /* for paladium */ 2023 if (CHIP_REV_IS_EMUL(params->chip_id)) { 2024 /* Use lane 1 (of lanes 0-3) */ 2025 REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1); 2026 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 2027 } 2028 /* for fpga */ 2029 else 2030 #endif 2031 #ifdef ELINK_INCLUDE_FPGA 2032 if (CHIP_REV_IS_FPGA(params->chip_id)) { 2033 /* Use lane 1 (of lanes 0-3) */ 2034 ELINK_DEBUG_P0(cb, "elink_emac_enable: Setting FPGA\n"); 2035 2036 REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1); 2037 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); 2038 } else 2039 #endif 2040 /* ASIC */ 2041 if (vars->phy_flags & PHY_XGXS_FLAG) { 2042 u32 ser_lane = ((params->lane_config & 2043 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 2044 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 2045 2046 ELINK_DEBUG_P0(cb, "XGXS\n"); 2047 /* select the master lanes (out of 0-3) */ 2048 REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); 2049 /* select XGXS */ 2050 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 2051 2052 } else { /* SerDes */ 2053 ELINK_DEBUG_P0(cb, "SerDes\n"); 2054 /* select SerDes */ 2055 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); 2056 } 2057 2058 elink_bits_en(cb, emac_base + EMAC_REG_EMAC_RX_MODE, 2059 EMAC_RX_MODE_RESET); 2060 elink_bits_en(cb, emac_base + EMAC_REG_EMAC_TX_MODE, 2061 EMAC_TX_MODE_RESET); 2062 2063 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) 2064 if (CHIP_REV_IS_SLOW(params->chip_id)) { 2065 /* config GMII mode */ 2066 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE); 2067 EMAC_WR(cb, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII)); 2068 } else { /* ASIC */ 2069 #endif /* defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)*/ 2070 /* pause enable/disable */ 2071 elink_bits_dis(cb, emac_base + EMAC_REG_EMAC_RX_MODE, 2072 EMAC_RX_MODE_FLOW_EN); 2073 2074 elink_bits_dis(cb, emac_base + EMAC_REG_EMAC_TX_MODE, 2075 (EMAC_TX_MODE_EXT_PAUSE_EN | 2076 EMAC_TX_MODE_FLOW_EN)); 2077 if (!(params->feature_config_flags & 2078 ELINK_FEATURE_CONFIG_PFC_ENABLED)) { 2079 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) 2080 elink_bits_en(cb, emac_base + 2081 EMAC_REG_EMAC_RX_MODE, 2082 EMAC_RX_MODE_FLOW_EN); 2083 2084 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) 2085 elink_bits_en(cb, emac_base + 2086 EMAC_REG_EMAC_TX_MODE, 2087 (EMAC_TX_MODE_EXT_PAUSE_EN | 2088 EMAC_TX_MODE_FLOW_EN)); 2089 } else 2090 elink_bits_en(cb, emac_base + EMAC_REG_EMAC_TX_MODE, 2091 EMAC_TX_MODE_FLOW_EN); 2092 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) 2093 } 2094 #endif /* defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) */ 2095 2096 /* KEEP_VLAN_TAG, promiscuous */ 2097 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_RX_MODE); 2098 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; 2099 2100 /* Setting this bit causes MAC control frames (except for pause 2101 * frames) to be passed on for processing. This setting has no 2102 * affect on the operation of the pause frames. This bit effects 2103 * all packets regardless of RX Parser packet sorting logic. 2104 * Turn the PFC off to make sure we are in Xon state before 2105 * enabling it. 2106 */ 2107 EMAC_WR(cb, EMAC_REG_RX_PFC_MODE, 0); 2108 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) { 2109 ELINK_DEBUG_P0(cb, "PFC is enabled\n"); 2110 /* Enable PFC again */ 2111 EMAC_WR(cb, EMAC_REG_RX_PFC_MODE, 2112 EMAC_REG_RX_PFC_MODE_RX_EN | 2113 EMAC_REG_RX_PFC_MODE_TX_EN | 2114 EMAC_REG_RX_PFC_MODE_PRIORITIES); 2115 2116 EMAC_WR(cb, EMAC_REG_RX_PFC_PARAM, 2117 ((0x0101 << 2118 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | 2119 (0x00ff << 2120 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); 2121 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; 2122 } 2123 EMAC_WR(cb, EMAC_REG_EMAC_RX_MODE, val); 2124 2125 /* Set Loopback */ 2126 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE); 2127 if (lb) 2128 val |= 0x810; 2129 else 2130 val &= ~0x810; 2131 EMAC_WR(cb, EMAC_REG_EMAC_MODE, val); 2132 2133 /* Enable emac */ 2134 REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 1); 2135 2136 #ifndef ELINK_AUX_POWER 2137 /* Enable emac for jumbo packets */ 2138 EMAC_WR(cb, EMAC_REG_EMAC_RX_MTU_SIZE, 2139 (EMAC_RX_MTU_SIZE_JUMBO_ENA | 2140 (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD))); 2141 #endif 2142 2143 /* Strip CRC */ 2144 REG_WR(cb, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); 2145 2146 /* Disable the NIG in/out to the bmac */ 2147 REG_WR(cb, NIG_REG_BMAC0_IN_EN + port*4, 0x0); 2148 REG_WR(cb, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); 2149 REG_WR(cb, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); 2150 2151 /* Enable the NIG in/out to the emac */ 2152 REG_WR(cb, NIG_REG_EMAC0_IN_EN + port*4, 0x1); 2153 val = 0; 2154 if ((params->feature_config_flags & 2155 ELINK_FEATURE_CONFIG_PFC_ENABLED) || 2156 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2157 val = 1; 2158 2159 REG_WR(cb, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); 2160 REG_WR(cb, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); 2161 2162 #ifdef ELINK_INCLUDE_EMUL 2163 if (CHIP_REV_IS_EMUL(params->chip_id)) { 2164 /* Take the BigMac out of reset */ 2165 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2166 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2167 2168 /* Enable access for bmac registers */ 2169 REG_WR(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 2170 } else 2171 #endif /* ELINK_INCLUDE_EMUL */ 2172 REG_WR(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); 2173 2174 vars->mac_type = ELINK_MAC_TYPE_EMAC; 2175 return ELINK_STATUS_OK; 2176 } 2177 2178 #endif //EXCLUDE_EMAC 2179 #ifndef EXCLUDE_BMAC1 2180 static void elink_update_pfc_bmac1(struct elink_params *params, 2181 struct elink_vars *vars) 2182 { 2183 u32 wb_data[2]; 2184 struct elink_dev *cb = params->cb; 2185 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 2186 NIG_REG_INGRESS_BMAC0_MEM; 2187 2188 u32 val = 0x14; 2189 if ((!(params->feature_config_flags & 2190 ELINK_FEATURE_CONFIG_PFC_ENABLED)) && 2191 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) 2192 /* Enable BigMAC to react on received Pause packets */ 2193 val |= (1<<5); 2194 wb_data[0] = val; 2195 wb_data[1] = 0; 2196 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); 2197 2198 /* TX control */ 2199 val = 0xc0; 2200 if (!(params->feature_config_flags & 2201 ELINK_FEATURE_CONFIG_PFC_ENABLED) && 2202 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2203 val |= 0x800000; 2204 wb_data[0] = val; 2205 wb_data[1] = 0; 2206 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); 2207 } 2208 #endif // EXCLUDE_BMAC1 2209 2210 #ifndef EXCLUDE_BMAC2 2211 static void elink_update_pfc_bmac2(struct elink_params *params, 2212 struct elink_vars *vars, 2213 u8 is_lb) 2214 { 2215 /* Set rx control: Strip CRC and enable BigMAC to relay 2216 * control packets to the system as well 2217 */ 2218 u32 wb_data[2]; 2219 struct elink_dev *cb = params->cb; 2220 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 2221 NIG_REG_INGRESS_BMAC0_MEM; 2222 u32 val = 0x14; 2223 2224 if ((!(params->feature_config_flags & 2225 ELINK_FEATURE_CONFIG_PFC_ENABLED)) && 2226 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) 2227 /* Enable BigMAC to react on received Pause packets */ 2228 val |= (1<<5); 2229 wb_data[0] = val; 2230 wb_data[1] = 0; 2231 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); 2232 USLEEP(cb, 30); 2233 2234 /* Tx control */ 2235 val = 0xc0; 2236 if (!(params->feature_config_flags & 2237 ELINK_FEATURE_CONFIG_PFC_ENABLED) && 2238 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2239 val |= 0x800000; 2240 wb_data[0] = val; 2241 wb_data[1] = 0; 2242 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); 2243 2244 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) { 2245 ELINK_DEBUG_P0(cb, "PFC is enabled\n"); 2246 /* Enable PFC RX & TX & STATS and set 8 COS */ 2247 wb_data[0] = 0x0; 2248 wb_data[0] |= (1<<0); /* RX */ 2249 wb_data[0] |= (1<<1); /* TX */ 2250 wb_data[0] |= (1<<2); /* Force initial Xon */ 2251 wb_data[0] |= (1<<3); /* 8 cos */ 2252 wb_data[0] |= (1<<5); /* STATS */ 2253 wb_data[1] = 0; 2254 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, 2255 wb_data, 2); 2256 /* Clear the force Xon */ 2257 wb_data[0] &= ~(1<<2); 2258 } else { 2259 ELINK_DEBUG_P0(cb, "PFC is disabled\n"); 2260 /* Disable PFC RX & TX & STATS and set 8 COS */ 2261 wb_data[0] = 0x8; 2262 wb_data[1] = 0; 2263 } 2264 2265 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); 2266 2267 /* Set Time (based unit is 512 bit time) between automatic 2268 * re-sending of PP packets amd enable automatic re-send of 2269 * Per-Priroity Packet as long as pp_gen is asserted and 2270 * pp_disable is low. 2271 */ 2272 val = 0x8000; 2273 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 2274 val |= (1<<16); /* enable automatic re-send */ 2275 2276 wb_data[0] = val; 2277 wb_data[1] = 0; 2278 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, 2279 wb_data, 2); 2280 2281 /* mac control */ 2282 val = 0x3; /* Enable RX and TX */ 2283 if (is_lb) { 2284 val |= 0x4; /* Local loopback */ 2285 ELINK_DEBUG_P0(cb, "enable bmac loopback\n"); 2286 } 2287 /* When PFC enabled, Pass pause frames towards the NIG. */ 2288 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 2289 val |= ((1<<6)|(1<<5)); 2290 2291 wb_data[0] = val; 2292 wb_data[1] = 0; 2293 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2294 } 2295 #endif // EXCLUDE_BMAC2 2296 #endif // EXCLUDE_NON_COMMON_INIT 2297 #ifdef ELINK_ENHANCEMENTS 2298 2299 /****************************************************************************** 2300 * Description: 2301 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 2302 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 2303 ******************************************************************************/ 2304 static elink_status_t elink_pfc_nig_rx_priority_mask(struct elink_dev *cb, 2305 u8 cos_entry, 2306 u32 priority_mask, u8 port) 2307 { 2308 u32 nig_reg_rx_priority_mask_add = 0; 2309 2310 switch (cos_entry) { 2311 case 0: 2312 nig_reg_rx_priority_mask_add = (port) ? 2313 NIG_REG_P1_RX_COS0_PRIORITY_MASK : 2314 NIG_REG_P0_RX_COS0_PRIORITY_MASK; 2315 break; 2316 case 1: 2317 nig_reg_rx_priority_mask_add = (port) ? 2318 NIG_REG_P1_RX_COS1_PRIORITY_MASK : 2319 NIG_REG_P0_RX_COS1_PRIORITY_MASK; 2320 break; 2321 case 2: 2322 nig_reg_rx_priority_mask_add = (port) ? 2323 NIG_REG_P1_RX_COS2_PRIORITY_MASK : 2324 NIG_REG_P0_RX_COS2_PRIORITY_MASK; 2325 break; 2326 case 3: 2327 if (port) 2328 return ELINK_STATUS_ERROR; 2329 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; 2330 break; 2331 case 4: 2332 if (port) 2333 return ELINK_STATUS_ERROR; 2334 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; 2335 break; 2336 case 5: 2337 if (port) 2338 return ELINK_STATUS_ERROR; 2339 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; 2340 break; 2341 } 2342 2343 REG_WR(cb, nig_reg_rx_priority_mask_add, priority_mask); 2344 2345 return ELINK_STATUS_OK; 2346 } 2347 #endif // ELINK_ENHANCEMENTS 2348 #ifndef EXCLUDE_NON_COMMON_INIT 2349 static void elink_update_mng(struct elink_params *params, u32 link_status) 2350 { 2351 struct elink_dev *cb = params->cb; 2352 2353 REG_WR(cb, params->shmem_base + 2354 OFFSETOF(struct shmem_region, 2355 port_mb[params->port].link_status), link_status); 2356 } 2357 2358 #ifdef ELINK_ENHANCEMENTS 2359 static void elink_update_pfc_nig(struct elink_params *params, 2360 struct elink_vars *vars, 2361 struct elink_nig_brb_pfc_port_params *nig_params) 2362 { 2363 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; 2364 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; 2365 u32 pkt_priority_to_cos = 0; 2366 struct elink_dev *cb = params->cb; 2367 u8 port = params->port; 2368 2369 int set_pfc = params->feature_config_flags & 2370 ELINK_FEATURE_CONFIG_PFC_ENABLED; 2371 ELINK_DEBUG_P0(cb, "updating pfc nig parameters\n"); 2372 2373 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set 2374 * MAC control frames (that are not pause packets) 2375 * will be forwarded to the XCM. 2376 */ 2377 xcm_mask = REG_RD(cb, port ? NIG_REG_LLH1_XCM_MASK : 2378 NIG_REG_LLH0_XCM_MASK); 2379 /* NIG params will override non PFC params, since it's possible to 2380 * do transition from PFC to SAFC 2381 */ 2382 if (set_pfc) { 2383 pause_enable = 0; 2384 llfc_out_en = 0; 2385 llfc_enable = 0; 2386 if (CHIP_IS_E3(params->chip_id)) 2387 ppp_enable = 0; 2388 else 2389 ppp_enable = 1; 2390 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2391 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2392 xcm_out_en = 0; 2393 hwpfc_enable = 1; 2394 } else { 2395 if (nig_params) { 2396 llfc_out_en = nig_params->llfc_out_en; 2397 llfc_enable = nig_params->llfc_enable; 2398 pause_enable = nig_params->pause_enable; 2399 } else /* Default non PFC mode - PAUSE */ 2400 pause_enable = 1; 2401 2402 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2403 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2404 xcm_out_en = 1; 2405 } 2406 2407 if (CHIP_IS_E3(params->chip_id)) 2408 REG_WR(cb, port ? NIG_REG_BRB1_PAUSE_IN_EN : 2409 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); 2410 REG_WR(cb, port ? NIG_REG_LLFC_OUT_EN_1 : 2411 NIG_REG_LLFC_OUT_EN_0, llfc_out_en); 2412 REG_WR(cb, port ? NIG_REG_LLFC_ENABLE_1 : 2413 NIG_REG_LLFC_ENABLE_0, llfc_enable); 2414 REG_WR(cb, port ? NIG_REG_PAUSE_ENABLE_1 : 2415 NIG_REG_PAUSE_ENABLE_0, pause_enable); 2416 2417 REG_WR(cb, port ? NIG_REG_PPP_ENABLE_1 : 2418 NIG_REG_PPP_ENABLE_0, ppp_enable); 2419 2420 REG_WR(cb, port ? NIG_REG_LLH1_XCM_MASK : 2421 NIG_REG_LLH0_XCM_MASK, xcm_mask); 2422 2423 REG_WR(cb, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : 2424 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); 2425 2426 /* Output enable for RX_XCM # IF */ 2427 REG_WR(cb, port ? NIG_REG_XCM1_OUT_EN : 2428 NIG_REG_XCM0_OUT_EN, xcm_out_en); 2429 2430 /* HW PFC TX enable */ 2431 REG_WR(cb, port ? NIG_REG_P1_HWPFC_ENABLE : 2432 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); 2433 2434 if (nig_params) { 2435 u8 i = 0; 2436 pkt_priority_to_cos = nig_params->pkt_priority_to_cos; 2437 2438 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) 2439 elink_pfc_nig_rx_priority_mask(cb, i, 2440 nig_params->rx_cos_priority_mask[i], port); 2441 2442 REG_WR(cb, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : 2443 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, 2444 nig_params->llfc_high_priority_classes); 2445 2446 REG_WR(cb, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : 2447 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, 2448 nig_params->llfc_low_priority_classes); 2449 } 2450 REG_WR(cb, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : 2451 NIG_REG_P0_PKT_PRIORITY_TO_COS, 2452 pkt_priority_to_cos); 2453 } 2454 2455 elink_status_t elink_update_pfc(struct elink_params *params, 2456 struct elink_vars *vars, 2457 struct elink_nig_brb_pfc_port_params *pfc_params) 2458 { 2459 /* The PFC and pause are orthogonal to one another, meaning when 2460 * PFC is enabled, the pause are disabled, and when PFC is 2461 * disabled, pause are set according to the pause result. 2462 */ 2463 u32 val; 2464 struct elink_dev *cb = params->cb; 2465 u8 bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC); 2466 2467 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 2468 vars->link_status |= LINK_STATUS_PFC_ENABLED; 2469 else 2470 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 2471 2472 elink_update_mng(params, vars->link_status); 2473 2474 /* Update NIG params */ 2475 elink_update_pfc_nig(params, vars, pfc_params); 2476 2477 if (!vars->link_up) 2478 return ELINK_STATUS_OK; 2479 2480 ELINK_DEBUG_P0(cb, "About to update PFC in BMAC\n"); 2481 2482 if (CHIP_IS_E3(params->chip_id)) { 2483 if (vars->mac_type == ELINK_MAC_TYPE_XMAC) 2484 elink_update_pfc_xmac(params, vars, 0); 2485 } else { 2486 val = REG_RD(cb, MISC_REG_RESET_REG_2); 2487 if ((val & 2488 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) 2489 == 0) { 2490 ELINK_DEBUG_P0(cb, "About to update PFC in EMAC\n"); 2491 elink_emac_enable(params, vars, 0); 2492 return ELINK_STATUS_OK; 2493 } 2494 if (CHIP_IS_E2(params->chip_id)) 2495 elink_update_pfc_bmac2(params, vars, bmac_loopback); 2496 else 2497 elink_update_pfc_bmac1(params, vars); 2498 2499 val = 0; 2500 if ((params->feature_config_flags & 2501 ELINK_FEATURE_CONFIG_PFC_ENABLED) || 2502 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2503 val = 1; 2504 REG_WR(cb, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); 2505 } 2506 return ELINK_STATUS_OK; 2507 } 2508 2509 #endif /* ELINK_ENHANCEMENTS */ 2510 #ifndef EXCLUDE_BMAC1 2511 static elink_status_t elink_bmac1_enable(struct elink_params *params, 2512 struct elink_vars *vars, 2513 u8 is_lb) 2514 { 2515 struct elink_dev *cb = params->cb; 2516 u8 port = params->port; 2517 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2518 NIG_REG_INGRESS_BMAC0_MEM; 2519 u32 wb_data[2]; 2520 u32 val; 2521 2522 ELINK_DEBUG_P0(cb, "Enabling BigMAC1\n"); 2523 2524 /* XGXS control */ 2525 wb_data[0] = 0x3c; 2526 wb_data[1] = 0; 2527 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, 2528 wb_data, 2); 2529 2530 /* TX MAC SA */ 2531 wb_data[0] = ((params->mac_addr[2] << 24) | 2532 (params->mac_addr[3] << 16) | 2533 (params->mac_addr[4] << 8) | 2534 params->mac_addr[5]); 2535 wb_data[1] = ((params->mac_addr[0] << 8) | 2536 params->mac_addr[1]); 2537 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); 2538 2539 /* MAC control */ 2540 val = 0x3; 2541 if (is_lb) { 2542 val |= 0x4; 2543 ELINK_DEBUG_P0(cb, "enable bmac loopback\n"); 2544 } 2545 wb_data[0] = val; 2546 wb_data[1] = 0; 2547 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); 2548 2549 /* Set rx mtu */ 2550 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 2551 wb_data[1] = 0; 2552 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); 2553 2554 elink_update_pfc_bmac1(params, vars); 2555 2556 /* Set tx mtu */ 2557 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 2558 wb_data[1] = 0; 2559 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); 2560 2561 /* Set cnt max size */ 2562 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 2563 wb_data[1] = 0; 2564 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2565 2566 /* Configure SAFC */ 2567 wb_data[0] = 0x1000200; 2568 wb_data[1] = 0; 2569 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, 2570 wb_data, 2); 2571 #ifdef ELINK_INCLUDE_EMUL 2572 /* Fix for emulation */ 2573 if (CHIP_REV_IS_EMUL(params->chip_id)) { 2574 wb_data[0] = 0xf000; 2575 wb_data[1] = 0; 2576 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD, 2577 wb_data, 2); 2578 } 2579 #endif /* ELINK_INCLUDE_EMUL */ 2580 2581 return ELINK_STATUS_OK; 2582 } 2583 #endif /* EXCLUDE_BMAC1 */ 2584 2585 #ifndef EXCLUDE_BMAC2 2586 static elink_status_t elink_bmac2_enable(struct elink_params *params, 2587 struct elink_vars *vars, 2588 u8 is_lb) 2589 { 2590 struct elink_dev *cb = params->cb; 2591 u8 port = params->port; 2592 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2593 NIG_REG_INGRESS_BMAC0_MEM; 2594 u32 wb_data[2]; 2595 2596 ELINK_DEBUG_P0(cb, "Enabling BigMAC2\n"); 2597 2598 wb_data[0] = 0; 2599 wb_data[1] = 0; 2600 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2601 USLEEP(cb, 30); 2602 2603 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ 2604 wb_data[0] = 0x3c; 2605 wb_data[1] = 0; 2606 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, 2607 wb_data, 2); 2608 2609 USLEEP(cb, 30); 2610 2611 /* TX MAC SA */ 2612 wb_data[0] = ((params->mac_addr[2] << 24) | 2613 (params->mac_addr[3] << 16) | 2614 (params->mac_addr[4] << 8) | 2615 params->mac_addr[5]); 2616 wb_data[1] = ((params->mac_addr[0] << 8) | 2617 params->mac_addr[1]); 2618 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, 2619 wb_data, 2); 2620 2621 USLEEP(cb, 30); 2622 2623 /* Configure SAFC */ 2624 wb_data[0] = 0x1000200; 2625 wb_data[1] = 0; 2626 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, 2627 wb_data, 2); 2628 USLEEP(cb, 30); 2629 2630 /* Set RX MTU */ 2631 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 2632 wb_data[1] = 0; 2633 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); 2634 USLEEP(cb, 30); 2635 2636 /* Set TX MTU */ 2637 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 2638 wb_data[1] = 0; 2639 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); 2640 USLEEP(cb, 30); 2641 /* Set cnt max size */ 2642 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2; 2643 wb_data[1] = 0; 2644 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2645 USLEEP(cb, 30); 2646 elink_update_pfc_bmac2(params, vars, is_lb); 2647 2648 return ELINK_STATUS_OK; 2649 } 2650 #endif /* EXCLUDE_BMAC2 */ 2651 2652 #if !defined(EXCLUDE_BMAC2) 2653 static elink_status_t elink_bmac_enable(struct elink_params *params, 2654 struct elink_vars *vars, 2655 u8 is_lb, u8 reset_bmac) 2656 { 2657 elink_status_t rc = ELINK_STATUS_OK; 2658 u8 port = params->port; 2659 struct elink_dev *cb = params->cb; 2660 u32 val; 2661 /* Reset and unreset the BigMac */ 2662 if (reset_bmac) { 2663 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2664 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2665 MSLEEP(cb, 1); 2666 } 2667 2668 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2669 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2670 2671 /* Enable access for bmac registers */ 2672 REG_WR(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 2673 2674 /* Enable BMAC according to BMAC type*/ 2675 #ifdef ELINK_ENHANCEMENTS 2676 if (CHIP_IS_E2(params->chip_id)) 2677 #endif 2678 #ifndef EXCLUDE_BMAC2 2679 rc = elink_bmac2_enable(params, vars, is_lb); 2680 #endif 2681 #ifdef ELINK_ENHANCEMENTS 2682 else 2683 #endif 2684 #ifndef EXCLUDE_BMAC1 2685 rc = elink_bmac1_enable(params, vars, is_lb); 2686 #endif 2687 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); 2688 REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); 2689 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); 2690 val = 0; 2691 if ((params->feature_config_flags & 2692 ELINK_FEATURE_CONFIG_PFC_ENABLED) || 2693 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2694 val = 1; 2695 REG_WR(cb, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); 2696 REG_WR(cb, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); 2697 REG_WR(cb, NIG_REG_EMAC0_IN_EN + port*4, 0x0); 2698 REG_WR(cb, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); 2699 REG_WR(cb, NIG_REG_BMAC0_IN_EN + port*4, 0x1); 2700 REG_WR(cb, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); 2701 2702 vars->mac_type = ELINK_MAC_TYPE_BMAC; 2703 return rc; 2704 } 2705 #endif /* #if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) */ 2706 2707 #if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) 2708 static void elink_set_bmac_rx(struct elink_dev *cb, u32 chip_id, u8 port, u8 en) 2709 { 2710 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2711 NIG_REG_INGRESS_BMAC0_MEM; 2712 u32 wb_data[2]; 2713 u32 nig_bmac_enable = REG_RD(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4); 2714 2715 if (CHIP_IS_E2(chip_id)) 2716 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL; 2717 else 2718 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL; 2719 /* Only if the bmac is out of reset */ 2720 if (REG_RD(cb, MISC_REG_RESET_REG_2) & 2721 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && 2722 nig_bmac_enable) { 2723 /* Clear Rx Enable bit in BMAC_CONTROL register */ 2724 REG_RD_DMAE(cb, bmac_addr, wb_data, 2); 2725 if (en) 2726 wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE; 2727 else 2728 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE; 2729 REG_WR_DMAE(cb, bmac_addr, wb_data, 2); 2730 MSLEEP(cb, 1); 2731 } 2732 } 2733 #endif /* !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) */ 2734 #endif // EXCLUDE_NON_COMMON_INIT 2735 2736 #ifndef ELINK_AUX_POWER 2737 static elink_status_t elink_pbf_update(struct elink_params *params, u32 flow_ctrl, 2738 u32 line_speed) 2739 { 2740 struct elink_dev *cb = params->cb; 2741 u8 port = params->port; 2742 u32 init_crd, crd; 2743 u32 count = 1000; 2744 2745 /* Disable port */ 2746 REG_WR(cb, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); 2747 2748 /* Wait for init credit */ 2749 init_crd = REG_RD(cb, PBF_REG_P0_INIT_CRD + port*4); 2750 crd = REG_RD(cb, PBF_REG_P0_CREDIT + port*8); 2751 ELINK_DEBUG_P2(cb, "init_crd 0x%x crd 0x%x\n", init_crd, crd); 2752 2753 while ((init_crd != crd) && count) { 2754 MSLEEP(cb, 5); 2755 crd = REG_RD(cb, PBF_REG_P0_CREDIT + port*8); 2756 count--; 2757 } 2758 crd = REG_RD(cb, PBF_REG_P0_CREDIT + port*8); 2759 if (init_crd != crd) { 2760 ELINK_DEBUG_P2(cb, "BUG! init_crd 0x%x != crd 0x%x\n", 2761 init_crd, crd); 2762 return ELINK_STATUS_ERROR; 2763 } 2764 2765 if (flow_ctrl & ELINK_FLOW_CTRL_RX || 2766 line_speed == ELINK_SPEED_10 || 2767 line_speed == ELINK_SPEED_100 || 2768 line_speed == ELINK_SPEED_1000 || 2769 line_speed == ELINK_SPEED_2500) { 2770 REG_WR(cb, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); 2771 /* Update threshold */ 2772 REG_WR(cb, PBF_REG_P0_ARB_THRSH + port*4, 0); 2773 /* Update init credit */ 2774 init_crd = 778; /* (800-18-4) */ 2775 2776 } else { 2777 u32 thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + 2778 ELINK_ETH_OVREHEAD)/16; 2779 REG_WR(cb, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 2780 /* Update threshold */ 2781 REG_WR(cb, PBF_REG_P0_ARB_THRSH + port*4, thresh); 2782 /* Update init credit */ 2783 switch (line_speed) { 2784 case ELINK_SPEED_10000: 2785 init_crd = thresh + 553 - 22; 2786 break; 2787 default: 2788 ELINK_DEBUG_P1(cb, "Invalid line_speed 0x%x\n", 2789 line_speed); 2790 return ELINK_STATUS_ERROR; 2791 } 2792 } 2793 REG_WR(cb, PBF_REG_P0_INIT_CRD + port*4, init_crd); 2794 ELINK_DEBUG_P2(cb, "PBF updated to speed %d credit %d\n", 2795 line_speed, init_crd); 2796 2797 /* Probe the credit changes */ 2798 REG_WR(cb, PBF_REG_INIT_P0 + port*4, 0x1); 2799 MSLEEP(cb, 5); 2800 REG_WR(cb, PBF_REG_INIT_P0 + port*4, 0x0); 2801 2802 /* Enable port */ 2803 REG_WR(cb, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); 2804 return ELINK_STATUS_OK; 2805 } 2806 #endif /* ELINK_AUX_POWER */ 2807 2808 #ifndef EXCLUDE_COMMON_INIT 2809 /** 2810 * elink_get_emac_base - retrive emac base address 2811 * 2812 * @bp: driver handle 2813 * @mdc_mdio_access: access type 2814 * @port: port id 2815 * 2816 * This function selects the MDC/MDIO access (through emac0 or 2817 * emac1) depend on the mdc_mdio_access, port, port swapped. Each 2818 * phy has a default access mode, which could also be overridden 2819 * by nvram configuration. This parameter, whether this is the 2820 * default phy configuration, or the nvram overrun 2821 * configuration, is passed here as mdc_mdio_access and selects 2822 * the emac_base for the CL45 read/writes operations 2823 */ 2824 static u32 elink_get_emac_base(struct elink_dev *cb, 2825 u32 mdc_mdio_access, u8 port) 2826 { 2827 u32 emac_base = 0; 2828 switch (mdc_mdio_access) { 2829 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: 2830 break; 2831 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: 2832 if (REG_RD(cb, NIG_REG_PORT_SWAP)) 2833 emac_base = GRCBASE_EMAC1; 2834 else 2835 emac_base = GRCBASE_EMAC0; 2836 break; 2837 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: 2838 if (REG_RD(cb, NIG_REG_PORT_SWAP)) 2839 emac_base = GRCBASE_EMAC0; 2840 else 2841 emac_base = GRCBASE_EMAC1; 2842 break; 2843 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: 2844 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 2845 break; 2846 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: 2847 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; 2848 break; 2849 default: 2850 break; 2851 } 2852 return emac_base; 2853 2854 } 2855 #endif /* EXCLUDE_COMMON_INIT */ 2856 2857 /******************************************************************/ 2858 /* CL22 access functions */ 2859 /******************************************************************/ 2860 #ifndef EXCLUDE_NON_COMMON_INIT 2861 #ifndef EXCLUDE_BCM54618SE 2862 static elink_status_t elink_cl22_write(struct elink_dev *cb, 2863 struct elink_phy *phy, 2864 u16 reg, u16 val) 2865 { 2866 u32 tmp, mode; 2867 u8 i; 2868 elink_status_t rc = ELINK_STATUS_OK; 2869 /* Switch to CL22 */ 2870 mode = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2871 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2872 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2873 2874 /* Address */ 2875 tmp = ((phy->addr << 21) | (reg << 16) | val | 2876 EMAC_MDIO_COMM_COMMAND_WRITE_22 | 2877 EMAC_MDIO_COMM_START_BUSY); 2878 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2879 2880 for (i = 0; i < 50; i++) { 2881 USLEEP(cb, 10); 2882 2883 tmp = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2884 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2885 USLEEP(cb, 5); 2886 break; 2887 } 2888 } 2889 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2890 ELINK_DEBUG_P0(cb, "write phy register failed\n"); 2891 rc = ELINK_STATUS_TIMEOUT; 2892 } 2893 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2894 return rc; 2895 } 2896 2897 static elink_status_t elink_cl22_read(struct elink_dev *cb, 2898 struct elink_phy *phy, 2899 u16 reg, u16 *ret_val) 2900 { 2901 u32 val, mode; 2902 u16 i; 2903 elink_status_t rc = ELINK_STATUS_OK; 2904 2905 /* Switch to CL22 */ 2906 mode = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2907 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2908 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2909 2910 /* Address */ 2911 val = ((phy->addr << 21) | (reg << 16) | 2912 EMAC_MDIO_COMM_COMMAND_READ_22 | 2913 EMAC_MDIO_COMM_START_BUSY); 2914 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2915 2916 for (i = 0; i < 50; i++) { 2917 USLEEP(cb, 10); 2918 2919 val = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2920 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2921 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2922 USLEEP(cb, 5); 2923 break; 2924 } 2925 } 2926 if (val & EMAC_MDIO_COMM_START_BUSY) { 2927 ELINK_DEBUG_P0(cb, "read phy register failed\n"); 2928 2929 *ret_val = 0; 2930 rc = ELINK_STATUS_TIMEOUT; 2931 } 2932 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2933 return rc; 2934 } 2935 #endif 2936 #endif /* EXCLUDE_NON_COMMON_INIT */ 2937 2938 /******************************************************************/ 2939 /* CL45 access functions */ 2940 /******************************************************************/ 2941 static elink_status_t elink_cl45_read(struct elink_dev *cb, struct elink_phy *phy, 2942 u8 devad, u16 reg, u16 *ret_val) 2943 { 2944 u32 val; 2945 u16 i; 2946 elink_status_t rc = ELINK_STATUS_OK; 2947 #ifndef ELINK_AUX_POWER 2948 u32 chip_id; 2949 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) { 2950 chip_id = (REG_RD(cb, MISC_REG_CHIP_NUM) << 16) | 2951 ((REG_RD(cb, MISC_REG_CHIP_REV) & 0xf) << 12); 2952 elink_set_mdio_clk(cb, chip_id, phy->mdio_ctrl); 2953 } 2954 #endif /* ELINK_AUX_POWER */ 2955 2956 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) 2957 elink_bits_en(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2958 EMAC_MDIO_STATUS_10MB); 2959 /* Address */ 2960 val = ((phy->addr << 21) | (devad << 16) | reg | 2961 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2962 EMAC_MDIO_COMM_START_BUSY); 2963 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2964 2965 for (i = 0; i < 50; i++) { 2966 USLEEP(cb, 10); 2967 2968 val = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2969 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2970 USLEEP(cb, 5); 2971 break; 2972 } 2973 } 2974 if (val & EMAC_MDIO_COMM_START_BUSY) { 2975 ELINK_DEBUG_P0(cb, "read phy register failed\n"); 2976 elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n" 2977 2978 *ret_val = 0; 2979 rc = ELINK_STATUS_TIMEOUT; 2980 } else { 2981 /* Data */ 2982 val = ((phy->addr << 21) | (devad << 16) | 2983 EMAC_MDIO_COMM_COMMAND_READ_45 | 2984 EMAC_MDIO_COMM_START_BUSY); 2985 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2986 2987 for (i = 0; i < 50; i++) { 2988 USLEEP(cb, 10); 2989 2990 val = REG_RD(cb, phy->mdio_ctrl + 2991 EMAC_REG_EMAC_MDIO_COMM); 2992 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2993 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2994 break; 2995 } 2996 } 2997 if (val & EMAC_MDIO_COMM_START_BUSY) { 2998 ELINK_DEBUG_P0(cb, "read phy register failed\n"); 2999 elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n" 3000 3001 *ret_val = 0; 3002 rc = ELINK_STATUS_TIMEOUT; 3003 } 3004 } 3005 /* Work around for E3 A0 */ 3006 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) { 3007 phy->flags ^= ELINK_FLAGS_DUMMY_READ; 3008 if (phy->flags & ELINK_FLAGS_DUMMY_READ) { 3009 u16 temp_val; 3010 elink_cl45_read(cb, phy, devad, 0xf, &temp_val); 3011 } 3012 } 3013 3014 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) 3015 elink_bits_dis(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 3016 EMAC_MDIO_STATUS_10MB); 3017 return rc; 3018 } 3019 3020 static elink_status_t elink_cl45_write(struct elink_dev *cb, struct elink_phy *phy, 3021 u8 devad, u16 reg, u16 val) 3022 { 3023 u32 tmp; 3024 u8 i; 3025 elink_status_t rc = ELINK_STATUS_OK; 3026 #ifndef ELINK_AUX_POWER 3027 u32 chip_id; 3028 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) { 3029 chip_id = (REG_RD(cb, MISC_REG_CHIP_NUM) << 16) | 3030 ((REG_RD(cb, MISC_REG_CHIP_REV) & 0xf) << 12); 3031 elink_set_mdio_clk(cb, chip_id, phy->mdio_ctrl); 3032 } 3033 #endif /* ELINK_AUX_POWER */ 3034 3035 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) 3036 elink_bits_en(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 3037 EMAC_MDIO_STATUS_10MB); 3038 3039 /* Address */ 3040 tmp = ((phy->addr << 21) | (devad << 16) | reg | 3041 EMAC_MDIO_COMM_COMMAND_ADDRESS | 3042 EMAC_MDIO_COMM_START_BUSY); 3043 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 3044 3045 for (i = 0; i < 50; i++) { 3046 USLEEP(cb, 10); 3047 3048 tmp = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 3049 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 3050 USLEEP(cb, 5); 3051 break; 3052 } 3053 } 3054 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 3055 ELINK_DEBUG_P0(cb, "write phy register failed\n"); 3056 elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n" 3057 3058 rc = ELINK_STATUS_TIMEOUT; 3059 } else { 3060 /* Data */ 3061 tmp = ((phy->addr << 21) | (devad << 16) | val | 3062 EMAC_MDIO_COMM_COMMAND_WRITE_45 | 3063 EMAC_MDIO_COMM_START_BUSY); 3064 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 3065 3066 for (i = 0; i < 50; i++) { 3067 USLEEP(cb, 10); 3068 3069 tmp = REG_RD(cb, phy->mdio_ctrl + 3070 EMAC_REG_EMAC_MDIO_COMM); 3071 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 3072 USLEEP(cb, 5); 3073 break; 3074 } 3075 } 3076 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 3077 ELINK_DEBUG_P0(cb, "write phy register failed\n"); 3078 elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n" 3079 3080 rc = ELINK_STATUS_TIMEOUT; 3081 } 3082 } 3083 /* Work around for E3 A0 */ 3084 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) { 3085 phy->flags ^= ELINK_FLAGS_DUMMY_READ; 3086 if (phy->flags & ELINK_FLAGS_DUMMY_READ) { 3087 u16 temp_val; 3088 elink_cl45_read(cb, phy, devad, 0xf, &temp_val); 3089 } 3090 } 3091 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) 3092 elink_bits_dis(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 3093 EMAC_MDIO_STATUS_10MB); 3094 return rc; 3095 } 3096 3097 /******************************************************************/ 3098 /* EEE section */ 3099 /******************************************************************/ 3100 #ifndef EXCLUDE_NON_COMMON_INIT 3101 #ifndef EXCLUDE_WARPCORE 3102 static u8 elink_eee_has_cap(struct elink_params *params) 3103 { 3104 struct elink_dev *cb = params->cb; 3105 3106 if (REG_RD(cb, params->shmem2_base) <= 3107 OFFSETOF(struct shmem2_region, eee_status[params->port])) 3108 return 0; 3109 3110 return 1; 3111 } 3112 3113 static elink_status_t elink_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer) 3114 { 3115 switch (nvram_mode) { 3116 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: 3117 *idle_timer = ELINK_EEE_MODE_NVRAM_BALANCED_TIME; 3118 break; 3119 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: 3120 *idle_timer = ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME; 3121 break; 3122 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: 3123 *idle_timer = ELINK_EEE_MODE_NVRAM_LATENCY_TIME; 3124 break; 3125 default: 3126 *idle_timer = 0; 3127 break; 3128 } 3129 3130 return ELINK_STATUS_OK; 3131 } 3132 3133 static elink_status_t elink_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode) 3134 { 3135 switch (idle_timer) { 3136 case ELINK_EEE_MODE_NVRAM_BALANCED_TIME: 3137 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; 3138 break; 3139 case ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME: 3140 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; 3141 break; 3142 case ELINK_EEE_MODE_NVRAM_LATENCY_TIME: 3143 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; 3144 break; 3145 default: 3146 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; 3147 break; 3148 } 3149 3150 return ELINK_STATUS_OK; 3151 } 3152 3153 static u32 elink_eee_calc_timer(struct elink_params *params) 3154 { 3155 u32 eee_mode, eee_idle; 3156 struct elink_dev *cb = params->cb; 3157 3158 if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) { 3159 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) { 3160 /* time value in eee_mode --> used directly*/ 3161 eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK; 3162 } else { 3163 /* hsi value in eee_mode --> time */ 3164 if (elink_eee_nvram_to_time(params->eee_mode & 3165 ELINK_EEE_MODE_NVRAM_MASK, 3166 &eee_idle)) 3167 return 0; 3168 } 3169 } else { 3170 /* hsi values in nvram --> time*/ 3171 eee_mode = ((REG_RD(cb, params->shmem_base + 3172 OFFSETOF(struct shmem_region, dev_info. 3173 port_feature_config[params->port]. 3174 eee_power_mode)) & 3175 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 3176 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 3177 3178 if (elink_eee_nvram_to_time(eee_mode, &eee_idle)) 3179 return 0; 3180 } 3181 3182 return eee_idle; 3183 } 3184 3185 static elink_status_t elink_eee_set_timers(struct elink_params *params, 3186 struct elink_vars *vars) 3187 { 3188 u32 eee_idle = 0, eee_mode; 3189 struct elink_dev *cb = params->cb; 3190 3191 eee_idle = elink_eee_calc_timer(params); 3192 3193 if (eee_idle) { 3194 REG_WR(cb, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), 3195 eee_idle); 3196 } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) && 3197 (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) && 3198 (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) { 3199 ELINK_DEBUG_P0(cb, "Error: Tx LPI is enabled with timer 0\n"); 3200 return ELINK_STATUS_ERROR; 3201 } 3202 3203 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); 3204 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) { 3205 /* eee_idle in 1u --> eee_status in 16u */ 3206 eee_idle >>= 4; 3207 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | 3208 SHMEM_EEE_TIME_OUTPUT_BIT; 3209 } else { 3210 if (elink_eee_time_to_nvram(eee_idle, &eee_mode)) 3211 return ELINK_STATUS_ERROR; 3212 vars->eee_status |= eee_mode; 3213 } 3214 3215 return ELINK_STATUS_OK; 3216 } 3217 3218 static elink_status_t elink_eee_initial_config(struct elink_params *params, 3219 struct elink_vars *vars, u8 mode) 3220 { 3221 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT; 3222 3223 /* Propogate params' bits --> vars (for migration exposure) */ 3224 if (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) 3225 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; 3226 else 3227 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; 3228 3229 if (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) 3230 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; 3231 else 3232 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; 3233 3234 return elink_eee_set_timers(params, vars); 3235 } 3236 3237 static elink_status_t elink_eee_disable(struct elink_phy *phy, 3238 struct elink_params *params, 3239 struct elink_vars *vars) 3240 { 3241 struct elink_dev *cb = params->cb; 3242 3243 /* Make Certain LPI is disabled */ 3244 REG_WR(cb, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); 3245 3246 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); 3247 3248 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 3249 3250 return ELINK_STATUS_OK; 3251 } 3252 3253 static elink_status_t elink_eee_advertise(struct elink_phy *phy, 3254 struct elink_params *params, 3255 struct elink_vars *vars, u8 modes) 3256 { 3257 struct elink_dev *cb = params->cb; 3258 u16 val = 0; 3259 3260 /* Mask events preventing LPI generation */ 3261 REG_WR(cb, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); 3262 3263 if (modes & SHMEM_EEE_10G_ADV) { 3264 ELINK_DEBUG_P0(cb, "Advertise 10GBase-T EEE\n"); 3265 val |= 0x8; 3266 } 3267 if (modes & SHMEM_EEE_1G_ADV) { 3268 ELINK_DEBUG_P0(cb, "Advertise 1GBase-T EEE\n"); 3269 val |= 0x4; 3270 } 3271 3272 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); 3273 3274 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 3275 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); 3276 3277 return ELINK_STATUS_OK; 3278 } 3279 3280 static void elink_update_mng_eee(struct elink_params *params, u32 eee_status) 3281 { 3282 struct elink_dev *cb = params->cb; 3283 3284 if (elink_eee_has_cap(params)) 3285 REG_WR(cb, params->shmem2_base + 3286 OFFSETOF(struct shmem2_region, 3287 eee_status[params->port]), eee_status); 3288 } 3289 3290 static void elink_eee_an_resolve(struct elink_phy *phy, 3291 struct elink_params *params, 3292 struct elink_vars *vars) 3293 { 3294 struct elink_dev *cb = params->cb; 3295 u16 adv = 0, lp = 0; 3296 u32 lp_adv = 0; 3297 u8 neg = 0; 3298 3299 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); 3300 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); 3301 3302 if (lp & 0x2) { 3303 lp_adv |= SHMEM_EEE_100M_ADV; 3304 if (adv & 0x2) { 3305 if (vars->line_speed == ELINK_SPEED_100) 3306 neg = 1; 3307 ELINK_DEBUG_P0(cb, "EEE negotiated - 100M\n"); 3308 } 3309 } 3310 if (lp & 0x14) { 3311 lp_adv |= SHMEM_EEE_1G_ADV; 3312 if (adv & 0x14) { 3313 if (vars->line_speed == ELINK_SPEED_1000) 3314 neg = 1; 3315 ELINK_DEBUG_P0(cb, "EEE negotiated - 1G\n"); 3316 } 3317 } 3318 if (lp & 0x68) { 3319 lp_adv |= SHMEM_EEE_10G_ADV; 3320 if (adv & 0x68) { 3321 if (vars->line_speed == ELINK_SPEED_10000) 3322 neg = 1; 3323 ELINK_DEBUG_P0(cb, "EEE negotiated - 10G\n"); 3324 } 3325 } 3326 3327 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; 3328 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); 3329 3330 if (neg) { 3331 ELINK_DEBUG_P0(cb, "EEE is active\n"); 3332 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; 3333 } 3334 } 3335 3336 /******************************************************************/ 3337 /* BSC access functions from E3 */ 3338 /******************************************************************/ 3339 static void elink_bsc_module_sel(struct elink_params *params) 3340 { 3341 int idx; 3342 u32 board_cfg, sfp_ctrl; 3343 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; 3344 struct elink_dev *cb = params->cb; 3345 u8 port = params->port; 3346 /* Read I2C output PINs */ 3347 board_cfg = REG_RD(cb, params->shmem_base + 3348 OFFSETOF(struct shmem_region, 3349 dev_info.shared_hw_config.board)); 3350 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; 3351 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> 3352 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; 3353 3354 /* Read I2C output value */ 3355 sfp_ctrl = REG_RD(cb, params->shmem_base + 3356 OFFSETOF(struct shmem_region, 3357 dev_info.port_hw_config[port].e3_cmn_pin_cfg)); 3358 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; 3359 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; 3360 ELINK_DEBUG_P0(cb, "Setting BSC switch\n"); 3361 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) 3362 elink_set_cfg_pin(cb, i2c_pins[idx], i2c_val[idx]); 3363 } 3364 3365 static elink_status_t elink_bsc_read(struct elink_params *params, 3366 struct elink_dev *cb, 3367 u8 sl_devid, 3368 u16 sl_addr, 3369 u8 lc_addr, 3370 u8 xfer_cnt, 3371 u32 *data_array) 3372 { 3373 u32 val, i; 3374 elink_status_t rc = ELINK_STATUS_OK; 3375 3376 if (xfer_cnt > 16) { 3377 ELINK_DEBUG_P1(cb, "invalid xfer_cnt %d. Max is 16 bytes\n", 3378 xfer_cnt); 3379 return ELINK_STATUS_ERROR; 3380 } 3381 if (params) 3382 elink_bsc_module_sel(params); 3383 3384 xfer_cnt = 16 - lc_addr; 3385 3386 /* Enable the engine */ 3387 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND); 3388 val |= MCPR_IMC_COMMAND_ENABLE; 3389 REG_WR(cb, MCP_REG_MCPR_IMC_COMMAND, val); 3390 3391 /* Program slave device ID */ 3392 val = (sl_devid << 16) | sl_addr; 3393 REG_WR(cb, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); 3394 3395 /* Start xfer with 0 byte to update the address pointer ???*/ 3396 val = (MCPR_IMC_COMMAND_ENABLE) | 3397 (MCPR_IMC_COMMAND_WRITE_OP << 3398 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3399 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); 3400 REG_WR(cb, MCP_REG_MCPR_IMC_COMMAND, val); 3401 3402 /* Poll for completion */ 3403 i = 0; 3404 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND); 3405 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3406 USLEEP(cb, 10); 3407 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND); 3408 if (i++ > 1000) { 3409 ELINK_DEBUG_P1(cb, "wr 0 byte timed out after %d try\n", 3410 i); 3411 rc = ELINK_STATUS_TIMEOUT; 3412 break; 3413 } 3414 } 3415 if (rc == ELINK_STATUS_TIMEOUT) 3416 return rc; 3417 3418 /* Start xfer with read op */ 3419 val = (MCPR_IMC_COMMAND_ENABLE) | 3420 (MCPR_IMC_COMMAND_READ_OP << 3421 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3422 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | 3423 (xfer_cnt); 3424 REG_WR(cb, MCP_REG_MCPR_IMC_COMMAND, val); 3425 3426 /* Poll for completion */ 3427 i = 0; 3428 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND); 3429 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3430 USLEEP(cb, 10); 3431 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND); 3432 if (i++ > 1000) { 3433 ELINK_DEBUG_P1(cb, "rd op timed out after %d try\n", i); 3434 rc = ELINK_STATUS_TIMEOUT; 3435 break; 3436 } 3437 } 3438 if (rc == ELINK_STATUS_TIMEOUT) 3439 return rc; 3440 3441 for (i = (lc_addr >> 2); i < 4; i++) { 3442 data_array[i] = REG_RD(cb, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); 3443 #ifdef BIG_ENDIAN 3444 data_array[i] = ((data_array[i] & 0x000000ff) << 24) | 3445 ((data_array[i] & 0x0000ff00) << 8) | 3446 ((data_array[i] & 0x00ff0000) >> 8) | 3447 ((data_array[i] & 0xff000000) >> 24); 3448 #endif 3449 } 3450 return rc; 3451 } 3452 3453 #endif /* EXCLUDE_WARPCORE */ 3454 #endif /* EXCLUDE_NON_COMMON_INIT */ 3455 #if !defined(EXCLUDE_NON_COMMON_INIT) || defined(INCLUDE_WARPCORE_UC_LOAD) 3456 static void elink_cl45_read_or_write(struct elink_dev *cb, struct elink_phy *phy, 3457 u8 devad, u16 reg, u16 or_val) 3458 { 3459 u16 val; 3460 elink_cl45_read(cb, phy, devad, reg, &val); 3461 elink_cl45_write(cb, phy, devad, reg, val | or_val); 3462 } 3463 3464 static void elink_cl45_read_and_write(struct elink_dev *cb, 3465 struct elink_phy *phy, 3466 u8 devad, u16 reg, u16 and_val) 3467 { 3468 u16 val; 3469 elink_cl45_read(cb, phy, devad, reg, &val); 3470 elink_cl45_write(cb, phy, devad, reg, val & and_val); 3471 } 3472 #endif 3473 3474 #ifdef ELINK_ENHANCEMENTS 3475 elink_status_t elink_phy_read(struct elink_params *params, u8 phy_addr, 3476 u8 devad, u16 reg, u16 *ret_val) 3477 { 3478 u8 phy_index; 3479 /* Probe for the phy according to the given phy_addr, and execute 3480 * the read request on it 3481 */ 3482 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3483 if (params->phy[phy_index].addr == phy_addr) { 3484 return elink_cl45_read(params->cb, 3485 ¶ms->phy[phy_index], devad, 3486 reg, ret_val); 3487 } 3488 } 3489 return ELINK_STATUS_ERROR; 3490 } 3491 3492 elink_status_t elink_phy_write(struct elink_params *params, u8 phy_addr, 3493 u8 devad, u16 reg, u16 val) 3494 { 3495 u8 phy_index; 3496 /* Probe for the phy according to the given phy_addr, and execute 3497 * the write request on it 3498 */ 3499 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3500 if (params->phy[phy_index].addr == phy_addr) { 3501 return elink_cl45_write(params->cb, 3502 ¶ms->phy[phy_index], devad, 3503 reg, val); 3504 } 3505 } 3506 return ELINK_STATUS_ERROR; 3507 } 3508 #endif // ELINK_ENHANCEMENTS 3509 3510 #if (!defined EXCLUDE_NON_COMMON_INIT) || (!defined EXCLUDE_WARPCORE) 3511 static u8 elink_get_warpcore_lane(struct elink_phy *phy, 3512 struct elink_params *params) 3513 { 3514 u8 lane = 0; 3515 #ifndef EXCLUDE_WARPCORE 3516 struct elink_dev *cb = params->cb; 3517 u32 path_swap, path_swap_ovr; 3518 u8 path, port; 3519 3520 path = PATH_ID(cb); 3521 port = params->port; 3522 3523 if (elink_is_4_port_mode(cb)) { 3524 u32 port_swap, port_swap_ovr; 3525 3526 /* Figure out path swap value */ 3527 path_swap_ovr = REG_RD(cb, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); 3528 if (path_swap_ovr & 0x1) 3529 path_swap = (path_swap_ovr & 0x2); 3530 else 3531 path_swap = REG_RD(cb, MISC_REG_FOUR_PORT_PATH_SWAP); 3532 3533 if (path_swap) 3534 path = path ^ 1; 3535 3536 /* Figure out port swap value */ 3537 port_swap_ovr = REG_RD(cb, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); 3538 if (port_swap_ovr & 0x1) 3539 port_swap = (port_swap_ovr & 0x2); 3540 else 3541 port_swap = REG_RD(cb, MISC_REG_FOUR_PORT_PORT_SWAP); 3542 3543 if (port_swap) 3544 port = port ^ 1; 3545 3546 lane = (port<<1) + path; 3547 } else { /* Two port mode - no port swap */ 3548 3549 /* Figure out path swap value */ 3550 path_swap_ovr = 3551 REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); 3552 if (path_swap_ovr & 0x1) { 3553 path_swap = (path_swap_ovr & 0x2); 3554 } else { 3555 path_swap = 3556 REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP); 3557 } 3558 if (path_swap) 3559 path = path ^ 1; 3560 3561 lane = path << 1 ; 3562 } 3563 #endif /* #ifndef EXCLUDE_WARPCORE */ 3564 return lane; 3565 } 3566 3567 3568 static void elink_set_aer_mmd(struct elink_params *params, 3569 struct elink_phy *phy) 3570 { 3571 u32 ser_lane; 3572 u16 offset, aer_val; 3573 struct elink_dev *cb = params->cb; 3574 ser_lane = ((params->lane_config & 3575 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 3576 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 3577 3578 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? 3579 (phy->addr + ser_lane) : 0; 3580 3581 if (ELINK_USES_WARPCORE(params->chip_id)) { 3582 aer_val = elink_get_warpcore_lane(phy, params); 3583 /* In Dual-lane mode, two lanes are joined together, 3584 * so in order to configure them, the AER broadcast method is 3585 * used here. 3586 * 0x200 is the broadcast address for lanes 0,1 3587 * 0x201 is the broadcast address for lanes 2,3 3588 */ 3589 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) 3590 aer_val = (aer_val >> 1) | 0x200; 3591 } else if (CHIP_IS_E2(params->chip_id)) 3592 aer_val = 0x3800 + offset - 1; 3593 else 3594 aer_val = 0x3800 + offset; 3595 3596 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 3597 MDIO_AER_BLOCK_AER_REG, aer_val); 3598 3599 } 3600 #endif 3601 #ifndef EXCLUDE_SERDES 3602 3603 /******************************************************************/ 3604 /* Internal phy section */ 3605 /******************************************************************/ 3606 3607 static void elink_set_serdes_access(struct elink_dev *cb, u8 port) 3608 { 3609 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 3610 3611 /* Set Clause 22 */ 3612 REG_WR(cb, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); 3613 REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); 3614 USLEEP(cb, 500); 3615 REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); 3616 USLEEP(cb, 500); 3617 /* Set Clause 45 */ 3618 REG_WR(cb, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); 3619 } 3620 3621 static void elink_serdes_deassert(struct elink_dev *cb, u8 port) 3622 { 3623 u32 val; 3624 3625 ELINK_DEBUG_P0(cb, "elink_serdes_deassert\n"); 3626 3627 val = ELINK_SERDES_RESET_BITS << (port*16); 3628 3629 /* Reset and unreset the SerDes/XGXS */ 3630 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3631 USLEEP(cb, 500); 3632 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3633 3634 elink_set_serdes_access(cb, port); 3635 3636 REG_WR(cb, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, 3637 ELINK_DEFAULT_PHY_DEV_ADDR); 3638 } 3639 #endif /* #ifndef EXCLUDE_SERDES */ 3640 3641 #ifndef EXCLUDE_NON_COMMON_INIT 3642 #ifndef EXCLUDE_XGXS 3643 static void elink_xgxs_specific_func(struct elink_phy *phy, 3644 struct elink_params *params, 3645 u32 action) 3646 { 3647 struct elink_dev *cb = params->cb; 3648 switch (action) { 3649 case ELINK_PHY_INIT: 3650 /* Set correct devad */ 3651 REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); 3652 REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, 3653 phy->def_md_devad); 3654 break; 3655 } 3656 } 3657 3658 static void elink_xgxs_deassert(struct elink_params *params) 3659 { 3660 struct elink_dev *cb = params->cb; 3661 u8 port; 3662 u32 val; 3663 ELINK_DEBUG_P0(cb, "elink_xgxs_deassert\n"); 3664 port = params->port; 3665 3666 val = ELINK_XGXS_RESET_BITS << (port*16); 3667 3668 /* Reset and unreset the SerDes/XGXS */ 3669 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3670 USLEEP(cb, 500); 3671 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3672 elink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params, 3673 ELINK_PHY_INIT); 3674 } 3675 #endif // EXCLUDE_XGXS 3676 3677 static void elink_calc_ieee_aneg_adv(struct elink_phy *phy, 3678 struct elink_params *params, u16 *ieee_fc) 3679 { 3680 #ifdef ELINK_DEBUG 3681 struct elink_dev *cb = params->cb; 3682 #endif 3683 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; 3684 /* Resolve pause mode and advertisement Please refer to Table 3685 * 28B-3 of the 802.3ab-1999 spec 3686 */ 3687 3688 switch (phy->req_flow_ctrl) { 3689 case ELINK_FLOW_CTRL_AUTO: 3690 switch (params->req_fc_auto_adv) { 3691 case ELINK_FLOW_CTRL_BOTH: 3692 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3693 break; 3694 case ELINK_FLOW_CTRL_RX: 3695 case ELINK_FLOW_CTRL_TX: 3696 *ieee_fc |= 3697 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3698 break; 3699 default: 3700 break; 3701 } 3702 break; 3703 case ELINK_FLOW_CTRL_TX: 3704 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3705 break; 3706 3707 case ELINK_FLOW_CTRL_RX: 3708 case ELINK_FLOW_CTRL_BOTH: 3709 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3710 break; 3711 3712 case ELINK_FLOW_CTRL_NONE: 3713 default: 3714 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; 3715 break; 3716 } 3717 ELINK_DEBUG_P1(cb, "ieee_fc = 0x%x\n", *ieee_fc); 3718 } 3719 #endif /* #ifndef EXCLUDE_NON_COMMON_INIT */ 3720 3721 static void set_phy_vars(struct elink_params *params, 3722 struct elink_vars *vars) 3723 { 3724 #ifdef ELINK_DEBUG 3725 struct elink_dev *cb = params->cb; 3726 #endif 3727 u8 actual_phy_idx, phy_index, link_cfg_idx; 3728 u8 phy_config_swapped = params->multi_phy_config & 3729 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 3730 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; 3731 phy_index++) { 3732 link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index); 3733 actual_phy_idx = phy_index; 3734 if (phy_config_swapped) { 3735 if (phy_index == ELINK_EXT_PHY1) 3736 actual_phy_idx = ELINK_EXT_PHY2; 3737 else if (phy_index == ELINK_EXT_PHY2) 3738 actual_phy_idx = ELINK_EXT_PHY1; 3739 } 3740 params->phy[actual_phy_idx].req_flow_ctrl = 3741 params->req_flow_ctrl[link_cfg_idx]; 3742 3743 params->phy[actual_phy_idx].req_line_speed = 3744 params->req_line_speed[link_cfg_idx]; 3745 3746 params->phy[actual_phy_idx].speed_cap_mask = 3747 params->speed_cap_mask[link_cfg_idx]; 3748 3749 params->phy[actual_phy_idx].req_duplex = 3750 params->req_duplex[link_cfg_idx]; 3751 3752 if (params->req_line_speed[link_cfg_idx] == 3753 ELINK_SPEED_AUTO_NEG) 3754 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 3755 3756 ELINK_DEBUG_P3(cb, "req_flow_ctrl %x, req_line_speed %x," 3757 " speed_cap_mask %x\n", 3758 params->phy[actual_phy_idx].req_flow_ctrl, 3759 params->phy[actual_phy_idx].req_line_speed, 3760 params->phy[actual_phy_idx].speed_cap_mask); 3761 } 3762 } 3763 3764 #ifndef EXCLUDE_NON_COMMON_INIT 3765 static void elink_ext_phy_set_pause(struct elink_params *params, 3766 struct elink_phy *phy, 3767 struct elink_vars *vars) 3768 { 3769 u16 val; 3770 struct elink_dev *cb = params->cb; 3771 /* Read modify write pause advertizing */ 3772 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); 3773 3774 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; 3775 3776 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 3777 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 3778 if ((vars->ieee_fc & 3779 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 3780 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 3781 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 3782 } 3783 if ((vars->ieee_fc & 3784 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 3785 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 3786 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 3787 } 3788 ELINK_DEBUG_P1(cb, "Ext phy AN advertize 0x%x\n", val); 3789 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); 3790 } 3791 3792 static void elink_pause_resolve(struct elink_vars *vars, u32 pause_result) 3793 { /* LD LP */ 3794 switch (pause_result) { /* ASYM P ASYM P */ 3795 case 0xb: /* 1 0 1 1 */ 3796 vars->flow_ctrl = ELINK_FLOW_CTRL_TX; 3797 break; 3798 3799 case 0xe: /* 1 1 1 0 */ 3800 vars->flow_ctrl = ELINK_FLOW_CTRL_RX; 3801 break; 3802 3803 case 0x5: /* 0 1 0 1 */ 3804 case 0x7: /* 0 1 1 1 */ 3805 case 0xd: /* 1 1 0 1 */ 3806 case 0xf: /* 1 1 1 1 */ 3807 vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH; 3808 break; 3809 3810 default: 3811 break; 3812 } 3813 if (pause_result & (1<<0)) 3814 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; 3815 if (pause_result & (1<<1)) 3816 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; 3817 3818 } 3819 3820 static void elink_ext_phy_update_adv_fc(struct elink_phy *phy, 3821 struct elink_params *params, 3822 struct elink_vars *vars) 3823 { 3824 u16 ld_pause; /* local */ 3825 u16 lp_pause; /* link partner */ 3826 u16 pause_result; 3827 struct elink_dev *cb = params->cb; 3828 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { 3829 #ifndef EXCLUDE_BCM54618SE 3830 elink_cl22_read(cb, phy, 0x4, &ld_pause); 3831 elink_cl22_read(cb, phy, 0x5, &lp_pause); 3832 #endif 3833 } else if (CHIP_IS_E3(params->chip_id) && 3834 ELINK_SINGLE_MEDIA_DIRECT(params)) { 3835 u8 lane = elink_get_warpcore_lane(phy, params); 3836 u16 gp_status, gp_mask; 3837 elink_cl45_read(cb, phy, 3838 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, 3839 &gp_status); 3840 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | 3841 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << 3842 lane; 3843 if ((gp_status & gp_mask) == gp_mask) { 3844 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 3845 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3846 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 3847 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3848 } else { 3849 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 3850 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 3851 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 3852 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 3853 ld_pause = ((ld_pause & 3854 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3855 << 3); 3856 lp_pause = ((lp_pause & 3857 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3858 << 3); 3859 } 3860 } else { 3861 elink_cl45_read(cb, phy, 3862 MDIO_AN_DEVAD, 3863 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3864 elink_cl45_read(cb, phy, 3865 MDIO_AN_DEVAD, 3866 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3867 } 3868 pause_result = (ld_pause & 3869 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; 3870 pause_result |= (lp_pause & 3871 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; 3872 ELINK_DEBUG_P1(cb, "Ext PHY pause result 0x%x\n", pause_result); 3873 elink_pause_resolve(vars, pause_result); 3874 3875 } 3876 3877 static u8 elink_ext_phy_resolve_fc(struct elink_phy *phy, 3878 struct elink_params *params, 3879 struct elink_vars *vars) 3880 { 3881 u8 ret = 0; 3882 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 3883 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) { 3884 /* Update the advertised flow-controled of LD/LP in AN */ 3885 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) 3886 elink_ext_phy_update_adv_fc(phy, params, vars); 3887 /* But set the flow-control result as the requested one */ 3888 vars->flow_ctrl = phy->req_flow_ctrl; 3889 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) 3890 vars->flow_ctrl = params->req_fc_auto_adv; 3891 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 3892 ret = 1; 3893 elink_ext_phy_update_adv_fc(phy, params, vars); 3894 } 3895 return ret; 3896 } 3897 #endif // EXCLUDE_NON_COMMON_INIT 3898 /******************************************************************/ 3899 /* Warpcore section */ 3900 /******************************************************************/ 3901 /* The init_internal_warpcore should mirror the xgxs, 3902 * i.e. reset the lane (if needed), set aer for the 3903 * init configuration, and set/clear SGMII flag. Internal 3904 * phy init is done purely in phy_init stage. 3905 */ 3906 #define WC_TX_DRIVER(post2, idriver, ipre) \ 3907 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \ 3908 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \ 3909 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)) 3910 3911 #define WC_TX_FIR(post, main, pre) \ 3912 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \ 3913 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \ 3914 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)) 3915 3916 #ifndef EXCLUDE_WARPCORE 3917 #ifndef EXCLUDE_NON_COMMON_INIT 3918 static void elink_update_link_attr(struct elink_params *params, u32 link_attr) 3919 { 3920 struct elink_dev *cb = params->cb; 3921 3922 if (SHMEM2_HAS(cb, params->shmem2_base, link_attr_sync)) 3923 REG_WR(cb, params->shmem2_base + 3924 OFFSETOF(struct shmem2_region, 3925 link_attr_sync[params->port]), link_attr); 3926 } 3927 3928 static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy, 3929 struct elink_params *params, 3930 struct elink_vars *vars) 3931 { 3932 struct elink_dev *cb = params->cb; 3933 u16 i; 3934 static struct elink_reg_set reg_set[] = { 3935 /* Step 1 - Program the TX/RX alignment markers */ 3936 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157}, 3937 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2}, 3938 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537}, 3939 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157}, 3940 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2}, 3941 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537}, 3942 /* Step 2 - Configure the NP registers */ 3943 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a}, 3944 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400}, 3945 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620}, 3946 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157}, 3947 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464}, 3948 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150}, 3949 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150}, 3950 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, 3951 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} 3952 }; 3953 ELINK_DEBUG_P0(cb, "Enabling 20G-KR2\n"); 3954 3955 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 3956 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6)); 3957 3958 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3959 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg, 3960 reg_set[i].val); 3961 3962 /* Start KR2 work-around timer which handles BCM8073 link-parner */ 3963 params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; 3964 elink_update_link_attr(params, params->link_attr_sync); 3965 } 3966 3967 static void elink_disable_kr2(struct elink_params *params, 3968 struct elink_vars *vars, 3969 struct elink_phy *phy) 3970 { 3971 struct elink_dev *cb = params->cb; 3972 int i; 3973 static struct elink_reg_set reg_set[] = { 3974 /* Step 1 - Program the TX/RX alignment markers */ 3975 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, 3976 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647}, 3977 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0}, 3978 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690}, 3979 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647}, 3980 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0}, 3981 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c}, 3982 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000}, 3983 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000}, 3984 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002}, 3985 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000}, 3986 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7}, 3987 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7}, 3988 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, 3989 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} 3990 }; 3991 ELINK_DEBUG_P0(cb, "Disabling 20G-KR2\n"); 3992 3993 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3994 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg, 3995 reg_set[i].val); 3996 params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; 3997 elink_update_link_attr(params, params->link_attr_sync); 3998 3999 vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT; 4000 } 4001 4002 static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy, 4003 struct elink_params *params) 4004 { 4005 struct elink_dev *cb = params->cb; 4006 4007 ELINK_DEBUG_P0(cb, "Configure WC for LPI pass through\n"); 4008 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4009 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); 4010 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4011 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); 4012 } 4013 4014 static void elink_warpcore_restart_AN_KR(struct elink_phy *phy, 4015 struct elink_params *params) 4016 { 4017 /* Restart autoneg on the leading lane only */ 4018 struct elink_dev *cb = params->cb; 4019 u16 lane = elink_get_warpcore_lane(phy, params); 4020 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4021 MDIO_AER_BLOCK_AER_REG, lane); 4022 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 4023 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 4024 4025 /* Restore AER */ 4026 elink_set_aer_mmd(params, phy); 4027 } 4028 4029 static void elink_warpcore_enable_AN_KR(struct elink_phy *phy, 4030 struct elink_params *params, 4031 struct elink_vars *vars) { 4032 u16 lane, i, cl72_ctrl, an_adv = 0, val; 4033 u32 wc_lane_config; 4034 struct elink_dev *cb = params->cb; 4035 static struct elink_reg_set reg_set[] = { 4036 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 4037 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, 4038 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, 4039 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, 4040 /* Disable Autoneg: re-enable it after adv is done. */ 4041 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}, 4042 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}, 4043 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, 4044 }; 4045 ELINK_DEBUG_P0(cb, "Enable Auto Negotiation for KR\n"); 4046 /* Set to default registers that may be overriden by 10G force */ 4047 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 4048 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg, 4049 reg_set[i].val); 4050 4051 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4052 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); 4053 cl72_ctrl &= 0x08ff; 4054 cl72_ctrl |= 0x3800; 4055 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4056 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); 4057 4058 /* Check adding advertisement for 1G KX */ 4059 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) && 4060 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 4061 (vars->line_speed == ELINK_SPEED_1000)) { 4062 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; 4063 an_adv |= (1<<5); 4064 4065 /* Enable CL37 1G Parallel Detect */ 4066 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, addr, 0x1); 4067 ELINK_DEBUG_P0(cb, "Advertize 1G\n"); 4068 } 4069 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) && 4070 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 4071 (vars->line_speed == ELINK_SPEED_10000)) { 4072 /* Check adding advertisement for 10G KR */ 4073 an_adv |= (1<<7); 4074 /* Enable 10G Parallel Detect */ 4075 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4076 MDIO_AER_BLOCK_AER_REG, 0); 4077 4078 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 4079 MDIO_WC_REG_PAR_DET_10G_CTRL, 1); 4080 elink_set_aer_mmd(params, phy); 4081 ELINK_DEBUG_P0(cb, "Advertize 10G\n"); 4082 } 4083 4084 /* Set Transmit PMD settings */ 4085 lane = elink_get_warpcore_lane(phy, params); 4086 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4087 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4088 WC_TX_DRIVER(0x02, 0x06, 0x09)); 4089 /* Configure the next lane if dual mode */ 4090 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) 4091 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4092 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1), 4093 WC_TX_DRIVER(0x02, 0x06, 0x09)); 4094 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4095 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 4096 0x03f0); 4097 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4098 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 4099 0x03f0); 4100 4101 /* Advertised speeds */ 4102 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 4103 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv); 4104 4105 /* Advertised and set FEC (Forward Error Correction) */ 4106 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 4107 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, 4108 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | 4109 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); 4110 4111 /* Enable CL37 BAM */ 4112 if (REG_RD(cb, params->shmem_base + 4113 OFFSETOF(struct shmem_region, dev_info. 4114 port_hw_config[params->port].default_cfg)) & 4115 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 4116 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4117 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, 4118 1); 4119 ELINK_DEBUG_P0(cb, "Enable CL37 BAM on KR\n"); 4120 } 4121 4122 /* Advertise pause */ 4123 elink_ext_phy_set_pause(params, phy, vars); 4124 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 4125 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4126 MDIO_WC_REG_DIGITAL5_MISC7, 0x100); 4127 4128 /* Over 1G - AN local device user page 1 */ 4129 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4130 MDIO_WC_REG_DIGITAL3_UP1, 0x1f); 4131 4132 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 4133 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || 4134 (phy->req_line_speed == ELINK_SPEED_20000)) { 4135 4136 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4137 MDIO_AER_BLOCK_AER_REG, lane); 4138 4139 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4140 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane), 4141 (1<<11)); 4142 4143 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4144 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); 4145 elink_set_aer_mmd(params, phy); 4146 4147 elink_warpcore_enable_AN_KR2(phy, params, vars); 4148 } else { 4149 /* Enable Auto-Detect to support 1G over CL37 as well */ 4150 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4151 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10); 4152 wc_lane_config = REG_RD(cb, params->shmem_base + 4153 OFFSETOF(struct shmem_region, dev_info. 4154 shared_hw_config.wc_lane_config)); 4155 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4156 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val); 4157 /* Force cl48 sync_status LOW to avoid getting stuck in CL73 4158 * parallel-detect loop when CL73 and CL37 are enabled. 4159 */ 4160 val |= 1 << 11; 4161 4162 /* Restore Polarity settings in case it was run over by 4163 * previous link owner 4164 */ 4165 if (wc_lane_config & 4166 (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane)) 4167 val |= 3 << 2; 4168 else 4169 val &= ~(3 << 2); 4170 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4171 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), 4172 val); 4173 4174 elink_disable_kr2(params, vars, phy); 4175 } 4176 4177 /* Enable Autoneg: only on the main lane */ 4178 elink_warpcore_restart_AN_KR(phy, params); 4179 } 4180 4181 static void elink_warpcore_set_10G_KR(struct elink_phy *phy, 4182 struct elink_params *params, 4183 struct elink_vars *vars) 4184 { 4185 struct elink_dev *cb = params->cb; 4186 u16 val16, i, lane; 4187 static struct elink_reg_set reg_set[] = { 4188 /* Disable Autoneg */ 4189 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 4190 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 4191 0x3f00}, 4192 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, 4193 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, 4194 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, 4195 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, 4196 /* Leave cl72 training enable, needed for KR */ 4197 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2} 4198 }; 4199 4200 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 4201 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg, 4202 reg_set[i].val); 4203 4204 lane = elink_get_warpcore_lane(phy, params); 4205 /* Global registers */ 4206 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4207 MDIO_AER_BLOCK_AER_REG, 0); 4208 /* Disable CL36 PCS Tx */ 4209 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4210 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 4211 val16 &= ~(0x0011 << lane); 4212 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4213 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 4214 4215 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4216 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 4217 val16 |= (0x0303 << (lane << 1)); 4218 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4219 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 4220 /* Restore AER */ 4221 elink_set_aer_mmd(params, phy); 4222 /* Set speed via PMA/PMD register */ 4223 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 4224 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); 4225 4226 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 4227 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); 4228 4229 /* Enable encoded forced speed */ 4230 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4231 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); 4232 4233 /* Turn TX scramble payload only the 64/66 scrambler */ 4234 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4235 MDIO_WC_REG_TX66_CONTROL, 0x9); 4236 4237 /* Turn RX scramble payload only the 64/66 scrambler */ 4238 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4239 MDIO_WC_REG_RX66_CONTROL, 0xF9); 4240 4241 /* Set and clear loopback to cause a reset to 64/66 decoder */ 4242 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4243 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); 4244 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4245 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); 4246 4247 } 4248 4249 static void elink_warpcore_set_10G_XFI(struct elink_phy *phy, 4250 struct elink_params *params, 4251 u8 is_xfi) 4252 { 4253 struct elink_dev *cb = params->cb; 4254 u16 misc1_val, tap_val, tx_driver_val, lane, val; 4255 u32 cfg_tap_val, tx_drv_brdct, tx_equal; 4256 4257 /* Hold rxSeqStart */ 4258 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4259 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); 4260 4261 /* Hold tx_fifo_reset */ 4262 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4263 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); 4264 4265 /* Disable CL73 AN */ 4266 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); 4267 4268 /* Disable 100FX Enable and Auto-Detect */ 4269 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4270 MDIO_WC_REG_FX100_CTRL1, 0xFFFA); 4271 4272 /* Disable 100FX Idle detect */ 4273 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4274 MDIO_WC_REG_FX100_CTRL3, 0x0080); 4275 4276 /* Set Block address to Remote PHY & Clear forced_speed[5] */ 4277 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4278 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F); 4279 4280 /* Turn off auto-detect & fiber mode */ 4281 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4282 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4283 0xFFEE); 4284 4285 /* Set filter_force_link, disable_false_link and parallel_detect */ 4286 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4287 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); 4288 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4289 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4290 ((val | 0x0006) & 0xFFFE)); 4291 4292 /* Set XFI / SFI */ 4293 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4294 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); 4295 4296 misc1_val &= ~(0x1f); 4297 4298 if (is_xfi) { 4299 misc1_val |= 0x5; 4300 tap_val = WC_TX_FIR(0x08, 0x37, 0x00); 4301 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03); 4302 } else { 4303 cfg_tap_val = REG_RD(cb, params->shmem_base + 4304 OFFSETOF(struct shmem_region, dev_info. 4305 port_hw_config[params->port]. 4306 sfi_tap_values)); 4307 4308 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK; 4309 4310 tx_drv_brdct = (cfg_tap_val & 4311 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >> 4312 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT; 4313 4314 misc1_val |= 0x9; 4315 4316 /* TAP values are controlled by nvram, if value there isn't 0 */ 4317 if (tx_equal) 4318 tap_val = (u16)tx_equal; 4319 else 4320 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02); 4321 4322 if (tx_drv_brdct) 4323 tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct, 4324 0x06); 4325 else 4326 tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06); 4327 } 4328 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4329 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); 4330 4331 /* Set Transmit PMD settings */ 4332 lane = elink_get_warpcore_lane(phy, params); 4333 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4334 MDIO_WC_REG_TX_FIR_TAP, 4335 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); 4336 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4337 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4338 tx_driver_val); 4339 4340 /* Enable fiber mode, enable and invert sig_det */ 4341 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4342 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); 4343 4344 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ 4345 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4346 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); 4347 4348 elink_warpcore_set_lpi_passthrough(phy, params); 4349 4350 /* 10G XFI Full Duplex */ 4351 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4352 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); 4353 4354 /* Release tx_fifo_reset */ 4355 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4356 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4357 0xFFFE); 4358 /* Release rxSeqStart */ 4359 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4360 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF); 4361 } 4362 #endif //EXCLUDE_NON_COMMON_INIT 4363 4364 #ifndef ELINK_AUX_POWER 4365 static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy, 4366 struct elink_params *params) 4367 { 4368 u16 val; 4369 struct elink_dev *cb = params->cb; 4370 /* Set global registers, so set AER lane to 0 */ 4371 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4372 MDIO_AER_BLOCK_AER_REG, 0); 4373 4374 /* Disable sequencer */ 4375 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4376 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13)); 4377 4378 elink_set_aer_mmd(params, phy); 4379 4380 elink_cl45_read_and_write(cb, phy, MDIO_PMA_DEVAD, 4381 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1)); 4382 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 4383 MDIO_AN_REG_CTRL, 0); 4384 /* Turn off CL73 */ 4385 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4386 MDIO_WC_REG_CL73_USERB0_CTRL, &val); 4387 val &= ~(1<<5); 4388 val |= (1<<6); 4389 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4390 MDIO_WC_REG_CL73_USERB0_CTRL, val); 4391 4392 /* Set 20G KR2 force speed */ 4393 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4394 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f); 4395 4396 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4397 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7)); 4398 4399 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4400 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val); 4401 val &= ~(3<<14); 4402 val |= (1<<15); 4403 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4404 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val); 4405 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4406 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A); 4407 4408 /* Enable sequencer (over lane 0) */ 4409 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4410 MDIO_AER_BLOCK_AER_REG, 0); 4411 4412 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4413 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13)); 4414 4415 elink_set_aer_mmd(params, phy); 4416 } 4417 #endif 4418 4419 #ifndef EXCLUDE_COMMON_INIT 4420 static void elink_warpcore_set_20G_DXGXS(struct elink_dev *cb, 4421 struct elink_phy *phy, 4422 u16 lane) 4423 { 4424 /* Rx0 anaRxControl1G */ 4425 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4426 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); 4427 4428 /* Rx2 anaRxControl1G */ 4429 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4430 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); 4431 4432 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4433 MDIO_WC_REG_RX66_SCW0, 0xE070); 4434 4435 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4436 MDIO_WC_REG_RX66_SCW1, 0xC0D0); 4437 4438 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4439 MDIO_WC_REG_RX66_SCW2, 0xA0B0); 4440 4441 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4442 MDIO_WC_REG_RX66_SCW3, 0x8090); 4443 4444 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4445 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); 4446 4447 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4448 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); 4449 4450 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4451 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); 4452 4453 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4454 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); 4455 4456 /* Serdes Digital Misc1 */ 4457 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4458 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); 4459 4460 /* Serdes Digital4 Misc3 */ 4461 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4462 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); 4463 4464 /* Set Transmit PMD settings */ 4465 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4466 MDIO_WC_REG_TX_FIR_TAP, 4467 (WC_TX_FIR(0x12, 0x2d, 0x00) | 4468 MDIO_WC_REG_TX_FIR_TAP_ENABLE)); 4469 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4470 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4471 WC_TX_DRIVER(0x02, 0x02, 0x02)); 4472 } 4473 #endif 4474 4475 #ifndef EXCLUDE_NON_COMMON_INIT 4476 static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy, 4477 struct elink_params *params, 4478 u8 fiber_mode, 4479 u8 always_autoneg) 4480 { 4481 struct elink_dev *cb = params->cb; 4482 u16 val16, digctrl_kx1, digctrl_kx2; 4483 4484 /* Clear XFI clock comp in non-10G single lane mode. */ 4485 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4486 MDIO_WC_REG_RX66_CONTROL, ~(3<<13)); 4487 4488 elink_warpcore_set_lpi_passthrough(phy, params); 4489 4490 if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { 4491 /* SGMII Autoneg */ 4492 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4493 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4494 0x1000); 4495 ELINK_DEBUG_P0(cb, "set SGMII AUTONEG\n"); 4496 } else { 4497 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4498 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4499 val16 &= 0xcebf; 4500 switch (phy->req_line_speed) { 4501 case ELINK_SPEED_10: 4502 break; 4503 case ELINK_SPEED_100: 4504 val16 |= 0x2000; 4505 break; 4506 case ELINK_SPEED_1000: 4507 val16 |= 0x0040; 4508 break; 4509 default: 4510 ELINK_DEBUG_P1(cb, 4511 "Speed not supported: 0x%x\n", phy->req_line_speed); 4512 return; 4513 } 4514 4515 if (phy->req_duplex == DUPLEX_FULL) 4516 val16 |= 0x0100; 4517 4518 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4519 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); 4520 4521 ELINK_DEBUG_P1(cb, "set SGMII force speed %d\n", 4522 phy->req_line_speed); 4523 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4524 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4525 ELINK_DEBUG_P1(cb, " (readback) %x\n", val16); 4526 } 4527 4528 /* SGMII Slave mode and disable signal detect */ 4529 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4530 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); 4531 if (fiber_mode) 4532 digctrl_kx1 = 1; 4533 else 4534 digctrl_kx1 &= 0xff4a; 4535 4536 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4537 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4538 digctrl_kx1); 4539 4540 /* Turn off parallel detect */ 4541 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4542 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); 4543 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4544 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4545 (digctrl_kx2 & ~(1<<2))); 4546 4547 /* Re-enable parallel detect */ 4548 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4549 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4550 (digctrl_kx2 | (1<<2))); 4551 4552 /* Enable autodet */ 4553 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4554 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4555 (digctrl_kx1 | 0x10)); 4556 } 4557 4558 #endif //EXCLUDE_NON_COMMON_INIT 4559 4560 static void elink_warpcore_reset_lane(struct elink_dev *cb, 4561 struct elink_phy *phy, 4562 u8 reset) 4563 { 4564 u16 val; 4565 /* Take lane out of reset after configuration is finished */ 4566 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4567 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4568 if (reset) 4569 val |= 0xC000; 4570 else 4571 val &= 0x3FFF; 4572 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4573 MDIO_WC_REG_DIGITAL5_MISC6, val); 4574 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4575 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4576 } 4577 4578 #ifndef EXCLUDE_NON_COMMON_INIT 4579 /* Clear SFI/XFI link settings registers */ 4580 static void elink_warpcore_clear_regs(struct elink_phy *phy, 4581 struct elink_params *params, 4582 u16 lane) 4583 { 4584 struct elink_dev *cb = params->cb; 4585 u16 i; 4586 static struct elink_reg_set wc_regs[] = { 4587 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, 4588 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, 4589 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, 4590 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, 4591 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4592 0x0195}, 4593 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4594 0x0007}, 4595 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4596 0x0002}, 4597 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, 4598 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, 4599 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, 4600 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} 4601 }; 4602 /* Set XFI clock comp as default. */ 4603 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4604 MDIO_WC_REG_RX66_CONTROL, (3<<13)); 4605 4606 for (i = 0; i < ARRAY_SIZE(wc_regs); i++) 4607 elink_cl45_write(cb, phy, wc_regs[i].devad, wc_regs[i].reg, 4608 wc_regs[i].val); 4609 4610 lane = elink_get_warpcore_lane(phy, params); 4611 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4612 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); 4613 4614 } 4615 4616 static elink_status_t elink_get_mod_abs_int_cfg(struct elink_dev *cb, 4617 u32 chip_id, 4618 u32 shmem_base, u8 port, 4619 u8 *gpio_num, u8 *gpio_port) 4620 { 4621 u32 cfg_pin; 4622 *gpio_num = 0; 4623 *gpio_port = 0; 4624 if (CHIP_IS_E3(chip_id)) { 4625 cfg_pin = (REG_RD(cb, shmem_base + 4626 OFFSETOF(struct shmem_region, 4627 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4628 PORT_HW_CFG_E3_MOD_ABS_MASK) >> 4629 PORT_HW_CFG_E3_MOD_ABS_SHIFT; 4630 4631 /* Should not happen. This function called upon interrupt 4632 * triggered by GPIO ( since EPIO can only generate interrupts 4633 * to MCP). 4634 * So if this function was called and none of the GPIOs was set, 4635 * it means the shit hit the fan. 4636 */ 4637 if ((cfg_pin < PIN_CFG_GPIO0_P0) || 4638 (cfg_pin > PIN_CFG_GPIO3_P1)) { 4639 ELINK_DEBUG_P1(cb, 4640 "No cfg pin %x for module detect indication\n", 4641 cfg_pin); 4642 return ELINK_STATUS_ERROR; 4643 } 4644 4645 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; 4646 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; 4647 } else { 4648 *gpio_num = MISC_REGISTERS_GPIO_3; 4649 *gpio_port = port; 4650 } 4651 4652 return ELINK_STATUS_OK; 4653 } 4654 4655 static int elink_is_sfp_module_plugged(struct elink_phy *phy, 4656 struct elink_params *params) 4657 { 4658 struct elink_dev *cb = params->cb; 4659 u8 gpio_num, gpio_port; 4660 u32 gpio_val; 4661 if (elink_get_mod_abs_int_cfg(cb, params->chip_id, 4662 params->shmem_base, params->port, 4663 &gpio_num, &gpio_port) != ELINK_STATUS_OK) 4664 return 0; 4665 gpio_val = ELINK_GET_GPIO(cb, gpio_num, gpio_port); 4666 4667 /* Call the handling function in case module is detected */ 4668 if (gpio_val == 0) 4669 return 1; 4670 else 4671 return 0; 4672 } 4673 int elink_warpcore_get_sigdet(struct elink_phy *phy, 4674 struct elink_params *params) 4675 { 4676 u16 gp2_status_reg0, lane; 4677 struct elink_dev *cb = params->cb; 4678 4679 lane = elink_get_warpcore_lane(phy, params); 4680 4681 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, 4682 &gp2_status_reg0); 4683 4684 return (gp2_status_reg0 >> (8+lane)) & 0x1; 4685 } 4686 4687 #ifndef ELINK_AUX_POWER 4688 static void elink_warpcore_config_runtime(struct elink_phy *phy, 4689 struct elink_params *params, 4690 struct elink_vars *vars) 4691 { 4692 struct elink_dev *cb = params->cb; 4693 u32 serdes_net_if; 4694 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0; 4695 4696 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; 4697 4698 if (!vars->turn_to_run_wc_rt) 4699 return; 4700 4701 if (vars->rx_tx_asic_rst) { 4702 u16 lane = elink_get_warpcore_lane(phy, params); 4703 serdes_net_if = (REG_RD(cb, params->shmem_base + 4704 OFFSETOF(struct shmem_region, dev_info. 4705 port_hw_config[params->port].default_cfg)) & 4706 PORT_HW_CFG_NET_SERDES_IF_MASK); 4707 4708 switch (serdes_net_if) { 4709 case PORT_HW_CFG_NET_SERDES_IF_KR: 4710 /* Do we get link yet? */ 4711 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 0x81d1, 4712 &gp_status1); 4713 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ 4714 /*10G KR*/ 4715 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; 4716 4717 if (lnkup_kr || lnkup) { 4718 vars->rx_tx_asic_rst = 0; 4719 } else { 4720 /* Reset the lane to see if link comes up.*/ 4721 elink_warpcore_reset_lane(cb, phy, 1); 4722 elink_warpcore_reset_lane(cb, phy, 0); 4723 4724 /* Restart Autoneg */ 4725 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 4726 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 4727 4728 vars->rx_tx_asic_rst--; 4729 ELINK_DEBUG_P1(cb, "0x%x retry left\n", 4730 vars->rx_tx_asic_rst); 4731 } 4732 break; 4733 4734 default: 4735 break; 4736 } 4737 4738 } /*params->rx_tx_asic_rst*/ 4739 4740 } 4741 #endif 4742 static void elink_warpcore_config_sfi(struct elink_phy *phy, 4743 struct elink_params *params) 4744 { 4745 u16 lane = elink_get_warpcore_lane(phy, params); 4746 #ifdef ELINK_DEBUG 4747 struct elink_dev *cb = params->cb; 4748 #endif 4749 elink_warpcore_clear_regs(phy, params, lane); 4750 if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] == 4751 ELINK_SPEED_10000) && 4752 (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) { 4753 ELINK_DEBUG_P0(cb, "Setting 10G SFI\n"); 4754 elink_warpcore_set_10G_XFI(phy, params, 0); 4755 } else { 4756 ELINK_DEBUG_P0(cb, "Setting 1G Fiber\n"); 4757 elink_warpcore_set_sgmii_speed(phy, params, 1, 0); 4758 } 4759 } 4760 4761 static void elink_sfp_e3_set_transmitter(struct elink_params *params, 4762 struct elink_phy *phy, 4763 u8 tx_en) 4764 { 4765 struct elink_dev *cb = params->cb; 4766 u32 cfg_pin; 4767 u8 port = params->port; 4768 4769 cfg_pin = REG_RD(cb, params->shmem_base + 4770 OFFSETOF(struct shmem_region, 4771 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4772 PORT_HW_CFG_E3_TX_LASER_MASK; 4773 /* Set the !tx_en since this pin is DISABLE_TX_LASER */ 4774 ELINK_DEBUG_P1(cb, "Setting WC TX to %d\n", tx_en); 4775 4776 /* For 20G, the expected pin to be used is 3 pins after the current */ 4777 elink_set_cfg_pin(cb, cfg_pin, tx_en ^ 1); 4778 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) 4779 elink_set_cfg_pin(cb, cfg_pin + 3, tx_en ^ 1); 4780 } 4781 4782 static void elink_warpcore_config_init(struct elink_phy *phy, 4783 struct elink_params *params, 4784 struct elink_vars *vars) 4785 { 4786 struct elink_dev *cb = params->cb; 4787 u32 serdes_net_if; 4788 u8 fiber_mode; 4789 u16 lane = elink_get_warpcore_lane(phy, params); 4790 serdes_net_if = (REG_RD(cb, params->shmem_base + 4791 OFFSETOF(struct shmem_region, dev_info. 4792 port_hw_config[params->port].default_cfg)) & 4793 PORT_HW_CFG_NET_SERDES_IF_MASK); 4794 ELINK_DEBUG_P2(cb, "Begin Warpcore init, link_speed %d, " 4795 "serdes_net_if = 0x%x\n", 4796 vars->line_speed, serdes_net_if); 4797 elink_set_aer_mmd(params, phy); 4798 elink_warpcore_reset_lane(cb, phy, 1); 4799 vars->phy_flags |= PHY_XGXS_FLAG; 4800 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || 4801 (phy->req_line_speed && 4802 ((phy->req_line_speed == ELINK_SPEED_100) || 4803 (phy->req_line_speed == ELINK_SPEED_10)))) { 4804 vars->phy_flags |= PHY_SGMII_FLAG; 4805 ELINK_DEBUG_P0(cb, "Setting SGMII mode\n"); 4806 elink_warpcore_clear_regs(phy, params, lane); 4807 elink_warpcore_set_sgmii_speed(phy, params, 0, 1); 4808 } else { 4809 switch (serdes_net_if) { 4810 case PORT_HW_CFG_NET_SERDES_IF_KR: 4811 /* Enable KR Auto Neg */ 4812 if (params->loopback_mode != ELINK_LOOPBACK_EXT) 4813 elink_warpcore_enable_AN_KR(phy, params, vars); 4814 else { 4815 ELINK_DEBUG_P0(cb, "Setting KR 10G-Force\n"); 4816 elink_warpcore_set_10G_KR(phy, params, vars); 4817 } 4818 break; 4819 4820 case PORT_HW_CFG_NET_SERDES_IF_XFI: 4821 elink_warpcore_clear_regs(phy, params, lane); 4822 if (vars->line_speed == ELINK_SPEED_10000) { 4823 ELINK_DEBUG_P0(cb, "Setting 10G XFI\n"); 4824 elink_warpcore_set_10G_XFI(phy, params, 1); 4825 } else { 4826 if (ELINK_SINGLE_MEDIA_DIRECT(params)) { 4827 ELINK_DEBUG_P0(cb, "1G Fiber\n"); 4828 fiber_mode = 1; 4829 } else { 4830 ELINK_DEBUG_P0(cb, "10/100/1G SGMII\n"); 4831 fiber_mode = 0; 4832 } 4833 elink_warpcore_set_sgmii_speed(phy, 4834 params, 4835 fiber_mode, 4836 0); 4837 } 4838 4839 break; 4840 4841 case PORT_HW_CFG_NET_SERDES_IF_SFI: 4842 /* Issue Module detection if module is plugged, or 4843 * enabled transmitter to avoid current leakage in case 4844 * no module is connected 4845 */ 4846 if ((params->loopback_mode == ELINK_LOOPBACK_NONE) || 4847 (params->loopback_mode == ELINK_LOOPBACK_EXT)) { 4848 if (elink_is_sfp_module_plugged(phy, params)) 4849 elink_sfp_module_detection(phy, params); 4850 else 4851 elink_sfp_e3_set_transmitter(params, 4852 phy, 1); 4853 } 4854 4855 elink_warpcore_config_sfi(phy, params); 4856 break; 4857 4858 #ifndef ELINK_AUX_POWER 4859 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 4860 if (vars->line_speed != ELINK_SPEED_20000) { 4861 ELINK_DEBUG_P0(cb, "Speed not supported yet\n"); 4862 return; 4863 } 4864 ELINK_DEBUG_P0(cb, "Setting 20G DXGXS\n"); 4865 elink_warpcore_set_20G_DXGXS(cb, phy, lane); 4866 /* Issue Module detection */ 4867 4868 elink_sfp_module_detection(phy, params); 4869 break; 4870 #endif 4871 case PORT_HW_CFG_NET_SERDES_IF_KR2: 4872 if (!params->loopback_mode) { 4873 elink_warpcore_enable_AN_KR(phy, params, vars); 4874 } else { 4875 #ifndef ELINK_AUX_POWER 4876 ELINK_DEBUG_P0(cb, "Setting KR 20G-Force\n"); 4877 elink_warpcore_set_20G_force_KR2(phy, params); 4878 #endif 4879 } 4880 break; 4881 default: 4882 ELINK_DEBUG_P1(cb, 4883 "Unsupported Serdes Net Interface 0x%x\n", 4884 serdes_net_if); 4885 return; 4886 } 4887 } 4888 4889 /* Take lane out of reset after configuration is finished */ 4890 elink_warpcore_reset_lane(cb, phy, 0); 4891 ELINK_DEBUG_P0(cb, "Exit config init\n"); 4892 } 4893 4894 static void elink_warpcore_link_reset(struct elink_phy *phy, 4895 struct elink_params *params) 4896 { 4897 #ifndef EXCLUDE_LINK_RESET 4898 struct elink_dev *cb = params->cb; 4899 u16 val16, lane; 4900 elink_sfp_e3_set_transmitter(params, phy, 0); 4901 elink_set_mdio_emac_per_phy(cb, params); 4902 elink_set_aer_mmd(params, phy); 4903 /* Global register */ 4904 elink_warpcore_reset_lane(cb, phy, 1); 4905 4906 /* Clear loopback settings (if any) */ 4907 /* 10G & 20G */ 4908 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4909 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF); 4910 4911 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4912 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe); 4913 4914 /* Update those 1-copy registers */ 4915 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4916 MDIO_AER_BLOCK_AER_REG, 0); 4917 /* Enable 1G MDIO (1-copy) */ 4918 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4919 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4920 ~0x10); 4921 4922 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4923 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); 4924 lane = elink_get_warpcore_lane(phy, params); 4925 /* Disable CL36 PCS Tx */ 4926 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4927 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 4928 val16 |= (0x11 << lane); 4929 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) 4930 val16 |= (0x22 << lane); 4931 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4932 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 4933 4934 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4935 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 4936 val16 &= ~(0x0303 << (lane << 1)); 4937 val16 |= (0x0101 << (lane << 1)); 4938 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) { 4939 val16 &= ~(0x0c0c << (lane << 1)); 4940 val16 |= (0x0404 << (lane << 1)); 4941 } 4942 4943 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4944 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 4945 /* Restore AER */ 4946 elink_set_aer_mmd(params, phy); 4947 #endif 4948 4949 } 4950 4951 static void elink_set_warpcore_loopback(struct elink_phy *phy, 4952 struct elink_params *params) 4953 { 4954 #ifdef ELINK_INCLUDE_LOOPBACK 4955 struct elink_dev *cb = params->cb; 4956 u16 val16; 4957 u32 lane; 4958 ELINK_DEBUG_P2(cb, "Setting Warpcore loopback type %x, speed %d\n", 4959 params->loopback_mode, phy->req_line_speed); 4960 4961 if (phy->req_line_speed < ELINK_SPEED_10000 || 4962 phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) { 4963 /* 10/100/1000/20G-KR2 */ 4964 4965 /* Update those 1-copy registers */ 4966 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4967 MDIO_AER_BLOCK_AER_REG, 0); 4968 /* Enable 1G MDIO (1-copy) */ 4969 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4970 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4971 0x10); 4972 /* Set 1G loopback based on lane (1-copy) */ 4973 lane = elink_get_warpcore_lane(phy, params); 4974 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4975 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); 4976 val16 |= (1<<lane); 4977 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) 4978 val16 |= (2<<lane); 4979 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4980 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 4981 val16); 4982 4983 /* Switch back to 4-copy registers */ 4984 elink_set_aer_mmd(params, phy); 4985 } else { 4986 /* 10G / 20G-DXGXS */ 4987 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4988 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4989 0x4000); 4990 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4991 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); 4992 } 4993 #endif // #ifdef ELINK_INCLUDE_LOOPBACK 4994 } 4995 #endif // EXCLUDE_NON_COMMON_INIT 4996 #endif // #ifndef EXCLUDE_WARPCORE 4997 4998 #ifdef INCLUDE_WARPCORE_UC_LOAD 4999 static void elink_warpcore_powerdown_secondport_lanes(struct elink_dev *cb, 5000 struct elink_phy *phy) 5001 { 5002 u16 path_swap_ovr, path_swap, i; 5003 u8 power_down_lanes[4]; 5004 5005 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5006 MDIO_WC_REG_XGXSBLK1_LANETEST0, 0); 5007 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5008 MDIO_WC_REG_XGXS_X2_CONTROL2, 0x29FB); 5009 5010 /* Figure out path swap value */ 5011 path_swap_ovr = REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); 5012 if (path_swap_ovr & 0x1) 5013 path_swap = (path_swap_ovr & 0x2); 5014 else 5015 path_swap = REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP); 5016 5017 /* Find which lanes to power down according to path swap value */ 5018 if (path_swap) { 5019 power_down_lanes[0] = 1; 5020 power_down_lanes[1] = 1; 5021 power_down_lanes[2] = 0; 5022 power_down_lanes[3] = 1; 5023 } else { 5024 power_down_lanes[0] = 0; 5025 power_down_lanes[1] = 1; 5026 power_down_lanes[2] = 1; 5027 power_down_lanes[3] = 1; 5028 } 5029 5030 /* Go through lanes which should be powered down */ 5031 for (i = 0; i < 4; i++) { 5032 if (power_down_lanes[i]) { 5033 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5034 MDIO_WC_REG_XGXSBLK1_LANECTRL3, 5035 (1 << i) | (1 << (4+i)) | 5036 (1 << 11)); 5037 5038 elink_cl45_read_and_write( 5039 cb, phy, MDIO_WC_DEVAD, 5040 MDIO_WC_REG_XGXSBLK1_LANECTRL0, 5041 ~((u16)((1 << i) | (1 << (4+i))))); 5042 } 5043 } 5044 } 5045 #endif //INCLUDE_WARPCORE_UC_LOAD 5046 5047 #ifdef INCLUDE_WARPCORE_UC_LOAD 5048 /** 5049 * elink_warpcore_sequencer 5050 * 5051 * @param cb 5052 * @param phy 5053 * @param enable - sequencer 5054 * 5055 * @return u32 5056 * 5057 * Before starting any of the specific speed/protocol flow, 5058 * there's need disable the sequencer and once all 5059 * configurations are made the sequencer will be enabled again. 5060 * That way it is guaranteed that improper link won't be 5061 * established during the init phase. 5062 */ 5063 static void elink_warpcore_sequencer(struct elink_dev *cb, 5064 struct elink_phy *phy, 5065 u8 enable){ 5066 5067 u16 val16; 5068 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5069 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, &val16); 5070 if(enable) 5071 val16 |= 0x2000; 5072 else 5073 val16 &= 0xDFFF; 5074 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5075 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, val16); 5076 } 5077 5078 static void elink_warpcore_set_lane_swap(struct elink_dev *cb, 5079 struct elink_phy *phy, 5080 u32 wc_lane_config) 5081 { 5082 u16 rx_lane_swap, tx_lane_swap, val16; 5083 rx_lane_swap = ((wc_lane_config & 5084 SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> 5085 SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); 5086 5087 tx_lane_swap = ((wc_lane_config & 5088 SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> 5089 SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); 5090 5091 /* Rx Lanes */ 5092 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5093 MDIO_WC_REG_XGXS_RX_LN_SWAP1, &val16); 5094 val16 &= 0xFF00; 5095 val16 |= rx_lane_swap; 5096 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5097 MDIO_WC_REG_XGXS_RX_LN_SWAP1, val16); 5098 5099 /* Tx Lanes */ 5100 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5101 MDIO_WC_REG_XGXS_TX_LN_SWAP1, &val16); 5102 val16 &= 0xFF00; 5103 val16 |= tx_lane_swap; 5104 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5105 MDIO_WC_REG_XGXS_TX_LN_SWAP1, val16); 5106 } 5107 5108 static void elink_warpcore_set_lane_polarity(struct elink_dev *cb, 5109 struct elink_phy *phy, 5110 u32 wc_lane_config) 5111 { 5112 /* Set RX polarity on all lanes; flip and enable the flip. */ 5113 if (wc_lane_config & SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED) 5114 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5115 MDIO_WC_REG_RX0_PCI_CTRL, (3<<2)); 5116 if (wc_lane_config & SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED) 5117 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5118 MDIO_WC_REG_RX1_PCI_CTRL, (3<<2)); 5119 if (wc_lane_config & SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED) 5120 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5121 MDIO_WC_REG_RX2_PCI_CTRL, (3<<2)); 5122 if (wc_lane_config & SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED) 5123 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5124 MDIO_WC_REG_RX3_PCI_CTRL, (3<<2)); 5125 /* Set TX polarity on all lanes */ 5126 if (wc_lane_config & SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED) 5127 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5128 MDIO_WC_REG_TX0_ANA_CTRL0, (1<<5)); 5129 if (wc_lane_config & SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED) 5130 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5131 MDIO_WC_REG_TX1_ANA_CTRL0, (1<<5)); 5132 if (wc_lane_config & SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED) 5133 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5134 MDIO_WC_REG_TX2_ANA_CTRL0, (1<<5)); 5135 if (wc_lane_config & SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED) 5136 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5137 MDIO_WC_REG_TX3_ANA_CTRL0, (1<<5)); 5138 } 5139 5140 static elink_status_t elink_reset_warpcore(struct elink_dev *cb) 5141 { 5142 u16 time; 5143 u32 pll_lock; 5144 ELINK_DEBUG_P0(cb, "Resetting Warpcore\n"); 5145 5146 REG_WR(cb, MISC_REG_WC0_RESET, 0xE); 5147 MSLEEP(cb, 1); 5148 REG_WR(cb, MISC_REG_WC0_RESET, 0xF); 5149 5150 for(time = 0; time < ELINK_MDIO_ACCESS_TIMEOUT; time++) { 5151 MSLEEP(cb, 1); 5152 pll_lock = REG_RD(cb, MISC_REG_WC0_PLL_LOCK); 5153 if (pll_lock & 0x1) { 5154 /* Flush all TX fifo */ 5155 REG_WR(cb, MISC_REG_WC0_RESET, 0x3FF); 5156 break; 5157 } 5158 } 5159 if (time == ELINK_MDIO_ACCESS_TIMEOUT) { 5160 ELINK_DEBUG_P0(cb, "BUG! WARPCORE is still in reset!\n"); 5161 return ELINK_STATUS_ERROR; 5162 } 5163 5164 return ELINK_STATUS_OK; 5165 } 5166 5167 5168 static void elink_warpcore_set_quad_mode(struct elink_dev *cb, 5169 struct elink_phy *phy) 5170 { 5171 u16 lane, val; 5172 /* Need to set lanes 0..3 */ 5173 for (lane = 0; lane < WC_LANE_MAX; lane++) { 5174 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 5175 MDIO_AER_BLOCK_AER_REG, lane); 5176 /* Reset Asic lane */ 5177 elink_warpcore_reset_lane(cb, phy, 1); 5178 // This access is required only for version 0xd101 of the WC FW 5179 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5180 MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL, 5181 &val); 5182 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5183 MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL, 5184 (val & 0xfe07) | 0x78); 5185 5186 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5187 MDIO_WC_REG_DSC_SMC, 0x8000); 5188 5189 /* Set on clock compensation in WC */ 5190 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5191 MDIO_WC_REG_RX66_CONTROL, 0x7415); 5192 5193 /* Set on clock compensation in WC 5194 * For WC/B0 programming register 0x8104 to value 0x8091 insures 5195 * that clock comensation in cl48 modes is enabled during 5196 * multi-port modes, and disabled during single port modes. 5197 */ 5198 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5199 MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G, 5200 0x8091); 5201 } 5202 } 5203 5204 static void elink_warpcore_set_dual_mode(struct elink_dev *cb, 5205 struct elink_phy *phy, 5206 u32 shmem_base) 5207 { 5208 u16 lane, val; 5209 u32 serdes_net_if; 5210 for (lane = 0; lane < WC_LANE_MAX; lane++) { 5211 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 5212 MDIO_AER_BLOCK_AER_REG, lane); 5213 5214 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5215 MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL, 5216 &val); 5217 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5218 MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL, 5219 (val & 0xfe07) | 0x50); 5220 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5221 MDIO_WC_REG_CL49_USERB0_CTRL, 5222 (3<<6)); 5223 5224 /* Set on clock compensation in WC 5225 * For WC/B0 programming register 0x8104 to value 0x8091 insures 5226 * that clock comensation in cl48 modes is enabled during 5227 * multi-port modes, and disabled during single port modes. 5228 */ 5229 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5230 MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G, 5231 0x8091); 5232 /* In dual port mode XFI compensation should be disabled by 5233 * setting 0x83C0[14:13] to 2'b00 for each port. 5234 */ 5235 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 5236 MDIO_WC_REG_RX66_CONTROL, ~(3<<13)); 5237 5238 /* This access is required only for version 0xd101 of the 5239 * WC FW 5240 */ 5241 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5242 MDIO_WC_REG_DSC_SMC, 0x8000); 5243 } 5244 5245 serdes_net_if = (REG_RD(cb, shmem_base + 5246 OFFSETOF(struct shmem_region, dev_info. 5247 port_hw_config[0].default_cfg)) & 5248 PORT_HW_CFG_NET_SERDES_IF_MASK); 5249 5250 /* Configure both ports to 20G to enable clock working on both ports */ 5251 for (lane = 0x200; lane <= 0x201; lane++) { 5252 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 5253 MDIO_AER_BLOCK_AER_REG, lane); 5254 elink_warpcore_reset_lane(cb, phy, 1); 5255 if (serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_DXGXS) 5256 elink_warpcore_set_20G_DXGXS(cb, phy, lane); 5257 } 5258 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5259 MDIO_WC_REG_RX1_PCI_CTRL, (1<<11)); 5260 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5261 MDIO_WC_REG_RX3_PCI_CTRL, (1<<11)); 5262 } 5263 5264 static elink_status_t elink_warpcore_load_uc(struct elink_dev *cb, 5265 struct elink_phy *phy) 5266 { 5267 u16 val, cnt; 5268 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 5269 MDIO_AER_BLOCK_AER_REG, 0); 5270 5271 /* Enable External memory access */ 5272 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5273 MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP, 0x0000); 5274 5275 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5276 MDIO_WC_REG_MICROBLK_CMD3, 0x0407); 5277 5278 /* Initialize ram memory prior to programming it */ 5279 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5280 MDIO_WC_REG_MICROBLK_CMD, 0x8000); 5281 5282 /* Wait for completion of memory initialization */ 5283 for (cnt = 0; cnt < ELINK_WC_UC_TIMEOUT; cnt++) { 5284 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5285 MDIO_WC_REG_MICROBLK_DL_STATUS , &val); 5286 if (val & 0x8000) 5287 break; 5288 USLEEP(cb, 1); 5289 } 5290 if (cnt >= ELINK_WC_UC_TIMEOUT) 5291 return ELINK_STATUS_TIMEOUT; 5292 5293 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, MDIO_WC_REG_UC_INFO_B1_CRC, 0); 5294 5295 /* Load Warpcore microcode for E3 and after */ 5296 elink_cb_load_warpcore_microcode(); 5297 5298 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5299 MDIO_WC_REG_MICROBLK_CMD3, 0x0404); 5300 5301 /* Turn off read_for_cmd bit, check for FW setting this later. */ 5302 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 5303 MDIO_WC_REG_DSC1B0_UC_CTRL, 5304 ~MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD); 5305 5306 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5307 MDIO_WC_REG_MICROBLK_CMD, 0x0810); 5308 for (cnt = 0; cnt < ELINK_WC_RDY_TIMEOUT_MSEC; cnt++) { 5309 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5310 MDIO_WC_REG_DSC1B0_UC_CTRL, &val); 5311 if (val & MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD) 5312 break; 5313 MSLEEP(cb, 1); 5314 } 5315 if (cnt >= ELINK_WC_RDY_TIMEOUT_MSEC) 5316 return ELINK_STATUS_TIMEOUT; 5317 5318 return ELINK_STATUS_OK; 5319 } 5320 #endif /* INCLUDE_WARPCORE_UC_LOAD */ 5321 5322 static void elink_sync_link(struct elink_params *params, 5323 struct elink_vars *vars) 5324 { 5325 #ifdef ELINK_DEBUG 5326 struct elink_dev *cb = params->cb; 5327 #endif 5328 u8 link_10g_plus; 5329 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 5330 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 5331 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); 5332 if (vars->link_up) { 5333 ELINK_DEBUG_P0(cb, "phy link up\n"); 5334 5335 vars->phy_link_up = 1; 5336 vars->duplex = DUPLEX_FULL; 5337 switch (vars->link_status & 5338 LINK_STATUS_SPEED_AND_DUPLEX_MASK) { 5339 case ELINK_LINK_10THD: 5340 vars->duplex = DUPLEX_HALF; 5341 /* Fall thru */ 5342 case ELINK_LINK_10TFD: 5343 vars->line_speed = ELINK_SPEED_10; 5344 break; 5345 5346 case ELINK_LINK_100TXHD: 5347 vars->duplex = DUPLEX_HALF; 5348 /* Fall thru */ 5349 case ELINK_LINK_100T4: 5350 case ELINK_LINK_100TXFD: 5351 vars->line_speed = ELINK_SPEED_100; 5352 break; 5353 5354 case ELINK_LINK_1000THD: 5355 vars->duplex = DUPLEX_HALF; 5356 /* Fall thru */ 5357 case ELINK_LINK_1000TFD: 5358 vars->line_speed = ELINK_SPEED_1000; 5359 break; 5360 5361 case ELINK_LINK_2500THD: 5362 vars->duplex = DUPLEX_HALF; 5363 /* Fall thru */ 5364 case ELINK_LINK_2500TFD: 5365 vars->line_speed = ELINK_SPEED_2500; 5366 break; 5367 5368 case ELINK_LINK_10GTFD: 5369 vars->line_speed = ELINK_SPEED_10000; 5370 break; 5371 case ELINK_LINK_20GTFD: 5372 vars->line_speed = ELINK_SPEED_20000; 5373 break; 5374 default: 5375 break; 5376 } 5377 vars->flow_ctrl = 0; 5378 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) 5379 vars->flow_ctrl |= ELINK_FLOW_CTRL_TX; 5380 5381 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) 5382 vars->flow_ctrl |= ELINK_FLOW_CTRL_RX; 5383 5384 if (!vars->flow_ctrl) 5385 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 5386 5387 if (vars->line_speed && 5388 ((vars->line_speed == ELINK_SPEED_10) || 5389 (vars->line_speed == ELINK_SPEED_100))) { 5390 vars->phy_flags |= PHY_SGMII_FLAG; 5391 } else { 5392 vars->phy_flags &= ~PHY_SGMII_FLAG; 5393 } 5394 #ifndef EXCLUDE_WARPCORE 5395 if (vars->line_speed && 5396 ELINK_USES_WARPCORE(params->chip_id) && 5397 (vars->line_speed == ELINK_SPEED_1000)) 5398 vars->phy_flags |= PHY_SGMII_FLAG; 5399 #endif /* #ifndef EXCLUDE_WARPCORE */ 5400 /* Anything 10 and over uses the bmac */ 5401 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000); 5402 5403 if (link_10g_plus) { 5404 if (ELINK_USES_WARPCORE(params->chip_id)) 5405 vars->mac_type = ELINK_MAC_TYPE_XMAC; 5406 else 5407 vars->mac_type = ELINK_MAC_TYPE_BMAC; 5408 } else { 5409 if (ELINK_USES_WARPCORE(params->chip_id)) 5410 vars->mac_type = ELINK_MAC_TYPE_UMAC; 5411 else 5412 vars->mac_type = ELINK_MAC_TYPE_EMAC; 5413 } 5414 } else { /* Link down */ 5415 ELINK_DEBUG_P0(cb, "phy link down\n"); 5416 5417 vars->phy_link_up = 0; 5418 5419 vars->line_speed = 0; 5420 vars->duplex = DUPLEX_FULL; 5421 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 5422 5423 /* Indicate no mac active */ 5424 vars->mac_type = ELINK_MAC_TYPE_NONE; 5425 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 5426 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 5427 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) 5428 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; 5429 } 5430 } 5431 5432 void elink_link_status_update(struct elink_params *params, 5433 struct elink_vars *vars) 5434 { 5435 struct elink_dev *cb = params->cb; 5436 u8 port = params->port; 5437 u32 sync_offset, media_types; 5438 /* Update PHY configuration */ 5439 set_phy_vars(params, vars); 5440 5441 vars->link_status = REG_RD(cb, params->shmem_base + 5442 OFFSETOF(struct shmem_region, 5443 port_mb[port].link_status)); 5444 5445 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */ 5446 if (params->loopback_mode != ELINK_LOOPBACK_NONE && 5447 params->loopback_mode != ELINK_LOOPBACK_EXT) 5448 vars->link_status |= LINK_STATUS_LINK_UP; 5449 5450 #ifndef EXCLUDE_NON_COMMON_INIT 5451 #ifndef EXCLUDE_WARPCORE 5452 if (elink_eee_has_cap(params)) 5453 vars->eee_status = REG_RD(cb, params->shmem2_base + 5454 OFFSETOF(struct shmem2_region, 5455 eee_status[params->port])); 5456 #endif 5457 #endif 5458 5459 vars->phy_flags = PHY_XGXS_FLAG; 5460 elink_sync_link(params, vars); 5461 /* Sync media type */ 5462 sync_offset = params->shmem_base + 5463 OFFSETOF(struct shmem_region, 5464 dev_info.port_hw_config[port].media_type); 5465 media_types = REG_RD(cb, sync_offset); 5466 5467 params->phy[ELINK_INT_PHY].media_type = 5468 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> 5469 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; 5470 params->phy[ELINK_EXT_PHY1].media_type = 5471 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> 5472 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; 5473 params->phy[ELINK_EXT_PHY2].media_type = 5474 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> 5475 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; 5476 ELINK_DEBUG_P1(cb, "media_types = 0x%x\n", media_types); 5477 5478 /* Sync AEU offset */ 5479 sync_offset = params->shmem_base + 5480 OFFSETOF(struct shmem_region, 5481 dev_info.port_hw_config[port].aeu_int_mask); 5482 5483 vars->aeu_int_mask = REG_RD(cb, sync_offset); 5484 5485 /* Sync PFC status */ 5486 if (vars->link_status & LINK_STATUS_PFC_ENABLED) 5487 params->feature_config_flags |= 5488 ELINK_FEATURE_CONFIG_PFC_ENABLED; 5489 else 5490 params->feature_config_flags &= 5491 ~ELINK_FEATURE_CONFIG_PFC_ENABLED; 5492 5493 if (SHMEM2_HAS(cb, params->shmem2_base, link_attr_sync)) 5494 params->link_attr_sync = SHMEM2_RD(cb, params->shmem2_base, 5495 link_attr_sync[params->port]); 5496 5497 ELINK_DEBUG_P3(cb, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", 5498 vars->link_status, vars->phy_link_up, vars->aeu_int_mask); 5499 ELINK_DEBUG_P3(cb, "line_speed %x duplex %x flow_ctrl 0x%x\n", 5500 vars->line_speed, vars->duplex, vars->flow_ctrl); 5501 } 5502 5503 #ifndef EXCLUDE_NON_COMMON_INIT 5504 #ifndef EXCLUDE_XGXS 5505 static void elink_set_master_ln(struct elink_params *params, 5506 struct elink_phy *phy) 5507 { 5508 struct elink_dev *cb = params->cb; 5509 u16 new_master_ln, ser_lane; 5510 ser_lane = ((params->lane_config & 5511 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 5512 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 5513 5514 /* Set the master_ln for AN */ 5515 CL22_RD_OVER_CL45(cb, phy, 5516 MDIO_REG_BANK_XGXS_BLOCK2, 5517 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 5518 &new_master_ln); 5519 5520 CL22_WR_OVER_CL45(cb, phy, 5521 MDIO_REG_BANK_XGXS_BLOCK2 , 5522 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 5523 (new_master_ln | ser_lane)); 5524 } 5525 5526 static elink_status_t elink_reset_unicore(struct elink_params *params, 5527 struct elink_phy *phy, 5528 u8 set_serdes) 5529 { 5530 struct elink_dev *cb = params->cb; 5531 u16 mii_control; 5532 u16 i; 5533 CL22_RD_OVER_CL45(cb, phy, 5534 MDIO_REG_BANK_COMBO_IEEE0, 5535 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); 5536 5537 /* Reset the unicore */ 5538 CL22_WR_OVER_CL45(cb, phy, 5539 MDIO_REG_BANK_COMBO_IEEE0, 5540 MDIO_COMBO_IEEE0_MII_CONTROL, 5541 (mii_control | 5542 MDIO_COMBO_IEEO_MII_CONTROL_RESET)); 5543 #ifndef EXCLUDE_SERDES 5544 if (set_serdes) 5545 elink_set_serdes_access(cb, params->port); 5546 #endif /* EXCLUDE_SERDES */ 5547 5548 /* Wait for the reset to self clear */ 5549 for (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) { 5550 USLEEP(cb, 5); 5551 5552 /* The reset erased the previous bank value */ 5553 CL22_RD_OVER_CL45(cb, phy, 5554 MDIO_REG_BANK_COMBO_IEEE0, 5555 MDIO_COMBO_IEEE0_MII_CONTROL, 5556 &mii_control); 5557 5558 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { 5559 USLEEP(cb, 5); 5560 return ELINK_STATUS_OK; 5561 } 5562 } 5563 5564 elink_cb_event_log(cb, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized," 5565 // " Port %d\n", 5566 5567 ELINK_DEBUG_P0(cb, "BUG! XGXS is still in reset!\n"); 5568 return ELINK_STATUS_ERROR; 5569 5570 } 5571 5572 static void elink_set_swap_lanes(struct elink_params *params, 5573 struct elink_phy *phy) 5574 { 5575 struct elink_dev *cb = params->cb; 5576 /* Each two bits represents a lane number: 5577 * No swap is 0123 => 0x1b no need to enable the swap 5578 */ 5579 u16 rx_lane_swap, tx_lane_swap; 5580 5581 rx_lane_swap = ((params->lane_config & 5582 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> 5583 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); 5584 tx_lane_swap = ((params->lane_config & 5585 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> 5586 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); 5587 5588 if (rx_lane_swap != 0x1b) { 5589 CL22_WR_OVER_CL45(cb, phy, 5590 MDIO_REG_BANK_XGXS_BLOCK2, 5591 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 5592 (rx_lane_swap | 5593 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | 5594 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); 5595 } else { 5596 CL22_WR_OVER_CL45(cb, phy, 5597 MDIO_REG_BANK_XGXS_BLOCK2, 5598 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); 5599 } 5600 5601 if (tx_lane_swap != 0x1b) { 5602 CL22_WR_OVER_CL45(cb, phy, 5603 MDIO_REG_BANK_XGXS_BLOCK2, 5604 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 5605 (tx_lane_swap | 5606 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); 5607 } else { 5608 CL22_WR_OVER_CL45(cb, phy, 5609 MDIO_REG_BANK_XGXS_BLOCK2, 5610 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); 5611 } 5612 } 5613 5614 static void elink_set_parallel_detection(struct elink_phy *phy, 5615 struct elink_params *params) 5616 { 5617 struct elink_dev *cb = params->cb; 5618 u16 control2; 5619 CL22_RD_OVER_CL45(cb, phy, 5620 MDIO_REG_BANK_SERDES_DIGITAL, 5621 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 5622 &control2); 5623 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 5624 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 5625 else 5626 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 5627 ELINK_DEBUG_P2(cb, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", 5628 phy->speed_cap_mask, control2); 5629 CL22_WR_OVER_CL45(cb, phy, 5630 MDIO_REG_BANK_SERDES_DIGITAL, 5631 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 5632 control2); 5633 5634 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 5635 (phy->speed_cap_mask & 5636 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 5637 ELINK_DEBUG_P0(cb, "XGXS\n"); 5638 5639 CL22_WR_OVER_CL45(cb, phy, 5640 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5641 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, 5642 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); 5643 5644 CL22_RD_OVER_CL45(cb, phy, 5645 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5646 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 5647 &control2); 5648 5649 5650 control2 |= 5651 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; 5652 5653 CL22_WR_OVER_CL45(cb, phy, 5654 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5655 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 5656 control2); 5657 5658 /* Disable parallel detection of HiG */ 5659 CL22_WR_OVER_CL45(cb, phy, 5660 MDIO_REG_BANK_XGXS_BLOCK2, 5661 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, 5662 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | 5663 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); 5664 } 5665 } 5666 5667 static void elink_set_autoneg(struct elink_phy *phy, 5668 struct elink_params *params, 5669 struct elink_vars *vars, 5670 u8 enable_cl73) 5671 { 5672 struct elink_dev *cb = params->cb; 5673 u16 reg_val; 5674 5675 /* CL37 Autoneg */ 5676 CL22_RD_OVER_CL45(cb, phy, 5677 MDIO_REG_BANK_COMBO_IEEE0, 5678 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 5679 5680 /* CL37 Autoneg Enabled */ 5681 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) 5682 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; 5683 else /* CL37 Autoneg Disabled */ 5684 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5685 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); 5686 5687 CL22_WR_OVER_CL45(cb, phy, 5688 MDIO_REG_BANK_COMBO_IEEE0, 5689 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5690 5691 /* Enable/Disable Autodetection */ 5692 5693 CL22_RD_OVER_CL45(cb, phy, 5694 MDIO_REG_BANK_SERDES_DIGITAL, 5695 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); 5696 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | 5697 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); 5698 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; 5699 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) 5700 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5701 else 5702 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5703 5704 CL22_WR_OVER_CL45(cb, phy, 5705 MDIO_REG_BANK_SERDES_DIGITAL, 5706 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); 5707 5708 /* Enable TetonII and BAM autoneg */ 5709 CL22_RD_OVER_CL45(cb, phy, 5710 MDIO_REG_BANK_BAM_NEXT_PAGE, 5711 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5712 ®_val); 5713 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) { 5714 /* Enable BAM aneg Mode and TetonII aneg Mode */ 5715 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5716 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5717 } else { 5718 /* TetonII and BAM Autoneg Disabled */ 5719 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5720 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5721 } 5722 CL22_WR_OVER_CL45(cb, phy, 5723 MDIO_REG_BANK_BAM_NEXT_PAGE, 5724 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5725 reg_val); 5726 5727 if (enable_cl73) { 5728 /* Enable Cl73 FSM status bits */ 5729 CL22_WR_OVER_CL45(cb, phy, 5730 MDIO_REG_BANK_CL73_USERB0, 5731 MDIO_CL73_USERB0_CL73_UCTRL, 5732 0xe); 5733 5734 /* Enable BAM Station Manager*/ 5735 CL22_WR_OVER_CL45(cb, phy, 5736 MDIO_REG_BANK_CL73_USERB0, 5737 MDIO_CL73_USERB0_CL73_BAM_CTRL1, 5738 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | 5739 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | 5740 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); 5741 5742 /* Advertise CL73 link speeds */ 5743 CL22_RD_OVER_CL45(cb, phy, 5744 MDIO_REG_BANK_CL73_IEEEB1, 5745 MDIO_CL73_IEEEB1_AN_ADV2, 5746 ®_val); 5747 if (phy->speed_cap_mask & 5748 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5749 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; 5750 if (phy->speed_cap_mask & 5751 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 5752 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; 5753 5754 CL22_WR_OVER_CL45(cb, phy, 5755 MDIO_REG_BANK_CL73_IEEEB1, 5756 MDIO_CL73_IEEEB1_AN_ADV2, 5757 reg_val); 5758 5759 /* CL73 Autoneg Enabled */ 5760 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; 5761 5762 } else /* CL73 Autoneg Disabled */ 5763 reg_val = 0; 5764 5765 CL22_WR_OVER_CL45(cb, phy, 5766 MDIO_REG_BANK_CL73_IEEEB0, 5767 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); 5768 } 5769 5770 /* Program SerDes, forced speed */ 5771 static void elink_program_serdes(struct elink_phy *phy, 5772 struct elink_params *params, 5773 struct elink_vars *vars) 5774 { 5775 struct elink_dev *cb = params->cb; 5776 u16 reg_val; 5777 5778 /* Program duplex, disable autoneg and sgmii*/ 5779 CL22_RD_OVER_CL45(cb, phy, 5780 MDIO_REG_BANK_COMBO_IEEE0, 5781 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 5782 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | 5783 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5784 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); 5785 if (phy->req_duplex == DUPLEX_FULL) 5786 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5787 CL22_WR_OVER_CL45(cb, phy, 5788 MDIO_REG_BANK_COMBO_IEEE0, 5789 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5790 5791 /* Program speed 5792 * - needed only if the speed is greater than 1G (2.5G or 10G) 5793 */ 5794 CL22_RD_OVER_CL45(cb, phy, 5795 MDIO_REG_BANK_SERDES_DIGITAL, 5796 MDIO_SERDES_DIGITAL_MISC1, ®_val); 5797 /* Clearing the speed value before setting the right speed */ 5798 ELINK_DEBUG_P1(cb, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); 5799 5800 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | 5801 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5802 5803 if (!((vars->line_speed == ELINK_SPEED_1000) || 5804 (vars->line_speed == ELINK_SPEED_100) || 5805 (vars->line_speed == ELINK_SPEED_10))) { 5806 5807 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | 5808 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5809 if (vars->line_speed == ELINK_SPEED_10000) 5810 reg_val |= 5811 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; 5812 } 5813 5814 CL22_WR_OVER_CL45(cb, phy, 5815 MDIO_REG_BANK_SERDES_DIGITAL, 5816 MDIO_SERDES_DIGITAL_MISC1, reg_val); 5817 5818 } 5819 5820 static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy, 5821 struct elink_params *params) 5822 { 5823 struct elink_dev *cb = params->cb; 5824 u16 val = 0; 5825 5826 /* Set extended capabilities */ 5827 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) 5828 val |= MDIO_OVER_1G_UP1_2_5G; 5829 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5830 val |= MDIO_OVER_1G_UP1_10G; 5831 CL22_WR_OVER_CL45(cb, phy, 5832 MDIO_REG_BANK_OVER_1G, 5833 MDIO_OVER_1G_UP1, val); 5834 5835 CL22_WR_OVER_CL45(cb, phy, 5836 MDIO_REG_BANK_OVER_1G, 5837 MDIO_OVER_1G_UP3, 0x400); 5838 } 5839 5840 static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy, 5841 struct elink_params *params, 5842 u16 ieee_fc) 5843 { 5844 struct elink_dev *cb = params->cb; 5845 u16 val; 5846 /* For AN, we are always publishing full duplex */ 5847 5848 CL22_WR_OVER_CL45(cb, phy, 5849 MDIO_REG_BANK_COMBO_IEEE0, 5850 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); 5851 CL22_RD_OVER_CL45(cb, phy, 5852 MDIO_REG_BANK_CL73_IEEEB1, 5853 MDIO_CL73_IEEEB1_AN_ADV1, &val); 5854 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; 5855 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); 5856 CL22_WR_OVER_CL45(cb, phy, 5857 MDIO_REG_BANK_CL73_IEEEB1, 5858 MDIO_CL73_IEEEB1_AN_ADV1, val); 5859 } 5860 5861 static void elink_restart_autoneg(struct elink_phy *phy, 5862 struct elink_params *params, 5863 u8 enable_cl73) 5864 { 5865 struct elink_dev *cb = params->cb; 5866 u16 mii_control; 5867 5868 ELINK_DEBUG_P0(cb, "elink_restart_autoneg\n"); 5869 /* Enable and restart BAM/CL37 aneg */ 5870 5871 if (enable_cl73) { 5872 CL22_RD_OVER_CL45(cb, phy, 5873 MDIO_REG_BANK_CL73_IEEEB0, 5874 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5875 &mii_control); 5876 5877 CL22_WR_OVER_CL45(cb, phy, 5878 MDIO_REG_BANK_CL73_IEEEB0, 5879 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5880 (mii_control | 5881 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | 5882 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); 5883 } else { 5884 5885 CL22_RD_OVER_CL45(cb, phy, 5886 MDIO_REG_BANK_COMBO_IEEE0, 5887 MDIO_COMBO_IEEE0_MII_CONTROL, 5888 &mii_control); 5889 ELINK_DEBUG_P1(cb, 5890 "elink_restart_autoneg mii_control before = 0x%x\n", 5891 mii_control); 5892 CL22_WR_OVER_CL45(cb, phy, 5893 MDIO_REG_BANK_COMBO_IEEE0, 5894 MDIO_COMBO_IEEE0_MII_CONTROL, 5895 (mii_control | 5896 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5897 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); 5898 } 5899 } 5900 5901 static void elink_initialize_sgmii_process(struct elink_phy *phy, 5902 struct elink_params *params, 5903 struct elink_vars *vars) 5904 { 5905 struct elink_dev *cb = params->cb; 5906 u16 control1; 5907 5908 /* In SGMII mode, the unicore is always slave */ 5909 5910 CL22_RD_OVER_CL45(cb, phy, 5911 MDIO_REG_BANK_SERDES_DIGITAL, 5912 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5913 &control1); 5914 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; 5915 /* Set sgmii mode (and not fiber) */ 5916 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | 5917 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | 5918 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); 5919 CL22_WR_OVER_CL45(cb, phy, 5920 MDIO_REG_BANK_SERDES_DIGITAL, 5921 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5922 control1); 5923 5924 /* If forced speed */ 5925 if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) { 5926 /* Set speed, disable autoneg */ 5927 u16 mii_control; 5928 5929 CL22_RD_OVER_CL45(cb, phy, 5930 MDIO_REG_BANK_COMBO_IEEE0, 5931 MDIO_COMBO_IEEE0_MII_CONTROL, 5932 &mii_control); 5933 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5934 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| 5935 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); 5936 5937 switch (vars->line_speed) { 5938 case ELINK_SPEED_100: 5939 mii_control |= 5940 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; 5941 break; 5942 case ELINK_SPEED_1000: 5943 mii_control |= 5944 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; 5945 break; 5946 case ELINK_SPEED_10: 5947 /* There is nothing to set for 10M */ 5948 break; 5949 default: 5950 /* Invalid speed for SGMII */ 5951 ELINK_DEBUG_P1(cb, "Invalid line_speed 0x%x\n", 5952 vars->line_speed); 5953 break; 5954 } 5955 5956 /* Setting the full duplex */ 5957 if (phy->req_duplex == DUPLEX_FULL) 5958 mii_control |= 5959 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5960 CL22_WR_OVER_CL45(cb, phy, 5961 MDIO_REG_BANK_COMBO_IEEE0, 5962 MDIO_COMBO_IEEE0_MII_CONTROL, 5963 mii_control); 5964 5965 } else { /* AN mode */ 5966 /* Enable and restart AN */ 5967 elink_restart_autoneg(phy, params, 0); 5968 } 5969 } 5970 5971 /* Link management 5972 */ 5973 static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy, 5974 struct elink_params *params) 5975 { 5976 struct elink_dev *cb = params->cb; 5977 u16 pd_10g, status2_1000x; 5978 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) 5979 return ELINK_STATUS_OK; 5980 CL22_RD_OVER_CL45(cb, phy, 5981 MDIO_REG_BANK_SERDES_DIGITAL, 5982 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5983 &status2_1000x); 5984 CL22_RD_OVER_CL45(cb, phy, 5985 MDIO_REG_BANK_SERDES_DIGITAL, 5986 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5987 &status2_1000x); 5988 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { 5989 ELINK_DEBUG_P1(cb, "1G parallel detect link on port %d\n", 5990 params->port); 5991 return 1; 5992 } 5993 5994 CL22_RD_OVER_CL45(cb, phy, 5995 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5996 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, 5997 &pd_10g); 5998 5999 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { 6000 ELINK_DEBUG_P1(cb, "10G parallel detect link on port %d\n", 6001 params->port); 6002 return 1; 6003 } 6004 return ELINK_STATUS_OK; 6005 } 6006 6007 static void elink_update_adv_fc(struct elink_phy *phy, 6008 struct elink_params *params, 6009 struct elink_vars *vars, 6010 u32 gp_status) 6011 { 6012 u16 ld_pause; /* local driver */ 6013 u16 lp_pause; /* link partner */ 6014 u16 pause_result; 6015 struct elink_dev *cb = params->cb; 6016 if ((gp_status & 6017 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 6018 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == 6019 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 6020 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { 6021 6022 CL22_RD_OVER_CL45(cb, phy, 6023 MDIO_REG_BANK_CL73_IEEEB1, 6024 MDIO_CL73_IEEEB1_AN_ADV1, 6025 &ld_pause); 6026 CL22_RD_OVER_CL45(cb, phy, 6027 MDIO_REG_BANK_CL73_IEEEB1, 6028 MDIO_CL73_IEEEB1_AN_LP_ADV1, 6029 &lp_pause); 6030 pause_result = (ld_pause & 6031 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; 6032 pause_result |= (lp_pause & 6033 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; 6034 ELINK_DEBUG_P1(cb, "pause_result CL73 0x%x\n", pause_result); 6035 } else { 6036 CL22_RD_OVER_CL45(cb, phy, 6037 MDIO_REG_BANK_COMBO_IEEE0, 6038 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, 6039 &ld_pause); 6040 CL22_RD_OVER_CL45(cb, phy, 6041 MDIO_REG_BANK_COMBO_IEEE0, 6042 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, 6043 &lp_pause); 6044 pause_result = (ld_pause & 6045 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; 6046 pause_result |= (lp_pause & 6047 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; 6048 ELINK_DEBUG_P1(cb, "pause_result CL37 0x%x\n", pause_result); 6049 } 6050 elink_pause_resolve(vars, pause_result); 6051 6052 } 6053 6054 static void elink_flow_ctrl_resolve(struct elink_phy *phy, 6055 struct elink_params *params, 6056 struct elink_vars *vars, 6057 u32 gp_status) 6058 { 6059 #ifdef ELINK_DEBUG 6060 struct elink_dev *cb = params->cb; 6061 #endif 6062 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 6063 6064 /* Resolve from gp_status in case of AN complete and not sgmii */ 6065 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) { 6066 /* Update the advertised flow-controled of LD/LP in AN */ 6067 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) 6068 elink_update_adv_fc(phy, params, vars, gp_status); 6069 /* But set the flow-control result as the requested one */ 6070 vars->flow_ctrl = phy->req_flow_ctrl; 6071 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) 6072 vars->flow_ctrl = params->req_fc_auto_adv; 6073 else if ((gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) && 6074 (!(vars->phy_flags & PHY_SGMII_FLAG))) { 6075 if (elink_direct_parallel_detect_used(phy, params)) { 6076 vars->flow_ctrl = params->req_fc_auto_adv; 6077 return; 6078 } 6079 elink_update_adv_fc(phy, params, vars, gp_status); 6080 } 6081 ELINK_DEBUG_P1(cb, "flow_ctrl 0x%x\n", vars->flow_ctrl); 6082 } 6083 6084 static void elink_check_fallback_to_cl37(struct elink_phy *phy, 6085 struct elink_params *params) 6086 { 6087 struct elink_dev *cb = params->cb; 6088 u16 rx_status, ustat_val, cl37_fsm_received; 6089 ELINK_DEBUG_P0(cb, "elink_check_fallback_to_cl37\n"); 6090 /* Step 1: Make sure signal is detected */ 6091 CL22_RD_OVER_CL45(cb, phy, 6092 MDIO_REG_BANK_RX0, 6093 MDIO_RX0_RX_STATUS, 6094 &rx_status); 6095 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != 6096 (MDIO_RX0_RX_STATUS_SIGDET)) { 6097 ELINK_DEBUG_P1(cb, "Signal is not detected. Restoring CL73." 6098 "rx_status(0x80b0) = 0x%x\n", rx_status); 6099 CL22_WR_OVER_CL45(cb, phy, 6100 MDIO_REG_BANK_CL73_IEEEB0, 6101 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 6102 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); 6103 return; 6104 } 6105 /* Step 2: Check CL73 state machine */ 6106 CL22_RD_OVER_CL45(cb, phy, 6107 MDIO_REG_BANK_CL73_USERB0, 6108 MDIO_CL73_USERB0_CL73_USTAT1, 6109 &ustat_val); 6110 if ((ustat_val & 6111 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 6112 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != 6113 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 6114 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { 6115 ELINK_DEBUG_P1(cb, "CL73 state-machine is not stable. " 6116 "ustat_val(0x8371) = 0x%x\n", ustat_val); 6117 return; 6118 } 6119 /* Step 3: Check CL37 Message Pages received to indicate LP 6120 * supports only CL37 6121 */ 6122 CL22_RD_OVER_CL45(cb, phy, 6123 MDIO_REG_BANK_REMOTE_PHY, 6124 MDIO_REMOTE_PHY_MISC_RX_STATUS, 6125 &cl37_fsm_received); 6126 if ((cl37_fsm_received & 6127 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 6128 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != 6129 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 6130 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { 6131 ELINK_DEBUG_P1(cb, "No CL37 FSM were received. " 6132 "misc_rx_status(0x8330) = 0x%x\n", 6133 cl37_fsm_received); 6134 return; 6135 } 6136 /* The combined cl37/cl73 fsm state information indicating that 6137 * we are connected to a device which does not support cl73, but 6138 * does support cl37 BAM. In this case we disable cl73 and 6139 * restart cl37 auto-neg 6140 */ 6141 6142 /* Disable CL73 */ 6143 CL22_WR_OVER_CL45(cb, phy, 6144 MDIO_REG_BANK_CL73_IEEEB0, 6145 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 6146 0); 6147 /* Restart CL37 autoneg */ 6148 elink_restart_autoneg(phy, params, 0); 6149 ELINK_DEBUG_P0(cb, "Disabling CL73, and restarting CL37 autoneg\n"); 6150 } 6151 6152 static void elink_xgxs_an_resolve(struct elink_phy *phy, 6153 struct elink_params *params, 6154 struct elink_vars *vars, 6155 u32 gp_status) 6156 { 6157 if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) 6158 vars->link_status |= 6159 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 6160 6161 if (elink_direct_parallel_detect_used(phy, params)) 6162 vars->link_status |= 6163 LINK_STATUS_PARALLEL_DETECTION_USED; 6164 } 6165 #endif /* EXCLUDE_XGXS */ 6166 static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy, 6167 struct elink_params *params, 6168 struct elink_vars *vars, 6169 u16 is_link_up, 6170 u16 speed_mask, 6171 u16 is_duplex) 6172 { 6173 #ifdef ELINK_DEBUG 6174 struct elink_dev *cb = params->cb; 6175 #endif 6176 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) 6177 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 6178 if (is_link_up) { 6179 ELINK_DEBUG_P0(cb, "phy link up\n"); 6180 6181 vars->phy_link_up = 1; 6182 vars->link_status |= LINK_STATUS_LINK_UP; 6183 6184 switch (speed_mask) { 6185 case ELINK_GP_STATUS_10M: 6186 vars->line_speed = ELINK_SPEED_10; 6187 if (is_duplex == DUPLEX_FULL) 6188 vars->link_status |= ELINK_LINK_10TFD; 6189 else 6190 vars->link_status |= ELINK_LINK_10THD; 6191 break; 6192 6193 case ELINK_GP_STATUS_100M: 6194 vars->line_speed = ELINK_SPEED_100; 6195 if (is_duplex == DUPLEX_FULL) 6196 vars->link_status |= ELINK_LINK_100TXFD; 6197 else 6198 vars->link_status |= ELINK_LINK_100TXHD; 6199 break; 6200 6201 case ELINK_GP_STATUS_1G: 6202 case ELINK_GP_STATUS_1G_KX: 6203 vars->line_speed = ELINK_SPEED_1000; 6204 if (is_duplex == DUPLEX_FULL) 6205 vars->link_status |= ELINK_LINK_1000TFD; 6206 else 6207 vars->link_status |= ELINK_LINK_1000THD; 6208 break; 6209 6210 case ELINK_GP_STATUS_2_5G: 6211 vars->line_speed = ELINK_SPEED_2500; 6212 if (is_duplex == DUPLEX_FULL) 6213 vars->link_status |= ELINK_LINK_2500TFD; 6214 else 6215 vars->link_status |= ELINK_LINK_2500THD; 6216 break; 6217 6218 case ELINK_GP_STATUS_5G: 6219 case ELINK_GP_STATUS_6G: 6220 ELINK_DEBUG_P1(cb, 6221 "link speed unsupported gp_status 0x%x\n", 6222 speed_mask); 6223 return ELINK_STATUS_ERROR; 6224 6225 case ELINK_GP_STATUS_10G_KX4: 6226 case ELINK_GP_STATUS_10G_HIG: 6227 case ELINK_GP_STATUS_10G_CX4: 6228 case ELINK_GP_STATUS_10G_KR: 6229 case ELINK_GP_STATUS_10G_SFI: 6230 case ELINK_GP_STATUS_10G_XFI: 6231 vars->line_speed = ELINK_SPEED_10000; 6232 vars->link_status |= ELINK_LINK_10GTFD; 6233 break; 6234 case ELINK_GP_STATUS_20G_DXGXS: 6235 case ELINK_GP_STATUS_20G_KR2: 6236 vars->line_speed = ELINK_SPEED_20000; 6237 vars->link_status |= ELINK_LINK_20GTFD; 6238 break; 6239 default: 6240 ELINK_DEBUG_P1(cb, 6241 "link speed unsupported gp_status 0x%x\n", 6242 speed_mask); 6243 return ELINK_STATUS_ERROR; 6244 } 6245 } else { /* link_down */ 6246 ELINK_DEBUG_P0(cb, "phy link down\n"); 6247 6248 vars->phy_link_up = 0; 6249 6250 vars->duplex = DUPLEX_FULL; 6251 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 6252 vars->mac_type = ELINK_MAC_TYPE_NONE; 6253 } 6254 ELINK_DEBUG_P2(cb, " phy_link_up %x line_speed %d\n", 6255 vars->phy_link_up, vars->line_speed); 6256 return ELINK_STATUS_OK; 6257 } 6258 6259 #ifndef EXCLUDE_XGXS 6260 static elink_status_t elink_link_settings_status(struct elink_phy *phy, 6261 struct elink_params *params, 6262 struct elink_vars *vars) 6263 { 6264 struct elink_dev *cb = params->cb; 6265 6266 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; 6267 elink_status_t rc = ELINK_STATUS_OK; 6268 6269 /* Read gp_status */ 6270 CL22_RD_OVER_CL45(cb, phy, 6271 MDIO_REG_BANK_GP_STATUS, 6272 MDIO_GP_STATUS_TOP_AN_STATUS1, 6273 &gp_status); 6274 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) 6275 duplex = DUPLEX_FULL; 6276 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) 6277 link_up = 1; 6278 speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK; 6279 ELINK_DEBUG_P3(cb, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", 6280 gp_status, link_up, speed_mask); 6281 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, 6282 duplex); 6283 if (rc == ELINK_STATUS_ERROR) 6284 return rc; 6285 6286 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { 6287 if (ELINK_SINGLE_MEDIA_DIRECT(params)) { 6288 vars->duplex = duplex; 6289 elink_flow_ctrl_resolve(phy, params, vars, gp_status); 6290 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) 6291 elink_xgxs_an_resolve(phy, params, vars, 6292 gp_status); 6293 } 6294 } else { /* Link_down */ 6295 if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 6296 ELINK_SINGLE_MEDIA_DIRECT(params)) { 6297 /* Check signal is detected */ 6298 elink_check_fallback_to_cl37(phy, params); 6299 } 6300 } 6301 6302 /* Read LP advertised speeds*/ 6303 if (ELINK_SINGLE_MEDIA_DIRECT(params) && 6304 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { 6305 u16 val; 6306 6307 CL22_RD_OVER_CL45(cb, phy, MDIO_REG_BANK_CL73_IEEEB1, 6308 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); 6309 6310 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 6311 vars->link_status |= 6312 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 6313 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 6314 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 6315 vars->link_status |= 6316 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 6317 6318 CL22_RD_OVER_CL45(cb, phy, MDIO_REG_BANK_OVER_1G, 6319 MDIO_OVER_1G_LP_UP1, &val); 6320 6321 if (val & MDIO_OVER_1G_UP1_2_5G) 6322 vars->link_status |= 6323 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 6324 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 6325 vars->link_status |= 6326 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 6327 } 6328 6329 ELINK_DEBUG_P3(cb, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 6330 vars->duplex, vars->flow_ctrl, vars->link_status); 6331 return rc; 6332 } 6333 #endif // EXCLUDE_XGXS 6334 6335 #ifndef EXCLUDE_WARPCORE 6336 static elink_status_t elink_warpcore_read_status(struct elink_phy *phy, 6337 struct elink_params *params, 6338 struct elink_vars *vars) 6339 { 6340 struct elink_dev *cb = params->cb; 6341 u8 lane; 6342 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; 6343 elink_status_t rc = ELINK_STATUS_OK; 6344 lane = elink_get_warpcore_lane(phy, params); 6345 /* Read gp_status */ 6346 if ((params->loopback_mode) && 6347 (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) { 6348 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6349 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 6350 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6351 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 6352 link_up &= 0x1; 6353 } else if ((phy->req_line_speed > ELINK_SPEED_10000) && 6354 (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) { 6355 u16 temp_link_up; 6356 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6357 1, &temp_link_up); 6358 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6359 1, &link_up); 6360 ELINK_DEBUG_P2(cb, "PCS RX link status = 0x%x-->0x%x\n", 6361 temp_link_up, link_up); 6362 link_up &= (1<<2); 6363 if (link_up) 6364 elink_ext_phy_resolve_fc(phy, params, vars); 6365 } else { 6366 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6367 MDIO_WC_REG_GP2_STATUS_GP_2_1, 6368 &gp_status1); 6369 ELINK_DEBUG_P1(cb, "0x81d1 = 0x%x\n", gp_status1); 6370 /* Check for either KR, 1G, or AN up. */ 6371 link_up = ((gp_status1 >> 8) | 6372 (gp_status1 >> 12) | 6373 (gp_status1)) & 6374 (1 << lane); 6375 if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) { 6376 u16 an_link; 6377 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 6378 MDIO_AN_REG_STATUS, &an_link); 6379 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 6380 MDIO_AN_REG_STATUS, &an_link); 6381 link_up |= (an_link & (1<<2)); 6382 } 6383 if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) { 6384 u16 pd, gp_status4; 6385 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { 6386 /* Check Autoneg complete */ 6387 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6388 MDIO_WC_REG_GP2_STATUS_GP_2_4, 6389 &gp_status4); 6390 if (gp_status4 & ((1<<12)<<lane)) 6391 vars->link_status |= 6392 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 6393 6394 /* Check parallel detect used */ 6395 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6396 MDIO_WC_REG_PAR_DET_10G_STATUS, 6397 &pd); 6398 if (pd & (1<<15)) 6399 vars->link_status |= 6400 LINK_STATUS_PARALLEL_DETECTION_USED; 6401 } 6402 elink_ext_phy_resolve_fc(phy, params, vars); 6403 vars->duplex = duplex; 6404 } 6405 } 6406 6407 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && 6408 ELINK_SINGLE_MEDIA_DIRECT(params)) { 6409 u16 val; 6410 6411 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 6412 MDIO_AN_REG_LP_AUTO_NEG2, &val); 6413 6414 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 6415 vars->link_status |= 6416 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 6417 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 6418 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 6419 vars->link_status |= 6420 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 6421 6422 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6423 MDIO_WC_REG_DIGITAL3_LP_UP1, &val); 6424 6425 if (val & MDIO_OVER_1G_UP1_2_5G) 6426 vars->link_status |= 6427 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 6428 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 6429 vars->link_status |= 6430 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 6431 6432 } 6433 6434 6435 if (lane < 2) { 6436 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6437 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); 6438 } else { 6439 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6440 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); 6441 } 6442 ELINK_DEBUG_P2(cb, "lane %d gp_speed 0x%x\n", lane, gp_speed); 6443 6444 if ((lane & 1) == 0) 6445 gp_speed <<= 8; 6446 gp_speed &= 0x3f00; 6447 link_up = !!link_up; 6448 6449 /* Reset the TX FIFO to fix SGMII issue */ 6450 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, 6451 duplex); 6452 6453 /* In case of KR link down, start up the recovering procedure */ 6454 if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) && 6455 (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE))) 6456 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 6457 6458 ELINK_DEBUG_P3(cb, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 6459 vars->duplex, vars->flow_ctrl, vars->link_status); 6460 return rc; 6461 } 6462 #endif /* #ifndef EXCLUDE_WARPCORE */ 6463 #ifndef EXCLUDE_XGXS 6464 static void elink_set_gmii_tx_driver(struct elink_params *params) 6465 { 6466 struct elink_dev *cb = params->cb; 6467 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; 6468 u16 lp_up2; 6469 u16 tx_driver; 6470 u16 bank; 6471 6472 /* Read precomp */ 6473 CL22_RD_OVER_CL45(cb, phy, 6474 MDIO_REG_BANK_OVER_1G, 6475 MDIO_OVER_1G_LP_UP2, &lp_up2); 6476 6477 /* Bits [10:7] at lp_up2, positioned at [15:12] */ 6478 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> 6479 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << 6480 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); 6481 6482 if (lp_up2 == 0) 6483 return; 6484 6485 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; 6486 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { 6487 CL22_RD_OVER_CL45(cb, phy, 6488 bank, 6489 MDIO_TX0_TX_DRIVER, &tx_driver); 6490 6491 /* Replace tx_driver bits [15:12] */ 6492 if (lp_up2 != 6493 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { 6494 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; 6495 tx_driver |= lp_up2; 6496 CL22_WR_OVER_CL45(cb, phy, 6497 bank, 6498 MDIO_TX0_TX_DRIVER, tx_driver); 6499 } 6500 } 6501 } 6502 6503 static elink_status_t elink_emac_program(struct elink_params *params, 6504 struct elink_vars *vars) 6505 { 6506 struct elink_dev *cb = params->cb; 6507 u8 port = params->port; 6508 u16 mode = 0; 6509 6510 ELINK_DEBUG_P0(cb, "setting link speed & duplex\n"); 6511 elink_bits_dis(cb, GRCBASE_EMAC0 + port*0x400 + 6512 EMAC_REG_EMAC_MODE, 6513 (EMAC_MODE_25G_MODE | 6514 EMAC_MODE_PORT_MII_10M | 6515 EMAC_MODE_HALF_DUPLEX)); 6516 switch (vars->line_speed) { 6517 case ELINK_SPEED_10: 6518 mode |= EMAC_MODE_PORT_MII_10M; 6519 break; 6520 6521 case ELINK_SPEED_100: 6522 mode |= EMAC_MODE_PORT_MII; 6523 break; 6524 6525 case ELINK_SPEED_1000: 6526 mode |= EMAC_MODE_PORT_GMII; 6527 break; 6528 6529 case ELINK_SPEED_2500: 6530 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); 6531 break; 6532 6533 default: 6534 /* 10G not valid for EMAC */ 6535 ELINK_DEBUG_P1(cb, "Invalid line_speed 0x%x\n", 6536 vars->line_speed); 6537 return ELINK_STATUS_ERROR; 6538 } 6539 6540 if (vars->duplex == DUPLEX_HALF) 6541 mode |= EMAC_MODE_HALF_DUPLEX; 6542 elink_bits_en(cb, 6543 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, 6544 mode); 6545 6546 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed); 6547 return ELINK_STATUS_OK; 6548 } 6549 6550 static void elink_set_preemphasis(struct elink_phy *phy, 6551 struct elink_params *params) 6552 { 6553 6554 u16 bank, i = 0; 6555 struct elink_dev *cb = params->cb; 6556 6557 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; 6558 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { 6559 CL22_WR_OVER_CL45(cb, phy, 6560 bank, 6561 MDIO_RX0_RX_EQ_BOOST, 6562 phy->rx_preemphasis[i]); 6563 } 6564 6565 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; 6566 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { 6567 CL22_WR_OVER_CL45(cb, phy, 6568 bank, 6569 MDIO_TX0_TX_DRIVER, 6570 phy->tx_preemphasis[i]); 6571 } 6572 } 6573 6574 static void elink_xgxs_config_init(struct elink_phy *phy, 6575 struct elink_params *params, 6576 struct elink_vars *vars) 6577 { 6578 #ifdef ELINK_DEBUG 6579 struct elink_dev *cb = params->cb; 6580 #endif 6581 u8 enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) || 6582 (params->loopback_mode == ELINK_LOOPBACK_XGXS)); 6583 if (!(vars->phy_flags & PHY_SGMII_FLAG)) { 6584 if (ELINK_SINGLE_MEDIA_DIRECT(params) && 6585 (params->feature_config_flags & 6586 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) 6587 elink_set_preemphasis(phy, params); 6588 6589 /* Forced speed requested? */ 6590 if (vars->line_speed != ELINK_SPEED_AUTO_NEG || 6591 (ELINK_SINGLE_MEDIA_DIRECT(params) && 6592 params->loopback_mode == ELINK_LOOPBACK_EXT)) { 6593 ELINK_DEBUG_P0(cb, "not SGMII, no AN\n"); 6594 6595 /* Disable autoneg */ 6596 elink_set_autoneg(phy, params, vars, 0); 6597 6598 /* Program speed and duplex */ 6599 elink_program_serdes(phy, params, vars); 6600 6601 } else { /* AN_mode */ 6602 ELINK_DEBUG_P0(cb, "not SGMII, AN\n"); 6603 6604 /* AN enabled */ 6605 elink_set_brcm_cl37_advertisement(phy, params); 6606 6607 /* Program duplex & pause advertisement (for aneg) */ 6608 elink_set_ieee_aneg_advertisement(phy, params, 6609 vars->ieee_fc); 6610 6611 /* Enable autoneg */ 6612 elink_set_autoneg(phy, params, vars, enable_cl73); 6613 6614 /* Enable and restart AN */ 6615 elink_restart_autoneg(phy, params, enable_cl73); 6616 } 6617 6618 } else { /* SGMII mode */ 6619 ELINK_DEBUG_P0(cb, "SGMII\n"); 6620 6621 elink_initialize_sgmii_process(phy, params, vars); 6622 } 6623 } 6624 6625 static elink_status_t elink_prepare_xgxs(struct elink_phy *phy, 6626 struct elink_params *params, 6627 struct elink_vars *vars) 6628 { 6629 elink_status_t rc; 6630 vars->phy_flags |= PHY_XGXS_FLAG; 6631 if ((phy->req_line_speed && 6632 ((phy->req_line_speed == ELINK_SPEED_100) || 6633 (phy->req_line_speed == ELINK_SPEED_10))) || 6634 (!phy->req_line_speed && 6635 (phy->speed_cap_mask >= 6636 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 6637 (phy->speed_cap_mask < 6638 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 6639 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) 6640 vars->phy_flags |= PHY_SGMII_FLAG; 6641 else 6642 vars->phy_flags &= ~PHY_SGMII_FLAG; 6643 6644 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 6645 elink_set_aer_mmd(params, phy); 6646 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 6647 elink_set_master_ln(params, phy); 6648 6649 rc = elink_reset_unicore(params, phy, 0); 6650 /* Reset the SerDes and wait for reset bit return low */ 6651 if (rc != ELINK_STATUS_OK) 6652 return rc; 6653 6654 elink_set_aer_mmd(params, phy); 6655 /* Setting the masterLn_def again after the reset */ 6656 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { 6657 elink_set_master_ln(params, phy); 6658 elink_set_swap_lanes(params, phy); 6659 } 6660 6661 return rc; 6662 } 6663 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 6664 #endif /* EXCLUDE_XGXS */ 6665 6666 #ifndef EXCLUDE_NON_COMMON_INIT 6667 #ifndef ELINK_EMUL_ONLY 6668 static u16 elink_wait_reset_complete(struct elink_dev *cb, 6669 struct elink_phy *phy, 6670 struct elink_params *params) 6671 { 6672 u16 cnt, ctrl; 6673 /* Wait for soft reset to get cleared up to 1 sec */ 6674 for (cnt = 0; cnt < 1000; cnt++) { 6675 #ifndef EXCLUDE_BCM54618SE 6676 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 6677 elink_cl22_read(cb, phy, 6678 MDIO_PMA_REG_CTRL, &ctrl); 6679 else 6680 #endif 6681 elink_cl45_read(cb, phy, 6682 MDIO_PMA_DEVAD, 6683 MDIO_PMA_REG_CTRL, &ctrl); 6684 if (!(ctrl & (1<<15))) 6685 break; 6686 MSLEEP(cb, 1); 6687 } 6688 6689 if (cnt == 1000) 6690 elink_cb_event_log(cb, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized," 6691 // " Port %d\n", 6692 6693 ELINK_DEBUG_P2(cb, "control reg 0x%x (after %d ms)\n", ctrl, cnt); 6694 return cnt; 6695 } 6696 #endif /* ELINK_EMUL_ONLY */ 6697 6698 static void elink_link_int_enable(struct elink_params *params) 6699 { 6700 u8 port = params->port; 6701 u32 mask; 6702 struct elink_dev *cb = params->cb; 6703 6704 /* Setting the status to report on link up for either XGXS or SerDes */ 6705 if (CHIP_IS_E3(params->chip_id)) { 6706 mask = ELINK_NIG_MASK_XGXS0_LINK_STATUS; 6707 if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) 6708 mask |= ELINK_NIG_MASK_MI_INT; 6709 } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) { 6710 mask = (ELINK_NIG_MASK_XGXS0_LINK10G | 6711 ELINK_NIG_MASK_XGXS0_LINK_STATUS); 6712 ELINK_DEBUG_P0(cb, "enabled XGXS interrupt\n"); 6713 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && 6714 params->phy[ELINK_INT_PHY].type != 6715 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { 6716 mask |= ELINK_NIG_MASK_MI_INT; 6717 ELINK_DEBUG_P0(cb, "enabled external phy int\n"); 6718 } 6719 6720 } else { /* SerDes */ 6721 mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS; 6722 ELINK_DEBUG_P0(cb, "enabled SerDes interrupt\n"); 6723 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && 6724 params->phy[ELINK_INT_PHY].type != 6725 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { 6726 mask |= ELINK_NIG_MASK_MI_INT; 6727 ELINK_DEBUG_P0(cb, "enabled external phy int\n"); 6728 } 6729 } 6730 elink_bits_en(cb, 6731 NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 6732 mask); 6733 6734 ELINK_DEBUG_P3(cb, "port %x, is_xgxs %x, int_status 0x%x\n", port, 6735 (params->switch_cfg == ELINK_SWITCH_CFG_10G), 6736 REG_RD(cb, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 6737 ELINK_DEBUG_P3(cb, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", 6738 REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 6739 REG_RD(cb, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), 6740 REG_RD(cb, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); 6741 ELINK_DEBUG_P2(cb, " 10G %x, XGXS_LINK %x\n", 6742 REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6743 REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6744 } 6745 6746 static void elink_rearm_latch_signal(struct elink_dev *cb, u8 port, 6747 u8 exp_mi_int) 6748 { 6749 u32 latch_status = 0; 6750 6751 /* Disable the MI INT ( external phy int ) by writing 1 to the 6752 * status register. Link down indication is high-active-signal, 6753 * so in this case we need to write the status to clear the XOR 6754 */ 6755 /* Read Latched signals */ 6756 latch_status = REG_RD(cb, 6757 NIG_REG_LATCH_STATUS_0 + port*8); 6758 ELINK_DEBUG_P1(cb, "latch_status = 0x%x\n", latch_status); 6759 /* Handle only those with latched-signal=up.*/ 6760 if (exp_mi_int) 6761 elink_bits_en(cb, 6762 NIG_REG_STATUS_INTERRUPT_PORT0 6763 + port*4, 6764 ELINK_NIG_STATUS_EMAC0_MI_INT); 6765 else 6766 elink_bits_dis(cb, 6767 NIG_REG_STATUS_INTERRUPT_PORT0 6768 + port*4, 6769 ELINK_NIG_STATUS_EMAC0_MI_INT); 6770 6771 if (latch_status & 1) { 6772 6773 /* For all latched-signal=up : Re-Arm Latch signals */ 6774 REG_WR(cb, NIG_REG_LATCH_STATUS_0 + port*8, 6775 (latch_status & 0xfffe) | (latch_status & 1)); 6776 } 6777 /* For all latched-signal=up,Write original_signal to status */ 6778 } 6779 6780 static void elink_link_int_ack(struct elink_params *params, 6781 struct elink_vars *vars, u8 is_10g_plus) 6782 { 6783 struct elink_dev *cb = params->cb; 6784 u8 port = params->port; 6785 u32 mask; 6786 /* First reset all status we assume only one line will be 6787 * change at a time 6788 */ 6789 elink_bits_dis(cb, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6790 (ELINK_NIG_STATUS_XGXS0_LINK10G | 6791 ELINK_NIG_STATUS_XGXS0_LINK_STATUS | 6792 ELINK_NIG_STATUS_SERDES0_LINK_STATUS)); 6793 if (vars->phy_link_up) { 6794 if (ELINK_USES_WARPCORE(params->chip_id)) 6795 mask = ELINK_NIG_STATUS_XGXS0_LINK_STATUS; 6796 else { 6797 if (is_10g_plus) 6798 mask = ELINK_NIG_STATUS_XGXS0_LINK10G; 6799 else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) { 6800 /* Disable the link interrupt by writing 1 to 6801 * the relevant lane in the status register 6802 */ 6803 u32 ser_lane = 6804 ((params->lane_config & 6805 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 6806 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 6807 mask = ((1 << ser_lane) << 6808 ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE); 6809 } else 6810 mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS; 6811 } 6812 ELINK_DEBUG_P1(cb, "Ack link up interrupt with mask 0x%x\n", 6813 mask); 6814 elink_bits_en(cb, 6815 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6816 mask); 6817 } 6818 } 6819 6820 #if !defined(ELINK_EMUL_ONLY) && (!defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_SFX7101) || !defined(EXCLUDE_BCM8705) || !defined(EXCLUDE_BCM87x6)) 6821 static elink_status_t elink_format_ver(u32 num, u8 *str, u16 *len) 6822 { 6823 #ifdef ELINK_ENHANCEMENTS 6824 u8 *str_ptr = str; 6825 u32 mask = 0xf0000000; 6826 u8 shift = 8*4; 6827 u8 digit; 6828 u8 remove_leading_zeros = 1; 6829 if (*len < 10) { 6830 /* Need more than 10chars for this format */ 6831 *str_ptr = '\0'; 6832 (*len)--; 6833 return ELINK_STATUS_ERROR; 6834 } 6835 while (shift > 0) { 6836 6837 shift -= 4; 6838 digit = ((num & mask) >> shift); 6839 if (digit == 0 && remove_leading_zeros) { 6840 mask = mask >> 4; 6841 continue; 6842 } else if (digit < 0xa) 6843 *str_ptr = digit + '0'; 6844 else 6845 *str_ptr = digit - 0xa + 'a'; 6846 remove_leading_zeros = 0; 6847 str_ptr++; 6848 (*len)--; 6849 mask = mask >> 4; 6850 if (shift == 4*4) { 6851 *str_ptr = '.'; 6852 str_ptr++; 6853 (*len)--; 6854 remove_leading_zeros = 1; 6855 } 6856 } 6857 #endif /* ELINK_ENHANCEMENTS */ 6858 return ELINK_STATUS_OK; 6859 } 6860 #endif /* ELINK_EMUL_ONLY */ 6861 6862 6863 #ifndef EXCLUDE_BCM8705 6864 static elink_status_t elink_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) 6865 { 6866 #ifdef ELINK_ENHANCEMENTS 6867 str[0] = '\0'; 6868 (*len)--; 6869 #endif // ELINK_ENHANCEMENTS 6870 return ELINK_STATUS_OK; 6871 } 6872 #endif // EXCLUDE_BCM8705 6873 6874 #ifdef ELINK_ENHANCEMENTS 6875 elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, u8 *version, 6876 u16 len) 6877 { 6878 struct elink_dev *cb; 6879 u32 spirom_ver = 0; 6880 elink_status_t status = ELINK_STATUS_OK; 6881 u8 *ver_p = version; 6882 u16 remain_len = len; 6883 if (version == NULL || params == NULL) 6884 return ELINK_STATUS_ERROR; 6885 cb = params->cb; 6886 6887 /* Extract first external phy*/ 6888 version[0] = '\0'; 6889 spirom_ver = REG_RD(cb, params->phy[ELINK_EXT_PHY1].ver_addr); 6890 6891 if (params->phy[ELINK_EXT_PHY1].format_fw_ver) { 6892 status |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver, 6893 ver_p, 6894 &remain_len); 6895 ver_p += (len - remain_len); 6896 } 6897 if ((params->num_phys == ELINK_MAX_PHYS) && 6898 (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) { 6899 spirom_ver = REG_RD(cb, params->phy[ELINK_EXT_PHY2].ver_addr); 6900 if (params->phy[ELINK_EXT_PHY2].format_fw_ver) { 6901 *ver_p = '/'; 6902 ver_p++; 6903 remain_len--; 6904 status |= params->phy[ELINK_EXT_PHY2].format_fw_ver( 6905 spirom_ver, 6906 ver_p, 6907 &remain_len); 6908 ver_p = version + (len - remain_len); 6909 } 6910 } 6911 *ver_p = '\0'; 6912 return status; 6913 } 6914 #endif // ELINK_ENHANCEMENTS 6915 6916 #ifndef EXCLUDE_XGXS 6917 static void elink_set_xgxs_loopback(struct elink_phy *phy, 6918 struct elink_params *params) 6919 { 6920 #ifdef ELINK_INCLUDE_LOOPBACK 6921 u8 port = params->port; 6922 struct elink_dev *cb = params->cb; 6923 6924 if (phy->req_line_speed != ELINK_SPEED_1000) { 6925 u32 md_devad = 0; 6926 6927 ELINK_DEBUG_P0(cb, "XGXS 10G loopback enable\n"); 6928 6929 if (!CHIP_IS_E3(params->chip_id)) { 6930 /* Change the uni_phy_addr in the nig */ 6931 md_devad = REG_RD(cb, (NIG_REG_XGXS0_CTRL_MD_DEVAD + 6932 port*0x18)); 6933 6934 REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6935 0x5); 6936 } 6937 6938 elink_cl45_write(cb, phy, 6939 5, 6940 (MDIO_REG_BANK_AER_BLOCK + 6941 (MDIO_AER_BLOCK_AER_REG & 0xf)), 6942 0x2800); 6943 6944 elink_cl45_write(cb, phy, 6945 5, 6946 (MDIO_REG_BANK_CL73_IEEEB0 + 6947 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), 6948 0x6041); 6949 MSLEEP(cb, 200); 6950 /* Set aer mmd back */ 6951 elink_set_aer_mmd(params, phy); 6952 6953 if (!CHIP_IS_E3(params->chip_id)) { 6954 /* And md_devad */ 6955 REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6956 md_devad); 6957 } 6958 } else { 6959 u16 mii_ctrl; 6960 ELINK_DEBUG_P0(cb, "XGXS 1G loopback enable\n"); 6961 elink_cl45_read(cb, phy, 5, 6962 (MDIO_REG_BANK_COMBO_IEEE0 + 6963 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6964 &mii_ctrl); 6965 elink_cl45_write(cb, phy, 5, 6966 (MDIO_REG_BANK_COMBO_IEEE0 + 6967 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6968 mii_ctrl | 6969 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); 6970 } 6971 #endif // ELINK_INCLUDE_LOOPBACK 6972 } 6973 #endif /* EXCLUDE_XGXS */ 6974 6975 elink_status_t elink_set_led(struct elink_params *params, 6976 struct elink_vars *vars, u8 mode, u32 speed) 6977 { 6978 u8 port = params->port; 6979 u16 hw_led_mode = params->hw_led_mode; 6980 elink_status_t rc = ELINK_STATUS_OK; 6981 u8 phy_idx; 6982 u32 tmp; 6983 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 6984 struct elink_dev *cb = params->cb; 6985 ELINK_DEBUG_P2(cb, "elink_set_led: port %x, mode %d\n", port, mode); 6986 ELINK_DEBUG_P2(cb, "speed 0x%x, hw_led_mode 0x%x\n", 6987 speed, hw_led_mode); 6988 /* In case */ 6989 for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 6990 if (params->phy[phy_idx].set_link_led) { 6991 params->phy[phy_idx].set_link_led( 6992 ¶ms->phy[phy_idx], params, mode); 6993 } 6994 } 6995 #ifdef ELINK_INCLUDE_EMUL 6996 if (params->feature_config_flags & 6997 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC) 6998 return rc; 6999 #endif 7000 7001 switch (mode) { 7002 case ELINK_LED_MODE_FRONT_PANEL_OFF: 7003 case ELINK_LED_MODE_OFF: 7004 REG_WR(cb, NIG_REG_LED_10G_P0 + port*4, 0); 7005 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 7006 SHARED_HW_CFG_LED_MAC1); 7007 7008 tmp = EMAC_RD(cb, EMAC_REG_EMAC_LED); 7009 if (params->phy[ELINK_EXT_PHY1].type == 7010 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 7011 tmp &= ~(EMAC_LED_1000MB_OVERRIDE | 7012 EMAC_LED_100MB_OVERRIDE | 7013 EMAC_LED_10MB_OVERRIDE); 7014 else 7015 tmp |= EMAC_LED_OVERRIDE; 7016 7017 EMAC_WR(cb, EMAC_REG_EMAC_LED, tmp); 7018 break; 7019 7020 case ELINK_LED_MODE_OPER: 7021 /* For all other phys, OPER mode is same as ON, so in case 7022 * link is down, do nothing 7023 */ 7024 if (!vars->link_up) 7025 break; 7026 /* FALLTHROUGH */ 7027 case ELINK_LED_MODE_ON: 7028 if (((params->phy[ELINK_EXT_PHY1].type == 7029 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || 7030 (params->phy[ELINK_EXT_PHY1].type == 7031 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && 7032 CHIP_IS_E2(params->chip_id) && params->num_phys == 2) { 7033 /* This is a work-around for E2+8727 Configurations */ 7034 if (mode == ELINK_LED_MODE_ON || 7035 speed == ELINK_SPEED_10000){ 7036 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 0); 7037 REG_WR(cb, NIG_REG_LED_10G_P0 + port*4, 1); 7038 7039 tmp = EMAC_RD(cb, EMAC_REG_EMAC_LED); 7040 EMAC_WR(cb, EMAC_REG_EMAC_LED, 7041 (tmp | EMAC_LED_OVERRIDE)); 7042 /* Return here without enabling traffic 7043 * LED blink and setting rate in ON mode. 7044 * In oper mode, enabling LED blink 7045 * and setting rate is needed. 7046 */ 7047 if (mode == ELINK_LED_MODE_ON) 7048 return rc; 7049 } 7050 } else if (ELINK_SINGLE_MEDIA_DIRECT(params)) { 7051 /* This is a work-around for HW issue found when link 7052 * is up in CL73 7053 */ 7054 if ((!CHIP_IS_E3(params->chip_id)) || 7055 (CHIP_IS_E3(params->chip_id) && 7056 mode == ELINK_LED_MODE_ON)) 7057 REG_WR(cb, NIG_REG_LED_10G_P0 + port*4, 1); 7058 7059 if (CHIP_IS_E1X(params->chip_id) || 7060 CHIP_IS_E2(params->chip_id) || 7061 (mode == ELINK_LED_MODE_ON)) 7062 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 0); 7063 else 7064 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 7065 hw_led_mode); 7066 } else if ((params->phy[ELINK_EXT_PHY1].type == 7067 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && 7068 (mode == ELINK_LED_MODE_ON)) { 7069 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 0); 7070 tmp = EMAC_RD(cb, EMAC_REG_EMAC_LED); 7071 EMAC_WR(cb, EMAC_REG_EMAC_LED, tmp | 7072 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); 7073 /* Break here; otherwise, it'll disable the 7074 * intended override. 7075 */ 7076 break; 7077 } else { 7078 u32 nig_led_mode = ((params->hw_led_mode << 7079 SHARED_HW_CFG_LED_MODE_SHIFT) == 7080 SHARED_HW_CFG_LED_EXTPHY2) ? 7081 (SHARED_HW_CFG_LED_PHY1 >> 7082 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode; 7083 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 7084 nig_led_mode); 7085 } 7086 7087 REG_WR(cb, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); 7088 /* Set blinking rate to ~15.9Hz */ 7089 if (CHIP_IS_E3(params->chip_id)) 7090 REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 7091 LED_BLINK_RATE_VAL_E3); 7092 else 7093 REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 7094 LED_BLINK_RATE_VAL_E1X_E2); 7095 REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + 7096 port*4, 1); 7097 tmp = EMAC_RD(cb, EMAC_REG_EMAC_LED); 7098 EMAC_WR(cb, EMAC_REG_EMAC_LED, 7099 (tmp & (~EMAC_LED_OVERRIDE))); 7100 7101 #ifndef ELINK_AUX_POWER 7102 if (CHIP_IS_E1(params->chip_id) && 7103 ((speed == ELINK_SPEED_2500) || 7104 (speed == ELINK_SPEED_1000) || 7105 (speed == ELINK_SPEED_100) || 7106 (speed == ELINK_SPEED_10))) { 7107 /* For speeds less than 10G LED scheme is different */ 7108 REG_WR(cb, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 7109 + port*4, 1); 7110 REG_WR(cb, NIG_REG_LED_CONTROL_TRAFFIC_P0 + 7111 port*4, 0); 7112 REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + 7113 port*4, 1); 7114 } 7115 #endif // ELINK_AUX_POWER 7116 break; 7117 7118 default: 7119 rc = ELINK_STATUS_ERROR; 7120 ELINK_DEBUG_P1(cb, "elink_set_led: Invalid led mode %d\n", 7121 mode); 7122 break; 7123 } 7124 return rc; 7125 7126 } 7127 7128 #endif // EXCLUDE_NON_COMMON_INIT 7129 #ifdef ELINK_ENHANCEMENTS 7130 /* This function comes to reflect the actual link state read DIRECTLY from the 7131 * HW 7132 */ 7133 elink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars, 7134 u8 is_serdes) 7135 { 7136 struct elink_dev *cb = params->cb; 7137 u16 gp_status = 0, phy_index = 0; 7138 u8 ext_phy_link_up = 0, serdes_phy_type; 7139 struct elink_vars temp_vars; 7140 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY]; 7141 #ifdef ELINK_INCLUDE_FPGA 7142 if (CHIP_REV_IS_FPGA(params->chip_id)) 7143 return ELINK_STATUS_OK; 7144 #endif /* ELINK_INCLUDE_FPGA */ 7145 #ifdef ELINK_INCLUDE_EMUL 7146 if (CHIP_REV_IS_EMUL(params->chip_id)) 7147 return ELINK_STATUS_OK; 7148 #endif /* ELINK_INCLUDE_EMUL */ 7149 7150 if (CHIP_IS_E3(params->chip_id)) { 7151 u16 link_up; 7152 if (params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] 7153 > ELINK_SPEED_10000) { 7154 /* Check 20G link */ 7155 elink_cl45_read(cb, int_phy, MDIO_WC_DEVAD, 7156 1, &link_up); 7157 elink_cl45_read(cb, int_phy, MDIO_WC_DEVAD, 7158 1, &link_up); 7159 link_up &= (1<<2); 7160 } else { 7161 /* Check 10G link and below*/ 7162 u8 lane = elink_get_warpcore_lane(int_phy, params); 7163 elink_cl45_read(cb, int_phy, MDIO_WC_DEVAD, 7164 MDIO_WC_REG_GP2_STATUS_GP_2_1, 7165 &gp_status); 7166 gp_status = ((gp_status >> 8) & 0xf) | 7167 ((gp_status >> 12) & 0xf); 7168 link_up = gp_status & (1 << lane); 7169 } 7170 if (!link_up) 7171 return ELINK_STATUS_NO_LINK; 7172 } else { 7173 CL22_RD_OVER_CL45(cb, int_phy, 7174 MDIO_REG_BANK_GP_STATUS, 7175 MDIO_GP_STATUS_TOP_AN_STATUS1, 7176 &gp_status); 7177 /* Link is up only if both local phy and external phy are up */ 7178 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) 7179 return ELINK_STATUS_NO_LINK; 7180 } 7181 /* In XGXS loopback mode, do not check external PHY */ 7182 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) 7183 return ELINK_STATUS_OK; 7184 7185 switch (params->num_phys) { 7186 case 1: 7187 /* No external PHY */ 7188 return ELINK_STATUS_OK; 7189 case 2: 7190 ext_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status( 7191 ¶ms->phy[ELINK_EXT_PHY1], 7192 params, &temp_vars); 7193 break; 7194 case 3: /* Dual Media */ 7195 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 7196 phy_index++) { 7197 serdes_phy_type = ((params->phy[phy_index].media_type == 7198 ELINK_ETH_PHY_SFPP_10G_FIBER) || 7199 (params->phy[phy_index].media_type == 7200 ELINK_ETH_PHY_SFP_1G_FIBER) || 7201 (params->phy[phy_index].media_type == 7202 ELINK_ETH_PHY_XFP_FIBER) || 7203 (params->phy[phy_index].media_type == 7204 ELINK_ETH_PHY_DA_TWINAX)); 7205 7206 if (is_serdes != serdes_phy_type) 7207 continue; 7208 if (params->phy[phy_index].read_status) { 7209 ext_phy_link_up |= 7210 params->phy[phy_index].read_status( 7211 ¶ms->phy[phy_index], 7212 params, &temp_vars); 7213 } 7214 } 7215 break; 7216 } 7217 if (ext_phy_link_up) 7218 return ELINK_STATUS_OK; 7219 return ELINK_STATUS_NO_LINK; 7220 } 7221 #endif // ELINK_ENHANCEMENT 7222 7223 #ifndef EXCLUDE_NON_COMMON_INIT 7224 static elink_status_t elink_link_initialize(struct elink_params *params, 7225 struct elink_vars *vars) 7226 { 7227 u8 phy_index, non_ext_phy; 7228 struct elink_dev *cb = params->cb; 7229 /* In case of external phy existence, the line speed would be the 7230 * line speed linked up by the external phy. In case it is direct 7231 * only, then the line_speed during initialization will be 7232 * equal to the req_line_speed 7233 */ 7234 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed; 7235 7236 /* Initialize the internal phy in case this is a direct board 7237 * (no external phys), or this board has external phy which requires 7238 * to first. 7239 */ 7240 #ifndef EXCLUDE_XGXS 7241 if (!ELINK_USES_WARPCORE(params->chip_id)) 7242 elink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars); 7243 #endif // EXCLUDE_XGXS 7244 /* init ext phy and enable link state int */ 7245 non_ext_phy = (ELINK_SINGLE_MEDIA_DIRECT(params) || 7246 (params->loopback_mode == ELINK_LOOPBACK_XGXS)); 7247 7248 if (non_ext_phy || 7249 (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) || 7250 (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) { 7251 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; 7252 #ifndef EXCLUDE_XGXS 7253 if (vars->line_speed == ELINK_SPEED_AUTO_NEG && 7254 (CHIP_IS_E1X(params->chip_id) || 7255 CHIP_IS_E2(params->chip_id))) 7256 elink_set_parallel_detection(phy, params); 7257 #endif // EXCLUDE_XGXS 7258 if (params->phy[ELINK_INT_PHY].config_init) 7259 params->phy[ELINK_INT_PHY].config_init(phy, params, vars); 7260 } 7261 7262 /* Re-read this value in case it was changed inside config_init due to 7263 * limitations of optic module 7264 */ 7265 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed; 7266 7267 /* Init external phy*/ 7268 if (non_ext_phy) { 7269 if (params->phy[ELINK_INT_PHY].supported & 7270 ELINK_SUPPORTED_FIBRE) 7271 vars->link_status |= LINK_STATUS_SERDES_LINK; 7272 } else { 7273 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 7274 phy_index++) { 7275 /* No need to initialize second phy in case of first 7276 * phy only selection. In case of second phy, we do 7277 * need to initialize the first phy, since they are 7278 * connected. 7279 */ 7280 if (params->phy[phy_index].supported & 7281 ELINK_SUPPORTED_FIBRE) 7282 vars->link_status |= LINK_STATUS_SERDES_LINK; 7283 7284 if (phy_index == ELINK_EXT_PHY2 && 7285 (elink_phy_selection(params) == 7286 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { 7287 ELINK_DEBUG_P0(cb, 7288 "Not initializing second phy\n"); 7289 continue; 7290 } 7291 params->phy[phy_index].config_init( 7292 ¶ms->phy[phy_index], 7293 params, vars); 7294 } 7295 } 7296 /* Reset the interrupt indication after phy was initialized */ 7297 elink_bits_dis(cb, NIG_REG_STATUS_INTERRUPT_PORT0 + 7298 params->port*4, 7299 (ELINK_NIG_STATUS_XGXS0_LINK10G | 7300 ELINK_NIG_STATUS_XGXS0_LINK_STATUS | 7301 ELINK_NIG_STATUS_SERDES0_LINK_STATUS | 7302 ELINK_NIG_MASK_MI_INT)); 7303 return ELINK_STATUS_OK; 7304 } 7305 7306 #ifndef EXCLUDE_XGXS 7307 static void elink_int_link_reset(struct elink_phy *phy, 7308 struct elink_params *params) 7309 { 7310 #ifndef EXCLUDE_LINK_RESET 7311 /* Reset the SerDes/XGXS */ 7312 REG_WR(params->cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, 7313 (0x1ff << (params->port*16))); 7314 #endif // EXCLUDE_LINK_RESET 7315 } 7316 #endif // EXCLUDE_XGXS 7317 7318 #if (!defined ELINK_EMUL_ONLY) && ((!defined EXCLUDE_BCM87x6) || (!defined EXCLUDE_SFX7101) || (!defined EXCLUDE_BCM8705)) 7319 static void elink_common_ext_link_reset(struct elink_phy *phy, 7320 struct elink_params *params) 7321 { 7322 #ifndef EXCLUDE_LINK_RESET 7323 struct elink_dev *cb = params->cb; 7324 u8 gpio_port; 7325 /* HW reset */ 7326 if (CHIP_IS_E2(params->chip_id)) 7327 gpio_port = PATH_ID(cb); 7328 else 7329 gpio_port = params->port; 7330 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1, 7331 MISC_REGISTERS_GPIO_OUTPUT_LOW, 7332 gpio_port); 7333 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 7334 MISC_REGISTERS_GPIO_OUTPUT_LOW, 7335 gpio_port); 7336 ELINK_DEBUG_P0(cb, "reset external PHY\n"); 7337 #endif /* EXCLUDE_LINK_RESET */ 7338 } 7339 #endif /* ELINK_EMUL_ONLY */ 7340 7341 static elink_status_t elink_update_link_down(struct elink_params *params, 7342 struct elink_vars *vars) 7343 { 7344 struct elink_dev *cb = params->cb; 7345 u8 port = params->port; 7346 7347 ELINK_DEBUG_P1(cb, "Port %x: Link is down\n", port); 7348 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0); 7349 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; 7350 /* Indicate no mac active */ 7351 vars->mac_type = ELINK_MAC_TYPE_NONE; 7352 7353 /* Update shared memory */ 7354 vars->link_status &= ~ELINK_LINK_UPDATE_MASK; 7355 vars->line_speed = 0; 7356 elink_update_mng(params, vars->link_status); 7357 7358 /* Activate nig drain */ 7359 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 7360 7361 /* Disable emac */ 7362 if (!CHIP_IS_E3(params->chip_id)) 7363 REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 0); 7364 7365 MSLEEP(cb, 10); 7366 #if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) 7367 /* Reset BigMac/Xmac */ 7368 if (CHIP_IS_E1X(params->chip_id) || 7369 CHIP_IS_E2(params->chip_id)) 7370 elink_set_bmac_rx(cb, params->chip_id, params->port, 0); 7371 #endif // #if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) 7372 7373 #ifndef EXCLUDE_WARPCORE 7374 if (CHIP_IS_E3(params->chip_id)) { 7375 /* Prevent LPI Generation by chip */ 7376 REG_WR(cb, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 7377 0); 7378 REG_WR(cb, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), 7379 0); 7380 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 7381 SHMEM_EEE_ACTIVE_BIT); 7382 7383 elink_update_mng_eee(params, vars->eee_status); 7384 elink_set_xmac_rxtx(params, 0); 7385 elink_set_umac_rxtx(params, 0); 7386 } 7387 #endif // EXCLUDE_WARPCORE 7388 7389 return ELINK_STATUS_OK; 7390 } 7391 7392 static elink_status_t elink_update_link_up(struct elink_params *params, 7393 struct elink_vars *vars, 7394 u8 link_10g) 7395 { 7396 struct elink_dev *cb = params->cb; 7397 u8 phy_idx, port = params->port; 7398 elink_status_t rc = ELINK_STATUS_OK; 7399 7400 vars->link_status |= (LINK_STATUS_LINK_UP | 7401 LINK_STATUS_PHYSICAL_LINK_FLAG); 7402 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 7403 7404 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) 7405 vars->link_status |= 7406 LINK_STATUS_TX_FLOW_CONTROL_ENABLED; 7407 7408 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) 7409 vars->link_status |= 7410 LINK_STATUS_RX_FLOW_CONTROL_ENABLED; 7411 #ifndef EXCLUDE_WARPCORE 7412 if (ELINK_USES_WARPCORE(params->chip_id)) { 7413 if (link_10g) { 7414 if (elink_xmac_enable(params, vars, 0) == 7415 ELINK_STATUS_NO_LINK) { 7416 ELINK_DEBUG_P0(cb, "Found errors on XMAC\n"); 7417 vars->link_up = 0; 7418 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 7419 vars->link_status &= ~LINK_STATUS_LINK_UP; 7420 } 7421 } else 7422 elink_umac_enable(params, vars, 0); 7423 elink_set_led(params, vars, 7424 ELINK_LED_MODE_OPER, vars->line_speed); 7425 7426 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && 7427 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { 7428 ELINK_DEBUG_P0(cb, "Enabling LPI assertion\n"); 7429 REG_WR(cb, MISC_REG_CPMU_LP_FW_ENABLE_P0 + 7430 (params->port << 2), 1); 7431 REG_WR(cb, MISC_REG_CPMU_LP_DR_ENABLE, 1); 7432 REG_WR(cb, MISC_REG_CPMU_LP_MASK_ENT_P0 + 7433 (params->port << 2), 0xfc20); 7434 } 7435 } 7436 #endif // EXCLUDE_WARPCORE 7437 #ifndef EXCLUDE_XGXS 7438 if ((CHIP_IS_E1X(params->chip_id) || 7439 CHIP_IS_E2(params->chip_id))) { 7440 if (link_10g) { 7441 if (elink_bmac_enable(params, vars, 0, 1) == 7442 ELINK_STATUS_NO_LINK) { 7443 ELINK_DEBUG_P0(cb, "Found errors on BMAC\n"); 7444 vars->link_up = 0; 7445 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 7446 vars->link_status &= ~LINK_STATUS_LINK_UP; 7447 } 7448 7449 elink_set_led(params, vars, 7450 ELINK_LED_MODE_OPER, ELINK_SPEED_10000); 7451 } else { 7452 rc = elink_emac_program(params, vars); 7453 elink_emac_enable(params, vars, 0); 7454 7455 /* AN complete? */ 7456 if ((vars->link_status & 7457 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) 7458 && (!(vars->phy_flags & PHY_SGMII_FLAG)) && 7459 ELINK_SINGLE_MEDIA_DIRECT(params)) 7460 elink_set_gmii_tx_driver(params); 7461 } 7462 } 7463 #endif // EXCLUDE_XGXS 7464 7465 #ifndef ELINK_AUX_POWER 7466 /* PBF - link up */ 7467 if (CHIP_IS_E1X(params->chip_id)) 7468 rc |= elink_pbf_update(params, vars->flow_ctrl, 7469 vars->line_speed); 7470 #endif /* ELINK_AUX_POWER */ 7471 7472 /* Disable drain */ 7473 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); 7474 7475 /* Update shared memory */ 7476 elink_update_mng(params, vars->link_status); 7477 #ifndef EXCLUDE_WARPCORE 7478 elink_update_mng_eee(params, vars->eee_status); 7479 #endif /* #ifndef EXCLUDE_WARPCORE */ 7480 /* Check remote fault */ 7481 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 7482 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) { 7483 elink_check_half_open_conn(params, vars, 0); 7484 break; 7485 } 7486 } 7487 MSLEEP(cb, 20); 7488 return rc; 7489 } 7490 7491 static void elink_chng_link_count(struct elink_params *params, u8 clear) 7492 { 7493 struct elink_dev *cb = params->cb; 7494 u32 addr, val; 7495 7496 /* Verify the link_change_count is supported by the MFW */ 7497 if (!(SHMEM2_HAS(cb, params->shmem2_base, link_change_count))) 7498 return; 7499 7500 addr = params->shmem2_base + 7501 OFFSETOF(struct shmem2_region, link_change_count[params->port]); 7502 if (clear) 7503 val = 0; 7504 else 7505 val = REG_RD(cb, addr) + 1; 7506 REG_WR(cb, addr, val); 7507 } 7508 7509 /* The elink_link_update function should be called upon link 7510 * interrupt. 7511 * Link is considered up as follows: 7512 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs 7513 * to be up 7514 * - SINGLE_MEDIA - The link between the 577xx and the external 7515 * phy (XGXS) need to up as well as the external link of the 7516 * phy (PHY_EXT1) 7517 * - DUAL_MEDIA - The link between the 577xx and the first 7518 * external phy needs to be up, and at least one of the 2 7519 * external phy link must be up. 7520 */ 7521 elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars) 7522 { 7523 struct elink_dev *cb = params->cb; 7524 struct elink_vars phy_vars[ELINK_MAX_PHYS]; 7525 u8 port = params->port; 7526 u8 link_10g_plus, phy_index; 7527 u32 prev_link_status = vars->link_status; 7528 u8 ext_phy_link_up = 0, cur_link_up; 7529 elink_status_t rc = ELINK_STATUS_OK; 7530 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; 7531 u8 active_external_phy = ELINK_INT_PHY; 7532 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; 7533 vars->link_status &= ~ELINK_LINK_UPDATE_MASK; 7534 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; 7535 phy_index++) { 7536 phy_vars[phy_index].flow_ctrl = 0; 7537 phy_vars[phy_index].link_status = 0; 7538 phy_vars[phy_index].line_speed = 0; 7539 phy_vars[phy_index].duplex = DUPLEX_FULL; 7540 phy_vars[phy_index].phy_link_up = 0; 7541 phy_vars[phy_index].link_up = 0; 7542 phy_vars[phy_index].fault_detected = 0; 7543 /* different consideration, since vars holds inner state */ 7544 phy_vars[phy_index].eee_status = vars->eee_status; 7545 } 7546 7547 if (ELINK_USES_WARPCORE(params->chip_id)) 7548 elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]); 7549 7550 ELINK_DEBUG_P3(cb, "port %x, XGXS?%x, int_status 0x%x\n", 7551 port, (vars->phy_flags & PHY_XGXS_FLAG), 7552 REG_RD(cb, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 7553 7554 ELINK_DEBUG_P3(cb, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", 7555 REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 7556 REG_RD(cb, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18) > 0, 7557 REG_RD(cb, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); 7558 7559 ELINK_DEBUG_P2(cb, " 10G %x, XGXS_LINK %x\n", 7560 REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 7561 REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 7562 7563 /* Disable emac */ 7564 if (!CHIP_IS_E3(params->chip_id)) 7565 REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 0); 7566 7567 /* Step 1: 7568 * Check external link change only for external phys, and apply 7569 * priority selection between them in case the link on both phys 7570 * is up. Note that instead of the common vars, a temporary 7571 * vars argument is used since each phy may have different link/ 7572 * speed/duplex result 7573 */ 7574 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 7575 phy_index++) { 7576 struct elink_phy *phy = ¶ms->phy[phy_index]; 7577 if (!phy->read_status) 7578 continue; 7579 /* Read link status and params of this ext phy */ 7580 cur_link_up = phy->read_status(phy, params, 7581 &phy_vars[phy_index]); 7582 if (cur_link_up) { 7583 ELINK_DEBUG_P1(cb, "phy in index %d link is up\n", 7584 phy_index); 7585 } else { 7586 ELINK_DEBUG_P1(cb, "phy in index %d link is down\n", 7587 phy_index); 7588 continue; 7589 } 7590 7591 if (!ext_phy_link_up) { 7592 ext_phy_link_up = 1; 7593 active_external_phy = phy_index; 7594 } else { 7595 switch (elink_phy_selection(params)) { 7596 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 7597 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 7598 /* In this option, the first PHY makes sure to pass the 7599 * traffic through itself only. 7600 * Its not clear how to reset the link on the second phy 7601 */ 7602 active_external_phy = ELINK_EXT_PHY1; 7603 break; 7604 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 7605 /* In this option, the first PHY makes sure to pass the 7606 * traffic through the second PHY. 7607 */ 7608 active_external_phy = ELINK_EXT_PHY2; 7609 break; 7610 default: 7611 /* Link indication on both PHYs with the following cases 7612 * is invalid: 7613 * - FIRST_PHY means that second phy wasn't initialized, 7614 * hence its link is expected to be down 7615 * - SECOND_PHY means that first phy should not be able 7616 * to link up by itself (using configuration) 7617 * - DEFAULT should be overriden during initialiazation 7618 */ 7619 ELINK_DEBUG_P1(cb, "Invalid link indication" 7620 "mpc=0x%x. DISABLING LINK !!!\n", 7621 params->multi_phy_config); 7622 ext_phy_link_up = 0; 7623 break; 7624 } 7625 } 7626 } 7627 prev_line_speed = vars->line_speed; 7628 /* Step 2: 7629 * Read the status of the internal phy. In case of 7630 * DIRECT_SINGLE_MEDIA board, this link is the external link, 7631 * otherwise this is the link between the 577xx and the first 7632 * external phy 7633 */ 7634 if (params->phy[ELINK_INT_PHY].read_status) 7635 params->phy[ELINK_INT_PHY].read_status( 7636 ¶ms->phy[ELINK_INT_PHY], 7637 params, vars); 7638 /* The INT_PHY flow control reside in the vars. This include the 7639 * case where the speed or flow control are not set to AUTO. 7640 * Otherwise, the active external phy flow control result is set 7641 * to the vars. The ext_phy_line_speed is needed to check if the 7642 * speed is different between the internal phy and external phy. 7643 * This case may be result of intermediate link speed change. 7644 */ 7645 if (active_external_phy > ELINK_INT_PHY) { 7646 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; 7647 /* Link speed is taken from the XGXS. AN and FC result from 7648 * the external phy. 7649 */ 7650 vars->link_status |= phy_vars[active_external_phy].link_status; 7651 7652 /* if active_external_phy is first PHY and link is up - disable 7653 * disable TX on second external PHY 7654 */ 7655 if (active_external_phy == ELINK_EXT_PHY1) { 7656 if (params->phy[ELINK_EXT_PHY2].phy_specific_func) { 7657 ELINK_DEBUG_P0(cb, 7658 "Disabling TX on EXT_PHY2\n"); 7659 params->phy[ELINK_EXT_PHY2].phy_specific_func( 7660 ¶ms->phy[ELINK_EXT_PHY2], 7661 params, ELINK_DISABLE_TX); 7662 } 7663 } 7664 7665 ext_phy_line_speed = phy_vars[active_external_phy].line_speed; 7666 vars->duplex = phy_vars[active_external_phy].duplex; 7667 if (params->phy[active_external_phy].supported & 7668 ELINK_SUPPORTED_FIBRE) 7669 vars->link_status |= LINK_STATUS_SERDES_LINK; 7670 else 7671 vars->link_status &= ~LINK_STATUS_SERDES_LINK; 7672 7673 vars->eee_status = phy_vars[active_external_phy].eee_status; 7674 7675 ELINK_DEBUG_P1(cb, "Active external phy selected: %x\n", 7676 active_external_phy); 7677 } 7678 7679 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 7680 phy_index++) { 7681 if (params->phy[phy_index].flags & 7682 ELINK_FLAGS_REARM_LATCH_SIGNAL) { 7683 elink_rearm_latch_signal(cb, port, 7684 phy_index == 7685 active_external_phy); 7686 break; 7687 } 7688 } 7689 ELINK_DEBUG_P3(cb, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," 7690 " ext_phy_line_speed = %d\n", vars->flow_ctrl, 7691 vars->link_status, ext_phy_line_speed); 7692 /* Upon link speed change set the NIG into drain mode. Comes to 7693 * deals with possible FIFO glitch due to clk change when speed 7694 * is decreased without link down indicator 7695 */ 7696 7697 if (vars->phy_link_up) { 7698 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && 7699 (ext_phy_line_speed != vars->line_speed)) { 7700 ELINK_DEBUG_P2(cb, "Internal link speed %d is" 7701 " different than the external" 7702 " link speed %d\n", vars->line_speed, 7703 ext_phy_line_speed); 7704 vars->phy_link_up = 0; 7705 } else if (prev_line_speed != vars->line_speed) { 7706 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 7707 0); 7708 MSLEEP(cb, 1); 7709 } 7710 } 7711 7712 /* Anything 10 and over uses the bmac */ 7713 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000); 7714 7715 elink_link_int_ack(params, vars, link_10g_plus); 7716 7717 /* In case external phy link is up, and internal link is down 7718 * (not initialized yet probably after link initialization, it 7719 * needs to be initialized. 7720 * Note that after link down-up as result of cable plug, the xgxs 7721 * link would probably become up again without the need 7722 * initialize it 7723 */ 7724 if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) { 7725 ELINK_DEBUG_P3(cb, "ext_phy_link_up = %d, int_link_up = %d," 7726 " init_preceding = %d\n", ext_phy_link_up, 7727 vars->phy_link_up, 7728 params->phy[ELINK_EXT_PHY1].flags & 7729 ELINK_FLAGS_INIT_XGXS_FIRST); 7730 if (!(params->phy[ELINK_EXT_PHY1].flags & 7731 ELINK_FLAGS_INIT_XGXS_FIRST) 7732 && ext_phy_link_up && !vars->phy_link_up) { 7733 vars->line_speed = ext_phy_line_speed; 7734 if (vars->line_speed < ELINK_SPEED_1000) 7735 vars->phy_flags |= PHY_SGMII_FLAG; 7736 else 7737 vars->phy_flags &= ~PHY_SGMII_FLAG; 7738 7739 if (params->phy[ELINK_INT_PHY].config_init) 7740 params->phy[ELINK_INT_PHY].config_init( 7741 ¶ms->phy[ELINK_INT_PHY], params, 7742 vars); 7743 } 7744 } 7745 /* Link is up only if both local phy and external phy (in case of 7746 * non-direct board) are up and no fault detected on active PHY. 7747 */ 7748 vars->link_up = (vars->phy_link_up && 7749 (ext_phy_link_up || 7750 ELINK_SINGLE_MEDIA_DIRECT(params)) && 7751 (phy_vars[active_external_phy].fault_detected == 0)); 7752 7753 /* Update the PFC configuration in case it was changed */ 7754 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 7755 vars->link_status |= LINK_STATUS_PFC_ENABLED; 7756 else 7757 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 7758 7759 if (vars->link_up) 7760 rc = elink_update_link_up(params, vars, link_10g_plus); 7761 else 7762 rc = elink_update_link_down(params, vars); 7763 7764 if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP) 7765 elink_chng_link_count(params, 0); 7766 7767 #ifndef ELINK_AUX_POWER 7768 /* Update MCP link status was changed */ 7769 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX) 7770 elink_cb_fw_command(cb, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); 7771 #endif // ELINK_AUX_POWER 7772 7773 return rc; 7774 } 7775 7776 #endif // EXCLUDE_NON_COMMON_INIT 7777 #ifndef ELINK_EMUL_ONLY 7778 /*****************************************************************************/ 7779 /* External Phy section */ 7780 /*****************************************************************************/ 7781 void elink_ext_phy_hw_reset(struct elink_dev *cb, u8 port) 7782 { 7783 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1, 7784 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 7785 MSLEEP(cb, 1); 7786 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1, 7787 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); 7788 } 7789 7790 #if !defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_SFX7101) || !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833) || !defined(EXCLUDE_SFX7101) || !defined(EXCLUDE_BCM8705) || !defined(EXCLUDE_BCM87x6) 7791 static void elink_save_spirom_version(struct elink_dev *cb, u8 port, 7792 u32 spirom_ver, u32 ver_addr) 7793 { 7794 ELINK_DEBUG_P3(cb, "FW version 0x%x:0x%x for port %d\n", 7795 (u16)(spirom_ver>>16), (u16)spirom_ver, port); 7796 7797 if (ver_addr) 7798 REG_WR(cb, ver_addr, spirom_ver); 7799 } 7800 7801 #if (!defined EXCLUDE_XGXS) && (!defined EXCLUDE_COMMON_INIT) 7802 static void elink_save_bcm_spirom_ver(struct elink_dev *cb, 7803 struct elink_phy *phy, 7804 u8 port) 7805 { 7806 u16 fw_ver1, fw_ver2; 7807 7808 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 7809 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7810 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 7811 MDIO_PMA_REG_ROM_VER2, &fw_ver2); 7812 elink_save_spirom_version(cb, port, (u32)(fw_ver1<<16 | fw_ver2), 7813 phy->ver_addr); 7814 } 7815 #endif // EXCLUDE_XGXS 7816 7817 #ifndef EXCLUDE_NON_COMMON_INIT 7818 static void elink_ext_phy_10G_an_resolve(struct elink_dev *cb, 7819 struct elink_phy *phy, 7820 struct elink_vars *vars) 7821 { 7822 u16 val; 7823 elink_cl45_read(cb, phy, 7824 MDIO_AN_DEVAD, 7825 MDIO_AN_REG_STATUS, &val); 7826 elink_cl45_read(cb, phy, 7827 MDIO_AN_DEVAD, 7828 MDIO_AN_REG_STATUS, &val); 7829 if (val & (1<<5)) 7830 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 7831 if ((val & (1<<0)) == 0) 7832 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; 7833 } 7834 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 7835 #endif // #if !defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833) || !defined(EXCLUDE_SFX7101) 7836 7837 /******************************************************************/ 7838 /* common BCM8073/BCM8727 PHY SECTION */ 7839 /******************************************************************/ 7840 #ifndef EXCLUDE_BCM8727_BCM8073 7841 #ifndef EXCLUDE_NON_COMMON_INIT 7842 static void elink_8073_resolve_fc(struct elink_phy *phy, 7843 struct elink_params *params, 7844 struct elink_vars *vars) 7845 { 7846 struct elink_dev *cb = params->cb; 7847 if (phy->req_line_speed == ELINK_SPEED_10 || 7848 phy->req_line_speed == ELINK_SPEED_100) { 7849 vars->flow_ctrl = phy->req_flow_ctrl; 7850 return; 7851 } 7852 7853 if (elink_ext_phy_resolve_fc(phy, params, vars) && 7854 (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) { 7855 u16 pause_result; 7856 u16 ld_pause; /* local */ 7857 u16 lp_pause; /* link partner */ 7858 elink_cl45_read(cb, phy, 7859 MDIO_AN_DEVAD, 7860 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 7861 7862 elink_cl45_read(cb, phy, 7863 MDIO_AN_DEVAD, 7864 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 7865 pause_result = (ld_pause & 7866 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; 7867 pause_result |= (lp_pause & 7868 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; 7869 7870 elink_pause_resolve(vars, pause_result); 7871 ELINK_DEBUG_P1(cb, "Ext PHY CL37 pause result 0x%x\n", 7872 pause_result); 7873 } 7874 } 7875 #endif // EXCLUDE_NON_COMMON_INIT 7876 #ifndef EXCLUDE_COMMON_INIT 7877 static elink_status_t elink_8073_8727_external_rom_boot(struct elink_dev *cb, 7878 struct elink_phy *phy, 7879 u8 port) 7880 { 7881 u32 count = 0; 7882 u16 fw_ver1, fw_msgout; 7883 elink_status_t rc = ELINK_STATUS_OK; 7884 7885 /* Boot port from external ROM */ 7886 /* EDC grst */ 7887 elink_cl45_write(cb, phy, 7888 MDIO_PMA_DEVAD, 7889 MDIO_PMA_REG_GEN_CTRL, 7890 0x0001); 7891 7892 /* Ucode reboot and rst */ 7893 elink_cl45_write(cb, phy, 7894 MDIO_PMA_DEVAD, 7895 MDIO_PMA_REG_GEN_CTRL, 7896 0x008c); 7897 7898 elink_cl45_write(cb, phy, 7899 MDIO_PMA_DEVAD, 7900 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 7901 7902 /* Reset internal microprocessor */ 7903 elink_cl45_write(cb, phy, 7904 MDIO_PMA_DEVAD, 7905 MDIO_PMA_REG_GEN_CTRL, 7906 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 7907 7908 /* Release srst bit */ 7909 elink_cl45_write(cb, phy, 7910 MDIO_PMA_DEVAD, 7911 MDIO_PMA_REG_GEN_CTRL, 7912 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 7913 7914 /* Delay 100ms per the PHY specifications */ 7915 MSLEEP(cb, 100); 7916 7917 /* 8073 sometimes taking longer to download */ 7918 do { 7919 count++; 7920 if (count > 300) { 7921 ELINK_DEBUG_P2(cb, 7922 "elink_8073_8727_external_rom_boot port %x:" 7923 "Download failed. fw version = 0x%x\n", 7924 port, fw_ver1); 7925 rc = ELINK_STATUS_ERROR; 7926 break; 7927 } 7928 7929 elink_cl45_read(cb, phy, 7930 MDIO_PMA_DEVAD, 7931 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7932 elink_cl45_read(cb, phy, 7933 MDIO_PMA_DEVAD, 7934 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); 7935 7936 MSLEEP(cb, 1); 7937 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || 7938 ((fw_msgout & 0xff) != 0x03 && (phy->type == 7939 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); 7940 7941 /* Clear ser_boot_ctl bit */ 7942 elink_cl45_write(cb, phy, 7943 MDIO_PMA_DEVAD, 7944 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 7945 elink_save_bcm_spirom_ver(cb, phy, port); 7946 7947 ELINK_DEBUG_P2(cb, 7948 "elink_8073_8727_external_rom_boot port %x:" 7949 "Download complete. fw version = 0x%x\n", 7950 port, fw_ver1); 7951 7952 return rc; 7953 } 7954 #endif // EXCLUDE_COMMON_INIT 7955 7956 /******************************************************************/ 7957 /* BCM8073 PHY SECTION */ 7958 /******************************************************************/ 7959 #ifndef EXCLUDE_NON_COMMON_INIT 7960 static elink_status_t elink_8073_is_snr_needed(struct elink_dev *cb, struct elink_phy *phy) 7961 { 7962 /* This is only required for 8073A1, version 102 only */ 7963 u16 val; 7964 7965 /* Read 8073 HW revision*/ 7966 elink_cl45_read(cb, phy, 7967 MDIO_PMA_DEVAD, 7968 MDIO_PMA_REG_8073_CHIP_REV, &val); 7969 7970 if (val != 1) { 7971 /* No need to workaround in 8073 A1 */ 7972 return ELINK_STATUS_OK; 7973 } 7974 7975 elink_cl45_read(cb, phy, 7976 MDIO_PMA_DEVAD, 7977 MDIO_PMA_REG_ROM_VER2, &val); 7978 7979 /* SNR should be applied only for version 0x102 */ 7980 if (val != 0x102) 7981 return ELINK_STATUS_OK; 7982 7983 return 1; 7984 } 7985 7986 static elink_status_t elink_8073_xaui_wa(struct elink_dev *cb, struct elink_phy *phy) 7987 { 7988 u16 val, cnt, cnt1 ; 7989 7990 elink_cl45_read(cb, phy, 7991 MDIO_PMA_DEVAD, 7992 MDIO_PMA_REG_8073_CHIP_REV, &val); 7993 7994 if (val > 0) { 7995 /* No need to workaround in 8073 A1 */ 7996 return ELINK_STATUS_OK; 7997 } 7998 /* XAUI workaround in 8073 A0: */ 7999 8000 /* After loading the boot ROM and restarting Autoneg, poll 8001 * Dev1, Reg $C820: 8002 */ 8003 8004 for (cnt = 0; cnt < 1000; cnt++) { 8005 elink_cl45_read(cb, phy, 8006 MDIO_PMA_DEVAD, 8007 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 8008 &val); 8009 /* If bit [14] = 0 or bit [13] = 0, continue on with 8010 * system initialization (XAUI work-around not required, as 8011 * these bits indicate 2.5G or 1G link up). 8012 */ 8013 if (!(val & (1<<14)) || !(val & (1<<13))) { 8014 ELINK_DEBUG_P0(cb, "XAUI work-around not required\n"); 8015 return ELINK_STATUS_OK; 8016 } else if (!(val & (1<<15))) { 8017 ELINK_DEBUG_P0(cb, "bit 15 went off\n"); 8018 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's 8019 * MSB (bit15) goes to 1 (indicating that the XAUI 8020 * workaround has completed), then continue on with 8021 * system initialization. 8022 */ 8023 for (cnt1 = 0; cnt1 < 1000; cnt1++) { 8024 elink_cl45_read(cb, phy, 8025 MDIO_PMA_DEVAD, 8026 MDIO_PMA_REG_8073_XAUI_WA, &val); 8027 if (val & (1<<15)) { 8028 ELINK_DEBUG_P0(cb, 8029 "XAUI workaround has completed\n"); 8030 return ELINK_STATUS_OK; 8031 } 8032 MSLEEP(cb, 3); 8033 } 8034 break; 8035 } 8036 MSLEEP(cb, 3); 8037 } 8038 ELINK_DEBUG_P0(cb, "Warning: XAUI work-around timeout !!!\n"); 8039 return ELINK_STATUS_ERROR; 8040 } 8041 8042 #ifdef ELINK_INCLUDE_LOOPBACK 8043 static void elink_807x_force_10G(struct elink_dev *cb, struct elink_phy *phy) 8044 { 8045 /* Force KR or KX */ 8046 elink_cl45_write(cb, phy, 8047 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 8048 elink_cl45_write(cb, phy, 8049 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); 8050 elink_cl45_write(cb, phy, 8051 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); 8052 elink_cl45_write(cb, phy, 8053 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 8054 } 8055 #endif // ELINK_INCLUDE_LOOPBACK 8056 8057 static void elink_8073_set_pause_cl37(struct elink_params *params, 8058 struct elink_phy *phy, 8059 struct elink_vars *vars) 8060 { 8061 u16 cl37_val; 8062 struct elink_dev *cb = params->cb; 8063 elink_cl45_read(cb, phy, 8064 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); 8065 8066 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 8067 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 8068 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 8069 if ((vars->ieee_fc & 8070 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == 8071 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { 8072 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; 8073 } 8074 if ((vars->ieee_fc & 8075 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 8076 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 8077 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 8078 } 8079 if ((vars->ieee_fc & 8080 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 8081 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 8082 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 8083 } 8084 ELINK_DEBUG_P1(cb, 8085 "Ext phy AN advertize cl37 0x%x\n", cl37_val); 8086 8087 elink_cl45_write(cb, phy, 8088 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); 8089 #ifndef ELINK_AUX_POWER 8090 MSLEEP(cb, 500); 8091 #endif // ELINK_AUX_POWER 8092 } 8093 8094 static void elink_8073_specific_func(struct elink_phy *phy, 8095 struct elink_params *params, 8096 u32 action) 8097 { 8098 struct elink_dev *cb = params->cb; 8099 switch (action) { 8100 case ELINK_PHY_INIT: 8101 /* Enable LASI */ 8102 elink_cl45_write(cb, phy, 8103 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); 8104 elink_cl45_write(cb, phy, 8105 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); 8106 break; 8107 } 8108 } 8109 8110 static elink_status_t elink_8073_config_init(struct elink_phy *phy, 8111 struct elink_params *params, 8112 struct elink_vars *vars) 8113 { 8114 struct elink_dev *cb = params->cb; 8115 u16 val = 0, tmp1; 8116 u8 gpio_port; 8117 ELINK_DEBUG_P0(cb, "Init 8073\n"); 8118 8119 if (CHIP_IS_E2(params->chip_id)) 8120 gpio_port = PATH_ID(cb); 8121 else 8122 gpio_port = params->port; 8123 /* Restore normal power mode*/ 8124 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 8125 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 8126 8127 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1, 8128 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 8129 8130 elink_8073_specific_func(phy, params, ELINK_PHY_INIT); 8131 elink_8073_set_pause_cl37(params, phy, vars); 8132 8133 elink_cl45_read(cb, phy, 8134 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 8135 8136 elink_cl45_read(cb, phy, 8137 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 8138 8139 ELINK_DEBUG_P1(cb, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); 8140 8141 /* Swap polarity if required - Must be done only in non-1G mode */ 8142 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 8143 /* Configure the 8073 to swap _P and _N of the KR lines */ 8144 ELINK_DEBUG_P0(cb, "Swapping polarity for the 8073\n"); 8145 /* 10G Rx/Tx and 1G Tx signal polarity swap */ 8146 elink_cl45_read(cb, phy, 8147 MDIO_PMA_DEVAD, 8148 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); 8149 elink_cl45_write(cb, phy, 8150 MDIO_PMA_DEVAD, 8151 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, 8152 (val | (3<<9))); 8153 } 8154 8155 8156 /* Enable CL37 BAM */ 8157 if (REG_RD(cb, params->shmem_base + 8158 OFFSETOF(struct shmem_region, dev_info. 8159 port_hw_config[params->port].default_cfg)) & 8160 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 8161 8162 elink_cl45_read(cb, phy, 8163 MDIO_AN_DEVAD, 8164 MDIO_AN_REG_8073_BAM, &val); 8165 elink_cl45_write(cb, phy, 8166 MDIO_AN_DEVAD, 8167 MDIO_AN_REG_8073_BAM, val | 1); 8168 ELINK_DEBUG_P0(cb, "Enable CL37 BAM on KR\n"); 8169 } 8170 #ifdef ELINK_INCLUDE_LOOPBACK 8171 if (params->loopback_mode == ELINK_LOOPBACK_EXT) { 8172 elink_807x_force_10G(cb, phy); 8173 ELINK_DEBUG_P0(cb, "Forced speed 10G on 807X\n"); 8174 return ELINK_STATUS_OK; 8175 } else { 8176 elink_cl45_write(cb, phy, 8177 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); 8178 } 8179 #endif // ELINK_INCLUDE_LOOPBACK 8180 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) { 8181 if (phy->req_line_speed == ELINK_SPEED_10000) { 8182 val = (1<<7); 8183 } else if (phy->req_line_speed == ELINK_SPEED_2500) { 8184 val = (1<<5); 8185 /* Note that 2.5G works only when used with 1G 8186 * advertisement 8187 */ 8188 } else 8189 val = (1<<5); 8190 } else { 8191 val = 0; 8192 if (phy->speed_cap_mask & 8193 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 8194 val |= (1<<7); 8195 8196 /* Note that 2.5G works only when used with 1G advertisement */ 8197 if (phy->speed_cap_mask & 8198 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | 8199 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 8200 val |= (1<<5); 8201 ELINK_DEBUG_P1(cb, "807x autoneg val = 0x%x\n", val); 8202 } 8203 8204 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); 8205 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); 8206 8207 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && 8208 (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) || 8209 (phy->req_line_speed == ELINK_SPEED_2500)) { 8210 u16 phy_ver; 8211 /* Allow 2.5G for A1 and above */ 8212 elink_cl45_read(cb, phy, 8213 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, 8214 &phy_ver); 8215 ELINK_DEBUG_P0(cb, "Add 2.5G\n"); 8216 if (phy_ver > 0) 8217 tmp1 |= 1; 8218 else 8219 tmp1 &= 0xfffe; 8220 } else { 8221 ELINK_DEBUG_P0(cb, "Disable 2.5G\n"); 8222 tmp1 &= 0xfffe; 8223 } 8224 8225 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); 8226 /* Add support for CL37 (passive mode) II */ 8227 8228 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); 8229 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 8230 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? 8231 0x20 : 0x40))); 8232 8233 /* Add support for CL37 (passive mode) III */ 8234 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 8235 8236 /* The SNR will improve about 2db by changing BW and FEE main 8237 * tap. Rest commands are executed after link is up 8238 * Change FFE main cursor to 5 in EDC register 8239 */ 8240 if (elink_8073_is_snr_needed(cb, phy)) 8241 elink_cl45_write(cb, phy, 8242 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, 8243 0xFB0C); 8244 8245 /* Enable FEC (Forware Error Correction) Request in the AN */ 8246 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); 8247 tmp1 |= (1<<15); 8248 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); 8249 8250 elink_ext_phy_set_pause(params, phy, vars); 8251 8252 /* Restart autoneg */ 8253 MSLEEP(cb, 500); 8254 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 8255 ELINK_DEBUG_P2(cb, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", 8256 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); 8257 return ELINK_STATUS_OK; 8258 } 8259 8260 static u8 elink_8073_read_status(struct elink_phy *phy, 8261 struct elink_params *params, 8262 struct elink_vars *vars) 8263 { 8264 struct elink_dev *cb = params->cb; 8265 u8 link_up = 0; 8266 u16 val1, val2; 8267 u16 link_status = 0; 8268 u16 an1000_status = 0; 8269 8270 elink_cl45_read(cb, phy, 8271 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 8272 8273 ELINK_DEBUG_P1(cb, "8703 LASI status 0x%x\n", val1); 8274 8275 /* Clear the interrupt LASI status register */ 8276 elink_cl45_read(cb, phy, 8277 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 8278 elink_cl45_read(cb, phy, 8279 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); 8280 ELINK_DEBUG_P2(cb, "807x PCS status 0x%x->0x%x\n", val2, val1); 8281 /* Clear MSG-OUT */ 8282 elink_cl45_read(cb, phy, 8283 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 8284 8285 /* Check the LASI */ 8286 elink_cl45_read(cb, phy, 8287 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 8288 8289 ELINK_DEBUG_P1(cb, "KR 0x9003 0x%x\n", val2); 8290 8291 /* Check the link status */ 8292 elink_cl45_read(cb, phy, 8293 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 8294 ELINK_DEBUG_P1(cb, "KR PCS status 0x%x\n", val2); 8295 8296 elink_cl45_read(cb, phy, 8297 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 8298 elink_cl45_read(cb, phy, 8299 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 8300 link_up = ((val1 & 4) == 4); 8301 ELINK_DEBUG_P1(cb, "PMA_REG_STATUS=0x%x\n", val1); 8302 8303 if (link_up && 8304 ((phy->req_line_speed != ELINK_SPEED_10000))) { 8305 if (elink_8073_xaui_wa(cb, phy) != 0) 8306 return 0; 8307 } 8308 elink_cl45_read(cb, phy, 8309 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 8310 elink_cl45_read(cb, phy, 8311 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 8312 8313 /* Check the link status on 1.1.2 */ 8314 elink_cl45_read(cb, phy, 8315 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 8316 elink_cl45_read(cb, phy, 8317 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 8318 ELINK_DEBUG_P3(cb, "KR PMA status 0x%x->0x%x," 8319 "an_link_status=0x%x\n", val2, val1, an1000_status); 8320 8321 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); 8322 if (link_up && elink_8073_is_snr_needed(cb, phy)) { 8323 /* The SNR will improve about 2dbby changing the BW and FEE main 8324 * tap. The 1st write to change FFE main tap is set before 8325 * restart AN. Change PLL Bandwidth in EDC register 8326 */ 8327 elink_cl45_write(cb, phy, 8328 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, 8329 0x26BC); 8330 8331 /* Change CDR Bandwidth in EDC register */ 8332 elink_cl45_write(cb, phy, 8333 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, 8334 0x0333); 8335 } 8336 elink_cl45_read(cb, phy, 8337 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 8338 &link_status); 8339 8340 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ 8341 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 8342 link_up = 1; 8343 vars->line_speed = ELINK_SPEED_10000; 8344 ELINK_DEBUG_P1(cb, "port %x: External link up in 10G\n", 8345 params->port); 8346 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { 8347 link_up = 1; 8348 vars->line_speed = ELINK_SPEED_2500; 8349 ELINK_DEBUG_P1(cb, "port %x: External link up in 2.5G\n", 8350 params->port); 8351 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 8352 link_up = 1; 8353 vars->line_speed = ELINK_SPEED_1000; 8354 ELINK_DEBUG_P1(cb, "port %x: External link up in 1G\n", 8355 params->port); 8356 } else { 8357 link_up = 0; 8358 ELINK_DEBUG_P1(cb, "port %x: External link is down\n", 8359 params->port); 8360 } 8361 8362 if (link_up) { 8363 /* Swap polarity if required */ 8364 if (params->lane_config & 8365 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 8366 /* Configure the 8073 to swap P and N of the KR lines */ 8367 elink_cl45_read(cb, phy, 8368 MDIO_XS_DEVAD, 8369 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); 8370 /* Set bit 3 to invert Rx in 1G mode and clear this bit 8371 * when it`s in 10G mode. 8372 */ 8373 if (vars->line_speed == ELINK_SPEED_1000) { 8374 ELINK_DEBUG_P0(cb, "Swapping 1G polarity for" 8375 "the 8073\n"); 8376 val1 |= (1<<3); 8377 } else 8378 val1 &= ~(1<<3); 8379 8380 elink_cl45_write(cb, phy, 8381 MDIO_XS_DEVAD, 8382 MDIO_XS_REG_8073_RX_CTRL_PCIE, 8383 val1); 8384 } 8385 elink_ext_phy_10G_an_resolve(cb, phy, vars); 8386 elink_8073_resolve_fc(phy, params, vars); 8387 vars->duplex = DUPLEX_FULL; 8388 } 8389 8390 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 8391 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 8392 MDIO_AN_REG_LP_AUTO_NEG2, &val1); 8393 8394 if (val1 & (1<<5)) 8395 vars->link_status |= 8396 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 8397 if (val1 & (1<<7)) 8398 vars->link_status |= 8399 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 8400 } 8401 8402 return link_up; 8403 } 8404 8405 static void elink_8073_link_reset(struct elink_phy *phy, 8406 struct elink_params *params) 8407 { 8408 #ifndef EXCLUDE_LINK_RESET 8409 struct elink_dev *cb = params->cb; 8410 u8 gpio_port; 8411 if (CHIP_IS_E2(params->chip_id)) 8412 gpio_port = PATH_ID(cb); 8413 else 8414 gpio_port = params->port; 8415 ELINK_DEBUG_P1(cb, "Setting 8073 port %d into low power mode\n", 8416 gpio_port); 8417 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 8418 MISC_REGISTERS_GPIO_OUTPUT_LOW, 8419 gpio_port); 8420 #endif // EXCLUDE_LINK_RESET 8421 } 8422 #endif // EXCLUDE_NON_COMMON_INIT 8423 #endif // EXCLUDE_BCM8727_BCM8073 8424 8425 /******************************************************************/ 8426 /* BCM8705 PHY SECTION */ 8427 /******************************************************************/ 8428 #ifndef EXCLUDE_BCM8705 8429 static elink_status_t elink_8705_config_init(struct elink_phy *phy, 8430 struct elink_params *params, 8431 struct elink_vars *vars) 8432 { 8433 struct elink_dev *cb = params->cb; 8434 ELINK_DEBUG_P0(cb, "init 8705\n"); 8435 /* Restore normal power mode*/ 8436 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 8437 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 8438 /* HW reset */ 8439 elink_ext_phy_hw_reset(cb, params->port); 8440 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 8441 elink_wait_reset_complete(cb, phy, params); 8442 8443 elink_cl45_write(cb, phy, 8444 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); 8445 elink_cl45_write(cb, phy, 8446 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); 8447 elink_cl45_write(cb, phy, 8448 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); 8449 elink_cl45_write(cb, phy, 8450 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); 8451 /* BCM8705 doesn't have microcode, hence the 0 */ 8452 elink_save_spirom_version(cb, params->port, params->shmem_base, 0); 8453 return ELINK_STATUS_OK; 8454 } 8455 8456 static u8 elink_8705_read_status(struct elink_phy *phy, 8457 struct elink_params *params, 8458 struct elink_vars *vars) 8459 { 8460 u8 link_up = 0; 8461 u16 val1, rx_sd; 8462 struct elink_dev *cb = params->cb; 8463 ELINK_DEBUG_P0(cb, "read status 8705\n"); 8464 elink_cl45_read(cb, phy, 8465 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 8466 ELINK_DEBUG_P1(cb, "8705 LASI status 0x%x\n", val1); 8467 8468 elink_cl45_read(cb, phy, 8469 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 8470 ELINK_DEBUG_P1(cb, "8705 LASI status 0x%x\n", val1); 8471 8472 elink_cl45_read(cb, phy, 8473 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 8474 8475 elink_cl45_read(cb, phy, 8476 MDIO_PMA_DEVAD, 0xc809, &val1); 8477 elink_cl45_read(cb, phy, 8478 MDIO_PMA_DEVAD, 0xc809, &val1); 8479 8480 ELINK_DEBUG_P1(cb, "8705 1.c809 val=0x%x\n", val1); 8481 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); 8482 if (link_up) { 8483 vars->line_speed = ELINK_SPEED_10000; 8484 elink_ext_phy_resolve_fc(phy, params, vars); 8485 } 8486 return link_up; 8487 } 8488 8489 #endif /* EXCLUDE_BCM8705 */ 8490 /******************************************************************/ 8491 /* SFP+ module Section */ 8492 /******************************************************************/ 8493 #ifndef EXCLUDE_NON_COMMON_INIT 8494 #ifndef EXCLUDE_BCM8727_BCM8073 8495 static void elink_set_disable_pmd_transmit(struct elink_params *params, 8496 struct elink_phy *phy, 8497 u8 pmd_dis) 8498 { 8499 struct elink_dev *cb = params->cb; 8500 /* Disable transmitter only for bootcodes which can enable it afterwards 8501 * (for D3 link) 8502 */ 8503 if (pmd_dis) { 8504 if (params->feature_config_flags & 8505 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) { 8506 ELINK_DEBUG_P0(cb, "Disabling PMD transmitter\n"); 8507 } else { 8508 ELINK_DEBUG_P0(cb, "NOT disabling PMD transmitter\n"); 8509 return; 8510 } 8511 } else 8512 ELINK_DEBUG_P0(cb, "Enabling PMD transmitter\n"); 8513 elink_cl45_write(cb, phy, 8514 MDIO_PMA_DEVAD, 8515 MDIO_PMA_REG_TX_DISABLE, pmd_dis); 8516 } 8517 #endif // EXCLUDE_BCM8727_BCM8073 8518 8519 #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) 8520 static u8 elink_get_gpio_port(struct elink_params *params) 8521 { 8522 u8 gpio_port; 8523 u32 swap_val, swap_override; 8524 struct elink_dev *cb = params->cb; 8525 if (CHIP_IS_E2(params->chip_id)) 8526 gpio_port = PATH_ID(cb); 8527 else 8528 gpio_port = params->port; 8529 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP); 8530 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE); 8531 return gpio_port ^ (swap_val && swap_override); 8532 } 8533 8534 static void elink_sfp_e1e2_set_transmitter(struct elink_params *params, 8535 struct elink_phy *phy, 8536 u8 tx_en) 8537 { 8538 u16 val; 8539 u8 port = params->port; 8540 struct elink_dev *cb = params->cb; 8541 u32 tx_en_mode; 8542 8543 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ 8544 tx_en_mode = REG_RD(cb, params->shmem_base + 8545 OFFSETOF(struct shmem_region, 8546 dev_info.port_hw_config[port].sfp_ctrl)) & 8547 PORT_HW_CFG_TX_LASER_MASK; 8548 ELINK_DEBUG_P3(cb, "Setting transmitter tx_en=%x for port %x " 8549 "mode = %x\n", tx_en, port, tx_en_mode); 8550 switch (tx_en_mode) { 8551 case PORT_HW_CFG_TX_LASER_MDIO: 8552 8553 elink_cl45_read(cb, phy, 8554 MDIO_PMA_DEVAD, 8555 MDIO_PMA_REG_PHY_IDENTIFIER, 8556 &val); 8557 8558 if (tx_en) 8559 val &= ~(1<<15); 8560 else 8561 val |= (1<<15); 8562 8563 elink_cl45_write(cb, phy, 8564 MDIO_PMA_DEVAD, 8565 MDIO_PMA_REG_PHY_IDENTIFIER, 8566 val); 8567 break; 8568 case PORT_HW_CFG_TX_LASER_GPIO0: 8569 case PORT_HW_CFG_TX_LASER_GPIO1: 8570 case PORT_HW_CFG_TX_LASER_GPIO2: 8571 case PORT_HW_CFG_TX_LASER_GPIO3: 8572 { 8573 u16 gpio_pin; 8574 u8 gpio_port, gpio_mode; 8575 if (tx_en) 8576 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; 8577 else 8578 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; 8579 8580 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; 8581 gpio_port = elink_get_gpio_port(params); 8582 ELINK_SET_GPIO(cb, gpio_pin, gpio_mode, gpio_port); 8583 break; 8584 } 8585 default: 8586 ELINK_DEBUG_P1(cb, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); 8587 break; 8588 } 8589 } 8590 #endif /* !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) */ 8591 8592 static void elink_sfp_set_transmitter(struct elink_params *params, 8593 struct elink_phy *phy, 8594 u8 tx_en) 8595 { 8596 #ifdef ELINK_ENHANCEMENTS 8597 struct elink_dev *cb = params->cb; 8598 ELINK_DEBUG_P1(cb, "Setting SFP+ transmitter to %d\n", tx_en); 8599 #endif // ELINK_ENHANCEMENTS 8600 #ifndef EXCLUDE_WARPCORE 8601 if (CHIP_IS_E3(params->chip_id)) 8602 elink_sfp_e3_set_transmitter(params, phy, tx_en); 8603 #endif // EXCLUDE_WARPCORE 8604 #ifdef ELINK_ENHANCEMENTS 8605 else 8606 #endif // ELINK_ENHANCEMENTS 8607 #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) 8608 elink_sfp_e1e2_set_transmitter(params, phy, tx_en); 8609 #endif 8610 } 8611 8612 static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy, 8613 struct elink_params *params, 8614 u8 dev_addr, u16 addr, u8 byte_cnt, 8615 u8 *o_buf, u8 is_init) 8616 { 8617 #ifndef EXCLUDE_BCM87x6 8618 struct elink_dev *cb = params->cb; 8619 u16 val = 0; 8620 u16 i; 8621 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { 8622 ELINK_DEBUG_P0(cb, 8623 "Reading from eeprom is limited to 0xf\n"); 8624 return ELINK_STATUS_ERROR; 8625 } 8626 /* Set the read command byte count */ 8627 elink_cl45_write(cb, phy, 8628 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 8629 (byte_cnt | (dev_addr << 8))); 8630 8631 /* Set the read command address */ 8632 elink_cl45_write(cb, phy, 8633 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 8634 addr); 8635 8636 /* Activate read command */ 8637 elink_cl45_write(cb, phy, 8638 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 8639 0x2c0f); 8640 8641 /* Wait up to 500us for command complete status */ 8642 for (i = 0; i < 100; i++) { 8643 elink_cl45_read(cb, phy, 8644 MDIO_PMA_DEVAD, 8645 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8646 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8647 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 8648 break; 8649 USLEEP(cb, 5); 8650 } 8651 8652 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 8653 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 8654 ELINK_DEBUG_P1(cb, 8655 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 8656 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 8657 return ELINK_STATUS_ERROR; 8658 } 8659 8660 /* Read the buffer */ 8661 for (i = 0; i < byte_cnt; i++) { 8662 elink_cl45_read(cb, phy, 8663 MDIO_PMA_DEVAD, 8664 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); 8665 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); 8666 } 8667 8668 for (i = 0; i < 100; i++) { 8669 elink_cl45_read(cb, phy, 8670 MDIO_PMA_DEVAD, 8671 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8672 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8673 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 8674 return ELINK_STATUS_OK; 8675 MSLEEP(cb, 1); 8676 } 8677 #endif // EXCLUDE_BCM87x6 8678 return ELINK_STATUS_ERROR; 8679 } 8680 8681 #ifndef EXCLUDE_WARPCORE 8682 #ifndef EXCLUDE_NON_COMMON_INIT 8683 static void elink_warpcore_power_module(struct elink_params *params, 8684 u8 power) 8685 { 8686 u32 pin_cfg; 8687 struct elink_dev *cb = params->cb; 8688 8689 pin_cfg = (REG_RD(cb, params->shmem_base + 8690 OFFSETOF(struct shmem_region, 8691 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & 8692 PORT_HW_CFG_E3_PWR_DIS_MASK) >> 8693 PORT_HW_CFG_E3_PWR_DIS_SHIFT; 8694 8695 if (pin_cfg == PIN_CFG_NA) 8696 return; 8697 ELINK_DEBUG_P2(cb, "Setting SFP+ module power to %d using pin cfg %d\n", 8698 power, pin_cfg); 8699 /* Low ==> corresponding SFP+ module is powered 8700 * high ==> the SFP+ module is powered down 8701 */ 8702 elink_set_cfg_pin(cb, pin_cfg, power ^ 1); 8703 } 8704 #endif 8705 static elink_status_t elink_warpcore_read_sfp_module_eeprom(struct elink_phy *phy, 8706 struct elink_params *params, 8707 u8 dev_addr, 8708 u16 addr, u8 byte_cnt, 8709 u8 *o_buf, u8 is_init) 8710 { 8711 elink_status_t rc = ELINK_STATUS_OK; 8712 u8 i, j = 0, cnt = 0; 8713 u32 data_array[4]; 8714 u16 addr32; 8715 struct elink_dev *cb = params->cb; 8716 8717 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { 8718 ELINK_DEBUG_P0(cb, 8719 "Reading from eeprom is limited to 16 bytes\n"); 8720 return ELINK_STATUS_ERROR; 8721 } 8722 8723 /* 4 byte aligned address */ 8724 addr32 = addr & (~0x3); 8725 do { 8726 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) { 8727 elink_warpcore_power_module(params, 0); 8728 /* Note that 100us are not enough here */ 8729 MSLEEP(cb, 1); 8730 elink_warpcore_power_module(params, 1); 8731 } 8732 rc = elink_bsc_read(params, cb, dev_addr, addr32, 0, byte_cnt, 8733 data_array); 8734 } while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT)); 8735 8736 if (rc == ELINK_STATUS_OK) { 8737 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { 8738 o_buf[j] = *((u8 *)data_array + i); 8739 j++; 8740 } 8741 } 8742 8743 return rc; 8744 } 8745 #endif /* EXCLUDE_WARPCORE */ 8746 8747 #ifndef EXCLUDE_BCM8727_BCM8073 8748 static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy, 8749 struct elink_params *params, 8750 u8 dev_addr, u16 addr, u8 byte_cnt, 8751 u8 *o_buf, u8 is_init) 8752 { 8753 struct elink_dev *cb = params->cb; 8754 u16 val, i; 8755 8756 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { 8757 ELINK_DEBUG_P0(cb, 8758 "Reading from eeprom is limited to 0xf\n"); 8759 return ELINK_STATUS_ERROR; 8760 } 8761 8762 /* Set 2-wire transfer rate of SFP+ module EEPROM 8763 * to 100Khz since some DACs(direct attached cables) do 8764 * not work at 400Khz. 8765 */ 8766 elink_cl45_write(cb, phy, 8767 MDIO_PMA_DEVAD, 8768 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, 8769 ((dev_addr << 8) | 1)); 8770 8771 /* Need to read from 1.8000 to clear it */ 8772 elink_cl45_read(cb, phy, 8773 MDIO_PMA_DEVAD, 8774 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 8775 &val); 8776 8777 /* Set the read command byte count */ 8778 elink_cl45_write(cb, phy, 8779 MDIO_PMA_DEVAD, 8780 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 8781 ((byte_cnt < 2) ? 2 : byte_cnt)); 8782 8783 /* Set the read command address */ 8784 elink_cl45_write(cb, phy, 8785 MDIO_PMA_DEVAD, 8786 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 8787 addr); 8788 /* Set the destination address */ 8789 elink_cl45_write(cb, phy, 8790 MDIO_PMA_DEVAD, 8791 0x8004, 8792 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); 8793 8794 /* Activate read command */ 8795 elink_cl45_write(cb, phy, 8796 MDIO_PMA_DEVAD, 8797 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 8798 0x8002); 8799 /* Wait appropriate time for two-wire command to finish before 8800 * polling the status register 8801 */ 8802 MSLEEP(cb, 1); 8803 8804 /* Wait up to 500us for command complete status */ 8805 for (i = 0; i < 100; i++) { 8806 elink_cl45_read(cb, phy, 8807 MDIO_PMA_DEVAD, 8808 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8809 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8810 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 8811 break; 8812 USLEEP(cb, 5); 8813 } 8814 8815 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 8816 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 8817 ELINK_DEBUG_P1(cb, 8818 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 8819 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 8820 return ELINK_STATUS_TIMEOUT; 8821 } 8822 8823 /* Read the buffer */ 8824 for (i = 0; i < byte_cnt; i++) { 8825 elink_cl45_read(cb, phy, 8826 MDIO_PMA_DEVAD, 8827 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); 8828 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); 8829 } 8830 8831 for (i = 0; i < 100; i++) { 8832 elink_cl45_read(cb, phy, 8833 MDIO_PMA_DEVAD, 8834 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8835 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8836 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 8837 return ELINK_STATUS_OK; 8838 MSLEEP(cb, 1); 8839 } 8840 8841 return ELINK_STATUS_ERROR; 8842 } 8843 #endif /* EXCLUDE_BCM8727_BCM8073 */ 8844 #endif /* #ifndef EXCLUDE_NON_COMMON_INIT */ 8845 #endif /* ELINK_EMUL_ONLY */ 8846 #ifndef EXCLUDE_FROM_BNX2X 8847 elink_status_t elink_validate_cc_dmi(u8 *sfp_a2_buf) 8848 { 8849 u8 i, checksum = 0; 8850 for (i = 0; i < ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE; i++) 8851 checksum += sfp_a2_buf[i]; 8852 if (checksum == sfp_a2_buf[ELINK_SFP_EEPROM_A2_CC_DMI_ADDR]) 8853 return ELINK_STATUS_OK; 8854 8855 return ELINK_STATUS_ERROR; 8856 } 8857 #endif 8858 #ifndef EXCLUDE_NON_COMMON_INIT 8859 elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy, 8860 struct elink_params *params, u8 dev_addr, 8861 u16 addr, u16 byte_cnt, u8 *o_buf) 8862 { 8863 elink_status_t rc = 0; 8864 #ifdef ELINK_DEBUG 8865 struct elink_dev *cb = params->cb; 8866 #endif 8867 u8 xfer_size; 8868 u8 *user_data = o_buf; 8869 read_sfp_module_eeprom_func_p read_func; 8870 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) { 8871 ELINK_DEBUG_P1(cb, "invalid dev_addr 0x%x\n", dev_addr); 8872 return ELINK_STATUS_ERROR; 8873 } 8874 8875 #ifndef ELINK_EMUL_ONLY 8876 switch (phy->type) { 8877 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 8878 read_func = elink_8726_read_sfp_module_eeprom; 8879 break; 8880 #ifndef EXCLUDE_BCM8727_BCM8073 8881 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8882 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8883 read_func = elink_8727_read_sfp_module_eeprom; 8884 break; 8885 #endif 8886 #ifndef EXCLUDE_WARPCORE 8887 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8888 read_func = elink_warpcore_read_sfp_module_eeprom; 8889 break; 8890 #endif /* EXCLUDE_WARPCORE */ 8891 default: 8892 return ELINK_OP_NOT_SUPPORTED; 8893 } 8894 8895 while (!rc && (byte_cnt > 0)) { 8896 xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ? 8897 ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt; 8898 rc = read_func(phy, params, dev_addr, addr, xfer_size, 8899 user_data, 0); 8900 byte_cnt -= xfer_size; 8901 user_data += xfer_size; 8902 addr += xfer_size; 8903 } 8904 #endif /* ELINK_EMUL_ONLY */ 8905 return rc; 8906 } 8907 #endif // EXCLUDE_NON_COMMON_INIT 8908 #ifndef ELINK_EMUL_ONLY 8909 8910 #ifndef EXCLUDE_NON_COMMON_INIT 8911 #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_WARPCORE) 8912 static elink_status_t elink_get_edc_mode(struct elink_phy *phy, 8913 struct elink_params *params, 8914 u16 *edc_mode) 8915 { 8916 struct elink_dev *cb = params->cb; 8917 u32 sync_offset = 0, phy_idx, media_types; 8918 u8 val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0; 8919 *edc_mode = ELINK_EDC_MODE_LIMITING; 8920 phy->media_type = ELINK_ETH_PHY_UNSPECIFIED; 8921 /* First check for copper cable */ 8922 if (elink_read_sfp_module_eeprom(phy, 8923 params, 8924 ELINK_I2C_DEV_ADDR_A0, 8925 0, 8926 ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1, 8927 (u8 *)val) != 0) { 8928 ELINK_DEBUG_P0(cb, "Failed to read from SFP+ module EEPROM\n"); 8929 return ELINK_STATUS_ERROR; 8930 } 8931 #ifndef EXCLUDE_WARPCORE 8932 params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK; 8933 params->link_attr_sync |= val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] << 8934 LINK_SFP_EEPROM_COMP_CODE_SHIFT; 8935 elink_update_link_attr(params, params->link_attr_sync); 8936 #endif 8937 switch (val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]) { 8938 case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER: 8939 { 8940 u8 copper_module_type; 8941 phy->media_type = ELINK_ETH_PHY_DA_TWINAX; 8942 /* Check if its active cable (includes SFP+ module) 8943 * of passive cable 8944 */ 8945 copper_module_type = val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR]; 8946 if (copper_module_type & 8947 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { 8948 ELINK_DEBUG_P0(cb, "Active Copper cable detected\n"); 8949 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 8950 *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC; 8951 else 8952 check_limiting_mode = 1; 8953 } else { 8954 *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC; 8955 /* Even in case PASSIVE_DAC indication is not set, 8956 * treat it as a passive DAC cable, since some cables 8957 * don't have this indication. 8958 */ 8959 if (copper_module_type & 8960 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { 8961 ELINK_DEBUG_P0(cb, 8962 "Passive Copper cable detected\n"); 8963 } else { 8964 ELINK_DEBUG_P0(cb, 8965 "Unknown copper-cable-type\n"); 8966 } 8967 } 8968 break; 8969 } 8970 case ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN: 8971 case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC: 8972 case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45: 8973 check_limiting_mode = 1; 8974 /* Module is considered as 1G in case it's NOT compliant with 8975 * any 10G ethernet protocol. 8976 */ 8977 if ((val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] & 8978 (ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK | 8979 ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK | 8980 ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) { 8981 ELINK_DEBUG_P0(cb, "1G SFP module detected\n"); 8982 phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER; 8983 if (phy->req_line_speed != ELINK_SPEED_1000) { 8984 #ifndef ELINK_AUX_POWER 8985 u8 gport = params->port; 8986 #endif 8987 phy->req_line_speed = ELINK_SPEED_1000; 8988 #ifndef ELINK_AUX_POWER 8989 if (!CHIP_IS_E1X(params->chip_id)) { 8990 gport = PATH_ID(cb) + 8991 (params->port << 1); 8992 } 8993 elink_cb_event_log(cb, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps." 8994 // " Current SFP module in port %d is not" 8995 // " compliant with 10G Ethernet\n", 8996 #endif 8997 } 8998 8999 if (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] & 9000 ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T) { 9001 /* Some 1G-baseT modules will not link up, 9002 * unless TX_EN is toggled with long delay in 9003 * between. 9004 */ 9005 elink_sfp_set_transmitter(params, phy, 0); 9006 MSLEEP(cb, 40); 9007 elink_sfp_set_transmitter(params, phy, 1); 9008 } 9009 } else { 9010 int idx, cfg_idx = 0; 9011 ELINK_DEBUG_P0(cb, "10G Optic module detected\n"); 9012 for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) { 9013 if (params->phy[idx].type == phy->type) { 9014 cfg_idx = ELINK_LINK_CONFIG_IDX(idx); 9015 break; 9016 } 9017 } 9018 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER; 9019 phy->req_line_speed = params->req_line_speed[cfg_idx]; 9020 } 9021 break; 9022 default: 9023 ELINK_DEBUG_P1(cb, "Unable to determine module type 0x%x !!!\n", 9024 val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]); 9025 return ELINK_STATUS_ERROR; 9026 } 9027 sync_offset = params->shmem_base + 9028 OFFSETOF(struct shmem_region, 9029 dev_info.port_hw_config[params->port].media_type); 9030 media_types = REG_RD(cb, sync_offset); 9031 /* Update media type for non-PMF sync */ 9032 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 9033 if (&(params->phy[phy_idx]) == phy) { 9034 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 9035 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 9036 media_types |= ((phy->media_type & 9037 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 9038 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 9039 break; 9040 } 9041 } 9042 REG_WR(cb, sync_offset, media_types); 9043 if (check_limiting_mode) { 9044 u8 options[ELINK_SFP_EEPROM_OPTIONS_SIZE]; 9045 if (elink_read_sfp_module_eeprom(phy, 9046 params, 9047 ELINK_I2C_DEV_ADDR_A0, 9048 ELINK_SFP_EEPROM_OPTIONS_ADDR, 9049 ELINK_SFP_EEPROM_OPTIONS_SIZE, 9050 options) != 0) { 9051 ELINK_DEBUG_P0(cb, 9052 "Failed to read Option field from module EEPROM\n"); 9053 return ELINK_STATUS_ERROR; 9054 } 9055 if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) 9056 *edc_mode = ELINK_EDC_MODE_LINEAR; 9057 else 9058 *edc_mode = ELINK_EDC_MODE_LIMITING; 9059 } 9060 ELINK_DEBUG_P1(cb, "EDC mode is set to 0x%x\n", *edc_mode); 9061 return ELINK_STATUS_OK; 9062 } 9063 #ifdef ELINK_ENHANCEMENTS 9064 /* This function read the relevant field from the module (SFP+), and verify it 9065 * is compliant with this board 9066 */ 9067 static elink_status_t elink_verify_sfp_module(struct elink_phy *phy, 9068 struct elink_params *params) 9069 { 9070 struct elink_dev *cb = params->cb; 9071 u32 val, cmd; 9072 u32 fw_resp, fw_cmd_param; 9073 char vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE+1]; 9074 char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE+1]; 9075 phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED; 9076 val = REG_RD(cb, params->shmem_base + 9077 OFFSETOF(struct shmem_region, dev_info. 9078 port_feature_config[params->port].config)); 9079 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9080 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { 9081 ELINK_DEBUG_P0(cb, "NOT enforcing module verification\n"); 9082 return ELINK_STATUS_OK; 9083 } 9084 9085 if (params->feature_config_flags & 9086 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { 9087 /* Use specific phy request */ 9088 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; 9089 } else if (params->feature_config_flags & 9090 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { 9091 /* Use first phy request only in case of non-dual media*/ 9092 if (ELINK_DUAL_MEDIA(params)) { 9093 ELINK_DEBUG_P0(cb, 9094 "FW does not support OPT MDL verification\n"); 9095 return ELINK_STATUS_ERROR; 9096 } 9097 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; 9098 } else { 9099 /* No support in OPT MDL detection */ 9100 ELINK_DEBUG_P0(cb, 9101 "FW does not support OPT MDL verification\n"); 9102 return ELINK_STATUS_ERROR; 9103 } 9104 9105 fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); 9106 fw_resp = elink_cb_fw_command(cb, cmd, fw_cmd_param); 9107 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { 9108 ELINK_DEBUG_P0(cb, "Approved module\n"); 9109 return ELINK_STATUS_OK; 9110 } 9111 9112 /* Format the warning message */ 9113 if (elink_read_sfp_module_eeprom(phy, 9114 params, 9115 ELINK_I2C_DEV_ADDR_A0, 9116 ELINK_SFP_EEPROM_VENDOR_NAME_ADDR, 9117 ELINK_SFP_EEPROM_VENDOR_NAME_SIZE, 9118 (u8 *)vendor_name)) 9119 vendor_name[0] = '\0'; 9120 else 9121 vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; 9122 if (elink_read_sfp_module_eeprom(phy, 9123 params, 9124 ELINK_I2C_DEV_ADDR_A0, 9125 ELINK_SFP_EEPROM_PART_NO_ADDR, 9126 ELINK_SFP_EEPROM_PART_NO_SIZE, 9127 (u8 *)vendor_pn)) 9128 vendor_pn[0] = '\0'; 9129 else 9130 vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0'; 9131 9132 elink_cb_event_log(cb, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected," 9133 // " Port %d from %s part number %s\n", 9134 9135 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != 9136 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) 9137 phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED; 9138 return ELINK_STATUS_ERROR; 9139 } 9140 #endif /* ELINK_ENHANCEMENTS */ 9141 9142 #ifndef EXCLUDE_BCM8727_BCM8073 9143 static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy *phy, 9144 struct elink_params *params) 9145 9146 { 9147 u8 val; 9148 elink_status_t rc; 9149 struct elink_dev *cb = params->cb; 9150 u16 timeout; 9151 /* Initialization time after hot-plug may take up to 300ms for 9152 * some phys type ( e.g. JDSU ) 9153 */ 9154 9155 for (timeout = 0; timeout < 60; timeout++) { 9156 #ifndef EXCLUDE_WARPCORE 9157 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 9158 rc = elink_warpcore_read_sfp_module_eeprom( 9159 phy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val, 9160 1); 9161 else 9162 #endif 9163 rc = elink_read_sfp_module_eeprom(phy, params, 9164 ELINK_I2C_DEV_ADDR_A0, 9165 1, 1, &val); 9166 if (rc == 0) { 9167 ELINK_DEBUG_P1(cb, 9168 "SFP+ module initialization took %d ms\n", 9169 timeout * 5); 9170 return ELINK_STATUS_OK; 9171 } 9172 MSLEEP(cb, 5); 9173 } 9174 rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0, 9175 1, 1, &val); 9176 return rc; 9177 } 9178 #endif /* EXCLUDE_BCM8727_BCM8073 */ 9179 #endif /* #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_WARPCORE) */ 9180 9181 #ifndef EXCLUDE_BCM8727_BCM8073 9182 static void elink_8727_power_module(struct elink_dev *cb, 9183 struct elink_phy *phy, 9184 u8 is_power_up) { 9185 /* Make sure GPIOs are not using for LED mode */ 9186 u16 val; 9187 /* In the GPIO register, bit 4 is use to determine if the GPIOs are 9188 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for 9189 * output 9190 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 9191 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 9192 * where the 1st bit is the over-current(only input), and 2nd bit is 9193 * for power( only output ) 9194 * 9195 * In case of NOC feature is disabled and power is up, set GPIO control 9196 * as input to enable listening of over-current indication 9197 */ 9198 if (phy->flags & ELINK_FLAGS_NOC) 9199 return; 9200 if (is_power_up) 9201 val = (1<<4); 9202 else 9203 /* Set GPIO control to OUTPUT, and set the power bit 9204 * to according to the is_power_up 9205 */ 9206 val = (1<<1); 9207 9208 elink_cl45_write(cb, phy, 9209 MDIO_PMA_DEVAD, 9210 MDIO_PMA_REG_8727_GPIO_CTRL, 9211 val); 9212 } 9213 #endif /* EXCLUDE_BCM8727_BCM8073 */ 9214 9215 #ifndef EXCLUDE_BCM87x6 9216 static elink_status_t elink_8726_set_limiting_mode(struct elink_dev *cb, 9217 struct elink_phy *phy, 9218 u16 edc_mode) 9219 { 9220 u16 cur_limiting_mode; 9221 9222 elink_cl45_read(cb, phy, 9223 MDIO_PMA_DEVAD, 9224 MDIO_PMA_REG_ROM_VER2, 9225 &cur_limiting_mode); 9226 ELINK_DEBUG_P1(cb, "Current Limiting mode is 0x%x\n", 9227 cur_limiting_mode); 9228 9229 if (edc_mode == ELINK_EDC_MODE_LIMITING) { 9230 ELINK_DEBUG_P0(cb, "Setting LIMITING MODE\n"); 9231 elink_cl45_write(cb, phy, 9232 MDIO_PMA_DEVAD, 9233 MDIO_PMA_REG_ROM_VER2, 9234 ELINK_EDC_MODE_LIMITING); 9235 } else { /* LRM mode ( default )*/ 9236 9237 ELINK_DEBUG_P0(cb, "Setting LRM MODE\n"); 9238 9239 /* Changing to LRM mode takes quite few seconds. So do it only 9240 * if current mode is limiting (default is LRM) 9241 */ 9242 if (cur_limiting_mode != ELINK_EDC_MODE_LIMITING) 9243 return ELINK_STATUS_OK; 9244 9245 elink_cl45_write(cb, phy, 9246 MDIO_PMA_DEVAD, 9247 MDIO_PMA_REG_LRM_MODE, 9248 0); 9249 elink_cl45_write(cb, phy, 9250 MDIO_PMA_DEVAD, 9251 MDIO_PMA_REG_ROM_VER2, 9252 0x128); 9253 elink_cl45_write(cb, phy, 9254 MDIO_PMA_DEVAD, 9255 MDIO_PMA_REG_MISC_CTRL0, 9256 0x4008); 9257 elink_cl45_write(cb, phy, 9258 MDIO_PMA_DEVAD, 9259 MDIO_PMA_REG_LRM_MODE, 9260 0xaaaa); 9261 } 9262 return ELINK_STATUS_OK; 9263 } 9264 #endif /* #ifndef EXCLUDE_BCM87x6 */ 9265 9266 #ifndef EXCLUDE_BCM8727_BCM8073 9267 static elink_status_t elink_8727_set_limiting_mode(struct elink_dev *cb, 9268 struct elink_phy *phy, 9269 u16 edc_mode) 9270 { 9271 u16 phy_identifier; 9272 u16 rom_ver2_val; 9273 elink_cl45_read(cb, phy, 9274 MDIO_PMA_DEVAD, 9275 MDIO_PMA_REG_PHY_IDENTIFIER, 9276 &phy_identifier); 9277 9278 elink_cl45_write(cb, phy, 9279 MDIO_PMA_DEVAD, 9280 MDIO_PMA_REG_PHY_IDENTIFIER, 9281 (phy_identifier & ~(1<<9))); 9282 9283 elink_cl45_read(cb, phy, 9284 MDIO_PMA_DEVAD, 9285 MDIO_PMA_REG_ROM_VER2, 9286 &rom_ver2_val); 9287 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ 9288 elink_cl45_write(cb, phy, 9289 MDIO_PMA_DEVAD, 9290 MDIO_PMA_REG_ROM_VER2, 9291 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); 9292 9293 elink_cl45_write(cb, phy, 9294 MDIO_PMA_DEVAD, 9295 MDIO_PMA_REG_PHY_IDENTIFIER, 9296 (phy_identifier | (1<<9))); 9297 9298 return ELINK_STATUS_OK; 9299 } 9300 9301 static void elink_8727_specific_func(struct elink_phy *phy, 9302 struct elink_params *params, 9303 u32 action) 9304 { 9305 struct elink_dev *cb = params->cb; 9306 u16 val; 9307 switch (action) { 9308 case ELINK_DISABLE_TX: 9309 elink_sfp_set_transmitter(params, phy, 0); 9310 break; 9311 case ELINK_ENABLE_TX: 9312 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) 9313 elink_sfp_set_transmitter(params, phy, 1); 9314 break; 9315 case ELINK_PHY_INIT: 9316 elink_cl45_write(cb, phy, 9317 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9318 (1<<2) | (1<<5)); 9319 elink_cl45_write(cb, phy, 9320 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 9321 0); 9322 elink_cl45_write(cb, phy, 9323 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); 9324 /* Make MOD_ABS give interrupt on change */ 9325 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 9326 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9327 &val); 9328 val |= (1<<12); 9329 if (phy->flags & ELINK_FLAGS_NOC) 9330 val |= (3<<5); 9331 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 9332 * status which reflect SFP+ module over-current 9333 */ 9334 if (!(phy->flags & ELINK_FLAGS_NOC)) 9335 val &= 0xff8f; /* Reset bits 4-6 */ 9336 elink_cl45_write(cb, phy, 9337 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9338 val); 9339 break; 9340 default: 9341 ELINK_DEBUG_P1(cb, "Function 0x%x not supported by 8727\n", 9342 action); 9343 return; 9344 } 9345 } 9346 9347 #ifdef ELINK_ENHANCEMENTS 9348 static void elink_set_e1e2_module_fault_led(struct elink_params *params, 9349 u8 gpio_mode) 9350 { 9351 struct elink_dev *cb = params->cb; 9352 9353 u32 fault_led_gpio = REG_RD(cb, params->shmem_base + 9354 OFFSETOF(struct shmem_region, 9355 dev_info.port_hw_config[params->port].sfp_ctrl)) & 9356 PORT_HW_CFG_FAULT_MODULE_LED_MASK; 9357 switch (fault_led_gpio) { 9358 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: 9359 return; 9360 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: 9361 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: 9362 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: 9363 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: 9364 { 9365 u8 gpio_port = elink_get_gpio_port(params); 9366 u16 gpio_pin = fault_led_gpio - 9367 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; 9368 ELINK_DEBUG_P3(cb, "Set fault module-detected led " 9369 "pin %x port %x mode %x\n", 9370 gpio_pin, gpio_port, gpio_mode); 9371 ELINK_SET_GPIO(cb, gpio_pin, gpio_mode, gpio_port); 9372 } 9373 break; 9374 default: 9375 ELINK_DEBUG_P1(cb, "Error: Invalid fault led mode 0x%x\n", 9376 fault_led_gpio); 9377 } 9378 } 9379 #endif /* #ifdef ELINK_ENHANCEMENTS */ 9380 #endif // EXCLUDE_BCM8727_BCM8073 9381 #endif // EXCLUDE_NON_COMMON_INIT 9382 9383 #ifdef ELINK_ENHANCEMENTS 9384 static void elink_set_e3_module_fault_led(struct elink_params *params, 9385 u8 gpio_mode) 9386 { 9387 u32 pin_cfg; 9388 u8 port = params->port; 9389 struct elink_dev *cb = params->cb; 9390 pin_cfg = (REG_RD(cb, params->shmem_base + 9391 OFFSETOF(struct shmem_region, 9392 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 9393 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> 9394 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; 9395 ELINK_DEBUG_P2(cb, "Setting Fault LED to %d using pin cfg %d\n", 9396 gpio_mode, pin_cfg); 9397 elink_set_cfg_pin(cb, pin_cfg, gpio_mode); 9398 } 9399 9400 static void elink_set_sfp_module_fault_led(struct elink_params *params, 9401 u8 gpio_mode) 9402 { 9403 struct elink_dev *cb = params->cb; 9404 ELINK_DEBUG_P1(cb, "Setting SFP+ module fault LED to %d\n", gpio_mode); 9405 if (CHIP_IS_E3(params->chip_id)) { 9406 /* Low ==> if SFP+ module is supported otherwise 9407 * High ==> if SFP+ module is not on the approved vendor list 9408 */ 9409 elink_set_e3_module_fault_led(params, gpio_mode); 9410 } else 9411 elink_set_e1e2_module_fault_led(params, gpio_mode); 9412 } 9413 #endif /* #ifdef ELINK_ENHANCEMENTS */ 9414 9415 #ifndef EXCLUDE_WARPCORE 9416 #ifndef EXCLUDE_NON_COMMON_INIT 9417 static void elink_warpcore_hw_reset(struct elink_phy *phy, 9418 struct elink_params *params) 9419 { 9420 struct elink_dev *cb = params->cb; 9421 elink_warpcore_power_module(params, 0); 9422 /* Put Warpcore in low power mode */ 9423 REG_WR(cb, MISC_REG_WC0_RESET, 0x0c0e); 9424 9425 /* Put LCPLL in low power mode */ 9426 REG_WR(cb, MISC_REG_LCPLL_E40_PWRDWN, 1); 9427 REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_ANA, 0); 9428 REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_DIG, 0); 9429 } 9430 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 9431 #endif // #ifndef EXCLUDE_WARPCORE 9432 9433 #ifndef EXCLUDE_NON_COMMON_INIT 9434 static void elink_power_sfp_module(struct elink_params *params, 9435 struct elink_phy *phy, 9436 u8 power) 9437 { 9438 #ifdef ELINK_DEBUG 9439 struct elink_dev *cb = params->cb; 9440 #endif /* ELINK_DEBUG */ 9441 ELINK_DEBUG_P1(cb, "Setting SFP+ power to %x\n", power); 9442 9443 switch (phy->type) { 9444 #ifndef EXCLUDE_BCM8727_BCM8073 9445 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 9446 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 9447 elink_8727_power_module(params->cb, phy, power); 9448 break; 9449 #endif // EXCLUDE_BCM8727_BCM8073 9450 #ifndef EXCLUDE_WARPCORE 9451 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 9452 elink_warpcore_power_module(params, power); 9453 break; 9454 #endif // EXCLUDE_WARPCORE 9455 default: 9456 break; 9457 } 9458 } 9459 #ifndef EXCLUDE_WARPCORE 9460 static void elink_warpcore_set_limiting_mode(struct elink_params *params, 9461 struct elink_phy *phy, 9462 u16 edc_mode) 9463 { 9464 u16 val = 0; 9465 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 9466 struct elink_dev *cb = params->cb; 9467 9468 u8 lane = elink_get_warpcore_lane(phy, params); 9469 /* This is a global register which controls all lanes */ 9470 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 9471 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 9472 val &= ~(0xf << (lane << 2)); 9473 9474 switch (edc_mode) { 9475 case ELINK_EDC_MODE_LINEAR: 9476 case ELINK_EDC_MODE_LIMITING: 9477 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 9478 break; 9479 case ELINK_EDC_MODE_PASSIVE_DAC: 9480 case ELINK_EDC_MODE_ACTIVE_DAC: 9481 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; 9482 break; 9483 default: 9484 break; 9485 } 9486 9487 val |= (mode << (lane << 2)); 9488 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 9489 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); 9490 /* A must read */ 9491 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 9492 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 9493 9494 /* Restart microcode to re-read the new mode */ 9495 elink_warpcore_reset_lane(cb, phy, 1); 9496 elink_warpcore_reset_lane(cb, phy, 0); 9497 9498 } 9499 #endif // EXCLUDE_WARPCORE 9500 9501 static void elink_set_limiting_mode(struct elink_params *params, 9502 struct elink_phy *phy, 9503 u16 edc_mode) 9504 { 9505 switch (phy->type) { 9506 #ifndef EXCLUDE_BCM87x6 9507 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 9508 elink_8726_set_limiting_mode(params->cb, phy, edc_mode); 9509 break; 9510 #endif /* #ifndef EXCLUDE_BCM87x6 */ 9511 #ifndef EXCLUDE_BCM8727_BCM8073 9512 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 9513 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 9514 elink_8727_set_limiting_mode(params->cb, phy, edc_mode); 9515 break; 9516 #endif // EXCLUDE_BCM8727_BCM8073 9517 #ifndef EXCLUDE_WARPCORE 9518 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 9519 elink_warpcore_set_limiting_mode(params, phy, edc_mode); 9520 break; 9521 #endif // EXCLUDE_WARPCORE 9522 } 9523 } 9524 9525 elink_status_t elink_sfp_module_detection(struct elink_phy *phy, 9526 struct elink_params *params) 9527 { 9528 struct elink_dev *cb = params->cb; 9529 u16 edc_mode; 9530 elink_status_t rc = ELINK_STATUS_OK; 9531 9532 u32 val = REG_RD(cb, params->shmem_base + 9533 OFFSETOF(struct shmem_region, dev_info. 9534 port_feature_config[params->port].config)); 9535 /* Enabled transmitter by default */ 9536 elink_sfp_set_transmitter(params, phy, 1); 9537 ELINK_DEBUG_P1(cb, "SFP+ module plugged in/out detected on port %d\n", 9538 params->port); 9539 /* Power up module */ 9540 elink_power_sfp_module(params, phy, 1); 9541 if (elink_get_edc_mode(phy, params, &edc_mode) != 0) { 9542 ELINK_DEBUG_P0(cb, "Failed to get valid module type\n"); 9543 return ELINK_STATUS_ERROR; 9544 #ifdef ELINK_ENHANCEMENTS 9545 } else if (elink_verify_sfp_module(phy, params) != 0) { 9546 /* Check SFP+ module compatibility */ 9547 ELINK_DEBUG_P0(cb, "Module verification failed!!\n"); 9548 rc = ELINK_STATUS_ERROR; 9549 /* Turn on fault module-detected led */ 9550 elink_set_sfp_module_fault_led(params, 9551 MISC_REGISTERS_GPIO_HIGH); 9552 9553 /* Check if need to power down the SFP+ module */ 9554 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9555 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { 9556 ELINK_DEBUG_P0(cb, "Shutdown SFP+ module!!\n"); 9557 elink_power_sfp_module(params, phy, 0); 9558 return rc; 9559 } 9560 } else { 9561 /* Turn off fault module-detected led */ 9562 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); 9563 #endif // ELINK_ENHANCEMENTS 9564 } 9565 9566 /* Check and set limiting mode / LRM mode on 8726. On 8727 it 9567 * is done automatically 9568 */ 9569 elink_set_limiting_mode(params, phy, edc_mode); 9570 9571 /* Disable transmit for this module if the module is not approved, and 9572 * laser needs to be disabled. 9573 */ 9574 if ((rc != 0) && 9575 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9576 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)) 9577 elink_sfp_set_transmitter(params, phy, 0); 9578 9579 return rc; 9580 } 9581 #endif // EXCLUDE_NON_COMMON_INIT 9582 9583 #ifdef ELINK_ENHANCEMENTS 9584 void elink_handle_module_detect_int(struct elink_params *params) 9585 { 9586 struct elink_dev *cb = params->cb; 9587 struct elink_phy *phy; 9588 u32 gpio_val; 9589 u8 gpio_num, gpio_port; 9590 if (CHIP_IS_E3(params->chip_id)) { 9591 phy = ¶ms->phy[ELINK_INT_PHY]; 9592 /* Always enable TX laser,will be disabled in case of fault */ 9593 elink_sfp_set_transmitter(params, phy, 1); 9594 } else { 9595 phy = ¶ms->phy[ELINK_EXT_PHY1]; 9596 } 9597 if (elink_get_mod_abs_int_cfg(cb, params->chip_id, params->shmem_base, 9598 params->port, &gpio_num, &gpio_port) == 9599 ELINK_STATUS_ERROR) { 9600 ELINK_DEBUG_P0(cb, "Failed to get MOD_ABS interrupt config\n"); 9601 return; 9602 } 9603 9604 /* Set valid module led off */ 9605 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); 9606 9607 /* Get current gpio val reflecting module plugged in / out*/ 9608 gpio_val = ELINK_GET_GPIO(cb, gpio_num, gpio_port); 9609 9610 /* Call the handling function in case module is detected */ 9611 if (gpio_val == 0) { 9612 #ifdef ELINK_AUX_POWER 9613 phy->flags |= ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC; 9614 #endif 9615 elink_set_mdio_emac_per_phy(cb, params); 9616 elink_set_aer_mmd(params, phy); 9617 9618 elink_power_sfp_module(params, phy, 1); 9619 ELINK_SET_GPIO_INT(cb, gpio_num, 9620 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, 9621 gpio_port); 9622 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) { 9623 elink_sfp_module_detection(phy, params); 9624 if (CHIP_IS_E3(params->chip_id)) { 9625 u16 rx_tx_in_reset; 9626 /* In case WC is out of reset, reconfigure the 9627 * link speed while taking into account 1G 9628 * module limitation. 9629 */ 9630 elink_cl45_read(cb, phy, 9631 MDIO_WC_DEVAD, 9632 MDIO_WC_REG_DIGITAL5_MISC6, 9633 &rx_tx_in_reset); 9634 if ((!rx_tx_in_reset) && 9635 (params->link_flags & 9636 ELINK_PHY_INITIALIZED)) { 9637 elink_warpcore_reset_lane(cb, phy, 1); 9638 elink_warpcore_config_sfi(phy, params); 9639 elink_warpcore_reset_lane(cb, phy, 0); 9640 } 9641 } 9642 } else { 9643 ELINK_DEBUG_P0(cb, "SFP+ module is not initialized\n"); 9644 } 9645 } else { 9646 #ifdef ELINK_AUX_POWER 9647 phy->flags &= ~ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC; 9648 #endif 9649 ELINK_SET_GPIO_INT(cb, gpio_num, 9650 MISC_REGISTERS_GPIO_INT_OUTPUT_SET, 9651 gpio_port); 9652 /* Module was plugged out. 9653 * Disable transmit for this module 9654 */ 9655 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT; 9656 } 9657 } 9658 #endif // ELINK_ENHANCEMENTS 9659 9660 /******************************************************************/ 9661 /* Used by 8706 and 8727 */ 9662 /******************************************************************/ 9663 #ifndef EXCLUDE_NON_COMMON_INIT 9664 #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) 9665 static void elink_sfp_mask_fault(struct elink_dev *cb, 9666 struct elink_phy *phy, 9667 u16 alarm_status_offset, 9668 u16 alarm_ctrl_offset) 9669 { 9670 u16 alarm_status, val; 9671 elink_cl45_read(cb, phy, 9672 MDIO_PMA_DEVAD, alarm_status_offset, 9673 &alarm_status); 9674 elink_cl45_read(cb, phy, 9675 MDIO_PMA_DEVAD, alarm_status_offset, 9676 &alarm_status); 9677 /* Mask or enable the fault event. */ 9678 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); 9679 if (alarm_status & (1<<0)) 9680 val &= ~(1<<0); 9681 else 9682 val |= (1<<0); 9683 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); 9684 } 9685 #endif // #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073 9686 /******************************************************************/ 9687 /* common BCM8706/BCM8726 PHY SECTION */ 9688 /******************************************************************/ 9689 #ifndef EXCLUDE_BCM87x6 9690 static u8 elink_8706_8726_read_status(struct elink_phy *phy, 9691 struct elink_params *params, 9692 struct elink_vars *vars) 9693 { 9694 u8 link_up = 0; 9695 u16 val1, val2, rx_sd, pcs_status; 9696 struct elink_dev *cb = params->cb; 9697 ELINK_DEBUG_P0(cb, "XGXS 8706/8726\n"); 9698 /* Clear RX Alarm*/ 9699 elink_cl45_read(cb, phy, 9700 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 9701 9702 elink_sfp_mask_fault(cb, phy, MDIO_PMA_LASI_TXSTAT, 9703 MDIO_PMA_LASI_TXCTRL); 9704 9705 /* Clear LASI indication*/ 9706 elink_cl45_read(cb, phy, 9707 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 9708 elink_cl45_read(cb, phy, 9709 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 9710 ELINK_DEBUG_P2(cb, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); 9711 9712 elink_cl45_read(cb, phy, 9713 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 9714 elink_cl45_read(cb, phy, 9715 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); 9716 elink_cl45_read(cb, phy, 9717 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 9718 elink_cl45_read(cb, phy, 9719 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 9720 9721 ELINK_DEBUG_P3(cb, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" 9722 " link_status 0x%x\n", rx_sd, pcs_status, val2); 9723 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status 9724 * are set, or if the autoneg bit 1 is set 9725 */ 9726 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); 9727 if (link_up) { 9728 if (val2 & (1<<1)) 9729 vars->line_speed = ELINK_SPEED_1000; 9730 else 9731 vars->line_speed = ELINK_SPEED_10000; 9732 elink_ext_phy_resolve_fc(phy, params, vars); 9733 vars->duplex = DUPLEX_FULL; 9734 } 9735 9736 /* Capture 10G link fault. Read twice to clear stale value. */ 9737 if (vars->line_speed == ELINK_SPEED_10000) { 9738 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 9739 MDIO_PMA_LASI_TXSTAT, &val1); 9740 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 9741 MDIO_PMA_LASI_TXSTAT, &val1); 9742 if (val1 & (1<<0)) 9743 vars->fault_detected = 1; 9744 } 9745 9746 return link_up; 9747 } 9748 9749 /******************************************************************/ 9750 /* BCM8706 PHY SECTION */ 9751 /******************************************************************/ 9752 static u8 elink_8706_config_init(struct elink_phy *phy, 9753 struct elink_params *params, 9754 struct elink_vars *vars) 9755 { 9756 u32 tx_en_mode; 9757 u16 cnt, val, tmp1; 9758 struct elink_dev *cb = params->cb; 9759 9760 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 9761 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 9762 /* HW reset */ 9763 elink_ext_phy_hw_reset(cb, params->port); 9764 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 9765 elink_wait_reset_complete(cb, phy, params); 9766 9767 /* Wait until fw is loaded */ 9768 for (cnt = 0; cnt < 100; cnt++) { 9769 elink_cl45_read(cb, phy, 9770 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); 9771 if (val) 9772 break; 9773 MSLEEP(cb, 10); 9774 } 9775 ELINK_DEBUG_P1(cb, "XGXS 8706 is initialized after %d ms\n", cnt); 9776 if ((params->feature_config_flags & 9777 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 9778 u8 i; 9779 u16 reg; 9780 for (i = 0; i < 4; i++) { 9781 reg = MDIO_XS_8706_REG_BANK_RX0 + 9782 i*(MDIO_XS_8706_REG_BANK_RX1 - 9783 MDIO_XS_8706_REG_BANK_RX0); 9784 elink_cl45_read(cb, phy, MDIO_XS_DEVAD, reg, &val); 9785 /* Clear first 3 bits of the control */ 9786 val &= ~0x7; 9787 /* Set control bits according to configuration */ 9788 val |= (phy->rx_preemphasis[i] & 0x7); 9789 ELINK_DEBUG_P2(cb, "Setting RX Equalizer to BCM8706" 9790 " reg 0x%x <-- val 0x%x\n", reg, val); 9791 elink_cl45_write(cb, phy, MDIO_XS_DEVAD, reg, val); 9792 } 9793 } 9794 /* Force speed */ 9795 if (phy->req_line_speed == ELINK_SPEED_10000) { 9796 ELINK_DEBUG_P0(cb, "XGXS 8706 force 10Gbps\n"); 9797 9798 elink_cl45_write(cb, phy, 9799 MDIO_PMA_DEVAD, 9800 MDIO_PMA_REG_DIGITAL_CTRL, 0x400); 9801 elink_cl45_write(cb, phy, 9802 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 9803 0); 9804 /* Arm LASI for link and Tx fault. */ 9805 elink_cl45_write(cb, phy, 9806 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); 9807 } else { 9808 /* Force 1Gbps using autoneg with 1G advertisement */ 9809 9810 /* Allow CL37 through CL73 */ 9811 ELINK_DEBUG_P0(cb, "XGXS 8706 AutoNeg\n"); 9812 elink_cl45_write(cb, phy, 9813 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 9814 9815 /* Enable Full-Duplex advertisement on CL37 */ 9816 elink_cl45_write(cb, phy, 9817 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); 9818 /* Enable CL37 AN */ 9819 elink_cl45_write(cb, phy, 9820 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 9821 /* 1G support */ 9822 elink_cl45_write(cb, phy, 9823 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); 9824 9825 /* Enable clause 73 AN */ 9826 elink_cl45_write(cb, phy, 9827 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 9828 elink_cl45_write(cb, phy, 9829 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9830 0x0400); 9831 elink_cl45_write(cb, phy, 9832 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 9833 0x0004); 9834 } 9835 elink_save_bcm_spirom_ver(cb, phy, params->port); 9836 9837 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 9838 * power mode, if TX Laser is disabled 9839 */ 9840 9841 tx_en_mode = REG_RD(cb, params->shmem_base + 9842 OFFSETOF(struct shmem_region, 9843 dev_info.port_hw_config[params->port].sfp_ctrl)) 9844 & PORT_HW_CFG_TX_LASER_MASK; 9845 9846 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 9847 ELINK_DEBUG_P0(cb, "Enabling TXONOFF_PWRDN_DIS\n"); 9848 elink_cl45_read(cb, phy, 9849 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); 9850 tmp1 |= 0x1; 9851 elink_cl45_write(cb, phy, 9852 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); 9853 } 9854 9855 return ELINK_STATUS_OK; 9856 } 9857 9858 static elink_status_t elink_8706_read_status(struct elink_phy *phy, 9859 struct elink_params *params, 9860 struct elink_vars *vars) 9861 { 9862 return elink_8706_8726_read_status(phy, params, vars); 9863 } 9864 9865 /******************************************************************/ 9866 /* BCM8726 PHY SECTION */ 9867 /******************************************************************/ 9868 static void elink_8726_config_loopback(struct elink_phy *phy, 9869 struct elink_params *params) 9870 { 9871 struct elink_dev *cb = params->cb; 9872 ELINK_DEBUG_P0(cb, "PMA/PMD ext_phy_loopback: 8726\n"); 9873 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); 9874 } 9875 9876 static void elink_8726_external_rom_boot(struct elink_phy *phy, 9877 struct elink_params *params) 9878 { 9879 struct elink_dev *cb = params->cb; 9880 /* Need to wait 100ms after reset */ 9881 MSLEEP(cb, 100); 9882 9883 /* Micro controller re-boot */ 9884 elink_cl45_write(cb, phy, 9885 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); 9886 9887 /* Set soft reset */ 9888 elink_cl45_write(cb, phy, 9889 MDIO_PMA_DEVAD, 9890 MDIO_PMA_REG_GEN_CTRL, 9891 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 9892 9893 elink_cl45_write(cb, phy, 9894 MDIO_PMA_DEVAD, 9895 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 9896 9897 elink_cl45_write(cb, phy, 9898 MDIO_PMA_DEVAD, 9899 MDIO_PMA_REG_GEN_CTRL, 9900 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 9901 9902 /* Wait for 150ms for microcode load */ 9903 MSLEEP(cb, 150); 9904 9905 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ 9906 elink_cl45_write(cb, phy, 9907 MDIO_PMA_DEVAD, 9908 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 9909 9910 MSLEEP(cb, 200); 9911 elink_save_bcm_spirom_ver(cb, phy, params->port); 9912 } 9913 9914 static u8 elink_8726_read_status(struct elink_phy *phy, 9915 struct elink_params *params, 9916 struct elink_vars *vars) 9917 { 9918 struct elink_dev *cb = params->cb; 9919 u16 val1; 9920 u8 link_up = elink_8706_8726_read_status(phy, params, vars); 9921 if (link_up) { 9922 elink_cl45_read(cb, phy, 9923 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9924 &val1); 9925 if (val1 & (1<<15)) { 9926 ELINK_DEBUG_P0(cb, "Tx is disabled\n"); 9927 link_up = 0; 9928 vars->line_speed = 0; 9929 } 9930 } 9931 return link_up; 9932 } 9933 9934 9935 static elink_status_t elink_8726_config_init(struct elink_phy *phy, 9936 struct elink_params *params, 9937 struct elink_vars *vars) 9938 { 9939 struct elink_dev *cb = params->cb; 9940 ELINK_DEBUG_P0(cb, "Initializing BCM8726\n"); 9941 9942 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 9943 elink_wait_reset_complete(cb, phy, params); 9944 9945 elink_8726_external_rom_boot(phy, params); 9946 9947 /* Need to call module detected on initialization since the module 9948 * detection triggered by actual module insertion might occur before 9949 * driver is loaded, and when driver is loaded, it reset all 9950 * registers, including the transmitter 9951 */ 9952 elink_sfp_module_detection(phy, params); 9953 9954 if (phy->req_line_speed == ELINK_SPEED_1000) { 9955 ELINK_DEBUG_P0(cb, "Setting 1G force\n"); 9956 elink_cl45_write(cb, phy, 9957 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 9958 elink_cl45_write(cb, phy, 9959 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 9960 elink_cl45_write(cb, phy, 9961 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); 9962 elink_cl45_write(cb, phy, 9963 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9964 0x400); 9965 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 9966 (phy->speed_cap_mask & 9967 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && 9968 ((phy->speed_cap_mask & 9969 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 9970 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 9971 ELINK_DEBUG_P0(cb, "Setting 1G clause37\n"); 9972 /* Set Flow control */ 9973 elink_ext_phy_set_pause(params, phy, vars); 9974 elink_cl45_write(cb, phy, 9975 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); 9976 elink_cl45_write(cb, phy, 9977 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 9978 elink_cl45_write(cb, phy, 9979 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); 9980 elink_cl45_write(cb, phy, 9981 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 9982 elink_cl45_write(cb, phy, 9983 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 9984 /* Enable RX-ALARM control to receive interrupt for 1G speed 9985 * change 9986 */ 9987 elink_cl45_write(cb, phy, 9988 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); 9989 elink_cl45_write(cb, phy, 9990 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9991 0x400); 9992 9993 } else { /* Default 10G. Set only LASI control */ 9994 elink_cl45_write(cb, phy, 9995 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); 9996 } 9997 9998 /* Set TX PreEmphasis if needed */ 9999 if ((params->feature_config_flags & 10000 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 10001 ELINK_DEBUG_P2(cb, 10002 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 10003 phy->tx_preemphasis[0], 10004 phy->tx_preemphasis[1]); 10005 elink_cl45_write(cb, phy, 10006 MDIO_PMA_DEVAD, 10007 MDIO_PMA_REG_8726_TX_CTRL1, 10008 phy->tx_preemphasis[0]); 10009 10010 elink_cl45_write(cb, phy, 10011 MDIO_PMA_DEVAD, 10012 MDIO_PMA_REG_8726_TX_CTRL2, 10013 phy->tx_preemphasis[1]); 10014 } 10015 10016 return ELINK_STATUS_OK; 10017 10018 } 10019 10020 static void elink_8726_link_reset(struct elink_phy *phy, 10021 struct elink_params *params) 10022 { 10023 #ifndef EXCLUDE_LINK_RESET 10024 struct elink_dev *cb = params->cb; 10025 ELINK_DEBUG_P1(cb, "elink_8726_link_reset port %d\n", params->port); 10026 /* Set serial boot control for external load */ 10027 elink_cl45_write(cb, phy, 10028 MDIO_PMA_DEVAD, 10029 MDIO_PMA_REG_GEN_CTRL, 0x0001); 10030 #endif // EXCLUDE_LINK_RESET 10031 } 10032 #endif /* #ifndef EXCLUDE_BCM87x6 */ 10033 10034 /******************************************************************/ 10035 /* BCM8727 PHY SECTION */ 10036 /******************************************************************/ 10037 10038 #ifndef EXCLUDE_BCM8727_BCM8073 10039 static void elink_8727_set_link_led(struct elink_phy *phy, 10040 struct elink_params *params, u8 mode) 10041 { 10042 struct elink_dev *cb = params->cb; 10043 u16 led_mode_bitmask = 0; 10044 u16 gpio_pins_bitmask = 0; 10045 u16 val; 10046 /* Only NOC flavor requires to set the LED specifically */ 10047 if (!(phy->flags & ELINK_FLAGS_NOC)) 10048 return; 10049 switch (mode) { 10050 case ELINK_LED_MODE_FRONT_PANEL_OFF: 10051 case ELINK_LED_MODE_OFF: 10052 led_mode_bitmask = 0; 10053 gpio_pins_bitmask = 0x03; 10054 break; 10055 case ELINK_LED_MODE_ON: 10056 led_mode_bitmask = 0; 10057 gpio_pins_bitmask = 0x02; 10058 break; 10059 case ELINK_LED_MODE_OPER: 10060 led_mode_bitmask = 0x60; 10061 gpio_pins_bitmask = 0x11; 10062 break; 10063 } 10064 elink_cl45_read(cb, phy, 10065 MDIO_PMA_DEVAD, 10066 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 10067 &val); 10068 val &= 0xff8f; 10069 val |= led_mode_bitmask; 10070 elink_cl45_write(cb, phy, 10071 MDIO_PMA_DEVAD, 10072 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 10073 val); 10074 elink_cl45_read(cb, phy, 10075 MDIO_PMA_DEVAD, 10076 MDIO_PMA_REG_8727_GPIO_CTRL, 10077 &val); 10078 val &= 0xffe0; 10079 val |= gpio_pins_bitmask; 10080 elink_cl45_write(cb, phy, 10081 MDIO_PMA_DEVAD, 10082 MDIO_PMA_REG_8727_GPIO_CTRL, 10083 val); 10084 } 10085 static void elink_8727_hw_reset(struct elink_phy *phy, 10086 struct elink_params *params) { 10087 u32 swap_val, swap_override; 10088 u8 port; 10089 /* The PHY reset is controlled by GPIO 1. Fake the port number 10090 * to cancel the swap done in set_gpio() 10091 */ 10092 struct elink_dev *cb = params->cb; 10093 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP); 10094 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE); 10095 port = (swap_val && swap_override) ^ 1; 10096 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1, 10097 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 10098 } 10099 10100 static void elink_8727_config_speed(struct elink_phy *phy, 10101 struct elink_params *params) 10102 { 10103 struct elink_dev *cb = params->cb; 10104 u16 tmp1, val; 10105 /* Set option 1G speed */ 10106 if ((phy->req_line_speed == ELINK_SPEED_1000) || 10107 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) { 10108 ELINK_DEBUG_P0(cb, "Setting 1G force\n"); 10109 elink_cl45_write(cb, phy, 10110 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 10111 elink_cl45_write(cb, phy, 10112 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 10113 elink_cl45_read(cb, phy, 10114 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); 10115 ELINK_DEBUG_P1(cb, "1.7 = 0x%x\n", tmp1); 10116 /* Power down the XAUI until link is up in case of dual-media 10117 * and 1G 10118 */ 10119 if (ELINK_DUAL_MEDIA(params)) { 10120 elink_cl45_read(cb, phy, 10121 MDIO_PMA_DEVAD, 10122 MDIO_PMA_REG_8727_PCS_GP, &val); 10123 val |= (3<<10); 10124 elink_cl45_write(cb, phy, 10125 MDIO_PMA_DEVAD, 10126 MDIO_PMA_REG_8727_PCS_GP, val); 10127 } 10128 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 10129 ((phy->speed_cap_mask & 10130 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && 10131 ((phy->speed_cap_mask & 10132 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 10133 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 10134 10135 ELINK_DEBUG_P0(cb, "Setting 1G clause37\n"); 10136 elink_cl45_write(cb, phy, 10137 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); 10138 elink_cl45_write(cb, phy, 10139 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); 10140 } else { 10141 /* Since the 8727 has only single reset pin, need to set the 10G 10142 * registers although it is default 10143 */ 10144 elink_cl45_write(cb, phy, 10145 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 10146 0x0020); 10147 elink_cl45_write(cb, phy, 10148 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); 10149 elink_cl45_write(cb, phy, 10150 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 10151 elink_cl45_write(cb, phy, 10152 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 10153 0x0008); 10154 } 10155 } 10156 10157 static elink_status_t elink_8727_config_init(struct elink_phy *phy, 10158 struct elink_params *params, 10159 struct elink_vars *vars) 10160 { 10161 u32 tx_en_mode; 10162 u16 tmp1, mod_abs, tmp2; 10163 struct elink_dev *cb = params->cb; 10164 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ 10165 10166 elink_wait_reset_complete(cb, phy, params); 10167 10168 ELINK_DEBUG_P0(cb, "Initializing BCM8727\n"); 10169 10170 elink_8727_specific_func(phy, params, ELINK_PHY_INIT); 10171 /* Initially configure MOD_ABS to interrupt when module is 10172 * presence( bit 8) 10173 */ 10174 elink_cl45_read(cb, phy, 10175 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 10176 /* Set EDC off by setting OPTXLOS signal input to low (bit 9). 10177 * When the EDC is off it locks onto a reference clock and avoids 10178 * becoming 'lost' 10179 */ 10180 mod_abs &= ~(1<<8); 10181 if (!(phy->flags & ELINK_FLAGS_NOC)) 10182 mod_abs &= ~(1<<9); 10183 elink_cl45_write(cb, phy, 10184 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 10185 10186 /* Enable/Disable PHY transmitter output */ 10187 elink_set_disable_pmd_transmit(params, phy, 0); 10188 10189 elink_8727_power_module(cb, phy, 1); 10190 10191 elink_cl45_read(cb, phy, 10192 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 10193 10194 elink_cl45_read(cb, phy, 10195 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 10196 10197 elink_8727_config_speed(phy, params); 10198 10199 10200 /* Set TX PreEmphasis if needed */ 10201 if ((params->feature_config_flags & 10202 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 10203 ELINK_DEBUG_P2(cb, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 10204 phy->tx_preemphasis[0], 10205 phy->tx_preemphasis[1]); 10206 elink_cl45_write(cb, phy, 10207 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, 10208 phy->tx_preemphasis[0]); 10209 10210 elink_cl45_write(cb, phy, 10211 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, 10212 phy->tx_preemphasis[1]); 10213 } 10214 10215 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 10216 * power mode, if TX Laser is disabled 10217 */ 10218 tx_en_mode = REG_RD(cb, params->shmem_base + 10219 OFFSETOF(struct shmem_region, 10220 dev_info.port_hw_config[params->port].sfp_ctrl)) 10221 & PORT_HW_CFG_TX_LASER_MASK; 10222 10223 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 10224 10225 ELINK_DEBUG_P0(cb, "Enabling TXONOFF_PWRDN_DIS\n"); 10226 elink_cl45_read(cb, phy, 10227 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); 10228 tmp2 |= 0x1000; 10229 tmp2 &= 0xFFEF; 10230 elink_cl45_write(cb, phy, 10231 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); 10232 elink_cl45_read(cb, phy, 10233 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 10234 &tmp2); 10235 elink_cl45_write(cb, phy, 10236 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 10237 (tmp2 & 0x7fff)); 10238 } 10239 10240 return ELINK_STATUS_OK; 10241 } 10242 10243 static void elink_8727_handle_mod_abs(struct elink_phy *phy, 10244 struct elink_params *params) 10245 { 10246 struct elink_dev *cb = params->cb; 10247 u16 mod_abs, rx_alarm_status; 10248 u32 val = REG_RD(cb, params->shmem_base + 10249 OFFSETOF(struct shmem_region, dev_info. 10250 port_feature_config[params->port]. 10251 config)); 10252 elink_cl45_read(cb, phy, 10253 MDIO_PMA_DEVAD, 10254 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 10255 if (mod_abs & (1<<8)) { 10256 10257 /* Module is absent */ 10258 ELINK_DEBUG_P0(cb, 10259 "MOD_ABS indication show module is absent\n"); 10260 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT; 10261 /* 1. Set mod_abs to detect next module 10262 * presence event 10263 * 2. Set EDC off by setting OPTXLOS signal input to low 10264 * (bit 9). 10265 * When the EDC is off it locks onto a reference clock and 10266 * avoids becoming 'lost'. 10267 */ 10268 mod_abs &= ~(1<<8); 10269 if (!(phy->flags & ELINK_FLAGS_NOC)) 10270 mod_abs &= ~(1<<9); 10271 elink_cl45_write(cb, phy, 10272 MDIO_PMA_DEVAD, 10273 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 10274 10275 /* Clear RX alarm since it stays up as long as 10276 * the mod_abs wasn't changed 10277 */ 10278 elink_cl45_read(cb, phy, 10279 MDIO_PMA_DEVAD, 10280 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 10281 10282 } else { 10283 /* Module is present */ 10284 ELINK_DEBUG_P0(cb, 10285 "MOD_ABS indication show module is present\n"); 10286 /* First disable transmitter, and if the module is ok, the 10287 * module_detection will enable it 10288 * 1. Set mod_abs to detect next module absent event ( bit 8) 10289 * 2. Restore the default polarity of the OPRXLOS signal and 10290 * this signal will then correctly indicate the presence or 10291 * absence of the Rx signal. (bit 9) 10292 */ 10293 mod_abs |= (1<<8); 10294 if (!(phy->flags & ELINK_FLAGS_NOC)) 10295 mod_abs |= (1<<9); 10296 elink_cl45_write(cb, phy, 10297 MDIO_PMA_DEVAD, 10298 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 10299 10300 /* Clear RX alarm since it stays up as long as the mod_abs 10301 * wasn't changed. This is need to be done before calling the 10302 * module detection, otherwise it will clear* the link update 10303 * alarm 10304 */ 10305 elink_cl45_read(cb, phy, 10306 MDIO_PMA_DEVAD, 10307 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 10308 10309 10310 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 10311 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) 10312 elink_sfp_set_transmitter(params, phy, 0); 10313 10314 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) 10315 elink_sfp_module_detection(phy, params); 10316 else 10317 ELINK_DEBUG_P0(cb, "SFP+ module is not initialized\n"); 10318 10319 /* Reconfigure link speed based on module type limitations */ 10320 elink_8727_config_speed(phy, params); 10321 } 10322 10323 ELINK_DEBUG_P1(cb, "8727 RX_ALARM_STATUS 0x%x\n", 10324 rx_alarm_status); 10325 /* No need to check link status in case of module plugged in/out */ 10326 } 10327 10328 static u8 elink_8727_read_status(struct elink_phy *phy, 10329 struct elink_params *params, 10330 struct elink_vars *vars) 10331 10332 { 10333 struct elink_dev *cb = params->cb; 10334 u8 link_up = 0; 10335 u16 link_status = 0; 10336 u16 rx_alarm_status, lasi_ctrl, val1; 10337 10338 /* If PHY is not initialized, do not check link status */ 10339 elink_cl45_read(cb, phy, 10340 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 10341 &lasi_ctrl); 10342 if (!lasi_ctrl) 10343 return 0; 10344 10345 /* Check the LASI on Rx */ 10346 elink_cl45_read(cb, phy, 10347 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, 10348 &rx_alarm_status); 10349 vars->line_speed = 0; 10350 ELINK_DEBUG_P1(cb, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); 10351 10352 elink_sfp_mask_fault(cb, phy, MDIO_PMA_LASI_TXSTAT, 10353 MDIO_PMA_LASI_TXCTRL); 10354 10355 elink_cl45_read(cb, phy, 10356 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 10357 10358 ELINK_DEBUG_P1(cb, "8727 LASI status 0x%x\n", val1); 10359 10360 /* Clear MSG-OUT */ 10361 elink_cl45_read(cb, phy, 10362 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 10363 10364 /* If a module is present and there is need to check 10365 * for over current 10366 */ 10367 if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { 10368 /* Check over-current using 8727 GPIO0 input*/ 10369 elink_cl45_read(cb, phy, 10370 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, 10371 &val1); 10372 10373 if ((val1 & (1<<8)) == 0) { 10374 #ifndef ELINK_AUX_POWER 10375 u8 oc_port = params->port; 10376 if (!CHIP_IS_E1X(params->chip_id)) 10377 oc_port = PATH_ID(cb) + (params->port << 1); 10378 ELINK_DEBUG_P1(cb, 10379 "8727 Power fault has been detected on port %d\n", 10380 oc_port); 10381 elink_cb_event_log(cb, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has " 10382 // "been detected and the power to " 10383 // "that SFP+ module has been removed " 10384 // "to prevent failure of the card. " 10385 // "Please remove the SFP+ module and " 10386 // "restart the system to clear this " 10387 // "error.\n", 10388 #endif 10389 /* Disable all RX_ALARMs except for mod_abs */ 10390 elink_cl45_write(cb, phy, 10391 MDIO_PMA_DEVAD, 10392 MDIO_PMA_LASI_RXCTRL, (1<<5)); 10393 10394 elink_cl45_read(cb, phy, 10395 MDIO_PMA_DEVAD, 10396 MDIO_PMA_REG_PHY_IDENTIFIER, &val1); 10397 /* Wait for module_absent_event */ 10398 val1 |= (1<<8); 10399 elink_cl45_write(cb, phy, 10400 MDIO_PMA_DEVAD, 10401 MDIO_PMA_REG_PHY_IDENTIFIER, val1); 10402 /* Clear RX alarm */ 10403 elink_cl45_read(cb, phy, 10404 MDIO_PMA_DEVAD, 10405 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 10406 elink_8727_power_module(params->cb, phy, 0); 10407 return 0; 10408 } 10409 } /* Over current check */ 10410 10411 /* When module absent bit is set, check module */ 10412 if (rx_alarm_status & (1<<5)) { 10413 elink_8727_handle_mod_abs(phy, params); 10414 /* Enable all mod_abs and link detection bits */ 10415 elink_cl45_write(cb, phy, 10416 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 10417 ((1<<5) | (1<<2))); 10418 } 10419 10420 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) { 10421 ELINK_DEBUG_P0(cb, "Enabling 8727 TX laser\n"); 10422 elink_sfp_set_transmitter(params, phy, 1); 10423 } else { 10424 ELINK_DEBUG_P0(cb, "Tx is disabled\n"); 10425 return 0; 10426 } 10427 10428 elink_cl45_read(cb, phy, 10429 MDIO_PMA_DEVAD, 10430 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); 10431 10432 /* Bits 0..2 --> speed detected, 10433 * Bits 13..15--> link is down 10434 */ 10435 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 10436 link_up = 1; 10437 vars->line_speed = ELINK_SPEED_10000; 10438 ELINK_DEBUG_P1(cb, "port %x: External link up in 10G\n", 10439 params->port); 10440 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 10441 link_up = 1; 10442 vars->line_speed = ELINK_SPEED_1000; 10443 ELINK_DEBUG_P1(cb, "port %x: External link up in 1G\n", 10444 params->port); 10445 } else { 10446 link_up = 0; 10447 ELINK_DEBUG_P1(cb, "port %x: External link is down\n", 10448 params->port); 10449 } 10450 10451 /* Capture 10G link fault. */ 10452 if (vars->line_speed == ELINK_SPEED_10000) { 10453 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 10454 MDIO_PMA_LASI_TXSTAT, &val1); 10455 10456 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 10457 MDIO_PMA_LASI_TXSTAT, &val1); 10458 10459 if (val1 & (1<<0)) { 10460 vars->fault_detected = 1; 10461 } 10462 } 10463 10464 if (link_up) { 10465 elink_ext_phy_resolve_fc(phy, params, vars); 10466 vars->duplex = DUPLEX_FULL; 10467 ELINK_DEBUG_P1(cb, "duplex = 0x%x\n", vars->duplex); 10468 } 10469 10470 if ((ELINK_DUAL_MEDIA(params)) && 10471 (phy->req_line_speed == ELINK_SPEED_1000)) { 10472 elink_cl45_read(cb, phy, 10473 MDIO_PMA_DEVAD, 10474 MDIO_PMA_REG_8727_PCS_GP, &val1); 10475 /* In case of dual-media board and 1G, power up the XAUI side, 10476 * otherwise power it down. For 10G it is done automatically 10477 */ 10478 if (link_up) 10479 val1 &= ~(3<<10); 10480 else 10481 val1 |= (3<<10); 10482 elink_cl45_write(cb, phy, 10483 MDIO_PMA_DEVAD, 10484 MDIO_PMA_REG_8727_PCS_GP, val1); 10485 } 10486 return link_up; 10487 } 10488 10489 static void elink_8727_link_reset(struct elink_phy *phy, 10490 struct elink_params *params) 10491 { 10492 #ifndef EXCLUDE_LINK_RESET 10493 struct elink_dev *cb = params->cb; 10494 10495 /* Enable/Disable PHY transmitter output */ 10496 elink_set_disable_pmd_transmit(params, phy, 1); 10497 10498 /* Disable Transmitter */ 10499 elink_sfp_set_transmitter(params, phy, 0); 10500 /* Clear LASI */ 10501 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); 10502 10503 #endif // EXCLUDE_LINK_RESET 10504 } 10505 #endif /* EXCLUDE_BCM8727_BCM8073 */ 10506 #endif // EXCLUDE_NON_COMMON_INIT 10507 10508 /******************************************************************/ 10509 /* BCM8481/BCM84823/BCM84833 PHY SECTION */ 10510 /******************************************************************/ 10511 #if !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833) 10512 static void elink_save_848xx_spirom_version(struct elink_phy *phy, 10513 struct elink_dev *cb, 10514 u8 port) 10515 { 10516 #ifndef EXCLUDE_BCM8481 10517 u16 val, fw_ver2, cnt, i; 10518 static struct elink_reg_set reg_set[] = { 10519 {MDIO_PMA_DEVAD, 0xA819, 0x0014}, 10520 {MDIO_PMA_DEVAD, 0xA81A, 0xc200}, 10521 {MDIO_PMA_DEVAD, 0xA81B, 0x0000}, 10522 {MDIO_PMA_DEVAD, 0xA81C, 0x0300}, 10523 {MDIO_PMA_DEVAD, 0xA817, 0x0009} 10524 }; 10525 #endif 10526 u16 fw_ver1; 10527 10528 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10529 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10530 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); 10531 elink_save_spirom_version(cb, port, fw_ver1 & 0xfff, 10532 phy->ver_addr); 10533 } else { 10534 #ifndef EXCLUDE_BCM8481 10535 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ 10536 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ 10537 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 10538 elink_cl45_write(cb, phy, reg_set[i].devad, 10539 reg_set[i].reg, reg_set[i].val); 10540 10541 for (cnt = 0; cnt < 100; cnt++) { 10542 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA818, &val); 10543 if (val & 1) 10544 break; 10545 USLEEP(cb, 5); 10546 } 10547 if (cnt == 100) { 10548 ELINK_DEBUG_P0(cb, "Unable to read 848xx " 10549 "phy fw version(1)\n"); 10550 elink_save_spirom_version(cb, port, 0, 10551 phy->ver_addr); 10552 return; 10553 } 10554 10555 10556 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ 10557 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); 10558 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); 10559 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); 10560 for (cnt = 0; cnt < 100; cnt++) { 10561 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA818, &val); 10562 if (val & 1) 10563 break; 10564 USLEEP(cb, 5); 10565 } 10566 if (cnt == 100) { 10567 ELINK_DEBUG_P0(cb, "Unable to read 848xx phy fw " 10568 "version(2)\n"); 10569 elink_save_spirom_version(cb, port, 0, 10570 phy->ver_addr); 10571 return; 10572 } 10573 10574 /* lower 16 bits of the register SPI_FW_STATUS */ 10575 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); 10576 /* upper 16 bits of register SPI_FW_STATUS */ 10577 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); 10578 10579 elink_save_spirom_version(cb, port, (fw_ver2<<16) | fw_ver1, 10580 phy->ver_addr); 10581 #endif /* EXCLUDE_BCM8481 */ 10582 } 10583 10584 } 10585 #ifndef EXCLUDE_NON_COMMON_INIT 10586 static void elink_848xx_set_led(struct elink_dev *cb, 10587 struct elink_phy *phy) 10588 { 10589 u16 val, offset, i; 10590 static struct elink_reg_set reg_set[] = { 10591 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080}, 10592 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018}, 10593 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006}, 10594 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000}, 10595 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, 10596 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ}, 10597 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} 10598 }; 10599 /* PHYC_CTL_LED_CTL */ 10600 elink_cl45_read(cb, phy, 10601 MDIO_PMA_DEVAD, 10602 MDIO_PMA_REG_8481_LINK_SIGNAL, &val); 10603 val &= 0xFE00; 10604 val |= 0x0092; 10605 10606 elink_cl45_write(cb, phy, 10607 MDIO_PMA_DEVAD, 10608 MDIO_PMA_REG_8481_LINK_SIGNAL, val); 10609 10610 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 10611 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg, 10612 reg_set[i].val); 10613 10614 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10615 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) 10616 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; 10617 else 10618 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; 10619 10620 /* stretch_en for LED3*/ 10621 elink_cl45_read_or_write(cb, phy, 10622 MDIO_PMA_DEVAD, offset, 10623 MDIO_PMA_REG_84823_LED3_STRETCH_EN); 10624 } 10625 10626 static void elink_848xx_specific_func(struct elink_phy *phy, 10627 struct elink_params *params, 10628 u32 action) 10629 { 10630 struct elink_dev *cb = params->cb; 10631 switch (action) { 10632 case ELINK_PHY_INIT: 10633 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 10634 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10635 /* Save spirom version */ 10636 elink_save_848xx_spirom_version(phy, cb, params->port); 10637 } 10638 /* This phy uses the NIG latch mechanism since link indication 10639 * arrives through its LED4 and not via its LASI signal, so we 10640 * get steady signal instead of clear on read 10641 */ 10642 elink_bits_en(cb, NIG_REG_LATCH_BC_0 + params->port*4, 10643 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT); 10644 10645 elink_848xx_set_led(cb, phy); 10646 break; 10647 } 10648 } 10649 10650 static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy, 10651 struct elink_params *params, 10652 struct elink_vars *vars) 10653 { 10654 struct elink_dev *cb = params->cb; 10655 u16 autoneg_val, an_1000_val, an_10_100_val; 10656 10657 elink_848xx_specific_func(phy, params, ELINK_PHY_INIT); 10658 elink_cl45_write(cb, phy, 10659 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); 10660 10661 /* set 1000 speed advertisement */ 10662 elink_cl45_read(cb, phy, 10663 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 10664 &an_1000_val); 10665 10666 elink_ext_phy_set_pause(params, phy, vars); 10667 elink_cl45_read(cb, phy, 10668 MDIO_AN_DEVAD, 10669 MDIO_AN_REG_8481_LEGACY_AN_ADV, 10670 &an_10_100_val); 10671 elink_cl45_read(cb, phy, 10672 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, 10673 &autoneg_val); 10674 /* Disable forced speed */ 10675 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 10676 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); 10677 10678 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 10679 (phy->speed_cap_mask & 10680 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 10681 (phy->req_line_speed == ELINK_SPEED_1000)) { 10682 an_1000_val |= (1<<8); 10683 autoneg_val |= (1<<9 | 1<<12); 10684 if (phy->req_duplex == DUPLEX_FULL) 10685 an_1000_val |= (1<<9); 10686 ELINK_DEBUG_P0(cb, "Advertising 1G\n"); 10687 } else 10688 an_1000_val &= ~((1<<8) | (1<<9)); 10689 10690 elink_cl45_write(cb, phy, 10691 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 10692 an_1000_val); 10693 10694 /* Set 10/100 speed advertisement */ 10695 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { 10696 if (phy->speed_cap_mask & 10697 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { 10698 /* Enable autoneg and restart autoneg for legacy speeds 10699 */ 10700 autoneg_val |= (1<<9 | 1<<12); 10701 an_10_100_val |= (1<<8); 10702 ELINK_DEBUG_P0(cb, "Advertising 100M-FD\n"); 10703 } 10704 10705 if (phy->speed_cap_mask & 10706 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { 10707 /* Enable autoneg and restart autoneg for legacy speeds 10708 */ 10709 autoneg_val |= (1<<9 | 1<<12); 10710 an_10_100_val |= (1<<7); 10711 ELINK_DEBUG_P0(cb, "Advertising 100M-HD\n"); 10712 } 10713 10714 if ((phy->speed_cap_mask & 10715 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 10716 (phy->supported & ELINK_SUPPORTED_10baseT_Full)) { 10717 an_10_100_val |= (1<<6); 10718 autoneg_val |= (1<<9 | 1<<12); 10719 ELINK_DEBUG_P0(cb, "Advertising 10M-FD\n"); 10720 } 10721 10722 if ((phy->speed_cap_mask & 10723 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) && 10724 (phy->supported & ELINK_SUPPORTED_10baseT_Half)) { 10725 an_10_100_val |= (1<<5); 10726 autoneg_val |= (1<<9 | 1<<12); 10727 ELINK_DEBUG_P0(cb, "Advertising 10M-HD\n"); 10728 } 10729 } 10730 10731 /* Only 10/100 are allowed to work in FORCE mode */ 10732 if ((phy->req_line_speed == ELINK_SPEED_100) && 10733 (phy->supported & 10734 (ELINK_SUPPORTED_100baseT_Half | 10735 ELINK_SUPPORTED_100baseT_Full))) { 10736 autoneg_val |= (1<<13); 10737 /* Enabled AUTO-MDIX when autoneg is disabled */ 10738 elink_cl45_write(cb, phy, 10739 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 10740 (1<<15 | 1<<9 | 7<<0)); 10741 /* The PHY needs this set even for forced link. */ 10742 an_10_100_val |= (1<<8) | (1<<7); 10743 ELINK_DEBUG_P0(cb, "Setting 100M force\n"); 10744 } 10745 if ((phy->req_line_speed == ELINK_SPEED_10) && 10746 (phy->supported & 10747 (ELINK_SUPPORTED_10baseT_Half | 10748 ELINK_SUPPORTED_10baseT_Full))) { 10749 /* Enabled AUTO-MDIX when autoneg is disabled */ 10750 elink_cl45_write(cb, phy, 10751 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 10752 (1<<15 | 1<<9 | 7<<0)); 10753 ELINK_DEBUG_P0(cb, "Setting 10M force\n"); 10754 } 10755 10756 elink_cl45_write(cb, phy, 10757 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, 10758 an_10_100_val); 10759 10760 if (phy->req_duplex == DUPLEX_FULL) 10761 autoneg_val |= (1<<8); 10762 10763 /* Always write this if this is not 84833/4. 10764 * For 84833/4, write it only when it's a forced speed. 10765 */ 10766 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 10767 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) || 10768 ((autoneg_val & (1<<12)) == 0)) 10769 elink_cl45_write(cb, phy, 10770 MDIO_AN_DEVAD, 10771 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); 10772 10773 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 10774 (phy->speed_cap_mask & 10775 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 10776 (phy->req_line_speed == ELINK_SPEED_10000)) { 10777 ELINK_DEBUG_P0(cb, "Advertising 10G\n"); 10778 /* Restart autoneg for 10G*/ 10779 10780 elink_cl45_read_or_write( 10781 cb, phy, 10782 MDIO_AN_DEVAD, 10783 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 10784 0x1000); 10785 elink_cl45_write(cb, phy, 10786 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 10787 0x3200); 10788 } else 10789 elink_cl45_write(cb, phy, 10790 MDIO_AN_DEVAD, 10791 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 10792 1); 10793 10794 return ELINK_STATUS_OK; 10795 } 10796 #endif // EXCLUDE_NON_COMMON_INIT 10797 #endif // #if !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833) 10798 10799 #ifndef EXCLUDE_BCM8481 10800 #ifndef EXCLUDE_NON_COMMON_INIT 10801 static elink_status_t elink_8481_config_init(struct elink_phy *phy, 10802 struct elink_params *params, 10803 struct elink_vars *vars) 10804 { 10805 struct elink_dev *cb = params->cb; 10806 /* Restore normal power mode*/ 10807 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 10808 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 10809 10810 /* HW reset */ 10811 elink_ext_phy_hw_reset(cb, params->port); 10812 elink_wait_reset_complete(cb, phy, params); 10813 10814 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 10815 return elink_848xx_cmn_config_init(phy, params, vars); 10816 } 10817 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 10818 #endif // EXCLUDE_BCM8481 10819 10820 #ifndef EXCLUDE_BCM84833 10821 #define PHY84833_CMDHDLR_WAIT 300 10822 #define PHY84833_CMDHDLR_MAX_ARGS 5 10823 static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy, 10824 struct elink_params *params, u16 fw_cmd, 10825 u16 cmd_args[], int argc) 10826 { 10827 int idx; 10828 u16 val; 10829 struct elink_dev *cb = params->cb; 10830 /* Write CMD_OPEN_OVERRIDE to STATUS reg */ 10831 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD, 10832 MDIO_84833_CMD_HDLR_STATUS, 10833 PHY84833_STATUS_CMD_OPEN_OVERRIDE); 10834 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 10835 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 10836 MDIO_84833_CMD_HDLR_STATUS, &val); 10837 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) 10838 break; 10839 MSLEEP(cb, 1); 10840 } 10841 if (idx >= PHY84833_CMDHDLR_WAIT) { 10842 ELINK_DEBUG_P0(cb, "FW cmd: FW not ready.\n"); 10843 return ELINK_STATUS_ERROR; 10844 } 10845 10846 /* Prepare argument(s) and issue command */ 10847 for (idx = 0; idx < argc; idx++) { 10848 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD, 10849 MDIO_84833_CMD_HDLR_DATA1 + idx, 10850 cmd_args[idx]); 10851 } 10852 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD, 10853 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); 10854 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 10855 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 10856 MDIO_84833_CMD_HDLR_STATUS, &val); 10857 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || 10858 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) 10859 break; 10860 MSLEEP(cb, 1); 10861 } 10862 if ((idx >= PHY84833_CMDHDLR_WAIT) || 10863 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { 10864 ELINK_DEBUG_P0(cb, "FW cmd failed.\n"); 10865 return ELINK_STATUS_ERROR; 10866 } 10867 /* Gather returning data */ 10868 for (idx = 0; idx < argc; idx++) { 10869 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 10870 MDIO_84833_CMD_HDLR_DATA1 + idx, 10871 &cmd_args[idx]); 10872 } 10873 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD, 10874 MDIO_84833_CMD_HDLR_STATUS, 10875 PHY84833_STATUS_CMD_CLEAR_COMPLETE); 10876 return ELINK_STATUS_OK; 10877 } 10878 10879 #ifndef EXCLUDE_NON_COMMON_INIT 10880 static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy, 10881 struct elink_params *params, 10882 struct elink_vars *vars) 10883 { 10884 u32 pair_swap; 10885 u16 data[PHY84833_CMDHDLR_MAX_ARGS]; 10886 elink_status_t status; 10887 struct elink_dev *cb = params->cb; 10888 10889 /* Check for configuration. */ 10890 pair_swap = REG_RD(cb, params->shmem_base + 10891 OFFSETOF(struct shmem_region, 10892 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & 10893 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; 10894 10895 if (pair_swap == 0) 10896 return ELINK_STATUS_OK; 10897 10898 /* Only the second argument is used for this command */ 10899 data[1] = (u16)pair_swap; 10900 10901 status = elink_84833_cmd_hdlr(phy, params, 10902 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS); 10903 if (status == ELINK_STATUS_OK) 10904 ELINK_DEBUG_P1(cb, "Pairswap OK, val=0x%x\n", data[1]); 10905 10906 return status; 10907 } 10908 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 10909 10910 static u8 elink_84833_get_reset_gpios(struct elink_dev *cb, 10911 u32 shmem_base_path[], 10912 u32 chip_id) 10913 { 10914 u32 reset_pin[2]; 10915 u32 idx; 10916 u8 reset_gpios; 10917 if (CHIP_IS_E3(chip_id)) { 10918 /* Assume that these will be GPIOs, not EPIOs. */ 10919 for (idx = 0; idx < 2; idx++) { 10920 /* Map config param to register bit. */ 10921 reset_pin[idx] = REG_RD(cb, shmem_base_path[idx] + 10922 OFFSETOF(struct shmem_region, 10923 dev_info.port_hw_config[0].e3_cmn_pin_cfg)); 10924 reset_pin[idx] = (reset_pin[idx] & 10925 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 10926 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 10927 reset_pin[idx] -= PIN_CFG_GPIO0_P0; 10928 reset_pin[idx] = (1 << reset_pin[idx]); 10929 } 10930 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 10931 } else { 10932 /* E2, look from diff place of shmem. */ 10933 for (idx = 0; idx < 2; idx++) { 10934 reset_pin[idx] = REG_RD(cb, shmem_base_path[idx] + 10935 OFFSETOF(struct shmem_region, 10936 dev_info.port_hw_config[0].default_cfg)); 10937 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; 10938 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; 10939 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; 10940 reset_pin[idx] = (1 << reset_pin[idx]); 10941 } 10942 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 10943 } 10944 10945 return reset_gpios; 10946 } 10947 10948 #ifndef EXCLUDE_NON_COMMON_INIT 10949 static elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy, 10950 struct elink_params *params) 10951 { 10952 struct elink_dev *cb = params->cb; 10953 u8 reset_gpios; 10954 u32 other_shmem_base_addr = REG_RD(cb, params->shmem2_base + 10955 OFFSETOF(struct shmem2_region, 10956 other_shmem_base_addr)); 10957 10958 u32 shmem_base_path[2]; 10959 10960 /* Work around for 84833 LED failure inside RESET status */ 10961 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 10962 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 10963 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); 10964 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 10965 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, 10966 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); 10967 10968 shmem_base_path[0] = params->shmem_base; 10969 shmem_base_path[1] = other_shmem_base_addr; 10970 10971 reset_gpios = elink_84833_get_reset_gpios(cb, shmem_base_path, 10972 params->chip_id); 10973 10974 #ifndef EDEBUG 10975 ELINK_SET_MULT_GPIO(cb, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 10976 USLEEP(cb, 10); 10977 ELINK_DEBUG_P1(cb, "84833 hw reset on pin values 0x%x\n", 10978 reset_gpios); 10979 #endif // EDEBUG 10980 10981 return ELINK_STATUS_OK; 10982 } 10983 #endif // EXCLUDE_NON_COMMON_INIT 10984 #endif // #ifndef EXCLUDE_BCM84833 10985 10986 #ifndef EXCLUDE_NON_COMMON_INIT 10987 #ifndef EXCLUDE_WARPCORE 10988 static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy, 10989 struct elink_params *params, 10990 struct elink_vars *vars) 10991 { 10992 elink_status_t rc; 10993 #if defined(ELINK_DEBUG) 10994 struct elink_dev *cb = params->cb; 10995 #endif 10996 u16 cmd_args = 0; 10997 10998 ELINK_DEBUG_P0(cb, "Don't Advertise 10GBase-T EEE\n"); 10999 11000 /* Prevent Phy from working in EEE and advertising it */ 11001 rc = elink_84833_cmd_hdlr(phy, params, 11002 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 11003 if (rc != ELINK_STATUS_OK) { 11004 ELINK_DEBUG_P0(cb, "EEE disable failed.\n"); 11005 return rc; 11006 } 11007 11008 return elink_eee_disable(phy, params, vars); 11009 } 11010 11011 static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy, 11012 struct elink_params *params, 11013 struct elink_vars *vars) 11014 { 11015 elink_status_t rc; 11016 #ifdef ELINK_DEBUG 11017 struct elink_dev *cb = params->cb; 11018 #endif 11019 u16 cmd_args = 1; 11020 11021 rc = elink_84833_cmd_hdlr(phy, params, 11022 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 11023 if (rc != ELINK_STATUS_OK) { 11024 ELINK_DEBUG_P0(cb, "EEE enable failed.\n"); 11025 return rc; 11026 } 11027 11028 return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); 11029 } 11030 #endif /* #ifndef EXCLUDE_WARPCORE */ 11031 11032 #if !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833) 11033 #define PHY84833_CONSTANT_LATENCY 1193 11034 static elink_status_t elink_848x3_config_init(struct elink_phy *phy, 11035 struct elink_params *params, 11036 struct elink_vars *vars) 11037 { 11038 struct elink_dev *cb = params->cb; 11039 u8 port, initialize = 1; 11040 u16 val; 11041 u32 actual_phy_selection; 11042 #ifndef EXCLUDE_BCM84833 11043 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; 11044 #endif // EXCLUDE_BCM84833 11045 elink_status_t rc = ELINK_STATUS_OK; 11046 11047 MSLEEP(cb, 1); 11048 11049 if (!(CHIP_IS_E1X(params->chip_id))) 11050 port = PATH_ID(cb); 11051 else 11052 port = params->port; 11053 11054 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 11055 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_3, 11056 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 11057 port); 11058 } else { 11059 /* MDIO reset */ 11060 elink_cl45_write(cb, phy, 11061 MDIO_PMA_DEVAD, 11062 MDIO_PMA_REG_CTRL, 0x8000); 11063 } 11064 11065 elink_wait_reset_complete(cb, phy, params); 11066 11067 /* Wait for GPHY to come out of reset */ 11068 MSLEEP(cb, 50); 11069 #ifndef EXCLUDE_BCM84833 11070 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 11071 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 11072 #endif // EXCLUDE_BCM84833 11073 #ifndef EXCLUDE_BCM8481 11074 /* BCM84823 requires that XGXS links up first @ 10G for normal 11075 * behavior. 11076 */ 11077 u16 temp; 11078 temp = vars->line_speed; 11079 vars->line_speed = ELINK_SPEED_10000; 11080 elink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0); 11081 elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars); 11082 vars->line_speed = temp; 11083 #endif // EXCLUDE_BCM8481 11084 #ifndef EXCLUDE_BCM84833 11085 } 11086 #endif /* Set dual-media configuration according to configuration */ 11087 11088 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 11089 MDIO_CTL_REG_84823_MEDIA, &val); 11090 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 11091 MDIO_CTL_REG_84823_MEDIA_LINE_MASK | 11092 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | 11093 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | 11094 MDIO_CTL_REG_84823_MEDIA_FIBER_1G); 11095 11096 if (CHIP_IS_E3(params->chip_id)) { 11097 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 11098 MDIO_CTL_REG_84823_MEDIA_LINE_MASK); 11099 } else { 11100 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | 11101 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); 11102 } 11103 11104 actual_phy_selection = elink_phy_selection(params); 11105 11106 switch (actual_phy_selection) { 11107 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 11108 /* Do nothing. Essentially this is like the priority copper */ 11109 break; 11110 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 11111 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; 11112 break; 11113 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 11114 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; 11115 break; 11116 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 11117 /* Do nothing here. The first PHY won't be initialized at all */ 11118 break; 11119 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 11120 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; 11121 initialize = 0; 11122 break; 11123 } 11124 if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000) 11125 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; 11126 11127 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD, 11128 MDIO_CTL_REG_84823_MEDIA, val); 11129 ELINK_DEBUG_P2(cb, "Multi_phy config = 0x%x, Media control = 0x%x\n", 11130 params->multi_phy_config, val); 11131 11132 #ifndef EXCLUDE_BCM84833 11133 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 11134 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 11135 elink_84833_pair_swap_cfg(phy, params, vars); 11136 11137 /* Keep AutogrEEEn disabled. */ 11138 cmd_args[0] = 0x0; 11139 cmd_args[1] = 0x0; 11140 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; 11141 cmd_args[3] = PHY84833_CONSTANT_LATENCY; 11142 rc = elink_84833_cmd_hdlr(phy, params, 11143 PHY84833_CMD_SET_EEE_MODE, cmd_args, 11144 PHY84833_CMDHDLR_MAX_ARGS); 11145 if (rc != ELINK_STATUS_OK) 11146 ELINK_DEBUG_P0(cb, "Cfg AutogrEEEn failed.\n"); 11147 } 11148 #endif // #ifndef EXCLUDE_BCM84833 11149 if (initialize) 11150 rc = elink_848xx_cmn_config_init(phy, params, vars); 11151 #ifdef ELINK_ENHANCEMENTS 11152 else 11153 elink_save_848xx_spirom_version(phy, cb, params->port); 11154 #endif // ELINK_ENHANCEMENTS 11155 /* 84833 PHY has a better feature and doesn't need to support this. */ 11156 #ifndef EXCLUDE_BCM8481 11157 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 11158 u32 cms_enable = REG_RD(cb, params->shmem_base + 11159 OFFSETOF(struct shmem_region, 11160 dev_info.port_hw_config[params->port].default_cfg)) & 11161 PORT_HW_CFG_ENABLE_CMS_MASK; 11162 11163 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 11164 MDIO_CTL_REG_84823_USER_CTRL_REG, &val); 11165 if (cms_enable) 11166 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; 11167 else 11168 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; 11169 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD, 11170 MDIO_CTL_REG_84823_USER_CTRL_REG, val); 11171 } 11172 #endif /* EXCLUDE_BCM8481 */ 11173 11174 #ifndef EXCLUDE_WARPCORE 11175 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 11176 MDIO_84833_TOP_CFG_FW_REV, &val); 11177 11178 /* Configure EEE support */ 11179 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && 11180 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && 11181 elink_eee_has_cap(params)) { 11182 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); 11183 if (rc != ELINK_STATUS_OK) { 11184 ELINK_DEBUG_P0(cb, "Failed to configure EEE timers\n"); 11185 elink_8483x_disable_eee(phy, params, vars); 11186 return rc; 11187 } 11188 11189 if ((phy->req_duplex == DUPLEX_FULL) && 11190 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) && 11191 (elink_eee_calc_timer(params) || 11192 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) 11193 rc = elink_8483x_enable_eee(phy, params, vars); 11194 else 11195 rc = elink_8483x_disable_eee(phy, params, vars); 11196 if (rc != ELINK_STATUS_OK) { 11197 ELINK_DEBUG_P0(cb, "Failed to set EEE advertisement\n"); 11198 return rc; 11199 } 11200 } else { 11201 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; 11202 } 11203 #endif /* #ifndef EXCLUDE_WARPCORE */ 11204 11205 #ifndef EXCLUDE_BCM84833 11206 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 11207 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 11208 /* Bring PHY out of super isolate mode as the final step. */ 11209 elink_cl45_read_and_write(cb, phy, 11210 MDIO_CTL_DEVAD, 11211 MDIO_84833_TOP_CFG_XGPHY_STRAP1, 11212 (u16)~MDIO_84833_SUPER_ISOLATE); 11213 } 11214 #endif /* #ifndef EXCLUDE_BCM84833 */ 11215 return rc; 11216 } 11217 11218 static u8 elink_848xx_read_status(struct elink_phy *phy, 11219 struct elink_params *params, 11220 struct elink_vars *vars) 11221 { 11222 struct elink_dev *cb = params->cb; 11223 u16 val, val1, val2; 11224 u8 link_up = 0; 11225 11226 11227 /* Check 10G-BaseT link status */ 11228 /* Check PMD signal ok */ 11229 elink_cl45_read(cb, phy, 11230 MDIO_AN_DEVAD, 0xFFFA, &val1); 11231 elink_cl45_read(cb, phy, 11232 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, 11233 &val2); 11234 ELINK_DEBUG_P1(cb, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); 11235 11236 /* Check link 10G */ 11237 if (val2 & (1<<11)) { 11238 vars->line_speed = ELINK_SPEED_10000; 11239 vars->duplex = DUPLEX_FULL; 11240 link_up = 1; 11241 elink_ext_phy_10G_an_resolve(cb, phy, vars); 11242 } else { /* Check Legacy speed link */ 11243 u16 legacy_status, legacy_speed; 11244 11245 /* Enable expansion register 0x42 (Operation mode status) */ 11246 elink_cl45_write(cb, phy, 11247 MDIO_AN_DEVAD, 11248 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); 11249 11250 /* Get legacy speed operation status */ 11251 elink_cl45_read(cb, phy, 11252 MDIO_AN_DEVAD, 11253 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, 11254 &legacy_status); 11255 11256 ELINK_DEBUG_P1(cb, "Legacy speed status = 0x%x\n", 11257 legacy_status); 11258 link_up = ((legacy_status & (1<<11)) == (1<<11)); 11259 legacy_speed = (legacy_status & (3<<9)); 11260 if (legacy_speed == (0<<9)) 11261 vars->line_speed = ELINK_SPEED_10; 11262 else if (legacy_speed == (1<<9)) 11263 vars->line_speed = ELINK_SPEED_100; 11264 else if (legacy_speed == (2<<9)) 11265 vars->line_speed = ELINK_SPEED_1000; 11266 else { /* Should not happen: Treat as link down */ 11267 vars->line_speed = 0; 11268 link_up = 0; 11269 } 11270 11271 #ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */ 11272 if (params->feature_config_flags & 11273 ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) { 11274 u16 mii_ctrl; 11275 11276 elink_cl45_read(cb, phy, 11277 MDIO_AN_DEVAD, 11278 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 11279 &mii_ctrl); 11280 /* For IEEE testing, check for a fake link. */ 11281 link_up |= ((mii_ctrl & 0x3040) == 0x40); 11282 } 11283 #endif 11284 11285 if (link_up) { 11286 if (legacy_status & (1<<8)) 11287 vars->duplex = DUPLEX_FULL; 11288 else 11289 vars->duplex = DUPLEX_HALF; 11290 11291 ELINK_DEBUG_P2(cb, 11292 "Link is up in %dMbps, is_duplex_full= %d\n", 11293 vars->line_speed, 11294 (vars->duplex == DUPLEX_FULL)); 11295 /* Check legacy speed AN resolution */ 11296 elink_cl45_read(cb, phy, 11297 MDIO_AN_DEVAD, 11298 MDIO_AN_REG_8481_LEGACY_MII_STATUS, 11299 &val); 11300 if (val & (1<<5)) 11301 vars->link_status |= 11302 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 11303 elink_cl45_read(cb, phy, 11304 MDIO_AN_DEVAD, 11305 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, 11306 &val); 11307 if ((val & (1<<0)) == 0) 11308 vars->link_status |= 11309 LINK_STATUS_PARALLEL_DETECTION_USED; 11310 } 11311 } 11312 if (link_up) { 11313 ELINK_DEBUG_P1(cb, "BCM848x3: link speed is %d\n", 11314 vars->line_speed); 11315 elink_ext_phy_resolve_fc(phy, params, vars); 11316 11317 /* Read LP advertised speeds */ 11318 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 11319 MDIO_AN_REG_CL37_FC_LP, &val); 11320 if (val & (1<<5)) 11321 vars->link_status |= 11322 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 11323 if (val & (1<<6)) 11324 vars->link_status |= 11325 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 11326 if (val & (1<<7)) 11327 vars->link_status |= 11328 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 11329 if (val & (1<<8)) 11330 vars->link_status |= 11331 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 11332 if (val & (1<<9)) 11333 vars->link_status |= 11334 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 11335 11336 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 11337 MDIO_AN_REG_1000T_STATUS, &val); 11338 11339 if (val & (1<<10)) 11340 vars->link_status |= 11341 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 11342 if (val & (1<<11)) 11343 vars->link_status |= 11344 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 11345 11346 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 11347 MDIO_AN_REG_MASTER_STATUS, &val); 11348 11349 if (val & (1<<11)) 11350 vars->link_status |= 11351 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 11352 11353 #if (!defined EXCLUDE_BCM84833) && (!defined EXCLUDE_WARPCORE) 11354 /* Determine if EEE was negotiated */ 11355 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 11356 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) 11357 elink_eee_an_resolve(phy, params, vars); 11358 #endif /* #ifndef EXCLUDE_WARPCORE */ 11359 } 11360 11361 return link_up; 11362 } 11363 11364 static elink_status_t elink_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) 11365 { 11366 elink_status_t status = ELINK_STATUS_OK; 11367 #ifdef ELINK_ENHANCEMENTS 11368 u32 spirom_ver; 11369 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); 11370 status = elink_format_ver(spirom_ver, str, len); 11371 #endif // ELINK_ENHANCEMENTS 11372 return status; 11373 } 11374 11375 #ifndef EXCLUDE_BCM8481 11376 static void elink_8481_hw_reset(struct elink_phy *phy, 11377 struct elink_params *params) 11378 { 11379 ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_1, 11380 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); 11381 ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_1, 11382 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); 11383 } 11384 11385 static void elink_8481_link_reset(struct elink_phy *phy, 11386 struct elink_params *params) 11387 { 11388 #ifndef EXCLUDE_LINK_RESET 11389 elink_cl45_write(params->cb, phy, 11390 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 11391 elink_cl45_write(params->cb, phy, 11392 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); 11393 #endif // EXCLUDE_LINK_RESET 11394 } 11395 #endif // #ifndef EXCLUDE_8481 11396 11397 static void elink_848x3_link_reset(struct elink_phy *phy, 11398 struct elink_params *params) 11399 { 11400 struct elink_dev *cb = params->cb; 11401 u8 port; 11402 u16 val16; 11403 11404 if (!(CHIP_IS_E1X(params->chip_id))) 11405 port = PATH_ID(cb); 11406 else 11407 port = params->port; 11408 11409 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 11410 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_3, 11411 MISC_REGISTERS_GPIO_OUTPUT_LOW, 11412 port); 11413 } else { 11414 elink_cl45_read(cb, phy, 11415 MDIO_CTL_DEVAD, 11416 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); 11417 val16 |= MDIO_84833_SUPER_ISOLATE; 11418 elink_cl45_write(cb, phy, 11419 MDIO_CTL_DEVAD, 11420 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); 11421 } 11422 } 11423 11424 static void elink_848xx_set_link_led(struct elink_phy *phy, 11425 struct elink_params *params, u8 mode) 11426 { 11427 struct elink_dev *cb = params->cb; 11428 u16 val; 11429 #ifndef ELINK_AUX_POWER 11430 u8 port; 11431 11432 if (!(CHIP_IS_E1X(params->chip_id))) 11433 port = PATH_ID(cb); 11434 else 11435 port = params->port; 11436 #endif 11437 switch (mode) { 11438 case ELINK_LED_MODE_OFF: 11439 11440 ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE OFF\n", port); 11441 11442 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 11443 SHARED_HW_CFG_LED_EXTPHY1) { 11444 11445 /* Set LED masks */ 11446 elink_cl45_write(cb, phy, 11447 MDIO_PMA_DEVAD, 11448 MDIO_PMA_REG_8481_LED1_MASK, 11449 0x0); 11450 11451 elink_cl45_write(cb, phy, 11452 MDIO_PMA_DEVAD, 11453 MDIO_PMA_REG_8481_LED2_MASK, 11454 0x0); 11455 11456 elink_cl45_write(cb, phy, 11457 MDIO_PMA_DEVAD, 11458 MDIO_PMA_REG_8481_LED3_MASK, 11459 0x0); 11460 11461 elink_cl45_write(cb, phy, 11462 MDIO_PMA_DEVAD, 11463 MDIO_PMA_REG_8481_LED5_MASK, 11464 0x0); 11465 11466 } else { 11467 elink_cl45_write(cb, phy, 11468 MDIO_PMA_DEVAD, 11469 MDIO_PMA_REG_8481_LED1_MASK, 11470 0x0); 11471 } 11472 break; 11473 case ELINK_LED_MODE_FRONT_PANEL_OFF: 11474 11475 ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE FRONT PANEL OFF\n", 11476 port); 11477 11478 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 11479 SHARED_HW_CFG_LED_EXTPHY1) { 11480 11481 /* Set LED masks */ 11482 elink_cl45_write(cb, phy, 11483 MDIO_PMA_DEVAD, 11484 MDIO_PMA_REG_8481_LED1_MASK, 11485 0x0); 11486 11487 elink_cl45_write(cb, phy, 11488 MDIO_PMA_DEVAD, 11489 MDIO_PMA_REG_8481_LED2_MASK, 11490 0x0); 11491 11492 elink_cl45_write(cb, phy, 11493 MDIO_PMA_DEVAD, 11494 MDIO_PMA_REG_8481_LED3_MASK, 11495 0x0); 11496 11497 elink_cl45_write(cb, phy, 11498 MDIO_PMA_DEVAD, 11499 MDIO_PMA_REG_8481_LED5_MASK, 11500 0x20); 11501 11502 } else { 11503 elink_cl45_write(cb, phy, 11504 MDIO_PMA_DEVAD, 11505 MDIO_PMA_REG_8481_LED1_MASK, 11506 0x0); 11507 if (phy->type == 11508 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 11509 /* Disable MI_INT interrupt before setting LED4 11510 * source to constant off. 11511 */ 11512 if (REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 + 11513 params->port*4) & 11514 ELINK_NIG_MASK_MI_INT) { 11515 params->link_flags |= 11516 ELINK_LINK_FLAGS_INT_DISABLED; 11517 11518 elink_bits_dis( 11519 cb, 11520 NIG_REG_MASK_INTERRUPT_PORT0 + 11521 params->port*4, 11522 ELINK_NIG_MASK_MI_INT); 11523 } 11524 elink_cl45_write(cb, phy, 11525 MDIO_PMA_DEVAD, 11526 MDIO_PMA_REG_8481_SIGNAL_MASK, 11527 0x0); 11528 } 11529 } 11530 break; 11531 case ELINK_LED_MODE_ON: 11532 11533 ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE ON\n", port); 11534 11535 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 11536 SHARED_HW_CFG_LED_EXTPHY1) { 11537 /* Set control reg */ 11538 elink_cl45_read(cb, phy, 11539 MDIO_PMA_DEVAD, 11540 MDIO_PMA_REG_8481_LINK_SIGNAL, 11541 &val); 11542 val &= 0x8000; 11543 val |= 0x2492; 11544 11545 elink_cl45_write(cb, phy, 11546 MDIO_PMA_DEVAD, 11547 MDIO_PMA_REG_8481_LINK_SIGNAL, 11548 val); 11549 11550 /* Set LED masks */ 11551 elink_cl45_write(cb, phy, 11552 MDIO_PMA_DEVAD, 11553 MDIO_PMA_REG_8481_LED1_MASK, 11554 0x0); 11555 11556 elink_cl45_write(cb, phy, 11557 MDIO_PMA_DEVAD, 11558 MDIO_PMA_REG_8481_LED2_MASK, 11559 0x20); 11560 11561 elink_cl45_write(cb, phy, 11562 MDIO_PMA_DEVAD, 11563 MDIO_PMA_REG_8481_LED3_MASK, 11564 0x20); 11565 11566 elink_cl45_write(cb, phy, 11567 MDIO_PMA_DEVAD, 11568 MDIO_PMA_REG_8481_LED5_MASK, 11569 0x0); 11570 } else { 11571 elink_cl45_write(cb, phy, 11572 MDIO_PMA_DEVAD, 11573 MDIO_PMA_REG_8481_LED1_MASK, 11574 0x20); 11575 if (phy->type == 11576 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 11577 /* Disable MI_INT interrupt before setting LED4 11578 * source to constant on. 11579 */ 11580 if (REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 + 11581 params->port*4) & 11582 ELINK_NIG_MASK_MI_INT) { 11583 params->link_flags |= 11584 ELINK_LINK_FLAGS_INT_DISABLED; 11585 11586 elink_bits_dis( 11587 cb, 11588 NIG_REG_MASK_INTERRUPT_PORT0 + 11589 params->port*4, 11590 ELINK_NIG_MASK_MI_INT); 11591 } 11592 elink_cl45_write(cb, phy, 11593 MDIO_PMA_DEVAD, 11594 MDIO_PMA_REG_8481_SIGNAL_MASK, 11595 0x20); 11596 } 11597 } 11598 break; 11599 11600 case ELINK_LED_MODE_OPER: 11601 11602 ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE OPER\n", port); 11603 11604 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 11605 SHARED_HW_CFG_LED_EXTPHY1) { 11606 11607 /* Set control reg */ 11608 elink_cl45_read(cb, phy, 11609 MDIO_PMA_DEVAD, 11610 MDIO_PMA_REG_8481_LINK_SIGNAL, 11611 &val); 11612 11613 if (!((val & 11614 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) 11615 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { 11616 ELINK_DEBUG_P0(cb, "Setting LINK_SIGNAL\n"); 11617 elink_cl45_write(cb, phy, 11618 MDIO_PMA_DEVAD, 11619 MDIO_PMA_REG_8481_LINK_SIGNAL, 11620 0xa492); 11621 } 11622 11623 /* Set LED masks */ 11624 elink_cl45_write(cb, phy, 11625 MDIO_PMA_DEVAD, 11626 MDIO_PMA_REG_8481_LED1_MASK, 11627 0x10); 11628 11629 elink_cl45_write(cb, phy, 11630 MDIO_PMA_DEVAD, 11631 MDIO_PMA_REG_8481_LED2_MASK, 11632 0x80); 11633 11634 elink_cl45_write(cb, phy, 11635 MDIO_PMA_DEVAD, 11636 MDIO_PMA_REG_8481_LED3_MASK, 11637 0x98); 11638 11639 elink_cl45_write(cb, phy, 11640 MDIO_PMA_DEVAD, 11641 MDIO_PMA_REG_8481_LED5_MASK, 11642 0x40); 11643 11644 } else { 11645 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED 11646 * sources are all wired through LED1, rather than only 11647 * 10G in other modes. 11648 */ 11649 val = ((params->hw_led_mode << 11650 SHARED_HW_CFG_LED_MODE_SHIFT) == 11651 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80; 11652 11653 elink_cl45_write(cb, phy, 11654 MDIO_PMA_DEVAD, 11655 MDIO_PMA_REG_8481_LED1_MASK, 11656 val); 11657 11658 /* Tell LED3 to blink on source */ 11659 elink_cl45_read(cb, phy, 11660 MDIO_PMA_DEVAD, 11661 MDIO_PMA_REG_8481_LINK_SIGNAL, 11662 &val); 11663 val &= ~(7<<6); 11664 val |= (1<<6); /* A83B[8:6]= 1 */ 11665 elink_cl45_write(cb, phy, 11666 MDIO_PMA_DEVAD, 11667 MDIO_PMA_REG_8481_LINK_SIGNAL, 11668 val); 11669 if (phy->type == 11670 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 11671 /* Restore LED4 source to external link, 11672 * and re-enable interrupts. 11673 */ 11674 elink_cl45_write(cb, phy, 11675 MDIO_PMA_DEVAD, 11676 MDIO_PMA_REG_8481_SIGNAL_MASK, 11677 0x40); 11678 if (params->link_flags & 11679 ELINK_LINK_FLAGS_INT_DISABLED) { 11680 elink_link_int_enable(params); 11681 params->link_flags &= 11682 ~ELINK_LINK_FLAGS_INT_DISABLED; 11683 } 11684 } 11685 } 11686 break; 11687 } 11688 11689 /* This is a workaround for E3+84833 until autoneg 11690 * restart is fixed in f/w 11691 */ 11692 if (CHIP_IS_E3(params->chip_id)) { 11693 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 11694 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); 11695 } 11696 } 11697 #endif /* EXCLUDE_BCM8481 / EXCLUDE_BCM8481 */ 11698 #endif // EXCLUDE_NON_COMMON_INIT 11699 11700 /******************************************************************/ 11701 /* 54618SE PHY SECTION */ 11702 /******************************************************************/ 11703 #if (!defined EXCLUDE_NON_COMMON_INIT) && (!defined EXCLUDE_BCM54618SE) 11704 #ifdef ELINK_AUX_POWER 11705 static int elink_54618se_init_required(struct elink_phy *phy, 11706 struct elink_params *params) 11707 { 11708 u16 autoneg_val, an_1000_val, an_10_100_val, ctrl, legacy_status; 11709 struct elink_dev *cb = params->cb; 11710 /* read all advertisement */ 11711 elink_cl22_read(cb, phy, 11712 MDIO_PMA_REG_CTRL, &ctrl); 11713 /* In case PHY is in reset */ 11714 if (ctrl & (1<<15)) 11715 return 1; 11716 11717 elink_cl22_read(cb, phy, 11718 0x09, 11719 &an_1000_val); 11720 elink_cl22_read(cb, phy, 11721 0x04, 11722 &an_10_100_val); 11723 elink_cl22_read(cb, phy, 11724 MDIO_PMA_REG_CTRL, 11725 &autoneg_val); 11726 elink_cl22_read(cb, phy, 11727 0x19, 11728 &legacy_status); 11729 /* Check conditions to avoid link reset in case link was 11730 * already initialized and up 11731 */ 11732 if ((an_1000_val & 0x300) && 11733 (an_10_100_val & 0x1e0) && 11734 (autoneg_val & 0x1000) && 11735 (legacy_status & (1<<2))) 11736 return 0; 11737 return 1; 11738 } 11739 #endif // ELINK_AUX_POWER 11740 static void elink_54618se_specific_func(struct elink_phy *phy, 11741 struct elink_params *params, 11742 u32 action) 11743 { 11744 struct elink_dev *cb = params->cb; 11745 u16 temp; 11746 switch (action) { 11747 case ELINK_PHY_INIT: 11748 /* Configure LED4: set to INTR (0x6). */ 11749 /* Accessing shadow register 0xe. */ 11750 elink_cl22_write(cb, phy, 11751 MDIO_REG_GPHY_SHADOW, 11752 MDIO_REG_GPHY_SHADOW_LED_SEL2); 11753 elink_cl22_read(cb, phy, 11754 MDIO_REG_GPHY_SHADOW, 11755 &temp); 11756 temp &= ~(0xf << 4); 11757 temp |= (0x6 << 4); 11758 elink_cl22_write(cb, phy, 11759 MDIO_REG_GPHY_SHADOW, 11760 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 11761 /* Configure INTR based on link status change. */ 11762 elink_cl22_write(cb, phy, 11763 MDIO_REG_INTR_MASK, 11764 ~MDIO_REG_INTR_MASK_LINK_STATUS); 11765 break; 11766 } 11767 } 11768 11769 static elink_status_t elink_54618se_config_init(struct elink_phy *phy, 11770 struct elink_params *params, 11771 struct elink_vars *vars) 11772 { 11773 struct elink_dev *cb = params->cb; 11774 u8 port; 11775 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; 11776 u32 cfg_pin; 11777 #ifdef ELINK_AUX_POWER 11778 u32 link_init_required = 1; 11779 if (!elink_54618se_init_required(phy, params)) 11780 link_init_required = 0; 11781 if (link_init_required) { 11782 #endif 11783 11784 ELINK_DEBUG_P0(cb, "54618SE cfg init\n"); 11785 MSLEEP(cb, 1); 11786 11787 /* This works with E3 only, no need to check the chip 11788 * before determining the port. 11789 */ 11790 port = params->port; 11791 11792 cfg_pin = (REG_RD(cb, params->shmem_base + 11793 OFFSETOF(struct shmem_region, 11794 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 11795 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 11796 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 11797 11798 /* Drive pin high to bring the GPHY out of reset. */ 11799 elink_set_cfg_pin(cb, cfg_pin, 1); 11800 11801 /* wait for GPHY to reset */ 11802 MSLEEP(cb, 50); 11803 11804 /* reset phy */ 11805 elink_cl22_write(cb, phy, 11806 MDIO_PMA_REG_CTRL, 0x8000); 11807 elink_wait_reset_complete(cb, phy, params); 11808 11809 /* Wait for GPHY to reset */ 11810 MSLEEP(cb, 50); 11811 11812 #ifdef ELINK_AUX_POWER 11813 } // If init required 11814 #endif 11815 11816 elink_54618se_specific_func(phy, params, ELINK_PHY_INIT); 11817 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ 11818 elink_cl22_write(cb, phy, 11819 MDIO_REG_GPHY_SHADOW, 11820 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); 11821 elink_cl22_read(cb, phy, 11822 MDIO_REG_GPHY_SHADOW, 11823 &temp); 11824 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; 11825 elink_cl22_write(cb, phy, 11826 MDIO_REG_GPHY_SHADOW, 11827 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 11828 11829 /* Set up fc */ 11830 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 11831 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 11832 #ifdef ELINK_AUX_POWER 11833 if (!link_init_required) 11834 return ELINK_STATUS_OK; 11835 #endif 11836 fc_val = 0; 11837 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 11838 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) 11839 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 11840 11841 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 11842 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 11843 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 11844 11845 /* Read all advertisement */ 11846 elink_cl22_read(cb, phy, 11847 0x09, 11848 &an_1000_val); 11849 11850 elink_cl22_read(cb, phy, 11851 0x04, 11852 &an_10_100_val); 11853 11854 elink_cl22_read(cb, phy, 11855 MDIO_PMA_REG_CTRL, 11856 &autoneg_val); 11857 11858 /* Disable forced speed */ 11859 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 11860 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | 11861 (1<<11)); 11862 11863 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 11864 (phy->speed_cap_mask & 11865 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 11866 (phy->req_line_speed == ELINK_SPEED_1000)) { 11867 an_1000_val |= (1<<8); 11868 autoneg_val |= (1<<9 | 1<<12); 11869 if (phy->req_duplex == DUPLEX_FULL) 11870 an_1000_val |= (1<<9); 11871 ELINK_DEBUG_P0(cb, "Advertising 1G\n"); 11872 } else 11873 an_1000_val &= ~((1<<8) | (1<<9)); 11874 11875 elink_cl22_write(cb, phy, 11876 0x09, 11877 an_1000_val); 11878 elink_cl22_read(cb, phy, 11879 0x09, 11880 &an_1000_val); 11881 11882 /* Advertise 10/100 link speed */ 11883 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { 11884 if (phy->speed_cap_mask & 11885 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { 11886 an_10_100_val |= (1<<5); 11887 autoneg_val |= (1<<9 | 1<<12); 11888 ELINK_DEBUG_P0(cb, "Advertising 10M-HD\n"); 11889 } 11890 if (phy->speed_cap_mask & 11891 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) { 11892 an_10_100_val |= (1<<6); 11893 autoneg_val |= (1<<9 | 1<<12); 11894 ELINK_DEBUG_P0(cb, "Advertising 10M-FD\n"); 11895 } 11896 if (phy->speed_cap_mask & 11897 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { 11898 an_10_100_val |= (1<<7); 11899 autoneg_val |= (1<<9 | 1<<12); 11900 ELINK_DEBUG_P0(cb, "Advertising 100M-HD\n"); 11901 } 11902 if (phy->speed_cap_mask & 11903 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { 11904 an_10_100_val |= (1<<8); 11905 autoneg_val |= (1<<9 | 1<<12); 11906 ELINK_DEBUG_P0(cb, "Advertising 100M-FD\n"); 11907 } 11908 } 11909 11910 /* Only 10/100 are allowed to work in FORCE mode */ 11911 if (phy->req_line_speed == ELINK_SPEED_100) { 11912 autoneg_val |= (1<<13); 11913 /* Enabled AUTO-MDIX when autoneg is disabled */ 11914 elink_cl22_write(cb, phy, 11915 0x18, 11916 (1<<15 | 1<<9 | 7<<0)); 11917 ELINK_DEBUG_P0(cb, "Setting 100M force\n"); 11918 } 11919 if (phy->req_line_speed == ELINK_SPEED_10) { 11920 /* Enabled AUTO-MDIX when autoneg is disabled */ 11921 elink_cl22_write(cb, phy, 11922 0x18, 11923 (1<<15 | 1<<9 | 7<<0)); 11924 ELINK_DEBUG_P0(cb, "Setting 10M force\n"); 11925 } 11926 11927 if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) { 11928 elink_status_t rc; 11929 11930 elink_cl22_write(cb, phy, MDIO_REG_GPHY_EXP_ACCESS, 11931 MDIO_REG_GPHY_EXP_ACCESS_TOP | 11932 MDIO_REG_GPHY_EXP_TOP_2K_BUF); 11933 elink_cl22_read(cb, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); 11934 temp &= 0xfffe; 11935 elink_cl22_write(cb, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); 11936 11937 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); 11938 if (rc != ELINK_STATUS_OK) { 11939 ELINK_DEBUG_P0(cb, "Failed to configure EEE timers\n"); 11940 elink_eee_disable(phy, params, vars); 11941 } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) && 11942 (phy->req_duplex == DUPLEX_FULL) && 11943 (elink_eee_calc_timer(params) || 11944 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) { 11945 /* Need to advertise EEE only when requested, 11946 * and either no LPI assertion was requested, 11947 * or it was requested and a valid timer was set. 11948 * Also notice full duplex is required for EEE. 11949 */ 11950 elink_eee_advertise(phy, params, vars, 11951 SHMEM_EEE_1G_ADV); 11952 } else { 11953 ELINK_DEBUG_P0(cb, "Don't Advertise 1GBase-T EEE\n"); 11954 elink_eee_disable(phy, params, vars); 11955 } 11956 } else { 11957 vars->eee_status &= ~SHMEM_EEE_1G_ADV << 11958 SHMEM_EEE_SUPPORTED_SHIFT; 11959 11960 if (phy->flags & ELINK_FLAGS_EEE) { 11961 /* Handle legacy auto-grEEEn */ 11962 if (params->feature_config_flags & 11963 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) { 11964 temp = 6; 11965 ELINK_DEBUG_P0(cb, "Enabling Auto-GrEEEn\n"); 11966 } else { 11967 temp = 0; 11968 ELINK_DEBUG_P0(cb, "Don't Adv. EEE\n"); 11969 } 11970 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 11971 MDIO_AN_REG_EEE_ADV, temp); 11972 } 11973 } 11974 11975 elink_cl22_write(cb, phy, 11976 0x04, 11977 an_10_100_val | fc_val); 11978 11979 if (phy->req_duplex == DUPLEX_FULL) 11980 autoneg_val |= (1<<8); 11981 11982 elink_cl22_write(cb, phy, 11983 MDIO_PMA_REG_CTRL, autoneg_val); 11984 11985 return ELINK_STATUS_OK; 11986 } 11987 11988 11989 static void elink_5461x_set_link_led(struct elink_phy *phy, 11990 struct elink_params *params, u8 mode) 11991 { 11992 #ifdef ELINK_ENHANCEMENTS 11993 struct elink_dev *cb = params->cb; 11994 u16 temp; 11995 11996 elink_cl22_write(cb, phy, 11997 MDIO_REG_GPHY_SHADOW, 11998 MDIO_REG_GPHY_SHADOW_LED_SEL1); 11999 elink_cl22_read(cb, phy, 12000 MDIO_REG_GPHY_SHADOW, 12001 &temp); 12002 temp &= 0xff00; 12003 12004 ELINK_DEBUG_P1(cb, "54618x set link led (mode=%x)\n", mode); 12005 switch (mode) { 12006 case ELINK_LED_MODE_FRONT_PANEL_OFF: 12007 case ELINK_LED_MODE_OFF: 12008 temp |= 0x00ee; 12009 break; 12010 case ELINK_LED_MODE_OPER: 12011 temp |= 0x0001; 12012 break; 12013 case ELINK_LED_MODE_ON: 12014 temp |= 0x00ff; 12015 break; 12016 default: 12017 break; 12018 } 12019 elink_cl22_write(cb, phy, 12020 MDIO_REG_GPHY_SHADOW, 12021 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 12022 return; 12023 #endif // ELINK_ENHANCEMENTS 12024 } 12025 12026 12027 static void elink_54618se_link_reset(struct elink_phy *phy, 12028 struct elink_params *params) 12029 { 12030 struct elink_dev *cb = params->cb; 12031 u32 cfg_pin; 12032 u8 port; 12033 12034 #ifdef ELINK_AUX_POWER 12035 if (!elink_54618se_init_required(phy, params)) 12036 return; 12037 #endif // ELINK_AUX_POWER 12038 /* In case of no EPIO routed to reset the GPHY, put it 12039 * in low power mode. 12040 */ 12041 elink_cl22_write(cb, phy, MDIO_PMA_REG_CTRL, 0x800); 12042 /* This works with E3 only, no need to check the chip 12043 * before determining the port. 12044 */ 12045 port = params->port; 12046 cfg_pin = (REG_RD(cb, params->shmem_base + 12047 OFFSETOF(struct shmem_region, 12048 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 12049 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 12050 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 12051 12052 /* Drive pin low to put GPHY in reset. */ 12053 elink_set_cfg_pin(cb, cfg_pin, 0); 12054 } 12055 12056 static u8 elink_54618se_read_status(struct elink_phy *phy, 12057 struct elink_params *params, 12058 struct elink_vars *vars) 12059 { 12060 struct elink_dev *cb = params->cb; 12061 u16 val; 12062 u8 link_up = 0; 12063 u16 legacy_status, legacy_speed; 12064 12065 /* Get speed operation status */ 12066 elink_cl22_read(cb, phy, 12067 MDIO_REG_GPHY_AUX_STATUS, 12068 &legacy_status); 12069 ELINK_DEBUG_P1(cb, "54618SE read_status: 0x%x\n", legacy_status); 12070 12071 /* Read status to clear the PHY interrupt. */ 12072 elink_cl22_read(cb, phy, 12073 MDIO_REG_INTR_STATUS, 12074 &val); 12075 12076 link_up = ((legacy_status & (1<<2)) == (1<<2)); 12077 12078 if (link_up) { 12079 legacy_speed = (legacy_status & (7<<8)); 12080 if (legacy_speed == (7<<8)) { 12081 vars->line_speed = ELINK_SPEED_1000; 12082 vars->duplex = DUPLEX_FULL; 12083 } else if (legacy_speed == (6<<8)) { 12084 vars->line_speed = ELINK_SPEED_1000; 12085 vars->duplex = DUPLEX_HALF; 12086 } else if (legacy_speed == (5<<8)) { 12087 vars->line_speed = ELINK_SPEED_100; 12088 vars->duplex = DUPLEX_FULL; 12089 } 12090 /* Omitting 100Base-T4 for now */ 12091 else if (legacy_speed == (3<<8)) { 12092 vars->line_speed = ELINK_SPEED_100; 12093 vars->duplex = DUPLEX_HALF; 12094 } else if (legacy_speed == (2<<8)) { 12095 vars->line_speed = ELINK_SPEED_10; 12096 vars->duplex = DUPLEX_FULL; 12097 } else if (legacy_speed == (1<<8)) { 12098 vars->line_speed = ELINK_SPEED_10; 12099 vars->duplex = DUPLEX_HALF; 12100 } else /* Should not happen */ 12101 vars->line_speed = 0; 12102 12103 ELINK_DEBUG_P2(cb, 12104 "Link is up in %dMbps, is_duplex_full= %d\n", 12105 vars->line_speed, 12106 (vars->duplex == DUPLEX_FULL)); 12107 12108 /* Check legacy speed AN resolution */ 12109 elink_cl22_read(cb, phy, 12110 0x01, 12111 &val); 12112 if (val & (1<<5)) 12113 vars->link_status |= 12114 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 12115 elink_cl22_read(cb, phy, 12116 0x06, 12117 &val); 12118 if ((val & (1<<0)) == 0) 12119 vars->link_status |= 12120 LINK_STATUS_PARALLEL_DETECTION_USED; 12121 12122 ELINK_DEBUG_P1(cb, "BCM54618SE: link speed is %d\n", 12123 vars->line_speed); 12124 12125 elink_ext_phy_resolve_fc(phy, params, vars); 12126 12127 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 12128 /* Report LP advertised speeds */ 12129 elink_cl22_read(cb, phy, 0x5, &val); 12130 12131 if (val & (1<<5)) 12132 vars->link_status |= 12133 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 12134 if (val & (1<<6)) 12135 vars->link_status |= 12136 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 12137 if (val & (1<<7)) 12138 vars->link_status |= 12139 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 12140 if (val & (1<<8)) 12141 vars->link_status |= 12142 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 12143 if (val & (1<<9)) 12144 vars->link_status |= 12145 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 12146 12147 elink_cl22_read(cb, phy, 0xa, &val); 12148 if (val & (1<<10)) 12149 vars->link_status |= 12150 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 12151 if (val & (1<<11)) 12152 vars->link_status |= 12153 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 12154 12155 if ((phy->flags & ELINK_FLAGS_EEE) && 12156 elink_eee_has_cap(params)) 12157 elink_eee_an_resolve(phy, params, vars); 12158 } 12159 } 12160 return link_up; 12161 } 12162 12163 static void elink_54618se_config_loopback(struct elink_phy *phy, 12164 struct elink_params *params) 12165 { 12166 #ifdef ELINK_INCLUDE_LOOPBACK 12167 struct elink_dev *cb = params->cb; 12168 u16 val; 12169 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 12170 12171 ELINK_DEBUG_P0(cb, "2PMA/PMD ext_phy_loopback: 54618se\n"); 12172 12173 /* Enable master/slave manual mmode and set to master */ 12174 /* mii write 9 [bits set 11 12] */ 12175 elink_cl22_write(cb, phy, 0x09, 3<<11); 12176 12177 /* forced 1G and disable autoneg */ 12178 /* set val [mii read 0] */ 12179 /* set val [expr $val & [bits clear 6 12 13]] */ 12180 /* set val [expr $val | [bits set 6 8]] */ 12181 /* mii write 0 $val */ 12182 elink_cl22_read(cb, phy, 0x00, &val); 12183 val &= ~((1<<6) | (1<<12) | (1<<13)); 12184 val |= (1<<6) | (1<<8); 12185 elink_cl22_write(cb, phy, 0x00, val); 12186 12187 /* Set external loopback and Tx using 6dB coding */ 12188 /* mii write 0x18 7 */ 12189 /* set val [mii read 0x18] */ 12190 /* mii write 0x18 [expr $val | [bits set 10 15]] */ 12191 elink_cl22_write(cb, phy, 0x18, 7); 12192 elink_cl22_read(cb, phy, 0x18, &val); 12193 elink_cl22_write(cb, phy, 0x18, val | (1<<10) | (1<<15)); 12194 12195 /* This register opens the gate for the UMAC despite its name */ 12196 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 12197 12198 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 12199 * length used by the MAC receive logic to check frames. 12200 */ 12201 REG_WR(cb, umac_base + UMAC_REG_MAXFR, 0x2710); 12202 #endif // ELINK_INCLUDE_LOOPBACK 12203 } 12204 12205 #endif // (!defined EXCLUDE_NON_COMMON_INIT) && (!defined EXCLUDE_BCM54618SE) 12206 /******************************************************************/ 12207 /* SFX7101 PHY SECTION */ 12208 /******************************************************************/ 12209 #ifndef EXCLUDE_SFX7101 12210 static void elink_7101_config_loopback(struct elink_phy *phy, 12211 struct elink_params *params) 12212 { 12213 struct elink_dev *cb = params->cb; 12214 /* SFX7101_XGXS_TEST1 */ 12215 elink_cl45_write(cb, phy, 12216 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); 12217 } 12218 12219 static elink_status_t elink_7101_config_init(struct elink_phy *phy, 12220 struct elink_params *params, 12221 struct elink_vars *vars) 12222 { 12223 u16 fw_ver1, fw_ver2, val; 12224 struct elink_dev *cb = params->cb; 12225 ELINK_DEBUG_P0(cb, "Setting the SFX7101 LASI indication\n"); 12226 12227 /* Restore normal power mode*/ 12228 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 12229 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 12230 /* HW reset */ 12231 elink_ext_phy_hw_reset(cb, params->port); 12232 elink_wait_reset_complete(cb, phy, params); 12233 12234 elink_cl45_write(cb, phy, 12235 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); 12236 ELINK_DEBUG_P0(cb, "Setting the SFX7101 LED to blink on traffic\n"); 12237 elink_cl45_write(cb, phy, 12238 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); 12239 12240 elink_ext_phy_set_pause(params, phy, vars); 12241 /* Restart autoneg */ 12242 elink_cl45_read(cb, phy, 12243 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); 12244 val |= 0x200; 12245 elink_cl45_write(cb, phy, 12246 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); 12247 12248 /* Save spirom version */ 12249 elink_cl45_read(cb, phy, 12250 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); 12251 12252 elink_cl45_read(cb, phy, 12253 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); 12254 elink_save_spirom_version(cb, params->port, 12255 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); 12256 return ELINK_STATUS_OK; 12257 } 12258 12259 static u8 elink_7101_read_status(struct elink_phy *phy, 12260 struct elink_params *params, 12261 struct elink_vars *vars) 12262 { 12263 struct elink_dev *cb = params->cb; 12264 u8 link_up; 12265 u16 val1, val2; 12266 elink_cl45_read(cb, phy, 12267 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 12268 elink_cl45_read(cb, phy, 12269 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 12270 ELINK_DEBUG_P2(cb, "10G-base-T LASI status 0x%x->0x%x\n", 12271 val2, val1); 12272 elink_cl45_read(cb, phy, 12273 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 12274 elink_cl45_read(cb, phy, 12275 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 12276 ELINK_DEBUG_P2(cb, "10G-base-T PMA status 0x%x->0x%x\n", 12277 val2, val1); 12278 link_up = ((val1 & 4) == 4); 12279 /* If link is up print the AN outcome of the SFX7101 PHY */ 12280 if (link_up) { 12281 elink_cl45_read(cb, phy, 12282 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, 12283 &val2); 12284 vars->line_speed = ELINK_SPEED_10000; 12285 vars->duplex = DUPLEX_FULL; 12286 ELINK_DEBUG_P2(cb, "SFX7101 AN status 0x%x->Master=%x\n", 12287 val2, (val2 & (1<<14))); 12288 elink_ext_phy_10G_an_resolve(cb, phy, vars); 12289 elink_ext_phy_resolve_fc(phy, params, vars); 12290 12291 /* Read LP advertised speeds */ 12292 if (val2 & (1<<11)) 12293 vars->link_status |= 12294 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 12295 } 12296 return link_up; 12297 } 12298 12299 static elink_status_t elink_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) 12300 { 12301 if (*len < 5) 12302 return ELINK_STATUS_ERROR; 12303 str[0] = (spirom_ver & 0xFF); 12304 str[1] = (spirom_ver & 0xFF00) >> 8; 12305 str[2] = (spirom_ver & 0xFF0000) >> 16; 12306 str[3] = (spirom_ver & 0xFF000000) >> 24; 12307 str[4] = '\0'; 12308 *len -= 5; 12309 return ELINK_STATUS_OK; 12310 } 12311 12312 void elink_sfx7101_sp_sw_reset(struct elink_dev *cb, struct elink_phy *phy) 12313 { 12314 u16 val, cnt; 12315 12316 elink_cl45_read(cb, phy, 12317 MDIO_PMA_DEVAD, 12318 MDIO_PMA_REG_7101_RESET, &val); 12319 12320 for (cnt = 0; cnt < 10; cnt++) { 12321 MSLEEP(cb, 50); 12322 /* Writes a self-clearing reset */ 12323 elink_cl45_write(cb, phy, 12324 MDIO_PMA_DEVAD, 12325 MDIO_PMA_REG_7101_RESET, 12326 (val | (1<<15))); 12327 /* Wait for clear */ 12328 elink_cl45_read(cb, phy, 12329 MDIO_PMA_DEVAD, 12330 MDIO_PMA_REG_7101_RESET, &val); 12331 12332 if ((val & (1<<15)) == 0) 12333 break; 12334 } 12335 } 12336 12337 static void elink_7101_hw_reset(struct elink_phy *phy, 12338 struct elink_params *params) { 12339 #ifdef ELINK_ENHANCEMENTS 12340 /* Low power mode is controlled by GPIO 2 */ 12341 ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_2, 12342 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 12343 /* The PHY reset is controlled by GPIO 1 */ 12344 ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_1, 12345 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 12346 #endif // ELINK_ENHANCEMENTS 12347 } 12348 12349 static void elink_7101_set_link_led(struct elink_phy *phy, 12350 struct elink_params *params, u8 mode) 12351 { 12352 u16 val = 0; 12353 struct elink_dev *cb = params->cb; 12354 switch (mode) { 12355 case ELINK_LED_MODE_FRONT_PANEL_OFF: 12356 case ELINK_LED_MODE_OFF: 12357 val = 2; 12358 break; 12359 case ELINK_LED_MODE_ON: 12360 val = 1; 12361 break; 12362 case ELINK_LED_MODE_OPER: 12363 val = 0; 12364 break; 12365 } 12366 elink_cl45_write(cb, phy, 12367 MDIO_PMA_DEVAD, 12368 MDIO_PMA_REG_7107_LINK_LED_CNTL, 12369 val); 12370 } 12371 #endif /* EXCLUDE_SFX7101 */ 12372 #endif /* ELINK_EMUL_ONLY */ 12373 12374 /******************************************************************/ 12375 /* STATIC PHY DECLARATION */ 12376 /******************************************************************/ 12377 12378 static const struct elink_phy phy_null = { 12379 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, 12380 /*.addr = */0, 12381 /*.def_md_devad = */0, 12382 /*.flags = */ELINK_FLAGS_INIT_XGXS_FIRST, 12383 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12384 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12385 /*.mdio_ctrl = */0, 12386 /*.supported = */0, 12387 /*.media_type = */ELINK_ETH_PHY_NOT_PRESENT, 12388 /*.ver_addr = */0, 12389 /*.req_flow_ctrl = */0, 12390 /*.req_line_speed = */0, 12391 /*.speed_cap_mask = */0, 12392 /*.req_duplex = */0, 12393 /*.rsrv = */0, 12394 /*.config_init = */(config_init_t)NULL, 12395 /*.read_status = */(read_status_t)NULL, 12396 /*.link_reset = */(link_reset_t)NULL, 12397 /*.config_loopback = */(config_loopback_t)NULL, 12398 /*.format_fw_ver = */(format_fw_ver_t)NULL, 12399 /*.hw_reset = */(hw_reset_t)NULL, 12400 /*.set_link_led = */(set_link_led_t)NULL, 12401 /*.phy_specific_func = */(phy_specific_func_t)NULL 12402 }; 12403 12404 #ifndef EXCLUDE_SERDES 12405 static const struct elink_phy phy_serdes = { 12406 /*.type = */PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, 12407 /*.addr = */0xff, 12408 /*.def_md_devad = */0, 12409 /*.flags = */0, 12410 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12411 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12412 /*.mdio_ctrl = */0, 12413 /*.supported = */(ELINK_SUPPORTED_10baseT_Half | 12414 ELINK_SUPPORTED_10baseT_Full | 12415 ELINK_SUPPORTED_100baseT_Half | 12416 ELINK_SUPPORTED_100baseT_Full | 12417 ELINK_SUPPORTED_1000baseT_Full | 12418 ELINK_SUPPORTED_2500baseX_Full | 12419 ELINK_SUPPORTED_TP | 12420 ELINK_SUPPORTED_Autoneg | 12421 ELINK_SUPPORTED_Pause | 12422 ELINK_SUPPORTED_Asym_Pause), 12423 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12424 /*.ver_addr = */0, 12425 /*.req_flow_ctrl = */0, 12426 /*.req_line_speed = */0, 12427 /*.speed_cap_mask = */0, 12428 /*.req_duplex = */0, 12429 /*.rsrv = */0, 12430 /*.config_init = */(config_init_t)elink_xgxs_config_init, 12431 /*.read_status = */(read_status_t)elink_link_settings_status, 12432 /*.link_reset = */(link_reset_t)elink_int_link_reset, 12433 /*.config_loopback = */(config_loopback_t)NULL, 12434 /*.format_fw_ver = */(format_fw_ver_t)NULL, 12435 /*.hw_reset = */(hw_reset_t)NULL, 12436 /*.set_link_led = */(set_link_led_t)NULL, 12437 /*.phy_specific_func = */(phy_specific_func_t)NULL 12438 }; 12439 12440 #endif /* #ifndef EXCLUDE_SERDES */ 12441 #ifndef EXCLUDE_XGXS 12442 static const struct elink_phy phy_xgxs = { 12443 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 12444 /*.addr = */0xff, 12445 /*.def_md_devad = */0, 12446 /*.flags = */0, 12447 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12448 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12449 /*.mdio_ctrl = */0, 12450 /*.supported = */(ELINK_SUPPORTED_10baseT_Half | 12451 ELINK_SUPPORTED_10baseT_Full | 12452 ELINK_SUPPORTED_100baseT_Half | 12453 ELINK_SUPPORTED_100baseT_Full | 12454 ELINK_SUPPORTED_1000baseT_Full | 12455 ELINK_SUPPORTED_2500baseX_Full | 12456 ELINK_SUPPORTED_10000baseT_Full | 12457 ELINK_SUPPORTED_FIBRE | 12458 ELINK_SUPPORTED_Autoneg | 12459 ELINK_SUPPORTED_Pause | 12460 ELINK_SUPPORTED_Asym_Pause), 12461 /*.media_type = */ELINK_ETH_PHY_CX4, 12462 /*.ver_addr = */0, 12463 /*.req_flow_ctrl = */0, 12464 /*.req_line_speed = */0, 12465 /*.speed_cap_mask = */0, 12466 /*.req_duplex = */0, 12467 /*.rsrv = */0, 12468 #ifndef EXCLUDE_NON_COMMON_INIT 12469 /*.config_init = */(config_init_t)elink_xgxs_config_init, 12470 /*.read_status = */(read_status_t)elink_link_settings_status, 12471 /*.link_reset = */(link_reset_t)elink_int_link_reset, 12472 /*.config_loopback = */(config_loopback_t)elink_set_xgxs_loopback, 12473 /*.format_fw_ver= */(format_fw_ver_t)NULL, 12474 /*.hw_reset = */(hw_reset_t)NULL, 12475 /*.set_link_led = */(set_link_led_t)NULL, 12476 /*.phy_specific_func = */(phy_specific_func_t)elink_xgxs_specific_func 12477 #endif 12478 }; 12479 #endif 12480 #ifndef EXCLUDE_WARPCORE 12481 static const struct elink_phy phy_warpcore = { 12482 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 12483 /*.addr = */0xff, 12484 /*.def_md_devad = */0, 12485 /*.flags = */ELINK_FLAGS_TX_ERROR_CHECK, 12486 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12487 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12488 /*.mdio_ctrl = */0, 12489 /*.supported = */(ELINK_SUPPORTED_10baseT_Half | 12490 ELINK_SUPPORTED_10baseT_Full | 12491 ELINK_SUPPORTED_100baseT_Half | 12492 ELINK_SUPPORTED_100baseT_Full | 12493 ELINK_SUPPORTED_1000baseT_Full | 12494 ELINK_SUPPORTED_10000baseT_Full | 12495 ELINK_SUPPORTED_20000baseKR2_Full | 12496 ELINK_SUPPORTED_20000baseMLD2_Full | 12497 ELINK_SUPPORTED_FIBRE | 12498 ELINK_SUPPORTED_Autoneg | 12499 ELINK_SUPPORTED_Pause | 12500 ELINK_SUPPORTED_Asym_Pause), 12501 /*.media_type = */ELINK_ETH_PHY_UNSPECIFIED, 12502 /*.ver_addr = */0, 12503 /*.req_flow_ctrl = */0, 12504 /*.req_line_speed = */0, 12505 /*.speed_cap_mask = */0, 12506 /* req_duplex = */0, 12507 /* rsrv = */0, 12508 #ifndef EXCLUDE_NON_COMMON_INIT 12509 /*.config_init = */(config_init_t)elink_warpcore_config_init, 12510 /*.read_status = */(read_status_t)elink_warpcore_read_status, 12511 /*.link_reset = */(link_reset_t)elink_warpcore_link_reset, 12512 /*.config_loopback = */(config_loopback_t)elink_set_warpcore_loopback, 12513 /*.format_fw_ver= */(format_fw_ver_t)NULL, 12514 /*.hw_reset = */(hw_reset_t)elink_warpcore_hw_reset, 12515 /*.set_link_led = */(set_link_led_t)NULL, 12516 /*.phy_specific_func = */(phy_specific_func_t)NULL 12517 #endif 12518 }; 12519 12520 #endif /* #ifndef EXCLUDE_WARPCORE */ 12521 12522 #ifndef ELINK_EMUL_ONLY 12523 #ifndef EXCLUDE_SFX7101 12524 static const struct elink_phy phy_7101 = { 12525 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, 12526 /*.addr = */0xff, 12527 /*.def_md_devad = */0, 12528 /*.flags = */ELINK_FLAGS_FAN_FAILURE_DET_REQ, 12529 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12530 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12531 /*.mdio_ctrl = */0, 12532 /*.supported = */(ELINK_SUPPORTED_10000baseT_Full | 12533 ELINK_SUPPORTED_TP | 12534 ELINK_SUPPORTED_Autoneg | 12535 ELINK_SUPPORTED_Pause | 12536 ELINK_SUPPORTED_Asym_Pause), 12537 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12538 /*.ver_addr = */0, 12539 /*.req_flow_ctrl = */0, 12540 /*.req_line_speed = */0, 12541 /*.speed_cap_mask = */0, 12542 /*.req_duplex = */0, 12543 /*.rsrv = */0, 12544 /*.config_init = */(config_init_t)elink_7101_config_init, 12545 /*.read_status = */(read_status_t)elink_7101_read_status, 12546 /*.link_reset = */(link_reset_t)elink_common_ext_link_reset, 12547 /*.config_loopback = */(config_loopback_t)elink_7101_config_loopback, 12548 /*.format_fw_ver= */(format_fw_ver_t)elink_7101_format_ver, 12549 /*.hw_reset = */(hw_reset_t)elink_7101_hw_reset, 12550 /*.set_link_led = */(set_link_led_t)elink_7101_set_link_led, 12551 /*.phy_specific_func = */(phy_specific_func_t)NULL 12552 }; 12553 #endif /* EXCLUDE_SFX7101 */ 12554 #ifndef EXCLUDE_BCM8727_BCM8073 12555 static const struct elink_phy phy_8073 = { 12556 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 12557 /*.addr = */0xff, 12558 /*.def_md_devad = */0, 12559 /*.flags = */0, 12560 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12561 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12562 /*.mdio_ctrl = */0, 12563 /*.supported = */(ELINK_SUPPORTED_10000baseT_Full | 12564 ELINK_SUPPORTED_2500baseX_Full | 12565 ELINK_SUPPORTED_1000baseT_Full | 12566 ELINK_SUPPORTED_FIBRE | 12567 ELINK_SUPPORTED_Autoneg | 12568 ELINK_SUPPORTED_Pause | 12569 ELINK_SUPPORTED_Asym_Pause), 12570 /*.media_type = */ELINK_ETH_PHY_KR, 12571 /*.ver_addr = */0, 12572 /*.req_flow_ctrl = */0, 12573 /*.req_line_speed = */0, 12574 /*.speed_cap_mask = */0, 12575 /*.req_duplex = */0, 12576 /*.rsrv = */0, 12577 #ifndef EXCLUDE_NON_COMMON_INIT 12578 /*.config_init = */(config_init_t)elink_8073_config_init, 12579 /*.read_status = */(read_status_t)elink_8073_read_status, 12580 /*.link_reset = */(link_reset_t)elink_8073_link_reset, 12581 /*.config_loopback = */(config_loopback_t)NULL, 12582 /*.format_fw_ver= */(format_fw_ver_t)elink_format_ver, 12583 /*.hw_reset = */(hw_reset_t)NULL, 12584 /*.set_link_led = */(set_link_led_t)NULL, 12585 /*.phy_specific_func = */(phy_specific_func_t)elink_8073_specific_func 12586 #endif 12587 }; 12588 #endif 12589 #ifndef EXCLUDE_BCM8705 12590 static const struct elink_phy phy_8705 = { 12591 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, 12592 /*.addr = */0xff, 12593 /*.def_md_devad = */0, 12594 /*.flags = */ELINK_FLAGS_INIT_XGXS_FIRST, 12595 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12596 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12597 /*.mdio_ctrl = */0, 12598 /*.supported = */(ELINK_SUPPORTED_10000baseT_Full | 12599 ELINK_SUPPORTED_FIBRE | 12600 ELINK_SUPPORTED_Pause | 12601 ELINK_SUPPORTED_Asym_Pause), 12602 /*.media_type = */ELINK_ETH_PHY_XFP_FIBER, 12603 /*.ver_addr = */0, 12604 /*.req_flow_ctrl = */0, 12605 /*.req_line_speed = */0, 12606 /*.speed_cap_mask = */0, 12607 /*.req_duplex = */0, 12608 /*.rsrv = */0, 12609 /*.config_init = */(config_init_t)elink_8705_config_init, 12610 /*.read_status = */(read_status_t)elink_8705_read_status, 12611 /*.link_reset = */(link_reset_t)elink_common_ext_link_reset, 12612 /*.config_loopback = */(config_loopback_t)NULL, 12613 /*.format_fw_ver= */(format_fw_ver_t)elink_null_format_ver, 12614 /*.hw_reset = */(hw_reset_t)NULL, 12615 /*.set_link_led = */(set_link_led_t)NULL, 12616 /*.phy_specific_func = */(phy_specific_func_t)NULL 12617 }; 12618 #endif /* EXCLUDE_BCM8705 */ 12619 #ifndef EXCLUDE_BCM87x6 12620 static const struct elink_phy phy_8706 = { 12621 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, 12622 /*.addr = */0xff, 12623 /*.def_md_devad = */0, 12624 /*.flags = */ELINK_FLAGS_INIT_XGXS_FIRST, 12625 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12626 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12627 /*.mdio_ctrl = */0, 12628 /*.supported = */(ELINK_SUPPORTED_10000baseT_Full | 12629 ELINK_SUPPORTED_1000baseT_Full | 12630 ELINK_SUPPORTED_FIBRE | 12631 ELINK_SUPPORTED_Pause | 12632 ELINK_SUPPORTED_Asym_Pause), 12633 /*.media_type = */ELINK_ETH_PHY_SFPP_10G_FIBER, 12634 /*.ver_addr = */0, 12635 /*.req_flow_ctrl = */0, 12636 /*.req_line_speed = */0, 12637 /*.speed_cap_mask = */0, 12638 /*.req_duplex = */0, 12639 /*.rsrv = */0, 12640 /*.config_init = */(config_init_t)elink_8706_config_init, 12641 /*.read_status = */(read_status_t)elink_8706_read_status, 12642 /*.link_reset = */(link_reset_t)elink_common_ext_link_reset, 12643 /*.config_loopback = */(config_loopback_t)NULL, 12644 /*.format_fw_ver= */(format_fw_ver_t)elink_format_ver, 12645 /*.hw_reset = */(hw_reset_t)NULL, 12646 /*.set_link_led = */(set_link_led_t)NULL, 12647 /*.phy_specific_func = */(phy_specific_func_t)NULL 12648 }; 12649 12650 static const struct elink_phy phy_8726 = { 12651 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, 12652 /*.addr = */0xff, 12653 /*.def_md_devad = */0, 12654 /*.flags = */(ELINK_FLAGS_INIT_XGXS_FIRST | 12655 ELINK_FLAGS_TX_ERROR_CHECK), 12656 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12657 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12658 /*.mdio_ctrl = */0, 12659 /*.supported = */(ELINK_SUPPORTED_10000baseT_Full | 12660 ELINK_SUPPORTED_1000baseT_Full | 12661 ELINK_SUPPORTED_Autoneg | 12662 ELINK_SUPPORTED_FIBRE | 12663 ELINK_SUPPORTED_Pause | 12664 ELINK_SUPPORTED_Asym_Pause), 12665 /*.media_type = */ELINK_ETH_PHY_NOT_PRESENT, 12666 /*.ver_addr = */0, 12667 /*.req_flow_ctrl = */0, 12668 /*.req_line_speed = */0, 12669 /*.speed_cap_mask = */0, 12670 /*.req_duplex = */0, 12671 /*.rsrv = */0, 12672 /*.config_init = */(config_init_t)elink_8726_config_init, 12673 /*.read_status = */(read_status_t)elink_8726_read_status, 12674 /*.link_reset = */(link_reset_t)elink_8726_link_reset, 12675 /*.config_loopback = */(config_loopback_t)elink_8726_config_loopback, 12676 /*.format_fw_ver= */(format_fw_ver_t)elink_format_ver, 12677 /*.hw_reset = */(hw_reset_t)NULL, 12678 /*.set_link_led = */(set_link_led_t)NULL, 12679 /*.phy_specific_func = */(phy_specific_func_t)NULL 12680 }; 12681 #endif /* #ifndef EXCLUDE_BCM87x6 */ 12682 12683 #ifndef EXCLUDE_BCM8727_BCM8073 12684 static const struct elink_phy phy_8727 = { 12685 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, 12686 /*.addr = */0xff, 12687 /*.def_md_devad = */0, 12688 /*.flags = */(ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12689 ELINK_FLAGS_TX_ERROR_CHECK), 12690 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12691 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12692 /*.mdio_ctrl = */0, 12693 /*.supported = */(ELINK_SUPPORTED_10000baseT_Full | 12694 ELINK_SUPPORTED_1000baseT_Full | 12695 ELINK_SUPPORTED_FIBRE | 12696 ELINK_SUPPORTED_Pause | 12697 ELINK_SUPPORTED_Asym_Pause), 12698 /*.media_type = */ELINK_ETH_PHY_NOT_PRESENT, 12699 /*.ver_addr = */0, 12700 /*.req_flow_ctrl = */0, 12701 /*.req_line_speed = */0, 12702 /*.speed_cap_mask = */0, 12703 /*.req_duplex = */0, 12704 /*.rsrv = */0, 12705 #ifndef EXCLUDE_NON_COMMON_INIT 12706 /*.config_init = */(config_init_t)elink_8727_config_init, 12707 /*.read_status = */(read_status_t)elink_8727_read_status, 12708 /*.link_reset = */(link_reset_t)elink_8727_link_reset, 12709 /*.config_loopback = */(config_loopback_t)NULL, 12710 /*.format_fw_ver= */(format_fw_ver_t)elink_format_ver, 12711 /*.hw_reset = */(hw_reset_t)elink_8727_hw_reset, 12712 /*.set_link_led = */(set_link_led_t)elink_8727_set_link_led, 12713 /*.phy_specific_func = */(phy_specific_func_t)elink_8727_specific_func 12714 #endif 12715 }; 12716 #endif 12717 #ifndef EXCLUDE_BCM8481 12718 static const struct elink_phy phy_8481 = { 12719 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, 12720 /*.addr = */0xff, 12721 /*.def_md_devad = */0, 12722 /*.flags = */ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12723 ELINK_FLAGS_REARM_LATCH_SIGNAL, 12724 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12725 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12726 /*.mdio_ctrl = */0, 12727 /*.supported = */(ELINK_SUPPORTED_10baseT_Half | 12728 ELINK_SUPPORTED_10baseT_Full | 12729 ELINK_SUPPORTED_100baseT_Half | 12730 ELINK_SUPPORTED_100baseT_Full | 12731 ELINK_SUPPORTED_1000baseT_Full | 12732 ELINK_SUPPORTED_10000baseT_Full | 12733 ELINK_SUPPORTED_TP | 12734 ELINK_SUPPORTED_Autoneg | 12735 ELINK_SUPPORTED_Pause | 12736 ELINK_SUPPORTED_Asym_Pause), 12737 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12738 /*.ver_addr = */0, 12739 /*.req_flow_ctrl = */0, 12740 /*.req_line_speed = */0, 12741 /*.speed_cap_mask = */0, 12742 /*.req_duplex = */0, 12743 /*.rsrv = */0, 12744 #ifndef EXCLUDE_NON_COMMON_INIT 12745 /*.config_init = */(config_init_t)elink_8481_config_init, 12746 /*.read_status = */(read_status_t)elink_848xx_read_status, 12747 /*.link_reset = */(link_reset_t)elink_8481_link_reset, 12748 /*.config_loopback = */(config_loopback_t)NULL, 12749 /*.format_fw_ver= */(format_fw_ver_t)elink_848xx_format_ver, 12750 /*.hw_reset = */(hw_reset_t)elink_8481_hw_reset, 12751 /*.set_link_led = */(set_link_led_t)elink_848xx_set_link_led, 12752 /*.phy_specific_func = */(phy_specific_func_t)NULL 12753 #endif 12754 }; 12755 12756 static const struct elink_phy phy_84823 = { 12757 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, 12758 /*.addr = */0xff, 12759 /*.def_md_devad = */0, 12760 /*.flags = */(ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12761 ELINK_FLAGS_REARM_LATCH_SIGNAL | 12762 ELINK_FLAGS_TX_ERROR_CHECK), 12763 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12764 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12765 /*.mdio_ctrl = */0, 12766 /*.supported = */(ELINK_SUPPORTED_10baseT_Half | 12767 ELINK_SUPPORTED_10baseT_Full | 12768 ELINK_SUPPORTED_100baseT_Half | 12769 ELINK_SUPPORTED_100baseT_Full | 12770 ELINK_SUPPORTED_1000baseT_Full | 12771 ELINK_SUPPORTED_10000baseT_Full | 12772 ELINK_SUPPORTED_TP | 12773 ELINK_SUPPORTED_Autoneg | 12774 ELINK_SUPPORTED_Pause | 12775 ELINK_SUPPORTED_Asym_Pause), 12776 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12777 /*.ver_addr = */0, 12778 /*.req_flow_ctrl = */0, 12779 /*.req_line_speed = */0, 12780 /*.speed_cap_mask = */0, 12781 /*.req_duplex = */0, 12782 /*.rsrv = */0, 12783 #ifndef EXCLUDE_NON_COMMON_INIT 12784 /*.config_init = */(config_init_t)elink_848x3_config_init, 12785 /*.read_status = */(read_status_t)elink_848xx_read_status, 12786 /*.link_reset = */(link_reset_t)elink_848x3_link_reset, 12787 /*.config_loopback = */(config_loopback_t)NULL, 12788 /*.format_fw_ver= */(format_fw_ver_t)elink_848xx_format_ver, 12789 /*.hw_reset = */(hw_reset_t)NULL, 12790 /*.set_link_led = */(set_link_led_t)elink_848xx_set_link_led, 12791 /*.phy_specific_func = */(phy_specific_func_t)elink_848xx_specific_func 12792 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 12793 }; 12794 #endif /* EXCLUDE_BCM8481 */ 12795 12796 #ifndef EXCLUDE_BCM84833 12797 static const struct elink_phy phy_84833 = { 12798 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, 12799 /*.addr = */0xff, 12800 /*.def_md_devad = */0, 12801 /*.flags = */(ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12802 ELINK_FLAGS_REARM_LATCH_SIGNAL | 12803 ELINK_FLAGS_TX_ERROR_CHECK | 12804 ELINK_FLAGS_TEMPERATURE), 12805 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12806 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12807 /*.mdio_ctrl = */0, 12808 /*.supported = */(ELINK_SUPPORTED_100baseT_Half | 12809 ELINK_SUPPORTED_100baseT_Full | 12810 ELINK_SUPPORTED_1000baseT_Full | 12811 ELINK_SUPPORTED_10000baseT_Full | 12812 ELINK_SUPPORTED_TP | 12813 ELINK_SUPPORTED_Autoneg | 12814 ELINK_SUPPORTED_Pause | 12815 ELINK_SUPPORTED_Asym_Pause), 12816 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12817 /*.ver_addr = */0, 12818 /*.req_flow_ctrl = */0, 12819 /*.req_line_speed = */0, 12820 /*.speed_cap_mask = */0, 12821 /*.req_duplex = */0, 12822 /*.rsrv = */0, 12823 #ifndef EXCLUDE_NON_COMMON_INIT 12824 /*.config_init = */(config_init_t)elink_848x3_config_init, 12825 /*.read_status = */(read_status_t)elink_848xx_read_status, 12826 /*.link_reset = */(link_reset_t)elink_848x3_link_reset, 12827 /*.config_loopback = */(config_loopback_t)NULL, 12828 /*.format_fw_ver= */(format_fw_ver_t)elink_848xx_format_ver, 12829 /*.hw_reset = */(hw_reset_t)elink_84833_hw_reset_phy, 12830 /*.set_link_led = */(set_link_led_t)elink_848xx_set_link_led, 12831 /*.phy_specific_func = */(phy_specific_func_t)elink_848xx_specific_func 12832 #endif 12833 }; 12834 12835 static const struct elink_phy phy_84834 = { 12836 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834, 12837 /*.addr = */0xff, 12838 /*.def_md_devad = */0, 12839 /*.flags = */ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12840 ELINK_FLAGS_REARM_LATCH_SIGNAL, 12841 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12842 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12843 /*.mdio_ctrl = */0, 12844 /*.supported = */(ELINK_SUPPORTED_100baseT_Half | 12845 ELINK_SUPPORTED_100baseT_Full | 12846 ELINK_SUPPORTED_1000baseT_Full | 12847 ELINK_SUPPORTED_10000baseT_Full | 12848 ELINK_SUPPORTED_TP | 12849 ELINK_SUPPORTED_Autoneg | 12850 ELINK_SUPPORTED_Pause | 12851 ELINK_SUPPORTED_Asym_Pause), 12852 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12853 /*.ver_addr = */0, 12854 /*.req_flow_ctrl = */0, 12855 /*.req_line_speed = */0, 12856 /*.speed_cap_mask = */0, 12857 /*.req_duplex = */0, 12858 /*.rsrv = */0, 12859 #ifndef EXCLUDE_NON_COMMON_INIT 12860 /*.config_init = */(config_init_t)elink_848x3_config_init, 12861 /*.read_status = */(read_status_t)elink_848xx_read_status, 12862 /*.link_reset = */(link_reset_t)elink_848x3_link_reset, 12863 /*.config_loopback = */(config_loopback_t)NULL, 12864 /*.format_fw_ver= */(format_fw_ver_t)elink_848xx_format_ver, 12865 /*.hw_reset = */(hw_reset_t)elink_84833_hw_reset_phy, 12866 /*.set_link_led = */(set_link_led_t)elink_848xx_set_link_led, 12867 /*.phy_specific_func = */(phy_specific_func_t)elink_848xx_specific_func 12868 #endif 12869 }; 12870 #endif // #ifndef EXCLUDE_BCM84833 12871 12872 #ifndef EXCLUDE_BCM54618SE 12873 static const struct elink_phy phy_54618se = { 12874 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, 12875 /*.addr = */0xff, 12876 /*.def_md_devad = */0, 12877 /*.flags = */ELINK_FLAGS_INIT_XGXS_FIRST, 12878 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12879 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12880 /*.mdio_ctrl = */0, 12881 /*.supported = */(ELINK_SUPPORTED_10baseT_Half | 12882 ELINK_SUPPORTED_10baseT_Full | 12883 ELINK_SUPPORTED_100baseT_Half | 12884 ELINK_SUPPORTED_100baseT_Full | 12885 ELINK_SUPPORTED_1000baseT_Full | 12886 ELINK_SUPPORTED_TP | 12887 ELINK_SUPPORTED_Autoneg | 12888 ELINK_SUPPORTED_Pause | 12889 ELINK_SUPPORTED_Asym_Pause), 12890 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12891 /*.ver_addr = */0, 12892 /*.req_flow_ctrl = */0, 12893 /*.req_line_speed = */0, 12894 /*.speed_cap_mask = */0, 12895 /* req_duplex = */0, 12896 /* rsrv = */0, 12897 #ifndef EXCLUDE_NON_COMMON_INIT 12898 /*.config_init = */(config_init_t)elink_54618se_config_init, 12899 /*.read_status = */(read_status_t)elink_54618se_read_status, 12900 /*.link_reset = */(link_reset_t)elink_54618se_link_reset, 12901 /*.config_loopback = */(config_loopback_t)elink_54618se_config_loopback, 12902 /*.format_fw_ver= */(format_fw_ver_t)NULL, 12903 /*.hw_reset = */(hw_reset_t)NULL, 12904 /*.set_link_led = */(set_link_led_t)elink_5461x_set_link_led, 12905 /*.phy_specific_func = */(phy_specific_func_t)elink_54618se_specific_func 12906 #endif 12907 }; 12908 #endif 12909 #endif /* ELINK_EMUL_ONLY */ 12910 /*****************************************************************/ 12911 /* */ 12912 /* Populate the phy according. Main function: elink_populate_phy */ 12913 /* */ 12914 /*****************************************************************/ 12915 12916 #ifndef EXCLUDE_COMMON_INIT 12917 static void elink_populate_preemphasis(struct elink_dev *cb, u32 shmem_base, 12918 struct elink_phy *phy, u8 port, 12919 u8 phy_index) 12920 { 12921 /* Get the 4 lanes xgxs config rx and tx */ 12922 u32 rx = 0, tx = 0, i; 12923 for (i = 0; i < 2; i++) { 12924 /* INT_PHY and ELINK_EXT_PHY1 share the same value location in 12925 * the shmem. When num_phys is greater than 1, than this value 12926 * applies only to ELINK_EXT_PHY1 12927 */ 12928 if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) { 12929 rx = REG_RD(cb, shmem_base + 12930 OFFSETOF(struct shmem_region, 12931 dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); 12932 12933 tx = REG_RD(cb, shmem_base + 12934 OFFSETOF(struct shmem_region, 12935 dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); 12936 } else { 12937 rx = REG_RD(cb, shmem_base + 12938 OFFSETOF(struct shmem_region, 12939 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 12940 12941 tx = REG_RD(cb, shmem_base + 12942 OFFSETOF(struct shmem_region, 12943 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 12944 } 12945 12946 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); 12947 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); 12948 12949 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); 12950 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); 12951 } 12952 } 12953 12954 #ifndef ELINK_EMUL_ONLY 12955 static u32 elink_get_ext_phy_config(struct elink_dev *cb, u32 shmem_base, 12956 u8 phy_index, u8 port) 12957 { 12958 u32 ext_phy_config = 0; 12959 switch (phy_index) { 12960 case ELINK_EXT_PHY1: 12961 ext_phy_config = REG_RD(cb, shmem_base + 12962 OFFSETOF(struct shmem_region, 12963 dev_info.port_hw_config[port].external_phy_config)); 12964 break; 12965 case ELINK_EXT_PHY2: 12966 ext_phy_config = REG_RD(cb, shmem_base + 12967 OFFSETOF(struct shmem_region, 12968 dev_info.port_hw_config[port].external_phy_config2)); 12969 break; 12970 default: 12971 ELINK_DEBUG_P1(cb, "Invalid phy_index %d\n", phy_index); 12972 return ELINK_STATUS_ERROR; 12973 } 12974 12975 return ext_phy_config; 12976 } 12977 #endif /* ELINK_EMUL_ONLY */ 12978 static elink_status_t elink_populate_int_phy(struct elink_dev *cb, u32 shmem_base, u8 port, 12979 struct elink_phy *phy) 12980 { 12981 u32 phy_addr; 12982 u32 chip_id; 12983 u32 switch_cfg = (REG_RD(cb, shmem_base + 12984 OFFSETOF(struct shmem_region, 12985 dev_info.port_feature_config[port].link_config)) & 12986 PORT_FEATURE_CONNECTED_SWITCH_MASK); 12987 chip_id = (REG_RD(cb, MISC_REG_CHIP_NUM) << 16) | 12988 ((REG_RD(cb, MISC_REG_CHIP_REV) & 0xf) << 12); 12989 12990 ELINK_DEBUG_P1(cb, ":chip_id = 0x%x\n", chip_id); 12991 #ifndef EXCLUDE_WARPCORE 12992 if (ELINK_USES_WARPCORE(chip_id)) { 12993 u32 serdes_net_if; 12994 phy_addr = REG_RD(cb, 12995 MISC_REG_WC0_CTRL_PHY_ADDR); 12996 *phy = phy_warpcore; 12997 if (REG_RD(cb, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) 12998 phy->flags |= ELINK_FLAGS_4_PORT_MODE; 12999 else 13000 phy->flags &= ~ELINK_FLAGS_4_PORT_MODE; 13001 /* Check Dual mode */ 13002 serdes_net_if = (REG_RD(cb, shmem_base + 13003 OFFSETOF(struct shmem_region, dev_info. 13004 port_hw_config[port].default_cfg)) & 13005 PORT_HW_CFG_NET_SERDES_IF_MASK); 13006 /* Set the appropriate supported and flags indications per 13007 * interface type of the chip 13008 */ 13009 switch (serdes_net_if) { 13010 case PORT_HW_CFG_NET_SERDES_IF_SGMII: 13011 phy->supported &= (ELINK_SUPPORTED_10baseT_Half | 13012 ELINK_SUPPORTED_10baseT_Full | 13013 ELINK_SUPPORTED_100baseT_Half | 13014 ELINK_SUPPORTED_100baseT_Full | 13015 ELINK_SUPPORTED_1000baseT_Full | 13016 ELINK_SUPPORTED_FIBRE | 13017 ELINK_SUPPORTED_Autoneg | 13018 ELINK_SUPPORTED_Pause | 13019 ELINK_SUPPORTED_Asym_Pause); 13020 phy->media_type = ELINK_ETH_PHY_BASE_T; 13021 break; 13022 case PORT_HW_CFG_NET_SERDES_IF_XFI: 13023 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | 13024 ELINK_SUPPORTED_10000baseT_Full | 13025 ELINK_SUPPORTED_FIBRE | 13026 ELINK_SUPPORTED_Pause | 13027 ELINK_SUPPORTED_Asym_Pause); 13028 phy->media_type = ELINK_ETH_PHY_XFP_FIBER; 13029 break; 13030 case PORT_HW_CFG_NET_SERDES_IF_SFI: 13031 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | 13032 ELINK_SUPPORTED_10000baseT_Full | 13033 ELINK_SUPPORTED_FIBRE | 13034 ELINK_SUPPORTED_Pause | 13035 ELINK_SUPPORTED_Asym_Pause); 13036 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER; 13037 break; 13038 case PORT_HW_CFG_NET_SERDES_IF_KR: 13039 phy->media_type = ELINK_ETH_PHY_KR; 13040 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | 13041 ELINK_SUPPORTED_10000baseT_Full | 13042 ELINK_SUPPORTED_FIBRE | 13043 ELINK_SUPPORTED_Autoneg | 13044 ELINK_SUPPORTED_Pause | 13045 ELINK_SUPPORTED_Asym_Pause); 13046 break; 13047 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 13048 phy->media_type = ELINK_ETH_PHY_KR; 13049 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE; 13050 phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full | 13051 ELINK_SUPPORTED_FIBRE | 13052 ELINK_SUPPORTED_Pause | 13053 ELINK_SUPPORTED_Asym_Pause); 13054 break; 13055 case PORT_HW_CFG_NET_SERDES_IF_KR2: 13056 phy->media_type = ELINK_ETH_PHY_KR; 13057 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE; 13058 phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full | 13059 ELINK_SUPPORTED_10000baseT_Full | 13060 ELINK_SUPPORTED_1000baseT_Full | 13061 ELINK_SUPPORTED_Autoneg | 13062 ELINK_SUPPORTED_FIBRE | 13063 ELINK_SUPPORTED_Pause | 13064 ELINK_SUPPORTED_Asym_Pause); 13065 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK; 13066 break; 13067 default: 13068 ELINK_DEBUG_P1(cb, "Unknown WC interface type 0x%x\n", 13069 serdes_net_if); 13070 break; 13071 } 13072 13073 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC 13074 * was not set as expected. For B0, ECO will be enabled so there 13075 * won't be an issue there 13076 */ 13077 if (CHIP_REV(chip_id) == CHIP_REV_Ax) 13078 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA; 13079 else 13080 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0; 13081 } else 13082 #endif 13083 { 13084 switch (switch_cfg) { 13085 #ifndef EXCLUDE_SERDES 13086 case ELINK_SWITCH_CFG_1G: 13087 phy_addr = REG_RD(cb, 13088 NIG_REG_SERDES0_CTRL_PHY_ADDR + 13089 port * 0x10); 13090 *phy = phy_serdes; 13091 break; 13092 #endif /* #ifndef EXCLUDE_SERDES */ 13093 #ifndef EXCLUDE_XGXS 13094 case ELINK_SWITCH_CFG_10G: 13095 phy_addr = REG_RD(cb, 13096 NIG_REG_XGXS0_CTRL_PHY_ADDR + 13097 port * 0x18); 13098 *phy = phy_xgxs; 13099 break; 13100 #endif /* EXCLUDE_XGXS */ 13101 default: 13102 ELINK_DEBUG_P0(cb, "Invalid switch_cfg\n"); 13103 return ELINK_STATUS_ERROR; 13104 } 13105 } 13106 phy->addr = (u8)phy_addr; 13107 phy->mdio_ctrl = elink_get_emac_base(cb, 13108 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, 13109 port); 13110 if (CHIP_IS_E2(chip_id)) 13111 phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR; 13112 else 13113 phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR; 13114 13115 ELINK_DEBUG_P3(cb, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", 13116 port, phy->addr, phy->mdio_ctrl); 13117 13118 elink_populate_preemphasis(cb, shmem_base, phy, port, ELINK_INT_PHY); 13119 return ELINK_STATUS_OK; 13120 } 13121 13122 #ifndef ELINK_EMUL_ONLY 13123 static elink_status_t elink_populate_ext_phy(struct elink_dev *cb, 13124 u8 phy_index, 13125 u32 shmem_base, 13126 u32 shmem2_base, 13127 u8 port, 13128 struct elink_phy *phy) 13129 { 13130 u32 ext_phy_config, phy_type, config2; 13131 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; 13132 ext_phy_config = elink_get_ext_phy_config(cb, shmem_base, 13133 phy_index, port); 13134 phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config); 13135 /* Select the phy type */ 13136 switch (phy_type) { 13137 #ifndef EXCLUDE_BCM8727_BCM8073 13138 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 13139 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; 13140 *phy = phy_8073; 13141 break; 13142 #endif 13143 #ifndef EXCLUDE_BCM8705 13144 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 13145 *phy = phy_8705; 13146 break; 13147 #endif 13148 #ifndef EXCLUDE_BCM87x6 13149 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 13150 *phy = phy_8706; 13151 break; 13152 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 13153 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 13154 *phy = phy_8726; 13155 break; 13156 #endif /* EXCLUDE_BCM87x6 */ 13157 #ifndef EXCLUDE_BCM8727_BCM8073 13158 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 13159 /* BCM8727_NOC => BCM8727 no over current */ 13160 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 13161 *phy = phy_8727; 13162 phy->flags |= ELINK_FLAGS_NOC; 13163 break; 13164 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 13165 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 13166 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 13167 *phy = phy_8727; 13168 break; 13169 #endif 13170 #ifndef EXCLUDE_BCM8481 13171 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 13172 *phy = phy_8481; 13173 break; 13174 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 13175 *phy = phy_84823; 13176 break; 13177 #endif 13178 #ifndef EXCLUDE_BCM84833 13179 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 13180 *phy = phy_84833; 13181 break; 13182 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 13183 *phy = phy_84834; 13184 break; 13185 #endif 13186 #ifndef EXCLUDE_BCM54618SE 13187 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616: 13188 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: 13189 *phy = phy_54618se; 13190 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 13191 phy->flags |= ELINK_FLAGS_EEE; 13192 break; 13193 #endif 13194 #ifndef EXCLUDE_SFX7101 13195 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 13196 *phy = phy_7101; 13197 break; 13198 #endif 13199 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 13200 *phy = phy_null; 13201 return ELINK_STATUS_ERROR; 13202 default: 13203 *phy = phy_null; 13204 /* In case external PHY wasn't found */ 13205 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 13206 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 13207 return ELINK_STATUS_ERROR; 13208 return ELINK_STATUS_OK; 13209 } 13210 13211 phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config); 13212 elink_populate_preemphasis(cb, shmem_base, phy, port, phy_index); 13213 13214 /* The shmem address of the phy version is located on different 13215 * structures. In case this structure is too old, do not set 13216 * the address 13217 */ 13218 config2 = REG_RD(cb, shmem_base + OFFSETOF(struct shmem_region, 13219 dev_info.shared_hw_config.config2)); 13220 if (phy_index == ELINK_EXT_PHY1) { 13221 phy->ver_addr = shmem_base + OFFSETOF(struct shmem_region, 13222 port_mb[port].ext_phy_fw_version); 13223 13224 /* Check specific mdc mdio settings */ 13225 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) 13226 mdc_mdio_access = config2 & 13227 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; 13228 } else { 13229 u32 size = REG_RD(cb, shmem2_base); 13230 13231 if (size > 13232 OFFSETOF(struct shmem2_region, ext_phy_fw_version2)) { 13233 phy->ver_addr = shmem2_base + 13234 OFFSETOF(struct shmem2_region, 13235 ext_phy_fw_version2[port]); 13236 } 13237 /* Check specific mdc mdio settings */ 13238 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) 13239 mdc_mdio_access = (config2 & 13240 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> 13241 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - 13242 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); 13243 } 13244 phy->mdio_ctrl = elink_get_emac_base(cb, mdc_mdio_access, port); 13245 13246 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 13247 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) && 13248 (phy->ver_addr)) { 13249 /* Remove 100Mb link supported for BCM84833/4 when phy fw 13250 * version lower than or equal to 1.39 13251 */ 13252 u32 raw_ver = REG_RD(cb, phy->ver_addr); 13253 if (((raw_ver & 0x7F) <= 39) && 13254 (((raw_ver & 0xF80) >> 7) <= 1)) 13255 phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half | 13256 ELINK_SUPPORTED_100baseT_Full); 13257 } 13258 13259 ELINK_DEBUG_P3(cb, "phy_type 0x%x port %d found in index %d\n", 13260 phy_type, port, phy_index); 13261 ELINK_DEBUG_P2(cb, " addr=0x%x, mdio_ctl=0x%x\n", 13262 phy->addr, phy->mdio_ctrl); 13263 return ELINK_STATUS_OK; 13264 } 13265 #endif /* ELINK_EMUL_ONLY */ 13266 13267 static elink_status_t elink_populate_phy(struct elink_dev *cb, u8 phy_index, u32 shmem_base, 13268 u32 shmem2_base, u8 port, struct elink_phy *phy) 13269 { 13270 elink_status_t status = ELINK_STATUS_OK; 13271 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; 13272 if (phy_index == ELINK_INT_PHY) 13273 return elink_populate_int_phy(cb, shmem_base, port, phy); 13274 #ifndef ELINK_EMUL_ONLY 13275 status = elink_populate_ext_phy(cb, phy_index, shmem_base, shmem2_base, 13276 port, phy); 13277 #endif /* ELINK_EMUL_ONLY */ 13278 return status; 13279 } 13280 13281 static void elink_phy_def_cfg(struct elink_params *params, 13282 struct elink_phy *phy, 13283 u8 phy_index) 13284 { 13285 struct elink_dev *cb = params->cb; 13286 u32 link_config; 13287 /* Populate the default phy configuration for MF mode */ 13288 if (phy_index == ELINK_EXT_PHY2) { 13289 link_config = REG_RD(cb, params->shmem_base + 13290 OFFSETOF(struct shmem_region, dev_info. 13291 port_feature_config[params->port].link_config2)); 13292 phy->speed_cap_mask = REG_RD(cb, params->shmem_base + 13293 OFFSETOF(struct shmem_region, 13294 dev_info. 13295 port_hw_config[params->port].speed_capability_mask2)); 13296 } else { 13297 link_config = REG_RD(cb, params->shmem_base + 13298 OFFSETOF(struct shmem_region, dev_info. 13299 port_feature_config[params->port].link_config)); 13300 phy->speed_cap_mask = REG_RD(cb, params->shmem_base + 13301 OFFSETOF(struct shmem_region, 13302 dev_info. 13303 port_hw_config[params->port].speed_capability_mask)); 13304 } 13305 ELINK_DEBUG_P3(cb, 13306 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", 13307 phy_index, link_config, phy->speed_cap_mask); 13308 13309 phy->req_duplex = DUPLEX_FULL; 13310 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 13311 case PORT_FEATURE_LINK_SPEED_10M_HALF: 13312 phy->req_duplex = DUPLEX_HALF; 13313 /* FALLTHROUGH */ 13314 case PORT_FEATURE_LINK_SPEED_10M_FULL: 13315 phy->req_line_speed = ELINK_SPEED_10; 13316 break; 13317 case PORT_FEATURE_LINK_SPEED_100M_HALF: 13318 phy->req_duplex = DUPLEX_HALF; 13319 /* FALLTHROUGH */ 13320 case PORT_FEATURE_LINK_SPEED_100M_FULL: 13321 phy->req_line_speed = ELINK_SPEED_100; 13322 break; 13323 case PORT_FEATURE_LINK_SPEED_1G: 13324 phy->req_line_speed = ELINK_SPEED_1000; 13325 break; 13326 case PORT_FEATURE_LINK_SPEED_2_5G: 13327 phy->req_line_speed = ELINK_SPEED_2500; 13328 break; 13329 case PORT_FEATURE_LINK_SPEED_10G_CX4: 13330 phy->req_line_speed = ELINK_SPEED_10000; 13331 break; 13332 default: 13333 phy->req_line_speed = ELINK_SPEED_AUTO_NEG; 13334 break; 13335 } 13336 13337 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { 13338 case PORT_FEATURE_FLOW_CONTROL_AUTO: 13339 phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO; 13340 break; 13341 case PORT_FEATURE_FLOW_CONTROL_TX: 13342 phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX; 13343 break; 13344 case PORT_FEATURE_FLOW_CONTROL_RX: 13345 phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX; 13346 break; 13347 case PORT_FEATURE_FLOW_CONTROL_BOTH: 13348 phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH; 13349 break; 13350 default: 13351 phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE; 13352 break; 13353 } 13354 } 13355 #endif /* EXCLUDE_COMMON_INIT */ 13356 13357 u32 elink_phy_selection(struct elink_params *params) 13358 { 13359 u32 phy_config_swapped, prio_cfg; 13360 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; 13361 13362 phy_config_swapped = params->multi_phy_config & 13363 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 13364 13365 prio_cfg = params->multi_phy_config & 13366 PORT_HW_CFG_PHY_SELECTION_MASK; 13367 13368 if (phy_config_swapped) { 13369 switch (prio_cfg) { 13370 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 13371 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; 13372 break; 13373 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 13374 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; 13375 break; 13376 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 13377 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 13378 break; 13379 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 13380 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 13381 break; 13382 } 13383 } else 13384 return_cfg = prio_cfg; 13385 13386 return return_cfg; 13387 } 13388 13389 #ifndef EXCLUDE_COMMON_INIT 13390 elink_status_t elink_phy_probe(struct elink_params *params) 13391 { 13392 u8 phy_index, actual_phy_idx; 13393 u32 phy_config_swapped, sync_offset, media_types; 13394 struct elink_dev *cb = params->cb; 13395 struct elink_phy *phy; 13396 params->num_phys = 0; 13397 ELINK_DEBUG_P0(cb, "Begin phy probe\n"); 13398 #ifdef ELINK_INCLUDE_EMUL 13399 if (CHIP_REV_IS_EMUL(params->chip_id)) 13400 return ELINK_STATUS_OK; 13401 #endif 13402 phy_config_swapped = params->multi_phy_config & 13403 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 13404 13405 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; 13406 phy_index++) { 13407 actual_phy_idx = phy_index; 13408 if (phy_config_swapped) { 13409 if (phy_index == ELINK_EXT_PHY1) 13410 actual_phy_idx = ELINK_EXT_PHY2; 13411 else if (phy_index == ELINK_EXT_PHY2) 13412 actual_phy_idx = ELINK_EXT_PHY1; 13413 } 13414 ELINK_DEBUG_P3(cb, "phy_config_swapped %x, phy_index %x," 13415 " actual_phy_idx %x\n", phy_config_swapped, 13416 phy_index, actual_phy_idx); 13417 phy = ¶ms->phy[actual_phy_idx]; 13418 if (elink_populate_phy(cb, phy_index, params->shmem_base, 13419 params->shmem2_base, params->port, 13420 phy) != ELINK_STATUS_OK) { 13421 params->num_phys = 0; 13422 ELINK_DEBUG_P1(cb, "phy probe failed in phy index %d\n", 13423 phy_index); 13424 for (phy_index = ELINK_INT_PHY; 13425 phy_index < ELINK_MAX_PHYS; 13426 phy_index++) 13427 *phy = phy_null; 13428 return ELINK_STATUS_ERROR; 13429 } 13430 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) 13431 break; 13432 13433 if (params->feature_config_flags & 13434 ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) 13435 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK; 13436 13437 if (!(params->feature_config_flags & 13438 ELINK_FEATURE_CONFIG_MT_SUPPORT)) 13439 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G; 13440 13441 sync_offset = params->shmem_base + 13442 OFFSETOF(struct shmem_region, 13443 dev_info.port_hw_config[params->port].media_type); 13444 media_types = REG_RD(cb, sync_offset); 13445 13446 /* Update media type for non-PMF sync only for the first time 13447 * In case the media type changes afterwards, it will be updated 13448 * using the update_status function 13449 */ 13450 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 13451 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 13452 actual_phy_idx))) == 0) { 13453 media_types |= ((phy->media_type & 13454 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 13455 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 13456 actual_phy_idx)); 13457 } 13458 REG_WR(cb, sync_offset, media_types); 13459 13460 elink_phy_def_cfg(params, phy, phy_index); 13461 params->num_phys++; 13462 } 13463 13464 ELINK_DEBUG_P1(cb, "End phy probe. #phys found %x\n", params->num_phys); 13465 return ELINK_STATUS_OK; 13466 } 13467 #endif /* EXCLUDE_COMMON_INIT */ 13468 13469 #ifdef ELINK_AUX_POWER 13470 u8 elink_phy_is_temperature_support(struct elink_params *params) 13471 { 13472 u8 phy_index; 13473 struct elink_phy *phy; 13474 13475 /* This function check that at least one of the phy's supports 13476 * temperature read. 13477 */ 13478 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; 13479 phy_index++) { 13480 phy = ¶ms->phy[phy_index]; 13481 if (phy->flags & ELINK_FLAGS_TEMPERATURE) 13482 return 1; 13483 } 13484 return 0; 13485 } 13486 #endif /* ELINK_AUX_POWER */ 13487 #ifdef ELINK_INCLUDE_EMUL 13488 static elink_status_t elink_init_e3_emul_mac(struct elink_params *params, 13489 struct elink_vars *vars) 13490 { 13491 struct elink_dev *cb = params->cb; 13492 vars->line_speed = params->req_line_speed[0]; 13493 /* In case link speed is auto, set speed the highest as possible */ 13494 if (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) { 13495 if (params->feature_config_flags & 13496 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) 13497 vars->line_speed = ELINK_SPEED_2500; 13498 else if (elink_is_4_port_mode(cb)) 13499 vars->line_speed = ELINK_SPEED_10000; 13500 else 13501 vars->line_speed = ELINK_SPEED_20000; 13502 } 13503 if (vars->line_speed < ELINK_SPEED_10000) { 13504 if ((params->feature_config_flags & 13505 ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC)) { 13506 ELINK_DEBUG_P1(cb, "Invalid line speed %d while UMAC is" 13507 " disabled!\n", params->req_line_speed[0]); 13508 return ELINK_STATUS_ERROR; 13509 } 13510 switch (vars->line_speed) { 13511 case ELINK_SPEED_10: 13512 vars->link_status = ELINK_LINK_10TFD; 13513 break; 13514 case ELINK_SPEED_100: 13515 vars->link_status = ELINK_LINK_100TXFD; 13516 break; 13517 case ELINK_SPEED_1000: 13518 vars->link_status = ELINK_LINK_1000TFD; 13519 break; 13520 case ELINK_SPEED_2500: 13521 vars->link_status = ELINK_LINK_2500TFD; 13522 break; 13523 default: 13524 ELINK_DEBUG_P1(cb, "Invalid line speed %d for UMAC\n", 13525 vars->line_speed); 13526 return ELINK_STATUS_ERROR; 13527 } 13528 vars->link_status |= LINK_STATUS_LINK_UP; 13529 13530 if (params->loopback_mode == ELINK_LOOPBACK_UMAC) 13531 elink_umac_enable(params, vars, 1); 13532 else 13533 elink_umac_enable(params, vars, 0); 13534 } else { 13535 /* Link speed >= 10000 requires XMAC enabled */ 13536 if (params->feature_config_flags & 13537 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) { 13538 ELINK_DEBUG_P1(cb, "Invalid line speed %d while XMAC is" 13539 " disabled!\n", params->req_line_speed[0]); 13540 return ELINK_STATUS_ERROR; 13541 } 13542 /* Check link speed */ 13543 switch (vars->line_speed) { 13544 case ELINK_SPEED_10000: 13545 vars->link_status = ELINK_LINK_10GTFD; 13546 break; 13547 case ELINK_SPEED_20000: 13548 vars->link_status = ELINK_LINK_20GTFD; 13549 break; 13550 default: 13551 ELINK_DEBUG_P1(cb, "Invalid line speed %d for XMAC\n", 13552 vars->line_speed); 13553 return ELINK_STATUS_ERROR; 13554 } 13555 vars->link_status |= LINK_STATUS_LINK_UP; 13556 if (params->loopback_mode == ELINK_LOOPBACK_XMAC) 13557 elink_xmac_enable(params, vars, 1); 13558 else 13559 elink_xmac_enable(params, vars, 0); 13560 } 13561 return ELINK_STATUS_OK; 13562 } 13563 13564 static elink_status_t elink_init_emul(struct elink_params *params, 13565 struct elink_vars *vars) 13566 { 13567 struct elink_dev *cb = params->cb; 13568 if (CHIP_IS_E3(params->chip_id)) { 13569 if (elink_init_e3_emul_mac(params, vars) != 13570 ELINK_STATUS_OK) 13571 return ELINK_STATUS_ERROR; 13572 } else { 13573 if (params->feature_config_flags & 13574 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC) { 13575 vars->line_speed = ELINK_SPEED_1000; 13576 vars->link_status = (LINK_STATUS_LINK_UP | 13577 ELINK_LINK_1000XFD); 13578 if (params->loopback_mode == 13579 ELINK_LOOPBACK_EMAC) 13580 elink_emac_enable(params, vars, 1); 13581 else 13582 elink_emac_enable(params, vars, 0); 13583 } else { 13584 vars->line_speed = ELINK_SPEED_10000; 13585 vars->link_status = (LINK_STATUS_LINK_UP | 13586 ELINK_LINK_10GTFD); 13587 if (params->loopback_mode == 13588 ELINK_LOOPBACK_BMAC) 13589 elink_bmac_enable(params, vars, 1, 1); 13590 else 13591 elink_bmac_enable(params, vars, 0, 1); 13592 } 13593 } 13594 vars->link_up = 1; 13595 vars->duplex = DUPLEX_FULL; 13596 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13597 13598 #ifndef ELINK_AUX_POWER 13599 if (CHIP_IS_E1X(params->chip_id)) 13600 elink_pbf_update(params, vars->flow_ctrl, 13601 vars->line_speed); 13602 #endif /* ELINK_AUX_POWER */ 13603 /* Disable drain */ 13604 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13605 13606 /* update shared memory */ 13607 elink_update_mng(params, vars->link_status); 13608 return ELINK_STATUS_OK; 13609 } 13610 #endif // ELINK_INCLUDE_EMUL 13611 #ifdef ELINK_INCLUDE_FPGA 13612 static elink_status_t elink_init_fpga(struct elink_params *params, 13613 struct elink_vars *vars) 13614 { 13615 /* Enable on E1.5 FPGA */ 13616 struct elink_dev *cb = params->cb; 13617 vars->duplex = DUPLEX_FULL; 13618 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13619 if (!(CHIP_IS_E1(params->chip_id))) { 13620 vars->flow_ctrl = (ELINK_FLOW_CTRL_TX | 13621 ELINK_FLOW_CTRL_RX); 13622 vars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED | 13623 LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 13624 } 13625 if (CHIP_IS_E3(params->chip_id)) { 13626 vars->line_speed = params->req_line_speed[0]; 13627 switch (vars->line_speed) { 13628 case ELINK_SPEED_AUTO_NEG: 13629 vars->line_speed = ELINK_SPEED_2500; 13630 case ELINK_SPEED_2500: 13631 vars->link_status = ELINK_LINK_2500TFD; 13632 break; 13633 case ELINK_SPEED_1000: 13634 vars->link_status = ELINK_LINK_1000XFD; 13635 break; 13636 case ELINK_SPEED_100: 13637 vars->link_status = ELINK_LINK_100TXFD; 13638 break; 13639 case ELINK_SPEED_10: 13640 vars->link_status = ELINK_LINK_10TFD; 13641 break; 13642 default: 13643 ELINK_DEBUG_P1(cb, "Invalid link speed %d\n", 13644 params->req_line_speed[0]); 13645 return ELINK_STATUS_ERROR; 13646 } 13647 vars->link_status |= LINK_STATUS_LINK_UP; 13648 if (params->loopback_mode == ELINK_LOOPBACK_UMAC) 13649 elink_umac_enable(params, vars, 1); 13650 else 13651 elink_umac_enable(params, vars, 0); 13652 } else { 13653 vars->line_speed = ELINK_SPEED_10000; 13654 vars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD); 13655 if (params->loopback_mode == ELINK_LOOPBACK_EMAC) 13656 elink_emac_enable(params, vars, 1); 13657 else 13658 elink_emac_enable(params, vars, 0); 13659 } 13660 vars->link_up = 1; 13661 13662 #ifndef ELINK_AUX_POWER 13663 if (CHIP_IS_E1X(params->chip_id)) 13664 elink_pbf_update(params, vars->flow_ctrl, 13665 vars->line_speed); 13666 #endif /* ELINK_AUX_POWER */ 13667 /* Disable drain */ 13668 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13669 13670 /* Update shared memory */ 13671 elink_update_mng(params, vars->link_status); 13672 return ELINK_STATUS_OK; 13673 } 13674 #endif // #ifdef ELINK_INCLUDE_FPGA 13675 #ifdef ELINK_INCLUDE_LOOPBACK 13676 static void elink_init_bmac_loopback(struct elink_params *params, 13677 struct elink_vars *vars) 13678 { 13679 struct elink_dev *cb = params->cb; 13680 vars->link_up = 1; 13681 vars->line_speed = ELINK_SPEED_10000; 13682 vars->duplex = DUPLEX_FULL; 13683 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13684 vars->mac_type = ELINK_MAC_TYPE_BMAC; 13685 13686 vars->phy_flags = PHY_XGXS_FLAG; 13687 13688 elink_xgxs_deassert(params); 13689 13690 /* Set bmac loopback */ 13691 elink_bmac_enable(params, vars, 1, 1); 13692 13693 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13694 } 13695 13696 static void elink_init_emac_loopback(struct elink_params *params, 13697 struct elink_vars *vars) 13698 { 13699 struct elink_dev *cb = params->cb; 13700 vars->link_up = 1; 13701 vars->line_speed = ELINK_SPEED_1000; 13702 vars->duplex = DUPLEX_FULL; 13703 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13704 vars->mac_type = ELINK_MAC_TYPE_EMAC; 13705 13706 vars->phy_flags = PHY_XGXS_FLAG; 13707 13708 elink_xgxs_deassert(params); 13709 /* Set bmac loopback */ 13710 elink_emac_enable(params, vars, 1); 13711 elink_emac_program(params, vars); 13712 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13713 } 13714 13715 static void elink_init_xmac_loopback(struct elink_params *params, 13716 struct elink_vars *vars) 13717 { 13718 struct elink_dev *cb = params->cb; 13719 vars->link_up = 1; 13720 if (!params->req_line_speed[0]) 13721 vars->line_speed = ELINK_SPEED_10000; 13722 else 13723 vars->line_speed = params->req_line_speed[0]; 13724 vars->duplex = DUPLEX_FULL; 13725 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13726 vars->mac_type = ELINK_MAC_TYPE_XMAC; 13727 vars->phy_flags = PHY_XGXS_FLAG; 13728 /* Set WC to loopback mode since link is required to provide clock 13729 * to the XMAC in 20G mode 13730 */ 13731 elink_set_aer_mmd(params, ¶ms->phy[0]); 13732 elink_warpcore_reset_lane(cb, ¶ms->phy[0], 0); 13733 params->phy[ELINK_INT_PHY].config_loopback( 13734 ¶ms->phy[ELINK_INT_PHY], 13735 params); 13736 13737 elink_xmac_enable(params, vars, 1); 13738 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13739 } 13740 13741 static void elink_init_umac_loopback(struct elink_params *params, 13742 struct elink_vars *vars) 13743 { 13744 struct elink_dev *cb = params->cb; 13745 vars->link_up = 1; 13746 vars->line_speed = ELINK_SPEED_1000; 13747 vars->duplex = DUPLEX_FULL; 13748 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13749 vars->mac_type = ELINK_MAC_TYPE_UMAC; 13750 vars->phy_flags = PHY_XGXS_FLAG; 13751 elink_umac_enable(params, vars, 1); 13752 13753 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13754 } 13755 13756 static void elink_init_xgxs_loopback(struct elink_params *params, 13757 struct elink_vars *vars) 13758 { 13759 struct elink_dev *cb = params->cb; 13760 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY]; 13761 vars->link_up = 1; 13762 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13763 vars->duplex = DUPLEX_FULL; 13764 if (params->req_line_speed[0] == ELINK_SPEED_1000) 13765 vars->line_speed = ELINK_SPEED_1000; 13766 else if ((params->req_line_speed[0] == ELINK_SPEED_20000) || 13767 (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) 13768 vars->line_speed = ELINK_SPEED_20000; 13769 else 13770 vars->line_speed = ELINK_SPEED_10000; 13771 13772 if (!ELINK_USES_WARPCORE(params->chip_id)) 13773 elink_xgxs_deassert(params); 13774 elink_link_initialize(params, vars); 13775 13776 if (params->req_line_speed[0] == ELINK_SPEED_1000) { 13777 if (ELINK_USES_WARPCORE(params->chip_id)) 13778 elink_umac_enable(params, vars, 0); 13779 else { 13780 elink_emac_program(params, vars); 13781 elink_emac_enable(params, vars, 0); 13782 } 13783 } else { 13784 if (ELINK_USES_WARPCORE(params->chip_id)) 13785 elink_xmac_enable(params, vars, 0); 13786 else 13787 elink_bmac_enable(params, vars, 0, 1); 13788 } 13789 13790 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) { 13791 /* Set 10G XGXS loopback */ 13792 int_phy->config_loopback(int_phy, params); 13793 } else { 13794 /* Set external phy loopback */ 13795 u8 phy_index; 13796 for (phy_index = ELINK_EXT_PHY1; 13797 phy_index < params->num_phys; phy_index++) 13798 if (params->phy[phy_index].config_loopback) 13799 params->phy[phy_index].config_loopback( 13800 ¶ms->phy[phy_index], 13801 params); 13802 } 13803 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13804 13805 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed); 13806 } 13807 #endif // #ifdef ELINK_INCLUDE_LOOPBACK 13808 13809 #ifdef ELINK_ENHANCEMENTS 13810 void elink_set_rx_filter(struct elink_params *params, u8 en) 13811 { 13812 struct elink_dev *cb = params->cb; 13813 u8 val = en * 0x1F; 13814 13815 /* Open / close the gate between the NIG and the BRB */ 13816 if (!CHIP_IS_E1X(params->chip_id)) 13817 val |= en * 0x20; 13818 REG_WR(cb, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); 13819 13820 if (!CHIP_IS_E1(params->chip_id)) { 13821 REG_WR(cb, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, 13822 en*0x3); 13823 } 13824 13825 REG_WR(cb, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : 13826 NIG_REG_LLH0_BRB1_NOT_MCP), en); 13827 } 13828 #endif /* #ifdef ELINK_ENHANCEMENTS */ 13829 #ifndef EXCLUDE_NON_COMMON_INIT 13830 static elink_status_t elink_avoid_link_flap(struct elink_params *params, 13831 struct elink_vars *vars) 13832 { 13833 u32 phy_idx; 13834 u32 dont_clear_stat, lfa_sts; 13835 struct elink_dev *cb = params->cb; 13836 13837 elink_set_mdio_emac_per_phy(cb, params); 13838 /* Sync the link parameters */ 13839 elink_link_status_update(params, vars); 13840 13841 /* 13842 * The module verification was already done by previous link owner, 13843 * so this call is meant only to get warning message 13844 */ 13845 13846 for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) { 13847 struct elink_phy *phy = ¶ms->phy[phy_idx]; 13848 if (phy->phy_specific_func) { 13849 ELINK_DEBUG_P0(cb, "Calling PHY specific func\n"); 13850 phy->phy_specific_func(phy, params, ELINK_PHY_INIT); 13851 } 13852 #ifdef ELINK_ENHANCEMENTS 13853 if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) || 13854 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) || 13855 (phy->media_type == ELINK_ETH_PHY_DA_TWINAX)) 13856 elink_verify_sfp_module(phy, params); 13857 #endif 13858 } 13859 lfa_sts = REG_RD(cb, params->lfa_base + 13860 OFFSETOF(struct shmem_lfa, 13861 lfa_sts)); 13862 13863 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT; 13864 13865 /* Re-enable the NIG/MAC */ 13866 if (CHIP_IS_E3(params->chip_id)) { 13867 #ifndef EXCLUDE_WARPCORE 13868 if (!dont_clear_stat) { 13869 REG_WR(cb, GRCBASE_MISC + 13870 MISC_REGISTERS_RESET_REG_2_CLEAR, 13871 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 13872 params->port)); 13873 REG_WR(cb, GRCBASE_MISC + 13874 MISC_REGISTERS_RESET_REG_2_SET, 13875 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 13876 params->port)); 13877 } 13878 if (vars->line_speed < ELINK_SPEED_10000) 13879 elink_umac_enable(params, vars, 0); 13880 else 13881 elink_xmac_enable(params, vars, 0); 13882 #endif 13883 } else { 13884 #ifndef EXCLUDE_BMAC2 13885 if (vars->line_speed < ELINK_SPEED_10000) 13886 elink_emac_enable(params, vars, 0); 13887 else 13888 elink_bmac_enable(params, vars, 0, !dont_clear_stat); 13889 #endif 13890 } 13891 13892 /* Increment LFA count */ 13893 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) | 13894 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >> 13895 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff) 13896 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET)); 13897 /* Clear link flap reason */ 13898 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 13899 13900 REG_WR(cb, params->lfa_base + 13901 OFFSETOF(struct shmem_lfa, lfa_sts), lfa_sts); 13902 13903 /* Disable NIG DRAIN */ 13904 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13905 13906 /* Enable interrupts */ 13907 elink_link_int_enable(params); 13908 return ELINK_STATUS_OK; 13909 } 13910 13911 static void elink_cannot_avoid_link_flap(struct elink_params *params, 13912 struct elink_vars *vars, 13913 int lfa_status) 13914 { 13915 u32 lfa_sts, cfg_idx, tmp_val; 13916 struct elink_dev *cb = params->cb; 13917 13918 elink_link_reset(params, vars, 1); 13919 13920 if (!params->lfa_base) 13921 return; 13922 /* Store the new link parameters */ 13923 REG_WR(cb, params->lfa_base + 13924 OFFSETOF(struct shmem_lfa, req_duplex), 13925 params->req_duplex[0] | (params->req_duplex[1] << 16)); 13926 13927 REG_WR(cb, params->lfa_base + 13928 OFFSETOF(struct shmem_lfa, req_flow_ctrl), 13929 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); 13930 13931 REG_WR(cb, params->lfa_base + 13932 OFFSETOF(struct shmem_lfa, req_line_speed), 13933 params->req_line_speed[0] | (params->req_line_speed[1] << 16)); 13934 13935 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) { 13936 REG_WR(cb, params->lfa_base + 13937 OFFSETOF(struct shmem_lfa, 13938 speed_cap_mask[cfg_idx]), 13939 params->speed_cap_mask[cfg_idx]); 13940 } 13941 13942 tmp_val = REG_RD(cb, params->lfa_base + 13943 OFFSETOF(struct shmem_lfa, additional_config)); 13944 tmp_val &= ~REQ_FC_AUTO_ADV_MASK; 13945 tmp_val |= params->req_fc_auto_adv; 13946 13947 REG_WR(cb, params->lfa_base + 13948 OFFSETOF(struct shmem_lfa, additional_config), tmp_val); 13949 13950 lfa_sts = REG_RD(cb, params->lfa_base + 13951 OFFSETOF(struct shmem_lfa, lfa_sts)); 13952 13953 /* Clear the "Don't Clear Statistics" bit, and set reason */ 13954 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT; 13955 13956 /* Set link flap reason */ 13957 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 13958 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) << 13959 LFA_LINK_FLAP_REASON_OFFSET); 13960 13961 /* Increment link flap counter */ 13962 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) | 13963 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >> 13964 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff) 13965 << LINK_FLAP_COUNT_OFFSET)); 13966 REG_WR(cb, params->lfa_base + 13967 OFFSETOF(struct shmem_lfa, lfa_sts), lfa_sts); 13968 /* Proceed with regular link initialization */ 13969 } 13970 13971 elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars) 13972 { 13973 int lfa_status; 13974 struct elink_dev *cb = params->cb; 13975 ELINK_DEBUG_P0(cb, "Phy Initialization started\n"); 13976 ELINK_DEBUG_P2(cb, "(1) req_speed %d, req_flowctrl %d\n", 13977 params->req_line_speed[0], params->req_flow_ctrl[0]); 13978 ELINK_DEBUG_P2(cb, "(2) req_speed %d, req_flowctrl %d\n", 13979 params->req_line_speed[1], params->req_flow_ctrl[1]); 13980 ELINK_DEBUG_P1(cb, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv); 13981 vars->link_status = 0; 13982 vars->phy_link_up = 0; 13983 vars->link_up = 0; 13984 vars->line_speed = 0; 13985 vars->duplex = DUPLEX_FULL; 13986 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13987 vars->mac_type = ELINK_MAC_TYPE_NONE; 13988 vars->phy_flags = 0; 13989 vars->check_kr2_recovery_cnt = 0; 13990 params->link_flags = ELINK_PHY_INITIALIZED; 13991 #ifdef ELINK_ENHANCEMENTS 13992 /* Driver opens NIG-BRB filters */ 13993 elink_set_rx_filter(params, 1); 13994 #endif 13995 elink_chng_link_count(params, 1); 13996 /* Check if link flap can be avoided */ 13997 lfa_status = elink_check_lfa(params); 13998 13999 if (lfa_status == 0) { 14000 ELINK_DEBUG_P0(cb, "Link Flap Avoidance in progress\n"); 14001 return elink_avoid_link_flap(params, vars); 14002 } 14003 14004 ELINK_DEBUG_P1(cb, "Cannot avoid link flap lfa_sta=0x%x\n", 14005 lfa_status); 14006 elink_cannot_avoid_link_flap(params, vars, lfa_status); 14007 14008 /* Disable attentions */ 14009 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 14010 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 14011 ELINK_NIG_MASK_XGXS0_LINK10G | 14012 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 14013 ELINK_NIG_MASK_MI_INT)); 14014 #ifdef ELINK_INCLUDE_EMUL 14015 if (!(params->feature_config_flags & 14016 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC)) 14017 #endif //ELINK_INCLUDE_EMUL 14018 14019 elink_emac_init(params, vars); 14020 14021 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 14022 vars->link_status |= LINK_STATUS_PFC_ENABLED; 14023 14024 if ((params->num_phys == 0) && 14025 !CHIP_REV_IS_SLOW(params->chip_id)) { 14026 ELINK_DEBUG_P0(cb, "No phy found for initialization !!\n"); 14027 return ELINK_STATUS_ERROR; 14028 } 14029 set_phy_vars(params, vars); 14030 14031 ELINK_DEBUG_P1(cb, "Num of phys on board: %d\n", params->num_phys); 14032 #ifdef ELINK_INCLUDE_FPGA 14033 if (CHIP_REV_IS_FPGA(params->chip_id)) { 14034 return elink_init_fpga(params, vars); 14035 } else 14036 #endif /* ELINK_INCLUDE_FPGA */ 14037 #ifdef ELINK_INCLUDE_EMUL 14038 if (CHIP_REV_IS_EMUL(params->chip_id)) { 14039 return elink_init_emul(params, vars); 14040 } else 14041 #endif /* ELINK_INCLUDE_EMUL */ 14042 #ifdef ELINK_INCLUDE_LOOPBACK 14043 switch (params->loopback_mode) { 14044 case ELINK_LOOPBACK_BMAC: 14045 elink_init_bmac_loopback(params, vars); 14046 break; 14047 case ELINK_LOOPBACK_EMAC: 14048 elink_init_emac_loopback(params, vars); 14049 break; 14050 case ELINK_LOOPBACK_XMAC: 14051 elink_init_xmac_loopback(params, vars); 14052 break; 14053 case ELINK_LOOPBACK_UMAC: 14054 elink_init_umac_loopback(params, vars); 14055 break; 14056 case ELINK_LOOPBACK_XGXS: 14057 case ELINK_LOOPBACK_EXT_PHY: 14058 elink_init_xgxs_loopback(params, vars); 14059 break; 14060 default: 14061 #endif /* ELINK_INCLUDE_LOOPBACK */ 14062 #ifndef EXCLUDE_XGXS 14063 if (!CHIP_IS_E3(params->chip_id)) { 14064 if (params->switch_cfg == ELINK_SWITCH_CFG_10G) 14065 elink_xgxs_deassert(params); 14066 #ifndef EXCLUDE_SERDES 14067 else 14068 elink_serdes_deassert(cb, params->port); 14069 #endif // EXCLUDE_SERDES 14070 } 14071 #endif /* EXCLUDE_XGXS */ 14072 elink_link_initialize(params, vars); 14073 MSLEEP(cb, 30); 14074 elink_link_int_enable(params); 14075 #ifdef ELINK_INCLUDE_LOOPBACK 14076 break; 14077 } 14078 #endif // ELINK_INCLUDE_LOOPBACK 14079 elink_update_mng(params, vars->link_status); 14080 14081 #ifndef EXCLUDE_WARPCORE 14082 elink_update_mng_eee(params, vars->eee_status); 14083 #endif /* #ifndef EXCLUDE_BCM84833 */ 14084 return ELINK_STATUS_OK; 14085 } 14086 14087 #ifndef EXCLUDE_LINK_RESET 14088 elink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars, 14089 u8 reset_ext_phy) 14090 { 14091 struct elink_dev *cb = params->cb; 14092 u8 phy_index, port = params->port, clear_latch_ind = 0; 14093 ELINK_DEBUG_P1(cb, "Resetting the link of port %d\n", port); 14094 /* Disable attentions */ 14095 vars->link_status = 0; 14096 elink_chng_link_count(params, 1); 14097 elink_update_mng(params, vars->link_status); 14098 #ifndef EXCLUDE_WARPCORE 14099 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 14100 SHMEM_EEE_ACTIVE_BIT); 14101 elink_update_mng_eee(params, vars->eee_status); 14102 #endif /* #ifndef EXCLUDE_BCM84833 */ 14103 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 14104 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 14105 ELINK_NIG_MASK_XGXS0_LINK10G | 14106 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 14107 ELINK_NIG_MASK_MI_INT)); 14108 14109 /* Activate nig drain */ 14110 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 14111 14112 /* Disable nig egress interface */ 14113 if (!CHIP_IS_E3(params->chip_id)) { 14114 REG_WR(cb, NIG_REG_BMAC0_OUT_EN + port*4, 0); 14115 REG_WR(cb, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); 14116 } 14117 14118 #ifdef ELINK_INCLUDE_EMUL 14119 /* Stop BigMac rx */ 14120 if (!(params->feature_config_flags & 14121 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC)) 14122 #endif // ELINK_INCLUDE_EMUL 14123 #if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) 14124 if (!CHIP_IS_E3(params->chip_id)) 14125 elink_set_bmac_rx(cb, params->chip_id, port, 0); 14126 #endif // !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) 14127 #ifndef EXCLUDE_WARPCORE 14128 #ifdef ELINK_INCLUDE_EMUL 14129 /* Stop XMAC/UMAC rx */ 14130 if (!(params->feature_config_flags & 14131 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC)) 14132 #endif // ELINK_INCLUDE_EMUL 14133 if (CHIP_IS_E3(params->chip_id) && 14134 !CHIP_REV_IS_FPGA(params->chip_id)) { 14135 elink_set_xmac_rxtx(params, 0); 14136 elink_set_umac_rxtx(params, 0); 14137 } 14138 #endif // EXCLUDE_WARPCORE 14139 /* Disable emac */ 14140 if (!CHIP_IS_E3(params->chip_id)) 14141 REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 0); 14142 14143 MSLEEP(cb, 10); 14144 /* The PHY reset is controlled by GPIO 1 14145 * Hold it as vars low 14146 */ 14147 /* Clear link led */ 14148 elink_set_mdio_emac_per_phy(cb, params); 14149 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0); 14150 14151 if (reset_ext_phy && (!CHIP_REV_IS_SLOW(params->chip_id))) { 14152 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 14153 phy_index++) { 14154 if (params->phy[phy_index].link_reset) { 14155 elink_set_aer_mmd(params, 14156 ¶ms->phy[phy_index]); 14157 params->phy[phy_index].link_reset( 14158 ¶ms->phy[phy_index], 14159 params); 14160 } 14161 if (params->phy[phy_index].flags & 14162 ELINK_FLAGS_REARM_LATCH_SIGNAL) 14163 clear_latch_ind = 1; 14164 } 14165 } 14166 14167 if (clear_latch_ind) { 14168 /* Clear latching indication */ 14169 elink_rearm_latch_signal(cb, port, 0); 14170 elink_bits_dis(cb, NIG_REG_LATCH_BC_0 + port*4, 14171 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT); 14172 } 14173 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) 14174 if (!CHIP_REV_IS_SLOW(params->chip_id)) 14175 #endif 14176 if (params->phy[ELINK_INT_PHY].link_reset) 14177 params->phy[ELINK_INT_PHY].link_reset( 14178 ¶ms->phy[ELINK_INT_PHY], params); 14179 14180 /* Disable nig ingress interface */ 14181 if (!CHIP_IS_E3(params->chip_id)) { 14182 /* Reset BigMac */ 14183 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 14184 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 14185 REG_WR(cb, NIG_REG_BMAC0_IN_EN + port*4, 0); 14186 REG_WR(cb, NIG_REG_EMAC0_IN_EN + port*4, 0); 14187 } else { 14188 #ifndef EXCLUDE_WARPCORE 14189 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 14190 elink_set_xumac_nig(params, 0, 0); 14191 if (REG_RD(cb, MISC_REG_RESET_REG_2) & 14192 MISC_REGISTERS_RESET_REG_2_XMAC) 14193 REG_WR(cb, xmac_base + XMAC_REG_CTRL, 14194 XMAC_CTRL_REG_SOFT_RESET); 14195 #endif // EXCLUDE_WARPCORE 14196 } 14197 vars->link_up = 0; 14198 vars->phy_flags = 0; 14199 return ELINK_STATUS_OK; 14200 } 14201 #endif // EXCLUDE_LINK_RESET 14202 #ifndef ELINK_AUX_POWER 14203 elink_status_t elink_lfa_reset(struct elink_params *params, 14204 struct elink_vars *vars) 14205 { 14206 struct elink_dev *cb = params->cb; 14207 vars->link_up = 0; 14208 vars->phy_flags = 0; 14209 params->link_flags &= ~ELINK_PHY_INITIALIZED; 14210 if (!params->lfa_base) 14211 return elink_link_reset(params, vars, 1); 14212 /* 14213 * Activate NIG drain so that during this time the device won't send 14214 * anything while it is unable to response. 14215 */ 14216 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 14217 14218 /* 14219 * Close gracefully the gate from BMAC to NIG such that no half packets 14220 * are passed. 14221 */ 14222 if (!CHIP_IS_E3(params->chip_id)) 14223 elink_set_bmac_rx(cb, params->chip_id, params->port, 0); 14224 14225 if (CHIP_IS_E3(params->chip_id)) { 14226 elink_set_xmac_rxtx(params, 0); 14227 elink_set_umac_rxtx(params, 0); 14228 } 14229 /* Wait 10ms for the pipe to clean up*/ 14230 MSLEEP(cb, 10); 14231 14232 #ifdef ELINK_ENHANCEMENTS 14233 /* Clean the NIG-BRB using the network filters in a way that will 14234 * not cut a packet in the middle. 14235 */ 14236 elink_set_rx_filter(params, 0); 14237 #endif 14238 14239 /* 14240 * Re-open the gate between the BMAC and the NIG, after verifying the 14241 * gate to the BRB is closed, otherwise packets may arrive to the 14242 * firmware before driver had initialized it. The target is to achieve 14243 * minimum management protocol down time. 14244 */ 14245 if (!CHIP_IS_E3(params->chip_id)) 14246 elink_set_bmac_rx(cb, params->chip_id, params->port, 1); 14247 14248 if (CHIP_IS_E3(params->chip_id)) { 14249 elink_set_xmac_rxtx(params, 1); 14250 elink_set_umac_rxtx(params, 1); 14251 } 14252 /* Disable NIG drain */ 14253 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 14254 return ELINK_STATUS_OK; 14255 } 14256 #endif /* ELINK_AUX_POWER */ 14257 #endif // EXCLUDE_NON_COMMON_INIT 14258 14259 /****************************************************************************/ 14260 /* Common function */ 14261 /****************************************************************************/ 14262 #ifndef EXCLUDE_COMMON_INIT 14263 #ifndef ELINK_EMUL_ONLY 14264 #ifndef EXCLUDE_BCM8727_BCM8073 14265 static elink_status_t elink_8073_common_init_phy(struct elink_dev *cb, 14266 u32 shmem_base_path[], 14267 u32 shmem2_base_path[], u8 phy_index, 14268 u32 chip_id) 14269 { 14270 struct elink_phy phy[PORT_MAX]; 14271 struct elink_phy *phy_blk[PORT_MAX]; 14272 u16 val; 14273 s8 port = 0; 14274 s8 port_of_path = 0; 14275 u32 swap_val, swap_override; 14276 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP); 14277 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE); 14278 port ^= (swap_val && swap_override); 14279 elink_ext_phy_hw_reset(cb, port); 14280 /* PART1 - Reset both phys */ 14281 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 14282 u32 shmem_base, shmem2_base; 14283 /* In E2, same phy is using for port0 of the two paths */ 14284 if (CHIP_IS_E1X(chip_id)) { 14285 shmem_base = shmem_base_path[0]; 14286 shmem2_base = shmem2_base_path[0]; 14287 port_of_path = port; 14288 } else { 14289 shmem_base = shmem_base_path[port]; 14290 shmem2_base = shmem2_base_path[port]; 14291 port_of_path = 0; 14292 } 14293 14294 /* Extract the ext phy address for the port */ 14295 if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base, 14296 port_of_path, &phy[port]) != 14297 ELINK_STATUS_OK) { 14298 ELINK_DEBUG_P0(cb, "populate_phy failed\n"); 14299 return ELINK_STATUS_ERROR; 14300 } 14301 /* Disable attentions */ 14302 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + 14303 port_of_path*4, 14304 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 14305 ELINK_NIG_MASK_XGXS0_LINK10G | 14306 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 14307 ELINK_NIG_MASK_MI_INT)); 14308 14309 /* Need to take the phy out of low power mode in order 14310 * to write to access its registers 14311 */ 14312 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 14313 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 14314 port); 14315 14316 /* Reset the phy */ 14317 elink_cl45_write(cb, &phy[port], 14318 MDIO_PMA_DEVAD, 14319 MDIO_PMA_REG_CTRL, 14320 1<<15); 14321 } 14322 14323 /* Add delay of 150ms after reset */ 14324 MSLEEP(cb, 150); 14325 14326 if (phy[PORT_0].addr & 0x1) { 14327 phy_blk[PORT_0] = &(phy[PORT_1]); 14328 phy_blk[PORT_1] = &(phy[PORT_0]); 14329 } else { 14330 phy_blk[PORT_0] = &(phy[PORT_0]); 14331 phy_blk[PORT_1] = &(phy[PORT_1]); 14332 } 14333 14334 /* PART2 - Download firmware to both phys */ 14335 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 14336 if (CHIP_IS_E1X(chip_id)) 14337 port_of_path = port; 14338 else 14339 port_of_path = 0; 14340 14341 ELINK_DEBUG_P1(cb, "Loading spirom for phy address 0x%x\n", 14342 phy_blk[port]->addr); 14343 if (elink_8073_8727_external_rom_boot(cb, phy_blk[port], 14344 port_of_path)) 14345 return ELINK_STATUS_ERROR; 14346 14347 /* Only set bit 10 = 1 (Tx power down) */ 14348 elink_cl45_read(cb, phy_blk[port], 14349 MDIO_PMA_DEVAD, 14350 MDIO_PMA_REG_TX_POWER_DOWN, &val); 14351 14352 /* Phase1 of TX_POWER_DOWN reset */ 14353 elink_cl45_write(cb, phy_blk[port], 14354 MDIO_PMA_DEVAD, 14355 MDIO_PMA_REG_TX_POWER_DOWN, 14356 (val | 1<<10)); 14357 } 14358 14359 /* Toggle Transmitter: Power down and then up with 600ms delay 14360 * between 14361 */ 14362 MSLEEP(cb, 600); 14363 14364 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ 14365 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 14366 /* Phase2 of POWER_DOWN_RESET */ 14367 /* Release bit 10 (Release Tx power down) */ 14368 elink_cl45_read(cb, phy_blk[port], 14369 MDIO_PMA_DEVAD, 14370 MDIO_PMA_REG_TX_POWER_DOWN, &val); 14371 14372 elink_cl45_write(cb, phy_blk[port], 14373 MDIO_PMA_DEVAD, 14374 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); 14375 MSLEEP(cb, 15); 14376 14377 /* Read modify write the SPI-ROM version select register */ 14378 elink_cl45_read(cb, phy_blk[port], 14379 MDIO_PMA_DEVAD, 14380 MDIO_PMA_REG_EDC_FFE_MAIN, &val); 14381 elink_cl45_write(cb, phy_blk[port], 14382 MDIO_PMA_DEVAD, 14383 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); 14384 14385 /* set GPIO2 back to LOW */ 14386 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 14387 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 14388 } 14389 return ELINK_STATUS_OK; 14390 } 14391 #endif /* EXCLUDE_BCM8727_BCM8073 */ 14392 #ifndef EXCLUDE_BCM87x6 14393 static elink_status_t elink_8726_common_init_phy(struct elink_dev *cb, 14394 u32 shmem_base_path[], 14395 u32 shmem2_base_path[], u8 phy_index, 14396 u32 chip_id) 14397 { 14398 u32 val; 14399 s8 port; 14400 struct elink_phy phy; 14401 /* Use port1 because of the static port-swap */ 14402 /* Enable the module detection interrupt */ 14403 val = REG_RD(cb, MISC_REG_GPIO_EVENT_EN); 14404 val |= ((1<<MISC_REGISTERS_GPIO_3)| 14405 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); 14406 REG_WR(cb, MISC_REG_GPIO_EVENT_EN, val); 14407 14408 elink_ext_phy_hw_reset(cb, 0); 14409 MSLEEP(cb, 5); 14410 for (port = 0; port < PORT_MAX; port++) { 14411 u32 shmem_base, shmem2_base; 14412 14413 /* In E2, same phy is using for port0 of the two paths */ 14414 if (CHIP_IS_E1X(chip_id)) { 14415 shmem_base = shmem_base_path[0]; 14416 shmem2_base = shmem2_base_path[0]; 14417 } else { 14418 shmem_base = shmem_base_path[port]; 14419 shmem2_base = shmem2_base_path[port]; 14420 } 14421 /* Extract the ext phy address for the port */ 14422 if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base, 14423 port, &phy) != 14424 ELINK_STATUS_OK) { 14425 ELINK_DEBUG_P0(cb, "populate phy failed\n"); 14426 return ELINK_STATUS_ERROR; 14427 } 14428 14429 /* Reset phy*/ 14430 elink_cl45_write(cb, &phy, 14431 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); 14432 14433 14434 /* Set fault module detected LED on */ 14435 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_0, 14436 MISC_REGISTERS_GPIO_HIGH, 14437 port); 14438 } 14439 14440 return ELINK_STATUS_OK; 14441 } 14442 #endif /* #ifndef EXCLUDE_BCM87x6 */ 14443 #ifndef EXCLUDE_BCM8727_BCM8073 14444 static void elink_get_ext_phy_reset_gpio(struct elink_dev *cb, u32 shmem_base, 14445 u8 *io_gpio, u8 *io_port) 14446 { 14447 14448 u32 phy_gpio_reset = REG_RD(cb, shmem_base + 14449 OFFSETOF(struct shmem_region, 14450 dev_info.port_hw_config[PORT_0].default_cfg)); 14451 switch (phy_gpio_reset) { 14452 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: 14453 *io_gpio = 0; 14454 *io_port = 0; 14455 break; 14456 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: 14457 *io_gpio = 1; 14458 *io_port = 0; 14459 break; 14460 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: 14461 *io_gpio = 2; 14462 *io_port = 0; 14463 break; 14464 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: 14465 *io_gpio = 3; 14466 *io_port = 0; 14467 break; 14468 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: 14469 *io_gpio = 0; 14470 *io_port = 1; 14471 break; 14472 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: 14473 *io_gpio = 1; 14474 *io_port = 1; 14475 break; 14476 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: 14477 *io_gpio = 2; 14478 *io_port = 1; 14479 break; 14480 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: 14481 *io_gpio = 3; 14482 *io_port = 1; 14483 break; 14484 default: 14485 /* Don't override the io_gpio and io_port */ 14486 break; 14487 } 14488 } 14489 14490 static elink_status_t elink_8727_common_init_phy(struct elink_dev *cb, 14491 u32 shmem_base_path[], 14492 u32 shmem2_base_path[], u8 phy_index, 14493 u32 chip_id) 14494 { 14495 s8 port, reset_gpio; 14496 u32 swap_val, swap_override; 14497 struct elink_phy phy[PORT_MAX]; 14498 struct elink_phy *phy_blk[PORT_MAX]; 14499 s8 port_of_path; 14500 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP); 14501 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE); 14502 14503 reset_gpio = MISC_REGISTERS_GPIO_1; 14504 port = 1; 14505 14506 /* Retrieve the reset gpio/port which control the reset. 14507 * Default is GPIO1, PORT1 14508 */ 14509 elink_get_ext_phy_reset_gpio(cb, shmem_base_path[0], 14510 (u8 *)&reset_gpio, (u8 *)&port); 14511 14512 /* Calculate the port based on port swap */ 14513 port ^= (swap_val && swap_override); 14514 14515 /* Initiate PHY reset*/ 14516 ELINK_SET_GPIO(cb, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, 14517 port); 14518 MSLEEP(cb, 1); 14519 ELINK_SET_GPIO(cb, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, 14520 port); 14521 14522 MSLEEP(cb, 5); 14523 14524 /* PART1 - Reset both phys */ 14525 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 14526 u32 shmem_base, shmem2_base; 14527 14528 /* In E2, same phy is using for port0 of the two paths */ 14529 if (CHIP_IS_E1X(chip_id)) { 14530 shmem_base = shmem_base_path[0]; 14531 shmem2_base = shmem2_base_path[0]; 14532 port_of_path = port; 14533 } else { 14534 shmem_base = shmem_base_path[port]; 14535 shmem2_base = shmem2_base_path[port]; 14536 port_of_path = 0; 14537 } 14538 14539 /* Extract the ext phy address for the port */ 14540 if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base, 14541 port_of_path, &phy[port]) != 14542 ELINK_STATUS_OK) { 14543 ELINK_DEBUG_P0(cb, "populate phy failed\n"); 14544 return ELINK_STATUS_ERROR; 14545 } 14546 /* disable attentions */ 14547 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + 14548 port_of_path*4, 14549 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 14550 ELINK_NIG_MASK_XGXS0_LINK10G | 14551 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 14552 ELINK_NIG_MASK_MI_INT)); 14553 14554 14555 /* Reset the phy */ 14556 elink_cl45_write(cb, &phy[port], 14557 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 14558 } 14559 14560 /* Add delay of 150ms after reset */ 14561 MSLEEP(cb, 150); 14562 if (phy[PORT_0].addr & 0x1) { 14563 phy_blk[PORT_0] = &(phy[PORT_1]); 14564 phy_blk[PORT_1] = &(phy[PORT_0]); 14565 } else { 14566 phy_blk[PORT_0] = &(phy[PORT_0]); 14567 phy_blk[PORT_1] = &(phy[PORT_1]); 14568 } 14569 /* PART2 - Download firmware to both phys */ 14570 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 14571 if (CHIP_IS_E1X(chip_id)) 14572 port_of_path = port; 14573 else 14574 port_of_path = 0; 14575 ELINK_DEBUG_P1(cb, "Loading spirom for phy address 0x%x\n", 14576 phy_blk[port]->addr); 14577 if (elink_8073_8727_external_rom_boot(cb, phy_blk[port], 14578 port_of_path)) 14579 return ELINK_STATUS_ERROR; 14580 /* Disable PHY transmitter output */ 14581 elink_cl45_write(cb, phy_blk[port], 14582 MDIO_PMA_DEVAD, 14583 MDIO_PMA_REG_TX_DISABLE, 1); 14584 14585 } 14586 return ELINK_STATUS_OK; 14587 } 14588 #endif /* EXCLUDE_BCM8727_BCM8073 */ 14589 14590 #ifndef EXCLUDE_BCM84833 14591 static elink_status_t elink_84833_common_init_phy(struct elink_dev *cb, 14592 u32 shmem_base_path[], 14593 u32 shmem2_base_path[], 14594 u8 phy_index, 14595 u32 chip_id) 14596 { 14597 u8 reset_gpios; 14598 reset_gpios = elink_84833_get_reset_gpios(cb, shmem_base_path, chip_id); 14599 #ifndef EDEBUG 14600 ELINK_SET_MULT_GPIO(cb, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 14601 USLEEP(cb, 10); 14602 ELINK_SET_MULT_GPIO(cb, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); 14603 ELINK_DEBUG_P1(cb, "84833 reset pulse on pin values 0x%x\n", 14604 reset_gpios); 14605 #endif 14606 return ELINK_STATUS_OK; 14607 } 14608 #ifndef EXCLUDE_FROM_BNX2X 14609 static elink_status_t elink_84833_pre_init_phy(struct elink_dev *cb, 14610 struct elink_phy *phy, 14611 u8 port) 14612 { 14613 u16 val, cnt; 14614 /* Wait for FW completing its initialization. */ 14615 for (cnt = 0; cnt < 1500; cnt++) { 14616 elink_cl45_read(cb, phy, 14617 MDIO_PMA_DEVAD, 14618 MDIO_PMA_REG_CTRL, &val); 14619 if (!(val & (1<<15))) 14620 break; 14621 MSLEEP(cb, 1); 14622 } 14623 if (cnt >= 1500) { 14624 ELINK_DEBUG_P0(cb, "84833 reset timeout\n"); 14625 return ELINK_STATUS_ERROR; 14626 } 14627 14628 /* Put the port in super isolate mode. */ 14629 elink_cl45_read(cb, phy, 14630 MDIO_CTL_DEVAD, 14631 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val); 14632 val |= MDIO_84833_SUPER_ISOLATE; 14633 elink_cl45_write(cb, phy, 14634 MDIO_CTL_DEVAD, 14635 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val); 14636 14637 /* Save spirom version */ 14638 elink_save_848xx_spirom_version(phy, cb, port); 14639 return ELINK_STATUS_OK; 14640 } 14641 14642 elink_status_t elink_pre_init_phy(struct elink_dev *cb, 14643 u32 shmem_base, 14644 u32 shmem2_base, 14645 u32 chip_id, 14646 u8 port) 14647 { 14648 elink_status_t rc = ELINK_STATUS_OK; 14649 struct elink_phy phy; 14650 if (elink_populate_phy(cb, ELINK_EXT_PHY1, shmem_base, shmem2_base, 14651 port, &phy) != ELINK_STATUS_OK) { 14652 ELINK_DEBUG_P0(cb, "populate_phy failed\n"); 14653 return ELINK_STATUS_ERROR; 14654 } 14655 elink_set_mdio_clk(cb, chip_id, phy.mdio_ctrl); 14656 switch (phy.type) { 14657 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 14658 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 14659 rc = elink_84833_pre_init_phy(cb, &phy, port); 14660 break; 14661 default: 14662 break; 14663 } 14664 return rc; 14665 } 14666 #endif /* EXCLUDE_FROM_BNX2X */ 14667 #endif /* EXCLUDE_BCM84833 */ 14668 static elink_status_t elink_ext_phy_common_init(struct elink_dev *cb, u32 shmem_base_path[], 14669 u32 shmem2_base_path[], u8 phy_index, 14670 u32 ext_phy_type, u32 chip_id) 14671 { 14672 elink_status_t rc = ELINK_STATUS_OK; 14673 14674 switch (ext_phy_type) { 14675 #ifndef EXCLUDE_BCM8727_BCM8073 14676 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 14677 rc = elink_8073_common_init_phy(cb, shmem_base_path, 14678 shmem2_base_path, 14679 phy_index, chip_id); 14680 break; 14681 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 14682 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 14683 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 14684 rc = elink_8727_common_init_phy(cb, shmem_base_path, 14685 shmem2_base_path, 14686 phy_index, chip_id); 14687 break; 14688 14689 #endif 14690 #ifndef EXCLUDE_BCM87x6 14691 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 14692 /* GPIO1 affects both ports, so there's need to pull 14693 * it for single port alone 14694 */ 14695 rc = elink_8726_common_init_phy(cb, shmem_base_path, 14696 shmem2_base_path, 14697 phy_index, chip_id); 14698 break; 14699 #endif /* #ifndef EXCLUDE_BCM87x6 */ 14700 #ifndef EXCLUDE_BCM84833 14701 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 14702 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 14703 /* GPIO3's are linked, and so both need to be toggled 14704 * to obtain required 2us pulse. 14705 */ 14706 rc = elink_84833_common_init_phy(cb, shmem_base_path, 14707 shmem2_base_path, 14708 phy_index, chip_id); 14709 break; 14710 #endif 14711 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 14712 rc = ELINK_STATUS_ERROR; 14713 break; 14714 default: 14715 ELINK_DEBUG_P1(cb, 14716 "ext_phy 0x%x common init not required\n", 14717 ext_phy_type); 14718 break; 14719 } 14720 14721 if (rc != ELINK_STATUS_OK) 14722 elink_cb_event_log(cb, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized," 14723 // " Port %d\n", 14724 14725 return rc; 14726 } 14727 14728 #ifdef INCLUDE_WARPCORE_UC_LOAD 14729 static elink_status_t elink_warpcore_common_init(struct elink_dev *cb, 14730 u32 shmem_base_path[], 14731 u32 shmem2_base_path[], 14732 u8 phy_index, 14733 u32 chip_id, 14734 u8 one_port_enabled) 14735 { 14736 struct elink_phy phy; 14737 u32 wc_lane_config; 14738 u16 val; 14739 elink_status_t rc; 14740 14741 REG_WR(cb, MISC_REG_LCPLL_E40_PWRDWN, 0); 14742 /* Procedure to bring the LCPLL out of reset. */ 14743 MSLEEP(cb, 1); 14744 REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_ANA, 1); 14745 MSLEEP(cb, 1); 14746 REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_DIG, 1); 14747 14748 ELINK_DEBUG_P0(cb, "Resetting Warpcore\n"); 14749 14750 if (elink_reset_warpcore(cb) != ELINK_STATUS_OK) 14751 return ELINK_STATUS_ERROR; 14752 14753 /* Extract the ext phy address for the port */ 14754 if (elink_populate_phy(cb, phy_index, shmem_base_path[0], 14755 shmem2_base_path[0], 14756 0, &phy) != ELINK_STATUS_OK) { 14757 ELINK_DEBUG_P0(cb, "populate phy failed\n"); 14758 return ELINK_STATUS_ERROR; 14759 } 14760 14761 /* Set WC to use CL45 */ 14762 REG_WR(cb, MISC_REG_WC0_CTRL_MD_ST, 0); 14763 /* Set swap lanes and polarity */ 14764 wc_lane_config = REG_RD(cb, shmem_base_path[0] + 14765 OFFSETOF(struct shmem_region, dev_info. 14766 shared_hw_config.wc_lane_config)); 14767 14768 /* Power down warpcore lanes */ 14769 if (one_port_enabled) 14770 elink_warpcore_powerdown_secondport_lanes(cb, &phy); 14771 14772 /* Disable sequencer */ 14773 elink_warpcore_sequencer(cb, &phy, 0); 14774 14775 elink_warpcore_set_lane_swap(cb, &phy, wc_lane_config); 14776 elink_warpcore_set_lane_polarity(cb, &phy, wc_lane_config); 14777 14778 if (phy.flags & ELINK_FLAGS_WC_DUAL_MODE) 14779 elink_warpcore_set_dual_mode(cb, &phy, shmem_base_path[0]); 14780 else 14781 elink_warpcore_set_quad_mode(cb, &phy); 14782 14783 /* Load Warpcore microcode */ 14784 rc = elink_warpcore_load_uc(cb, &phy); 14785 if (rc != ELINK_STATUS_OK) 14786 return rc; 14787 14788 /* RX traffic and TX traffic requires clock sync. 14789 * When transmiting we send data + clock to the Warpcore. 14790 * This clock is provided by lane 0 of the Warpcore. 14791 * So we need to configure this lane to supply us the correct clock 14792 * which will be use for transmit on all lanes 14793 */ 14794 14795 CL22_WR_OVER_CL45(cb, &phy, MDIO_REG_BANK_AER_BLOCK, 14796 MDIO_AER_BLOCK_AER_REG, 0); 14797 elink_cl45_read(cb, &phy, MDIO_WC_DEVAD, 14798 MDIO_WC_REG_XGXS_X2_CONTROL2, &val); 14799 val &= 0xDE1F; 14800 if (phy.flags & ELINK_FLAGS_WC_DUAL_MODE) { 14801 val |= (1<<11); 14802 val |= (9<<5); 14803 /* To force tx_wclk33 to txckp[0] */ 14804 if (phy.supported & ELINK_SUPPORTED_20000baseKR2_Full) 14805 val |= (1<<13); 14806 14807 /* Dual mode - lanes 0,1 use same clocks/resets - from lane 0 14808 * Lanes 2,3 use same clocks/resets - from lane 2 14809 */ 14810 elink_cl45_write(cb, &phy, MDIO_WC_DEVAD, 14811 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); 14812 } else 14813 val |= 0x2800; 14814 14815 elink_cl45_write(cb, &phy, MDIO_WC_DEVAD, 14816 MDIO_WC_REG_XGXS_X2_CONTROL2, val); 14817 14818 /* Enable sequencer */ 14819 elink_warpcore_sequencer(cb, &phy, 1); 14820 14821 return ELINK_STATUS_OK; 14822 } 14823 14824 #endif /* INCLUDE_WARPCORE_UC_LOAD */ 14825 #endif /* ELINK_EMUL_ONLY */ 14826 elink_status_t elink_common_init_phy(struct elink_dev *cb, u32 shmem_base_path[], 14827 u32 shmem2_base_path[], u32 chip_id, 14828 u8 one_port_enabled) 14829 { 14830 elink_status_t rc = ELINK_STATUS_OK; 14831 u32 phy_ver, val; 14832 #ifndef ELINK_EMUL_ONLY 14833 u8 phy_index = 0; 14834 u32 ext_phy_type, ext_phy_config; 14835 #endif 14836 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) 14837 if (CHIP_REV_IS_EMUL(chip_id) || CHIP_REV_IS_FPGA(chip_id)) 14838 return ELINK_STATUS_OK; 14839 #endif 14840 14841 elink_set_mdio_clk(cb, chip_id, GRCBASE_EMAC0); 14842 elink_set_mdio_clk(cb, chip_id, GRCBASE_EMAC1); 14843 ELINK_DEBUG_P0(cb, "Begin common phy init\n"); 14844 if (CHIP_IS_E3(chip_id)) { 14845 /* Enable EPIO */ 14846 val = REG_RD(cb, MISC_REG_GEN_PURP_HWG); 14847 REG_WR(cb, MISC_REG_GEN_PURP_HWG, val | 1); 14848 } 14849 #ifndef ELINK_EMUL_ONLY 14850 /* Check if common init was already done */ 14851 phy_ver = REG_RD(cb, shmem_base_path[0] + 14852 OFFSETOF(struct shmem_region, 14853 port_mb[PORT_0].ext_phy_fw_version)); 14854 if (phy_ver) { 14855 ELINK_DEBUG_P1(cb, "Not doing common init; phy ver is 0x%x\n", 14856 phy_ver); 14857 return ELINK_STATUS_OK; 14858 } 14859 14860 #ifdef INCLUDE_WARPCORE_UC_LOAD 14861 if (ELINK_USES_WARPCORE(chip_id)) { 14862 rc |= elink_warpcore_common_init(cb, shmem_base_path, 14863 shmem2_base_path, phy_index, 14864 chip_id, one_port_enabled); 14865 } 14866 #endif 14867 /* Read the ext_phy_type for arbitrary port(0) */ 14868 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; 14869 phy_index++) { 14870 ext_phy_config = elink_get_ext_phy_config(cb, 14871 shmem_base_path[0], 14872 phy_index, 0); 14873 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config); 14874 rc |= elink_ext_phy_common_init(cb, shmem_base_path, 14875 shmem2_base_path, 14876 phy_index, ext_phy_type, 14877 chip_id); 14878 } 14879 #endif /* ELINK_EMUL_ONLY */ 14880 return rc; 14881 } 14882 #endif // #ifndef EXCLUDE_COMMON_INIT 14883 14884 #ifndef EXCLUDE_NON_COMMON_INIT 14885 #ifndef EXCLUDE_WARPCORE 14886 static void elink_check_over_curr(struct elink_params *params, 14887 struct elink_vars *vars) 14888 { 14889 struct elink_dev *cb = params->cb; 14890 u32 cfg_pin; 14891 u8 port = params->port; 14892 u32 pin_val; 14893 14894 cfg_pin = (REG_RD(cb, params->shmem_base + 14895 OFFSETOF(struct shmem_region, 14896 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & 14897 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> 14898 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; 14899 14900 /* Ignore check if no external input PIN available */ 14901 if (elink_get_cfg_pin(cb, cfg_pin, &pin_val) != ELINK_STATUS_OK) 14902 return; 14903 14904 if (!pin_val) { 14905 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { 14906 #ifndef ELINK_AUX_POWER 14907 elink_cb_event_log(cb, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has" 14908 // " been detected and the power to " 14909 // "that SFP+ module has been removed" 14910 // " to prevent failure of the card." 14911 // " Please remove the SFP+ module and" 14912 // " restart the system to clear this" 14913 // " error.\n", 14914 #endif /* ELINK_AUX_POWER */ 14915 vars->phy_flags |= PHY_OVER_CURRENT_FLAG; 14916 elink_warpcore_power_module(params, 0); 14917 } 14918 } else 14919 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; 14920 } 14921 #endif // EXCLUDE_WARPCORE 14922 14923 /* Returns 0 if no change occured since last check; 1 otherwise. */ 14924 static u8 elink_analyze_link_error(struct elink_params *params, 14925 struct elink_vars *vars, u32 status, 14926 u32 phy_flag, u32 link_flag, u8 notify) 14927 { 14928 struct elink_dev *cb = params->cb; 14929 /* Compare new value with previous value */ 14930 u8 led_mode; 14931 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0; 14932 14933 if ((status ^ old_status) == 0) 14934 return 0; 14935 14936 /* If values differ */ 14937 switch (phy_flag) { 14938 case PHY_HALF_OPEN_CONN_FLAG: 14939 ELINK_DEBUG_P0(cb, "Analyze Remote Fault\n"); 14940 break; 14941 case PHY_SFP_TX_FAULT_FLAG: 14942 ELINK_DEBUG_P0(cb, "Analyze TX Fault\n"); 14943 break; 14944 default: 14945 ELINK_DEBUG_P0(cb, "Analyze UNKNOWN\n"); 14946 } 14947 ELINK_DEBUG_P3(cb, "Link changed:[%x %x]->%x\n", vars->link_up, 14948 old_status, status); 14949 14950 /* Do not touch the link in case physical link down */ 14951 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) 14952 return 1; 14953 14954 /* a. Update shmem->link_status accordingly 14955 * b. Update elink_vars->link_up 14956 */ 14957 if (status) { 14958 vars->link_status &= ~LINK_STATUS_LINK_UP; 14959 vars->link_status |= link_flag; 14960 vars->link_up = 0; 14961 vars->phy_flags |= phy_flag; 14962 14963 /* activate nig drain */ 14964 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 14965 /* Set LED mode to off since the PHY doesn't know about these 14966 * errors 14967 */ 14968 led_mode = ELINK_LED_MODE_OFF; 14969 } else { 14970 vars->link_status |= LINK_STATUS_LINK_UP; 14971 vars->link_status &= ~link_flag; 14972 vars->link_up = 1; 14973 vars->phy_flags &= ~phy_flag; 14974 led_mode = ELINK_LED_MODE_OPER; 14975 14976 /* Clear nig drain */ 14977 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 14978 } 14979 #ifndef ELINK_AUX_POWER 14980 #ifdef ELINK_57711E_SUPPORT 14981 elink_sync_link(params, vars); 14982 #endif // ELINK_57711E_SUPPORT 14983 #endif // ELINK_AUX_POWER 14984 /* Update the LED according to the link state */ 14985 elink_set_led(params, vars, led_mode, ELINK_SPEED_10000); 14986 14987 /* Update link status in the shared memory */ 14988 elink_update_mng(params, vars->link_status); 14989 14990 /* C. Trigger General Attention */ 14991 vars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT; 14992 #ifndef EDEBUG 14993 if (notify) 14994 elink_cb_notify_link_changed(cb); 14995 #endif // EDEBUG 14996 14997 return 1; 14998 } 14999 15000 /****************************************************************************** 15001 * Description: 15002 * This function checks for half opened connection change indication. 15003 * When such change occurs, it calls the elink_analyze_link_error 15004 * to check if Remote Fault is set or cleared. Reception of remote fault 15005 * status message in the MAC indicates that the peer's MAC has detected 15006 * a fault, for example, due to break in the TX side of fiber. 15007 * 15008 ******************************************************************************/ 15009 #ifdef BNX2X_ADD /* BNX2X_ADD */ 15010 static 15011 #endif 15012 elink_status_t elink_check_half_open_conn(struct elink_params *params, 15013 struct elink_vars *vars, 15014 u8 notify) 15015 { 15016 struct elink_dev *cb = params->cb; 15017 u32 lss_status = 0; 15018 u32 mac_base; 15019 /* In case link status is physically up @ 10G do */ 15020 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || 15021 (REG_RD(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) 15022 return ELINK_STATUS_OK; 15023 15024 if (CHIP_IS_E3(params->chip_id) && 15025 (REG_RD(cb, MISC_REG_RESET_REG_2) & 15026 (MISC_REGISTERS_RESET_REG_2_XMAC))) { 15027 /* Check E3 XMAC */ 15028 /* Note that link speed cannot be queried here, since it may be 15029 * zero while link is down. In case UMAC is active, LSS will 15030 * simply not be set 15031 */ 15032 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 15033 15034 /* Clear stick bits (Requires rising edge) */ 15035 REG_WR(cb, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 15036 REG_WR(cb, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 15037 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 15038 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 15039 if (REG_RD(cb, mac_base + XMAC_REG_RX_LSS_STATUS)) 15040 lss_status = 1; 15041 15042 elink_analyze_link_error(params, vars, lss_status, 15043 PHY_HALF_OPEN_CONN_FLAG, 15044 LINK_STATUS_NONE, notify); 15045 } else if (REG_RD(cb, MISC_REG_RESET_REG_2) & 15046 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { 15047 /* Check E1X / E2 BMAC */ 15048 u32 lss_status_reg; 15049 u32 wb_data[2]; 15050 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 15051 NIG_REG_INGRESS_BMAC0_MEM; 15052 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ 15053 if (CHIP_IS_E2(params->chip_id)) 15054 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; 15055 else 15056 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; 15057 15058 REG_RD_DMAE(cb, mac_base + lss_status_reg, wb_data, 2); 15059 lss_status = (wb_data[0] > 0); 15060 15061 elink_analyze_link_error(params, vars, lss_status, 15062 PHY_HALF_OPEN_CONN_FLAG, 15063 LINK_STATUS_NONE, notify); 15064 } 15065 return ELINK_STATUS_OK; 15066 } 15067 #ifdef ELINK_ENHANCEMENTS 15068 static void elink_sfp_tx_fault_detection(struct elink_phy *phy, 15069 struct elink_params *params, 15070 struct elink_vars *vars) 15071 { 15072 struct elink_dev *cb = params->cb; 15073 u32 cfg_pin, value = 0; 15074 u8 led_change, port = params->port; 15075 15076 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ 15077 cfg_pin = (REG_RD(cb, params->shmem_base + OFFSETOF(struct shmem_region, 15078 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 15079 PORT_HW_CFG_E3_TX_FAULT_MASK) >> 15080 PORT_HW_CFG_E3_TX_FAULT_SHIFT; 15081 15082 if (elink_get_cfg_pin(cb, cfg_pin, &value)) { 15083 ELINK_DEBUG_P1(cb, "Failed to read pin 0x%02x\n", cfg_pin); 15084 return; 15085 } 15086 15087 led_change = elink_analyze_link_error(params, vars, value, 15088 PHY_SFP_TX_FAULT_FLAG, 15089 LINK_STATUS_SFP_TX_FAULT, 1); 15090 15091 if (led_change) { 15092 /* Change TX_Fault led, set link status for further syncs */ 15093 u8 led_mode; 15094 15095 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { 15096 led_mode = MISC_REGISTERS_GPIO_HIGH; 15097 vars->link_status |= LINK_STATUS_SFP_TX_FAULT; 15098 } else { 15099 led_mode = MISC_REGISTERS_GPIO_LOW; 15100 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 15101 } 15102 15103 /* If module is unapproved, led should be on regardless */ 15104 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) { 15105 ELINK_DEBUG_P1(cb, "Change TX_Fault LED: ->%x\n", 15106 led_mode); 15107 elink_set_e3_module_fault_led(params, led_mode); 15108 } 15109 } 15110 } 15111 #endif 15112 #ifndef EXCLUDE_WARPCORE 15113 static void elink_kr2_recovery(struct elink_params *params, 15114 struct elink_vars *vars, 15115 struct elink_phy *phy) 15116 { 15117 #ifdef ELINK_DEBUG 15118 struct elink_dev *cb = params->cb; 15119 ELINK_DEBUG_P0(cb, "KR2 recovery\n"); 15120 #endif // ELINK_DEBUG 15121 elink_warpcore_enable_AN_KR2(phy, params, vars); 15122 elink_warpcore_restart_AN_KR(phy, params); 15123 } 15124 15125 static void elink_check_kr2_wa(struct elink_params *params, 15126 struct elink_vars *vars, 15127 struct elink_phy *phy) 15128 { 15129 struct elink_dev *cb = params->cb; 15130 u16 base_page, next_page, not_kr2_device, lane; 15131 int sigdet; 15132 15133 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery 15134 * Since some switches tend to reinit the AN process and clear the 15135 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled 15136 * and recovered many times 15137 */ 15138 if (vars->check_kr2_recovery_cnt > 0) { 15139 vars->check_kr2_recovery_cnt--; 15140 return; 15141 } 15142 15143 sigdet = elink_warpcore_get_sigdet(phy, params); 15144 if (!sigdet) { 15145 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 15146 elink_kr2_recovery(params, vars, phy); 15147 ELINK_DEBUG_P0(cb, "No sigdet\n"); 15148 } 15149 return; 15150 } 15151 15152 lane = elink_get_warpcore_lane(phy, params); 15153 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 15154 MDIO_AER_BLOCK_AER_REG, lane); 15155 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 15156 MDIO_AN_REG_LP_AUTO_NEG, &base_page); 15157 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 15158 MDIO_AN_REG_LP_AUTO_NEG2, &next_page); 15159 elink_set_aer_mmd(params, phy); 15160 15161 /* CL73 has not begun yet */ 15162 if (base_page == 0) { 15163 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 15164 elink_kr2_recovery(params, vars, phy); 15165 ELINK_DEBUG_P0(cb, "No BP\n"); 15166 } 15167 return; 15168 } 15169 15170 /* In case NP bit is not set in the BasePage, or it is set, 15171 * but only KX is advertised, declare this link partner as non-KR2 15172 * device. 15173 */ 15174 not_kr2_device = (((base_page & 0x8000) == 0) || 15175 (((base_page & 0x8000) && 15176 ((next_page & 0xe0) == 0x20)))); 15177 15178 /* In case KR2 is already disabled, check if we need to re-enable it */ 15179 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 15180 if (!not_kr2_device) { 15181 ELINK_DEBUG_P2(cb, "BP=0x%x, NP=0x%x\n", base_page, 15182 next_page); 15183 elink_kr2_recovery(params, vars, phy); 15184 } 15185 return; 15186 } 15187 /* KR2 is enabled, but not KR2 device */ 15188 if (not_kr2_device) { 15189 /* Disable KR2 on both lanes */ 15190 ELINK_DEBUG_P2(cb, "BP=0x%x, NP=0x%x\n", base_page, next_page); 15191 elink_disable_kr2(params, vars, phy); 15192 /* Restart AN on leading lane */ 15193 elink_warpcore_restart_AN_KR(phy, params); 15194 return; 15195 } 15196 } 15197 #endif 15198 15199 void elink_period_func(struct elink_params *params, struct elink_vars *vars) 15200 { 15201 u16 phy_idx; 15202 #if defined(ELINK_DEBUG) || defined(ELINK_ENHANCEMENTS) 15203 struct elink_dev *cb = params->cb; 15204 #endif 15205 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 15206 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) { 15207 elink_set_aer_mmd(params, ¶ms->phy[phy_idx]); 15208 if (elink_check_half_open_conn(params, vars, 1) != 15209 ELINK_STATUS_OK) 15210 ELINK_DEBUG_P0(cb, "Fault detection failed\n"); 15211 break; 15212 } 15213 } 15214 15215 #ifndef EXCLUDE_WARPCORE 15216 if (CHIP_IS_E3(params->chip_id)) { 15217 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; 15218 elink_set_aer_mmd(params, phy); 15219 if ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) && 15220 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) 15221 elink_check_kr2_wa(params, vars, phy); 15222 #ifdef ELINK_AUX_POWER 15223 if ((phy->flags & ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC) == 0) { 15224 if (elink_is_sfp_module_plugged(phy, params)) { 15225 phy->flags |= 15226 ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC; 15227 elink_sfp_module_detection(phy, params); 15228 } 15229 } else { 15230 if (!elink_is_sfp_module_plugged(phy, params)) { 15231 elink_sfp_set_transmitter(params, phy, 1); 15232 phy->flags &= 15233 ~ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC; 15234 } 15235 } 15236 #endif // ELINK_AUX_POWER 15237 elink_check_over_curr(params, vars); 15238 #ifdef ELINK_ENHANCEMENTS 15239 if (vars->rx_tx_asic_rst) 15240 elink_warpcore_config_runtime(phy, params, vars); 15241 15242 if ((REG_RD(cb, params->shmem_base + 15243 OFFSETOF(struct shmem_region, dev_info. 15244 port_hw_config[params->port].default_cfg)) 15245 & PORT_HW_CFG_NET_SERDES_IF_MASK) == 15246 PORT_HW_CFG_NET_SERDES_IF_SFI) { 15247 if (elink_is_sfp_module_plugged(phy, params)) { 15248 elink_sfp_tx_fault_detection(phy, params, vars); 15249 } else if (vars->link_status & 15250 LINK_STATUS_SFP_TX_FAULT) { 15251 /* Clean trail, interrupt corrects the leds */ 15252 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 15253 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; 15254 /* Update link status in the shared memory */ 15255 elink_update_mng(params, vars->link_status); 15256 } 15257 } 15258 #endif // ELINK_ENHANCEMENTS 15259 } 15260 #endif /* EXCLUDE_WARPCORE */ 15261 } 15262 15263 #ifdef ELINK_ENHANCEMENTS 15264 u8 elink_fan_failure_det_req(struct elink_dev *cb, 15265 u32 shmem_base, 15266 u32 shmem2_base, 15267 u8 port) 15268 { 15269 u8 phy_index, fan_failure_det_req = 0; 15270 struct elink_phy phy; 15271 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; 15272 phy_index++) { 15273 if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base, 15274 port, &phy) 15275 != ELINK_STATUS_OK) { 15276 ELINK_DEBUG_P0(cb, "populate phy failed\n"); 15277 return 0; 15278 } 15279 fan_failure_det_req |= (phy.flags & 15280 ELINK_FLAGS_FAN_FAILURE_DET_REQ); 15281 } 15282 return fan_failure_det_req; 15283 } 15284 #endif // ELINK_ENHANCEMENTS 15285 #ifdef ELINK_AUX_POWER 15286 void elink_enable_pmd_tx(struct elink_params *params) 15287 { 15288 u8 phy_index; 15289 elink_set_mdio_emac_per_phy(params->cb, params); 15290 15291 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; 15292 phy_index++) { 15293 switch (params->phy[phy_index].type) { 15294 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 15295 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 15296 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 15297 elink_cl45_write(params->cb, ¶ms->phy[phy_index], 15298 MDIO_PMA_DEVAD, 15299 MDIO_PMA_REG_TX_DISABLE, 0); 15300 default: 15301 break; 15302 } 15303 } 15304 } 15305 #endif // ELINK_AUX_POWER 15306 15307 void elink_hw_reset_phy(struct elink_params *params) 15308 { 15309 u8 phy_index; 15310 struct elink_dev *cb = params->cb; 15311 elink_update_mng(params, 0); 15312 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 15313 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 15314 ELINK_NIG_MASK_XGXS0_LINK10G | 15315 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 15316 ELINK_NIG_MASK_MI_INT)); 15317 15318 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; 15319 phy_index++) { 15320 if (params->phy[phy_index].hw_reset) { 15321 params->phy[phy_index].hw_reset( 15322 ¶ms->phy[phy_index], 15323 params); 15324 params->phy[phy_index] = phy_null; 15325 } 15326 } 15327 } 15328 15329 #ifdef ELINK_ENHANCEMENTS 15330 void elink_init_mod_abs_int(struct elink_dev *cb, struct elink_vars *vars, 15331 u32 chip_id, u32 shmem_base, u32 shmem2_base, 15332 u8 port) 15333 { 15334 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index; 15335 u32 val; 15336 u32 offset, aeu_mask, swap_val, swap_override, sync_offset; 15337 if (CHIP_IS_E3(chip_id)) { 15338 if (elink_get_mod_abs_int_cfg(cb, chip_id, 15339 shmem_base, 15340 port, 15341 &gpio_num, 15342 &gpio_port) != ELINK_STATUS_OK) 15343 return; 15344 } else { 15345 struct elink_phy phy; 15346 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; 15347 phy_index++) { 15348 if (elink_populate_phy(cb, phy_index, shmem_base, 15349 shmem2_base, port, &phy) 15350 != ELINK_STATUS_OK) { 15351 ELINK_DEBUG_P0(cb, "populate phy failed\n"); 15352 return; 15353 } 15354 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { 15355 gpio_num = MISC_REGISTERS_GPIO_3; 15356 gpio_port = port; 15357 break; 15358 } 15359 } 15360 } 15361 15362 if (gpio_num == 0xff) 15363 return; 15364 15365 /* Set GPIO3 to trigger SFP+ module insertion/removal */ 15366 ELINK_SET_GPIO(cb, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); 15367 15368 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP); 15369 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE); 15370 gpio_port ^= (swap_val && swap_override); 15371 15372 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << 15373 (gpio_num + (gpio_port << 2)); 15374 15375 sync_offset = shmem_base + 15376 OFFSETOF(struct shmem_region, 15377 dev_info.port_hw_config[port].aeu_int_mask); 15378 REG_WR(cb, sync_offset, vars->aeu_int_mask); 15379 15380 ELINK_DEBUG_P3(cb, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", 15381 gpio_num, gpio_port, vars->aeu_int_mask); 15382 15383 if (port == 0) 15384 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; 15385 else 15386 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; 15387 15388 /* Open appropriate AEU for interrupts */ 15389 aeu_mask = REG_RD(cb, offset); 15390 aeu_mask |= vars->aeu_int_mask; 15391 REG_WR(cb, offset, aeu_mask); 15392 15393 /* Enable the GPIO to trigger interrupt */ 15394 val = REG_RD(cb, MISC_REG_GPIO_EVENT_EN); 15395 val |= 1 << (gpio_num + (gpio_port << 2)); 15396 REG_WR(cb, MISC_REG_GPIO_EVENT_EN, val); 15397 } 15398 #endif // ELINK_ENHANCEMENTS 15399 #endif // EXCLUDE_NON_COMMON_INIT 15400 15401 #ifdef ELINK_AUX_POWER 15402 void elink_adjust_phy_func_ptr(struct elink_params *params) 15403 { 15404 u32 phy_idx; 15405 struct elink_phy phy, *cur_phy; 15406 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 15407 cur_phy = ¶ms->phy[phy_idx]; 15408 /* Select the phy type */ 15409 switch (cur_phy->type) { 15410 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 15411 #ifndef EXCLUDE_WARPCORE 15412 phy = phy_warpcore; 15413 #else 15414 phy = phy_xgxs; 15415 #endif 15416 break; 15417 #ifndef EXCLUDE_BCM8727_BCM8073 15418 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 15419 phy = phy_8073; 15420 break; 15421 #endif 15422 #ifndef EXCLUDE_BCM8705 15423 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 15424 phy = phy_8705; 15425 break; 15426 #endif 15427 #ifndef EXCLUDE_BCM87x6 15428 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 15429 phy = phy_8706; 15430 break; 15431 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 15432 phy = phy_8726; 15433 break; 15434 #endif /* EXCLUDE_BCM87x6 */ 15435 #ifndef EXCLUDE_BCM8727_BCM8073 15436 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 15437 phy = phy_8727; 15438 break; 15439 #endif 15440 #ifndef EXCLUDE_BCM8481 15441 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 15442 phy = phy_8481; 15443 break; 15444 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 15445 phy = phy_84823; 15446 break; 15447 #endif 15448 #ifndef EXCLUDE_BCM84833 15449 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 15450 phy = phy_84833; 15451 break; 15452 #endif 15453 #ifndef EXCLUDE_BCM54618SE 15454 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: 15455 phy = phy_54618se; 15456 break; 15457 #endif 15458 #ifndef EXCLUDE_SFX7101 15459 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 15460 phy = phy_7101; 15461 break; 15462 #endif 15463 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 15464 phy = phy_null; 15465 return; 15466 default: 15467 phy = phy_null; 15468 continue; 15469 } 15470 cur_phy->config_init = phy.config_init; 15471 cur_phy->read_status = phy.read_status; 15472 cur_phy->link_reset = phy.link_reset; 15473 cur_phy->config_loopback = phy.config_loopback; 15474 cur_phy->format_fw_ver = phy.format_fw_ver; 15475 cur_phy->hw_reset = phy.hw_reset; 15476 cur_phy->set_link_led = phy.set_link_led; 15477 cur_phy->phy_specific_func = phy.phy_specific_func; 15478 } 15479 } 15480 15481 #ifndef EXCLUDE_COMMON_INIT 15482 elink_status_t elink_get_phy_temperature(struct elink_params *params, 15483 u32 *temp_reading, u8 path, u8 port) 15484 { 15485 /* The temperature returned from this function is expected 15486 * to be degree C. Any conversion from hardware value to 15487 * degree C will be performed here. 15488 */ 15489 15490 struct elink_phy *phy; 15491 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; 15492 elink_status_t rc; 15493 u8 idx; 15494 15495 for (idx = 0; idx < PHY84833_CMDHDLR_MAX_ARGS; idx++) 15496 cmd_args[idx] = 0; 15497 for (idx = 0; idx < params->num_phys; idx++) { 15498 phy = ¶ms->phy[idx]; 15499 if (phy->flags & ELINK_FLAGS_TEMPERATURE) { 15500 rc = elink_84833_cmd_hdlr(phy, params, 15501 PHY84833_CMD_GET_CURRENT_TEMP, 15502 cmd_args, 15503 PHY84833_CMDHDLR_MAX_ARGS); 15504 if ((path == 0) && (cmd_args[1] == 0)) 15505 cmd_args[1] = cmd_args[0] + 5; 15506 if (cmd_args[0] > cmd_args[1]) 15507 *temp_reading = (u32)cmd_args[0]; 15508 else 15509 *temp_reading = (u32)cmd_args[1]; 15510 15511 return rc; 15512 } 15513 } 15514 15515 return ELINK_STATUS_ERROR; 15516 } 15517 #ifndef EXCLUDE_WARPCORE 15518 void set_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 val) 15519 { 15520 elink_set_cfg_pin(cb, pin_cfg, val); 15521 } 15522 int get_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 *val) 15523 { 15524 return elink_get_cfg_pin(cb, pin_cfg, val); 15525 } 15526 15527 void elink_force_link(struct elink_params *params, int enable) { 15528 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; 15529 struct elink_dev *cb = params->cb; 15530 u8 lane = elink_get_warpcore_lane(phy, params); 15531 u16 val; 15532 15533 /* Global register - operate on lane 0 */ 15534 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 15535 MDIO_AER_BLOCK_AER_REG, 0); 15536 15537 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 15538 MDIO_WC_REG_XGXSBLK2_LANE_RESET, &val); 15539 if (enable) 15540 val &= ~(0x11 << lane); 15541 else 15542 val |= (0x11 << lane); 15543 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 15544 MDIO_WC_REG_XGXSBLK2_LANE_RESET, 15545 val); 15546 15547 /* Restore AER */ 15548 elink_set_aer_mmd(params, phy); 15549 } 15550 15551 #endif /* EXCLUDE_WARPCORE */ 15552 #endif /* #ifndef EXCLUDE_COMMON_INIT */ 15553 #endif 15554