1 /* 2 * Copyright 2014-2017 Cavium, Inc. 3 * The contents of this file are subject to the terms of the Common Development 4 * and Distribution License, v.1, (the "License"). 5 * 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the License at available 9 * at http://opensource.org/licenses/CDDL-1.0 10 * 11 * See the License for the specific language governing permissions and 12 * limitations under the License. 13 */ 14 15 /* 16 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 17 * Copyright (c) 2019, Joyent, Inc. 18 */ 19 20 #ifndef _BNX_H 21 #define _BNX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #include <sys/types.h> 28 #include <sys/stream.h> 29 #include <sys/stropts.h> 30 #include <sys/errno.h> 31 #include <sys/cred.h> 32 #include <sys/poll.h> 33 #include <sys/modctl.h> 34 #ifdef __10u7 35 #include <sys/mac.h> 36 #else 37 #include <sys/mac_provider.h> 38 #endif 39 #include <sys/stat.h> 40 #include <sys/ddi.h> 41 #include <sys/sunddi.h> 42 #include <sys/pattr.h> 43 #include <sys/sysmacros.h> 44 #include <sys/ethernet.h> 45 #include <sys/strsun.h> 46 #include <netinet/in.h> 47 #include <netinet/ip.h> 48 #include <netinet/udp.h> 49 #include <inet/common.h> 50 #include <inet/ip.h> 51 #include <inet/ip_if.h> 52 #include <sys/strsubr.h> 53 #include <sys/pci.h> 54 #include <sys/kstat.h> 55 56 57 58 /* 59 */ 60 #pragma weak hcksum_retrieve 61 #pragma weak hcksum_assoc 62 63 64 #include "listq.h" 65 #include "lm5706.h" 66 #include "54xx_reg.h" 67 68 #define BNX_MAGIC 0x0feedead 69 #define BNX_STR_SIZE 32 70 71 #ifdef __sparc 72 #define BNX_DMA_ALIGNMENT 0x2000UL 73 #else 74 #define BNX_DMA_ALIGNMENT 0x1000UL 75 #endif 76 77 #define BNX_MAX_SGL_ENTRIES 16 78 #define BNX_MIN_BYTES_PER_FRAGMENT 32 79 80 #define FW_VER_WITH_UNLOAD_POWER_DOWN 0x01090003 81 82 83 extern ddi_device_acc_attr_t bnxAccessAttribBAR; 84 extern ddi_device_acc_attr_t bnxAccessAttribBUF; 85 extern ddi_dma_attr_t bnx_std_dma_attrib; 86 87 88 typedef struct _bnx_memreq_t { 89 void * addr; 90 size_t size; 91 } bnx_memreq_t; 92 93 94 95 /* 96 * Transmit queue info structure holds information regarding transmit resources. 97 * This consists of two list, one is a free list of transmit packets and another 98 * a list of pending packets (packets posted to ASIC for transmit). Upon 99 * receiving transmit complete notification from the asic, the message blocks 100 * are freed and and packet structure is moved to the free list. 101 */ 102 103 typedef struct _um_xmit_qinfo { 104 ddi_dma_handle_t dcpyhndl; 105 ddi_acc_handle_t dcpyahdl; 106 caddr_t dcpyvirt; 107 lm_u64_t dcpyphys; 108 size_t dcpyhard; 109 110 /* Packet descriptor memory. */ 111 u32_t desc_cnt; 112 bnx_memreq_t desc_mem; 113 114 /* Low resource water marks. */ 115 u32_t thresh_pdwm; 116 117 /* Free queue mutex */ 118 kmutex_t free_mutex; 119 120 /* Packet descriptors that are free for use. */ 121 s_list_t free_tx_desc; 122 123 /* Packet descriptors that have been setup and are awaiting xmit. */ 124 s_list_t tx_resc_que; 125 } um_xmit_qinfo; 126 127 128 129 /* 130 * Receive queue is mostly managed by the LM (lm_dev->rx_info.chain[]). 131 * During initialization, UM allocates receive buffers and prepares the 132 * rx descriptions to posts the receive buffers. 133 */ 134 typedef struct _um_recv_qinfo { 135 volatile boolean_t processing; 136 137 /* For packet descriptors that do not have rx buffers assigned. */ 138 s_list_t buffq; 139 140 /* For packet descriptors waiting to be sent up. */ 141 s_list_t waitq; 142 } um_recv_qinfo; 143 144 145 typedef struct _os_param { 146 u32_t active_resc_flag; 147 #define DRV_RESOURCE_PCICFG_MAPPED 0x0001 148 #define DRV_RESOURCE_MAP_REGS 0x0002 149 #define DRV_RESOURCE_INTR_1 0x0004 150 #define DRV_RESOURCE_MUTEX 0x0008 151 #define DRV_RESOURCE_HDWR_REGISTER 0x0020 152 #define DRV_RESOURCE_GLD_REGISTER 0x0040 153 #define DRV_RESOURCE_KSTAT 0x0080 154 #define DRV_RESOURCE_TIMER 0x0100 155 #define DRV_RESOURCE_MINOR_NODE 0x0200 156 #define DRV_LINK_TIMEOUT_CB 0x0400 157 158 dev_info_t *dip; 159 160 ddi_acc_handle_t pci_cfg_handle; 161 ddi_acc_handle_t reg_acc_handle; 162 163 mac_handle_t macp; 164 mac_resource_handle_t rx_resc_handle[NUM_RX_CHAIN]; 165 caddr_t regs_addr; 166 167 kmutex_t gld_mutex; 168 krwlock_t gld_snd_mutex; 169 kmutex_t xmit_mutex; 170 kmutex_t rcv_mutex; 171 kmutex_t phy_mutex; 172 kmutex_t ind_mutex; 173 174 /* 175 * Following are generic DMA handles used for the following - 176 * 1. Status _ Statistic DMA memory 177 * 2. TXBD queue 178 * 3. RXBD queue 179 */ 180 #define BNX_MAX_PHYS_MEMREQS 32 181 u32_t dma_handles_used; 182 void *dma_virt[BNX_MAX_PHYS_MEMREQS]; 183 ddi_dma_handle_t dma_handle[BNX_MAX_PHYS_MEMREQS]; 184 ddi_acc_handle_t dma_acc_handle[BNX_MAX_PHYS_MEMREQS]; 185 186 ddi_dma_handle_t *status_block_dma_hdl; 187 188 } os_param_t; 189 190 191 192 193 /* 194 * Following structure hosts attributes related to the device, like media type, 195 * transmit/receive descriptor queue information, last status index 196 * processed/acknowledged, etc' 197 */ 198 199 typedef struct _dev_param { 200 201 u32_t mtu; 202 203 lm_rx_mask_t rx_filter_mask; 204 lm_offload_t enabled_oflds; 205 206 /* 207 * This is the last value of 'status_idx' processed and acknowledged 208 * by the driver. This value is compared with current value in the 209 * status block to determine if new status block was generated by 210 * host coalesce block. 211 */ 212 u32_t processed_status_idx; 213 214 u32_t fw_ver; 215 216 boolean_t isfiber; 217 218 boolean_t disableMsix; 219 220 lm_status_t indLink; 221 lm_medium_t indMedium; 222 } device_param_t; 223 224 225 typedef struct _bnx_ndd_lnk_tbl_t { 226 const char **label; 227 const boolean_t *value; 228 } bnx_ndd_lnk_tbl_t; 229 230 231 /* NDD parameters related structure members. */ 232 typedef struct _bnx_ndd_t { 233 caddr_t ndd_data; 234 235 bnx_ndd_lnk_tbl_t lnktbl[3]; 236 237 int link_speed; 238 boolean_t link_duplex; 239 boolean_t link_tx_pause; 240 boolean_t link_rx_pause; 241 } bnx_ndd_t; 242 243 244 typedef struct _bnx_lnk_cfg_t { 245 boolean_t link_autoneg; 246 boolean_t param_2500fdx; 247 boolean_t param_1000fdx; 248 boolean_t param_1000hdx; 249 boolean_t param_100fdx; 250 boolean_t param_100hdx; 251 boolean_t param_10fdx; 252 boolean_t param_10hdx; 253 boolean_t param_tx_pause; 254 boolean_t param_rx_pause; 255 } bnx_lnk_cfg_t; 256 257 258 259 typedef struct _bnx_phy_cfg_t { 260 bnx_lnk_cfg_t lnkcfg; 261 262 boolean_t flow_autoneg; 263 boolean_t wirespeed; 264 } bnx_phy_cfg_t; 265 266 267 268 typedef struct _um_device { 269 /* Lower Module device structure should be the first element */ 270 struct _lm_device_t lm_dev; 271 272 u32_t magic; 273 274 ddi_intr_handle_t *pIntrBlock; 275 u32_t intrPriority; 276 int intrType; 277 278 volatile boolean_t intr_enabled; 279 kmutex_t intr_mutex; 280 uint32_t intr_count; 281 uint32_t intr_no_change; 282 uint32_t intr_in_disabled; 283 284 volatile boolean_t timer_enabled; 285 kmutex_t tmr_mutex; 286 timeout_id_t tmrtid; 287 unsigned int timer_link_check_interval; 288 unsigned int timer_link_check_counter; 289 unsigned int timer_link_check_interval2; 290 unsigned int timer_link_check_counter2; 291 292 volatile boolean_t dev_start; 293 volatile boolean_t link_updates_ok; 294 295 os_param_t os_param; 296 device_param_t dev_var; 297 298 u32_t tx_copy_threshold; 299 300 u32_t no_tx_credits; 301 #define BNX_TX_RESOURCES_NO_CREDIT 0x01 302 #define BNX_TX_RESOURCES_NO_DESC 0x02 303 /* Unable to allocate DMA resources. (e.g. bind error) */ 304 #define BNX_TX_RESOURCES_NO_OS_DMA_RES 0x08 305 #define BNX_TX_RESOURCES_TOO_MANY_FRAGS 0x10 306 307 um_xmit_qinfo txq[NUM_TX_CHAIN]; 308 #define _TX_QINFO(pdev, chain) (pdev->txq[chain]) 309 #define _TXQ_FREE_DESC(pdev, chain) (pdev->txq[chain].free_tx_desc) 310 #define _TXQ_RESC_DESC(pdev, chain) (pdev->txq[chain].tx_resc_que) 311 312 u32_t rx_copy_threshold; 313 uint32_t recv_discards; 314 315 um_recv_qinfo rxq[NUM_RX_CHAIN]; 316 #define _RX_QINFO(pdev, chain) (pdev->rxq[chain]) 317 318 bnx_ndd_t nddcfg; 319 320 bnx_phy_cfg_t hwinit; 321 bnx_phy_cfg_t curcfg; 322 bnx_lnk_cfg_t remote; 323 324 char dev_name[BNX_STR_SIZE]; 325 int instance; 326 char version[BNX_STR_SIZE]; 327 char versionFW[BNX_STR_SIZE]; 328 char chipName[BNX_STR_SIZE]; 329 char intrAlloc[BNX_STR_SIZE]; 330 u64_t intrFired; 331 332 kstat_t *kstats; 333 kmutex_t kstatMutex; 334 335 #define BNX_MAX_MEMREQS 2 336 unsigned int memcnt; 337 bnx_memreq_t memreq[BNX_MAX_MEMREQS]; 338 } um_device_t; 339 340 341 342 /* 343 * Following structure defines the packet descriptor as seen by the UM module. 344 * This is used to map buffers to lm_packet on xmit path and receive path. 345 */ 346 347 typedef struct _um_txpacket_t { 348 /* Must be the first entry in this structure. */ 349 struct _lm_packet_t lm_pkt; 350 351 mblk_t *mp; 352 353 ddi_dma_handle_t *cpyhdl; 354 caddr_t cpymem; 355 lm_u64_t cpyphy; 356 off_t cpyoff; 357 358 u32_t num_handles; 359 ddi_dma_handle_t dma_handle[BNX_MAX_SGL_ENTRIES]; 360 361 lm_frag_list_t frag_list; 362 lm_frag_t frag_list_buffer[BNX_MAX_SGL_ENTRIES]; 363 } um_txpacket_t; 364 365 366 367 #define BNX_RECV_MAX_FRAGS 1 368 typedef struct _um_rxpacket_t { 369 /* Must be the first entry in this structure. */ 370 struct _lm_packet_t lmpacket; 371 372 ddi_dma_handle_t dma_handle; 373 ddi_acc_handle_t dma_acc_handle; 374 } um_rxpacket_t; 375 376 377 #define VLAN_TPID 0x8100u 378 #define VLAN_TAGSZ 4 379 #define VLAN_TAG_SIZE 4 380 #define VLAN_VID_MAX 4094 /* 4095 is reserved */ 381 382 383 typedef struct ether_vlan_header vlan_hdr_t; 384 #define DRV_EXTRACT_VLAN_TPID(vhdrp) htons(vhdrp->ether_tpid) 385 #define DRV_EXTRACT_VLAN_TCI(vhdrp) htons(vhdrp->ether_tci) 386 #define DRV_SET_VLAN_TPID(vhdrp, tpid) vhdrp->ether_tpid = htons(tpid) 387 #define DRV_SET_VLAN_TCI(vhdrp, vtag) vhdrp->ether_tci = htons(vtag) 388 389 390 391 392 393 /* 394 * 395 * 'ndd' Get/Set IOCTL Definition 396 * 397 */ 398 399 400 /* 401 * (Internal) return values from ioctl subroutines 402 */ 403 enum ioc_reply { 404 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 405 IOC_DONE, /* OK, reply sent */ 406 IOC_ACK, /* OK, just send ACK */ 407 IOC_REPLY, /* OK, just send reply */ 408 IOC_RESTART_ACK, /* OK, restart & ACK */ 409 IOC_RESTART_REPLY /* OK, restart & reply */ 410 }; 411 412 /* 413 * Function Prototypes 414 * 415 */ 416 417 ddi_dma_handle_t *bnx_find_dma_hdl(um_device_t * const umdevice, 418 const void * const virtaddr); 419 420 void um_send_driver_pulse(um_device_t *udevp); 421 422 int bnx_find_mchash_collision(lm_mc_table_t *mc_table, 423 const u8_t *const mc_addr); 424 425 void bnx_update_phy(um_device_t *pdev); 426 427 428 boolean_t bnx_kstat_init(um_device_t *pUM); 429 void bnx_kstat_fini(um_device_t *pUM); 430 431 #ifdef __cplusplus 432 } 433 #endif 434 435 #endif /* _BNX_H */ 436