1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include "bge_impl.h" 28 29 /* 30 * Bit test macros, returning boolean_t values 31 */ 32 #define BIS(w, b) (((w) & (b)) ? B_TRUE : B_FALSE) 33 #define BIC(w, b) (((w) & (b)) ? B_FALSE : B_TRUE) 34 #define UPORDOWN(x) ((x) ? "up" : "down") 35 36 /* 37 * ========== Copper (PHY) support ========== 38 */ 39 40 #define BGE_DBG BGE_DBG_PHY /* debug flag for this code */ 41 42 /* 43 * #defines: 44 * BGE_COPPER_WIRESPEED controls whether the Broadcom WireSpeed(tm) 45 * feature is enabled. We need to recheck whether this can be 46 * enabled; at one time it seemed to interact unpleasantly with the 47 * loopback modes. 48 * 49 * BGE_COPPER_IDLEOFF controls whether the (copper) PHY power is 50 * turned off when the PHY is idled i.e. during driver suspend(). 51 * For now this is disabled because the chip doesn't seem to 52 * resume cleanly if the PHY power is turned off. 53 */ 54 #define BGE_COPPER_WIRESPEED B_TRUE 55 #define BGE_COPPER_IDLEOFF B_FALSE 56 57 /* 58 * The arrays below can be indexed by the MODE bits from the Auxiliary 59 * Status register to determine the current speed/duplex settings. 60 */ 61 static const int16_t bge_copper_link_speed[] = { 62 0, /* MII_AUX_STATUS_MODE_NONE */ 63 10, /* MII_AUX_STATUS_MODE_10_H */ 64 10, /* MII_AUX_STATUS_MODE_10_F */ 65 100, /* MII_AUX_STATUS_MODE_100_H */ 66 0, /* MII_AUX_STATUS_MODE_100_4 */ 67 100, /* MII_AUX_STATUS_MODE_100_F */ 68 1000, /* MII_AUX_STATUS_MODE_1000_H */ 69 1000 /* MII_AUX_STATUS_MODE_1000_F */ 70 }; 71 72 static const int8_t bge_copper_link_duplex[] = { 73 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_NONE */ 74 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_10_H */ 75 LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_10_F */ 76 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_100_H */ 77 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_100_4 */ 78 LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_100_F */ 79 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_1000_H */ 80 LINK_DUPLEX_FULL /* MII_AUX_STATUS_MODE_1000_F */ 81 }; 82 83 static const int16_t bge_copper_link_speed_5906[] = { 84 0, /* MII_AUX_STATUS_MODE_NONE */ 85 10, /* MII_AUX_STATUS_MODE_10_H */ 86 10, /* MII_AUX_STATUS_MODE_10_F */ 87 100, /* MII_AUX_STATUS_MODE_100_H */ 88 0, /* MII_AUX_STATUS_MODE_100_4 */ 89 100, /* MII_AUX_STATUS_MODE_100_F */ 90 0, /* MII_AUX_STATUS_MODE_1000_H */ 91 0 /* MII_AUX_STATUS_MODE_1000_F */ 92 }; 93 94 static const int8_t bge_copper_link_duplex_5906[] = { 95 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_NONE */ 96 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_10_H */ 97 LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_10_F */ 98 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_100_H */ 99 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_100_4 */ 100 LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_100_F */ 101 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_1000_H */ 102 LINK_DUPLEX_UNKNOWN /* MII_AUX_STATUS_MODE_1000_F */ 103 }; 104 105 #if BGE_DEBUGGING 106 107 static void 108 bge_phydump(bge_t *bgep, uint16_t mii_status, uint16_t aux) 109 { 110 uint16_t regs[32]; 111 int i; 112 113 ASSERT(mutex_owned(bgep->genlock)); 114 115 for (i = 0; i < 32; ++i) 116 switch (i) { 117 default: 118 regs[i] = bge_mii_get16(bgep, i); 119 break; 120 121 case MII_STATUS: 122 regs[i] = mii_status; 123 break; 124 125 case MII_AUX_STATUS: 126 regs[i] = aux; 127 break; 128 129 case 0x0b: case 0x0c: case 0x0d: case 0x0e: 130 case 0x15: case 0x16: case 0x17: 131 case 0x1c: 132 case 0x1f: 133 /* reserved registers -- don't read these */ 134 regs[i] = 0; 135 break; 136 } 137 138 for (i = 0; i < 32; i += 8) 139 BGE_DEBUG(("bge_phydump: " 140 "0x%04x %04x %04x %04x %04x %04x %04x %04x", 141 regs[i+0], regs[i+1], regs[i+2], regs[i+3], 142 regs[i+4], regs[i+5], regs[i+6], regs[i+7])); 143 } 144 145 #endif /* BGE_DEBUGGING */ 146 147 /* 148 * Basic low-level function to probe for a PHY 149 * 150 * Returns TRUE if the PHY responds with valid data, FALSE otherwise 151 */ 152 static boolean_t 153 bge_phy_probe(bge_t *bgep) 154 { 155 uint16_t miicfg; 156 uint32_t nicsig, niccfg; 157 158 BGE_TRACE(("bge_phy_probe($%p)", (void *)bgep)); 159 160 ASSERT(mutex_owned(bgep->genlock)); 161 162 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 163 if (nicsig == BGE_NIC_DATA_SIG) { 164 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 165 switch (niccfg & BGE_NIC_CFG_PHY_TYPE_MASK) { 166 default: 167 case BGE_NIC_CFG_PHY_TYPE_COPPER: 168 return (B_TRUE); 169 case BGE_NIC_CFG_PHY_TYPE_FIBER: 170 return (B_FALSE); 171 } 172 } else { 173 /* 174 * Read the MII_STATUS register twice, in 175 * order to clear any sticky bits (but they should 176 * have been cleared by the RESET, I think). 177 */ 178 miicfg = bge_mii_get16(bgep, MII_STATUS); 179 miicfg = bge_mii_get16(bgep, MII_STATUS); 180 BGE_DEBUG(("bge_phy_probe: status 0x%x", miicfg)); 181 182 /* 183 * Now check the value read; it should have at least one bit set 184 * (for the device capabilities) and at least one clear (one of 185 * the error bits). So if we see all 0s or all 1s, there's a 186 * problem. In particular, bge_mii_get16() returns all 1s if 187 * communications fails ... 188 */ 189 switch (miicfg) { 190 case 0x0000: 191 case 0xffff: 192 return (B_FALSE); 193 194 default : 195 return (B_TRUE); 196 } 197 } 198 } 199 200 /* 201 * Basic low-level function to reset the PHY. 202 * Doesn't incorporate any special-case workarounds. 203 * 204 * Returns TRUE on success, FALSE if the RESET bit doesn't clear 205 */ 206 static boolean_t 207 bge_phy_reset(bge_t *bgep) 208 { 209 uint16_t control; 210 uint_t count; 211 212 BGE_TRACE(("bge_phy_reset($%p)", (void *)bgep)); 213 214 ASSERT(mutex_owned(bgep->genlock)); 215 216 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 217 drv_usecwait(40); 218 /* put PHY into ready state */ 219 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ); 220 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */ 221 drv_usecwait(40); 222 } 223 224 /* 225 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear 226 */ 227 bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_RESET); 228 for (count = 0; ++count < 1000; ) { 229 drv_usecwait(5); 230 control = bge_mii_get16(bgep, MII_CONTROL); 231 if (BIC(control, MII_CONTROL_RESET)) 232 return (B_TRUE); 233 } 234 235 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 236 (void) bge_adj_volt_5906(bgep); 237 238 BGE_DEBUG(("bge_phy_reset: FAILED, control now 0x%x", control)); 239 240 return (B_FALSE); 241 } 242 243 /* 244 * Basic low-level function to powerdown the PHY, if supported 245 * If powerdown support is compiled out, this function does nothing. 246 */ 247 static void 248 bge_phy_powerdown(bge_t *bgep) 249 { 250 BGE_TRACE(("bge_phy_powerdown")); 251 #if BGE_COPPER_IDLEOFF 252 bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_PWRDN); 253 #endif /* BGE_COPPER_IDLEOFF */ 254 } 255 256 /* 257 * The following functions are based on sample code provided by 258 * Broadcom (20-June-2003), and implement workarounds said to be 259 * required on the early revisions of the BCM5703/4C. 260 * 261 * The registers and values used are mostly UNDOCUMENTED, and 262 * therefore don't have symbolic names ;-( 263 * 264 * Many of the comments are straight out of the Broadcom code: 265 * even where the code has been restructured, the original 266 * comments have been preserved in order to explain what these 267 * undocumented registers & values are all about ... 268 */ 269 270 static void 271 bge_phy_macro_wait(bge_t *bgep) 272 { 273 uint_t count; 274 275 for (count = 100; --count; ) 276 if ((bge_mii_get16(bgep, 0x16) & 0x1000) == 0) 277 break; 278 } 279 280 /* 281 * PHY test data pattern: 282 * 283 * For 5703/04, each DFE TAP has 21-bits (low word 15, hi word 6) 284 * For 5705, each DFE TAP has 19-bits (low word 15, hi word 4) 285 * For simplicity, we check only 19-bits, so we don't have to 286 * distinguish which chip it is. 287 * the LO word contains 15 bits, make sure pattern data is < 0x7fff 288 * the HI word contains 6 bits, make sure pattern data is < 0x003f 289 */ 290 #define N_CHANNELS 4 291 #define N_TAPS 3 292 293 static struct { 294 uint16_t lo; 295 uint16_t hi; 296 } tap_data[N_CHANNELS][N_TAPS] = { 297 { 298 { 0x5555, 0x0005 }, /* ch0, TAP 0, LO/HI pattern */ 299 { 0x2aaa, 0x000a }, /* ch0, TAP 1, LO/HI pattern */ 300 { 0x3456, 0x0003 } /* ch0, TAP 2, LO/HI pattern */ 301 }, 302 { 303 { 0x2aaa, 0x000a }, /* ch1, TAP 0, LO/HI pattern */ 304 { 0x3333, 0x0003 }, /* ch1, TAP 1, LO/HI pattern */ 305 { 0x789a, 0x0005 } /* ch1, TAP 2, LO/HI pattern */ 306 }, 307 { 308 { 0x5a5a, 0x0005 }, /* ch2, TAP 0, LO/HI pattern */ 309 { 0x2a6a, 0x000a }, /* ch2, TAP 1, LO/HI pattern */ 310 { 0x1bcd, 0x0003 } /* ch2, TAP 2, LO/HI pattern */ 311 }, 312 { 313 { 0x2a5a, 0x000a }, /* ch3, TAP 0, LO/HI pattern */ 314 { 0x33c3, 0x0003 }, /* ch3, TAP 1, LO/HI pattern */ 315 { 0x2ef1, 0x0005 } /* ch3, TAP 2, LO/HI pattern */ 316 } 317 }; 318 319 /* 320 * Check whether the PHY has locked up after a RESET. 321 * 322 * Returns TRUE if it did, FALSE is it's OK ;-) 323 */ 324 static boolean_t 325 bge_phy_locked_up(bge_t *bgep) 326 { 327 uint16_t dataLo; 328 uint16_t dataHi; 329 uint_t chan; 330 uint_t tap; 331 332 /* 333 * Check TAPs for all 4 channels, as soon as we see a lockup 334 * we'll stop checking. 335 */ 336 for (chan = 0; chan < N_CHANNELS; ++chan) { 337 /* Select channel and set TAP index to 0 */ 338 bge_mii_put16(bgep, 0x17, (chan << 13) | 0x0200); 339 /* Freeze filter again just to be safe */ 340 bge_mii_put16(bgep, 0x16, 0x0002); 341 342 /* 343 * Write fixed pattern to the RAM, 3 TAPs for 344 * each channel, each TAP have 2 WORDs (LO/HI) 345 */ 346 for (tap = 0; tap < N_TAPS; ++tap) { 347 bge_mii_put16(bgep, 0x15, tap_data[chan][tap].lo); 348 bge_mii_put16(bgep, 0x15, tap_data[chan][tap].hi); 349 } 350 351 /* 352 * Active PHY's Macro operation to write DFE 353 * TAP from RAM, and wait for Macro to complete. 354 */ 355 bge_mii_put16(bgep, 0x16, 0x0202); 356 bge_phy_macro_wait(bgep); 357 358 /* 359 * Done with write phase, now begin read phase. 360 */ 361 362 /* Select channel and set TAP index to 0 */ 363 bge_mii_put16(bgep, 0x17, (chan << 13) | 0x0200); 364 365 /* 366 * Active PHY's Macro operation to load DFE 367 * TAP to RAM, and wait for Macro to complete 368 */ 369 bge_mii_put16(bgep, 0x16, 0x0082); 370 bge_phy_macro_wait(bgep); 371 372 /* Enable "pre-fetch" */ 373 bge_mii_put16(bgep, 0x16, 0x0802); 374 bge_phy_macro_wait(bgep); 375 376 /* 377 * Read back the TAP values. 3 TAPs for each 378 * channel, each TAP have 2 WORDs (LO/HI) 379 */ 380 for (tap = 0; tap < N_TAPS; ++tap) { 381 /* 382 * Read Lo/Hi then wait for 'done' is faster. 383 * For DFE TAP, the HI word contains 6 bits, 384 * LO word contains 15 bits 385 */ 386 dataLo = bge_mii_get16(bgep, 0x15) & 0x7fff; 387 dataHi = bge_mii_get16(bgep, 0x15) & 0x003f; 388 bge_phy_macro_wait(bgep); 389 390 /* 391 * Check if what we wrote is what we read back. 392 * If failed, then the PHY is locked up, we need 393 * to do PHY reset again 394 */ 395 if (dataLo != tap_data[chan][tap].lo) 396 return (B_TRUE); /* wedged! */ 397 398 if (dataHi != tap_data[chan][tap].hi) 399 return (B_TRUE); /* wedged! */ 400 } 401 } 402 403 /* 404 * The PHY isn't locked up ;-) 405 */ 406 return (B_FALSE); 407 } 408 409 /* 410 * Special-case code to reset the PHY on the 5702/5703/5704C/5705/5782. 411 * Tries up to 5 times to recover from failure to reset or PHY lockup. 412 * 413 * Returns TRUE on success, FALSE if there's an unrecoverable problem 414 */ 415 static boolean_t 416 bge_phy_reset_and_check(bge_t *bgep) 417 { 418 boolean_t reset_success; 419 boolean_t phy_locked; 420 uint16_t extctrl; 421 uint_t retries; 422 423 for (retries = 0; retries < 5; ++retries) { 424 /* Issue a phy reset, and wait for reset to complete */ 425 /* Assuming reset is successful first */ 426 reset_success = bge_phy_reset(bgep); 427 428 /* 429 * Now go check the DFE TAPs to see if locked up, but 430 * first, we need to set up PHY so we can read DFE 431 * TAPs. 432 */ 433 434 /* 435 * Disable Transmitter and Interrupt, while we play 436 * with the PHY registers, so the link partner won't 437 * see any strange data and the Driver won't see any 438 * interrupts. 439 */ 440 extctrl = bge_mii_get16(bgep, 0x10); 441 bge_mii_put16(bgep, 0x10, extctrl | 0x3000); 442 443 /* Setup Full-Duplex, 1000 mbps */ 444 bge_mii_put16(bgep, 0x0, 0x0140); 445 446 /* Set to Master mode */ 447 bge_mii_put16(bgep, 0x9, 0x1800); 448 449 /* Enable SM_DSP_CLOCK & 6dB */ 450 bge_mii_put16(bgep, 0x18, 0x0c00); /* "the ADC fix" */ 451 452 /* Work-arounds */ 453 bge_mii_put16(bgep, 0x17, 0x201f); 454 bge_mii_put16(bgep, 0x15, 0x2aaa); 455 456 /* More workarounds */ 457 bge_mii_put16(bgep, 0x17, 0x000a); 458 bge_mii_put16(bgep, 0x15, 0x0323); /* "the Gamma fix" */ 459 460 /* Blocks the PHY control access */ 461 bge_mii_put16(bgep, 0x17, 0x8005); 462 bge_mii_put16(bgep, 0x15, 0x0800); 463 464 /* Test whether PHY locked up ;-( */ 465 phy_locked = bge_phy_locked_up(bgep); 466 if (reset_success && !phy_locked) 467 break; 468 469 /* 470 * Some problem here ... log it & retry 471 */ 472 if (!reset_success) 473 BGE_REPORT((bgep, "PHY didn't reset!")); 474 if (phy_locked) 475 BGE_REPORT((bgep, "PHY locked up!")); 476 } 477 478 /* Remove block phy control */ 479 bge_mii_put16(bgep, 0x17, 0x8005); 480 bge_mii_put16(bgep, 0x15, 0x0000); 481 482 /* Unfreeze DFE TAP filter for all channels */ 483 bge_mii_put16(bgep, 0x17, 0x8200); 484 bge_mii_put16(bgep, 0x16, 0x0000); 485 486 /* Restore PHY back to operating state */ 487 bge_mii_put16(bgep, 0x18, 0x0400); 488 489 /* Enable transmitter and interrupt */ 490 extctrl = bge_mii_get16(bgep, 0x10); 491 bge_mii_put16(bgep, 0x10, extctrl & ~0x3000); 492 493 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 494 (void) bge_adj_volt_5906(bgep); 495 496 if (!reset_success) 497 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 498 else if (phy_locked) 499 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 500 return (reset_success && !phy_locked); 501 } 502 503 static void 504 bge_phy_tweak_gmii(bge_t *bgep) 505 { 506 /* Tweak GMII timing */ 507 bge_mii_put16(bgep, 0x1c, 0x8d68); 508 bge_mii_put16(bgep, 0x1c, 0x8d68); 509 } 510 511 /* Bit Error Rate reduction fix */ 512 static void 513 bge_phy_bit_err_fix(bge_t *bgep) 514 { 515 bge_mii_put16(bgep, 0x18, 0x0c00); 516 bge_mii_put16(bgep, 0x17, 0x000a); 517 bge_mii_put16(bgep, 0x15, 0x310b); 518 bge_mii_put16(bgep, 0x17, 0x201f); 519 bge_mii_put16(bgep, 0x15, 0x9506); 520 bge_mii_put16(bgep, 0x17, 0x401f); 521 bge_mii_put16(bgep, 0x15, 0x14e2); 522 bge_mii_put16(bgep, 0x18, 0x0400); 523 } 524 525 /* 526 * End of Broadcom-derived workaround code * 527 */ 528 529 static int 530 bge_restart_copper(bge_t *bgep, boolean_t powerdown) 531 { 532 uint16_t phy_status; 533 boolean_t reset_ok; 534 uint16_t extctrl, auxctrl; 535 536 BGE_TRACE(("bge_restart_copper($%p, %d)", (void *)bgep, powerdown)); 537 538 ASSERT(mutex_owned(bgep->genlock)); 539 540 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 541 default: 542 /* 543 * Shouldn't happen; it means we don't recognise this chip. 544 * It's probably a new one, so we'll try our best anyway ... 545 */ 546 case MHCR_CHIP_ASIC_REV_5703: 547 case MHCR_CHIP_ASIC_REV_5704: 548 case MHCR_CHIP_ASIC_REV_5705: 549 case MHCR_CHIP_ASIC_REV_5752: 550 case MHCR_CHIP_ASIC_REV_5714: 551 case MHCR_CHIP_ASIC_REV_5715: 552 reset_ok = bge_phy_reset_and_check(bgep); 553 break; 554 555 case MHCR_CHIP_ASIC_REV_5906: 556 case MHCR_CHIP_ASIC_REV_5700: 557 case MHCR_CHIP_ASIC_REV_5701: 558 case MHCR_CHIP_ASIC_REV_5723: 559 case MHCR_CHIP_ASIC_REV_5721_5751: 560 /* 561 * Just a plain reset; the "check" code breaks these chips 562 */ 563 reset_ok = bge_phy_reset(bgep); 564 if (!reset_ok) 565 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 566 break; 567 } 568 if (!reset_ok) { 569 BGE_REPORT((bgep, "PHY failed to reset correctly")); 570 return (DDI_FAILURE); 571 } 572 573 /* 574 * Step 5: disable WOL (not required after RESET) 575 * 576 * Step 6: refer to errata 577 */ 578 switch (bgep->chipid.asic_rev) { 579 default: 580 break; 581 582 case MHCR_CHIP_REV_5704_A0: 583 bge_phy_tweak_gmii(bgep); 584 break; 585 } 586 587 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 588 case MHCR_CHIP_ASIC_REV_5705: 589 case MHCR_CHIP_ASIC_REV_5721_5751: 590 bge_phy_bit_err_fix(bgep); 591 break; 592 } 593 594 if (!(bgep->chipid.flags & CHIP_FLAG_NO_JUMBO) && 595 (bgep->chipid.default_mtu > BGE_DEFAULT_MTU)) { 596 /* Set the GMII Fifo Elasticity to high latency */ 597 extctrl = bge_mii_get16(bgep, 0x10); 598 bge_mii_put16(bgep, 0x10, extctrl | 0x1); 599 600 /* Allow reception of extended length packets */ 601 bge_mii_put16(bgep, MII_AUX_CONTROL, 0x0007); 602 auxctrl = bge_mii_get16(bgep, MII_AUX_CONTROL); 603 auxctrl |= 0x4000; 604 bge_mii_put16(bgep, MII_AUX_CONTROL, auxctrl); 605 } 606 607 /* 608 * Step 7: read the MII_INTR_STATUS register twice, 609 * in order to clear any sticky bits (but they should 610 * have been cleared by the RESET, I think), and we're 611 * not using PHY interrupts anyway. 612 * 613 * Step 8: enable the PHY to interrupt on link status 614 * change (not required) 615 * 616 * Step 9: configure PHY LED Mode - not applicable? 617 * 618 * Step 10: read the MII_STATUS register twice, in 619 * order to clear any sticky bits (but they should 620 * have been cleared by the RESET, I think). 621 */ 622 phy_status = bge_mii_get16(bgep, MII_STATUS); 623 phy_status = bge_mii_get16(bgep, MII_STATUS); 624 BGE_DEBUG(("bge_restart_copper: status 0x%x", phy_status)); 625 626 /* 627 * Finally, shut down the PHY, if required 628 */ 629 if (powerdown) 630 bge_phy_powerdown(bgep); 631 return (DDI_SUCCESS); 632 } 633 634 /* 635 * Synchronise the (copper) PHY's speed/duplex/autonegotiation capabilities 636 * and advertisements with the required settings as specified by the various 637 * param_* variables that can be poked via the NDD interface. 638 * 639 * We always reset the PHY and reprogram *all* the relevant registers, 640 * not just those changed. This should cause the link to go down, and then 641 * back up again once the link is stable and autonegotiation (if enabled) 642 * is complete. We should get a link state change interrupt somewhere along 643 * the way ... 644 * 645 * NOTE: <genlock> must already be held by the caller 646 */ 647 static int 648 bge_update_copper(bge_t *bgep) 649 { 650 boolean_t adv_autoneg; 651 boolean_t adv_pause; 652 boolean_t adv_asym_pause; 653 boolean_t adv_1000fdx; 654 boolean_t adv_1000hdx; 655 boolean_t adv_100fdx; 656 boolean_t adv_100hdx; 657 boolean_t adv_10fdx; 658 boolean_t adv_10hdx; 659 660 uint16_t control; 661 uint16_t gigctrl; 662 uint16_t auxctrl; 663 uint16_t anar; 664 665 BGE_TRACE(("bge_update_copper($%p)", (void *)bgep)); 666 667 ASSERT(mutex_owned(bgep->genlock)); 668 669 BGE_DEBUG(("bge_update_copper: autoneg %d " 670 "pause %d asym_pause %d " 671 "1000fdx %d 1000hdx %d " 672 "100fdx %d 100hdx %d " 673 "10fdx %d 10hdx %d ", 674 bgep->param_adv_autoneg, 675 bgep->param_adv_pause, bgep->param_adv_asym_pause, 676 bgep->param_adv_1000fdx, bgep->param_adv_1000hdx, 677 bgep->param_adv_100fdx, bgep->param_adv_100hdx, 678 bgep->param_adv_10fdx, bgep->param_adv_10hdx)); 679 680 control = gigctrl = auxctrl = anar = 0; 681 682 /* 683 * PHY settings are normally based on the param_* variables, 684 * but if any loopback mode is in effect, that takes precedence. 685 * 686 * BGE supports MAC-internal loopback, PHY-internal loopback, 687 * and External loopback at a variety of speeds (with a special 688 * cable). In all cases, autoneg is turned OFF, full-duplex 689 * is turned ON, and the speed/mastership is forced. 690 */ 691 switch (bgep->param_loop_mode) { 692 case BGE_LOOP_NONE: 693 default: 694 adv_autoneg = bgep->param_adv_autoneg; 695 adv_pause = bgep->param_adv_pause; 696 adv_asym_pause = bgep->param_adv_asym_pause; 697 adv_1000fdx = bgep->param_adv_1000fdx; 698 adv_1000hdx = bgep->param_adv_1000hdx; 699 adv_100fdx = bgep->param_adv_100fdx; 700 adv_100hdx = bgep->param_adv_100hdx; 701 adv_10fdx = bgep->param_adv_10fdx; 702 adv_10hdx = bgep->param_adv_10hdx; 703 break; 704 705 case BGE_LOOP_EXTERNAL_1000: 706 case BGE_LOOP_EXTERNAL_100: 707 case BGE_LOOP_EXTERNAL_10: 708 case BGE_LOOP_INTERNAL_PHY: 709 case BGE_LOOP_INTERNAL_MAC: 710 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 711 adv_1000fdx = adv_100fdx = adv_10fdx = B_FALSE; 712 adv_1000hdx = adv_100hdx = adv_10hdx = B_FALSE; 713 bgep->param_link_duplex = LINK_DUPLEX_FULL; 714 715 switch (bgep->param_loop_mode) { 716 case BGE_LOOP_EXTERNAL_1000: 717 bgep->param_link_speed = 1000; 718 adv_1000fdx = B_TRUE; 719 auxctrl = MII_AUX_CTRL_NORM_EXT_LOOPBACK; 720 gigctrl |= MII_MSCONTROL_MANUAL; 721 gigctrl |= MII_MSCONTROL_MASTER; 722 break; 723 724 case BGE_LOOP_EXTERNAL_100: 725 bgep->param_link_speed = 100; 726 adv_100fdx = B_TRUE; 727 auxctrl = MII_AUX_CTRL_NORM_EXT_LOOPBACK; 728 break; 729 730 case BGE_LOOP_EXTERNAL_10: 731 bgep->param_link_speed = 10; 732 adv_10fdx = B_TRUE; 733 auxctrl = MII_AUX_CTRL_NORM_EXT_LOOPBACK; 734 break; 735 736 case BGE_LOOP_INTERNAL_PHY: 737 bgep->param_link_speed = 1000; 738 adv_1000fdx = B_TRUE; 739 control = MII_CONTROL_LOOPBACK; 740 break; 741 742 case BGE_LOOP_INTERNAL_MAC: 743 bgep->param_link_speed = 1000; 744 adv_1000fdx = B_TRUE; 745 break; 746 } 747 } 748 749 BGE_DEBUG(("bge_update_copper: autoneg %d " 750 "pause %d asym_pause %d " 751 "1000fdx %d 1000hdx %d " 752 "100fdx %d 100hdx %d " 753 "10fdx %d 10hdx %d ", 754 adv_autoneg, 755 adv_pause, adv_asym_pause, 756 adv_1000fdx, adv_1000hdx, 757 adv_100fdx, adv_100hdx, 758 adv_10fdx, adv_10hdx)); 759 760 /* 761 * We should have at least one technology capability set; 762 * if not, we select a default of 1000Mb/s full-duplex 763 */ 764 if (!adv_1000fdx && !adv_100fdx && !adv_10fdx && 765 !adv_1000hdx && !adv_100hdx && !adv_10hdx) 766 adv_1000fdx = B_TRUE; 767 768 /* 769 * Now transform the adv_* variables into the proper settings 770 * of the PHY registers ... 771 * 772 * If autonegotiation is (now) enabled, we want to trigger 773 * a new autonegotiation cycle once the PHY has been 774 * programmed with the capabilities to be advertised. 775 */ 776 if (adv_autoneg) 777 control |= MII_CONTROL_ANE|MII_CONTROL_RSAN; 778 779 if (adv_1000fdx) 780 control |= MII_CONTROL_1GB|MII_CONTROL_FDUPLEX; 781 else if (adv_1000hdx) 782 control |= MII_CONTROL_1GB; 783 else if (adv_100fdx) 784 control |= MII_CONTROL_100MB|MII_CONTROL_FDUPLEX; 785 else if (adv_100hdx) 786 control |= MII_CONTROL_100MB; 787 else if (adv_10fdx) 788 control |= MII_CONTROL_FDUPLEX; 789 else if (adv_10hdx) 790 control |= 0; 791 else 792 { _NOTE(EMPTY); } /* Can't get here anyway ... */ 793 794 if (adv_1000fdx) 795 gigctrl |= MII_MSCONTROL_1000T_FD; 796 if (adv_1000hdx) 797 gigctrl |= MII_MSCONTROL_1000T; 798 799 if (adv_100fdx) 800 anar |= MII_ABILITY_100BASE_TX_FD; 801 if (adv_100hdx) 802 anar |= MII_ABILITY_100BASE_TX; 803 if (adv_10fdx) 804 anar |= MII_ABILITY_10BASE_T_FD; 805 if (adv_10hdx) 806 anar |= MII_ABILITY_10BASE_T; 807 808 if (adv_pause) 809 anar |= MII_ABILITY_PAUSE; 810 if (adv_asym_pause) 811 anar |= MII_ABILITY_ASMPAUSE; 812 813 /* 814 * Munge in any other fixed bits we require ... 815 */ 816 anar |= MII_AN_SELECTOR_8023; 817 auxctrl |= MII_AUX_CTRL_NORM_TX_MODE; 818 auxctrl |= MII_AUX_CTRL_NORMAL; 819 820 /* 821 * Restart the PHY and write the new values. Note the 822 * time, so that we can say whether subsequent link state 823 * changes can be attributed to our reprogramming the PHY 824 */ 825 if ((*bgep->physops->phys_restart)(bgep, B_FALSE) == DDI_FAILURE) 826 return (DDI_FAILURE); 827 bge_mii_put16(bgep, MII_AN_ADVERT, anar); 828 bge_mii_put16(bgep, MII_CONTROL, control); 829 if (auxctrl & MII_AUX_CTRL_NORM_EXT_LOOPBACK) 830 bge_mii_put16(bgep, MII_AUX_CONTROL, auxctrl); 831 bge_mii_put16(bgep, MII_MSCONTROL, gigctrl); 832 833 BGE_DEBUG(("bge_update_copper: anar <- 0x%x", anar)); 834 BGE_DEBUG(("bge_update_copper: control <- 0x%x", control)); 835 BGE_DEBUG(("bge_update_copper: auxctrl <- 0x%x", auxctrl)); 836 BGE_DEBUG(("bge_update_copper: gigctrl <- 0x%x", gigctrl)); 837 838 #if BGE_COPPER_WIRESPEED 839 /* 840 * Enable the 'wire-speed' feature, if the chip supports it 841 * and we haven't got (any) loopback mode selected. 842 */ 843 switch (bgep->chipid.device) { 844 case DEVICE_ID_5700: 845 case DEVICE_ID_5700x: 846 case DEVICE_ID_5705C: 847 case DEVICE_ID_5782: 848 /* 849 * These chips are known or assumed not to support it 850 */ 851 break; 852 853 default: 854 /* 855 * All other Broadcom chips are expected to support it. 856 */ 857 if (bgep->param_loop_mode == BGE_LOOP_NONE) 858 bge_mii_put16(bgep, MII_AUX_CONTROL, 859 MII_AUX_CTRL_MISC_WRITE_ENABLE | 860 MII_AUX_CTRL_MISC_WIRE_SPEED | 861 MII_AUX_CTRL_MISC); 862 break; 863 } 864 #endif /* BGE_COPPER_WIRESPEED */ 865 return (DDI_SUCCESS); 866 } 867 868 static boolean_t 869 bge_check_copper(bge_t *bgep, boolean_t recheck) 870 { 871 uint32_t emac_status; 872 uint16_t mii_status; 873 uint16_t aux; 874 uint_t mode; 875 boolean_t linkup; 876 877 /* 878 * Step 10: read the status from the PHY (which is self-clearing 879 * on read!); also read & clear the main (Ethernet) MAC status 880 * (the relevant bits of this are write-one-to-clear). 881 */ 882 mii_status = bge_mii_get16(bgep, MII_STATUS); 883 emac_status = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG); 884 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, emac_status); 885 886 BGE_DEBUG(("bge_check_copper: link %d/%s, MII status 0x%x " 887 "(was 0x%x), Ethernet MAC status 0x%x", 888 bgep->link_state, UPORDOWN(bgep->param_link_up), mii_status, 889 bgep->phy_gen_status, emac_status)); 890 891 /* 892 * If the PHY status hasn't changed since last we looked, and 893 * we not forcing a recheck (i.e. the link state was already 894 * known), there's nothing to do. 895 */ 896 if (mii_status == bgep->phy_gen_status && !recheck) 897 return (B_FALSE); 898 899 do { 900 /* 901 * Step 11: read AUX STATUS register to find speed/duplex 902 */ 903 aux = bge_mii_get16(bgep, MII_AUX_STATUS); 904 BGE_CDB(bge_phydump, (bgep, mii_status, aux)); 905 906 /* 907 * We will only consider the link UP if all the readings 908 * are consistent and give meaningful results ... 909 */ 910 mode = aux & MII_AUX_STATUS_MODE_MASK; 911 mode >>= MII_AUX_STATUS_MODE_SHIFT; 912 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 913 linkup = BIS(aux, MII_AUX_STATUS_LINKUP); 914 linkup &= BIS(mii_status, MII_STATUS_LINKUP); 915 } else { 916 linkup = bge_copper_link_speed[mode] > 0; 917 linkup &= bge_copper_link_duplex[mode] != 918 LINK_DUPLEX_UNKNOWN; 919 linkup &= BIS(aux, MII_AUX_STATUS_LINKUP); 920 linkup &= BIS(mii_status, MII_STATUS_LINKUP); 921 } 922 923 BGE_DEBUG(("bge_check_copper: MII status 0x%x aux 0x%x " 924 "=> mode %d (%s)", 925 mii_status, aux, 926 mode, UPORDOWN(linkup))); 927 928 /* 929 * Record current register values, then reread status 930 * register & loop until it stabilises ... 931 */ 932 bgep->phy_aux_status = aux; 933 bgep->phy_gen_status = mii_status; 934 mii_status = bge_mii_get16(bgep, MII_STATUS); 935 } while (mii_status != bgep->phy_gen_status); 936 937 /* 938 * Assume very little ... 939 */ 940 bgep->param_lp_autoneg = B_FALSE; 941 bgep->param_lp_1000fdx = B_FALSE; 942 bgep->param_lp_1000hdx = B_FALSE; 943 bgep->param_lp_100fdx = B_FALSE; 944 bgep->param_lp_100hdx = B_FALSE; 945 bgep->param_lp_10fdx = B_FALSE; 946 bgep->param_lp_10hdx = B_FALSE; 947 bgep->param_lp_pause = B_FALSE; 948 bgep->param_lp_asym_pause = B_FALSE; 949 bgep->param_link_autoneg = B_FALSE; 950 bgep->param_link_tx_pause = B_FALSE; 951 if (bgep->param_adv_autoneg) 952 bgep->param_link_rx_pause = B_FALSE; 953 else 954 bgep->param_link_rx_pause = bgep->param_adv_pause; 955 956 /* 957 * Discover all the link partner's abilities. 958 * These are scattered through various registers ... 959 */ 960 if (BIS(aux, MII_AUX_STATUS_LP_ANEG_ABLE)) { 961 bgep->param_lp_autoneg = B_TRUE; 962 bgep->param_link_autoneg = B_TRUE; 963 bgep->param_link_tx_pause = BIS(aux, MII_AUX_STATUS_TX_PAUSE); 964 bgep->param_link_rx_pause = BIS(aux, MII_AUX_STATUS_RX_PAUSE); 965 966 aux = bge_mii_get16(bgep, MII_MSSTATUS); 967 bgep->param_lp_1000fdx = BIS(aux, MII_MSSTATUS_LP1000T_FD); 968 bgep->param_lp_1000hdx = BIS(aux, MII_MSSTATUS_LP1000T); 969 970 aux = bge_mii_get16(bgep, MII_AN_LPABLE); 971 bgep->param_lp_100fdx = BIS(aux, MII_ABILITY_100BASE_TX_FD); 972 bgep->param_lp_100hdx = BIS(aux, MII_ABILITY_100BASE_TX); 973 bgep->param_lp_10fdx = BIS(aux, MII_ABILITY_10BASE_T_FD); 974 bgep->param_lp_10hdx = BIS(aux, MII_ABILITY_10BASE_T); 975 bgep->param_lp_pause = BIS(aux, MII_ABILITY_PAUSE); 976 bgep->param_lp_asym_pause = BIS(aux, MII_ABILITY_ASMPAUSE); 977 } 978 979 /* 980 * Step 12: update ndd-visible state parameters, BUT! 981 * we don't transfer the new state to <link_state> just yet; 982 * instead we mark the <link_state> as UNKNOWN, and our caller 983 * will resolve it once the status has stopped changing and 984 * been stable for several seconds. 985 */ 986 BGE_DEBUG(("bge_check_copper: link was %s speed %d duplex %d", 987 UPORDOWN(bgep->param_link_up), 988 bgep->param_link_speed, 989 bgep->param_link_duplex)); 990 991 if (!linkup) 992 mode = MII_AUX_STATUS_MODE_NONE; 993 bgep->param_link_up = linkup; 994 bgep->link_state = LINK_STATE_UNKNOWN; 995 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 996 if (bgep->phy_aux_status & MII_AUX_STATUS_NEG_ENABLED_5906) { 997 bgep->param_link_speed = 998 bge_copper_link_speed_5906[mode]; 999 bgep->param_link_duplex = 1000 bge_copper_link_duplex_5906[mode]; 1001 } else { 1002 bgep->param_link_speed = (bgep->phy_aux_status & 1003 MII_AUX_STATUS_SPEED_IND_5906) ? 100 : 10; 1004 bgep->param_link_duplex = (bgep->phy_aux_status & 1005 MII_AUX_STATUS_DUPLEX_IND_5906) ? LINK_DUPLEX_FULL : 1006 LINK_DUPLEX_HALF; 1007 } 1008 } else { 1009 bgep->param_link_speed = bge_copper_link_speed[mode]; 1010 bgep->param_link_duplex = bge_copper_link_duplex[mode]; 1011 } 1012 1013 BGE_DEBUG(("bge_check_copper: link now %s speed %d duplex %d", 1014 UPORDOWN(bgep->param_link_up), 1015 bgep->param_link_speed, 1016 bgep->param_link_duplex)); 1017 1018 return (B_TRUE); 1019 } 1020 1021 static const phys_ops_t copper_ops = { 1022 bge_restart_copper, 1023 bge_update_copper, 1024 bge_check_copper 1025 }; 1026 1027 1028 /* 1029 * ========== SerDes support ========== 1030 */ 1031 1032 #undef BGE_DBG 1033 #define BGE_DBG BGE_DBG_SERDES /* debug flag for this code */ 1034 1035 /* 1036 * Reinitialise the SerDes interface. Note that it normally powers 1037 * up in the disabled state, so we need to explicitly activate it. 1038 */ 1039 static int 1040 bge_restart_serdes(bge_t *bgep, boolean_t powerdown) 1041 { 1042 uint32_t macmode; 1043 1044 BGE_TRACE(("bge_restart_serdes($%p, %d)", (void *)bgep, powerdown)); 1045 1046 ASSERT(mutex_owned(bgep->genlock)); 1047 1048 /* 1049 * Ensure that the main Ethernet MAC mode register is programmed 1050 * appropriately for the SerDes interface ... 1051 */ 1052 macmode = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 1053 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1054 macmode |= ETHERNET_MODE_LINK_POLARITY; 1055 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 1056 macmode |= ETHERNET_MODE_PORTMODE_GMII; 1057 } else { 1058 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 1059 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 1060 macmode |= ETHERNET_MODE_PORTMODE_TBI; 1061 } 1062 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 1063 1064 /* 1065 * Ensure that loopback is OFF and comma detection is enabled. Then 1066 * disable the SerDes output (the first time through, it may/will 1067 * already be disabled). If we're shutting down, leave it disabled. 1068 */ 1069 bge_reg_clr32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TBI_LOOPBACK); 1070 bge_reg_set32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_COMMA_DETECT); 1071 bge_reg_set32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TX_DISABLE); 1072 if (powerdown) 1073 return (DDI_SUCCESS); 1074 1075 /* 1076 * Otherwise, pause, (re-)enable the SerDes output, and send 1077 * all-zero config words in order to force autoneg restart. 1078 * Invalidate the saved "link partners received configs", as 1079 * we're starting over ... 1080 */ 1081 drv_usecwait(10000); 1082 bge_reg_clr32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TX_DISABLE); 1083 bge_reg_put32(bgep, TX_1000BASEX_AUTONEG_REG, 0); 1084 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_SEND_CFGS); 1085 drv_usecwait(10); 1086 bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_SEND_CFGS); 1087 bgep->serdes_lpadv = AUTONEG_CODE_FAULT_ANEG_ERR; 1088 bgep->serdes_status = ~0U; 1089 return (DDI_SUCCESS); 1090 } 1091 1092 /* 1093 * Synchronise the SerDes speed/duplex/autonegotiation capabilities and 1094 * advertisements with the required settings as specified by the various 1095 * param_* variables that can be poked via the NDD interface. 1096 * 1097 * We always reinitalise the SerDes; this should cause the link to go down, 1098 * and then back up again once the link is stable and autonegotiation 1099 * (if enabled) is complete. We should get a link state change interrupt 1100 * somewhere along the way ... 1101 * 1102 * NOTE: SerDes only supports 1000FDX/HDX (with or without pause) so the 1103 * param_* variables relating to lower speeds are ignored. 1104 * 1105 * NOTE: <genlock> must already be held by the caller 1106 */ 1107 static int 1108 bge_update_serdes(bge_t *bgep) 1109 { 1110 boolean_t adv_autoneg; 1111 boolean_t adv_pause; 1112 boolean_t adv_asym_pause; 1113 boolean_t adv_1000fdx; 1114 boolean_t adv_1000hdx; 1115 1116 uint32_t serdes; 1117 uint32_t advert; 1118 1119 BGE_TRACE(("bge_update_serdes($%p)", (void *)bgep)); 1120 1121 ASSERT(mutex_owned(bgep->genlock)); 1122 1123 BGE_DEBUG(("bge_update_serdes: autoneg %d " 1124 "pause %d asym_pause %d " 1125 "1000fdx %d 1000hdx %d " 1126 "100fdx %d 100hdx %d " 1127 "10fdx %d 10hdx %d ", 1128 bgep->param_adv_autoneg, 1129 bgep->param_adv_pause, bgep->param_adv_asym_pause, 1130 bgep->param_adv_1000fdx, bgep->param_adv_1000hdx, 1131 bgep->param_adv_100fdx, bgep->param_adv_100hdx, 1132 bgep->param_adv_10fdx, bgep->param_adv_10hdx)); 1133 1134 serdes = advert = 0; 1135 1136 /* 1137 * SerDes settings are normally based on the param_* variables, 1138 * but if any loopback mode is in effect, that takes precedence. 1139 * 1140 * BGE supports MAC-internal loopback, PHY-internal loopback, 1141 * and External loopback at a variety of speeds (with a special 1142 * cable). In all cases, autoneg is turned OFF, full-duplex 1143 * is turned ON, and the speed/mastership is forced. 1144 * 1145 * Note: for the SerDes interface, "PHY" internal loopback is 1146 * interpreted as SerDes internal loopback, and all external 1147 * loopback modes are treated equivalently, as 1Gb/external. 1148 */ 1149 switch (bgep->param_loop_mode) { 1150 case BGE_LOOP_NONE: 1151 default: 1152 adv_autoneg = bgep->param_adv_autoneg; 1153 adv_pause = bgep->param_adv_pause; 1154 adv_asym_pause = bgep->param_adv_asym_pause; 1155 adv_1000fdx = bgep->param_adv_1000fdx; 1156 adv_1000hdx = bgep->param_adv_1000hdx; 1157 break; 1158 1159 case BGE_LOOP_INTERNAL_PHY: 1160 serdes |= SERDES_CONTROL_TBI_LOOPBACK; 1161 /* FALLTHRU */ 1162 case BGE_LOOP_INTERNAL_MAC: 1163 case BGE_LOOP_EXTERNAL_1000: 1164 case BGE_LOOP_EXTERNAL_100: 1165 case BGE_LOOP_EXTERNAL_10: 1166 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 1167 adv_1000fdx = B_TRUE; 1168 adv_1000hdx = B_FALSE; 1169 break; 1170 } 1171 1172 BGE_DEBUG(("bge_update_serdes: autoneg %d " 1173 "pause %d asym_pause %d " 1174 "1000fdx %d 1000hdx %d ", 1175 adv_autoneg, 1176 adv_pause, adv_asym_pause, 1177 adv_1000fdx, adv_1000hdx)); 1178 1179 /* 1180 * We should have at least one gigabit technology capability 1181 * set; if not, we select a default of 1000Mb/s full-duplex 1182 */ 1183 if (!adv_1000fdx && !adv_1000hdx) 1184 adv_1000fdx = B_TRUE; 1185 1186 /* 1187 * Now transform the adv_* variables into the proper settings 1188 * of the SerDes registers ... 1189 * 1190 * If autonegotiation is (now) not enabled, pretend it's been 1191 * done and failed ... 1192 */ 1193 if (!adv_autoneg) 1194 advert |= AUTONEG_CODE_FAULT_ANEG_ERR; 1195 1196 if (adv_1000fdx) { 1197 advert |= AUTONEG_CODE_FULL_DUPLEX; 1198 bgep->param_adv_1000fdx = adv_1000fdx; 1199 bgep->param_link_duplex = LINK_DUPLEX_FULL; 1200 bgep->param_link_speed = 1000; 1201 } 1202 if (adv_1000hdx) { 1203 advert |= AUTONEG_CODE_HALF_DUPLEX; 1204 bgep->param_adv_1000hdx = adv_1000hdx; 1205 bgep->param_link_duplex = LINK_DUPLEX_HALF; 1206 bgep->param_link_speed = 1000; 1207 } 1208 1209 if (adv_pause) 1210 advert |= AUTONEG_CODE_PAUSE; 1211 if (adv_asym_pause) 1212 advert |= AUTONEG_CODE_ASYM_PAUSE; 1213 1214 /* 1215 * Restart the SerDes and write the new values. Note the 1216 * time, so that we can say whether subsequent link state 1217 * changes can be attributed to our reprogramming the SerDes 1218 */ 1219 bgep->serdes_advert = advert; 1220 (void) bge_restart_serdes(bgep, B_FALSE); 1221 bge_reg_set32(bgep, SERDES_CONTROL_REG, serdes); 1222 1223 BGE_DEBUG(("bge_update_serdes: serdes |= 0x%x, advert 0x%x", 1224 serdes, advert)); 1225 return (DDI_SUCCESS); 1226 } 1227 1228 /* 1229 * Bare-minimum autoneg protocol 1230 * 1231 * This code is only called when the link is up and we're receiving config 1232 * words, which implies that the link partner wants to autonegotiate 1233 * (otherwise, we wouldn't see configs and wouldn't reach this code). 1234 */ 1235 static void 1236 bge_autoneg_serdes(bge_t *bgep) 1237 { 1238 boolean_t ack; 1239 1240 bgep->serdes_lpadv = bge_reg_get32(bgep, RX_1000BASEX_AUTONEG_REG); 1241 ack = BIS(bgep->serdes_lpadv, AUTONEG_CODE_ACKNOWLEDGE); 1242 1243 if (!ack) { 1244 /* 1245 * Phase 1: after SerDes reset, we send a few zero configs 1246 * but then stop. Here the partner is sending configs, but 1247 * not ACKing ours; we assume that's 'cos we're not sending 1248 * any. So here we send ours, with ACK already set. 1249 */ 1250 bge_reg_put32(bgep, TX_1000BASEX_AUTONEG_REG, 1251 bgep->serdes_advert | AUTONEG_CODE_ACKNOWLEDGE); 1252 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 1253 ETHERNET_MODE_SEND_CFGS); 1254 } else { 1255 /* 1256 * Phase 2: partner has ACKed our configs, so now we can 1257 * stop sending; once our partner also stops sending, we 1258 * can resolve the Tx/Rx configs. 1259 */ 1260 bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, 1261 ETHERNET_MODE_SEND_CFGS); 1262 } 1263 1264 BGE_DEBUG(("bge_autoneg_serdes: Rx 0x%x %s Tx 0x%x", 1265 bgep->serdes_lpadv, 1266 ack ? "stop" : "send", 1267 bgep->serdes_advert)); 1268 } 1269 1270 static boolean_t 1271 bge_check_serdes(bge_t *bgep, boolean_t recheck) 1272 { 1273 uint32_t emac_status; 1274 uint32_t lpadv; 1275 boolean_t linkup; 1276 boolean_t linkup_old = bgep->param_link_up; 1277 1278 for (;;) { 1279 /* 1280 * Step 10: BCM5714S, BCM5715S only 1281 * Don't call function bge_autoneg_serdes() as 1282 * RX_1000BASEX_AUTONEG_REG (0x0448) is not applicable 1283 * to BCM5705, BCM5788, BCM5721, BCM5751, BCM5752, 1284 * BCM5714, and BCM5715 devices. 1285 */ 1286 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1287 emac_status = bge_reg_get32(bgep, MI_STATUS_REG); 1288 linkup = BIS(emac_status, MI_STATUS_LINK); 1289 bgep->serdes_status = emac_status; 1290 if ((linkup && linkup_old) || 1291 (!linkup && !linkup_old)) { 1292 emac_status &= ~ETHERNET_STATUS_LINK_CHANGED; 1293 emac_status &= ~ETHERNET_STATUS_RECEIVING_CFG; 1294 break; 1295 } 1296 emac_status |= ETHERNET_STATUS_LINK_CHANGED; 1297 emac_status |= ETHERNET_STATUS_RECEIVING_CFG; 1298 if (linkup) 1299 linkup_old = B_TRUE; 1300 else 1301 linkup_old = B_FALSE; 1302 recheck = B_TRUE; 1303 } else { 1304 /* 1305 * Step 10: others 1306 * read & clear the main (Ethernet) MAC status 1307 * (the relevant bits of this are write-one-to-clear). 1308 */ 1309 emac_status = bge_reg_get32(bgep, 1310 ETHERNET_MAC_STATUS_REG); 1311 bge_reg_put32(bgep, 1312 ETHERNET_MAC_STATUS_REG, emac_status); 1313 1314 BGE_DEBUG(("bge_check_serdes: link %d/%s, " 1315 "MAC status 0x%x (was 0x%x)", 1316 bgep->link_state, UPORDOWN(bgep->param_link_up), 1317 emac_status, bgep->serdes_status)); 1318 1319 /* 1320 * We will only consider the link UP if all the readings 1321 * are consistent and give meaningful results ... 1322 */ 1323 bgep->serdes_status = emac_status; 1324 linkup = BIS(emac_status, 1325 ETHERNET_STATUS_SIGNAL_DETECT); 1326 linkup &= BIS(emac_status, ETHERNET_STATUS_PCS_SYNCHED); 1327 1328 /* 1329 * Now some fiddling with the interpretation: 1330 * if there's been an error at the PCS level, treat 1331 * it as a link change (the h/w doesn't do this) 1332 * 1333 * if there's been a change, but it's only a PCS 1334 * sync change (not a config change), AND the link 1335 * already was & is still UP, then ignore the 1336 * change 1337 */ 1338 if (BIS(emac_status, ETHERNET_STATUS_PCS_ERROR)) 1339 emac_status |= ETHERNET_STATUS_LINK_CHANGED; 1340 else if (BIC(emac_status, ETHERNET_STATUS_CFG_CHANGED)) 1341 if (bgep->param_link_up && linkup) 1342 emac_status &= 1343 ~ETHERNET_STATUS_LINK_CHANGED; 1344 1345 BGE_DEBUG(("bge_check_serdes: status 0x%x => 0x%x %s", 1346 bgep->serdes_status, emac_status, 1347 UPORDOWN(linkup))); 1348 1349 /* 1350 * If we're receiving configs, run the autoneg protocol 1351 */ 1352 if (linkup && BIS(emac_status, 1353 ETHERNET_STATUS_RECEIVING_CFG)) 1354 bge_autoneg_serdes(bgep); 1355 1356 /* 1357 * If the SerDes status hasn't changed, we're done ... 1358 */ 1359 if (BIC(emac_status, ETHERNET_STATUS_LINK_CHANGED)) 1360 break; 1361 1362 /* 1363 * Go round again until we no longer see a change ... 1364 */ 1365 recheck = B_TRUE; 1366 } 1367 } 1368 1369 /* 1370 * If we're not forcing a recheck (i.e. the link state was already 1371 * known), and we didn't see the hardware flag a change, there's 1372 * no more to do (and we tell the caller nothing happened). 1373 */ 1374 if (!recheck) 1375 return (B_FALSE); 1376 1377 /* 1378 * Don't resolve autoneg until we're no longer receiving configs 1379 */ 1380 if (linkup && BIS(emac_status, ETHERNET_STATUS_RECEIVING_CFG)) 1381 return (B_FALSE); 1382 1383 /* 1384 * Assume very little ... 1385 */ 1386 bgep->param_lp_autoneg = B_FALSE; 1387 bgep->param_lp_1000fdx = B_FALSE; 1388 bgep->param_lp_1000hdx = B_FALSE; 1389 bgep->param_lp_100fdx = B_FALSE; 1390 bgep->param_lp_100hdx = B_FALSE; 1391 bgep->param_lp_10fdx = B_FALSE; 1392 bgep->param_lp_10hdx = B_FALSE; 1393 bgep->param_lp_pause = B_FALSE; 1394 bgep->param_lp_asym_pause = B_FALSE; 1395 bgep->param_link_autoneg = B_FALSE; 1396 bgep->param_link_tx_pause = B_FALSE; 1397 if (bgep->param_adv_autoneg) 1398 bgep->param_link_rx_pause = B_FALSE; 1399 else 1400 bgep->param_link_rx_pause = bgep->param_adv_pause; 1401 1402 /* 1403 * Discover all the link partner's abilities. 1404 */ 1405 lpadv = bgep->serdes_lpadv; 1406 if (lpadv != 0 && BIC(lpadv, AUTONEG_CODE_FAULT_MASK)) { 1407 /* 1408 * No fault, so derive partner's capabilities 1409 */ 1410 bgep->param_lp_autoneg = B_TRUE; 1411 bgep->param_lp_1000fdx = BIS(lpadv, AUTONEG_CODE_FULL_DUPLEX); 1412 bgep->param_lp_1000hdx = BIS(lpadv, AUTONEG_CODE_HALF_DUPLEX); 1413 bgep->param_lp_pause = BIS(lpadv, AUTONEG_CODE_PAUSE); 1414 bgep->param_lp_asym_pause = BIS(lpadv, AUTONEG_CODE_ASYM_PAUSE); 1415 1416 /* 1417 * Pause direction resolution 1418 */ 1419 bgep->param_link_autoneg = B_TRUE; 1420 if (bgep->param_adv_pause && 1421 bgep->param_lp_pause) { 1422 bgep->param_link_tx_pause = B_TRUE; 1423 bgep->param_link_rx_pause = B_TRUE; 1424 } 1425 if (bgep->param_adv_asym_pause && 1426 bgep->param_lp_asym_pause) { 1427 if (bgep->param_adv_pause) 1428 bgep->param_link_rx_pause = B_TRUE; 1429 if (bgep->param_lp_pause) 1430 bgep->param_link_tx_pause = B_TRUE; 1431 } 1432 } 1433 1434 /* 1435 * Step 12: update ndd-visible state parameters, BUT! 1436 * we don't transfer the new state to <link_state> just yet; 1437 * instead we mark the <link_state> as UNKNOWN, and our caller 1438 * will resolve it once the status has stopped changing and 1439 * been stable for several seconds. 1440 */ 1441 BGE_DEBUG(("bge_check_serdes: link was %s speed %d duplex %d", 1442 UPORDOWN(bgep->param_link_up), 1443 bgep->param_link_speed, 1444 bgep->param_link_duplex)); 1445 1446 if (linkup) { 1447 bgep->param_link_up = B_TRUE; 1448 bgep->param_link_speed = 1000; 1449 if (bgep->param_adv_1000fdx) 1450 bgep->param_link_duplex = LINK_DUPLEX_FULL; 1451 else 1452 bgep->param_link_duplex = LINK_DUPLEX_HALF; 1453 if (bgep->param_lp_autoneg && !bgep->param_lp_1000fdx) 1454 bgep->param_link_duplex = LINK_DUPLEX_HALF; 1455 } else { 1456 bgep->param_link_up = B_FALSE; 1457 bgep->param_link_speed = 0; 1458 bgep->param_link_duplex = LINK_DUPLEX_UNKNOWN; 1459 } 1460 bgep->link_state = LINK_STATE_UNKNOWN; 1461 1462 BGE_DEBUG(("bge_check_serdes: link now %s speed %d duplex %d", 1463 UPORDOWN(bgep->param_link_up), 1464 bgep->param_link_speed, 1465 bgep->param_link_duplex)); 1466 1467 return (B_TRUE); 1468 } 1469 1470 static const phys_ops_t serdes_ops = { 1471 bge_restart_serdes, 1472 bge_update_serdes, 1473 bge_check_serdes 1474 }; 1475 1476 /* 1477 * ========== Exported physical layer control routines ========== 1478 */ 1479 1480 #undef BGE_DBG 1481 #define BGE_DBG BGE_DBG_PHYS /* debug flag for this code */ 1482 1483 /* 1484 * Here we have to determine which media we're using (copper or serdes). 1485 * Once that's done, we can initialise the physical layer appropriately. 1486 */ 1487 int 1488 bge_phys_init(bge_t *bgep) 1489 { 1490 BGE_TRACE(("bge_phys_init($%p)", (void *)bgep)); 1491 1492 mutex_enter(bgep->genlock); 1493 1494 /* 1495 * Probe for the (internal) PHY. If it's not there, we'll assume 1496 * that this is a 5703/4S, with a SerDes interface rather than 1497 * a PHY. BCM5714S/BCM5715S are not supported.It are based on 1498 * BCM800x PHY. 1499 */ 1500 bgep->phy_mii_addr = 1; 1501 if (bge_phy_probe(bgep)) { 1502 bgep->chipid.flags &= ~CHIP_FLAG_SERDES; 1503 bgep->physops = &copper_ops; 1504 } else { 1505 bgep->chipid.flags |= CHIP_FLAG_SERDES; 1506 bgep->physops = &serdes_ops; 1507 } 1508 1509 if ((*bgep->physops->phys_restart)(bgep, B_FALSE) != DDI_SUCCESS) { 1510 mutex_exit(bgep->genlock); 1511 return (EIO); 1512 } 1513 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 1514 mutex_exit(bgep->genlock); 1515 return (EIO); 1516 } 1517 mutex_exit(bgep->genlock); 1518 return (0); 1519 } 1520 1521 /* 1522 * Reset the physical layer 1523 */ 1524 void 1525 bge_phys_reset(bge_t *bgep) 1526 { 1527 BGE_TRACE(("bge_phys_reset($%p)", (void *)bgep)); 1528 1529 mutex_enter(bgep->genlock); 1530 if ((*bgep->physops->phys_restart)(bgep, B_FALSE) != DDI_SUCCESS) 1531 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 1532 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 1533 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 1534 mutex_exit(bgep->genlock); 1535 } 1536 1537 /* 1538 * Reset and power off the physical layer. 1539 * 1540 * Another RESET should get it back to working, but it may take a few 1541 * seconds it may take a few moments to return to normal operation ... 1542 */ 1543 int 1544 bge_phys_idle(bge_t *bgep) 1545 { 1546 BGE_TRACE(("bge_phys_idle($%p)", (void *)bgep)); 1547 1548 ASSERT(mutex_owned(bgep->genlock)); 1549 return ((*bgep->physops->phys_restart)(bgep, B_TRUE)); 1550 } 1551 1552 /* 1553 * Synchronise the PHYSICAL layer's speed/duplex/autonegotiation capabilities 1554 * and advertisements with the required settings as specified by the various 1555 * param_* variables that can be poked via the NDD interface. 1556 * 1557 * We always reset the PHYSICAL layer and reprogram *all* relevant registers. 1558 * This is expected to cause the link to go down, and then back up again once 1559 * the link is stable and autonegotiation (if enabled) is complete. We should 1560 * get a link state change interrupt somewhere along the way ... 1561 * 1562 * NOTE: <genlock> must already be held by the caller 1563 */ 1564 int 1565 bge_phys_update(bge_t *bgep) 1566 { 1567 BGE_TRACE(("bge_phys_update($%p)", (void *)bgep)); 1568 1569 ASSERT(mutex_owned(bgep->genlock)); 1570 return ((*bgep->physops->phys_update)(bgep)); 1571 } 1572 1573 #undef BGE_DBG 1574 #define BGE_DBG BGE_DBG_LINK /* debug flag for this code */ 1575 1576 /* 1577 * Read the link status and determine whether anything's changed ... 1578 * 1579 * This routine should be called whenever the chip flags a change 1580 * in the hardware link state. 1581 * 1582 * This routine returns B_FALSE if the link state has not changed, 1583 * returns B_TRUE when the change to the new state should be accepted. 1584 * In such a case, the param_* variables give the new hardware state, 1585 * which the caller should use to update link_state etc. 1586 * 1587 * The caller must already hold <genlock> 1588 */ 1589 boolean_t 1590 bge_phys_check(bge_t *bgep) 1591 { 1592 int32_t orig_state; 1593 boolean_t recheck; 1594 1595 BGE_TRACE(("bge_phys_check($%p)", (void *)bgep)); 1596 1597 ASSERT(mutex_owned(bgep->genlock)); 1598 1599 orig_state = bgep->link_state; 1600 recheck = orig_state == LINK_STATE_UNKNOWN; 1601 recheck = (*bgep->physops->phys_check)(bgep, recheck); 1602 if (!recheck) 1603 return (B_FALSE); 1604 1605 return (B_TRUE); 1606 } 1607