1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "bge_impl.h" 30 #include <sys/sdt.h> 31 32 /* 33 * This is the string displayed by modinfo, etc. 34 * Make sure you keep the version ID up to date! 35 */ 36 static char bge_ident[] = "Broadcom Gb Ethernet v0.59"; 37 38 /* 39 * Property names 40 */ 41 static char debug_propname[] = "bge-debug-flags"; 42 static char clsize_propname[] = "cache-line-size"; 43 static char latency_propname[] = "latency-timer"; 44 static char localmac_boolname[] = "local-mac-address?"; 45 static char localmac_propname[] = "local-mac-address"; 46 static char macaddr_propname[] = "mac-address"; 47 static char subdev_propname[] = "subsystem-id"; 48 static char subven_propname[] = "subsystem-vendor-id"; 49 static char rxrings_propname[] = "bge-rx-rings"; 50 static char txrings_propname[] = "bge-tx-rings"; 51 static char fm_cap[] = "fm-capable"; 52 static char default_mtu[] = "default_mtu"; 53 54 static int bge_add_intrs(bge_t *, int); 55 static void bge_rem_intrs(bge_t *); 56 57 /* 58 * Describes the chip's DMA engine 59 */ 60 static ddi_dma_attr_t dma_attr = { 61 DMA_ATTR_V0, /* dma_attr version */ 62 0x0000000000000000ull, /* dma_attr_addr_lo */ 63 0xFFFFFFFFFFFFFFFFull, /* dma_attr_addr_hi */ 64 0x00000000FFFFFFFFull, /* dma_attr_count_max */ 65 0x0000000000000001ull, /* dma_attr_align */ 66 0x00000FFF, /* dma_attr_burstsizes */ 67 0x00000001, /* dma_attr_minxfer */ 68 0x000000000000FFFFull, /* dma_attr_maxxfer */ 69 0xFFFFFFFFFFFFFFFFull, /* dma_attr_seg */ 70 1, /* dma_attr_sgllen */ 71 0x00000001, /* dma_attr_granular */ 72 DDI_DMA_FLAGERR /* dma_attr_flags */ 73 }; 74 75 /* 76 * PIO access attributes for registers 77 */ 78 static ddi_device_acc_attr_t bge_reg_accattr = { 79 DDI_DEVICE_ATTR_V0, 80 DDI_NEVERSWAP_ACC, 81 DDI_STRICTORDER_ACC, 82 DDI_FLAGERR_ACC 83 }; 84 85 /* 86 * DMA access attributes for descriptors: NOT to be byte swapped. 87 */ 88 static ddi_device_acc_attr_t bge_desc_accattr = { 89 DDI_DEVICE_ATTR_V0, 90 DDI_NEVERSWAP_ACC, 91 DDI_STRICTORDER_ACC, 92 DDI_FLAGERR_ACC 93 }; 94 95 /* 96 * DMA access attributes for data: NOT to be byte swapped. 97 */ 98 static ddi_device_acc_attr_t bge_data_accattr = { 99 DDI_DEVICE_ATTR_V0, 100 DDI_NEVERSWAP_ACC, 101 DDI_STRICTORDER_ACC 102 }; 103 104 /* 105 * Versions of the O/S up to Solaris 8 didn't support network booting 106 * from any network interface except the first (NET0). Patching this 107 * flag to a non-zero value will tell the driver to work around this 108 * limitation by creating an extra (internal) pathname node. To do 109 * this, just add a line like the following to the CLIENT'S etc/system 110 * file ON THE ROOT FILESYSTEM SERVER before booting the client: 111 * 112 * set bge:bge_net1_boot_support = 1; 113 */ 114 static uint32_t bge_net1_boot_support = 1; 115 116 static int bge_m_start(void *); 117 static void bge_m_stop(void *); 118 static int bge_m_promisc(void *, boolean_t); 119 static int bge_m_multicst(void *, boolean_t, const uint8_t *); 120 static int bge_m_unicst(void *, const uint8_t *); 121 static void bge_m_resources(void *); 122 static void bge_m_ioctl(void *, queue_t *, mblk_t *); 123 static boolean_t bge_m_getcapab(void *, mac_capab_t, void *); 124 static int bge_unicst_set(void *, const uint8_t *, 125 mac_addr_slot_t); 126 static int bge_m_unicst_add(void *, mac_multi_addr_t *); 127 static int bge_m_unicst_remove(void *, mac_addr_slot_t); 128 static int bge_m_unicst_modify(void *, mac_multi_addr_t *); 129 static int bge_m_unicst_get(void *, mac_multi_addr_t *); 130 131 #define BGE_M_CALLBACK_FLAGS (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB) 132 133 static mac_callbacks_t bge_m_callbacks = { 134 BGE_M_CALLBACK_FLAGS, 135 bge_m_stat, 136 bge_m_start, 137 bge_m_stop, 138 bge_m_promisc, 139 bge_m_multicst, 140 bge_m_unicst, 141 bge_m_tx, 142 bge_m_resources, 143 bge_m_ioctl, 144 bge_m_getcapab 145 }; 146 147 /* 148 * ========== Transmit and receive ring reinitialisation ========== 149 */ 150 151 /* 152 * These <reinit> routines each reset the specified ring to an initial 153 * state, assuming that the corresponding <init> routine has already 154 * been called exactly once. 155 */ 156 157 static void 158 bge_reinit_send_ring(send_ring_t *srp) 159 { 160 bge_queue_t *txbuf_queue; 161 bge_queue_item_t *txbuf_head; 162 sw_txbuf_t *txbuf; 163 sw_sbd_t *ssbdp; 164 uint32_t slot; 165 166 /* 167 * Reinitialise control variables ... 168 */ 169 srp->tx_flow = 0; 170 srp->tx_next = 0; 171 srp->txfill_next = 0; 172 srp->tx_free = srp->desc.nslots; 173 ASSERT(mutex_owned(srp->tc_lock)); 174 srp->tc_next = 0; 175 srp->txpkt_next = 0; 176 srp->tx_block = 0; 177 srp->tx_nobd = 0; 178 srp->tx_nobuf = 0; 179 180 /* 181 * Initialize the tx buffer push queue 182 */ 183 mutex_enter(srp->freetxbuf_lock); 184 mutex_enter(srp->txbuf_lock); 185 txbuf_queue = &srp->freetxbuf_queue; 186 txbuf_queue->head = NULL; 187 txbuf_queue->count = 0; 188 txbuf_queue->lock = srp->freetxbuf_lock; 189 srp->txbuf_push_queue = txbuf_queue; 190 191 /* 192 * Initialize the tx buffer pop queue 193 */ 194 txbuf_queue = &srp->txbuf_queue; 195 txbuf_queue->head = NULL; 196 txbuf_queue->count = 0; 197 txbuf_queue->lock = srp->txbuf_lock; 198 srp->txbuf_pop_queue = txbuf_queue; 199 txbuf_head = srp->txbuf_head; 200 txbuf = srp->txbuf; 201 for (slot = 0; slot < srp->tx_buffers; ++slot) { 202 txbuf_head->item = txbuf; 203 txbuf_head->next = txbuf_queue->head; 204 txbuf_queue->head = txbuf_head; 205 txbuf_queue->count++; 206 txbuf++; 207 txbuf_head++; 208 } 209 mutex_exit(srp->txbuf_lock); 210 mutex_exit(srp->freetxbuf_lock); 211 212 /* 213 * Zero and sync all the h/w Send Buffer Descriptors 214 */ 215 DMA_ZERO(srp->desc); 216 DMA_SYNC(srp->desc, DDI_DMA_SYNC_FORDEV); 217 bzero(srp->pktp, BGE_SEND_BUF_MAX * sizeof (*srp->pktp)); 218 ssbdp = srp->sw_sbds; 219 for (slot = 0; slot < srp->desc.nslots; ++ssbdp, ++slot) 220 ssbdp->pbuf = NULL; 221 } 222 223 static void 224 bge_reinit_recv_ring(recv_ring_t *rrp) 225 { 226 /* 227 * Reinitialise control variables ... 228 */ 229 rrp->rx_next = 0; 230 } 231 232 static void 233 bge_reinit_buff_ring(buff_ring_t *brp, uint32_t ring) 234 { 235 bge_rbd_t *hw_rbd_p; 236 sw_rbd_t *srbdp; 237 uint32_t bufsize; 238 uint32_t nslots; 239 uint32_t slot; 240 241 static uint16_t ring_type_flag[BGE_BUFF_RINGS_MAX] = { 242 RBD_FLAG_STD_RING, 243 RBD_FLAG_JUMBO_RING, 244 RBD_FLAG_MINI_RING 245 }; 246 247 /* 248 * Zero, initialise and sync all the h/w Receive Buffer Descriptors 249 * Note: all the remaining fields (<type>, <flags>, <ip_cksum>, 250 * <tcp_udp_cksum>, <error_flag>, <vlan_tag>, and <reserved>) 251 * should be zeroed, and so don't need to be set up specifically 252 * once the whole area has been cleared. 253 */ 254 DMA_ZERO(brp->desc); 255 256 hw_rbd_p = DMA_VPTR(brp->desc); 257 nslots = brp->desc.nslots; 258 ASSERT(brp->buf[0].nslots == nslots/BGE_SPLIT); 259 bufsize = brp->buf[0].size; 260 srbdp = brp->sw_rbds; 261 for (slot = 0; slot < nslots; ++hw_rbd_p, ++srbdp, ++slot) { 262 hw_rbd_p->host_buf_addr = srbdp->pbuf.cookie.dmac_laddress; 263 hw_rbd_p->index = slot; 264 hw_rbd_p->len = bufsize; 265 hw_rbd_p->opaque = srbdp->pbuf.token; 266 hw_rbd_p->flags |= ring_type_flag[ring]; 267 } 268 269 DMA_SYNC(brp->desc, DDI_DMA_SYNC_FORDEV); 270 271 /* 272 * Finally, reinitialise the ring control variables ... 273 */ 274 brp->rf_next = (nslots != 0) ? (nslots-1) : 0; 275 } 276 277 /* 278 * Reinitialize all rings 279 */ 280 static void 281 bge_reinit_rings(bge_t *bgep) 282 { 283 uint32_t ring; 284 285 ASSERT(mutex_owned(bgep->genlock)); 286 287 /* 288 * Send Rings ... 289 */ 290 for (ring = 0; ring < bgep->chipid.tx_rings; ++ring) 291 bge_reinit_send_ring(&bgep->send[ring]); 292 293 /* 294 * Receive Return Rings ... 295 */ 296 for (ring = 0; ring < bgep->chipid.rx_rings; ++ring) 297 bge_reinit_recv_ring(&bgep->recv[ring]); 298 299 /* 300 * Receive Producer Rings ... 301 */ 302 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 303 bge_reinit_buff_ring(&bgep->buff[ring], ring); 304 } 305 306 /* 307 * ========== Internal state management entry points ========== 308 */ 309 310 #undef BGE_DBG 311 #define BGE_DBG BGE_DBG_NEMO /* debug flag for this code */ 312 313 /* 314 * These routines provide all the functionality required by the 315 * corresponding GLD entry points, but don't update the GLD state 316 * so they can be called internally without disturbing our record 317 * of what GLD thinks we should be doing ... 318 */ 319 320 /* 321 * bge_reset() -- reset h/w & rings to initial state 322 */ 323 static int 324 #ifdef BGE_IPMI_ASF 325 bge_reset(bge_t *bgep, uint_t asf_mode) 326 #else 327 bge_reset(bge_t *bgep) 328 #endif 329 { 330 uint32_t ring; 331 int retval; 332 333 BGE_TRACE(("bge_reset($%p)", (void *)bgep)); 334 335 ASSERT(mutex_owned(bgep->genlock)); 336 337 /* 338 * Grab all the other mutexes in the world (this should 339 * ensure no other threads are manipulating driver state) 340 */ 341 for (ring = 0; ring < BGE_RECV_RINGS_MAX; ++ring) 342 mutex_enter(bgep->recv[ring].rx_lock); 343 for (ring = 0; ring < BGE_BUFF_RINGS_MAX; ++ring) 344 mutex_enter(bgep->buff[ring].rf_lock); 345 rw_enter(bgep->errlock, RW_WRITER); 346 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring) 347 mutex_enter(bgep->send[ring].tx_lock); 348 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring) 349 mutex_enter(bgep->send[ring].tc_lock); 350 351 #ifdef BGE_IPMI_ASF 352 retval = bge_chip_reset(bgep, B_TRUE, asf_mode); 353 #else 354 retval = bge_chip_reset(bgep, B_TRUE); 355 #endif 356 bge_reinit_rings(bgep); 357 358 /* 359 * Free the world ... 360 */ 361 for (ring = BGE_SEND_RINGS_MAX; ring-- > 0; ) 362 mutex_exit(bgep->send[ring].tc_lock); 363 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring) 364 mutex_exit(bgep->send[ring].tx_lock); 365 rw_exit(bgep->errlock); 366 for (ring = BGE_BUFF_RINGS_MAX; ring-- > 0; ) 367 mutex_exit(bgep->buff[ring].rf_lock); 368 for (ring = BGE_RECV_RINGS_MAX; ring-- > 0; ) 369 mutex_exit(bgep->recv[ring].rx_lock); 370 371 BGE_DEBUG(("bge_reset($%p) done", (void *)bgep)); 372 return (retval); 373 } 374 375 /* 376 * bge_stop() -- stop processing, don't reset h/w or rings 377 */ 378 static void 379 bge_stop(bge_t *bgep) 380 { 381 BGE_TRACE(("bge_stop($%p)", (void *)bgep)); 382 383 ASSERT(mutex_owned(bgep->genlock)); 384 385 #ifdef BGE_IPMI_ASF 386 if (bgep->asf_enabled) { 387 bgep->asf_pseudostop = B_TRUE; 388 } else { 389 #endif 390 bge_chip_stop(bgep, B_FALSE); 391 #ifdef BGE_IPMI_ASF 392 } 393 #endif 394 395 BGE_DEBUG(("bge_stop($%p) done", (void *)bgep)); 396 } 397 398 /* 399 * bge_start() -- start transmitting/receiving 400 */ 401 static int 402 bge_start(bge_t *bgep, boolean_t reset_phys) 403 { 404 int retval; 405 406 BGE_TRACE(("bge_start($%p, %d)", (void *)bgep, reset_phys)); 407 408 ASSERT(mutex_owned(bgep->genlock)); 409 410 /* 411 * Start chip processing, including enabling interrupts 412 */ 413 retval = bge_chip_start(bgep, reset_phys); 414 415 BGE_DEBUG(("bge_start($%p, %d) done", (void *)bgep, reset_phys)); 416 return (retval); 417 } 418 419 /* 420 * bge_restart - restart transmitting/receiving after error or suspend 421 */ 422 int 423 bge_restart(bge_t *bgep, boolean_t reset_phys) 424 { 425 int retval = DDI_SUCCESS; 426 ASSERT(mutex_owned(bgep->genlock)); 427 428 #ifdef BGE_IPMI_ASF 429 if (bgep->asf_enabled) { 430 if (bge_reset(bgep, ASF_MODE_POST_INIT) != DDI_SUCCESS) 431 retval = DDI_FAILURE; 432 } else 433 if (bge_reset(bgep, ASF_MODE_NONE) != DDI_SUCCESS) 434 retval = DDI_FAILURE; 435 #else 436 if (bge_reset(bgep) != DDI_SUCCESS) 437 retval = DDI_FAILURE; 438 #endif 439 if (bgep->bge_mac_state == BGE_MAC_STARTED) { 440 if (bge_start(bgep, reset_phys) != DDI_SUCCESS) 441 retval = DDI_FAILURE; 442 bgep->watchdog = 0; 443 ddi_trigger_softintr(bgep->drain_id); 444 } 445 446 BGE_DEBUG(("bge_restart($%p, %d) done", (void *)bgep, reset_phys)); 447 return (retval); 448 } 449 450 451 /* 452 * ========== Nemo-required management entry points ========== 453 */ 454 455 #undef BGE_DBG 456 #define BGE_DBG BGE_DBG_NEMO /* debug flag for this code */ 457 458 /* 459 * bge_m_stop() -- stop transmitting/receiving 460 */ 461 static void 462 bge_m_stop(void *arg) 463 { 464 bge_t *bgep = arg; /* private device info */ 465 send_ring_t *srp; 466 uint32_t ring; 467 468 BGE_TRACE(("bge_m_stop($%p)", arg)); 469 470 /* 471 * Just stop processing, then record new GLD state 472 */ 473 mutex_enter(bgep->genlock); 474 if (!(bgep->progress & PROGRESS_INTR)) { 475 /* can happen during autorecovery */ 476 mutex_exit(bgep->genlock); 477 return; 478 } 479 bge_stop(bgep); 480 /* 481 * Free the possible tx buffers allocated in tx process. 482 */ 483 #ifdef BGE_IPMI_ASF 484 if (!bgep->asf_pseudostop) 485 #endif 486 { 487 rw_enter(bgep->errlock, RW_WRITER); 488 for (ring = 0; ring < bgep->chipid.tx_rings; ++ring) { 489 srp = &bgep->send[ring]; 490 mutex_enter(srp->tx_lock); 491 if (srp->tx_array > 1) 492 bge_free_txbuf_arrays(srp); 493 mutex_exit(srp->tx_lock); 494 } 495 rw_exit(bgep->errlock); 496 } 497 bgep->bge_mac_state = BGE_MAC_STOPPED; 498 BGE_DEBUG(("bge_m_stop($%p) done", arg)); 499 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 500 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 501 mutex_exit(bgep->genlock); 502 } 503 504 /* 505 * bge_m_start() -- start transmitting/receiving 506 */ 507 static int 508 bge_m_start(void *arg) 509 { 510 bge_t *bgep = arg; /* private device info */ 511 512 BGE_TRACE(("bge_m_start($%p)", arg)); 513 514 /* 515 * Start processing and record new GLD state 516 */ 517 mutex_enter(bgep->genlock); 518 if (!(bgep->progress & PROGRESS_INTR)) { 519 /* can happen during autorecovery */ 520 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 521 mutex_exit(bgep->genlock); 522 return (EIO); 523 } 524 #ifdef BGE_IPMI_ASF 525 if (bgep->asf_enabled) { 526 if ((bgep->asf_status == ASF_STAT_RUN) && 527 (bgep->asf_pseudostop)) { 528 529 bgep->bge_mac_state = BGE_MAC_STARTED; 530 mutex_exit(bgep->genlock); 531 return (0); 532 } 533 } 534 if (bge_reset(bgep, ASF_MODE_INIT) != DDI_SUCCESS) { 535 #else 536 if (bge_reset(bgep) != DDI_SUCCESS) { 537 #endif 538 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 539 (void) bge_check_acc_handle(bgep, bgep->io_handle); 540 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 541 mutex_exit(bgep->genlock); 542 return (EIO); 543 } 544 if (bge_start(bgep, B_TRUE) != DDI_SUCCESS) { 545 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 546 (void) bge_check_acc_handle(bgep, bgep->io_handle); 547 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 548 mutex_exit(bgep->genlock); 549 return (EIO); 550 } 551 bgep->bge_mac_state = BGE_MAC_STARTED; 552 BGE_DEBUG(("bge_m_start($%p) done", arg)); 553 554 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 555 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 556 mutex_exit(bgep->genlock); 557 return (EIO); 558 } 559 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 560 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 561 mutex_exit(bgep->genlock); 562 return (EIO); 563 } 564 #ifdef BGE_IPMI_ASF 565 if (bgep->asf_enabled) { 566 if (bgep->asf_status != ASF_STAT_RUN) { 567 /* start ASF heart beat */ 568 bgep->asf_timeout_id = timeout(bge_asf_heartbeat, 569 (void *)bgep, 570 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 571 bgep->asf_status = ASF_STAT_RUN; 572 } 573 } 574 #endif 575 mutex_exit(bgep->genlock); 576 577 return (0); 578 } 579 580 /* 581 * bge_m_unicst() -- set the physical network address 582 */ 583 static int 584 bge_m_unicst(void *arg, const uint8_t *macaddr) 585 { 586 /* 587 * Request to set address in 588 * address slot 0, i.e., default address 589 */ 590 return (bge_unicst_set(arg, macaddr, 0)); 591 } 592 593 /* 594 * bge_unicst_set() -- set the physical network address 595 */ 596 static int 597 bge_unicst_set(void *arg, const uint8_t *macaddr, mac_addr_slot_t slot) 598 { 599 bge_t *bgep = arg; /* private device info */ 600 601 BGE_TRACE(("bge_m_unicst_set($%p, %s)", arg, 602 ether_sprintf((void *)macaddr))); 603 /* 604 * Remember the new current address in the driver state 605 * Sync the chip's idea of the address too ... 606 */ 607 mutex_enter(bgep->genlock); 608 if (!(bgep->progress & PROGRESS_INTR)) { 609 /* can happen during autorecovery */ 610 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 611 mutex_exit(bgep->genlock); 612 return (EIO); 613 } 614 ethaddr_copy(macaddr, bgep->curr_addr[slot].addr); 615 #ifdef BGE_IPMI_ASF 616 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) { 617 #else 618 if (bge_chip_sync(bgep) == DDI_FAILURE) { 619 #endif 620 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 621 (void) bge_check_acc_handle(bgep, bgep->io_handle); 622 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 623 mutex_exit(bgep->genlock); 624 return (EIO); 625 } 626 #ifdef BGE_IPMI_ASF 627 if (bgep->asf_enabled) { 628 /* 629 * The above bge_chip_sync() function wrote the ethernet MAC 630 * addresses registers which destroyed the IPMI/ASF sideband. 631 * Here, we have to reset chip to make IPMI/ASF sideband work. 632 */ 633 if (bgep->asf_status == ASF_STAT_RUN) { 634 /* 635 * We must stop ASF heart beat before bge_chip_stop(), 636 * otherwise some computers (ex. IBM HS20 blade server) 637 * may crash. 638 */ 639 bge_asf_update_status(bgep); 640 bge_asf_stop_timer(bgep); 641 bgep->asf_status = ASF_STAT_STOP; 642 643 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 644 } 645 bge_chip_stop(bgep, B_FALSE); 646 647 if (bge_restart(bgep, B_FALSE) == DDI_FAILURE) { 648 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 649 (void) bge_check_acc_handle(bgep, bgep->io_handle); 650 ddi_fm_service_impact(bgep->devinfo, 651 DDI_SERVICE_DEGRADED); 652 mutex_exit(bgep->genlock); 653 return (EIO); 654 } 655 656 /* 657 * Start our ASF heartbeat counter as soon as possible. 658 */ 659 if (bgep->asf_status != ASF_STAT_RUN) { 660 /* start ASF heart beat */ 661 bgep->asf_timeout_id = timeout(bge_asf_heartbeat, 662 (void *)bgep, 663 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 664 bgep->asf_status = ASF_STAT_RUN; 665 } 666 } 667 #endif 668 BGE_DEBUG(("bge_m_unicst_set($%p) done", arg)); 669 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 670 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 671 mutex_exit(bgep->genlock); 672 return (EIO); 673 } 674 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 675 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 676 mutex_exit(bgep->genlock); 677 return (EIO); 678 } 679 mutex_exit(bgep->genlock); 680 681 return (0); 682 } 683 684 /* 685 * The following four routines are used as callbacks for multiple MAC 686 * address support: 687 * - bge_m_unicst_add(void *, mac_multi_addr_t *); 688 * - bge_m_unicst_remove(void *, mac_addr_slot_t); 689 * - bge_m_unicst_modify(void *, mac_multi_addr_t *); 690 * - bge_m_unicst_get(void *, mac_multi_addr_t *); 691 */ 692 693 /* 694 * bge_m_unicst_add() - will find an unused address slot, set the 695 * address value to the one specified, reserve that slot and enable 696 * the NIC to start filtering on the new MAC address. 697 * address slot. Returns 0 on success. 698 */ 699 static int 700 bge_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 701 { 702 bge_t *bgep = arg; /* private device info */ 703 mac_addr_slot_t slot; 704 int err; 705 706 if (mac_unicst_verify(bgep->mh, 707 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 708 return (EINVAL); 709 710 mutex_enter(bgep->genlock); 711 if (bgep->unicst_addr_avail == 0) { 712 /* no slots available */ 713 mutex_exit(bgep->genlock); 714 return (ENOSPC); 715 } 716 717 /* 718 * Primary/default address is in slot 0. The next three 719 * addresses are the multiple MAC addresses. So multiple 720 * MAC address 0 is in slot 1, 1 in slot 2, and so on. 721 * So the first multiple MAC address resides in slot 1. 722 */ 723 for (slot = 1; slot < bgep->unicst_addr_total; slot++) { 724 if (bgep->curr_addr[slot].set == B_FALSE) { 725 bgep->curr_addr[slot].set = B_TRUE; 726 break; 727 } 728 } 729 730 ASSERT(slot < bgep->unicst_addr_total); 731 bgep->unicst_addr_avail--; 732 mutex_exit(bgep->genlock); 733 maddr->mma_slot = slot; 734 735 if ((err = bge_unicst_set(bgep, maddr->mma_addr, slot)) != 0) { 736 mutex_enter(bgep->genlock); 737 bgep->curr_addr[slot].set = B_FALSE; 738 bgep->unicst_addr_avail++; 739 mutex_exit(bgep->genlock); 740 } 741 return (err); 742 } 743 744 /* 745 * bge_m_unicst_remove() - removes a MAC address that was added by a 746 * call to bge_m_unicst_add(). The slot number that was returned in 747 * add() is passed in the call to remove the address. 748 * Returns 0 on success. 749 */ 750 static int 751 bge_m_unicst_remove(void *arg, mac_addr_slot_t slot) 752 { 753 bge_t *bgep = arg; /* private device info */ 754 755 if (slot <= 0 || slot >= bgep->unicst_addr_total) 756 return (EINVAL); 757 758 mutex_enter(bgep->genlock); 759 if (bgep->curr_addr[slot].set == B_TRUE) { 760 bgep->curr_addr[slot].set = B_FALSE; 761 bgep->unicst_addr_avail++; 762 mutex_exit(bgep->genlock); 763 /* 764 * Copy the default address to the passed slot 765 */ 766 return (bge_unicst_set(bgep, bgep->curr_addr[0].addr, slot)); 767 } 768 mutex_exit(bgep->genlock); 769 return (EINVAL); 770 } 771 772 /* 773 * bge_m_unicst_modify() - modifies the value of an address that 774 * has been added by bge_m_unicst_add(). The new address, address 775 * length and the slot number that was returned in the call to add 776 * should be passed to bge_m_unicst_modify(). mma_flags should be 777 * set to 0. Returns 0 on success. 778 */ 779 static int 780 bge_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 781 { 782 bge_t *bgep = arg; /* private device info */ 783 mac_addr_slot_t slot; 784 785 if (mac_unicst_verify(bgep->mh, 786 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 787 return (EINVAL); 788 789 slot = maddr->mma_slot; 790 791 if (slot <= 0 || slot >= bgep->unicst_addr_total) 792 return (EINVAL); 793 794 mutex_enter(bgep->genlock); 795 if (bgep->curr_addr[slot].set == B_TRUE) { 796 mutex_exit(bgep->genlock); 797 return (bge_unicst_set(bgep, maddr->mma_addr, slot)); 798 } 799 mutex_exit(bgep->genlock); 800 801 return (EINVAL); 802 } 803 804 /* 805 * bge_m_unicst_get() - will get the MAC address and all other 806 * information related to the address slot passed in mac_multi_addr_t. 807 * mma_flags should be set to 0 in the call. 808 * On return, mma_flags can take the following values: 809 * 1) MMAC_SLOT_UNUSED 810 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 811 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 812 * 4) MMAC_SLOT_USED 813 */ 814 static int 815 bge_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 816 { 817 bge_t *bgep = arg; /* private device info */ 818 mac_addr_slot_t slot; 819 820 slot = maddr->mma_slot; 821 822 if (slot <= 0 || slot >= bgep->unicst_addr_total) 823 return (EINVAL); 824 825 mutex_enter(bgep->genlock); 826 if (bgep->curr_addr[slot].set == B_TRUE) { 827 ethaddr_copy(bgep->curr_addr[slot].addr, 828 maddr->mma_addr); 829 maddr->mma_flags = MMAC_SLOT_USED; 830 } else { 831 maddr->mma_flags = MMAC_SLOT_UNUSED; 832 } 833 mutex_exit(bgep->genlock); 834 835 return (0); 836 } 837 838 /* 839 * Compute the index of the required bit in the multicast hash map. 840 * This must mirror the way the hardware actually does it! 841 * See Broadcom document 570X-PG102-R page 125. 842 */ 843 static uint32_t 844 bge_hash_index(const uint8_t *mca) 845 { 846 uint32_t hash; 847 848 CRC32(hash, mca, ETHERADDRL, -1U, crc32_table); 849 850 return (hash); 851 } 852 853 /* 854 * bge_m_multicst_add() -- enable/disable a multicast address 855 */ 856 static int 857 bge_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 858 { 859 bge_t *bgep = arg; /* private device info */ 860 uint32_t hash; 861 uint32_t index; 862 uint32_t word; 863 uint32_t bit; 864 uint8_t *refp; 865 866 BGE_TRACE(("bge_m_multicst($%p, %s, %s)", arg, 867 (add) ? "add" : "remove", ether_sprintf((void *)mca))); 868 869 /* 870 * Precalculate all required masks, pointers etc ... 871 */ 872 hash = bge_hash_index(mca); 873 index = hash % BGE_HASH_TABLE_SIZE; 874 word = index/32u; 875 bit = 1 << (index % 32u); 876 refp = &bgep->mcast_refs[index]; 877 878 BGE_DEBUG(("bge_m_multicst: hash 0x%x index %d (%d:0x%x) = %d", 879 hash, index, word, bit, *refp)); 880 881 /* 882 * We must set the appropriate bit in the hash map (and the 883 * corresponding h/w register) when the refcount goes from 0 884 * to >0, and clear it when the last ref goes away (refcount 885 * goes from >0 back to 0). If we change the hash map, we 886 * must also update the chip's hardware map registers. 887 */ 888 mutex_enter(bgep->genlock); 889 if (!(bgep->progress & PROGRESS_INTR)) { 890 /* can happen during autorecovery */ 891 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 892 mutex_exit(bgep->genlock); 893 return (EIO); 894 } 895 if (add) { 896 if ((*refp)++ == 0) { 897 bgep->mcast_hash[word] |= bit; 898 #ifdef BGE_IPMI_ASF 899 if (bge_chip_sync(bgep, B_TRUE) == DDI_FAILURE) { 900 #else 901 if (bge_chip_sync(bgep) == DDI_FAILURE) { 902 #endif 903 (void) bge_check_acc_handle(bgep, 904 bgep->cfg_handle); 905 (void) bge_check_acc_handle(bgep, 906 bgep->io_handle); 907 ddi_fm_service_impact(bgep->devinfo, 908 DDI_SERVICE_DEGRADED); 909 mutex_exit(bgep->genlock); 910 return (EIO); 911 } 912 } 913 } else { 914 if (--(*refp) == 0) { 915 bgep->mcast_hash[word] &= ~bit; 916 #ifdef BGE_IPMI_ASF 917 if (bge_chip_sync(bgep, B_TRUE) == DDI_FAILURE) { 918 #else 919 if (bge_chip_sync(bgep) == DDI_FAILURE) { 920 #endif 921 (void) bge_check_acc_handle(bgep, 922 bgep->cfg_handle); 923 (void) bge_check_acc_handle(bgep, 924 bgep->io_handle); 925 ddi_fm_service_impact(bgep->devinfo, 926 DDI_SERVICE_DEGRADED); 927 mutex_exit(bgep->genlock); 928 return (EIO); 929 } 930 } 931 } 932 BGE_DEBUG(("bge_m_multicst($%p) done", arg)); 933 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 934 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 935 mutex_exit(bgep->genlock); 936 return (EIO); 937 } 938 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 939 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 940 mutex_exit(bgep->genlock); 941 return (EIO); 942 } 943 mutex_exit(bgep->genlock); 944 945 return (0); 946 } 947 948 /* 949 * bge_m_promisc() -- set or reset promiscuous mode on the board 950 * 951 * Program the hardware to enable/disable promiscuous and/or 952 * receive-all-multicast modes. 953 */ 954 static int 955 bge_m_promisc(void *arg, boolean_t on) 956 { 957 bge_t *bgep = arg; 958 959 BGE_TRACE(("bge_m_promisc_set($%p, %d)", arg, on)); 960 961 /* 962 * Store MAC layer specified mode and pass to chip layer to update h/w 963 */ 964 mutex_enter(bgep->genlock); 965 if (!(bgep->progress & PROGRESS_INTR)) { 966 /* can happen during autorecovery */ 967 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 968 mutex_exit(bgep->genlock); 969 return (EIO); 970 } 971 bgep->promisc = on; 972 #ifdef BGE_IPMI_ASF 973 if (bge_chip_sync(bgep, B_TRUE) == DDI_FAILURE) { 974 #else 975 if (bge_chip_sync(bgep) == DDI_FAILURE) { 976 #endif 977 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 978 (void) bge_check_acc_handle(bgep, bgep->io_handle); 979 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 980 mutex_exit(bgep->genlock); 981 return (EIO); 982 } 983 BGE_DEBUG(("bge_m_promisc_set($%p) done", arg)); 984 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 985 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 986 mutex_exit(bgep->genlock); 987 return (EIO); 988 } 989 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 990 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 991 mutex_exit(bgep->genlock); 992 return (EIO); 993 } 994 mutex_exit(bgep->genlock); 995 return (0); 996 } 997 998 /*ARGSUSED*/ 999 static boolean_t 1000 bge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 1001 { 1002 bge_t *bgep = arg; 1003 1004 switch (cap) { 1005 case MAC_CAPAB_HCKSUM: { 1006 uint32_t *txflags = cap_data; 1007 1008 *txflags = HCKSUM_INET_FULL_V4 | HCKSUM_IPHDRCKSUM; 1009 break; 1010 } 1011 1012 case MAC_CAPAB_POLL: 1013 /* 1014 * There's nothing for us to fill in, simply returning 1015 * B_TRUE stating that we support polling is sufficient. 1016 */ 1017 break; 1018 1019 case MAC_CAPAB_MULTIADDRESS: { 1020 multiaddress_capab_t *mmacp = cap_data; 1021 1022 mutex_enter(bgep->genlock); 1023 /* 1024 * The number of MAC addresses made available by 1025 * this capability is one less than the total as 1026 * the primary address in slot 0 is counted in 1027 * the total. 1028 */ 1029 mmacp->maddr_naddr = bgep->unicst_addr_total - 1; 1030 mmacp->maddr_naddrfree = bgep->unicst_addr_avail; 1031 /* No multiple factory addresses, set mma_flag to 0 */ 1032 mmacp->maddr_flag = 0; 1033 mmacp->maddr_handle = bgep; 1034 mmacp->maddr_add = bge_m_unicst_add; 1035 mmacp->maddr_remove = bge_m_unicst_remove; 1036 mmacp->maddr_modify = bge_m_unicst_modify; 1037 mmacp->maddr_get = bge_m_unicst_get; 1038 mmacp->maddr_reserve = NULL; 1039 mutex_exit(bgep->genlock); 1040 break; 1041 } 1042 1043 default: 1044 return (B_FALSE); 1045 } 1046 return (B_TRUE); 1047 } 1048 1049 /* 1050 * Loopback ioctl code 1051 */ 1052 1053 static lb_property_t loopmodes[] = { 1054 { normal, "normal", BGE_LOOP_NONE }, 1055 { external, "1000Mbps", BGE_LOOP_EXTERNAL_1000 }, 1056 { external, "100Mbps", BGE_LOOP_EXTERNAL_100 }, 1057 { external, "10Mbps", BGE_LOOP_EXTERNAL_10 }, 1058 { internal, "PHY", BGE_LOOP_INTERNAL_PHY }, 1059 { internal, "MAC", BGE_LOOP_INTERNAL_MAC } 1060 }; 1061 1062 static enum ioc_reply 1063 bge_set_loop_mode(bge_t *bgep, uint32_t mode) 1064 { 1065 /* 1066 * If the mode isn't being changed, there's nothing to do ... 1067 */ 1068 if (mode == bgep->param_loop_mode) 1069 return (IOC_ACK); 1070 1071 /* 1072 * Validate the requested mode and prepare a suitable message 1073 * to explain the link down/up cycle that the change will 1074 * probably induce ... 1075 */ 1076 switch (mode) { 1077 default: 1078 return (IOC_INVAL); 1079 1080 case BGE_LOOP_NONE: 1081 case BGE_LOOP_EXTERNAL_1000: 1082 case BGE_LOOP_EXTERNAL_100: 1083 case BGE_LOOP_EXTERNAL_10: 1084 case BGE_LOOP_INTERNAL_PHY: 1085 case BGE_LOOP_INTERNAL_MAC: 1086 break; 1087 } 1088 1089 /* 1090 * All OK; tell the caller to reprogram 1091 * the PHY and/or MAC for the new mode ... 1092 */ 1093 bgep->param_loop_mode = mode; 1094 return (IOC_RESTART_ACK); 1095 } 1096 1097 static enum ioc_reply 1098 bge_loop_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 1099 { 1100 lb_info_sz_t *lbsp; 1101 lb_property_t *lbpp; 1102 uint32_t *lbmp; 1103 int cmd; 1104 1105 _NOTE(ARGUNUSED(wq)) 1106 1107 /* 1108 * Validate format of ioctl 1109 */ 1110 if (mp->b_cont == NULL) 1111 return (IOC_INVAL); 1112 1113 cmd = iocp->ioc_cmd; 1114 switch (cmd) { 1115 default: 1116 /* NOTREACHED */ 1117 bge_error(bgep, "bge_loop_ioctl: invalid cmd 0x%x", cmd); 1118 return (IOC_INVAL); 1119 1120 case LB_GET_INFO_SIZE: 1121 if (iocp->ioc_count != sizeof (lb_info_sz_t)) 1122 return (IOC_INVAL); 1123 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 1124 *lbsp = sizeof (loopmodes); 1125 return (IOC_REPLY); 1126 1127 case LB_GET_INFO: 1128 if (iocp->ioc_count != sizeof (loopmodes)) 1129 return (IOC_INVAL); 1130 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 1131 bcopy(loopmodes, lbpp, sizeof (loopmodes)); 1132 return (IOC_REPLY); 1133 1134 case LB_GET_MODE: 1135 if (iocp->ioc_count != sizeof (uint32_t)) 1136 return (IOC_INVAL); 1137 lbmp = (uint32_t *)mp->b_cont->b_rptr; 1138 *lbmp = bgep->param_loop_mode; 1139 return (IOC_REPLY); 1140 1141 case LB_SET_MODE: 1142 if (iocp->ioc_count != sizeof (uint32_t)) 1143 return (IOC_INVAL); 1144 lbmp = (uint32_t *)mp->b_cont->b_rptr; 1145 return (bge_set_loop_mode(bgep, *lbmp)); 1146 } 1147 } 1148 1149 /* 1150 * Specific bge IOCTLs, the gld module handles the generic ones. 1151 */ 1152 static void 1153 bge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 1154 { 1155 bge_t *bgep = arg; 1156 struct iocblk *iocp; 1157 enum ioc_reply status; 1158 boolean_t need_privilege; 1159 int err; 1160 int cmd; 1161 1162 /* 1163 * Validate the command before bothering with the mutex ... 1164 */ 1165 iocp = (struct iocblk *)mp->b_rptr; 1166 iocp->ioc_error = 0; 1167 need_privilege = B_TRUE; 1168 cmd = iocp->ioc_cmd; 1169 switch (cmd) { 1170 default: 1171 miocnak(wq, mp, 0, EINVAL); 1172 return; 1173 1174 case BGE_MII_READ: 1175 case BGE_MII_WRITE: 1176 case BGE_SEE_READ: 1177 case BGE_SEE_WRITE: 1178 case BGE_FLASH_READ: 1179 case BGE_FLASH_WRITE: 1180 case BGE_DIAG: 1181 case BGE_PEEK: 1182 case BGE_POKE: 1183 case BGE_PHY_RESET: 1184 case BGE_SOFT_RESET: 1185 case BGE_HARD_RESET: 1186 break; 1187 1188 case LB_GET_INFO_SIZE: 1189 case LB_GET_INFO: 1190 case LB_GET_MODE: 1191 need_privilege = B_FALSE; 1192 /* FALLTHRU */ 1193 case LB_SET_MODE: 1194 break; 1195 1196 case ND_GET: 1197 need_privilege = B_FALSE; 1198 /* FALLTHRU */ 1199 case ND_SET: 1200 break; 1201 } 1202 1203 if (need_privilege) { 1204 /* 1205 * Check for specific net_config privilege on Solaris 10+. 1206 */ 1207 err = secpolicy_net_config(iocp->ioc_cr, B_FALSE); 1208 if (err != 0) { 1209 miocnak(wq, mp, 0, err); 1210 return; 1211 } 1212 } 1213 1214 mutex_enter(bgep->genlock); 1215 if (!(bgep->progress & PROGRESS_INTR)) { 1216 /* can happen during autorecovery */ 1217 mutex_exit(bgep->genlock); 1218 miocnak(wq, mp, 0, EIO); 1219 return; 1220 } 1221 1222 switch (cmd) { 1223 default: 1224 _NOTE(NOTREACHED) 1225 status = IOC_INVAL; 1226 break; 1227 1228 case BGE_MII_READ: 1229 case BGE_MII_WRITE: 1230 case BGE_SEE_READ: 1231 case BGE_SEE_WRITE: 1232 case BGE_FLASH_READ: 1233 case BGE_FLASH_WRITE: 1234 case BGE_DIAG: 1235 case BGE_PEEK: 1236 case BGE_POKE: 1237 case BGE_PHY_RESET: 1238 case BGE_SOFT_RESET: 1239 case BGE_HARD_RESET: 1240 status = bge_chip_ioctl(bgep, wq, mp, iocp); 1241 break; 1242 1243 case LB_GET_INFO_SIZE: 1244 case LB_GET_INFO: 1245 case LB_GET_MODE: 1246 case LB_SET_MODE: 1247 status = bge_loop_ioctl(bgep, wq, mp, iocp); 1248 break; 1249 1250 case ND_GET: 1251 case ND_SET: 1252 status = bge_nd_ioctl(bgep, wq, mp, iocp); 1253 break; 1254 } 1255 1256 /* 1257 * Do we need to reprogram the PHY and/or the MAC? 1258 * Do it now, while we still have the mutex. 1259 * 1260 * Note: update the PHY first, 'cos it controls the 1261 * speed/duplex parameters that the MAC code uses. 1262 */ 1263 switch (status) { 1264 case IOC_RESTART_REPLY: 1265 case IOC_RESTART_ACK: 1266 if (bge_phys_update(bgep) != DDI_SUCCESS) { 1267 ddi_fm_service_impact(bgep->devinfo, 1268 DDI_SERVICE_DEGRADED); 1269 status = IOC_INVAL; 1270 } 1271 #ifdef BGE_IPMI_ASF 1272 if (bge_chip_sync(bgep, B_TRUE) == DDI_FAILURE) { 1273 #else 1274 if (bge_chip_sync(bgep) == DDI_FAILURE) { 1275 #endif 1276 ddi_fm_service_impact(bgep->devinfo, 1277 DDI_SERVICE_DEGRADED); 1278 status = IOC_INVAL; 1279 } 1280 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 1281 bge_chip_msi_trig(bgep); 1282 break; 1283 } 1284 1285 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 1286 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 1287 status = IOC_INVAL; 1288 } 1289 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 1290 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 1291 status = IOC_INVAL; 1292 } 1293 mutex_exit(bgep->genlock); 1294 1295 /* 1296 * Finally, decide how to reply 1297 */ 1298 switch (status) { 1299 default: 1300 case IOC_INVAL: 1301 /* 1302 * Error, reply with a NAK and EINVAL or the specified error 1303 */ 1304 miocnak(wq, mp, 0, iocp->ioc_error == 0 ? 1305 EINVAL : iocp->ioc_error); 1306 break; 1307 1308 case IOC_DONE: 1309 /* 1310 * OK, reply already sent 1311 */ 1312 break; 1313 1314 case IOC_RESTART_ACK: 1315 case IOC_ACK: 1316 /* 1317 * OK, reply with an ACK 1318 */ 1319 miocack(wq, mp, 0, 0); 1320 break; 1321 1322 case IOC_RESTART_REPLY: 1323 case IOC_REPLY: 1324 /* 1325 * OK, send prepared reply as ACK or NAK 1326 */ 1327 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1328 M_IOCACK : M_IOCNAK; 1329 qreply(wq, mp); 1330 break; 1331 } 1332 } 1333 1334 static void 1335 bge_m_resources(void *arg) 1336 { 1337 bge_t *bgep = arg; 1338 recv_ring_t *rrp; 1339 mac_rx_fifo_t mrf; 1340 int ring; 1341 1342 mutex_enter(bgep->genlock); 1343 1344 /* 1345 * Register Rx rings as resources and save mac 1346 * resource id for future reference 1347 */ 1348 mrf.mrf_type = MAC_RX_FIFO; 1349 mrf.mrf_blank = bge_chip_blank; 1350 mrf.mrf_arg = (void *)bgep; 1351 mrf.mrf_normal_blank_time = bge_rx_ticks_norm; 1352 mrf.mrf_normal_pkt_count = bge_rx_count_norm; 1353 1354 for (ring = 0; ring < bgep->chipid.rx_rings; ring++) { 1355 rrp = &bgep->recv[ring]; 1356 rrp->handle = mac_resource_add(bgep->mh, 1357 (mac_resource_t *)&mrf); 1358 } 1359 1360 mutex_exit(bgep->genlock); 1361 } 1362 1363 /* 1364 * ========== Per-instance setup/teardown code ========== 1365 */ 1366 1367 #undef BGE_DBG 1368 #define BGE_DBG BGE_DBG_INIT /* debug flag for this code */ 1369 /* 1370 * Allocate an area of memory and a DMA handle for accessing it 1371 */ 1372 static int 1373 bge_alloc_dma_mem(bge_t *bgep, size_t memsize, ddi_device_acc_attr_t *attr_p, 1374 uint_t dma_flags, dma_area_t *dma_p) 1375 { 1376 caddr_t va; 1377 int err; 1378 1379 BGE_TRACE(("bge_alloc_dma_mem($%p, %ld, $%p, 0x%x, $%p)", 1380 (void *)bgep, memsize, attr_p, dma_flags, dma_p)); 1381 1382 /* 1383 * Allocate handle 1384 */ 1385 err = ddi_dma_alloc_handle(bgep->devinfo, &dma_attr, 1386 DDI_DMA_DONTWAIT, NULL, &dma_p->dma_hdl); 1387 if (err != DDI_SUCCESS) 1388 return (DDI_FAILURE); 1389 1390 /* 1391 * Allocate memory 1392 */ 1393 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p, 1394 dma_flags, DDI_DMA_DONTWAIT, NULL, &va, &dma_p->alength, 1395 &dma_p->acc_hdl); 1396 if (err != DDI_SUCCESS) 1397 return (DDI_FAILURE); 1398 1399 /* 1400 * Bind the two together 1401 */ 1402 dma_p->mem_va = va; 1403 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL, 1404 va, dma_p->alength, dma_flags, DDI_DMA_DONTWAIT, NULL, 1405 &dma_p->cookie, &dma_p->ncookies); 1406 1407 BGE_DEBUG(("bge_alloc_dma_mem(): bind %d bytes; err %d, %d cookies", 1408 dma_p->alength, err, dma_p->ncookies)); 1409 1410 if (err != DDI_DMA_MAPPED || dma_p->ncookies != 1) 1411 return (DDI_FAILURE); 1412 1413 dma_p->nslots = ~0U; 1414 dma_p->size = ~0U; 1415 dma_p->token = ~0U; 1416 dma_p->offset = 0; 1417 return (DDI_SUCCESS); 1418 } 1419 1420 /* 1421 * Free one allocated area of DMAable memory 1422 */ 1423 static void 1424 bge_free_dma_mem(dma_area_t *dma_p) 1425 { 1426 if (dma_p->dma_hdl != NULL) { 1427 if (dma_p->ncookies) { 1428 (void) ddi_dma_unbind_handle(dma_p->dma_hdl); 1429 dma_p->ncookies = 0; 1430 } 1431 ddi_dma_free_handle(&dma_p->dma_hdl); 1432 dma_p->dma_hdl = NULL; 1433 } 1434 1435 if (dma_p->acc_hdl != NULL) { 1436 ddi_dma_mem_free(&dma_p->acc_hdl); 1437 dma_p->acc_hdl = NULL; 1438 } 1439 } 1440 /* 1441 * Utility routine to carve a slice off a chunk of allocated memory, 1442 * updating the chunk descriptor accordingly. The size of the slice 1443 * is given by the product of the <qty> and <size> parameters. 1444 */ 1445 static void 1446 bge_slice_chunk(dma_area_t *slice, dma_area_t *chunk, 1447 uint32_t qty, uint32_t size) 1448 { 1449 static uint32_t sequence = 0xbcd5704a; 1450 size_t totsize; 1451 1452 totsize = qty*size; 1453 ASSERT(size >= 0); 1454 ASSERT(totsize <= chunk->alength); 1455 1456 *slice = *chunk; 1457 slice->nslots = qty; 1458 slice->size = size; 1459 slice->alength = totsize; 1460 slice->token = ++sequence; 1461 1462 chunk->mem_va = (caddr_t)chunk->mem_va + totsize; 1463 chunk->alength -= totsize; 1464 chunk->offset += totsize; 1465 chunk->cookie.dmac_laddress += totsize; 1466 chunk->cookie.dmac_size -= totsize; 1467 } 1468 1469 /* 1470 * Initialise the specified Receive Producer (Buffer) Ring, using 1471 * the information in the <dma_area> descriptors that it contains 1472 * to set up all the other fields. This routine should be called 1473 * only once for each ring. 1474 */ 1475 static void 1476 bge_init_buff_ring(bge_t *bgep, uint64_t ring) 1477 { 1478 buff_ring_t *brp; 1479 bge_status_t *bsp; 1480 sw_rbd_t *srbdp; 1481 dma_area_t pbuf; 1482 uint32_t bufsize; 1483 uint32_t nslots; 1484 uint32_t slot; 1485 uint32_t split; 1486 1487 static bge_regno_t nic_ring_addrs[BGE_BUFF_RINGS_MAX] = { 1488 NIC_MEM_SHADOW_BUFF_STD, 1489 NIC_MEM_SHADOW_BUFF_JUMBO, 1490 NIC_MEM_SHADOW_BUFF_MINI 1491 }; 1492 static bge_regno_t mailbox_regs[BGE_BUFF_RINGS_MAX] = { 1493 RECV_STD_PROD_INDEX_REG, 1494 RECV_JUMBO_PROD_INDEX_REG, 1495 RECV_MINI_PROD_INDEX_REG 1496 }; 1497 static bge_regno_t buff_cons_xref[BGE_BUFF_RINGS_MAX] = { 1498 STATUS_STD_BUFF_CONS_INDEX, 1499 STATUS_JUMBO_BUFF_CONS_INDEX, 1500 STATUS_MINI_BUFF_CONS_INDEX 1501 }; 1502 1503 BGE_TRACE(("bge_init_buff_ring($%p, %d)", 1504 (void *)bgep, ring)); 1505 1506 brp = &bgep->buff[ring]; 1507 nslots = brp->desc.nslots; 1508 ASSERT(brp->buf[0].nslots == nslots/BGE_SPLIT); 1509 bufsize = brp->buf[0].size; 1510 1511 /* 1512 * Set up the copy of the h/w RCB 1513 * 1514 * Note: unlike Send & Receive Return Rings, (where the max_len 1515 * field holds the number of slots), in a Receive Buffer Ring 1516 * this field indicates the size of each buffer in the ring. 1517 */ 1518 brp->hw_rcb.host_ring_addr = brp->desc.cookie.dmac_laddress; 1519 brp->hw_rcb.max_len = bufsize; 1520 brp->hw_rcb.flags = nslots > 0 ? 0 : RCB_FLAG_RING_DISABLED; 1521 brp->hw_rcb.nic_ring_addr = nic_ring_addrs[ring]; 1522 1523 /* 1524 * Other one-off initialisation of per-ring data 1525 */ 1526 brp->bgep = bgep; 1527 bsp = DMA_VPTR(bgep->status_block); 1528 brp->cons_index_p = &bsp->buff_cons_index[buff_cons_xref[ring]]; 1529 brp->chip_mbx_reg = mailbox_regs[ring]; 1530 mutex_init(brp->rf_lock, NULL, MUTEX_DRIVER, 1531 DDI_INTR_PRI(bgep->intr_pri)); 1532 1533 /* 1534 * Allocate the array of s/w Receive Buffer Descriptors 1535 */ 1536 srbdp = kmem_zalloc(nslots*sizeof (*srbdp), KM_SLEEP); 1537 brp->sw_rbds = srbdp; 1538 1539 /* 1540 * Now initialise each array element once and for all 1541 */ 1542 for (split = 0; split < BGE_SPLIT; ++split) { 1543 pbuf = brp->buf[split]; 1544 for (slot = 0; slot < nslots/BGE_SPLIT; ++srbdp, ++slot) 1545 bge_slice_chunk(&srbdp->pbuf, &pbuf, 1, bufsize); 1546 ASSERT(pbuf.alength == 0); 1547 } 1548 } 1549 1550 /* 1551 * Clean up initialisation done above before the memory is freed 1552 */ 1553 static void 1554 bge_fini_buff_ring(bge_t *bgep, uint64_t ring) 1555 { 1556 buff_ring_t *brp; 1557 sw_rbd_t *srbdp; 1558 1559 BGE_TRACE(("bge_fini_buff_ring($%p, %d)", 1560 (void *)bgep, ring)); 1561 1562 brp = &bgep->buff[ring]; 1563 srbdp = brp->sw_rbds; 1564 kmem_free(srbdp, brp->desc.nslots*sizeof (*srbdp)); 1565 1566 mutex_destroy(brp->rf_lock); 1567 } 1568 1569 /* 1570 * Initialise the specified Receive (Return) Ring, using the 1571 * information in the <dma_area> descriptors that it contains 1572 * to set up all the other fields. This routine should be called 1573 * only once for each ring. 1574 */ 1575 static void 1576 bge_init_recv_ring(bge_t *bgep, uint64_t ring) 1577 { 1578 recv_ring_t *rrp; 1579 bge_status_t *bsp; 1580 uint32_t nslots; 1581 1582 BGE_TRACE(("bge_init_recv_ring($%p, %d)", 1583 (void *)bgep, ring)); 1584 1585 /* 1586 * The chip architecture requires that receive return rings have 1587 * 512 or 1024 or 2048 elements per ring. See 570X-PG108-R page 103. 1588 */ 1589 rrp = &bgep->recv[ring]; 1590 nslots = rrp->desc.nslots; 1591 ASSERT(nslots == 0 || nslots == 512 || 1592 nslots == 1024 || nslots == 2048); 1593 1594 /* 1595 * Set up the copy of the h/w RCB 1596 */ 1597 rrp->hw_rcb.host_ring_addr = rrp->desc.cookie.dmac_laddress; 1598 rrp->hw_rcb.max_len = nslots; 1599 rrp->hw_rcb.flags = nslots > 0 ? 0 : RCB_FLAG_RING_DISABLED; 1600 rrp->hw_rcb.nic_ring_addr = 0; 1601 1602 /* 1603 * Other one-off initialisation of per-ring data 1604 */ 1605 rrp->bgep = bgep; 1606 bsp = DMA_VPTR(bgep->status_block); 1607 rrp->prod_index_p = RECV_INDEX_P(bsp, ring); 1608 rrp->chip_mbx_reg = RECV_RING_CONS_INDEX_REG(ring); 1609 mutex_init(rrp->rx_lock, NULL, MUTEX_DRIVER, 1610 DDI_INTR_PRI(bgep->intr_pri)); 1611 } 1612 1613 1614 /* 1615 * Clean up initialisation done above before the memory is freed 1616 */ 1617 static void 1618 bge_fini_recv_ring(bge_t *bgep, uint64_t ring) 1619 { 1620 recv_ring_t *rrp; 1621 1622 BGE_TRACE(("bge_fini_recv_ring($%p, %d)", 1623 (void *)bgep, ring)); 1624 1625 rrp = &bgep->recv[ring]; 1626 if (rrp->rx_softint) 1627 ddi_remove_softintr(rrp->rx_softint); 1628 mutex_destroy(rrp->rx_lock); 1629 } 1630 1631 /* 1632 * Initialise the specified Send Ring, using the information in the 1633 * <dma_area> descriptors that it contains to set up all the other 1634 * fields. This routine should be called only once for each ring. 1635 */ 1636 static void 1637 bge_init_send_ring(bge_t *bgep, uint64_t ring) 1638 { 1639 send_ring_t *srp; 1640 bge_status_t *bsp; 1641 sw_sbd_t *ssbdp; 1642 dma_area_t desc; 1643 dma_area_t pbuf; 1644 uint32_t nslots; 1645 uint32_t slot; 1646 uint32_t split; 1647 sw_txbuf_t *txbuf; 1648 1649 BGE_TRACE(("bge_init_send_ring($%p, %d)", 1650 (void *)bgep, ring)); 1651 1652 /* 1653 * The chip architecture requires that host-based send rings 1654 * have 512 elements per ring. See 570X-PG102-R page 56. 1655 */ 1656 srp = &bgep->send[ring]; 1657 nslots = srp->desc.nslots; 1658 ASSERT(nslots == 0 || nslots == 512); 1659 1660 /* 1661 * Set up the copy of the h/w RCB 1662 */ 1663 srp->hw_rcb.host_ring_addr = srp->desc.cookie.dmac_laddress; 1664 srp->hw_rcb.max_len = nslots; 1665 srp->hw_rcb.flags = nslots > 0 ? 0 : RCB_FLAG_RING_DISABLED; 1666 srp->hw_rcb.nic_ring_addr = NIC_MEM_SHADOW_SEND_RING(ring, nslots); 1667 1668 /* 1669 * Other one-off initialisation of per-ring data 1670 */ 1671 srp->bgep = bgep; 1672 bsp = DMA_VPTR(bgep->status_block); 1673 srp->cons_index_p = SEND_INDEX_P(bsp, ring); 1674 srp->chip_mbx_reg = SEND_RING_HOST_INDEX_REG(ring); 1675 mutex_init(srp->tx_lock, NULL, MUTEX_DRIVER, 1676 DDI_INTR_PRI(bgep->intr_pri)); 1677 mutex_init(srp->txbuf_lock, NULL, MUTEX_DRIVER, 1678 DDI_INTR_PRI(bgep->intr_pri)); 1679 mutex_init(srp->freetxbuf_lock, NULL, MUTEX_DRIVER, 1680 DDI_INTR_PRI(bgep->intr_pri)); 1681 mutex_init(srp->tc_lock, NULL, MUTEX_DRIVER, 1682 DDI_INTR_PRI(bgep->intr_pri)); 1683 if (nslots == 0) 1684 return; 1685 1686 /* 1687 * Allocate the array of s/w Send Buffer Descriptors 1688 */ 1689 ssbdp = kmem_zalloc(nslots*sizeof (*ssbdp), KM_SLEEP); 1690 txbuf = kmem_zalloc(BGE_SEND_BUF_MAX*sizeof (*txbuf), KM_SLEEP); 1691 srp->txbuf_head = 1692 kmem_zalloc(BGE_SEND_BUF_MAX*sizeof (bge_queue_item_t), KM_SLEEP); 1693 srp->pktp = kmem_zalloc(BGE_SEND_BUF_MAX*sizeof (send_pkt_t), KM_SLEEP); 1694 srp->sw_sbds = ssbdp; 1695 srp->txbuf = txbuf; 1696 srp->tx_buffers = BGE_SEND_BUF_NUM; 1697 srp->tx_buffers_low = srp->tx_buffers / 4; 1698 if (bgep->chipid.snd_buff_size > BGE_SEND_BUFF_SIZE_DEFAULT) 1699 srp->tx_array_max = BGE_SEND_BUF_ARRAY_JUMBO; 1700 else 1701 srp->tx_array_max = BGE_SEND_BUF_ARRAY; 1702 srp->tx_array = 1; 1703 1704 /* 1705 * Chunk tx desc area 1706 */ 1707 desc = srp->desc; 1708 for (slot = 0; slot < nslots; ++ssbdp, ++slot) { 1709 bge_slice_chunk(&ssbdp->desc, &desc, 1, 1710 sizeof (bge_sbd_t)); 1711 } 1712 ASSERT(desc.alength == 0); 1713 1714 /* 1715 * Chunk tx buffer area 1716 */ 1717 for (split = 0; split < BGE_SPLIT; ++split) { 1718 pbuf = srp->buf[0][split]; 1719 for (slot = 0; slot < BGE_SEND_BUF_NUM/BGE_SPLIT; ++slot) { 1720 bge_slice_chunk(&txbuf->buf, &pbuf, 1, 1721 bgep->chipid.snd_buff_size); 1722 txbuf++; 1723 } 1724 ASSERT(pbuf.alength == 0); 1725 } 1726 } 1727 1728 /* 1729 * Clean up initialisation done above before the memory is freed 1730 */ 1731 static void 1732 bge_fini_send_ring(bge_t *bgep, uint64_t ring) 1733 { 1734 send_ring_t *srp; 1735 uint32_t array; 1736 uint32_t split; 1737 uint32_t nslots; 1738 1739 BGE_TRACE(("bge_fini_send_ring($%p, %d)", 1740 (void *)bgep, ring)); 1741 1742 srp = &bgep->send[ring]; 1743 mutex_destroy(srp->tc_lock); 1744 mutex_destroy(srp->freetxbuf_lock); 1745 mutex_destroy(srp->txbuf_lock); 1746 mutex_destroy(srp->tx_lock); 1747 nslots = srp->desc.nslots; 1748 if (nslots == 0) 1749 return; 1750 1751 for (array = 1; array < srp->tx_array; ++array) 1752 for (split = 0; split < BGE_SPLIT; ++split) 1753 bge_free_dma_mem(&srp->buf[array][split]); 1754 kmem_free(srp->sw_sbds, nslots*sizeof (*srp->sw_sbds)); 1755 kmem_free(srp->txbuf_head, BGE_SEND_BUF_MAX*sizeof (*srp->txbuf_head)); 1756 kmem_free(srp->txbuf, BGE_SEND_BUF_MAX*sizeof (*srp->txbuf)); 1757 kmem_free(srp->pktp, BGE_SEND_BUF_MAX*sizeof (*srp->pktp)); 1758 srp->sw_sbds = NULL; 1759 srp->txbuf_head = NULL; 1760 srp->txbuf = NULL; 1761 srp->pktp = NULL; 1762 } 1763 1764 /* 1765 * Initialise all transmit, receive, and buffer rings. 1766 */ 1767 void 1768 bge_init_rings(bge_t *bgep) 1769 { 1770 uint32_t ring; 1771 1772 BGE_TRACE(("bge_init_rings($%p)", (void *)bgep)); 1773 1774 /* 1775 * Perform one-off initialisation of each ring ... 1776 */ 1777 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring) 1778 bge_init_send_ring(bgep, ring); 1779 for (ring = 0; ring < BGE_RECV_RINGS_MAX; ++ring) 1780 bge_init_recv_ring(bgep, ring); 1781 for (ring = 0; ring < BGE_BUFF_RINGS_MAX; ++ring) 1782 bge_init_buff_ring(bgep, ring); 1783 } 1784 1785 /* 1786 * Undo the work of bge_init_rings() above before the memory is freed 1787 */ 1788 void 1789 bge_fini_rings(bge_t *bgep) 1790 { 1791 uint32_t ring; 1792 1793 BGE_TRACE(("bge_fini_rings($%p)", (void *)bgep)); 1794 1795 for (ring = 0; ring < BGE_BUFF_RINGS_MAX; ++ring) 1796 bge_fini_buff_ring(bgep, ring); 1797 for (ring = 0; ring < BGE_RECV_RINGS_MAX; ++ring) 1798 bge_fini_recv_ring(bgep, ring); 1799 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring) 1800 bge_fini_send_ring(bgep, ring); 1801 } 1802 1803 /* 1804 * Called from the bge_m_stop() to free the tx buffers which are 1805 * allocated from the tx process. 1806 */ 1807 void 1808 bge_free_txbuf_arrays(send_ring_t *srp) 1809 { 1810 uint32_t array; 1811 uint32_t split; 1812 1813 ASSERT(mutex_owned(srp->tx_lock)); 1814 1815 /* 1816 * Free the extra tx buffer DMA area 1817 */ 1818 for (array = 1; array < srp->tx_array; ++array) 1819 for (split = 0; split < BGE_SPLIT; ++split) 1820 bge_free_dma_mem(&srp->buf[array][split]); 1821 1822 /* 1823 * Restore initial tx buffer numbers 1824 */ 1825 srp->tx_array = 1; 1826 srp->tx_buffers = BGE_SEND_BUF_NUM; 1827 srp->tx_buffers_low = srp->tx_buffers / 4; 1828 srp->tx_flow = 0; 1829 bzero(srp->pktp, BGE_SEND_BUF_MAX * sizeof (*srp->pktp)); 1830 } 1831 1832 /* 1833 * Called from tx process to allocate more tx buffers 1834 */ 1835 bge_queue_item_t * 1836 bge_alloc_txbuf_array(bge_t *bgep, send_ring_t *srp) 1837 { 1838 bge_queue_t *txbuf_queue; 1839 bge_queue_item_t *txbuf_item_last; 1840 bge_queue_item_t *txbuf_item; 1841 bge_queue_item_t *txbuf_item_rtn; 1842 sw_txbuf_t *txbuf; 1843 dma_area_t area; 1844 size_t txbuffsize; 1845 uint32_t slot; 1846 uint32_t array; 1847 uint32_t split; 1848 uint32_t err; 1849 1850 ASSERT(mutex_owned(srp->tx_lock)); 1851 1852 array = srp->tx_array; 1853 if (array >= srp->tx_array_max) 1854 return (NULL); 1855 1856 /* 1857 * Allocate memory & handles for TX buffers 1858 */ 1859 txbuffsize = BGE_SEND_BUF_NUM*bgep->chipid.snd_buff_size; 1860 ASSERT((txbuffsize % BGE_SPLIT) == 0); 1861 for (split = 0; split < BGE_SPLIT; ++split) { 1862 err = bge_alloc_dma_mem(bgep, txbuffsize/BGE_SPLIT, 1863 &bge_data_accattr, DDI_DMA_WRITE | BGE_DMA_MODE, 1864 &srp->buf[array][split]); 1865 if (err != DDI_SUCCESS) { 1866 /* Free the last already allocated OK chunks */ 1867 for (slot = 0; slot <= split; ++slot) 1868 bge_free_dma_mem(&srp->buf[array][slot]); 1869 srp->tx_alloc_fail++; 1870 return (NULL); 1871 } 1872 } 1873 1874 /* 1875 * Chunk tx buffer area 1876 */ 1877 txbuf = srp->txbuf + array*BGE_SEND_BUF_NUM; 1878 for (split = 0; split < BGE_SPLIT; ++split) { 1879 area = srp->buf[array][split]; 1880 for (slot = 0; slot < BGE_SEND_BUF_NUM/BGE_SPLIT; ++slot) { 1881 bge_slice_chunk(&txbuf->buf, &area, 1, 1882 bgep->chipid.snd_buff_size); 1883 txbuf++; 1884 } 1885 } 1886 1887 /* 1888 * Add above buffers to the tx buffer pop queue 1889 */ 1890 txbuf_item = srp->txbuf_head + array*BGE_SEND_BUF_NUM; 1891 txbuf = srp->txbuf + array*BGE_SEND_BUF_NUM; 1892 txbuf_item_last = NULL; 1893 for (slot = 0; slot < BGE_SEND_BUF_NUM; ++slot) { 1894 txbuf_item->item = txbuf; 1895 txbuf_item->next = txbuf_item_last; 1896 txbuf_item_last = txbuf_item; 1897 txbuf++; 1898 txbuf_item++; 1899 } 1900 txbuf_item = srp->txbuf_head + array*BGE_SEND_BUF_NUM; 1901 txbuf_item_rtn = txbuf_item; 1902 txbuf_item++; 1903 txbuf_queue = srp->txbuf_pop_queue; 1904 mutex_enter(txbuf_queue->lock); 1905 txbuf_item->next = txbuf_queue->head; 1906 txbuf_queue->head = txbuf_item_last; 1907 txbuf_queue->count += BGE_SEND_BUF_NUM - 1; 1908 mutex_exit(txbuf_queue->lock); 1909 1910 srp->tx_array++; 1911 srp->tx_buffers += BGE_SEND_BUF_NUM; 1912 srp->tx_buffers_low = srp->tx_buffers / 4; 1913 1914 return (txbuf_item_rtn); 1915 } 1916 1917 /* 1918 * This function allocates all the transmit and receive buffers 1919 * and descriptors, in four chunks. 1920 */ 1921 int 1922 bge_alloc_bufs(bge_t *bgep) 1923 { 1924 dma_area_t area; 1925 size_t rxbuffsize; 1926 size_t txbuffsize; 1927 size_t rxbuffdescsize; 1928 size_t rxdescsize; 1929 size_t txdescsize; 1930 uint32_t ring; 1931 uint32_t rx_rings = bgep->chipid.rx_rings; 1932 uint32_t tx_rings = bgep->chipid.tx_rings; 1933 int split; 1934 int err; 1935 1936 BGE_TRACE(("bge_alloc_bufs($%p)", 1937 (void *)bgep)); 1938 1939 rxbuffsize = BGE_STD_SLOTS_USED*bgep->chipid.std_buf_size; 1940 rxbuffsize += bgep->chipid.jumbo_slots*bgep->chipid.recv_jumbo_size; 1941 rxbuffsize += BGE_MINI_SLOTS_USED*BGE_MINI_BUFF_SIZE; 1942 1943 txbuffsize = BGE_SEND_BUF_NUM*bgep->chipid.snd_buff_size; 1944 txbuffsize *= tx_rings; 1945 1946 rxdescsize = rx_rings*bgep->chipid.recv_slots; 1947 rxdescsize *= sizeof (bge_rbd_t); 1948 1949 rxbuffdescsize = BGE_STD_SLOTS_USED; 1950 rxbuffdescsize += bgep->chipid.jumbo_slots; 1951 rxbuffdescsize += BGE_MINI_SLOTS_USED; 1952 rxbuffdescsize *= sizeof (bge_rbd_t); 1953 1954 txdescsize = tx_rings*BGE_SEND_SLOTS_USED; 1955 txdescsize *= sizeof (bge_sbd_t); 1956 txdescsize += sizeof (bge_statistics_t); 1957 txdescsize += sizeof (bge_status_t); 1958 txdescsize += BGE_STATUS_PADDING; 1959 1960 /* 1961 * Enable PCI relaxed ordering only for RX/TX data buffers 1962 */ 1963 if (bge_relaxed_ordering) 1964 dma_attr.dma_attr_flags |= DDI_DMA_RELAXED_ORDERING; 1965 1966 /* 1967 * Allocate memory & handles for RX buffers 1968 */ 1969 ASSERT((rxbuffsize % BGE_SPLIT) == 0); 1970 for (split = 0; split < BGE_SPLIT; ++split) { 1971 err = bge_alloc_dma_mem(bgep, rxbuffsize/BGE_SPLIT, 1972 &bge_data_accattr, DDI_DMA_READ | BGE_DMA_MODE, 1973 &bgep->rx_buff[split]); 1974 if (err != DDI_SUCCESS) 1975 return (DDI_FAILURE); 1976 } 1977 1978 /* 1979 * Allocate memory & handles for TX buffers 1980 */ 1981 ASSERT((txbuffsize % BGE_SPLIT) == 0); 1982 for (split = 0; split < BGE_SPLIT; ++split) { 1983 err = bge_alloc_dma_mem(bgep, txbuffsize/BGE_SPLIT, 1984 &bge_data_accattr, DDI_DMA_WRITE | BGE_DMA_MODE, 1985 &bgep->tx_buff[split]); 1986 if (err != DDI_SUCCESS) 1987 return (DDI_FAILURE); 1988 } 1989 1990 dma_attr.dma_attr_flags &= ~DDI_DMA_RELAXED_ORDERING; 1991 1992 /* 1993 * Allocate memory & handles for receive return rings 1994 */ 1995 ASSERT((rxdescsize % rx_rings) == 0); 1996 for (split = 0; split < rx_rings; ++split) { 1997 err = bge_alloc_dma_mem(bgep, rxdescsize/rx_rings, 1998 &bge_desc_accattr, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1999 &bgep->rx_desc[split]); 2000 if (err != DDI_SUCCESS) 2001 return (DDI_FAILURE); 2002 } 2003 2004 /* 2005 * Allocate memory & handles for buffer (producer) descriptor rings 2006 */ 2007 err = bge_alloc_dma_mem(bgep, rxbuffdescsize, &bge_desc_accattr, 2008 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &bgep->rx_desc[split]); 2009 if (err != DDI_SUCCESS) 2010 return (DDI_FAILURE); 2011 2012 /* 2013 * Allocate memory & handles for TX descriptor rings, 2014 * status block, and statistics area 2015 */ 2016 err = bge_alloc_dma_mem(bgep, txdescsize, &bge_desc_accattr, 2017 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &bgep->tx_desc); 2018 if (err != DDI_SUCCESS) 2019 return (DDI_FAILURE); 2020 2021 /* 2022 * Now carve up each of the allocated areas ... 2023 */ 2024 for (split = 0; split < BGE_SPLIT; ++split) { 2025 area = bgep->rx_buff[split]; 2026 bge_slice_chunk(&bgep->buff[BGE_STD_BUFF_RING].buf[split], 2027 &area, BGE_STD_SLOTS_USED/BGE_SPLIT, 2028 bgep->chipid.std_buf_size); 2029 bge_slice_chunk(&bgep->buff[BGE_JUMBO_BUFF_RING].buf[split], 2030 &area, bgep->chipid.jumbo_slots/BGE_SPLIT, 2031 bgep->chipid.recv_jumbo_size); 2032 bge_slice_chunk(&bgep->buff[BGE_MINI_BUFF_RING].buf[split], 2033 &area, BGE_MINI_SLOTS_USED/BGE_SPLIT, 2034 BGE_MINI_BUFF_SIZE); 2035 ASSERT(area.alength >= 0); 2036 } 2037 2038 for (split = 0; split < BGE_SPLIT; ++split) { 2039 area = bgep->tx_buff[split]; 2040 for (ring = 0; ring < tx_rings; ++ring) 2041 bge_slice_chunk(&bgep->send[ring].buf[0][split], 2042 &area, BGE_SEND_BUF_NUM/BGE_SPLIT, 2043 bgep->chipid.snd_buff_size); 2044 for (; ring < BGE_SEND_RINGS_MAX; ++ring) 2045 bge_slice_chunk(&bgep->send[ring].buf[0][split], 2046 &area, 0, bgep->chipid.snd_buff_size); 2047 ASSERT(area.alength >= 0); 2048 } 2049 2050 for (ring = 0; ring < rx_rings; ++ring) 2051 bge_slice_chunk(&bgep->recv[ring].desc, &bgep->rx_desc[ring], 2052 bgep->chipid.recv_slots, sizeof (bge_rbd_t)); 2053 2054 area = bgep->rx_desc[rx_rings]; 2055 for (; ring < BGE_RECV_RINGS_MAX; ++ring) 2056 bge_slice_chunk(&bgep->recv[ring].desc, &area, 2057 0, sizeof (bge_rbd_t)); 2058 bge_slice_chunk(&bgep->buff[BGE_STD_BUFF_RING].desc, &area, 2059 BGE_STD_SLOTS_USED, sizeof (bge_rbd_t)); 2060 bge_slice_chunk(&bgep->buff[BGE_JUMBO_BUFF_RING].desc, &area, 2061 bgep->chipid.jumbo_slots, sizeof (bge_rbd_t)); 2062 bge_slice_chunk(&bgep->buff[BGE_MINI_BUFF_RING].desc, &area, 2063 BGE_MINI_SLOTS_USED, sizeof (bge_rbd_t)); 2064 ASSERT(area.alength == 0); 2065 2066 area = bgep->tx_desc; 2067 for (ring = 0; ring < tx_rings; ++ring) 2068 bge_slice_chunk(&bgep->send[ring].desc, &area, 2069 BGE_SEND_SLOTS_USED, sizeof (bge_sbd_t)); 2070 for (; ring < BGE_SEND_RINGS_MAX; ++ring) 2071 bge_slice_chunk(&bgep->send[ring].desc, &area, 2072 0, sizeof (bge_sbd_t)); 2073 bge_slice_chunk(&bgep->statistics, &area, 1, sizeof (bge_statistics_t)); 2074 bge_slice_chunk(&bgep->status_block, &area, 1, sizeof (bge_status_t)); 2075 ASSERT(area.alength == BGE_STATUS_PADDING); 2076 DMA_ZERO(bgep->status_block); 2077 2078 return (DDI_SUCCESS); 2079 } 2080 2081 /* 2082 * This routine frees the transmit and receive buffers and descriptors. 2083 * Make sure the chip is stopped before calling it! 2084 */ 2085 void 2086 bge_free_bufs(bge_t *bgep) 2087 { 2088 int split; 2089 2090 BGE_TRACE(("bge_free_bufs($%p)", 2091 (void *)bgep)); 2092 2093 bge_free_dma_mem(&bgep->tx_desc); 2094 for (split = 0; split < BGE_RECV_RINGS_SPLIT; ++split) 2095 bge_free_dma_mem(&bgep->rx_desc[split]); 2096 for (split = 0; split < BGE_SPLIT; ++split) 2097 bge_free_dma_mem(&bgep->tx_buff[split]); 2098 for (split = 0; split < BGE_SPLIT; ++split) 2099 bge_free_dma_mem(&bgep->rx_buff[split]); 2100 } 2101 2102 /* 2103 * Determine (initial) MAC address ("BIA") to use for this interface 2104 */ 2105 2106 static void 2107 bge_find_mac_address(bge_t *bgep, chip_id_t *cidp) 2108 { 2109 struct ether_addr sysaddr; 2110 char propbuf[8]; /* "true" or "false", plus NUL */ 2111 uchar_t *bytes; 2112 int *ints; 2113 uint_t nelts; 2114 int err; 2115 2116 BGE_TRACE(("bge_find_mac_address($%p)", 2117 (void *)bgep)); 2118 2119 BGE_DEBUG(("bge_find_mac_address: hw_mac_addr %012llx, => %s (%sset)", 2120 cidp->hw_mac_addr, 2121 ether_sprintf((void *)cidp->vendor_addr.addr), 2122 cidp->vendor_addr.set ? "" : "not ")); 2123 2124 /* 2125 * The "vendor's factory-set address" may already have 2126 * been extracted from the chip, but if the property 2127 * "local-mac-address" is set we use that instead. It 2128 * will normally be set by OBP, but it could also be 2129 * specified in a .conf file(!) 2130 * 2131 * There doesn't seem to be a way to define byte-array 2132 * properties in a .conf, so we check whether it looks 2133 * like an array of 6 ints instead. 2134 * 2135 * Then, we check whether it looks like an array of 6 2136 * bytes (which it should, if OBP set it). If we can't 2137 * make sense of it either way, we'll ignore it. 2138 */ 2139 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2140 DDI_PROP_DONTPASS, localmac_propname, &ints, &nelts); 2141 if (err == DDI_PROP_SUCCESS) { 2142 if (nelts == ETHERADDRL) { 2143 while (nelts--) 2144 cidp->vendor_addr.addr[nelts] = ints[nelts]; 2145 cidp->vendor_addr.set = B_TRUE; 2146 } 2147 ddi_prop_free(ints); 2148 } 2149 2150 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, bgep->devinfo, 2151 DDI_PROP_DONTPASS, localmac_propname, &bytes, &nelts); 2152 if (err == DDI_PROP_SUCCESS) { 2153 if (nelts == ETHERADDRL) { 2154 while (nelts--) 2155 cidp->vendor_addr.addr[nelts] = bytes[nelts]; 2156 cidp->vendor_addr.set = B_TRUE; 2157 } 2158 ddi_prop_free(bytes); 2159 } 2160 2161 BGE_DEBUG(("bge_find_mac_address: +local %s (%sset)", 2162 ether_sprintf((void *)cidp->vendor_addr.addr), 2163 cidp->vendor_addr.set ? "" : "not ")); 2164 2165 /* 2166 * Look up the OBP property "local-mac-address?". Note that even 2167 * though its value is a string (which should be "true" or "false"), 2168 * it can't be decoded by ddi_prop_lookup_string(9F). So, we zero 2169 * the buffer first and then fetch the property as an untyped array; 2170 * this may or may not include a final NUL, but since there will 2171 * always be one left at the end of the buffer we can now treat it 2172 * as a string anyway. 2173 */ 2174 nelts = sizeof (propbuf); 2175 bzero(propbuf, nelts--); 2176 err = ddi_getlongprop_buf(DDI_DEV_T_ANY, bgep->devinfo, 2177 DDI_PROP_CANSLEEP, localmac_boolname, propbuf, (int *)&nelts); 2178 2179 /* 2180 * Now, if the address still isn't set from the hardware (SEEPROM) 2181 * or the OBP or .conf property, OR if the user has foolishly set 2182 * 'local-mac-address? = false', use "the system address" instead 2183 * (but only if it's non-null i.e. has been set from the IDPROM). 2184 */ 2185 if (cidp->vendor_addr.set == B_FALSE || strcmp(propbuf, "false") == 0) 2186 if (localetheraddr(NULL, &sysaddr) != 0) { 2187 ethaddr_copy(&sysaddr, cidp->vendor_addr.addr); 2188 cidp->vendor_addr.set = B_TRUE; 2189 } 2190 2191 BGE_DEBUG(("bge_find_mac_address: +system %s (%sset)", 2192 ether_sprintf((void *)cidp->vendor_addr.addr), 2193 cidp->vendor_addr.set ? "" : "not ")); 2194 2195 /* 2196 * Finally(!), if there's a valid "mac-address" property (created 2197 * if we netbooted from this interface), we must use this instead 2198 * of any of the above to ensure that the NFS/install server doesn't 2199 * get confused by the address changing as Solaris takes over! 2200 */ 2201 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, bgep->devinfo, 2202 DDI_PROP_DONTPASS, macaddr_propname, &bytes, &nelts); 2203 if (err == DDI_PROP_SUCCESS) { 2204 if (nelts == ETHERADDRL) { 2205 while (nelts--) 2206 cidp->vendor_addr.addr[nelts] = bytes[nelts]; 2207 cidp->vendor_addr.set = B_TRUE; 2208 } 2209 ddi_prop_free(bytes); 2210 } 2211 2212 BGE_DEBUG(("bge_find_mac_address: =final %s (%sset)", 2213 ether_sprintf((void *)cidp->vendor_addr.addr), 2214 cidp->vendor_addr.set ? "" : "not ")); 2215 } 2216 2217 2218 /*ARGSUSED*/ 2219 int 2220 bge_check_acc_handle(bge_t *bgep, ddi_acc_handle_t handle) 2221 { 2222 ddi_fm_error_t de; 2223 2224 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 2225 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 2226 return (de.fme_status); 2227 } 2228 2229 /*ARGSUSED*/ 2230 int 2231 bge_check_dma_handle(bge_t *bgep, ddi_dma_handle_t handle) 2232 { 2233 ddi_fm_error_t de; 2234 2235 ASSERT(bgep->progress & PROGRESS_BUFS); 2236 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 2237 return (de.fme_status); 2238 } 2239 2240 /* 2241 * The IO fault service error handling callback function 2242 */ 2243 /*ARGSUSED*/ 2244 static int 2245 bge_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 2246 { 2247 /* 2248 * as the driver can always deal with an error in any dma or 2249 * access handle, we can just return the fme_status value. 2250 */ 2251 pci_ereport_post(dip, err, NULL); 2252 return (err->fme_status); 2253 } 2254 2255 static void 2256 bge_fm_init(bge_t *bgep) 2257 { 2258 ddi_iblock_cookie_t iblk; 2259 2260 /* Only register with IO Fault Services if we have some capability */ 2261 if (bgep->fm_capabilities) { 2262 bge_reg_accattr.devacc_attr_access = DDI_FLAGERR_ACC; 2263 bge_desc_accattr.devacc_attr_access = DDI_FLAGERR_ACC; 2264 dma_attr.dma_attr_flags = DDI_DMA_FLAGERR; 2265 2266 /* Register capabilities with IO Fault Services */ 2267 ddi_fm_init(bgep->devinfo, &bgep->fm_capabilities, &iblk); 2268 2269 /* 2270 * Initialize pci ereport capabilities if ereport capable 2271 */ 2272 if (DDI_FM_EREPORT_CAP(bgep->fm_capabilities) || 2273 DDI_FM_ERRCB_CAP(bgep->fm_capabilities)) 2274 pci_ereport_setup(bgep->devinfo); 2275 2276 /* 2277 * Register error callback if error callback capable 2278 */ 2279 if (DDI_FM_ERRCB_CAP(bgep->fm_capabilities)) 2280 ddi_fm_handler_register(bgep->devinfo, 2281 bge_fm_error_cb, (void*) bgep); 2282 } else { 2283 /* 2284 * These fields have to be cleared of FMA if there are no 2285 * FMA capabilities at runtime. 2286 */ 2287 bge_reg_accattr.devacc_attr_access = DDI_DEFAULT_ACC; 2288 bge_desc_accattr.devacc_attr_access = DDI_DEFAULT_ACC; 2289 dma_attr.dma_attr_flags = 0; 2290 } 2291 } 2292 2293 static void 2294 bge_fm_fini(bge_t *bgep) 2295 { 2296 /* Only unregister FMA capabilities if we registered some */ 2297 if (bgep->fm_capabilities) { 2298 2299 /* 2300 * Release any resources allocated by pci_ereport_setup() 2301 */ 2302 if (DDI_FM_EREPORT_CAP(bgep->fm_capabilities) || 2303 DDI_FM_ERRCB_CAP(bgep->fm_capabilities)) 2304 pci_ereport_teardown(bgep->devinfo); 2305 2306 /* 2307 * Un-register error callback if error callback capable 2308 */ 2309 if (DDI_FM_ERRCB_CAP(bgep->fm_capabilities)) 2310 ddi_fm_handler_unregister(bgep->devinfo); 2311 2312 /* Unregister from IO Fault Services */ 2313 ddi_fm_fini(bgep->devinfo); 2314 } 2315 } 2316 2317 static void 2318 #ifdef BGE_IPMI_ASF 2319 bge_unattach(bge_t *bgep, uint_t asf_mode) 2320 #else 2321 bge_unattach(bge_t *bgep) 2322 #endif 2323 { 2324 BGE_TRACE(("bge_unattach($%p)", 2325 (void *)bgep)); 2326 2327 /* 2328 * Flag that no more activity may be initiated 2329 */ 2330 bgep->progress &= ~PROGRESS_READY; 2331 2332 /* 2333 * Quiesce the PHY and MAC (leave it reset but still powered). 2334 * Clean up and free all BGE data structures 2335 */ 2336 if (bgep->cyclic_id) { 2337 mutex_enter(&cpu_lock); 2338 cyclic_remove(bgep->cyclic_id); 2339 mutex_exit(&cpu_lock); 2340 } 2341 if (bgep->progress & PROGRESS_KSTATS) 2342 bge_fini_kstats(bgep); 2343 if (bgep->progress & PROGRESS_NDD) 2344 bge_nd_cleanup(bgep); 2345 if (bgep->progress & PROGRESS_PHY) 2346 bge_phys_reset(bgep); 2347 if (bgep->progress & PROGRESS_HWINT) { 2348 mutex_enter(bgep->genlock); 2349 #ifdef BGE_IPMI_ASF 2350 if (bge_chip_reset(bgep, B_FALSE, asf_mode) != DDI_SUCCESS) 2351 #else 2352 if (bge_chip_reset(bgep, B_FALSE) != DDI_SUCCESS) 2353 #endif 2354 ddi_fm_service_impact(bgep->devinfo, 2355 DDI_SERVICE_UNAFFECTED); 2356 #ifdef BGE_IPMI_ASF 2357 if (bgep->asf_enabled) { 2358 /* 2359 * This register has been overlaid. We restore its 2360 * initial value here. 2361 */ 2362 bge_nic_put32(bgep, BGE_NIC_DATA_SIG_ADDR, 2363 BGE_NIC_DATA_SIG); 2364 } 2365 #endif 2366 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 2367 ddi_fm_service_impact(bgep->devinfo, 2368 DDI_SERVICE_UNAFFECTED); 2369 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2370 ddi_fm_service_impact(bgep->devinfo, 2371 DDI_SERVICE_UNAFFECTED); 2372 mutex_exit(bgep->genlock); 2373 } 2374 if (bgep->progress & PROGRESS_INTR) { 2375 bge_intr_disable(bgep); 2376 bge_fini_rings(bgep); 2377 } 2378 if (bgep->progress & PROGRESS_HWINT) { 2379 bge_rem_intrs(bgep); 2380 rw_destroy(bgep->errlock); 2381 mutex_destroy(bgep->softintrlock); 2382 mutex_destroy(bgep->genlock); 2383 } 2384 if (bgep->progress & PROGRESS_FACTOTUM) 2385 ddi_remove_softintr(bgep->factotum_id); 2386 if (bgep->progress & PROGRESS_RESCHED) 2387 ddi_remove_softintr(bgep->drain_id); 2388 if (bgep->progress & PROGRESS_BUFS) 2389 bge_free_bufs(bgep); 2390 if (bgep->progress & PROGRESS_REGS) 2391 ddi_regs_map_free(&bgep->io_handle); 2392 if (bgep->progress & PROGRESS_CFG) 2393 pci_config_teardown(&bgep->cfg_handle); 2394 2395 bge_fm_fini(bgep); 2396 2397 ddi_remove_minor_node(bgep->devinfo, NULL); 2398 kmem_free(bgep->pstats, sizeof (bge_statistics_reg_t)); 2399 kmem_free(bgep->nd_params, PARAM_COUNT * sizeof (nd_param_t)); 2400 kmem_free(bgep, sizeof (*bgep)); 2401 } 2402 2403 static int 2404 bge_resume(dev_info_t *devinfo) 2405 { 2406 bge_t *bgep; /* Our private data */ 2407 chip_id_t *cidp; 2408 chip_id_t chipid; 2409 2410 bgep = ddi_get_driver_private(devinfo); 2411 if (bgep == NULL) 2412 return (DDI_FAILURE); 2413 2414 /* 2415 * Refuse to resume if the data structures aren't consistent 2416 */ 2417 if (bgep->devinfo != devinfo) 2418 return (DDI_FAILURE); 2419 2420 #ifdef BGE_IPMI_ASF 2421 /* 2422 * Power management hasn't been supported in BGE now. If you 2423 * want to implement it, please add the ASF/IPMI related 2424 * code here. 2425 */ 2426 2427 #endif 2428 2429 /* 2430 * Read chip ID & set up config space command register(s) 2431 * Refuse to resume if the chip has changed its identity! 2432 */ 2433 cidp = &bgep->chipid; 2434 mutex_enter(bgep->genlock); 2435 bge_chip_cfg_init(bgep, &chipid, B_FALSE); 2436 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 2437 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2438 mutex_exit(bgep->genlock); 2439 return (DDI_FAILURE); 2440 } 2441 mutex_exit(bgep->genlock); 2442 if (chipid.vendor != cidp->vendor) 2443 return (DDI_FAILURE); 2444 if (chipid.device != cidp->device) 2445 return (DDI_FAILURE); 2446 if (chipid.revision != cidp->revision) 2447 return (DDI_FAILURE); 2448 if (chipid.asic_rev != cidp->asic_rev) 2449 return (DDI_FAILURE); 2450 2451 /* 2452 * All OK, reinitialise h/w & kick off GLD scheduling 2453 */ 2454 mutex_enter(bgep->genlock); 2455 if (bge_restart(bgep, B_TRUE) != DDI_SUCCESS) { 2456 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 2457 (void) bge_check_acc_handle(bgep, bgep->io_handle); 2458 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2459 mutex_exit(bgep->genlock); 2460 return (DDI_FAILURE); 2461 } 2462 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 2463 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2464 mutex_exit(bgep->genlock); 2465 return (DDI_FAILURE); 2466 } 2467 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 2468 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2469 mutex_exit(bgep->genlock); 2470 return (DDI_FAILURE); 2471 } 2472 mutex_exit(bgep->genlock); 2473 return (DDI_SUCCESS); 2474 } 2475 2476 /* 2477 * attach(9E) -- Attach a device to the system 2478 * 2479 * Called once for each board successfully probed. 2480 */ 2481 static int 2482 bge_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 2483 { 2484 bge_t *bgep; /* Our private data */ 2485 mac_register_t *macp; 2486 chip_id_t *cidp; 2487 cyc_handler_t cychand; 2488 cyc_time_t cyctime; 2489 caddr_t regs; 2490 int instance; 2491 int err; 2492 int intr_types; 2493 #ifdef BGE_IPMI_ASF 2494 uint32_t mhcrValue; 2495 #ifdef __sparc 2496 uint16_t value16; 2497 #endif 2498 #ifdef BGE_NETCONSOLE 2499 int retval; 2500 #endif 2501 #endif 2502 2503 instance = ddi_get_instance(devinfo); 2504 2505 BGE_GTRACE(("bge_attach($%p, %d) instance %d", 2506 (void *)devinfo, cmd, instance)); 2507 BGE_BRKPT(NULL, "bge_attach"); 2508 2509 switch (cmd) { 2510 default: 2511 return (DDI_FAILURE); 2512 2513 case DDI_RESUME: 2514 return (bge_resume(devinfo)); 2515 2516 case DDI_ATTACH: 2517 break; 2518 } 2519 2520 bgep = kmem_zalloc(sizeof (*bgep), KM_SLEEP); 2521 bgep->pstats = kmem_zalloc(sizeof (bge_statistics_reg_t), KM_SLEEP); 2522 bgep->nd_params = 2523 kmem_zalloc(PARAM_COUNT * sizeof (nd_param_t), KM_SLEEP); 2524 ddi_set_driver_private(devinfo, bgep); 2525 bgep->bge_guard = BGE_GUARD; 2526 bgep->devinfo = devinfo; 2527 2528 /* 2529 * Initialize more fields in BGE private data 2530 */ 2531 bgep->debug = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2532 DDI_PROP_DONTPASS, debug_propname, bge_debug); 2533 (void) snprintf(bgep->ifname, sizeof (bgep->ifname), "%s%d", 2534 BGE_DRIVER_NAME, instance); 2535 2536 /* 2537 * Initialize for fma support 2538 */ 2539 bgep->fm_capabilities = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2540 DDI_PROP_DONTPASS, fm_cap, 2541 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 2542 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 2543 BGE_DEBUG(("bgep->fm_capabilities = %d", bgep->fm_capabilities)); 2544 bge_fm_init(bgep); 2545 2546 /* 2547 * Look up the IOMMU's page size for DVMA mappings (must be 2548 * a power of 2) and convert to a mask. This can be used to 2549 * determine whether a message buffer crosses a page boundary. 2550 * Note: in 2s complement binary notation, if X is a power of 2551 * 2, then -X has the representation "11...1100...00". 2552 */ 2553 bgep->pagemask = dvma_pagesize(devinfo); 2554 ASSERT(ddi_ffs(bgep->pagemask) == ddi_fls(bgep->pagemask)); 2555 bgep->pagemask = -bgep->pagemask; 2556 2557 /* 2558 * Map config space registers 2559 * Read chip ID & set up config space command register(s) 2560 * 2561 * Note: this leaves the chip accessible by Memory Space 2562 * accesses, but with interrupts and Bus Mastering off. 2563 * This should ensure that nothing untoward will happen 2564 * if it has been left active by the (net-)bootloader. 2565 * We'll re-enable Bus Mastering once we've reset the chip, 2566 * and allow interrupts only when everything else is set up. 2567 */ 2568 err = pci_config_setup(devinfo, &bgep->cfg_handle); 2569 #ifdef BGE_IPMI_ASF 2570 #ifdef __sparc 2571 value16 = pci_config_get16(bgep->cfg_handle, PCI_CONF_COMM); 2572 value16 = value16 | (PCI_COMM_MAE | PCI_COMM_ME); 2573 pci_config_put16(bgep->cfg_handle, PCI_CONF_COMM, value16); 2574 mhcrValue = MHCR_ENABLE_INDIRECT_ACCESS | 2575 MHCR_ENABLE_TAGGED_STATUS_MODE | 2576 MHCR_MASK_INTERRUPT_MODE | 2577 MHCR_MASK_PCI_INT_OUTPUT | 2578 MHCR_CLEAR_INTERRUPT_INTA | 2579 MHCR_ENABLE_ENDIAN_WORD_SWAP | 2580 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 2581 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcrValue); 2582 bge_ind_put32(bgep, MEMORY_ARBITER_MODE_REG, 2583 bge_ind_get32(bgep, MEMORY_ARBITER_MODE_REG) | 2584 MEMORY_ARBITER_ENABLE); 2585 #else 2586 mhcrValue = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR); 2587 #endif 2588 if (mhcrValue & MHCR_ENABLE_ENDIAN_WORD_SWAP) { 2589 bgep->asf_wordswapped = B_TRUE; 2590 } else { 2591 bgep->asf_wordswapped = B_FALSE; 2592 } 2593 bge_asf_get_config(bgep); 2594 #endif 2595 if (err != DDI_SUCCESS) { 2596 bge_problem(bgep, "pci_config_setup() failed"); 2597 goto attach_fail; 2598 } 2599 bgep->progress |= PROGRESS_CFG; 2600 cidp = &bgep->chipid; 2601 bzero(cidp, sizeof (*cidp)); 2602 bge_chip_cfg_init(bgep, cidp, B_FALSE); 2603 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 2604 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2605 goto attach_fail; 2606 } 2607 2608 #ifdef BGE_IPMI_ASF 2609 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 2610 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2611 bgep->asf_newhandshake = B_TRUE; 2612 } else { 2613 bgep->asf_newhandshake = B_FALSE; 2614 } 2615 #endif 2616 2617 /* 2618 * Update those parts of the chip ID derived from volatile 2619 * registers with the values seen by OBP (in case the chip 2620 * has been reset externally and therefore lost them). 2621 */ 2622 cidp->subven = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2623 DDI_PROP_DONTPASS, subven_propname, cidp->subven); 2624 cidp->subdev = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2625 DDI_PROP_DONTPASS, subdev_propname, cidp->subdev); 2626 cidp->clsize = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2627 DDI_PROP_DONTPASS, clsize_propname, cidp->clsize); 2628 cidp->latency = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2629 DDI_PROP_DONTPASS, latency_propname, cidp->latency); 2630 cidp->rx_rings = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2631 DDI_PROP_DONTPASS, rxrings_propname, cidp->rx_rings); 2632 cidp->tx_rings = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2633 DDI_PROP_DONTPASS, txrings_propname, cidp->tx_rings); 2634 2635 if (bge_jumbo_enable == B_TRUE) { 2636 cidp->default_mtu = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2637 DDI_PROP_DONTPASS, default_mtu, BGE_DEFAULT_MTU); 2638 if ((cidp->default_mtu < BGE_DEFAULT_MTU)|| 2639 (cidp->default_mtu > BGE_MAXIMUM_MTU)) { 2640 cidp->default_mtu = BGE_DEFAULT_MTU; 2641 } 2642 } 2643 /* 2644 * Map operating registers 2645 */ 2646 err = ddi_regs_map_setup(devinfo, BGE_PCI_OPREGS_RNUMBER, 2647 ®s, 0, 0, &bge_reg_accattr, &bgep->io_handle); 2648 if (err != DDI_SUCCESS) { 2649 bge_problem(bgep, "ddi_regs_map_setup() failed"); 2650 goto attach_fail; 2651 } 2652 bgep->io_regs = regs; 2653 bgep->progress |= PROGRESS_REGS; 2654 2655 /* 2656 * Characterise the device, so we know its requirements. 2657 * Then allocate the appropriate TX and RX descriptors & buffers. 2658 */ 2659 if (bge_chip_id_init(bgep) == EIO) { 2660 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2661 goto attach_fail; 2662 } 2663 err = bge_alloc_bufs(bgep); 2664 if (err != DDI_SUCCESS) { 2665 bge_problem(bgep, "DMA buffer allocation failed"); 2666 goto attach_fail; 2667 } 2668 bgep->progress |= PROGRESS_BUFS; 2669 2670 /* 2671 * Add the softint handlers: 2672 * 2673 * Both of these handlers are used to avoid restrictions on the 2674 * context and/or mutexes required for some operations. In 2675 * particular, the hardware interrupt handler and its subfunctions 2676 * can detect a number of conditions that we don't want to handle 2677 * in that context or with that set of mutexes held. So, these 2678 * softints are triggered instead: 2679 * 2680 * the <resched> softint is triggered if we have previously 2681 * had to refuse to send a packet because of resource shortage 2682 * (we've run out of transmit buffers), but the send completion 2683 * interrupt handler has now detected that more buffers have 2684 * become available. 2685 * 2686 * the <factotum> is triggered if the h/w interrupt handler 2687 * sees the <link state changed> or <error> bits in the status 2688 * block. It's also triggered periodically to poll the link 2689 * state, just in case we aren't getting link status change 2690 * interrupts ... 2691 */ 2692 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, &bgep->drain_id, 2693 NULL, NULL, bge_send_drain, (caddr_t)bgep); 2694 if (err != DDI_SUCCESS) { 2695 bge_problem(bgep, "ddi_add_softintr() failed"); 2696 goto attach_fail; 2697 } 2698 bgep->progress |= PROGRESS_RESCHED; 2699 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, &bgep->factotum_id, 2700 NULL, NULL, bge_chip_factotum, (caddr_t)bgep); 2701 if (err != DDI_SUCCESS) { 2702 bge_problem(bgep, "ddi_add_softintr() failed"); 2703 goto attach_fail; 2704 } 2705 bgep->progress |= PROGRESS_FACTOTUM; 2706 2707 /* Get supported interrupt types */ 2708 if (ddi_intr_get_supported_types(devinfo, &intr_types) != DDI_SUCCESS) { 2709 bge_error(bgep, "ddi_intr_get_supported_types failed\n"); 2710 2711 goto attach_fail; 2712 } 2713 2714 BGE_DEBUG(("%s: ddi_intr_get_supported_types() returned: %x", 2715 bgep->ifname, intr_types)); 2716 2717 if ((intr_types & DDI_INTR_TYPE_MSI) && bgep->chipid.msi_enabled) { 2718 if (bge_add_intrs(bgep, DDI_INTR_TYPE_MSI) != DDI_SUCCESS) { 2719 bge_error(bgep, "MSI registration failed, " 2720 "trying FIXED interrupt type\n"); 2721 } else { 2722 BGE_DEBUG(("%s: Using MSI interrupt type", 2723 bgep->ifname)); 2724 bgep->intr_type = DDI_INTR_TYPE_MSI; 2725 bgep->progress |= PROGRESS_HWINT; 2726 } 2727 } 2728 2729 if (!(bgep->progress & PROGRESS_HWINT) && 2730 (intr_types & DDI_INTR_TYPE_FIXED)) { 2731 if (bge_add_intrs(bgep, DDI_INTR_TYPE_FIXED) != DDI_SUCCESS) { 2732 bge_error(bgep, "FIXED interrupt " 2733 "registration failed\n"); 2734 goto attach_fail; 2735 } 2736 2737 BGE_DEBUG(("%s: Using FIXED interrupt type", bgep->ifname)); 2738 2739 bgep->intr_type = DDI_INTR_TYPE_FIXED; 2740 bgep->progress |= PROGRESS_HWINT; 2741 } 2742 2743 if (!(bgep->progress & PROGRESS_HWINT)) { 2744 bge_error(bgep, "No interrupts registered\n"); 2745 goto attach_fail; 2746 } 2747 2748 /* 2749 * Note that interrupts are not enabled yet as 2750 * mutex locks are not initialized. Initialize mutex locks. 2751 */ 2752 mutex_init(bgep->genlock, NULL, MUTEX_DRIVER, 2753 DDI_INTR_PRI(bgep->intr_pri)); 2754 mutex_init(bgep->softintrlock, NULL, MUTEX_DRIVER, 2755 DDI_INTR_PRI(bgep->intr_pri)); 2756 rw_init(bgep->errlock, NULL, RW_DRIVER, 2757 DDI_INTR_PRI(bgep->intr_pri)); 2758 2759 /* 2760 * Initialize rings. 2761 */ 2762 bge_init_rings(bgep); 2763 2764 /* 2765 * Now that mutex locks are initialized, enable interrupts. 2766 */ 2767 bge_intr_enable(bgep); 2768 bgep->progress |= PROGRESS_INTR; 2769 2770 /* 2771 * Initialise link state variables 2772 * Stop, reset & reinitialise the chip. 2773 * Initialise the (internal) PHY. 2774 */ 2775 bgep->link_state = LINK_STATE_UNKNOWN; 2776 2777 mutex_enter(bgep->genlock); 2778 2779 /* 2780 * Reset chip & rings to initial state; also reset address 2781 * filtering, promiscuity, loopback mode. 2782 */ 2783 #ifdef BGE_IPMI_ASF 2784 #ifdef BGE_NETCONSOLE 2785 if (bge_reset(bgep, ASF_MODE_INIT) != DDI_SUCCESS) { 2786 #else 2787 if (bge_reset(bgep, ASF_MODE_SHUTDOWN) != DDI_SUCCESS) { 2788 #endif 2789 #else 2790 if (bge_reset(bgep) != DDI_SUCCESS) { 2791 #endif 2792 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 2793 (void) bge_check_acc_handle(bgep, bgep->io_handle); 2794 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2795 mutex_exit(bgep->genlock); 2796 goto attach_fail; 2797 } 2798 2799 #ifdef BGE_IPMI_ASF 2800 if (bgep->asf_enabled) { 2801 bgep->asf_status = ASF_STAT_RUN_INIT; 2802 } 2803 #endif 2804 2805 bzero(bgep->mcast_hash, sizeof (bgep->mcast_hash)); 2806 bzero(bgep->mcast_refs, sizeof (bgep->mcast_refs)); 2807 bgep->promisc = B_FALSE; 2808 bgep->param_loop_mode = BGE_LOOP_NONE; 2809 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 2810 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2811 mutex_exit(bgep->genlock); 2812 goto attach_fail; 2813 } 2814 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 2815 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2816 mutex_exit(bgep->genlock); 2817 goto attach_fail; 2818 } 2819 2820 mutex_exit(bgep->genlock); 2821 2822 if (bge_phys_init(bgep) == EIO) { 2823 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2824 goto attach_fail; 2825 } 2826 bgep->progress |= PROGRESS_PHY; 2827 2828 /* 2829 * Register NDD-tweakable parameters 2830 */ 2831 if (bge_nd_init(bgep)) { 2832 bge_problem(bgep, "bge_nd_init() failed"); 2833 goto attach_fail; 2834 } 2835 bgep->progress |= PROGRESS_NDD; 2836 2837 /* 2838 * Create & initialise named kstats 2839 */ 2840 bge_init_kstats(bgep, instance); 2841 bgep->progress |= PROGRESS_KSTATS; 2842 2843 /* 2844 * Determine whether to override the chip's own MAC address 2845 */ 2846 bge_find_mac_address(bgep, cidp); 2847 ethaddr_copy(cidp->vendor_addr.addr, bgep->curr_addr[0].addr); 2848 bgep->curr_addr[0].set = B_TRUE; 2849 2850 bgep->unicst_addr_total = MAC_ADDRESS_REGS_MAX; 2851 /* 2852 * Address available is one less than MAX 2853 * as primary address is not advertised 2854 * as a multiple MAC address. 2855 */ 2856 bgep->unicst_addr_avail = MAC_ADDRESS_REGS_MAX - 1; 2857 2858 if ((macp = mac_alloc(MAC_VERSION)) == NULL) 2859 goto attach_fail; 2860 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 2861 macp->m_driver = bgep; 2862 macp->m_dip = devinfo; 2863 macp->m_src_addr = bgep->curr_addr[0].addr; 2864 macp->m_callbacks = &bge_m_callbacks; 2865 macp->m_min_sdu = 0; 2866 macp->m_max_sdu = cidp->ethmax_size - sizeof (struct ether_header); 2867 /* 2868 * Finally, we're ready to register ourselves with the MAC layer 2869 * interface; if this succeeds, we're all ready to start() 2870 */ 2871 err = mac_register(macp, &bgep->mh); 2872 mac_free(macp); 2873 if (err != 0) 2874 goto attach_fail; 2875 2876 cychand.cyh_func = bge_chip_cyclic; 2877 cychand.cyh_arg = bgep; 2878 cychand.cyh_level = CY_LOCK_LEVEL; 2879 cyctime.cyt_when = 0; 2880 cyctime.cyt_interval = BGE_CYCLIC_PERIOD; 2881 mutex_enter(&cpu_lock); 2882 bgep->cyclic_id = cyclic_add(&cychand, &cyctime); 2883 mutex_exit(&cpu_lock); 2884 2885 bgep->progress |= PROGRESS_READY; 2886 ASSERT(bgep->bge_guard == BGE_GUARD); 2887 #ifdef BGE_IPMI_ASF 2888 #ifdef BGE_NETCONSOLE 2889 if (bgep->asf_enabled) { 2890 mutex_enter(bgep->genlock); 2891 retval = bge_chip_start(bgep, B_TRUE); 2892 mutex_exit(bgep->genlock); 2893 if (retval != DDI_SUCCESS) 2894 goto attach_fail; 2895 } 2896 #endif 2897 #endif 2898 return (DDI_SUCCESS); 2899 2900 attach_fail: 2901 #ifdef BGE_IPMI_ASF 2902 bge_unattach(bgep, ASF_MODE_SHUTDOWN); 2903 #else 2904 bge_unattach(bgep); 2905 #endif 2906 return (DDI_FAILURE); 2907 } 2908 2909 /* 2910 * bge_suspend() -- suspend transmit/receive for powerdown 2911 */ 2912 static int 2913 bge_suspend(bge_t *bgep) 2914 { 2915 /* 2916 * Stop processing and idle (powerdown) the PHY ... 2917 */ 2918 mutex_enter(bgep->genlock); 2919 #ifdef BGE_IPMI_ASF 2920 /* 2921 * Power management hasn't been supported in BGE now. If you 2922 * want to implement it, please add the ASF/IPMI related 2923 * code here. 2924 */ 2925 #endif 2926 bge_stop(bgep); 2927 if (bge_phys_idle(bgep) != DDI_SUCCESS) { 2928 (void) bge_check_acc_handle(bgep, bgep->io_handle); 2929 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 2930 mutex_exit(bgep->genlock); 2931 return (DDI_FAILURE); 2932 } 2933 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 2934 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 2935 mutex_exit(bgep->genlock); 2936 return (DDI_FAILURE); 2937 } 2938 mutex_exit(bgep->genlock); 2939 2940 return (DDI_SUCCESS); 2941 } 2942 2943 /* 2944 * detach(9E) -- Detach a device from the system 2945 */ 2946 static int 2947 bge_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 2948 { 2949 bge_t *bgep; 2950 #ifdef BGE_IPMI_ASF 2951 uint_t asf_mode; 2952 asf_mode = ASF_MODE_NONE; 2953 #endif 2954 2955 BGE_GTRACE(("bge_detach($%p, %d)", (void *)devinfo, cmd)); 2956 2957 bgep = ddi_get_driver_private(devinfo); 2958 2959 switch (cmd) { 2960 default: 2961 return (DDI_FAILURE); 2962 2963 case DDI_SUSPEND: 2964 return (bge_suspend(bgep)); 2965 2966 case DDI_DETACH: 2967 break; 2968 } 2969 2970 #ifdef BGE_IPMI_ASF 2971 mutex_enter(bgep->genlock); 2972 if (bgep->asf_enabled && ((bgep->asf_status == ASF_STAT_RUN) || 2973 (bgep->asf_status == ASF_STAT_RUN_INIT))) { 2974 2975 bge_asf_update_status(bgep); 2976 if (bgep->asf_status == ASF_STAT_RUN) { 2977 bge_asf_stop_timer(bgep); 2978 } 2979 bgep->asf_status = ASF_STAT_STOP; 2980 2981 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 2982 2983 if (bgep->asf_pseudostop) { 2984 bge_chip_stop(bgep, B_FALSE); 2985 bgep->bge_mac_state = BGE_MAC_STOPPED; 2986 bgep->asf_pseudostop = B_FALSE; 2987 } 2988 2989 asf_mode = ASF_MODE_POST_SHUTDOWN; 2990 2991 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 2992 ddi_fm_service_impact(bgep->devinfo, 2993 DDI_SERVICE_UNAFFECTED); 2994 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2995 ddi_fm_service_impact(bgep->devinfo, 2996 DDI_SERVICE_UNAFFECTED); 2997 } 2998 mutex_exit(bgep->genlock); 2999 #endif 3000 3001 /* 3002 * Unregister from the GLD subsystem. This can fail, in 3003 * particular if there are DLPI style-2 streams still open - 3004 * in which case we just return failure without shutting 3005 * down chip operations. 3006 */ 3007 if (mac_unregister(bgep->mh) != 0) 3008 return (DDI_FAILURE); 3009 3010 /* 3011 * All activity stopped, so we can clean up & exit 3012 */ 3013 #ifdef BGE_IPMI_ASF 3014 bge_unattach(bgep, asf_mode); 3015 #else 3016 bge_unattach(bgep); 3017 #endif 3018 return (DDI_SUCCESS); 3019 } 3020 3021 3022 /* 3023 * ========== Module Loading Data & Entry Points ========== 3024 */ 3025 3026 #undef BGE_DBG 3027 #define BGE_DBG BGE_DBG_INIT /* debug flag for this code */ 3028 3029 DDI_DEFINE_STREAM_OPS(bge_dev_ops, nulldev, nulldev, bge_attach, bge_detach, 3030 nodev, NULL, D_MP, NULL); 3031 3032 static struct modldrv bge_modldrv = { 3033 &mod_driverops, /* Type of module. This one is a driver */ 3034 bge_ident, /* short description */ 3035 &bge_dev_ops /* driver specific ops */ 3036 }; 3037 3038 static struct modlinkage modlinkage = { 3039 MODREV_1, (void *)&bge_modldrv, NULL 3040 }; 3041 3042 3043 int 3044 _info(struct modinfo *modinfop) 3045 { 3046 return (mod_info(&modlinkage, modinfop)); 3047 } 3048 3049 int 3050 _init(void) 3051 { 3052 int status; 3053 3054 mac_init_ops(&bge_dev_ops, "bge"); 3055 status = mod_install(&modlinkage); 3056 if (status == DDI_SUCCESS) 3057 mutex_init(bge_log_mutex, NULL, MUTEX_DRIVER, NULL); 3058 else 3059 mac_fini_ops(&bge_dev_ops); 3060 return (status); 3061 } 3062 3063 int 3064 _fini(void) 3065 { 3066 int status; 3067 3068 status = mod_remove(&modlinkage); 3069 if (status == DDI_SUCCESS) { 3070 mac_fini_ops(&bge_dev_ops); 3071 mutex_destroy(bge_log_mutex); 3072 } 3073 return (status); 3074 } 3075 3076 3077 /* 3078 * bge_add_intrs: 3079 * 3080 * Register FIXED or MSI interrupts. 3081 */ 3082 static int 3083 bge_add_intrs(bge_t *bgep, int intr_type) 3084 { 3085 dev_info_t *dip = bgep->devinfo; 3086 int avail, actual, intr_size, count = 0; 3087 int i, flag, ret; 3088 3089 BGE_DEBUG(("bge_add_intrs($%p, 0x%x)", (void *)bgep, intr_type)); 3090 3091 /* Get number of interrupts */ 3092 ret = ddi_intr_get_nintrs(dip, intr_type, &count); 3093 if ((ret != DDI_SUCCESS) || (count == 0)) { 3094 bge_error(bgep, "ddi_intr_get_nintrs() failure, ret: %d, " 3095 "count: %d", ret, count); 3096 3097 return (DDI_FAILURE); 3098 } 3099 3100 /* Get number of available interrupts */ 3101 ret = ddi_intr_get_navail(dip, intr_type, &avail); 3102 if ((ret != DDI_SUCCESS) || (avail == 0)) { 3103 bge_error(bgep, "ddi_intr_get_navail() failure, " 3104 "ret: %d, avail: %d\n", ret, avail); 3105 3106 return (DDI_FAILURE); 3107 } 3108 3109 if (avail < count) { 3110 BGE_DEBUG(("%s: nintrs() returned %d, navail returned %d", 3111 bgep->ifname, count, avail)); 3112 } 3113 3114 /* 3115 * BGE hardware generates only single MSI even though it claims 3116 * to support multiple MSIs. So, hard code MSI count value to 1. 3117 */ 3118 if (intr_type == DDI_INTR_TYPE_MSI) { 3119 count = 1; 3120 flag = DDI_INTR_ALLOC_STRICT; 3121 } else { 3122 flag = DDI_INTR_ALLOC_NORMAL; 3123 } 3124 3125 /* Allocate an array of interrupt handles */ 3126 intr_size = count * sizeof (ddi_intr_handle_t); 3127 bgep->htable = kmem_alloc(intr_size, KM_SLEEP); 3128 3129 /* Call ddi_intr_alloc() */ 3130 ret = ddi_intr_alloc(dip, bgep->htable, intr_type, 0, 3131 count, &actual, flag); 3132 3133 if ((ret != DDI_SUCCESS) || (actual == 0)) { 3134 bge_error(bgep, "ddi_intr_alloc() failed %d\n", ret); 3135 3136 kmem_free(bgep->htable, intr_size); 3137 return (DDI_FAILURE); 3138 } 3139 3140 if (actual < count) { 3141 BGE_DEBUG(("%s: Requested: %d, Received: %d", 3142 bgep->ifname, count, actual)); 3143 } 3144 3145 bgep->intr_cnt = actual; 3146 3147 /* 3148 * Get priority for first msi, assume remaining are all the same 3149 */ 3150 if ((ret = ddi_intr_get_pri(bgep->htable[0], &bgep->intr_pri)) != 3151 DDI_SUCCESS) { 3152 bge_error(bgep, "ddi_intr_get_pri() failed %d\n", ret); 3153 3154 /* Free already allocated intr */ 3155 for (i = 0; i < actual; i++) { 3156 (void) ddi_intr_free(bgep->htable[i]); 3157 } 3158 3159 kmem_free(bgep->htable, intr_size); 3160 return (DDI_FAILURE); 3161 } 3162 3163 /* Call ddi_intr_add_handler() */ 3164 for (i = 0; i < actual; i++) { 3165 if ((ret = ddi_intr_add_handler(bgep->htable[i], bge_intr, 3166 (caddr_t)bgep, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 3167 bge_error(bgep, "ddi_intr_add_handler() " 3168 "failed %d\n", ret); 3169 3170 /* Free already allocated intr */ 3171 for (i = 0; i < actual; i++) { 3172 (void) ddi_intr_free(bgep->htable[i]); 3173 } 3174 3175 kmem_free(bgep->htable, intr_size); 3176 return (DDI_FAILURE); 3177 } 3178 } 3179 3180 if ((ret = ddi_intr_get_cap(bgep->htable[0], &bgep->intr_cap)) 3181 != DDI_SUCCESS) { 3182 bge_error(bgep, "ddi_intr_get_cap() failed %d\n", ret); 3183 3184 for (i = 0; i < actual; i++) { 3185 (void) ddi_intr_remove_handler(bgep->htable[i]); 3186 (void) ddi_intr_free(bgep->htable[i]); 3187 } 3188 3189 kmem_free(bgep->htable, intr_size); 3190 return (DDI_FAILURE); 3191 } 3192 3193 return (DDI_SUCCESS); 3194 } 3195 3196 /* 3197 * bge_rem_intrs: 3198 * 3199 * Unregister FIXED or MSI interrupts 3200 */ 3201 static void 3202 bge_rem_intrs(bge_t *bgep) 3203 { 3204 int i; 3205 3206 BGE_DEBUG(("bge_rem_intrs($%p)", (void *)bgep)); 3207 3208 /* Call ddi_intr_remove_handler() */ 3209 for (i = 0; i < bgep->intr_cnt; i++) { 3210 (void) ddi_intr_remove_handler(bgep->htable[i]); 3211 (void) ddi_intr_free(bgep->htable[i]); 3212 } 3213 3214 kmem_free(bgep->htable, bgep->intr_cnt * sizeof (ddi_intr_handle_t)); 3215 } 3216 3217 3218 void 3219 bge_intr_enable(bge_t *bgep) 3220 { 3221 int i; 3222 3223 if (bgep->intr_cap & DDI_INTR_FLAG_BLOCK) { 3224 /* Call ddi_intr_block_enable() for MSI interrupts */ 3225 (void) ddi_intr_block_enable(bgep->htable, bgep->intr_cnt); 3226 } else { 3227 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 3228 for (i = 0; i < bgep->intr_cnt; i++) { 3229 (void) ddi_intr_enable(bgep->htable[i]); 3230 } 3231 } 3232 } 3233 3234 3235 void 3236 bge_intr_disable(bge_t *bgep) 3237 { 3238 int i; 3239 3240 if (bgep->intr_cap & DDI_INTR_FLAG_BLOCK) { 3241 /* Call ddi_intr_block_disable() */ 3242 (void) ddi_intr_block_disable(bgep->htable, bgep->intr_cnt); 3243 } else { 3244 for (i = 0; i < bgep->intr_cnt; i++) { 3245 (void) ddi_intr_disable(bgep->htable[i]); 3246 } 3247 } 3248 } 3249