1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _BGE_IMPL_H 28 #define _BGE_IMPL_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 #include <sys/stream.h> 38 #include <sys/strsun.h> 39 #include <sys/strsubr.h> 40 #include <sys/stat.h> 41 #include <sys/pci.h> 42 #include <sys/note.h> 43 #include <sys/modctl.h> 44 #include <sys/crc32.h> 45 #ifdef __sparcv9 46 #include <v9/sys/membar.h> 47 #endif /* __sparcv9 */ 48 #include <sys/kstat.h> 49 #include <sys/ethernet.h> 50 #include <sys/vlan.h> 51 #include <sys/errno.h> 52 #include <sys/dlpi.h> 53 #include <sys/devops.h> 54 #include <sys/debug.h> 55 #include <sys/cyclic.h> 56 #include <sys/conf.h> 57 58 #include <netinet/ip6.h> 59 60 #include <inet/common.h> 61 #include <inet/ip.h> 62 #include <inet/mi.h> 63 #include <inet/nd.h> 64 #include <sys/pattr.h> 65 66 #include <sys/dditypes.h> 67 #include <sys/ddi.h> 68 #include <sys/sunddi.h> 69 70 #include <sys/ddifm.h> 71 #include <sys/fm/protocol.h> 72 #include <sys/fm/util.h> 73 #include <sys/fm/io/ddi.h> 74 75 #include <sys/mac.h> 76 #include <sys/mac_ether.h> 77 78 #ifdef __amd64 79 #include <sys/x86_archext.h> 80 #endif 81 82 /* 83 * <sys/ethernet.h> *may* already have provided the typedef ether_addr_t; 84 * but of course C doesn't provide a way to check this directly. So here 85 * we rely on the fact that the symbol ETHERTYPE_AT was added to the 86 * header file (as a #define, which we *can* test for) at the same time 87 * as the typedef for ether_addr_t ;-! 88 */ 89 #ifndef ETHERTYPE_AT 90 typedef uchar_t ether_addr_t[ETHERADDRL]; 91 #endif /* ETHERTYPE_AT */ 92 93 /* 94 * Reconfiguring the network devices requires the net_config privilege 95 * in Solaris 10+. 96 */ 97 extern int secpolicy_net_config(const cred_t *, boolean_t); 98 99 #include <sys/netlb.h> /* originally from cassini */ 100 #include <sys/miiregs.h> /* by fjlite out of intel */ 101 102 #include "bge.h" 103 #include "bge_hw.h" 104 105 /* 106 * Compile-time feature switches ... 107 */ 108 #define BGE_DO_PPIO 0 /* peek/poke ioctls */ 109 #define BGE_RX_SOFTINT 0 /* softint per receive ring */ 110 #define BGE_CHOOSE_SEND_METHOD 0 /* send by copying only */ 111 112 /* 113 * NOTES: 114 * 115 * #defines: 116 * 117 * BGE_PCI_CONFIG_RNUMBER and BGE_PCI_OPREGS_RNUMBER are the 118 * register-set numbers to use for the config space registers 119 * and the operating registers respectively. On an OBP-based 120 * machine, regset 0 refers to CONFIG space, and regset 1 will 121 * be the operating registers in MEMORY space. If an expansion 122 * ROM is fitted, it may appear as a further register set. 123 * 124 * BGE_DMA_MODE defines the mode (STREAMING/CONSISTENT) used 125 * for the data buffers. The descriptors are always set up 126 * in CONSISTENT mode. 127 * 128 * BGE_HEADROOM defines how much space we'll leave in allocated 129 * mblks before the first valid data byte. This should be chosen 130 * to be 2 modulo 4, so that once the ethernet header (14 bytes) 131 * has been stripped off, the packet data will be 4-byte aligned. 132 * The remaining space can be used by upstream modules to prepend 133 * any headers required. 134 */ 135 136 #define BGE_PCI_CONFIG_RNUMBER 0 137 #define BGE_PCI_OPREGS_RNUMBER 1 138 #define BGE_DMA_MODE DDI_DMA_STREAMING 139 #define BGE_HEADROOM 34 140 141 /* 142 * BGE_HALFTICK is half the period of the cyclic callback (in 143 * nanoseconds), chosen so that 0.5s <= cyclic period <= 1s. 144 * Other time values are derived as odd multiples of this value 145 * so that there's little chance of ambiguity w.r.t. which tick 146 * a timeout expires on. 147 * 148 * BGE_PHY_STABLE_TIME is the period for which the contents of the 149 * PHY's status register must remain unchanging before we accept 150 * that the link has come up. [Sometimes the link comes up, only 151 * to go down again within a short time as the autonegotiation 152 * process cycles through various options before finding the best 153 * compatible mode. We don't want to report repeated link up/down 154 * cycles, so we wait until we think it's stable.] 155 * 156 * BGE_SERDES_STABLE_TIME is the analogous value for the SerDes 157 * interface. It's much shorter, 'cos the SerDes doesn't show 158 * these effects as much as the copper PHY. 159 * 160 * BGE_LINK_SETTLE_TIME is the period during which we regard link 161 * up/down cycles as an normal event after resetting/reprogramming 162 * the PHY. During this time, link up/down messages are sent to 163 * the log only, not the console. At any other time, link change 164 * events are regarded as unexpected and sent to both console & log. 165 * 166 * These latter two values have no theoretical justification, but 167 * are derived from observations and heuristics - the values below 168 * just seem to work quite well. 169 */ 170 171 #define BGE_HALFTICK 268435456LL /* 2**28 ns! */ 172 #define BGE_CYCLIC_PERIOD (2*BGE_HALFTICK) /* ~0.5s */ 173 #define BGE_SERDES_STABLE_TIME (3*BGE_HALFTICK) /* ~0.8s */ 174 #define BGE_PHY_STABLE_TIME (11*BGE_HALFTICK) /* ~3.0s */ 175 #define BGE_LINK_SETTLE_TIME (111*BGE_HALFTICK) /* ~30.0s */ 176 177 /* 178 * Indices used to identify the different buffer rings internally 179 */ 180 #define BGE_STD_BUFF_RING 0 181 #define BGE_JUMBO_BUFF_RING 1 182 #define BGE_MINI_BUFF_RING 2 183 184 /* 185 * Current implementation limits 186 */ 187 #define BGE_BUFF_RINGS_USED 2 /* std & jumbo ring */ 188 /* for now */ 189 #define BGE_RECV_RINGS_USED 16 /* up to 16 rtn rings */ 190 /* for now */ 191 #define BGE_SEND_RINGS_USED 4 /* up to 4 tx rings */ 192 /* for now */ 193 #define BGE_HASH_TABLE_SIZE 128 /* may be 256 later */ 194 195 /* 196 * Ring/buffer size parameters 197 * 198 * All of the (up to) 16 TX rings & and the corresponding buffers are the 199 * same size. 200 * 201 * Each of the (up to) 3 receive producer (aka buffer) rings is a different 202 * size and has different sized buffers associated with it too. 203 * 204 * The (up to) 16 receive return rings have no buffers associated with them. 205 * The number of slots per receive return ring must be 2048 if the mini 206 * ring is enabled, otherwise it may be 1024. See Broadcom document 207 * 570X-PG102-R page 56. 208 * 209 * Note: only the 5700 supported external memory (and therefore the mini 210 * ring); the 5702/3/4 don't. This driver doesn't support the original 211 * 5700, so we won't ever use the mini ring capability. 212 */ 213 214 #define BGE_SEND_RINGS_DEFAULT 1 215 #define BGE_RECV_RINGS_DEFAULT 1 216 217 #define BGE_SEND_BUFF_SIZE_DEFAULT 1536 218 #define BGE_SEND_BUFF_SIZE_JUMBO 9022 219 #define BGE_SEND_SLOTS_USED 512 220 221 #define BGE_STD_BUFF_SIZE 1536 /* 0x600 */ 222 #define BGE_STD_SLOTS_USED 512 223 224 #define BGE_JUMBO_BUFF_SIZE 9022 /* 9k */ 225 #define BGE_JUMBO_SLOTS_USED 256 226 227 #define BGE_MINI_BUFF_SIZE 128 /* 64? 256? */ 228 #define BGE_MINI_SLOTS_USED 0 /* must be 0; see above */ 229 230 #define BGE_RECV_BUFF_SIZE 0 231 #if BGE_MINI_SLOTS_USED > 0 232 #define BGE_RECV_SLOTS_USED 2048 /* required */ 233 #else 234 #define BGE_RECV_SLOTS_USED 1024 /* could be 2048 anyway */ 235 #endif 236 237 #define BGE_SEND_BUF_NUM 512 238 #define BGE_SEND_BUF_ARRAY 16 239 #define BGE_SEND_BUF_ARRAY_JUMBO 3 240 #define BGE_SEND_BUF_MAX (BGE_SEND_BUF_NUM*BGE_SEND_BUF_ARRAY) 241 242 /* 243 * PCI type. PCI-Express or PCI/PCIX 244 */ 245 #define BGE_PCI 0 246 #define BGE_PCI_E 1 247 #define BGE_PCI_X 2 248 249 /* 250 * Statistic type. There are two type of statistic: 251 * statistic block and statistic registers 252 */ 253 #define BGE_STAT_BLK 1 254 #define BGE_STAT_REG 2 255 256 /* 257 * MTU.for all chipsets ,the default is 1500 ,and some chipsets 258 * support 9k jumbo frames size 259 */ 260 #define BGE_DEFAULT_MTU 1500 261 #define BGE_MAXIMUM_MTU 9000 262 263 /* 264 * Pad the h/w defined status block (which can be up to 80 bytes long) 265 * to a power-of-two boundary 266 */ 267 #define BGE_STATUS_PADDING (128 - sizeof (bge_status_t)) 268 269 /* 270 * On platforms which support DVMA, we can simply allocate one big piece 271 * of memory for all the Tx buffers and another for the Rx buffers, and 272 * then carve them up as required. It doesn't matter if they aren't just 273 * one physically contiguous piece each, because both the CPU *and* the 274 * I/O device can see them *as though they were*. 275 * 276 * However, if only physically-addressed DMA is possible, this doesn't 277 * work; we can't expect to get enough contiguously-addressed memory for 278 * all the buffers of each type, so in this case we request a number of 279 * smaller pieces, each still large enough for several buffers but small 280 * enough to fit within "an I/O page" (e.g. 64K). 281 * 282 * The #define below specifies how many pieces of memory are to be used; 283 * 16 has been shown to work on an i86pc architecture but this could be 284 * different on other non-DVMA platforms ... 285 */ 286 #ifdef _DMA_USES_VIRTADDR 287 #define BGE_SPLIT 1 /* no split required */ 288 #else 289 #if ((BGE_BUFF_RINGS_USED > 1) || (BGE_SEND_RINGS_USED > 1) || \ 290 (BGE_RECV_RINGS_USED > 1)) 291 #define BGE_SPLIT 128 /* split 128 ways */ 292 #else 293 #define BGE_SPLIT 16 /* split 16 ways */ 294 #endif 295 #endif /* _DMA_USES_VIRTADDR */ 296 297 #define BGE_RECV_RINGS_SPLIT (BGE_RECV_RINGS_MAX + 1) 298 299 /* 300 * STREAMS parameters 301 */ 302 #define BGE_IDNUM 0 /* zero seems to work */ 303 #define BGE_LOWAT (256) 304 #define BGE_HIWAT (256*1024) 305 306 307 /* 308 * Basic data types, for clarity in distinguishing 'numbers' 309 * used for different purposes ... 310 * 311 * A <bge_regno_t> is a register 'address' (offset) in any one of 312 * various address spaces (PCI config space, PCI memory-mapped I/O 313 * register space, MII registers, etc). None of these exceeds 64K, 314 * so we could use a 16-bit representation but pointer-sized objects 315 * are more "natural" in most architectures; they seem to be handled 316 * more efficiently on SPARC and no worse on x86. 317 * 318 * BGE_REGNO_NONE represents the non-existent value in this space. 319 */ 320 typedef uintptr_t bge_regno_t; /* register # (offset) */ 321 #define BGE_REGNO_NONE (~(uintptr_t)0u) 322 323 /* 324 * Describes one chunk of allocated DMA-able memory 325 * 326 * In some cases, this is a single chunk as allocated from the system; 327 * but we also use this structure to represent slices carved off such 328 * a chunk. Even when we don't really need all the information, we 329 * use this structure as a convenient way of correlating the various 330 * ways of looking at a piece of memory (kernel VA, IO space DVMA, 331 * handle+offset, etc). 332 */ 333 typedef struct { 334 ddi_acc_handle_t acc_hdl; /* handle for memory */ 335 void *mem_va; /* CPU VA of memory */ 336 uint32_t nslots; /* number of slots */ 337 uint32_t size; /* size per slot */ 338 size_t alength; /* allocated size */ 339 /* >= product of above */ 340 341 ddi_dma_handle_t dma_hdl; /* DMA handle */ 342 offset_t offset; /* relative to handle */ 343 ddi_dma_cookie_t cookie; /* associated cookie */ 344 uint32_t ncookies; /* must be 1 */ 345 uint32_t token; /* arbitrary identifier */ 346 } dma_area_t; /* 0x50 (80) bytes */ 347 348 typedef struct bge_queue_item { 349 struct bge_queue_item *next; 350 void *item; 351 } bge_queue_item_t; 352 353 typedef struct bge_queue { 354 bge_queue_item_t *head; 355 uint32_t count; 356 kmutex_t *lock; 357 } bge_queue_t; 358 /* 359 * Software version of the Receive Buffer Descriptor 360 * There's one of these for each receive buffer (up to 256/512/1024 per ring). 361 */ 362 typedef struct sw_rbd { 363 dma_area_t pbuf; /* (const) related */ 364 /* buffer area */ 365 } sw_rbd_t; /* 0x50 (80) bytes */ 366 367 /* 368 * Software Receive Buffer (Producer) Ring Control Block 369 * There's one of these for each receiver producer ring (up to 3), 370 * but each holds buffers of a different size. 371 */ 372 typedef struct buff_ring { 373 dma_area_t desc; /* (const) related h/w */ 374 /* descriptor area */ 375 dma_area_t buf[BGE_SPLIT]; /* (const) related */ 376 /* buffer area(s) */ 377 bge_rcb_t hw_rcb; /* (const) image of h/w */ 378 /* RCB, and used to */ 379 struct bge *bgep; /* (const) containing */ 380 /* driver soft state */ 381 /* initialise same */ 382 volatile uint16_t *cons_index_p; /* (const) ptr to h/w */ 383 /* "consumer index" */ 384 /* (in status block) */ 385 386 /* 387 * The rf_lock must be held when updating the h/w producer index 388 * mailbox register (*chip_mbox_reg), or the s/w producer index 389 * (rf_next). 390 */ 391 bge_regno_t chip_mbx_reg; /* (const) h/w producer */ 392 /* index mailbox offset */ 393 kmutex_t rf_lock[1]; /* serialize refill */ 394 uint64_t rf_next; /* next slot to refill */ 395 /* ("producer index") */ 396 397 sw_rbd_t *sw_rbds; /* software descriptors */ 398 void *spare[4]; /* padding */ 399 } buff_ring_t; /* 0x100 (256) bytes */ 400 401 /* 402 * Software Receive (Return) Ring Control Block 403 * There's one of these for each receiver return ring (up to 16). 404 */ 405 typedef struct recv_ring { 406 /* 407 * The elements flagged (const) in the comments below are 408 * set up once during initialiation and thereafter unchanged. 409 */ 410 dma_area_t desc; /* (const) related h/w */ 411 /* descriptor area */ 412 bge_rcb_t hw_rcb; /* (const) image of h/w */ 413 /* RCB, and used to */ 414 /* initialise same */ 415 struct bge *bgep; /* (const) containing */ 416 /* driver soft state */ 417 ddi_softintr_t rx_softint; /* (const) per-ring */ 418 /* receive callback */ 419 volatile uint16_t *prod_index_p; /* (const) ptr to h/w */ 420 /* "producer index" */ 421 /* (in status block) */ 422 423 /* 424 * The rx_lock must be held when updating the h/w consumer index 425 * mailbox register (*chip_mbox_reg), or the s/w consumer index 426 * (rx_next). 427 */ 428 bge_regno_t chip_mbx_reg; /* (const) h/w consumer */ 429 /* index mailbox offset */ 430 kmutex_t rx_lock[1]; /* serialize receive */ 431 uint64_t rx_next; /* next slot to examine */ 432 mac_resource_handle_t handle; /* per ring cookie */ 433 /* ("producer index") */ 434 } recv_ring_t; /* 0x90 (144) bytes */ 435 436 /* 437 * Send packet structure 438 */ 439 typedef struct send_pkt { 440 uint16_t vlan_tci; 441 uint32_t pflags; 442 boolean_t tx_ready; 443 bge_queue_item_t *txbuf_item; 444 } send_pkt_t; 445 446 /* 447 * Software version of tx buffer structure 448 */ 449 typedef struct sw_txbuf { 450 dma_area_t buf; 451 uint32_t copy_len; 452 } sw_txbuf_t; 453 454 /* 455 * Software version of the Send Buffer Descriptor 456 * There's one of these for each send buffer (up to 512 per ring) 457 */ 458 typedef struct sw_sbd { 459 dma_area_t desc; /* (const) related h/w */ 460 /* descriptor area */ 461 bge_queue_item_t *pbuf; /* (const) related */ 462 /* buffer area */ 463 } sw_sbd_t; 464 465 /* 466 * Software Send Ring Control Block 467 * There's one of these for each of (up to) 16 send rings 468 */ 469 typedef struct send_ring { 470 /* 471 * The elements flagged (const) in the comments below are 472 * set up once during initialiation and thereafter unchanged. 473 */ 474 dma_area_t desc; /* (const) related h/w */ 475 /* descriptor area */ 476 dma_area_t buf[BGE_SEND_BUF_ARRAY][BGE_SPLIT]; 477 /* buffer area(s) */ 478 bge_rcb_t hw_rcb; /* (const) image of h/w */ 479 /* RCB, and used to */ 480 /* initialise same */ 481 struct bge *bgep; /* (const) containing */ 482 /* driver soft state */ 483 volatile uint16_t *cons_index_p; /* (const) ptr to h/w */ 484 /* "consumer index" */ 485 /* (in status block) */ 486 487 bge_regno_t chip_mbx_reg; /* (const) h/w producer */ 488 /* index mailbox offset */ 489 /* 490 * Tx buffer queue 491 */ 492 bge_queue_t txbuf_queue; 493 bge_queue_t freetxbuf_queue; 494 bge_queue_t *txbuf_push_queue; 495 bge_queue_t *txbuf_pop_queue; 496 kmutex_t txbuf_lock[1]; 497 kmutex_t freetxbuf_lock[1]; 498 bge_queue_item_t *txbuf_head; 499 send_pkt_t *pktp; 500 uint64_t txpkt_next; 501 uint64_t txfill_next; 502 sw_txbuf_t *txbuf; 503 uint32_t tx_buffers; 504 uint32_t tx_buffers_low; 505 uint32_t tx_array_max; 506 uint32_t tx_array; 507 kmutex_t tx_lock[1]; /* serialize h/w update */ 508 /* ("producer index") */ 509 uint64_t tx_next; /* next slot to use */ 510 uint64_t tx_flow; /* # concurrent sends */ 511 uint64_t tx_block; 512 uint64_t tx_nobd; 513 uint64_t tx_nobuf; 514 uint64_t tx_alloc_fail; 515 516 /* 517 * These counters/indexes are manipulated in the transmit 518 * path using atomics rather than mutexes for speed 519 */ 520 uint64_t tx_free; /* # of slots available */ 521 522 /* 523 * The tc_lock must be held while manipulating the s/w consumer 524 * index (tc_next). 525 */ 526 kmutex_t tc_lock[1]; /* serialize recycle */ 527 uint64_t tc_next; /* next slot to recycle */ 528 /* ("consumer index") */ 529 530 sw_sbd_t *sw_sbds; /* software descriptors */ 531 uint64_t mac_resid; /* special per resource id */ 532 } send_ring_t; /* 0x100 (256) bytes */ 533 534 typedef struct { 535 ether_addr_t addr; /* in canonical form */ 536 uint8_t spare; 537 boolean_t set; /* B_TRUE => valid */ 538 } bge_mac_addr_t; 539 540 /* 541 * The original 5700/01 supported only SEEPROMs. Later chips (5702+) 542 * support both SEEPROMs (using the same 2-wire CLK/DATA interface for 543 * the hardware and a backwards-compatible software access method), and 544 * buffered or unbuffered FLASH devices connected to the 4-wire SPI bus 545 * and using a new software access method. 546 * 547 * The access methods for SEEPROM and Flash are generally similar, with 548 * the chip handling the serialisation/deserialisation and handshaking, 549 * but the registers used are different, as are a few details of the 550 * protocol, and the timing, so we have to determine which (if any) is 551 * fitted. 552 * 553 * The value UNKNOWN means just that; we haven't yet tried to determine 554 * the device type. 555 * 556 * The value NONE can indicate either that a real and definite absence of 557 * any NVmem has been detected, or that there may be NVmem but we can't 558 * determine its type, perhaps because the NVconfig pins on the chip have 559 * been wired up incorrectly. In either case, access to the NVmem (if any) 560 * is not supported. 561 */ 562 enum bge_nvmem_type { 563 BGE_NVTYPE_NONE = -1, /* (or indeterminable) */ 564 BGE_NVTYPE_UNKNOWN, /* not yet checked */ 565 BGE_NVTYPE_SEEPROM, /* BCM5700/5701 only */ 566 BGE_NVTYPE_LEGACY_SEEPROM, /* 5702+ */ 567 BGE_NVTYPE_UNBUFFERED_FLASH, /* 5702+ */ 568 BGE_NVTYPE_BUFFERED_FLASH /* 5702+ */ 569 }; 570 571 /* 572 * Describes the characteristics of a specific chip 573 * 574 * Note: elements from <businfo> to <latency> are filled in by during 575 * the first phase of chip initialisation (see bge_chip_cfg_init()). 576 * The remaining ones are determined just after the first RESET, in 577 * bge_poll_firmware(). Thereafter, the entire structure is readonly. 578 */ 579 typedef struct { 580 uint32_t asic_rev; /* masked from MHCR */ 581 uint32_t businfo; /* from private reg */ 582 uint16_t command; /* saved during attach */ 583 584 uint16_t vendor; /* vendor-id */ 585 uint16_t device; /* device-id */ 586 uint16_t subven; /* subsystem-vendor-id */ 587 uint16_t subdev; /* subsystem-id */ 588 uint8_t revision; /* revision-id */ 589 uint8_t clsize; /* cache-line-size */ 590 uint8_t latency; /* latency-timer */ 591 592 uint8_t flags; 593 uint16_t chip_label; /* numeric part only */ 594 /* (e.g. 5703/5794/etc) */ 595 uint32_t mbuf_base; /* Mbuf pool parameters */ 596 uint32_t mbuf_length; /* depend on chiptype */ 597 uint32_t pci_type; 598 uint32_t statistic_type; 599 uint32_t bge_dma_rwctrl; 600 uint32_t bge_mlcr_default; 601 uint32_t recv_slots; /* receive ring size */ 602 enum bge_nvmem_type nvtype; /* SEEPROM or Flash */ 603 604 uint16_t jumbo_slots; 605 uint16_t ethmax_size; 606 uint16_t snd_buff_size; 607 uint16_t recv_jumbo_size; 608 uint16_t std_buf_size; 609 uint32_t mbuf_hi_water; 610 uint32_t mbuf_lo_water_rmac; 611 uint32_t mbuf_lo_water_rdma; 612 613 uint32_t rx_rings; /* from bge.conf */ 614 uint32_t tx_rings; /* from bge.conf */ 615 uint32_t default_mtu; /* from bge.conf */ 616 617 uint64_t hw_mac_addr; /* from chip register */ 618 bge_mac_addr_t vendor_addr; /* transform of same */ 619 boolean_t msi_enabled; /* default to true */ 620 } chip_id_t; 621 622 #define CHIP_FLAG_SUPPORTED 0x80 623 #define CHIP_FLAG_SERDES 0x40 624 #define CHIP_FLAG_PARTIAL_CSUM 0x20 625 #define CHIP_FLAG_NO_JUMBO 0x1 626 627 /* 628 * Collection of physical-layer functions to: 629 * (re)initialise the physical layer 630 * update it to match software settings 631 * check for link status change 632 */ 633 typedef struct { 634 int (*phys_restart)(struct bge *, boolean_t); 635 int (*phys_update)(struct bge *); 636 boolean_t (*phys_check)(struct bge *, boolean_t); 637 } phys_ops_t; 638 639 /* 640 * Named Data (ND) Parameter Management Structure 641 */ 642 typedef struct { 643 int ndp_info; 644 int ndp_min; 645 int ndp_max; 646 int ndp_val; 647 char *ndp_name; 648 } nd_param_t; /* 0x18 (24) bytes */ 649 650 /* 651 * NDD parameter indexes, divided into: 652 * 653 * read-only parameters describing the hardware's capabilities 654 * read-write parameters controlling the advertised capabilities 655 * read-only parameters describing the partner's capabilities 656 * read-only parameters describing the link state 657 */ 658 enum { 659 PARAM_AUTONEG_CAP, 660 PARAM_PAUSE_CAP, 661 PARAM_ASYM_PAUSE_CAP, 662 PARAM_1000FDX_CAP, 663 PARAM_1000HDX_CAP, 664 PARAM_100T4_CAP, 665 PARAM_100FDX_CAP, 666 PARAM_100HDX_CAP, 667 PARAM_10FDX_CAP, 668 PARAM_10HDX_CAP, 669 670 PARAM_ADV_AUTONEG_CAP, 671 PARAM_ADV_PAUSE_CAP, 672 PARAM_ADV_ASYM_PAUSE_CAP, 673 PARAM_ADV_1000FDX_CAP, 674 PARAM_ADV_1000HDX_CAP, 675 PARAM_ADV_100T4_CAP, 676 PARAM_ADV_100FDX_CAP, 677 PARAM_ADV_100HDX_CAP, 678 PARAM_ADV_10FDX_CAP, 679 PARAM_ADV_10HDX_CAP, 680 681 PARAM_LP_AUTONEG_CAP, 682 PARAM_LP_PAUSE_CAP, 683 PARAM_LP_ASYM_PAUSE_CAP, 684 PARAM_LP_1000FDX_CAP, 685 PARAM_LP_1000HDX_CAP, 686 PARAM_LP_100T4_CAP, 687 PARAM_LP_100FDX_CAP, 688 PARAM_LP_100HDX_CAP, 689 PARAM_LP_10FDX_CAP, 690 PARAM_LP_10HDX_CAP, 691 692 PARAM_LINK_STATUS, 693 PARAM_LINK_SPEED, 694 PARAM_LINK_DUPLEX, 695 696 PARAM_LINK_AUTONEG, 697 PARAM_LINK_RX_PAUSE, 698 PARAM_LINK_TX_PAUSE, 699 700 PARAM_LOOP_MODE, 701 PARAM_MSI_CNT, 702 703 PARAM_DRAIN_MAX, 704 705 PARAM_COUNT 706 }; 707 708 /* 709 * Actual state of the BCM570x chip 710 */ 711 enum bge_chip_state { 712 BGE_CHIP_FAULT = -2, /* fault, need reset */ 713 BGE_CHIP_ERROR, /* error, want reset */ 714 BGE_CHIP_INITIAL, /* Initial state only */ 715 BGE_CHIP_RESET, /* reset, need init */ 716 BGE_CHIP_STOPPED, /* Tx/Rx stopped */ 717 BGE_CHIP_RUNNING /* with interrupts */ 718 }; 719 720 enum bge_mac_state { 721 BGE_MAC_STOPPED = 0, 722 BGE_MAC_STARTED 723 }; 724 725 /* 726 * (Internal) return values from ioctl subroutines 727 */ 728 enum ioc_reply { 729 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 730 IOC_DONE, /* OK, reply sent */ 731 IOC_ACK, /* OK, just send ACK */ 732 IOC_REPLY, /* OK, just send reply */ 733 IOC_RESTART_ACK, /* OK, restart & ACK */ 734 IOC_RESTART_REPLY /* OK, restart & reply */ 735 }; 736 737 /* 738 * (Internal) return values from send_msg subroutines 739 */ 740 enum send_status { 741 SEND_FAIL = -1, /* Not OK */ 742 SEND_KEEP, /* OK, msg queued */ 743 SEND_FREE /* OK, free msg */ 744 }; 745 746 /* 747 * (Internal) enumeration of this driver's kstats 748 */ 749 enum { 750 BGE_KSTAT_RAW = 0, 751 BGE_KSTAT_STATS, 752 BGE_KSTAT_PARAMS, 753 BGE_KSTAT_CHIPID, 754 BGE_KSTAT_DRIVER, 755 BGE_KSTAT_PHYS, 756 BGE_KSTAT_MII, 757 758 BGE_KSTAT_COUNT 759 }; 760 761 #define BGE_MAX_RESOURCES 255 762 763 /* 764 * Per-instance soft-state structure 765 */ 766 typedef struct bge { 767 /* 768 * These fields are set by attach() and unchanged thereafter ... 769 */ 770 dev_info_t *devinfo; /* device instance */ 771 mac_handle_t mh; /* mac module handle */ 772 ddi_acc_handle_t cfg_handle; /* DDI I/O handle */ 773 ddi_acc_handle_t io_handle; /* DDI I/O handle */ 774 void *io_regs; /* mapped registers */ 775 cyclic_id_t cyclic_id; /* cyclic callback */ 776 ddi_softintr_t factotum_id; /* factotum callback */ 777 ddi_softintr_t drain_id; /* reschedule callback */ 778 779 ddi_intr_handle_t *htable; /* For array of interrupts */ 780 int intr_type; /* What type of interrupt */ 781 int intr_cnt; /* # of intrs count returned */ 782 uint_t intr_pri; /* Interrupt priority */ 783 int intr_cap; /* Interrupt capabilities */ 784 uint32_t progress; /* attach tracking */ 785 uint32_t debug; /* per-instance debug */ 786 chip_id_t chipid; 787 const phys_ops_t *physops; 788 char ifname[8]; /* "bge0" ... "bge999" */ 789 790 int fm_capabilities; /* FMA capabilities */ 791 792 /* 793 * These structures describe the blocks of memory allocated during 794 * attach(). They remain unchanged thereafter, although the memory 795 * they describe is carved up into various separate regions and may 796 * therefore be described by other structures as well. 797 */ 798 dma_area_t tx_desc; /* transmit descriptors */ 799 dma_area_t rx_desc[BGE_RECV_RINGS_SPLIT]; 800 /* receive descriptors */ 801 dma_area_t tx_buff[BGE_SPLIT]; 802 dma_area_t rx_buff[BGE_SPLIT]; 803 804 /* 805 * The memory described by the <dma_area> structures above 806 * is carved up into various pieces, which are described by 807 * the structures below. 808 */ 809 dma_area_t statistics; /* describes hardware */ 810 /* statistics area */ 811 dma_area_t status_block; /* describes hardware */ 812 /* status block */ 813 /* 814 * For the BCM5705/5788/5721/5751/5752/5714 and 5715, 815 * the statistic block is not available,the statistic counter must 816 * be gotten from statistic registers.And bge_statistics_reg_t record 817 * the statistic registers value 818 */ 819 bge_statistics_reg_t *pstats; 820 821 /* 822 * Runtime read-write data starts here ... 823 * 824 * 3 Buffer Rings (std/jumbo/mini) 825 * 16 Receive (Return) Rings 826 * 16 Send Rings 827 * 828 * Note: they're not necessarily all used. 829 */ 830 buff_ring_t buff[BGE_BUFF_RINGS_MAX]; /* 3*0x0100 */ 831 recv_ring_t recv[BGE_RECV_RINGS_MAX]; /* 16*0x0090 */ 832 send_ring_t send[BGE_SEND_RINGS_MAX]; /* 16*0x0100 */ 833 834 /* 835 * Locks: 836 * 837 * Each buffer ring contains its own <rf_lock> which regulates 838 * ring refilling. 839 * 840 * Each receive (return) ring contains its own <rx_lock> which 841 * protects the critical cyclic counters etc. 842 * 843 * Each send ring contains two locks: <tx_lock> for the send-path 844 * protocol data and <tc_lock> for send-buffer recycling. 845 * 846 * Finally <genlock> is a general lock, protecting most other 847 * operational data in the state structure and chip register 848 * accesses. It is acquired by the interrupt handler and 849 * most "mode-control" routines. 850 * 851 * Any of the locks can be acquired singly, but where multiple 852 * locks are acquired, they *must* be in the order: 853 * 854 * genlock >>> rx_lock >>> rf_lock >>> tx_lock >>> tc_lock. 855 * 856 * and within any one class of lock the rings must be locked in 857 * ascending order (send[0].tc_lock >>> send[1].tc_lock), etc. 858 * 859 * Note: actually I don't believe there's any need to acquire 860 * locks on multiple rings, or even locks of all these classes 861 * concurrently; but I've set out the above order so there is a 862 * clear definition of lock hierarchy in case it's ever needed. 863 * 864 * Note: the combinations of locks that are actually held 865 * concurrently are: 866 * 867 * genlock >>> (bge_chip_interrupt()) 868 * rx_lock[i] >>> (bge_receive()) 869 * rf_lock[n] (bge_refill()) 870 * tc_lock[i] (bge_recycle()) 871 */ 872 kmutex_t genlock[1]; 873 krwlock_t errlock[1]; 874 kmutex_t softintrlock[1]; 875 876 /* 877 * Current Ethernet addresses and multicast hash (bitmap) and 878 * refcount tables, protected by <genlock> 879 */ 880 bge_mac_addr_t curr_addr[MAC_ADDRESS_REGS_MAX]; 881 uint32_t mcast_hash[BGE_HASH_TABLE_SIZE/32]; 882 uint8_t mcast_refs[BGE_HASH_TABLE_SIZE]; 883 uint32_t unicst_addr_total; /* total unicst addresses */ 884 uint32_t unicst_addr_avail; 885 /* unused unicst addr slots */ 886 887 /* 888 * Link state data (protected by genlock) 889 */ 890 const char *link_mode_msg; /* describes link mode */ 891 const char *link_down_msg; /* reason for link DOWN */ 892 const char *link_up_msg; /* comment on link UP */ 893 894 link_state_t link_state; 895 896 /* 897 * Physical layer (PHY/SerDes) state data (protected by genlock) 898 */ 899 hrtime_t phys_write_time; /* when last written */ 900 hrtime_t phys_event_time; /* when status changed */ 901 hrtime_t phys_delta_time; /* time to settle */ 902 903 /* 904 * Physical layer: copper only 905 */ 906 bge_regno_t phy_mii_addr; /* should be (const) 1! */ 907 uint16_t phy_gen_status; 908 uint16_t phy_aux_status; 909 910 /* 911 * Physical layer: serdes only 912 */ 913 uint32_t serdes_status; 914 uint32_t serdes_advert; 915 uint32_t serdes_lpadv; 916 917 /* 918 * Driver kstats, protected by <genlock> where necessary 919 */ 920 kstat_t *bge_kstats[BGE_KSTAT_COUNT]; 921 922 /* 923 * Miscellaneous operating variables (protected by genlock) 924 */ 925 uint64_t chip_resets; /* # of chip RESETs */ 926 uint64_t missed_dmas; /* # of missed DMAs */ 927 uint64_t missed_updates; /* # of missed updates */ 928 enum bge_mac_state bge_mac_state; /* definitions above */ 929 enum bge_chip_state bge_chip_state; /* definitions above */ 930 boolean_t send_hw_tcp_csum; 931 boolean_t recv_hw_tcp_csum; 932 boolean_t promisc; 933 934 /* 935 * Miscellaneous operating variables (not synchronised) 936 */ 937 uint32_t watchdog; /* watches for Tx stall */ 938 boolean_t bge_intr_running; 939 boolean_t bge_dma_error; 940 boolean_t tx_resched_needed; 941 uint64_t tx_resched; 942 uint32_t factotum_flag; /* softint pending */ 943 uintptr_t pagemask; 944 945 /* 946 * NDD parameters (protected by genlock) 947 */ 948 caddr_t nd_data_p; 949 nd_param_t *nd_params; 950 951 /* 952 * A flag to prevent excessive config space accesses 953 * on platforms having BCM5714C/15C 954 */ 955 boolean_t lastWriteZeroData; 956 957 /* 958 * Spare space, plus guard element used to check data integrity 959 */ 960 uint64_t spare[5]; 961 uint64_t bge_guard; 962 963 /* 964 * Receive rules configure 965 */ 966 bge_recv_rule_t recv_rules[RECV_RULES_NUM_MAX]; 967 968 #ifdef BGE_IPMI_ASF 969 boolean_t asf_enabled; 970 boolean_t asf_wordswapped; 971 boolean_t asf_newhandshake; 972 boolean_t asf_pseudostop; 973 974 uint32_t asf_status; 975 timeout_id_t asf_timeout_id; 976 #endif 977 } bge_t; 978 979 /* 980 * 'Progress' bit flags ... 981 */ 982 #define PROGRESS_CFG 0x0001 /* config space mapped */ 983 #define PROGRESS_REGS 0x0002 /* registers mapped */ 984 #define PROGRESS_BUFS 0x0004 /* ring buffers allocated */ 985 #define PROGRESS_RESCHED 0x0010 /* resched softint registered */ 986 #define PROGRESS_FACTOTUM 0x0020 /* factotum softint registered */ 987 #define PROGRESS_HWINT 0x0040 /* h/w interrupt registered */ 988 /* and mutexen initialised */ 989 #define PROGRESS_INTR 0x0080 /* Intrs enabled */ 990 #define PROGRESS_PHY 0x0100 /* PHY initialised */ 991 #define PROGRESS_NDD 0x1000 /* NDD parameters set up */ 992 #define PROGRESS_KSTATS 0x2000 /* kstats created */ 993 #define PROGRESS_READY 0x8000 /* ready for work */ 994 995 /* 996 * Shorthand for the NDD parameters 997 */ 998 #define param_adv_autoneg nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val 999 #define param_adv_pause nd_params[PARAM_ADV_PAUSE_CAP].ndp_val 1000 #define param_adv_asym_pause nd_params[PARAM_ADV_ASYM_PAUSE_CAP].ndp_val 1001 #define param_adv_1000fdx nd_params[PARAM_ADV_1000FDX_CAP].ndp_val 1002 #define param_adv_1000hdx nd_params[PARAM_ADV_1000HDX_CAP].ndp_val 1003 #define param_adv_100fdx nd_params[PARAM_ADV_100FDX_CAP].ndp_val 1004 #define param_adv_100hdx nd_params[PARAM_ADV_100HDX_CAP].ndp_val 1005 #define param_adv_10fdx nd_params[PARAM_ADV_10FDX_CAP].ndp_val 1006 #define param_adv_10hdx nd_params[PARAM_ADV_10HDX_CAP].ndp_val 1007 1008 #define param_lp_autoneg nd_params[PARAM_LP_AUTONEG_CAP].ndp_val 1009 #define param_lp_pause nd_params[PARAM_LP_PAUSE_CAP].ndp_val 1010 #define param_lp_asym_pause nd_params[PARAM_LP_ASYM_PAUSE_CAP].ndp_val 1011 #define param_lp_1000fdx nd_params[PARAM_LP_1000FDX_CAP].ndp_val 1012 #define param_lp_1000hdx nd_params[PARAM_LP_1000HDX_CAP].ndp_val 1013 #define param_lp_100fdx nd_params[PARAM_LP_100FDX_CAP].ndp_val 1014 #define param_lp_100hdx nd_params[PARAM_LP_100HDX_CAP].ndp_val 1015 #define param_lp_10fdx nd_params[PARAM_LP_10FDX_CAP].ndp_val 1016 #define param_lp_10hdx nd_params[PARAM_LP_10HDX_CAP].ndp_val 1017 1018 #define param_link_up nd_params[PARAM_LINK_STATUS].ndp_val 1019 #define param_link_speed nd_params[PARAM_LINK_SPEED].ndp_val 1020 #define param_link_duplex nd_params[PARAM_LINK_DUPLEX].ndp_val 1021 1022 #define param_link_autoneg nd_params[PARAM_LINK_AUTONEG].ndp_val 1023 #define param_link_rx_pause nd_params[PARAM_LINK_RX_PAUSE].ndp_val 1024 #define param_link_tx_pause nd_params[PARAM_LINK_TX_PAUSE].ndp_val 1025 1026 #define param_loop_mode nd_params[PARAM_LOOP_MODE].ndp_val 1027 #define param_msi_cnt nd_params[PARAM_MSI_CNT].ndp_val 1028 #define param_drain_max nd_params[PARAM_DRAIN_MAX].ndp_val 1029 1030 /* 1031 * Sync a DMA area described by a dma_area_t 1032 */ 1033 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl, \ 1034 (area).offset, (area).alength, (flag))) 1035 1036 /* 1037 * Find the (kernel virtual) address of block of memory 1038 * described by a dma_area_t 1039 */ 1040 #define DMA_VPTR(area) ((area).mem_va) 1041 1042 /* 1043 * Zero a block of memory described by a dma_area_t 1044 */ 1045 #define DMA_ZERO(area) bzero(DMA_VPTR(area), (area).alength) 1046 1047 /* 1048 * Next value of a cyclic index 1049 */ 1050 #define NEXT(index, limit) ((index)+1 < (limit) ? (index)+1 : 0) 1051 1052 /* 1053 * Property lookups 1054 */ 1055 #define BGE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 1056 DDI_PROP_DONTPASS, (n)) 1057 #define BGE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 1058 DDI_PROP_DONTPASS, (n), -1) 1059 1060 /* 1061 * Copy an ethernet address 1062 */ 1063 #define ethaddr_copy(src, dst) bcopy((src), (dst), ETHERADDRL) 1064 1065 /* 1066 * Endian swap 1067 */ 1068 /* BEGIN CSTYLED */ 1069 #define BGE_BSWAP_32(x) ((((x) & 0xff000000) >> 24) | \ 1070 (((x) & 0x00ff0000) >> 8) | \ 1071 (((x) & 0x0000ff00) << 8) | \ 1072 (((x) & 0x000000ff) << 24)) 1073 /* END CSTYLED */ 1074 1075 /* 1076 * Marker value placed at the end of the driver's state 1077 */ 1078 #define BGE_GUARD 0x1919306009031802 1079 1080 /* 1081 * Bit flags in the 'debug' word ... 1082 */ 1083 #define BGE_DBG_STOP 0x00000001 /* early debug_enter() */ 1084 #define BGE_DBG_TRACE 0x00000002 /* general flow tracing */ 1085 1086 #define BGE_DBG_REGS 0x00000010 /* low-level accesses */ 1087 #define BGE_DBG_MII 0x00000020 /* low-level MII access */ 1088 #define BGE_DBG_SEEPROM 0x00000040 /* low-level SEEPROM IO */ 1089 #define BGE_DBG_CHIP 0x00000080 /* low(ish)-level code */ 1090 1091 #define BGE_DBG_RECV 0x00000100 /* receive-side code */ 1092 #define BGE_DBG_SEND 0x00000200 /* packet-send code */ 1093 1094 #define BGE_DBG_INT 0x00001000 /* interrupt handler */ 1095 #define BGE_DBG_FACT 0x00002000 /* factotum (softint) */ 1096 1097 #define BGE_DBG_PHY 0x00010000 /* Copper PHY code */ 1098 #define BGE_DBG_SERDES 0x00020000 /* SerDes code */ 1099 #define BGE_DBG_PHYS 0x00040000 /* Physical layer code */ 1100 #define BGE_DBG_LINK 0x00080000 /* Link status check */ 1101 1102 #define BGE_DBG_INIT 0x00100000 /* initialisation */ 1103 #define BGE_DBG_NEMO 0x00200000 /* nemo interaction */ 1104 #define BGE_DBG_ADDR 0x00400000 /* address-setting code */ 1105 #define BGE_DBG_STATS 0x00800000 /* statistics */ 1106 1107 #define BGE_DBG_IOCTL 0x01000000 /* ioctl handling */ 1108 #define BGE_DBG_LOOP 0x02000000 /* loopback ioctl code */ 1109 #define BGE_DBG_PPIO 0x04000000 /* Peek/poke ioctls */ 1110 #define BGE_DBG_BADIOC 0x08000000 /* unknown ioctls */ 1111 1112 #define BGE_DBG_MCTL 0x10000000 /* mctl (csum) code */ 1113 #define BGE_DBG_NDD 0x20000000 /* NDD operations */ 1114 1115 /* 1116 * Debugging ... 1117 */ 1118 #ifdef DEBUG 1119 #define BGE_DEBUGGING 1 1120 #else 1121 #define BGE_DEBUGGING 0 1122 #endif /* DEBUG */ 1123 1124 1125 /* 1126 * 'Do-if-debugging' macro. The parameter <command> should be one or more 1127 * C statements (but without the *final* semicolon), which will either be 1128 * compiled inline or completely ignored, depending on the BGE_DEBUGGING 1129 * compile-time flag. 1130 * 1131 * You should get a compile-time error (at least on a DEBUG build) if 1132 * your statement isn't actually a statement, rather than unexpected 1133 * run-time behaviour caused by unintended matching of if-then-elses etc. 1134 * 1135 * Note that the BGE_DDB() macro itself can only be used as a statement, 1136 * not an expression, and should always be followed by a semicolon. 1137 */ 1138 #if BGE_DEBUGGING 1139 #define BGE_DDB(command) do { \ 1140 { command; } \ 1141 _NOTE(CONSTANTCONDITION) \ 1142 } while (0) 1143 #else /* BGE_DEBUGGING */ 1144 #define BGE_DDB(command) do { \ 1145 { _NOTE(EMPTY); } \ 1146 _NOTE(CONSTANTCONDITION) \ 1147 } while (0) 1148 #endif /* BGE_DEBUGGING */ 1149 1150 /* 1151 * 'Internal' macros used to construct the TRACE/DEBUG macros below. 1152 * These provide the primitive conditional-call capability required. 1153 * Note: the parameter <args> is a parenthesised list of the actual 1154 * printf-style arguments to be passed to the debug function ... 1155 */ 1156 #define BGE_XDB(b, w, f, args) BGE_DDB(if ((b) & (w)) f args) 1157 #define BGE_GDB(b, args) BGE_XDB(b, bge_debug, (*bge_gdb()), args) 1158 #define BGE_LDB(b, args) BGE_XDB(b, bgep->debug, (*bge_db(bgep)), args) 1159 #define BGE_CDB(f, args) BGE_XDB(BGE_DBG, bgep->debug, f, args) 1160 1161 /* 1162 * Conditional-print macros. 1163 * 1164 * Define BGE_DBG to be the relevant member of the set of BGE_DBG_* values 1165 * above before using the BGE_GDEBUG() or BGE_DEBUG() macros. The 'G' 1166 * versions look at the Global debug flag word (bge_debug); the non-G 1167 * versions look in the per-instance data (bgep->debug) and so require a 1168 * variable called 'bgep' to be in scope (and initialised!) before use. 1169 * 1170 * You could redefine BGE_TRC too if you really need two different 1171 * flavours of debugging output in the same area of code, but I don't 1172 * really recommend it. 1173 * 1174 * Note: the parameter <args> is a parenthesised list of the actual 1175 * arguments to be passed to the debug function, usually a printf-style 1176 * format string and corresponding values to be formatted. 1177 */ 1178 1179 #define BGE_TRC BGE_DBG_TRACE /* default 'trace' bit */ 1180 #define BGE_GTRACE(args) BGE_GDB(BGE_TRC, args) 1181 #define BGE_GDEBUG(args) BGE_GDB(BGE_DBG, args) 1182 #define BGE_TRACE(args) BGE_LDB(BGE_TRC, args) 1183 #define BGE_DEBUG(args) BGE_LDB(BGE_DBG, args) 1184 1185 /* 1186 * Debug-only action macros 1187 */ 1188 #define BGE_BRKPT(bgep, s) BGE_DDB(bge_dbg_enter(bgep, s)) 1189 #define BGE_MARK(bgep) BGE_DDB(bge_led_mark(bgep)) 1190 #define BGE_PCICHK(bgep) BGE_DDB(bge_pci_check(bgep)) 1191 #define BGE_PKTDUMP(args) BGE_DDB(bge_pkt_dump args) 1192 #define BGE_REPORT(args) BGE_DDB(bge_log args) 1193 1194 /* 1195 * Inter-source-file linkage ... 1196 */ 1197 1198 /* bge_chip.c */ 1199 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1200 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t value); 1201 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 1202 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t value); 1203 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 1204 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 1205 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t value); 1206 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 1207 int bge_chip_id_init(bge_t *bgep); 1208 int bge_chip_start(bge_t *bgep, boolean_t reset_phy); 1209 void bge_chip_stop(bge_t *bgep, boolean_t fault); 1210 #ifdef BGE_IPMI_ASF 1211 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 1212 #pragma inline(bge_nic_put32) 1213 uint32_t bge_nic_read32(bge_t *bgep, bge_regno_t addr); 1214 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 1215 #pragma inline(bge_ind_put32) 1216 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 1217 #pragma inline(bge_ind_get32) 1218 void bge_asf_update_status(bge_t *bgep); 1219 void bge_asf_heartbeat(void *bgep); 1220 void bge_asf_stop_timer(bge_t *bgep); 1221 void bge_asf_get_config(bge_t *bgep); 1222 void bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode); 1223 void bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode); 1224 void bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode); 1225 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 1226 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 1227 #else 1228 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 1229 int bge_chip_sync(bge_t *bgep); 1230 #endif 1231 void bge_chip_blank(void *arg, time_t ticks, uint_t count); 1232 uint_t bge_chip_factotum(caddr_t arg); 1233 void bge_chip_cyclic(void *arg); 1234 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 1235 struct iocblk *iocp); 1236 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 1237 extern uint32_t bge_rx_ticks_norm; 1238 extern uint32_t bge_tx_ticks_norm; 1239 extern uint32_t bge_rx_count_norm; 1240 extern uint32_t bge_tx_count_norm; 1241 extern boolean_t bge_jumbo_enable; 1242 extern boolean_t bge_relaxed_ordering; 1243 1244 void bge_chip_msi_trig(bge_t *bgep); 1245 1246 /* bge_kstats.c */ 1247 void bge_init_kstats(bge_t *bgep, int instance); 1248 void bge_fini_kstats(bge_t *bgep); 1249 int bge_m_stat(void *arg, uint_t stat, uint64_t *val); 1250 1251 /* bge_log.c */ 1252 #if BGE_DEBUGGING 1253 void (*bge_db(bge_t *bgep))(const char *fmt, ...); 1254 void (*bge_gdb(void))(const char *fmt, ...); 1255 void bge_pkt_dump(bge_t *bgep, bge_rbd_t *hbp, sw_rbd_t *sdp, const char *msg); 1256 void bge_dbg_enter(bge_t *bgep, const char *msg); 1257 #endif /* BGE_DEBUGGING */ 1258 void bge_problem(bge_t *bgep, const char *fmt, ...); 1259 void bge_notice(bge_t *bgep, const char *fmt, ...); 1260 void bge_log(bge_t *bgep, const char *fmt, ...); 1261 void bge_error(bge_t *bgep, const char *fmt, ...); 1262 void bge_fm_ereport(bge_t *bgep, char *detail); 1263 extern kmutex_t bge_log_mutex[1]; 1264 extern uint32_t bge_debug; 1265 1266 /* bge_main.c */ 1267 int bge_restart(bge_t *bgep, boolean_t reset_phy); 1268 int bge_check_acc_handle(bge_t *bgep, ddi_acc_handle_t handle); 1269 int bge_check_dma_handle(bge_t *bgep, ddi_dma_handle_t handle); 1270 void bge_init_rings(bge_t *bgep); 1271 void bge_fini_rings(bge_t *bgep); 1272 bge_queue_item_t *bge_alloc_txbuf_array(bge_t *bgep, send_ring_t *srp); 1273 void bge_free_txbuf_arrays(send_ring_t *srp); 1274 int bge_alloc_bufs(bge_t *bgep); 1275 void bge_free_bufs(bge_t *bgep); 1276 void bge_intr_enable(bge_t *bgep); 1277 void bge_intr_disable(bge_t *bgep); 1278 1279 /* bge_phys.c */ 1280 int bge_phys_init(bge_t *bgep); 1281 void bge_phys_reset(bge_t *bgep); 1282 int bge_phys_idle(bge_t *bgep); 1283 int bge_phys_update(bge_t *bgep); 1284 boolean_t bge_phys_check(bge_t *bgep); 1285 1286 /* bge_ndd.c */ 1287 int bge_nd_init(bge_t *bgep); 1288 enum ioc_reply bge_nd_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 1289 struct iocblk *iocp); 1290 void bge_nd_cleanup(bge_t *bgep); 1291 1292 /* bge_recv.c */ 1293 void bge_receive(bge_t *bgep, bge_status_t *bsp); 1294 1295 /* bge_send.c */ 1296 mblk_t *bge_m_tx(void *arg, mblk_t *mp); 1297 void bge_recycle(bge_t *bgep, bge_status_t *bsp); 1298 uint_t bge_send_drain(caddr_t arg); 1299 1300 /* bge_atomic.c */ 1301 uint64_t bge_atomic_reserve(uint64_t *count_p, uint64_t n); 1302 void bge_atomic_renounce(uint64_t *count_p, uint64_t n); 1303 uint64_t bge_atomic_claim(uint64_t *count_p, uint64_t limit); 1304 uint64_t bge_atomic_next(uint64_t *sp, uint64_t limit); 1305 void bge_atomic_sub64(uint64_t *count_p, uint64_t n); 1306 uint64_t bge_atomic_clr64(uint64_t *sp, uint64_t bits); 1307 uint32_t bge_atomic_shl32(uint32_t *sp, uint_t count); 1308 1309 /* 1310 * Reset type 1311 */ 1312 #define BGE_SHUTDOWN_RESET 0 1313 #define BGE_INIT_RESET 1 1314 #define BGE_SUSPEND_RESET 2 1315 1316 /* For asf_status */ 1317 #define ASF_STAT_NONE 0 1318 #define ASF_STAT_STOP 1 1319 #define ASF_STAT_RUN 2 1320 #define ASF_STAT_RUN_INIT 3 /* attached but don't plumb */ 1321 1322 /* ASF modes for bge_reset() and bge_chip_reset() */ 1323 #define ASF_MODE_NONE 0 /* don't launch asf */ 1324 #define ASF_MODE_SHUTDOWN 1 /* asf shutdown mode */ 1325 #define ASF_MODE_INIT 2 /* asf init mode */ 1326 #define ASF_MODE_POST_SHUTDOWN 3 /* only do post-shutdown */ 1327 #define ASF_MODE_POST_INIT 4 /* only do post-init */ 1328 1329 #define BGE_ASF_HEARTBEAT_INTERVAL 1500000 1330 1331 #ifdef __cplusplus 1332 } 1333 #endif 1334 1335 #endif /* _BGE_IMPL_H */ 1336