1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_BGE_IMPL_H 28 #define _SYS_BGE_IMPL_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 #include <sys/stream.h> 38 #include <sys/strsun.h> 39 #include <sys/strsubr.h> 40 #include <sys/stat.h> 41 #include <sys/pci.h> 42 #include <sys/note.h> 43 #include <sys/modctl.h> 44 #include <sys/crc32.h> 45 #ifdef __sparcv9 46 #include <v9/sys/membar.h> 47 #endif /* __sparcv9 */ 48 #include <sys/kstat.h> 49 #include <sys/ethernet.h> 50 #include <sys/vlan.h> 51 #include <sys/errno.h> 52 #include <sys/dlpi.h> 53 #include <sys/devops.h> 54 #include <sys/debug.h> 55 #include <sys/cyclic.h> 56 #include <sys/conf.h> 57 58 #include <netinet/ip6.h> 59 60 #include <inet/common.h> 61 #include <inet/ip.h> 62 #include <inet/mi.h> 63 #include <inet/nd.h> 64 #include <sys/pattr.h> 65 66 #include <sys/dditypes.h> 67 #include <sys/ddi.h> 68 #include <sys/sunddi.h> 69 70 #include <sys/ddifm.h> 71 #include <sys/fm/protocol.h> 72 #include <sys/fm/util.h> 73 #include <sys/fm/io/ddi.h> 74 75 #include <sys/mac.h> 76 #include <sys/mac_ether.h> 77 78 #ifdef __amd64 79 #include <sys/x86_archext.h> 80 #endif 81 82 /* 83 * <sys/ethernet.h> *may* already have provided the typedef ether_addr_t; 84 * but of course C doesn't provide a way to check this directly. So here 85 * we rely on the fact that the symbol ETHERTYPE_AT was added to the 86 * header file (as a #define, which we *can* test for) at the same time 87 * as the typedef for ether_addr_t ;-! 88 */ 89 #ifndef ETHERTYPE_AT 90 typedef uchar_t ether_addr_t[ETHERADDRL]; 91 #endif /* ETHERTYPE_AT */ 92 93 /* 94 * Reconfiguring the network devices requires the net_config privilege 95 * in Solaris 10+. 96 */ 97 extern int secpolicy_net_config(const cred_t *, boolean_t); 98 99 #include <sys/netlb.h> /* originally from cassini */ 100 #include <sys/miiregs.h> /* by fjlite out of intel */ 101 102 #include "bge.h" 103 #include "bge_hw.h" 104 105 /* 106 * Compile-time feature switches ... 107 */ 108 #define BGE_DO_PPIO 0 /* peek/poke ioctls */ 109 #define BGE_RX_SOFTINT 0 /* softint per receive ring */ 110 #define BGE_CHOOSE_SEND_METHOD 0 /* send by copying only */ 111 112 /* 113 * NOTES: 114 * 115 * #defines: 116 * 117 * BGE_PCI_CONFIG_RNUMBER and BGE_PCI_OPREGS_RNUMBER are the 118 * register-set numbers to use for the config space registers 119 * and the operating registers respectively. On an OBP-based 120 * machine, regset 0 refers to CONFIG space, and regset 1 will 121 * be the operating registers in MEMORY space. If an expansion 122 * ROM is fitted, it may appear as a further register set. 123 * 124 * BGE_DMA_MODE defines the mode (STREAMING/CONSISTENT) used 125 * for the data buffers. The descriptors are always set up 126 * in CONSISTENT mode. 127 * 128 * BGE_HEADROOM defines how much space we'll leave in allocated 129 * mblks before the first valid data byte. This should be chosen 130 * to be 2 modulo 4, so that once the ethernet header (14 bytes) 131 * has been stripped off, the packet data will be 4-byte aligned. 132 * The remaining space can be used by upstream modules to prepend 133 * any headers required. 134 */ 135 136 #define BGE_PCI_CONFIG_RNUMBER 0 137 #define BGE_PCI_OPREGS_RNUMBER 1 138 #define BGE_DMA_MODE DDI_DMA_STREAMING 139 #define BGE_HEADROOM 34 140 141 /* 142 * BGE_HALFTICK is half the period of the cyclic callback (in 143 * nanoseconds), chosen so that 0.5s <= cyclic period <= 1s. 144 * Other time values are derived as odd multiples of this value 145 * so that there's little chance of ambiguity w.r.t. which tick 146 * a timeout expires on. 147 * 148 * BGE_PHY_STABLE_TIME is the period for which the contents of the 149 * PHY's status register must remain unchanging before we accept 150 * that the link has come up. [Sometimes the link comes up, only 151 * to go down again within a short time as the autonegotiation 152 * process cycles through various options before finding the best 153 * compatible mode. We don't want to report repeated link up/down 154 * cycles, so we wait until we think it's stable.] 155 * 156 * BGE_SERDES_STABLE_TIME is the analogous value for the SerDes 157 * interface. It's much shorter, 'cos the SerDes doesn't show 158 * these effects as much as the copper PHY. 159 * 160 * BGE_LINK_SETTLE_TIME is the period during which we regard link 161 * up/down cycles as an normal event after resetting/reprogramming 162 * the PHY. During this time, link up/down messages are sent to 163 * the log only, not the console. At any other time, link change 164 * events are regarded as unexpected and sent to both console & log. 165 * 166 * These latter two values have no theoretical justification, but 167 * are derived from observations and heuristics - the values below 168 * just seem to work quite well. 169 */ 170 171 #define BGE_HALFTICK 268435456LL /* 2**28 ns! */ 172 #define BGE_CYCLIC_PERIOD (2*BGE_HALFTICK) /* ~0.5s */ 173 #define BGE_SERDES_STABLE_TIME (3*BGE_HALFTICK) /* ~0.8s */ 174 #define BGE_PHY_STABLE_TIME (11*BGE_HALFTICK) /* ~3.0s */ 175 #define BGE_LINK_SETTLE_TIME (111*BGE_HALFTICK) /* ~30.0s */ 176 177 /* 178 * Indices used to identify the different buffer rings internally 179 */ 180 #define BGE_STD_BUFF_RING 0 181 #define BGE_JUMBO_BUFF_RING 1 182 #define BGE_MINI_BUFF_RING 2 183 184 /* 185 * Current implementation limits 186 */ 187 #define BGE_BUFF_RINGS_USED 2 /* std & jumbo ring */ 188 /* for now */ 189 #define BGE_RECV_RINGS_USED 16 /* up to 16 rtn rings */ 190 /* for now */ 191 #define BGE_SEND_RINGS_USED 4 /* up to 4 tx rings */ 192 /* for now */ 193 #define BGE_HASH_TABLE_SIZE 128 /* may be 256 later */ 194 195 /* 196 * Ring/buffer size parameters 197 * 198 * All of the (up to) 16 TX rings & and the corresponding buffers are the 199 * same size. 200 * 201 * Each of the (up to) 3 receive producer (aka buffer) rings is a different 202 * size and has different sized buffers associated with it too. 203 * 204 * The (up to) 16 receive return rings have no buffers associated with them. 205 * The number of slots per receive return ring must be 2048 if the mini 206 * ring is enabled, otherwise it may be 1024. See Broadcom document 207 * 570X-PG102-R page 56. 208 * 209 * Note: only the 5700 supported external memory (and therefore the mini 210 * ring); the 5702/3/4 don't. This driver doesn't support the original 211 * 5700, so we won't ever use the mini ring capability. 212 */ 213 214 #define BGE_SEND_RINGS_DEFAULT 1 215 #define BGE_RECV_RINGS_DEFAULT 1 216 217 #define BGE_SEND_BUFF_SIZE_DEFAULT 1536 218 #define BGE_SEND_BUFF_SIZE_JUMBO 9022 219 #define BGE_SEND_SLOTS_USED 512 220 221 #define BGE_STD_BUFF_SIZE 1536 /* 0x600 */ 222 #define BGE_STD_SLOTS_USED 512 223 224 #define BGE_JUMBO_BUFF_SIZE 9022 /* 9k */ 225 #define BGE_JUMBO_SLOTS_USED 256 226 227 #define BGE_MINI_BUFF_SIZE 128 /* 64? 256? */ 228 #define BGE_MINI_SLOTS_USED 0 /* must be 0; see above */ 229 230 #define BGE_RECV_BUFF_SIZE 0 231 #if BGE_MINI_SLOTS_USED > 0 232 #define BGE_RECV_SLOTS_USED 2048 /* required */ 233 #else 234 #define BGE_RECV_SLOTS_USED 1024 /* could be 2048 anyway */ 235 #endif 236 237 /* 238 * PCI type. PCI-Express or PCI/PCIX 239 */ 240 #define BGE_PCI 0 241 #define BGE_PCI_E 1 242 #define BGE_PCI_X 2 243 244 /* 245 * Statistic type. There are two type of statistic: 246 * statistic block and statistic registers 247 */ 248 #define BGE_STAT_BLK 1 249 #define BGE_STAT_REG 2 250 251 /* 252 * MTU.for all chipsets ,the default is 1500 ,and some chipsets 253 * support 9k jumbo frames size 254 */ 255 #define BGE_DEFAULT_MTU 1500 256 #define BGE_MAXIMUM_MTU 9000 257 258 /* 259 * Pad the h/w defined status block (which can be up to 80 bytes long) 260 * to a power-of-two boundary 261 */ 262 #define BGE_STATUS_PADDING (128 - sizeof (bge_status_t)) 263 264 /* 265 * On platforms which support DVMA, we can simply allocate one big piece 266 * of memory for all the Tx buffers and another for the Rx buffers, and 267 * then carve them up as required. It doesn't matter if they aren't just 268 * one physically contiguous piece each, because both the CPU *and* the 269 * I/O device can see them *as though they were*. 270 * 271 * However, if only physically-addressed DMA is possible, this doesn't 272 * work; we can't expect to get enough contiguously-addressed memory for 273 * all the buffers of each type, so in this case we request a number of 274 * smaller pieces, each still large enough for several buffers but small 275 * enough to fit within "an I/O page" (e.g. 64K). 276 * 277 * The #define below specifies how many pieces of memory are to be used; 278 * 16 has been shown to work on an i86pc architecture but this could be 279 * different on other non-DVMA platforms ... 280 */ 281 #ifdef _DMA_USES_VIRTADDR 282 #define BGE_SPLIT 1 /* no split required */ 283 #else 284 #if ((BGE_BUFF_RINGS_USED > 1) || (BGE_SEND_RINGS_USED > 1) || \ 285 (BGE_RECV_RINGS_USED > 1)) 286 #define BGE_SPLIT 128 /* split 128 ways */ 287 #else 288 #define BGE_SPLIT 16 /* split 16 ways */ 289 #endif 290 #endif /* _DMA_USES_VIRTADDR */ 291 292 #define BGE_RECV_RINGS_SPLIT (BGE_RECV_RINGS_MAX + 1) 293 294 /* 295 * MONOLITHIC allocation is a hardware debugging aid, so that a logic 296 * analyser can more easily be programmed with the (single) range of 297 * memory addresses that the chip will then use for DMA. 298 * 299 * It's incompatible with non-DVMA architectures that require BGE_SPLIT 300 * to be set greater than 1. Here, it overrides BGE_SPLIT, so the code 301 * will compile correctly but will *probably* fail at runtime because it 302 * simply won't be able to allocate a big enough piece of memory ... 303 */ 304 #define BGE_MONOLITHIC 0 305 #if BGE_MONOLITHIC 306 #undef BGE_SPLIT 307 #define BGE_SPLIT 1 /* must be 1 if MONOLITHIC */ 308 #endif /* BGE_MONOLITHIC */ 309 310 /* 311 * STREAMS parameters 312 */ 313 #define BGE_IDNUM 0 /* zero seems to work */ 314 #define BGE_LOWAT (256) 315 #define BGE_HIWAT (256*1024) 316 317 318 /* 319 * Basic data types, for clarity in distinguishing 'numbers' 320 * used for different purposes ... 321 * 322 * A <bge_regno_t> is a register 'address' (offset) in any one of 323 * various address spaces (PCI config space, PCI memory-mapped I/O 324 * register space, MII registers, etc). None of these exceeds 64K, 325 * so we could use a 16-bit representation but pointer-sized objects 326 * are more "natural" in most architectures; they seem to be handled 327 * more efficiently on SPARC and no worse on x86. 328 * 329 * BGE_REGNO_NONE represents the non-existent value in this space. 330 */ 331 typedef uintptr_t bge_regno_t; /* register # (offset) */ 332 #define BGE_REGNO_NONE (~(uintptr_t)0u) 333 334 /* 335 * Describes one chunk of allocated DMA-able memory 336 * 337 * In some cases, this is a single chunk as allocated from the system; 338 * but we also use this structure to represent slices carved off such 339 * a chunk. Even when we don't really need all the information, we 340 * use this structure as a convenient way of correlating the various 341 * ways of looking at a piece of memory (kernel VA, IO space DVMA, 342 * handle+offset, etc). 343 */ 344 typedef struct { 345 ddi_acc_handle_t acc_hdl; /* handle for memory */ 346 void *mem_va; /* CPU VA of memory */ 347 uint32_t nslots; /* number of slots */ 348 uint32_t size; /* size per slot */ 349 size_t alength; /* allocated size */ 350 /* >= product of above */ 351 352 ddi_dma_handle_t dma_hdl; /* DMA handle */ 353 offset_t offset; /* relative to handle */ 354 ddi_dma_cookie_t cookie; /* associated cookie */ 355 uint32_t ncookies; /* must be 1 */ 356 uint32_t token; /* arbitrary identifier */ 357 } dma_area_t; /* 0x50 (80) bytes */ 358 359 /* 360 * Software version of the Receive Buffer Descriptor 361 * There's one of these for each receive buffer (up to 256/512/1024 per ring). 362 */ 363 typedef struct sw_rbd { 364 dma_area_t pbuf; /* (const) related */ 365 /* buffer area */ 366 } sw_rbd_t; /* 0x50 (80) bytes */ 367 368 /* 369 * Software Receive Buffer (Producer) Ring Control Block 370 * There's one of these for each receiver producer ring (up to 3), 371 * but each holds buffers of a different size. 372 */ 373 typedef struct buff_ring { 374 dma_area_t desc; /* (const) related h/w */ 375 /* descriptor area */ 376 dma_area_t buf[BGE_SPLIT]; /* (const) related */ 377 /* buffer area(s) */ 378 bge_rcb_t hw_rcb; /* (const) image of h/w */ 379 /* RCB, and used to */ 380 struct bge *bgep; /* (const) containing */ 381 /* driver soft state */ 382 /* initialise same */ 383 volatile uint16_t *cons_index_p; /* (const) ptr to h/w */ 384 /* "consumer index" */ 385 /* (in status block) */ 386 387 /* 388 * The rf_lock must be held when updating the h/w producer index 389 * mailbox register (*chip_mbox_reg), or the s/w producer index 390 * (rf_next). 391 */ 392 bge_regno_t chip_mbx_reg; /* (const) h/w producer */ 393 /* index mailbox offset */ 394 kmutex_t rf_lock[1]; /* serialize refill */ 395 uint64_t rf_next; /* next slot to refill */ 396 /* ("producer index") */ 397 398 sw_rbd_t *sw_rbds; /* software descriptors */ 399 void *spare[4]; /* padding */ 400 } buff_ring_t; /* 0x100 (256) bytes */ 401 402 /* 403 * Software Receive (Return) Ring Control Block 404 * There's one of these for each receiver return ring (up to 16). 405 */ 406 typedef struct recv_ring { 407 /* 408 * The elements flagged (const) in the comments below are 409 * set up once during initialiation and thereafter unchanged. 410 */ 411 dma_area_t desc; /* (const) related h/w */ 412 /* descriptor area */ 413 bge_rcb_t hw_rcb; /* (const) image of h/w */ 414 /* RCB, and used to */ 415 /* initialise same */ 416 struct bge *bgep; /* (const) containing */ 417 /* driver soft state */ 418 ddi_softintr_t rx_softint; /* (const) per-ring */ 419 /* receive callback */ 420 volatile uint16_t *prod_index_p; /* (const) ptr to h/w */ 421 /* "producer index" */ 422 /* (in status block) */ 423 424 /* 425 * The rx_lock must be held when updating the h/w consumer index 426 * mailbox register (*chip_mbox_reg), or the s/w consumer index 427 * (rx_next). 428 */ 429 bge_regno_t chip_mbx_reg; /* (const) h/w consumer */ 430 /* index mailbox offset */ 431 kmutex_t rx_lock[1]; /* serialize receive */ 432 uint64_t rx_next; /* next slot to examine */ 433 mac_resource_handle_t handle; /* per ring cookie */ 434 /* ("producer index") */ 435 } recv_ring_t; /* 0x90 (144) bytes */ 436 437 /* 438 * Software version of the Send Buffer Descriptor 439 * There's one of these for each send buffer (up to 512 per ring) 440 */ 441 typedef struct sw_sbd { 442 dma_area_t desc; /* (const) related h/w */ 443 /* descriptor area */ 444 dma_area_t pbuf; /* (const) related */ 445 /* buffer area */ 446 447 void (*recycle)(struct sw_sbd *); 448 uint64_t flags; 449 450 mblk_t *mp; /* related mblk, if any */ 451 ddi_dma_handle_t mblk_hdl; /* handle for same */ 452 } sw_sbd_t; /* 0xc0 (192) bytes */ 453 454 #define SW_SBD_FLAG_BUSY 0x0000000000000001 455 #define SW_SBD_FLAG_PBUF 0x0000000000000002 456 #define SW_SBD_FLAG_BIND 0x0000000000000004 457 458 /* 459 * Software Send Ring Control Block 460 * There's one of these for each of (up to) 16 send rings 461 */ 462 typedef struct send_ring { 463 /* 464 * The elements flagged (const) in the comments below are 465 * set up once during initialiation and thereafter unchanged. 466 */ 467 dma_area_t desc; /* (const) related h/w */ 468 /* descriptor area */ 469 dma_area_t buf[BGE_SPLIT]; /* (const) related */ 470 /* buffer area(s) */ 471 bge_rcb_t hw_rcb; /* (const) image of h/w */ 472 /* RCB, and used to */ 473 /* initialise same */ 474 struct bge *bgep; /* (const) containing */ 475 /* driver soft state */ 476 volatile uint16_t *cons_index_p; /* (const) ptr to h/w */ 477 /* "consumer index" */ 478 /* (in status block) */ 479 480 bge_regno_t chip_mbx_reg; /* (const) h/w producer */ 481 /* index mailbox offset */ 482 kmutex_t tx_lock[1]; /* serialize h/w update */ 483 /* ("producer index") */ 484 uint64_t tx_next; /* next slot to use */ 485 uint64_t tx_flow; /* # concurrent sends */ 486 487 /* 488 * These counters/indexes are manipulated in the transmit 489 * path using atomics rather than mutexes for speed 490 */ 491 uint64_t tx_free; /* # of slots available */ 492 493 /* 494 * The tc_lock must be held while manipulating the s/w consumer 495 * index (tc_next). 496 */ 497 kmutex_t tc_lock[1]; /* serialize recycle */ 498 uint64_t tc_next; /* next slot to recycle */ 499 /* ("consumer index") */ 500 501 sw_sbd_t *sw_sbds; /* software descriptors */ 502 uint64_t mac_resid; /* special per resource id */ 503 } send_ring_t; /* 0x100 (256) bytes */ 504 505 typedef struct { 506 ether_addr_t addr; /* in canonical form */ 507 uint8_t spare; 508 boolean_t set; /* B_TRUE => valid */ 509 } bge_mac_addr_t; 510 511 /* 512 * The original 5700/01 supported only SEEPROMs. Later chips (5702+) 513 * support both SEEPROMs (using the same 2-wire CLK/DATA interface for 514 * the hardware and a backwards-compatible software access method), and 515 * buffered or unbuffered FLASH devices connected to the 4-wire SPI bus 516 * and using a new software access method. 517 * 518 * The access methods for SEEPROM and Flash are generally similar, with 519 * the chip handling the serialisation/deserialisation and handshaking, 520 * but the registers used are different, as are a few details of the 521 * protocol, and the timing, so we have to determine which (if any) is 522 * fitted. 523 * 524 * The value UNKNOWN means just that; we haven't yet tried to determine 525 * the device type. 526 * 527 * The value NONE can indicate either that a real and definite absence of 528 * any NVmem has been detected, or that there may be NVmem but we can't 529 * determine its type, perhaps because the NVconfig pins on the chip have 530 * been wired up incorrectly. In either case, access to the NVmem (if any) 531 * is not supported. 532 */ 533 enum bge_nvmem_type { 534 BGE_NVTYPE_NONE = -1, /* (or indeterminable) */ 535 BGE_NVTYPE_UNKNOWN, /* not yet checked */ 536 BGE_NVTYPE_SEEPROM, /* BCM5700/5701 only */ 537 BGE_NVTYPE_LEGACY_SEEPROM, /* 5702+ */ 538 BGE_NVTYPE_UNBUFFERED_FLASH, /* 5702+ */ 539 BGE_NVTYPE_BUFFERED_FLASH /* 5702+ */ 540 }; 541 542 /* 543 * Describes the characteristics of a specific chip 544 * 545 * Note: elements from <businfo> to <latency> are filled in by during 546 * the first phase of chip initialisation (see bge_chip_cfg_init()). 547 * The remaining ones are determined just after the first RESET, in 548 * bge_poll_firmware(). Thereafter, the entire structure is readonly. 549 */ 550 typedef struct { 551 uint32_t asic_rev; /* masked from MHCR */ 552 uint32_t businfo; /* from private reg */ 553 uint16_t command; /* saved during attach */ 554 555 uint16_t vendor; /* vendor-id */ 556 uint16_t device; /* device-id */ 557 uint16_t subven; /* subsystem-vendor-id */ 558 uint16_t subdev; /* subsystem-id */ 559 uint8_t revision; /* revision-id */ 560 uint8_t clsize; /* cache-line-size */ 561 uint8_t latency; /* latency-timer */ 562 563 uint8_t flags; 564 uint16_t chip_label; /* numeric part only */ 565 /* (e.g. 5703/5794/etc) */ 566 uint32_t mbuf_base; /* Mbuf pool parameters */ 567 uint32_t mbuf_length; /* depend on chiptype */ 568 uint32_t pci_type; 569 uint32_t statistic_type; 570 uint32_t bge_dma_rwctrl; 571 uint32_t bge_mlcr_default; 572 uint32_t recv_slots; /* receive ring size */ 573 enum bge_nvmem_type nvtype; /* SEEPROM or Flash */ 574 575 uint16_t jumbo_slots; 576 uint16_t ethmax_size; 577 uint16_t snd_buff_size; 578 uint16_t recv_jumbo_size; 579 uint16_t std_buf_size; 580 uint32_t mbuf_hi_water; 581 uint32_t mbuf_lo_water_rmac; 582 uint32_t mbuf_lo_water_rdma; 583 584 uint64_t rx_rings; /* from bge.conf */ 585 uint64_t tx_rings; /* from bge.conf */ 586 uint64_t default_mtu; /* from bge.conf */ 587 588 uint64_t hw_mac_addr; /* from chip register */ 589 bge_mac_addr_t vendor_addr; /* transform of same */ 590 boolean_t msi_enabled; /* default to true */ 591 } chip_id_t; 592 593 #define CHIP_FLAG_SUPPORTED 0x80 594 #define CHIP_FLAG_SERDES 0x40 595 #define CHIP_FLAG_PARTIAL_CSUM 0x20 596 #define CHIP_FLAG_NO_JUMBO 0x1 597 598 /* 599 * Collection of physical-layer functions to: 600 * (re)initialise the physical layer 601 * update it to match software settings 602 * check for link status change 603 */ 604 typedef struct { 605 int (*phys_restart)(struct bge *, boolean_t); 606 int (*phys_update)(struct bge *); 607 boolean_t (*phys_check)(struct bge *, boolean_t); 608 } phys_ops_t; 609 610 /* 611 * Named Data (ND) Parameter Management Structure 612 */ 613 typedef struct { 614 int ndp_info; 615 int ndp_min; 616 int ndp_max; 617 int ndp_val; 618 char *ndp_name; 619 } nd_param_t; /* 0x18 (24) bytes */ 620 621 /* 622 * NDD parameter indexes, divided into: 623 * 624 * read-only parameters describing the hardware's capabilities 625 * read-write parameters controlling the advertised capabilities 626 * read-only parameters describing the partner's capabilities 627 * read-only parameters describing the link state 628 */ 629 enum { 630 PARAM_AUTONEG_CAP, 631 PARAM_PAUSE_CAP, 632 PARAM_ASYM_PAUSE_CAP, 633 PARAM_1000FDX_CAP, 634 PARAM_1000HDX_CAP, 635 PARAM_100T4_CAP, 636 PARAM_100FDX_CAP, 637 PARAM_100HDX_CAP, 638 PARAM_10FDX_CAP, 639 PARAM_10HDX_CAP, 640 641 PARAM_ADV_AUTONEG_CAP, 642 PARAM_ADV_PAUSE_CAP, 643 PARAM_ADV_ASYM_PAUSE_CAP, 644 PARAM_ADV_1000FDX_CAP, 645 PARAM_ADV_1000HDX_CAP, 646 PARAM_ADV_100T4_CAP, 647 PARAM_ADV_100FDX_CAP, 648 PARAM_ADV_100HDX_CAP, 649 PARAM_ADV_10FDX_CAP, 650 PARAM_ADV_10HDX_CAP, 651 652 PARAM_LP_AUTONEG_CAP, 653 PARAM_LP_PAUSE_CAP, 654 PARAM_LP_ASYM_PAUSE_CAP, 655 PARAM_LP_1000FDX_CAP, 656 PARAM_LP_1000HDX_CAP, 657 PARAM_LP_100T4_CAP, 658 PARAM_LP_100FDX_CAP, 659 PARAM_LP_100HDX_CAP, 660 PARAM_LP_10FDX_CAP, 661 PARAM_LP_10HDX_CAP, 662 663 PARAM_LINK_STATUS, 664 PARAM_LINK_SPEED, 665 PARAM_LINK_DUPLEX, 666 667 PARAM_LINK_AUTONEG, 668 PARAM_LINK_RX_PAUSE, 669 PARAM_LINK_TX_PAUSE, 670 671 PARAM_LOOP_MODE, 672 PARAM_MSI_CNT, 673 674 PARAM_COUNT 675 }; 676 677 /* 678 * Actual state of the BCM570x chip 679 */ 680 enum bge_chip_state { 681 BGE_CHIP_FAULT = -2, /* fault, need reset */ 682 BGE_CHIP_ERROR, /* error, want reset */ 683 BGE_CHIP_INITIAL, /* Initial state only */ 684 BGE_CHIP_RESET, /* reset, need init */ 685 BGE_CHIP_STOPPED, /* Tx/Rx stopped */ 686 BGE_CHIP_RUNNING /* with interrupts */ 687 }; 688 689 enum bge_mac_state { 690 BGE_MAC_STOPPED = 0, 691 BGE_MAC_STARTED 692 }; 693 694 /* 695 * (Internal) return values from ioctl subroutines 696 */ 697 enum ioc_reply { 698 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 699 IOC_DONE, /* OK, reply sent */ 700 IOC_ACK, /* OK, just send ACK */ 701 IOC_REPLY, /* OK, just send reply */ 702 IOC_RESTART_ACK, /* OK, restart & ACK */ 703 IOC_RESTART_REPLY /* OK, restart & reply */ 704 }; 705 706 /* 707 * (Internal) return values from send_msg subroutines 708 */ 709 enum send_status { 710 SEND_FAIL = -1, /* Not OK */ 711 SEND_KEEP, /* OK, msg queued */ 712 SEND_FREE /* OK, free msg */ 713 }; 714 715 /* 716 * (Internal) enumeration of this driver's kstats 717 */ 718 enum { 719 BGE_KSTAT_RAW = 0, 720 BGE_KSTAT_STATS, 721 BGE_KSTAT_PARAMS, 722 BGE_KSTAT_CHIPID, 723 BGE_KSTAT_DRIVER, 724 BGE_KSTAT_PHYS, 725 BGE_KSTAT_MII, 726 727 BGE_KSTAT_COUNT 728 }; 729 730 #define BGE_MAX_RESOURCES 255 731 732 /* 733 * Per-instance soft-state structure 734 */ 735 typedef struct bge { 736 /* 737 * These fields are set by attach() and unchanged thereafter ... 738 */ 739 dev_info_t *devinfo; /* device instance */ 740 mac_handle_t mh; /* mac module handle */ 741 ddi_acc_handle_t cfg_handle; /* DDI I/O handle */ 742 ddi_acc_handle_t io_handle; /* DDI I/O handle */ 743 void *io_regs; /* mapped registers */ 744 cyclic_id_t cyclic_id; /* cyclic callback */ 745 ddi_softintr_t factotum_id; /* factotum callback */ 746 ddi_softintr_t resched_id; /* reschedule callback */ 747 748 ddi_intr_handle_t *htable; /* For array of interrupts */ 749 int intr_type; /* What type of interrupt */ 750 int intr_cnt; /* # of intrs count returned */ 751 uint_t intr_pri; /* Interrupt priority */ 752 int intr_cap; /* Interrupt capabilities */ 753 uint32_t progress; /* attach tracking */ 754 uint32_t debug; /* per-instance debug */ 755 chip_id_t chipid; 756 const phys_ops_t *physops; 757 char ifname[8]; /* "bge0" ... "bge999" */ 758 759 int fm_capabilities; /* FMA capabilities */ 760 761 /* 762 * These structures describe the blocks of memory allocated during 763 * attach(). They remain unchanged thereafter, although the memory 764 * they describe is carved up into various separate regions and may 765 * therefore be described by other structures as well. 766 */ 767 dma_area_t tx_desc; /* transmit descriptors */ 768 dma_area_t rx_desc[BGE_RECV_RINGS_SPLIT]; 769 /* receive descriptors */ 770 dma_area_t tx_buff[BGE_SPLIT]; 771 dma_area_t rx_buff[BGE_SPLIT]; 772 773 /* 774 * The memory described by the <dma_area> structures above 775 * is carved up into various pieces, which are described by 776 * the structures below. 777 */ 778 dma_area_t statistics; /* describes hardware */ 779 /* statistics area */ 780 dma_area_t status_block; /* describes hardware */ 781 /* status block */ 782 /* 783 * For the BCM5705/5788/5721/5751/5752/5714 and 5715, 784 * the statistic block is not available,the statistic counter must 785 * be gotten from statistic registers.And bge_statistics_reg_t record 786 * the statistic registers value 787 */ 788 bge_statistics_reg_t stat_val; 789 790 /* 791 * Runtime read-write data starts here ... 792 * 793 * 3 Buffer Rings (std/jumbo/mini) 794 * 16 Receive (Return) Rings 795 * 16 Send Rings 796 * 797 * Note: they're not necessarily all used. 798 */ 799 buff_ring_t buff[BGE_BUFF_RINGS_MAX]; /* 3*0x0100 */ 800 recv_ring_t recv[BGE_RECV_RINGS_MAX]; /* 16*0x0090 */ 801 send_ring_t send[BGE_SEND_RINGS_MAX]; /* 16*0x0100 */ 802 803 /* 804 * Locks: 805 * 806 * Each buffer ring contains its own <rf_lock> which regulates 807 * ring refilling. 808 * 809 * Each receive (return) ring contains its own <rx_lock> which 810 * protects the critical cyclic counters etc. 811 * 812 * Each send ring contains two locks: <tx_lock> for the send-path 813 * protocol data and <tc_lock> for send-buffer recycling. 814 * 815 * Finally <genlock> is a general lock, protecting most other 816 * operational data in the state structure and chip register 817 * accesses. It is acquired by the interrupt handler and 818 * most "mode-control" routines. 819 * 820 * Any of the locks can be acquired singly, but where multiple 821 * locks are acquired, they *must* be in the order: 822 * 823 * genlock >>> rx_lock >>> rf_lock >>> tx_lock >>> tc_lock. 824 * 825 * and within any one class of lock the rings must be locked in 826 * ascending order (send[0].tc_lock >>> send[1].tc_lock), etc. 827 * 828 * Note: actually I don't believe there's any need to acquire 829 * locks on multiple rings, or even locks of all these classes 830 * concurrently; but I've set out the above order so there is a 831 * clear definition of lock hierarchy in case it's ever needed. 832 * 833 * Note: the combinations of locks that are actually held 834 * concurrently are: 835 * 836 * genlock >>> (bge_chip_interrupt()) 837 * rx_lock[i] >>> (bge_receive()) 838 * rf_lock[n] (bge_refill()) 839 * tc_lock[i] (bge_recycle()) 840 */ 841 kmutex_t genlock[1]; 842 krwlock_t errlock[1]; 843 kmutex_t softintrlock[1]; 844 845 /* 846 * Current Ethernet addresses and multicast hash (bitmap) and 847 * refcount tables, protected by <genlock> 848 */ 849 bge_mac_addr_t curr_addr[MAC_ADDRESS_REGS_MAX]; 850 uint32_t mcast_hash[BGE_HASH_TABLE_SIZE/32]; 851 uint8_t mcast_refs[BGE_HASH_TABLE_SIZE]; 852 uint32_t unicst_addr_total; /* total unicst addresses */ 853 uint32_t unicst_addr_avail; 854 /* unused unicst addr slots */ 855 856 /* 857 * Link state data (protected by genlock) 858 */ 859 const char *link_mode_msg; /* describes link mode */ 860 const char *link_down_msg; /* reason for link DOWN */ 861 const char *link_up_msg; /* comment on link UP */ 862 863 link_state_t link_state; 864 865 /* 866 * Physical layer (PHY/SerDes) state data (protected by genlock) 867 */ 868 hrtime_t phys_write_time; /* when last written */ 869 hrtime_t phys_event_time; /* when status changed */ 870 hrtime_t phys_delta_time; /* time to settle */ 871 872 /* 873 * Physical layer: copper only 874 */ 875 bge_regno_t phy_mii_addr; /* should be (const) 1! */ 876 uint16_t phy_gen_status; 877 uint16_t phy_aux_status; 878 879 /* 880 * Physical layer: serdes only 881 */ 882 uint32_t serdes_status; 883 uint32_t serdes_advert; 884 uint32_t serdes_lpadv; 885 886 /* 887 * Driver kstats, protected by <genlock> where necessary 888 */ 889 kstat_t *bge_kstats[BGE_KSTAT_COUNT]; 890 891 /* 892 * Miscellaneous operating variables (protected by genlock) 893 */ 894 uint64_t chip_resets; /* # of chip RESETs */ 895 uint64_t missed_dmas; /* # of missed DMAs */ 896 enum bge_mac_state bge_mac_state; /* definitions above */ 897 enum bge_chip_state bge_chip_state; /* definitions above */ 898 boolean_t send_hw_tcp_csum; 899 boolean_t recv_hw_tcp_csum; 900 boolean_t promisc; 901 902 /* 903 * Miscellaneous operating variables (not synchronised) 904 */ 905 uint32_t watchdog; /* watches for Tx stall */ 906 boolean_t bge_intr_running; 907 boolean_t bge_dma_error; 908 boolean_t resched_needed; 909 boolean_t resched_running; 910 uint32_t factotum_flag; /* softint pending */ 911 uintptr_t pagemask; 912 913 /* 914 * NDD parameters (protected by genlock) 915 */ 916 caddr_t nd_data_p; 917 nd_param_t nd_params[PARAM_COUNT]; 918 919 uintptr_t resmap[BGE_MAX_RESOURCES]; 920 921 /* 922 * A flag to prevent excessive config space accesses 923 * on platforms having BCM5714C/15C 924 */ 925 boolean_t lastWriteZeroData; 926 927 /* 928 * Spare space, plus guard element used to check data integrity 929 */ 930 uint64_t spare[5]; 931 uint64_t bge_guard; 932 933 /* 934 * Receive rules configure 935 */ 936 bge_recv_rule_t recv_rules[RECV_RULES_NUM_MAX]; 937 938 #ifdef BGE_IPMI_ASF 939 boolean_t asf_enabled; 940 boolean_t asf_wordswapped; 941 boolean_t asf_newhandshake; 942 boolean_t asf_pseudostop; 943 944 uint32_t asf_status; 945 timeout_id_t asf_timeout_id; 946 #endif 947 } bge_t; 948 949 /* 950 * 'Progress' bit flags ... 951 */ 952 #define PROGRESS_CFG 0x0001 /* config space mapped */ 953 #define PROGRESS_REGS 0x0002 /* registers mapped */ 954 #define PROGRESS_BUFS 0x0004 /* ring buffers allocated */ 955 #define PROGRESS_RESCHED 0x0010 /* resched softint registered */ 956 #define PROGRESS_FACTOTUM 0x0020 /* factotum softint registered */ 957 #define PROGRESS_HWINT 0x0040 /* h/w interrupt registered */ 958 /* and mutexen initialised */ 959 #define PROGRESS_INTR 0x0080 /* Intrs enabled */ 960 #define PROGRESS_PHY 0x0100 /* PHY initialised */ 961 #define PROGRESS_NDD 0x1000 /* NDD parameters set up */ 962 #define PROGRESS_KSTATS 0x2000 /* kstats created */ 963 #define PROGRESS_READY 0x8000 /* ready for work */ 964 965 /* 966 * Shorthand for the NDD parameters 967 */ 968 #define param_adv_autoneg nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val 969 #define param_adv_pause nd_params[PARAM_ADV_PAUSE_CAP].ndp_val 970 #define param_adv_asym_pause nd_params[PARAM_ADV_ASYM_PAUSE_CAP].ndp_val 971 #define param_adv_1000fdx nd_params[PARAM_ADV_1000FDX_CAP].ndp_val 972 #define param_adv_1000hdx nd_params[PARAM_ADV_1000HDX_CAP].ndp_val 973 #define param_adv_100fdx nd_params[PARAM_ADV_100FDX_CAP].ndp_val 974 #define param_adv_100hdx nd_params[PARAM_ADV_100HDX_CAP].ndp_val 975 #define param_adv_10fdx nd_params[PARAM_ADV_10FDX_CAP].ndp_val 976 #define param_adv_10hdx nd_params[PARAM_ADV_10HDX_CAP].ndp_val 977 978 #define param_lp_autoneg nd_params[PARAM_LP_AUTONEG_CAP].ndp_val 979 #define param_lp_pause nd_params[PARAM_LP_PAUSE_CAP].ndp_val 980 #define param_lp_asym_pause nd_params[PARAM_LP_ASYM_PAUSE_CAP].ndp_val 981 #define param_lp_1000fdx nd_params[PARAM_LP_1000FDX_CAP].ndp_val 982 #define param_lp_1000hdx nd_params[PARAM_LP_1000HDX_CAP].ndp_val 983 #define param_lp_100fdx nd_params[PARAM_LP_100FDX_CAP].ndp_val 984 #define param_lp_100hdx nd_params[PARAM_LP_100HDX_CAP].ndp_val 985 #define param_lp_10fdx nd_params[PARAM_LP_10FDX_CAP].ndp_val 986 #define param_lp_10hdx nd_params[PARAM_LP_10HDX_CAP].ndp_val 987 988 #define param_link_up nd_params[PARAM_LINK_STATUS].ndp_val 989 #define param_link_speed nd_params[PARAM_LINK_SPEED].ndp_val 990 #define param_link_duplex nd_params[PARAM_LINK_DUPLEX].ndp_val 991 992 #define param_link_autoneg nd_params[PARAM_LINK_AUTONEG].ndp_val 993 #define param_link_rx_pause nd_params[PARAM_LINK_RX_PAUSE].ndp_val 994 #define param_link_tx_pause nd_params[PARAM_LINK_TX_PAUSE].ndp_val 995 996 #define param_loop_mode nd_params[PARAM_LOOP_MODE].ndp_val 997 #define param_msi_cnt nd_params[PARAM_MSI_CNT].ndp_val 998 999 /* 1000 * Sync a DMA area described by a dma_area_t 1001 */ 1002 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl, \ 1003 (area).offset, (area).alength, (flag))) 1004 1005 /* 1006 * Find the (kernel virtual) address of block of memory 1007 * described by a dma_area_t 1008 */ 1009 #define DMA_VPTR(area) ((area).mem_va) 1010 1011 /* 1012 * Zero a block of memory described by a dma_area_t 1013 */ 1014 #define DMA_ZERO(area) bzero(DMA_VPTR(area), (area).alength) 1015 1016 /* 1017 * Next value of a cyclic index 1018 */ 1019 #define NEXT(index, limit) ((index)+1 < (limit) ? (index)+1 : 0); 1020 1021 /* 1022 * Property lookups 1023 */ 1024 #define BGE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 1025 DDI_PROP_DONTPASS, (n)) 1026 #define BGE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 1027 DDI_PROP_DONTPASS, (n), -1) 1028 1029 /* 1030 * Copy an ethernet address 1031 */ 1032 #define ethaddr_copy(src, dst) bcopy((src), (dst), ETHERADDRL) 1033 1034 /* 1035 * Endian swap 1036 */ 1037 /* BEGIN CSTYLED */ 1038 #define BGE_BSWAP_32(x) ((((x) & 0xff000000) >> 24) | \ 1039 (((x) & 0x00ff0000) >> 8) | \ 1040 (((x) & 0x0000ff00) << 8) | \ 1041 (((x) & 0x000000ff) << 24)) 1042 /* END CSTYLED */ 1043 1044 /* 1045 * Marker value placed at the end of the driver's state 1046 */ 1047 #define BGE_GUARD 0x1919306009031802 1048 1049 /* 1050 * Bit flags in the 'debug' word ... 1051 */ 1052 #define BGE_DBG_STOP 0x00000001 /* early debug_enter() */ 1053 #define BGE_DBG_TRACE 0x00000002 /* general flow tracing */ 1054 1055 #define BGE_DBG_REGS 0x00000010 /* low-level accesses */ 1056 #define BGE_DBG_MII 0x00000020 /* low-level MII access */ 1057 #define BGE_DBG_SEEPROM 0x00000040 /* low-level SEEPROM IO */ 1058 #define BGE_DBG_CHIP 0x00000080 /* low(ish)-level code */ 1059 1060 #define BGE_DBG_RECV 0x00000100 /* receive-side code */ 1061 #define BGE_DBG_SEND 0x00000200 /* packet-send code */ 1062 1063 #define BGE_DBG_INT 0x00001000 /* interrupt handler */ 1064 #define BGE_DBG_FACT 0x00002000 /* factotum (softint) */ 1065 1066 #define BGE_DBG_PHY 0x00010000 /* Copper PHY code */ 1067 #define BGE_DBG_SERDES 0x00020000 /* SerDes code */ 1068 #define BGE_DBG_PHYS 0x00040000 /* Physical layer code */ 1069 #define BGE_DBG_LINK 0x00080000 /* Link status check */ 1070 1071 #define BGE_DBG_INIT 0x00100000 /* initialisation */ 1072 #define BGE_DBG_NEMO 0x00200000 /* nemo interaction */ 1073 #define BGE_DBG_ADDR 0x00400000 /* address-setting code */ 1074 #define BGE_DBG_STATS 0x00800000 /* statistics */ 1075 1076 #define BGE_DBG_IOCTL 0x01000000 /* ioctl handling */ 1077 #define BGE_DBG_LOOP 0x02000000 /* loopback ioctl code */ 1078 #define BGE_DBG_PPIO 0x04000000 /* Peek/poke ioctls */ 1079 #define BGE_DBG_BADIOC 0x08000000 /* unknown ioctls */ 1080 1081 #define BGE_DBG_MCTL 0x10000000 /* mctl (csum) code */ 1082 #define BGE_DBG_NDD 0x20000000 /* NDD operations */ 1083 1084 /* 1085 * Debugging ... 1086 */ 1087 #ifdef DEBUG 1088 #define BGE_DEBUGGING 1 1089 #else 1090 #define BGE_DEBUGGING 0 1091 #endif /* DEBUG */ 1092 1093 1094 /* 1095 * 'Do-if-debugging' macro. The parameter <command> should be one or more 1096 * C statements (but without the *final* semicolon), which will either be 1097 * compiled inline or completely ignored, depending on the BGE_DEBUGGING 1098 * compile-time flag. 1099 * 1100 * You should get a compile-time error (at least on a DEBUG build) if 1101 * your statement isn't actually a statement, rather than unexpected 1102 * run-time behaviour caused by unintended matching of if-then-elses etc. 1103 * 1104 * Note that the BGE_DDB() macro itself can only be used as a statement, 1105 * not an expression, and should always be followed by a semicolon. 1106 */ 1107 #if BGE_DEBUGGING 1108 #define BGE_DDB(command) do { \ 1109 { command; } \ 1110 _NOTE(CONSTANTCONDITION) \ 1111 } while (0) 1112 #else /* BGE_DEBUGGING */ 1113 #define BGE_DDB(command) do { \ 1114 { _NOTE(EMPTY); } \ 1115 _NOTE(CONSTANTCONDITION) \ 1116 } while (0) 1117 #endif /* BGE_DEBUGGING */ 1118 1119 /* 1120 * 'Internal' macros used to construct the TRACE/DEBUG macros below. 1121 * These provide the primitive conditional-call capability required. 1122 * Note: the parameter <args> is a parenthesised list of the actual 1123 * printf-style arguments to be passed to the debug function ... 1124 */ 1125 #define BGE_XDB(b, w, f, args) BGE_DDB(if ((b) & (w)) f args) 1126 #define BGE_GDB(b, args) BGE_XDB(b, bge_debug, (*bge_gdb()), args) 1127 #define BGE_LDB(b, args) BGE_XDB(b, bgep->debug, (*bge_db(bgep)), args) 1128 #define BGE_CDB(f, args) BGE_XDB(BGE_DBG, bgep->debug, f, args) 1129 1130 /* 1131 * Conditional-print macros. 1132 * 1133 * Define BGE_DBG to be the relevant member of the set of BGE_DBG_* values 1134 * above before using the BGE_GDEBUG() or BGE_DEBUG() macros. The 'G' 1135 * versions look at the Global debug flag word (bge_debug); the non-G 1136 * versions look in the per-instance data (bgep->debug) and so require a 1137 * variable called 'bgep' to be in scope (and initialised!) before use. 1138 * 1139 * You could redefine BGE_TRC too if you really need two different 1140 * flavours of debugging output in the same area of code, but I don't 1141 * really recommend it. 1142 * 1143 * Note: the parameter <args> is a parenthesised list of the actual 1144 * arguments to be passed to the debug function, usually a printf-style 1145 * format string and corresponding values to be formatted. 1146 */ 1147 1148 #define BGE_TRC BGE_DBG_TRACE /* default 'trace' bit */ 1149 #define BGE_GTRACE(args) BGE_GDB(BGE_TRC, args) 1150 #define BGE_GDEBUG(args) BGE_GDB(BGE_DBG, args) 1151 #define BGE_TRACE(args) BGE_LDB(BGE_TRC, args) 1152 #define BGE_DEBUG(args) BGE_LDB(BGE_DBG, args) 1153 1154 /* 1155 * Debug-only action macros 1156 */ 1157 #define BGE_BRKPT(bgep, s) BGE_DDB(bge_dbg_enter(bgep, s)) 1158 #define BGE_MARK(bgep) BGE_DDB(bge_led_mark(bgep)) 1159 #define BGE_PCICHK(bgep) BGE_DDB(bge_pci_check(bgep)) 1160 #define BGE_PKTDUMP(args) BGE_DDB(bge_pkt_dump args) 1161 #define BGE_REPORT(args) BGE_DDB(bge_log args) 1162 1163 /* 1164 * Inter-source-file linkage ... 1165 */ 1166 1167 /* bge_chip.c */ 1168 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1169 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t value); 1170 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 1171 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t value); 1172 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 1173 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 1174 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t value); 1175 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 1176 int bge_chip_id_init(bge_t *bgep); 1177 int bge_chip_start(bge_t *bgep, boolean_t reset_phy); 1178 void bge_chip_stop(bge_t *bgep, boolean_t fault); 1179 #ifdef BGE_IPMI_ASF 1180 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 1181 #pragma inline(bge_nic_put32) 1182 uint32_t bge_nic_read32(bge_t *bgep, bge_regno_t addr); 1183 void bge_asf_update_status(bge_t *bgep); 1184 void bge_asf_heartbeat(void *bgep); 1185 void bge_asf_stop_timer(bge_t *bgep); 1186 void bge_asf_get_config(bge_t *bgep); 1187 void bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode); 1188 void bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode); 1189 void bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode); 1190 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 1191 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 1192 #else 1193 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 1194 int bge_chip_sync(bge_t *bgep); 1195 #endif 1196 void bge_chip_blank(void *arg, time_t ticks, uint_t count); 1197 uint_t bge_chip_factotum(caddr_t arg); 1198 void bge_chip_cyclic(void *arg); 1199 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 1200 struct iocblk *iocp); 1201 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 1202 extern uint32_t bge_rx_ticks_norm; 1203 extern uint32_t bge_tx_ticks_norm; 1204 extern uint32_t bge_rx_count_norm; 1205 extern uint32_t bge_tx_count_norm; 1206 extern boolean_t bge_jumbo_enable; 1207 void bge_chip_msi_trig(bge_t *bgep); 1208 1209 /* bge_kstats.c */ 1210 void bge_init_kstats(bge_t *bgep, int instance); 1211 void bge_fini_kstats(bge_t *bgep); 1212 int bge_m_stat(void *arg, uint_t stat, uint64_t *val); 1213 1214 /* bge_log.c */ 1215 #if BGE_DEBUGGING 1216 void (*bge_db(bge_t *bgep))(const char *fmt, ...); 1217 void (*bge_gdb(void))(const char *fmt, ...); 1218 void bge_pkt_dump(bge_t *bgep, bge_rbd_t *hbp, sw_rbd_t *sdp, const char *msg); 1219 void bge_dbg_enter(bge_t *bgep, const char *msg); 1220 #endif /* BGE_DEBUGGING */ 1221 void bge_problem(bge_t *bgep, const char *fmt, ...); 1222 void bge_notice(bge_t *bgep, const char *fmt, ...); 1223 void bge_log(bge_t *bgep, const char *fmt, ...); 1224 void bge_error(bge_t *bgep, const char *fmt, ...); 1225 void bge_fm_ereport(bge_t *bgep, char *detail); 1226 extern kmutex_t bge_log_mutex[1]; 1227 extern uint32_t bge_debug; 1228 1229 /* bge_main.c */ 1230 int bge_restart(bge_t *bgep, boolean_t reset_phy); 1231 int bge_check_acc_handle(bge_t *bgep, ddi_acc_handle_t handle); 1232 int bge_check_dma_handle(bge_t *bgep, ddi_dma_handle_t handle); 1233 void bge_init_rings(bge_t *bgep); 1234 void bge_fini_rings(bge_t *bgep); 1235 int bge_alloc_bufs(bge_t *bgep); 1236 void bge_free_bufs(bge_t *bgep); 1237 void bge_intr_enable(bge_t *bgep); 1238 void bge_intr_disable(bge_t *bgep); 1239 1240 /* bge_phys.c */ 1241 int bge_phys_init(bge_t *bgep); 1242 void bge_phys_reset(bge_t *bgep); 1243 int bge_phys_idle(bge_t *bgep); 1244 int bge_phys_update(bge_t *bgep); 1245 boolean_t bge_phys_check(bge_t *bgep); 1246 1247 /* bge_ndd.c */ 1248 int bge_nd_init(bge_t *bgep); 1249 enum ioc_reply bge_nd_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 1250 struct iocblk *iocp); 1251 void bge_nd_cleanup(bge_t *bgep); 1252 1253 /* bge_recv.c */ 1254 void bge_receive(bge_t *bgep, bge_status_t *bsp); 1255 1256 /* bge_send.c */ 1257 mblk_t *bge_m_tx(void *arg, mblk_t *mp); 1258 void bge_recycle(bge_t *bgep, bge_status_t *bsp); 1259 uint_t bge_reschedule(caddr_t arg); 1260 1261 /* bge_atomic_sparc.s/bge_atomic_intel.c */ 1262 uint64_t bge_atomic_reserve(uint64_t *count_p, uint64_t n); 1263 void bge_atomic_renounce(uint64_t *count_p, uint64_t n); 1264 uint64_t bge_atomic_claim(uint64_t *count_p, uint64_t limit); 1265 uint64_t bge_atomic_clr64(uint64_t *sp, uint64_t bits); 1266 uint32_t bge_atomic_shl32(uint32_t *sp, uint_t count); 1267 1268 1269 /* 1270 * Reset type 1271 */ 1272 #define BGE_SHUTDOWN_RESET 0 1273 #define BGE_INIT_RESET 1 1274 #define BGE_SUSPEND_RESET 2 1275 1276 /* For asf_status */ 1277 #define ASF_STAT_NONE 0 1278 #define ASF_STAT_STOP 1 1279 #define ASF_STAT_RUN 2 1280 #define ASF_STAT_RUN_INIT 3 /* attached but don't plumb */ 1281 1282 /* ASF modes for bge_reset() and bge_chip_reset() */ 1283 #define ASF_MODE_NONE 0 /* don't launch asf */ 1284 #define ASF_MODE_SHUTDOWN 1 /* asf shutdown mode */ 1285 #define ASF_MODE_INIT 2 /* asf init mode */ 1286 #define ASF_MODE_POST_SHUTDOWN 3 /* only do post-shutdown */ 1287 #define ASF_MODE_POST_INIT 4 /* only do post-init */ 1288 1289 #define BGE_ASF_HEARTBEAT_INTERVAL 1500000 1290 1291 #ifdef __cplusplus 1292 } 1293 #endif 1294 1295 #endif /* _SYS_BGE_IMPL_H */ 1296