1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _BGE_HW_H 28 #define _BGE_HW_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <sys/types.h> 35 36 37 /* 38 * First section: 39 * Identification of the various Broadcom chips 40 * 41 * Note: the various ID values are *not* all unique ;-( 42 * 43 * Note: the presence of an ID here does *not* imply that the chip is 44 * supported. At this time, only the 5703C, 5704C, and 5704S devices 45 * used on the motherboards of certain Sun products are supported. 46 * 47 * Note: the revision-id values in the PCI revision ID register are 48 * *NOT* guaranteed correct. Use the chip ID from the MHCR instead. 49 */ 50 51 #define VENDOR_ID_BROADCOM 0x14e4 52 #define VENDOR_ID_SUN 0x108e 53 54 #define DEVICE_ID_5700 0x1644 55 #define DEVICE_ID_5700x 0x0003 56 #define DEVICE_ID_5701 0x1645 57 #define DEVICE_ID_5702 0x16a6 58 #define DEVICE_ID_5702fe 0x164d 59 #define DEVICE_ID_5703C 0x1647 60 #define DEVICE_ID_5703S 0x16a7 61 #define DEVICE_ID_5703 0x16c7 62 #define DEVICE_ID_5704C 0x1648 63 #define DEVICE_ID_5704S 0x16a8 64 #define DEVICE_ID_5704 0x1649 65 #define DEVICE_ID_5705C 0x1653 66 #define DEVICE_ID_5705_2 0x1654 67 #define DEVICE_ID_5705M 0x165d 68 #define DEVICE_ID_5705MA3 0x165e 69 #define DEVICE_ID_5705F 0x166e 70 #define DEVICE_ID_5780 0x166a 71 #define DEVICE_ID_5782 0x1696 72 #define DEVICE_ID_5787 0x169b 73 #define DEVICE_ID_5787M 0x1693 74 #define DEVICE_ID_5788 0x169c 75 #define DEVICE_ID_5789 0x169d 76 #define DEVICE_ID_5751 0x1677 77 #define DEVICE_ID_5751M 0x167d 78 #define DEVICE_ID_5752 0x1600 79 #define DEVICE_ID_5752M 0x1601 80 #define DEVICE_ID_5753 0x16fd 81 #define DEVICE_ID_5754 0x167a 82 #define DEVICE_ID_5755 0x167b 83 #define DEVICE_ID_5755M 0x1673 84 #define DEVICE_ID_5756M 0x1674 85 #define DEVICE_ID_5721 0x1659 86 #define DEVICE_ID_5722 0x165a 87 #define DEVICE_ID_5723 0x165b 88 #define DEVICE_ID_5714C 0x1668 89 #define DEVICE_ID_5714S 0x1669 90 #define DEVICE_ID_5715C 0x1678 91 #define DEVICE_ID_5715S 0x1679 92 #define DEVICE_ID_5906 0x1712 93 #define DEVICE_ID_5906M 0x1713 94 95 #define REVISION_ID_5700_B0 0x10 96 #define REVISION_ID_5700_B2 0x12 97 #define REVISION_ID_5700_B3 0x13 98 #define REVISION_ID_5700_C0 0x20 99 #define REVISION_ID_5700_C1 0x21 100 #define REVISION_ID_5700_C2 0x22 101 102 #define REVISION_ID_5701_A0 0x08 103 #define REVISION_ID_5701_A2 0x12 104 #define REVISION_ID_5701_A3 0x15 105 106 #define REVISION_ID_5702_A0 0x00 107 108 #define REVISION_ID_5703_A0 0x00 109 #define REVISION_ID_5703_A1 0x01 110 #define REVISION_ID_5703_A2 0x02 111 112 #define REVISION_ID_5704_A0 0x00 113 #define REVISION_ID_5704_A1 0x01 114 #define REVISION_ID_5704_A2 0x02 115 #define REVISION_ID_5704_A3 0x03 116 #define REVISION_ID_5704_B0 0x10 117 118 #define REVISION_ID_5705_A0 0x00 119 #define REVISION_ID_5705_A1 0x01 120 #define REVISION_ID_5705_A2 0x02 121 #define REVISION_ID_5705_A3 0x03 122 123 #define REVISION_ID_5721_A0 0x00 124 #define REVISION_ID_5721_A1 0x01 125 126 #define REVISION_ID_5751_A0 0x00 127 #define REVISION_ID_5751_A1 0x01 128 129 #define REVISION_ID_5714_A0 0x00 130 #define REVISION_ID_5714_A1 0x01 131 #define REVISION_ID_5714_A2 0xA2 132 #define REVISION_ID_5714_A3 0xA3 133 134 #define REVISION_ID_5715_A0 0x00 135 #define REVISION_ID_5715_A1 0x01 136 #define REVISION_ID_5715_A2 0xA2 137 138 #define REVISION_ID_5715S_A0 0x00 139 #define REVISION_ID_5715S_A1 0x01 140 141 #define REVISION_ID_5754_A0 0x00 142 #define REVISION_ID_5754_A1 0x01 143 144 #define DEVICE_5704_SERIES_CHIPSETS(bgep)\ 145 ((bgep->chipid.device == DEVICE_ID_5700) ||\ 146 (bgep->chipid.device == DEVICE_ID_5701) ||\ 147 (bgep->chipid.device == DEVICE_ID_5702) ||\ 148 (bgep->chipid.device == DEVICE_ID_5702fe)||\ 149 (bgep->chipid.device == DEVICE_ID_5703C) ||\ 150 (bgep->chipid.device == DEVICE_ID_5703S) ||\ 151 (bgep->chipid.device == DEVICE_ID_5703) ||\ 152 (bgep->chipid.device == DEVICE_ID_5704C) ||\ 153 (bgep->chipid.device == DEVICE_ID_5704S) ||\ 154 (bgep->chipid.device == DEVICE_ID_5704)) 155 156 #define DEVICE_5702_SERIES_CHIPSETS(bgep) \ 157 ((bgep->chipid.device == DEVICE_ID_5702) ||\ 158 (bgep->chipid.device == DEVICE_ID_5702fe)) 159 160 #define DEVICE_5705_SERIES_CHIPSETS(bgep) \ 161 ((bgep->chipid.device == DEVICE_ID_5705C) ||\ 162 (bgep->chipid.device == DEVICE_ID_5705M) ||\ 163 (bgep->chipid.device == DEVICE_ID_5705MA3) ||\ 164 (bgep->chipid.device == DEVICE_ID_5705F) ||\ 165 (bgep->chipid.device == DEVICE_ID_5780) ||\ 166 (bgep->chipid.device == DEVICE_ID_5782) ||\ 167 (bgep->chipid.device == DEVICE_ID_5788) ||\ 168 (bgep->chipid.device == DEVICE_ID_5705_2) ||\ 169 (bgep->chipid.device == DEVICE_ID_5754) ||\ 170 (bgep->chipid.device == DEVICE_ID_5755) ||\ 171 (bgep->chipid.device == DEVICE_ID_5756M) ||\ 172 (bgep->chipid.device == DEVICE_ID_5753)) 173 174 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \ 175 ((bgep->chipid.device == DEVICE_ID_5721) ||\ 176 (bgep->chipid.device == DEVICE_ID_5751) ||\ 177 (bgep->chipid.device == DEVICE_ID_5751M) ||\ 178 (bgep->chipid.device == DEVICE_ID_5752) ||\ 179 (bgep->chipid.device == DEVICE_ID_5752M) ||\ 180 (bgep->chipid.device == DEVICE_ID_5789)) 181 182 #define DEVICE_5723_SERIES_CHIPSETS(bgep) \ 183 (bgep->chipid.device == DEVICE_ID_5723) 184 185 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \ 186 ((bgep->chipid.device == DEVICE_ID_5714C) ||\ 187 (bgep->chipid.device == DEVICE_ID_5714S) ||\ 188 (bgep->chipid.device == DEVICE_ID_5715C) ||\ 189 (bgep->chipid.device == DEVICE_ID_5715S)) 190 191 #define DEVICE_5906_SERIES_CHIPSETS(bgep) \ 192 ((bgep->chipid.device == DEVICE_ID_5906) ||\ 193 (bgep->chipid.device == DEVICE_ID_5906M)) 194 195 /* 196 * Second section: 197 * Offsets of important registers & definitions for bits therein 198 */ 199 200 /* 201 * PCI-X registers & bits 202 */ 203 #define PCIX_CONF_COMM 0x42 204 #define PCIX_COMM_RELAXED 0x0002 205 206 /* 207 * Miscellaneous Host Control Register, in PCI config space 208 */ 209 #define PCI_CONF_BGE_MHCR 0x68 210 #define MHCR_CHIP_REV_MASK 0xffff0000 211 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200 212 #define MHCR_MASK_INTERRUPT_MODE 0x00000100 213 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080 214 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040 215 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020 216 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010 217 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008 218 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004 219 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002 220 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001 221 222 #define MHCR_CHIP_REV_5700_B0 0x71000000 223 #define MHCR_CHIP_REV_5700_B2 0x71020000 224 #define MHCR_CHIP_REV_5700_B3 0x71030000 225 #define MHCR_CHIP_REV_5700_C0 0x72000000 226 #define MHCR_CHIP_REV_5700_C1 0x72010000 227 #define MHCR_CHIP_REV_5700_C2 0x72020000 228 229 #define MHCR_CHIP_REV_5701_A0 0x00000000 230 #define MHCR_CHIP_REV_5701_A2 0x00020000 231 #define MHCR_CHIP_REV_5701_A3 0x00030000 232 #define MHCR_CHIP_REV_5701_A5 0x01050000 233 234 #define MHCR_CHIP_REV_5702_A0 0x10000000 235 #define MHCR_CHIP_REV_5702_A1 0x10010000 236 #define MHCR_CHIP_REV_5702_A2 0x10020000 237 238 #define MHCR_CHIP_REV_5703_A0 0x10000000 239 #define MHCR_CHIP_REV_5703_A1 0x10010000 240 #define MHCR_CHIP_REV_5703_A2 0x10020000 241 #define MHCR_CHIP_REV_5703_B0 0x11000000 242 #define MHCR_CHIP_REV_5703_B1 0x11010000 243 244 #define MHCR_CHIP_REV_5704_A0 0x20000000 245 #define MHCR_CHIP_REV_5704_A1 0x20010000 246 #define MHCR_CHIP_REV_5704_A2 0x20020000 247 #define MHCR_CHIP_REV_5704_A3 0x20030000 248 #define MHCR_CHIP_REV_5704_B0 0x21000000 249 250 #define MHCR_CHIP_REV_5705_A0 0x30000000 251 #define MHCR_CHIP_REV_5705_A1 0x30010000 252 #define MHCR_CHIP_REV_5705_A2 0x30020000 253 #define MHCR_CHIP_REV_5705_A3 0x30030000 254 #define MHCR_CHIP_REV_5705_A5 0x30050000 255 256 #define MHCR_CHIP_REV_5782_A0 0x30030000 257 #define MHCR_CHIP_REV_5782_A1 0x30030088 258 259 #define MHCR_CHIP_REV_5788_A1 0x30050000 260 261 #define MHCR_CHIP_REV_5751_A0 0x40000000 262 #define MHCR_CHIP_REV_5751_A1 0x40010000 263 264 #define MHCR_CHIP_REV_5721_A0 0x41000000 265 #define MHCR_CHIP_REV_5721_A1 0x41010000 266 267 #define MHCR_CHIP_REV_5714_A0 0x50000000 268 #define MHCR_CHIP_REV_5714_A1 0x90010000 269 270 #define MHCR_CHIP_REV_5715_A0 0x50000000 271 #define MHCR_CHIP_REV_5715_A1 0x90010000 272 273 #define MHCR_CHIP_REV_5715S_A0 0x50000000 274 #define MHCR_CHIP_REV_5715S_A1 0x90010000 275 276 #define MHCR_CHIP_REV_5754_A0 0xb0000000 277 #define MHCR_CHIP_REV_5754_A1 0xb0010000 278 279 #define MHCR_CHIP_REV_5787_A0 0xb0000000 280 #define MHCR_CHIP_REV_5787_A1 0xb0010000 281 #define MHCR_CHIP_REV_5787_A2 0xb0020000 282 283 #define MHCR_CHIP_REV_5755_A0 0xa0000000 284 #define MHCR_CHIP_REV_5755_A1 0xa0010000 285 286 #define MHCR_CHIP_REV_5906_A0 0xc0000000 287 #define MHCR_CHIP_REV_5906_A1 0xc0010000 288 #define MHCR_CHIP_REV_5906_A2 0xc0020000 289 290 #define MHCR_CHIP_REV_5723_A0 0xf0000000 291 #define MHCR_CHIP_REV_5723_A1 0xf0010000 292 #define MHCR_CHIP_REV_5723_A2 0xf0020000 293 #define MHCR_CHIP_REV_5723_B0 0xf1000000 294 295 #define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000) 296 #define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28) 297 #define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28) 298 #define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28) 299 #define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28) 300 #define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28) 301 #define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28) 302 #define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28) 303 #define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28) 304 #define MHCR_CHIP_ASIC_REV_5754 (0xb << 28) 305 #define MHCR_CHIP_ASIC_REV_5787 ((uint32_t)0xb << 28) 306 #define MHCR_CHIP_ASIC_REV_5755 ((uint32_t)0xa << 28) 307 #define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28) 308 #define MHCR_CHIP_ASIC_REV_5906 ((uint32_t)0xc << 28) 309 #define MHCR_CHIP_ASIC_REV_5723 ((uint32_t)0xf << 28) 310 311 312 /* 313 * PCI DMA read/write Control Register, in PCI config space 314 * 315 * Note that several fields previously defined here have been deleted 316 * as they are not implemented in the 5703/4. 317 * 318 * Note: the value of this register is critical. It is possible to 319 * cause various unpleasant effects (DTOs, transaction deadlock, etc) 320 * by programming the wrong value. The value #defined below has been 321 * tested and shown to avoid all known problems. If it is to be changed, 322 * correct operation must be reverified on all supported platforms. 323 * 324 * In particular, we set both watermark fields to 2xCacheLineSize (128) 325 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions 326 * with Tomatillo's internal pipelines, that otherwise result in stalls, 327 * repeated retries, and DTOs. 328 */ 329 #define PCI_CONF_BGE_PDRWCR 0x6c 330 #define PDRWCR_RWCMD_MASK 0xFF000000 331 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000 332 #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000 333 #define PDRWCR_READ_WATERMARK_MASK 0x00070000 334 #define PDRWCR_CONCURRENCY_MASK 0x0000c000 335 #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000 336 #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000 337 #define PDRWCR_MIN_BEAT_MASK 0x000000ff 338 339 /* 340 * These are the actual values to be put into the fields shown above 341 */ 342 #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */ 343 #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */ 344 #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */ 345 #define PDRWCR_MIN_BEATS 0x00000000 346 347 #define PDRWCR_VAR_DEFAULT 0x761b0000 348 #define PDRWCR_VAR_5721 0x76180000 349 #define PDRWCR_VAR_5714 0x76148000 /* OR of above */ 350 #define PDRWCR_VAR_5715 0x76144000 /* OR of above */ 351 352 /* 353 * PCI State Register, in PCI config space 354 * 355 * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit 356 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW 357 */ 358 #define PCI_CONF_BGE_PCISTATE 0x70 359 #define PCISTATE_RETRY_SAME_DMA 0x00002000 360 #define PCISTATE_FLAT_VIEW 0x00000100 361 #define PCISTATE_EXT_ROM_RETRY 0x00000040 362 #define PCISTATE_EXT_ROM_ENABLE 0x00000020 363 #define PCISTATE_BUS_IS_32_BIT 0x00000010 364 #define PCISTATE_BUS_IS_FAST 0x00000008 365 #define PCISTATE_BUS_IS_PCI 0x00000004 366 #define PCISTATE_INTA_STATE 0x00000002 367 #define PCISTATE_FORCE_RESET 0x00000001 368 369 /* 370 * PCI Clock Control Register, in PCI config space 371 */ 372 #define PCI_CONF_BGE_CLKCTL 0x74 373 #define CLKCTL_PCIE_PLP_DISABLE 0x80000000 374 #define CLKCTL_PCIE_DLP_DISABLE 0x40000000 375 #define CLKCTL_PCIE_TLP_DISABLE 0x20000000 376 #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000 377 #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000 378 #define CLKCTL_PCIE_A0_FIX 0x00101000 379 380 /* 381 * Dual MAC Control Register, in PCI config space 382 */ 383 #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8 384 #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */ 385 #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */ 386 387 /* 388 * Register Indirect Access Address Register, 0x78 in PCI config 389 * space. Once this is set, accesses to the Register Indirect 390 * Access Data Register (0x80) refer to the register whose address 391 * is given by *this* register. This allows access to all the 392 * operating registers, while using only config space accesses. 393 * 394 * Note that the address written to the RIIAR should lie in one 395 * of the following ranges: 396 * 0x00000000 <= address < 0x00008000 (regular registers) 397 * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad) 398 * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad) 399 * 0x00038000 <= address < 0x00038800 (RxRISC ROM) 400 */ 401 #define PCI_CONF_BGE_RIAAR 0x78 402 #define PCI_CONF_BGE_RIADR 0x80 403 404 #define RIAAR_REGISTER_MIN 0x00000000 405 #define RIAAR_REGISTER_MAX 0x00008000 406 #define RIAAR_RX_SCRATCH_MIN 0x00030000 407 #define RIAAR_RX_SCRATCH_MAX 0x00034000 408 #define RIAAR_TX_SCRATCH_MIN 0x00034000 409 #define RIAAR_TX_SCRATCH_MAX 0x00038000 410 #define RIAAR_RXROM_MIN 0x00038000 411 #define RIAAR_RXROM_MAX 0x00038800 412 413 /* 414 * Memory Window Base Address Register, 0x7c in PCI config space 415 * Once this is set, accesses to the Memory Window Data Access Register 416 * (0x84) refer to the word of NIC-local memory whose address is given 417 * by this register. When used in this way, the whole of the address 418 * written to this register is significant. 419 * 420 * This register also provides the 32K-aligned base address for a 32K 421 * region of NIC-local memory that the host can directly address in 422 * the upper 32K of the 64K of PCI memory space allocated to the chip. 423 * In this case, the bottom 15 bits of the register are ignored. 424 * 425 * Note that the address written to the MWBAR should lie in the range 426 * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M 427 * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external 428 * memory were present, but it's only supported on the 5700, not the 429 * 5701/5703/5704. 430 */ 431 #define PCI_CONF_BGE_MWBAR 0x7c 432 #define PCI_CONF_BGE_MWDAR 0x84 433 #define MWBAR_GRANULARITY 0x00008000 /* 32k */ 434 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1) 435 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */ 436 437 /* 438 * The PCI express device control register and device status register 439 * which are only applicable on BCM5751 and BCM5721. 440 */ 441 #define PCI_CONF_DEV_CTRL 0xd8 442 #define PCI_CONF_DEV_CTRL_5723 0xd4 443 #define READ_REQ_SIZE_MAX 0x5000 444 #define DEV_CTRL_NO_SNOOP 0x0800 445 #define DEV_CTRL_RELAXED 0x0010 446 447 #define PCI_CONF_DEV_STUS 0xda 448 #define PCI_CONF_DEV_STUS_5723 0xd6 449 #define DEVICE_ERROR_STUS 0xf 450 451 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */ 452 453 /* 454 * Where to find things in NIC-local (on-chip) memory 455 */ 456 #define NIC_MEM_SEND_RINGS 0x0100 457 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring)) 458 #define NIC_MEM_RECV_RINGS 0x0200 459 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring)) 460 #define NIC_MEM_STATISTICS 0x0300 461 #define NIC_MEM_STATISTICS_SIZE 0x0800 462 #define NIC_MEM_STATUS_BLOCK 0x0b00 463 #define NIC_MEM_STATUS_SIZE 0x0050 464 #define NIC_MEM_GENCOMM 0x0b50 465 466 467 /* 468 * Note: the (non-bogus) values below are appropriate for systems 469 * without external memory. They would be different on a 5700 with 470 * external memory. 471 * 472 * Note: The higher send ring addresses and the mini ring shadow 473 * buffer address are dummies - systems without external memory 474 * are limited to 4 send rings and no mini receive ring. 475 */ 476 #define NIC_MEM_SHADOW_DMA 0x2000 477 #define NIC_MEM_SHADOW_SEND_1_4 0x4000 478 #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */ 479 #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */ 480 #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */ 481 #define NIC_MEM_SHADOW_BUFF_STD 0x6000 482 #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000 483 #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */ 484 #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots)) 485 486 /* 487 * Put this in the GENCOMM port to tell the firmware not to run PXE 488 */ 489 #define T3_MAGIC_NUMBER 0x4b657654u 490 491 /* 492 * The remaining registers appear in the low 32K of regular 493 * PCI Memory Address Space 494 */ 495 496 /* 497 * All the state machine control registers below have at least a 498 * <RESET> bit and an <ENABLE> bit as defined below. Some also 499 * have an <ATTN_ENABLE> bit. 500 */ 501 #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004 502 #define STATE_MACHINE_ENABLE_BIT 0x00000002 503 #define STATE_MACHINE_RESET_BIT 0x00000001 504 505 #define TRANSMIT_MAC_MODE_REG 0x045c 506 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00 507 #define SEND_DATA_COMPLETION_MODE_REG 0x1000 508 #define SEND_BD_SELECTOR_MODE_REG 0x1400 509 #define SEND_BD_INITIATOR_MODE_REG 0x1800 510 #define SEND_BD_COMPLETION_MODE_REG 0x1c00 511 512 #define RECEIVE_MAC_MODE_REG 0x0468 513 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000 514 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400 515 #define RCV_DATA_COMPLETION_MODE_REG 0x2800 516 #define RCV_BD_INITIATOR_MODE_REG 0x2c00 517 #define RCV_BD_COMPLETION_MODE_REG 0x3000 518 #define RCV_LIST_SELECTOR_MODE_REG 0x3400 519 520 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800 521 #define HOST_COALESCE_MODE_REG 0x3c00 522 #define MEMORY_ARBITER_MODE_REG 0x4000 523 #define BUFFER_MANAGER_MODE_REG 0x4400 524 #define READ_DMA_MODE_REG 0x4800 525 #define WRITE_DMA_MODE_REG 0x4c00 526 #define DMA_COMPLETION_MODE_REG 0x6400 527 528 /* 529 * Other bits in some of the above state machine control registers 530 */ 531 532 /* 533 * Transmit MAC Mode Register 534 * (TRANSMIT_MAC_MODE_REG, 0x045c) 535 */ 536 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040 537 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020 538 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010 539 540 /* 541 * Receive MAC Mode Register 542 * (RECEIVE_MAC_MODE_REG, 0x0468) 543 */ 544 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400 545 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200 546 #define RECEIVE_MODE_PROMISCUOUS 0x00000100 547 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080 548 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040 549 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020 550 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010 551 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004 552 553 /* 554 * Receive BD Initiator Mode Register 555 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00) 556 * 557 * Each of these bits controls whether ATTN is asserted 558 * on a particular condition 559 */ 560 #define RCV_BD_DISABLED_RING_ATTN 0x00000004 561 562 /* 563 * Receive Data & Receive BD Initiator Mode Register 564 * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400) 565 * 566 * Each of these bits controls whether ATTN is asserted 567 * on a particular condition 568 */ 569 #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010 570 #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008 571 #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004 572 573 #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c 574 575 /* 576 * Host Coalescing Mode Control Register 577 * (HOST_COALESCE_MODE_REG, 0x3c00) 578 */ 579 #define COALESCE_64_BYTE_RINGS 12 580 #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000 581 #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800 582 #define COALESCE_CLR_TICKS_TX 0x00000400 583 #define COALESCE_CLR_TICKS_RX 0x00000200 584 #define COALESCE_32_BYTE_STATUS 0x00000100 585 #define COALESCE_64_BYTE_STATUS 0x00000080 586 #define COALESCE_NOW 0x00000008 587 588 /* 589 * Memory Arbiter Mode Register 590 * (MEMORY_ARBITER_MODE_REG, 0x4000) 591 */ 592 #define MEMORY_ARBITER_ENABLE 0x00000002 593 594 /* 595 * Buffer Manager Mode Register 596 * (BUFFER_MANAGER_MODE_REG, 0x4400) 597 * 598 * In addition to the usual error-attn common to most state machines 599 * this register has a separate bit for attn on running-low-on-mbufs 600 */ 601 #define BUFF_MGR_TEST_MODE 0x00000008 602 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010 603 604 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014 605 606 /* 607 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG, 608 * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00) 609 * 610 * These registers each contain a 2-bit priority field, which controls 611 * the relative priority of that type of DMA (read vs. write vs. MSI), 612 * and a set of bits that control whether ATTN is asserted on each 613 * particular condition 614 */ 615 #define DMA_PRIORITY_MASK 0xc0000000 616 #define DMA_PRIORITY_SHIFT 30 617 #define ALL_DMA_ATTN_BITS 0x000003fc 618 619 /* 620 * BCM5755, 5755M, 5906, 5906M only 621 * 1 - Enable Fix. Device will send out the status block before 622 * the interrupt message 623 * 0 - Disable fix. Device will send out the interrupt message 624 * before the status block 625 */ 626 #define DMA_STATUS_TAG_FIX_CQ12384 0x20000000 627 628 /* 629 * End of state machine control register definitions 630 */ 631 632 633 /* 634 * High priority mailbox registers. 635 * Mailbox Registers (8 bytes each, but high half unused) 636 */ 637 #define INTERRUPT_MBOX_0_REG 0x0200 638 #define INTERRUPT_MBOX_1_REG 0x0208 639 #define INTERRUPT_MBOX_2_REG 0x0210 640 #define INTERRUPT_MBOX_3_REG 0x0218 641 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n)) 642 643 /* 644 * Low priority mailbox registers, for BCM5906, BCM5906M. 645 */ 646 #define INTERRUPT_LP_MBOX_0_REG 0x5800 647 648 /* 649 * Ring Producer/Consumer Index (Mailbox) Registers 650 */ 651 #define RECV_STD_PROD_INDEX_REG 0x0268 652 #define RECV_JUMBO_PROD_INDEX_REG 0x0270 653 #define RECV_MINI_PROD_INDEX_REG 0x0278 654 #define RECV_RING_CONS_INDEX_REGS 0x0280 655 #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300 656 #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380 657 658 #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring)) 659 #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring)) 660 #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring)) 661 662 /* 663 * Ethernet MAC Mode Register 664 */ 665 #define ETHERNET_MAC_MODE_REG 0x0400 666 #define ETHERNET_MODE_ENABLE_FHDE 0x00800000 667 #define ETHERNET_MODE_ENABLE_RDE 0x00400000 668 #define ETHERNET_MODE_ENABLE_TDE 0x00200000 669 #define ETHERNET_MODE_ENABLE_MIP 0x00100000 670 #define ETHERNET_MODE_ENABLE_ACPI 0x00080000 671 #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000 672 #define ETHERNET_MODE_SEND_CFGS 0x00020000 673 #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000 674 #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000 675 #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000 676 #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000 677 #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000 678 #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800 679 #define ETHERNET_MODE_LINK_POLARITY 0x00000400 680 #define ETHERNET_MODE_MAX_DEFER 0x00000200 681 #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100 682 #define ETHERNET_MODE_TAGGED_MODE 0x00000080 683 #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010 684 #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c 685 #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c 686 #define ETHERNET_MODE_PORTMODE_GMII 0x00000008 687 #define ETHERNET_MODE_PORTMODE_MII 0x00000004 688 #define ETHERNET_MODE_PORTMODE_NONE 0x00000000 689 #define ETHERNET_MODE_HALF_DUPLEX 0x00000002 690 #define ETHERNET_MODE_GLOBAL_RESET 0x00000001 691 692 /* 693 * Ethernet MAC Status & Event Registers 694 */ 695 #define ETHERNET_MAC_STATUS_REG 0x0404 696 #define ETHERNET_STATUS_MI_INT 0x00800000 697 #define ETHERNET_STATUS_MI_COMPLETE 0x00400000 698 #define ETHERNET_STATUS_LINK_CHANGED 0x00001000 699 #define ETHERNET_STATUS_PCS_ERROR 0x00000400 700 #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010 701 #define ETHERNET_STATUS_CFG_CHANGED 0x00000008 702 #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004 703 #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002 704 #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001 705 706 #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408 707 #define ETHERNET_EVENT_MI_INT 0x00800000 708 #define ETHERNET_EVENT_LINK_INT 0x00001000 709 #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400 710 711 /* 712 * Ethernet MAC LED Control Register 713 * 714 * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and 715 * the external LED driver circuitry is wired up to assume that this mode 716 * will always be selected. Software must not change it! 717 */ 718 #define ETHERNET_MAC_LED_CONTROL_REG 0x040c 719 #define LED_CONTROL_OVERRIDE_BLINK 0x80000000 720 #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000 721 #define LED_CONTROL_LED_MODE_MASK 0x00001800 722 #define LED_CONTROL_LED_MODE_5700 0x00000000 723 #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */ 724 #define LED_CONTROL_LED_MODE_PHY_2 0x00001000 725 #define LED_CONTROL_LED_MODE_RESERVED 0x00001800 726 #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400 727 #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200 728 #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100 729 #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080 730 #define LED_CONTROL_BLINK_TRAFFIC 0x00000040 731 #define LED_CONTROL_TRAFFIC_LED 0x00000020 732 #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010 733 #define LED_CONTROL_10MBPS_LED 0x00000008 734 #define LED_CONTROL_100MBPS_LED 0x00000004 735 #define LED_CONTROL_1000MBPS_LED 0x00000002 736 #define LED_CONTROL_OVERRIDE_LINK 0x00000001 737 #define LED_CONTROL_DEFAULT 0x02000800 738 739 /* 740 * MAC Address registers 741 * 742 * These four eight-byte registers each hold one unicast address 743 * (six bytes), right justified & zero-filled on the left. 744 * They will normally all be set to the same value, as a station 745 * usually only has one h/w address. The value in register 0 is 746 * used for pause packets; any of the four can be specified for 747 * substitution into other transmitted packets if required. 748 */ 749 #define MAC_ADDRESS_0_REG 0x0410 750 #define MAC_ADDRESS_1_REG 0x0418 751 #define MAC_ADDRESS_2_REG 0x0420 752 #define MAC_ADDRESS_3_REG 0x0428 753 754 #define MAC_ADDRESS_REG(n) (0x0410+8*(n)) 755 #define MAC_ADDRESS_REGS_MAX 4 756 757 /* 758 * More MAC Registers ... 759 */ 760 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438 761 #define MAC_RX_MTU_SIZE_REG 0x043c 762 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */ 763 #define MAC_TX_LENGTHS_REG 0x0464 764 #define MAC_TX_LENGTHS_DEFAULT 0x00002620 765 766 /* 767 * MII access registers 768 */ 769 #define MI_COMMS_REG 0x044c 770 #define MI_COMMS_START 0x20000000 771 #define MI_COMMS_READ_FAILED 0x10000000 772 #define MI_COMMS_COMMAND_MASK 0x0c000000 773 #define MI_COMMS_COMMAND_READ 0x08000000 774 #define MI_COMMS_COMMAND_WRITE 0x04000000 775 #define MI_COMMS_ADDRESS_MASK 0x03e00000 776 #define MI_COMMS_ADDRESS_SHIFT 21 777 #define MI_COMMS_REGISTER_MASK 0x001f0000 778 #define MI_COMMS_REGISTER_SHIFT 16 779 #define MI_COMMS_DATA_MASK 0x0000ffff 780 #define MI_COMMS_DATA_SHIFT 0 781 782 #define MI_STATUS_REG 0x0450 783 #define MI_STATUS_10MBPS 0x00000002 784 #define MI_STATUS_LINK 0x00000001 785 786 #define MI_MODE_REG 0x0454 787 #define MI_MODE_CLOCK_MASK 0x001f0000 788 #define MI_MODE_AUTOPOLL 0x00000010 789 #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002 790 #define MI_MODE_DEFAULT 0x000c0000 791 792 #define MI_AUTOPOLL_STATUS_REG 0x0458 793 #define MI_AUTOPOLL_ERROR 0x00000001 794 795 #define TRANSMIT_MAC_STATUS_REG 0x0460 796 #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020 797 #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010 798 #define TRANSMIT_STATUS_LINK_UP 0x00000008 799 #define TRANSMIT_STATUS_SENT_XON 0x00000004 800 #define TRANSMIT_STATUS_SENT_XOFF 0x00000002 801 #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001 802 803 #define RECEIVE_MAC_STATUS_REG 0x046c 804 #define RECEIVE_STATUS_RCVD_XON 0x00000004 805 #define RECEIVE_STATUS_RCVD_XOFF 0x00000002 806 #define RECEIVE_STATUS_SENT_XOFF 0x00000001 807 808 /* 809 * These four-byte registers constitute a hash table for deciding 810 * whether to accept incoming multicast packets. The bits are 811 * numbered in big-endian fashion, from hash 0 => the MSB of 812 * register 0 to hash 127 => the LSB of the highest-numbered 813 * register. 814 * 815 * NOTE: the 5704 can use a 256-bit table (registers 0-7) if 816 * enabled by setting the appropriate bit in the Rx MAC mode 817 * register. Otherwise, and on all earlier chips, the table 818 * is only 128 bits (registers 0-3). 819 */ 820 #define MAC_HASH_0_REG 0x0470 821 #define MAC_HASH_1_REG 0x0474 822 #define MAC_HASH_2_REG 0x0478 823 #define MAC_HASH_3_REG 0x047c 824 #define MAC_HASH_4_REG 0x???? 825 #define MAC_HASH_5_REG 0x???? 826 #define MAC_HASH_6_REG 0x???? 827 #define MAC_HASH_7_REG 0x???? 828 #define MAC_HASH_REG(n) (0x470+4*(n)) 829 830 /* 831 * Receive Rules Registers: 16 pairs of control+mask/value pairs 832 */ 833 #define RCV_RULES_CONTROL_0_REG 0x0480 834 #define RCV_RULES_MASK_0_REG 0x0484 835 #define RCV_RULES_CONTROL_15_REG 0x04f8 836 #define RCV_RULES_MASK_15_REG 0x04fc 837 #define RCV_RULES_CONFIG_REG 0x0500 838 #define RCV_RULES_CONFIG_DEFAULT 0x00000008 839 840 #define RECV_RULES_NUM_MAX 16 841 #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule)) 842 #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule)) 843 844 #define RECV_RULE_CTL_ENABLE 0x80000000 845 #define RECV_RULE_CTL_AND 0x40000000 846 #define RECV_RULE_CTL_P1 0x20000000 847 #define RECV_RULE_CTL_P2 0x10000000 848 #define RECV_RULE_CTL_P3 0x08000000 849 #define RECV_RULE_CTL_MASK 0x04000000 850 #define RECV_RULE_CTL_DISCARD 0x02000000 851 #define RECV_RULE_CTL_MAP 0x01000000 852 #define RECV_RULE_CTL_RESV_BITS 0x00fc0000 853 #define RECV_RULE_CTL_OP 0x00030000 854 #define RECV_RULE_CTL_OP_EQ 0x00000000 855 #define RECV_RULE_CTL_OP_NEQ 0x00010000 856 #define RECV_RULE_CTL_OP_GREAT 0x00020000 857 #define RECV_RULE_CTL_OP_LESS 0x00030000 858 #define RECV_RULE_CTL_HEADER 0x0000e000 859 #define RECV_RULE_CTL_HEADER_FRAME 0x00000000 860 #define RECV_RULE_CTL_HEADER_IP 0x00002000 861 #define RECV_RULE_CTL_HEADER_TCP 0x00004000 862 #define RECV_RULE_CTL_HEADER_UDP 0x00006000 863 #define RECV_RULE_CTL_HEADER_DATA 0x00008000 864 #define RECV_RULE_CTL_CLASS_BITS 0x00001f00 865 #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \ 866 RECV_RULE_CTL_CLASS_BITS) 867 #define RECV_RULE_CTL_OFFSET 0x000000ff 868 869 /* 870 * Receive Rules definition 871 */ 872 #define ETHERHEADER_DEST_OFFSET 0x00 873 #define IPHEADER_PROTO_OFFSET 0x08 874 #define IPHEADER_SIP_OFFSET 0x0c 875 #define IPHEADER_DIP_OFFSET 0x10 876 #define TCPHEADER_SPORT_OFFSET 0x00 877 #define TCPHEADER_DPORT_OFFSET 0x02 878 #define UDPHEADER_SPORT_OFFSET 0x00 879 #define UDPHEADER_DPORT_OFFSET 0x02 880 881 #define RULE_MATCH(ring) (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \ 882 RECV_RULE_CTL_CLASS((ring))) 883 884 #define RULE_MATCH_MASK(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_MASK) 885 886 #define RULE_DEST_MAC_1(ring) (RULE_MATCH(ring) | \ 887 RECV_RULE_CTL_HEADER_FRAME | \ 888 ETHERHEADER_DEST_OFFSET) 889 890 #define RULE_DEST_MAC_2(ring) (RULE_MATCH_MASK(ring) | \ 891 RECV_RULE_CTL_HEADER_FRAME | \ 892 ETHERHEADER_DEST_OFFSET + 4) 893 894 #define RULE_LOCAL_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \ 895 IPHEADER_DIP_OFFSET) 896 897 #define RULE_REMOTE_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \ 898 IPHEADER_SIP_OFFSET) 899 900 #define RULE_IP_PROTO(ring) (RULE_MATCH_MASK(ring) | \ 901 RECV_RULE_CTL_HEADER_IP | \ 902 IPHEADER_PROTO_OFFSET) 903 904 #define RULE_TCP_SPORT(ring) (RULE_MATCH_MASK(ring) | \ 905 RECV_RULE_CTL_HEADER_TCP | \ 906 TCPHEADER_SPORT_OFFSET) 907 908 #define RULE_TCP_DPORT(ring) (RULE_MATCH_MASK(ring) | \ 909 RECV_RULE_CTL_HEADER_TCP | \ 910 TCPHEADER_DPORT_OFFSET) 911 912 #define RULE_UDP_SPORT(ring) (RULE_MATCH_MASK(ring) | \ 913 RECV_RULE_CTL_HEADER_UDP | \ 914 UDPHEADER_SPORT_OFFSET) 915 916 #define RULE_UDP_DPORT(ring) (RULE_MATCH_MASK(ring) | \ 917 RECV_RULE_CTL_HEADER_UDP | \ 918 UDPHEADER_DPORT_OFFSET) 919 920 /* 921 * 1000BaseX low-level access registers 922 */ 923 #define MAC_GIGABIT_PCS_TEST_REG 0x0440 924 #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000 925 #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff 926 #define TX_1000BASEX_AUTONEG_REG 0x0444 927 #define RX_1000BASEX_AUTONEG_REG 0x0448 928 929 /* 930 * Autoneg code bits for the 1000BASE-X AUTONEG registers 931 */ 932 #define AUTONEG_CODE_PAUSE 0x00008000 933 #define AUTONEG_CODE_HALF_DUPLEX 0x00004000 934 #define AUTONEG_CODE_FULL_DUPLEX 0x00002000 935 #define AUTONEG_CODE_NEXT_PAGE 0x00000080 936 #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040 937 #define AUTONEG_CODE_FAULT_MASK 0x00000030 938 #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030 939 #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020 940 #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010 941 #define AUTONEG_CODE_ASYM_PAUSE 0x00000001 942 943 /* 944 * SerDes Registers (5703S/5704S only) 945 */ 946 #define SERDES_CONTROL_REG 0x0590 947 #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000 948 #define SERDES_CONTROL_COMMA_DETECT 0x00010000 949 #define SERDES_CONTROL_TX_DISABLE 0x00004000 950 #define SERDES_STATUS_REG 0x0594 951 #define SERDES_STATUS_COMMA_DETECTED 0x00000100 952 #define SERDES_STATUS_RXSTAT 0x000000ff 953 954 /* 955 * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only) 956 */ 957 #define STAT_IFHCOUT_OCTETS_REG 0x0800 958 #define STAT_ETHER_COLLIS_REG 0x0808 959 #define STAT_OUTXON_SENT_REG 0x080c 960 #define STAT_OUTXOFF_SENT_REG 0x0810 961 #define STAT_DOT3_INTMACTX_ERR_REG 0x0818 962 #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c 963 #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820 964 #define STAT_DOT3_DEFERED_TX_REG 0x0824 965 #define STAT_DOT3_EXCE_COLLI_REG 0x082c 966 #define STAT_DOT3_LATE_COLLI_REG 0x0830 967 #define STAT_IFHCOUT_UPKGS_REG 0x086c 968 #define STAT_IFHCOUT_MPKGS_REG 0x0870 969 #define STAT_IFHCOUT_BPKGS_REG 0x0874 970 971 #define STAT_IFHCIN_OCTETS_REG 0x0880 972 #define STAT_ETHER_FRAGMENT_REG 0x0888 973 #define STAT_IFHCIN_UPKGS_REG 0x088c 974 #define STAT_IFHCIN_MPKGS_REG 0x0890 975 #define STAT_IFHCIN_BPKGS_REG 0x0894 976 977 #define STAT_DOT3_FCS_ERR_REG 0x0898 978 #define STAT_DOT3_ALIGN_ERR_REG 0x089c 979 #define STAT_XON_PAUSE_RX_REG 0x08a0 980 #define STAT_XOFF_PAUSE_RX_REG 0x08a4 981 #define STAT_MAC_CTRL_RX_REG 0x08a8 982 #define STAT_XOFF_STATE_ENTER_REG 0x08ac 983 #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0 984 #define STAT_ETHER_JABBERS_REG 0x08b4 985 #define STAT_ETHER_UNDERSIZE_REG 0x08b8 986 #define SIZE_OF_STATISTIC_REG 0x1B 987 /* 988 * Send Data Initiator Registers 989 */ 990 #define SEND_INIT_STATS_CONTROL_REG 0x0c08 991 #define SEND_INIT_STATS_ZERO 0x00000010 992 #define SEND_INIT_STATS_FLUSH 0x00000008 993 #define SEND_INIT_STATS_CLEAR 0x00000004 994 #define SEND_INIT_STATS_FASTER 0x00000002 995 #define SEND_INIT_STATS_ENABLE 0x00000001 996 997 #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c 998 999 /* 1000 * Send Buffer Descriptor Selector Control Registers 1001 */ 1002 #define SEND_BD_SELECTOR_STATUS_REG 0x1404 1003 #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408 1004 #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n)) 1005 1006 /* 1007 * Receive List Placement Registers 1008 */ 1009 #define RCV_LP_CONFIG_REG 0x2010 1010 #define RCV_LP_CONFIG_DEFAULT 0x00000009 1011 #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1) 1012 1013 #define RCV_LP_STATS_CONTROL_REG 0x2014 1014 #define RCV_LP_STATS_ZERO 0x00000010 1015 #define RCV_LP_STATS_FLUSH 0x00000008 1016 #define RCV_LP_STATS_CLEAR 0x00000004 1017 #define RCV_LP_STATS_FASTER 0x00000002 1018 #define RCV_LP_STATS_ENABLE 0x00000001 1019 1020 #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018 1021 #define RCV_LP_STATS_DISABLE_MACTQ 0x040000 1022 1023 /* 1024 * Receive Data & BD Initiator Registers 1025 */ 1026 #define RCV_INITIATOR_STATUS_REG 0x2404 1027 1028 /* 1029 * Receive Buffer Descriptor Ring Control Block Registers 1030 * NB: sixteen bytes (128 bits) each 1031 */ 1032 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440 1033 #define STD_RCV_BD_RING_RCB_REG 0x2450 1034 #define MINI_RCV_BD_RING_RCB_REG 0x2460 1035 1036 /* 1037 * Receive Buffer Descriptor Ring Replenish Threshold Registers 1038 */ 1039 #define MINI_RCV_BD_REPLENISH_REG 0x2c14 1040 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */ 1041 #define STD_RCV_BD_REPLENISH_REG 0x2c18 1042 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */ 1043 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c 1044 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */ 1045 1046 /* 1047 * Host Coalescing Engine Control Registers 1048 */ 1049 #define RCV_COALESCE_TICKS_REG 0x3c08 1050 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 1051 #define SEND_COALESCE_TICKS_REG 0x3c0c 1052 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 1053 #define RCV_COALESCE_MAX_BD_REG 0x3c10 1054 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1055 #define SEND_COALESCE_MAX_BD_REG 0x3c14 1056 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1057 #define RCV_COALESCE_INT_TICKS_REG 0x3c18 1058 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1059 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c 1060 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1061 #define RCV_COALESCE_INT_BD_REG 0x3c20 1062 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1063 #define SEND_COALESCE_INT_BD_REG 0x3c24 1064 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1065 #define STATISTICS_TICKS_REG 0x3c28 1066 #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */ 1067 #define STATISTICS_HOST_ADDR_REG 0x3c30 1068 #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38 1069 #define STATISTICS_BASE_ADDR_REG 0x3c40 1070 #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44 1071 #define FLOW_ATTN_REG 0x3c48 1072 1073 #define NIC_JUMBO_RECV_INDEX_REG 0x3c50 1074 #define NIC_STD_RECV_INDEX_REG 0x3c54 1075 #define NIC_MINI_RECV_INDEX_REG 0x3c58 1076 #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n)) 1077 #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n)) 1078 1079 /* 1080 * Mbuf Pool Initialisation & Watermark Registers 1081 * 1082 * There are some conflicts in the PRM; compare the recommendations 1083 * on pp. 115, 236, and 339. The values here were recommended by 1084 * dkim@broadcom.com (and the PRM should be corrected soon ;-) 1085 */ 1086 #define BUFFER_MANAGER_STATUS_REG 0x4404 1087 #define MBUF_POOL_BASE_REG 0x4408 1088 #define MBUF_POOL_BASE_DEFAULT 0x00008000 1089 #define MBUF_POOL_BASE_5721 0x00010000 1090 #define MBUF_POOL_BASE_5704 0x00010000 1091 #define MBUF_POOL_BASE_5705 0x00010000 1092 #define MBUF_POOL_LENGTH_REG 0x440c 1093 #define MBUF_POOL_LENGTH_DEFAULT 0x00018000 1094 #define MBUF_POOL_LENGTH_5704 0x00010000 1095 #define MBUF_POOL_LENGTH_5705 0x00008000 1096 #define MBUF_POOL_LENGTH_5721 0x00008000 1097 #define RDMA_MBUF_LOWAT_REG 0x4410 1098 #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050 1099 #define RDMA_MBUF_LOWAT_5705 0x00000000 1100 #define RDMA_MBUF_LOWAT_5906 0x00000000 1101 #define RDMA_MBUF_LOWAT_JUMBO 0x00000130 1102 #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000 1103 #define MAC_RX_MBUF_LOWAT_REG 0x4414 1104 #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020 1105 #define MAC_RX_MBUF_LOWAT_5705 0x00000010 1106 #define MAC_RX_MBUF_LOWAT_5906 0x00000004 1107 #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098 1108 #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b 1109 #define MBUF_HIWAT_REG 0x4418 1110 #define MBUF_HIWAT_DEFAULT 0x00000060 1111 #define MBUF_HIWAT_5705 0x00000060 1112 #define MBUF_HIWAT_5906 0x00000010 1113 #define MBUF_HIWAT_JUMBO 0x0000017c 1114 #define MBUF_HIWAT_5714_JUMBO 0x00000096 1115 1116 /* 1117 * DMA Descriptor Pool Initialisation & Watermark Registers 1118 */ 1119 #define DMAD_POOL_BASE_REG 0x442c 1120 #define DMAD_POOL_BASE_DEFAULT 0x00002000 1121 #define DMAD_POOL_LENGTH_REG 0x4430 1122 #define DMAD_POOL_LENGTH_DEFAULT 0x00002000 1123 #define DMAD_POOL_LOWAT_REG 0x4434 1124 #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */ 1125 #define DMAD_POOL_HIWAT_REG 0x4438 1126 #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */ 1127 1128 /* 1129 * More threshold/watermark registers ... 1130 */ 1131 #define RECV_FLOW_THRESHOLD_REG 0x4458 1132 #define LOWAT_MAX_RECV_FRAMES_REG 0x0504 1133 #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002 1134 1135 /* 1136 * Read/Write DMA Status Registers 1137 */ 1138 #define READ_DMA_STATUS_REG 0x4804 1139 #define WRITE_DMA_STATUS_REG 0x4c04 1140 1141 /* 1142 * RX/TX RISC Registers 1143 */ 1144 #define RX_RISC_MODE_REG 0x5000 1145 #define RX_RISC_STATE_REG 0x5004 1146 #define RX_RISC_PC_REG 0x501c 1147 #define TX_RISC_MODE_REG 0x5400 1148 #define TX_RISC_STATE_REG 0x5404 1149 #define TX_RISC_PC_REG 0x541c 1150 1151 /* 1152 * V? RISC Registerss 1153 */ 1154 #define VCPU_STATUS_REG 0x5100 1155 #define VCPU_INIT_DONE 0x04000000 1156 #define VCPU_DRV_RESET 0x08000000 1157 1158 #define VCPU_EXT_CTL 0x6890 1159 #define VCPU_EXT_CTL_HALF 0x00400000 1160 1161 #define FTQ_RESET_REG 0x5c00 1162 1163 #define MSI_MODE_REG 0x6000 1164 #define MSI_PRI_HIGHEST 0xc0000000 1165 #define MSI_MSI_ENABLE 0x00000002 1166 #define MSI_ERROR_ATTENTION 0x0000001c 1167 1168 #define MSI_STATUS_REG 0x6004 1169 1170 #define MODE_CONTROL_REG 0x6800 1171 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000 1172 #define MODE_4X_NIC_SEND_RINGS 0x20000000 1173 #define MODE_INT_ON_FLOW_ATTN 0x10000000 1174 #define MODE_INT_ON_DMA_ATTN 0x08000000 1175 #define MODE_INT_ON_MAC_ATTN 0x04000000 1176 #define MODE_INT_ON_RXRISC_ATTN 0x02000000 1177 #define MODE_INT_ON_TXRISC_ATTN 0x01000000 1178 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000 1179 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000 1180 #define MODE_HOST_SEND_BDS 0x00020000 1181 #define MODE_HOST_STACK_UP 0x00010000 1182 #define MODE_FORCE_32_BIT_PCI 0x00008000 1183 #define MODE_NO_INT_ON_RECV 0x00004000 1184 #define MODE_NO_INT_ON_SEND 0x00002000 1185 #define MODE_ALLOW_BAD_FRAMES 0x00000800 1186 #define MODE_NO_CRC 0x00000400 1187 #define MODE_NO_FRAME_CRACKING 0x00000200 1188 #define MODE_WORD_SWAP_FRAME 0x00000020 1189 #define MODE_BYTE_SWAP_FRAME 0x00000010 1190 #define MODE_WORD_SWAP_NONFRAME 0x00000004 1191 #define MODE_BYTE_SWAP_NONFRAME 0x00000002 1192 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001 1193 1194 /* 1195 * Miscellaneous Configuration Register 1196 * 1197 * This contains various bits relating to power control (which differ 1198 * among different members of the chip family), but the important bits 1199 * for our purposes are the RESET bit and the Timer Prescaler field. 1200 * 1201 * The RESET bit in this register serves to reset the whole chip, even 1202 * including the PCI interface(!) Once it's set, the chip will not 1203 * respond to ANY accesses -- not even CONFIG space -- until the reset 1204 * completes internally. According to the PRM, this should take less 1205 * than 100us. Any access during this period will get a bus error. 1206 * 1207 * The Timer Prescaler field must be programmed so that the timer period 1208 * is as near as possible to 1us. The value in this field should be 1209 * the Core Clock frequency in MHz minus 1. From my reading of the PRM, 1210 * the Core Clock should always be 66MHz (independently of the bus speed, 1211 * at least for PCI rather than PCI-X), so this register must be set to 1212 * the value 0x82 ((66-1) << 1). 1213 */ 1214 #define CORE_CLOCK_MHZ 66 1215 #define MISC_CONFIG_REG 0x6804 1216 #define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000 1217 #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000 1218 #define MISC_CONFIG_POWERDOWN 0x00100000 1219 #define MISC_CONFIG_POWER_STATE 0x00060000 1220 #define MISC_CONFIG_PRESCALE_MASK 0x000000fe 1221 #define MISC_CONFIG_RESET_BIT 0x00000001 1222 #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1) 1223 #define MISC_CONFIG_EPHY_IDDQ 0x00200000 1224 1225 /* 1226 * Miscellaneous Local Control Register (MLCR) 1227 */ 1228 #define MISC_LOCAL_CONTROL_REG 0x6808 1229 #define MLCR_PCI_CTRL_SELECT 0x10000000 1230 #define MLCR_LEGACY_PCI_MODE 0x08000000 1231 #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000 1232 #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000 1233 #define MLCR_SSRAM_TYPE 0x00400000 1234 #define MLCR_BANK_SELECT 0x00200000 1235 #define MLCR_SRAM_SIZE_MASK 0x001c0000 1236 #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000 1237 1238 #define MLCR_MISC_PINS_OUTPUT_2 0x00010000 1239 #define MLCR_MISC_PINS_OUTPUT_1 0x00008000 1240 #define MLCR_MISC_PINS_OUTPUT_0 0x00004000 1241 #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000 1242 #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000 1243 #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800 1244 #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */ 1245 #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */ 1246 #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */ 1247 1248 #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */ 1249 #define MLCR_SET_INT 0x00000004 /* W/O */ 1250 #define MLCR_CLR_INT 0x00000002 /* W/O */ 1251 #define MLCR_INTA_STATE 0x00000001 /* R/O */ 1252 1253 /* 1254 * This value defines all GPIO bits as INPUTS, but sets their default 1255 * values as outputs to HIGH, on the assumption that external circuits 1256 * (if any) will probably be active-LOW with passive pullups. 1257 * 1258 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in 1259 * just this fashion. It has to be set as an OUTPUT and driven LOW to 1260 * enable writing. Otherwise, the SEEPROM is protected. 1261 */ 1262 #define MLCR_DEFAULT 0x0101c000 1263 #define MLCR_DEFAULT_5714 0x1901c000 1264 1265 /* 1266 * Serial EEPROM Data/Address Registers (auto-access mode) 1267 */ 1268 #define SERIAL_EEPROM_DATA_REG 0x683c 1269 #define SERIAL_EEPROM_ADDRESS_REG 0x6838 1270 #define SEEPROM_ACCESS_READ 0x80000000 1271 #define SEEPROM_ACCESS_WRITE 0x00000000 1272 #define SEEPROM_ACCESS_COMPLETE 0x40000000 1273 #define SEEPROM_ACCESS_RESET 0x20000000 1274 #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000 1275 #define SEEPROM_ACCESS_START 0x02000000 1276 #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000 1277 #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc 1278 1279 #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */ 1280 #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */ 1281 #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */ 1282 1283 #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */ 1284 #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */ 1285 1286 /* 1287 * "Linearised" address mask, treating multiple devices as consecutive 1288 */ 1289 #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */ 1290 1291 /* 1292 * Non-Volatile Memory Interface Registers 1293 * Note: on chips that support the flash interface (5702+), flash is the 1294 * default and the legacy seeprom interface must be explicitly enabled 1295 * if required. On older chips (5700/01), SEEPROM is the default (and 1296 * only) non-volatile memory available, and these registers don't exist! 1297 */ 1298 #define NVM_FLASH_CMD_REG 0x7000 1299 #define NVM_FLASH_CMD_LAST 0x00000100 1300 #define NVM_FLASH_CMD_FIRST 0x00000080 1301 #define NVM_FLASH_CMD_RD 0x00000000 1302 #define NVM_FLASH_CMD_WR 0x00000020 1303 #define NVM_FLASH_CMD_DOIT 0x00000010 1304 #define NVM_FLASH_CMD_DONE 0x00000008 1305 1306 #define NVM_FLASH_WRITE_REG 0x7008 1307 #define NVM_FLASH_READ_REG 0x7010 1308 1309 #define NVM_FLASH_ADDR_REG 0x700c 1310 #define NVM_FLASH_ADDR_MASK 0x00fffffc 1311 1312 #define NVM_CONFIG1_REG 0x7014 1313 #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000 1314 #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800 1315 #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780 1316 #define NVM_CFG1_BUFFERED_MODE 0x00000002 1317 #define NVM_CFG1_FLASH_MODE 0x00000001 1318 1319 #define NVM_SW_ARBITRATION_REG 0x7020 1320 #define NVM_READ_REQ3 0X00008000 1321 #define NVM_READ_REQ2 0X00004000 1322 #define NVM_READ_REQ1 0X00002000 1323 #define NVM_READ_REQ0 0X00001000 1324 #define NVM_WON_REQ3 0X00000800 1325 #define NVM_WON_REQ2 0X00000400 1326 #define NVM_WON_REQ1 0X00000200 1327 #define NVM_WON_REQ0 0X00000100 1328 #define NVM_RESET_REQ3 0X00000080 1329 #define NVM_RESET_REQ2 0X00000040 1330 #define NVM_RESET_REQ1 0X00000020 1331 #define NVM_RESET_REQ0 0X00000010 1332 #define NVM_SET_REQ3 0X00000008 1333 #define NVM_SET_REQ2 0X00000004 1334 #define NVM_SET_REQ1 0X00000002 1335 #define NVM_SET_REQ0 0X00000001 1336 1337 /* 1338 * NVM access register 1339 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714 1340 * and BCM5715 only. 1341 */ 1342 #define NVM_ACCESS_REG 0X7024 1343 #define NVM_WRITE_ENABLE 0X00000002 1344 #define NVM_ACCESS_ENABLE 0X00000001 1345 1346 /* 1347 * TLP Control Register 1348 * Applicable to BCM5721 and BCM5751 only 1349 */ 1350 #define TLP_CONTROL_REG 0x7c00 1351 #define TLP_DATA_FIFO_PROTECT 0x02000000 1352 1353 /* 1354 * PHY Test Control Register 1355 * Applicable to BCM5721 and BCM5751 only 1356 */ 1357 #define PHY_TEST_CTRL_REG 0x7e2c 1358 #define PHY_PCIE_SCRAM_MODE 0x20 1359 #define PHY_PCIE_LTASS_MODE 0x40 1360 1361 /* 1362 * The internal firmware expects a certain layout of the non-volatile 1363 * memory (if fitted), and will check for it during startup, and use the 1364 * contents to initialise various internal parameters if it looks good. 1365 * 1366 * The offsets and field definitions below refer to where to find some 1367 * important values, and how to interpret them ... 1368 */ 1369 #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */ 1370 #define NVMEM_DATA_MAC_ADDRESS_5906 0x0010 /* 8 bytes */ 1371 1372 /* 1373 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 1374 */ 1375 1376 #define MII_AN_LPNXTPG 8 1377 #define MII_1000BASE_T_CONTROL 9 1378 #define MII_1000BASE_T_STATUS 10 1379 #define MII_IEEE_EXT_STATUS 15 1380 1381 /* 1382 * New bits in the MII_CONTROL register 1383 */ 1384 #define MII_CONTROL_1000MB 0x0040 1385 1386 /* 1387 * New bits in the MII_AN_ADVERT register 1388 */ 1389 #define MII_ABILITY_ASYM_PAUSE 0x0800 1390 #define MII_ABILITY_PAUSE 0x0400 1391 1392 /* 1393 * Values for the <selector> field of the MII_AN_ADVERT register 1394 */ 1395 #define MII_AN_SELECTOR_8023 0x0001 1396 1397 /* 1398 * Bits in the MII_1000BASE_T_CONTROL register 1399 * 1400 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 1401 * (otherwise, roles are automatically negotiated). When this bit is set, 1402 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 1403 */ 1404 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 1405 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 1406 #define MII_1000BT_CTL_ADV_FDX 0x0200 1407 #define MII_1000BT_CTL_ADV_HDX 0x0100 1408 1409 /* 1410 * Bits in the MII_1000BASE_T_STATUS register 1411 */ 1412 #define MII_1000BT_STAT_MASTER_FAULT 0x8000 1413 #define MII_1000BT_STAT_MASTER_MODE 0x4000 /* shows role selected */ 1414 #define MII_1000BT_STAT_LCL_RCV_OK 0x2000 1415 #define MII_1000BT_STAT_RMT_RCV_OK 0x1000 1416 #define MII_1000BT_STAT_LP_FDX_CAP 0x0800 1417 #define MII_1000BT_STAT_LP_HDX_CAP 0x0400 1418 1419 /* 1420 * Vendor-specific MII registers 1421 */ 1422 #define MII_EXT_CONTROL MII_VENDOR(0) 1423 #define MII_EXT_STATUS MII_VENDOR(1) 1424 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 1425 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 1426 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 1427 #define MII_AUX_CONTROL MII_VENDOR(8) 1428 #define MII_AUX_STATUS MII_VENDOR(9) 1429 #define MII_INTR_STATUS MII_VENDOR(10) 1430 #define MII_INTR_MASK MII_VENDOR(11) 1431 #define MII_HCD_STATUS MII_VENDOR(13) 1432 1433 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 1434 1435 /* 1436 * Bits in the MII_EXT_CONTROL register 1437 */ 1438 #define MII_EXT_CTRL_INTERFACE_TBI 0x8000 1439 #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000 1440 #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000 1441 #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000 1442 #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800 1443 #define MII_EXT_CTRL_BYPASS_4B5B 0x0400 1444 #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200 1445 #define MII_EXT_CTRL_BYPASS_MLT3 0x0100 1446 #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080 1447 #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040 1448 #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020 1449 #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010 1450 #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008 1451 #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004 1452 #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002 1453 #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001 1454 1455 /* 1456 * Bits in the MII_EXT_STATUS register 1457 */ 1458 #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000 1459 #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000 1460 #define MII_EXT_STAT_MDIX_STATE 0x2000 1461 #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000 1462 #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800 1463 #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400 1464 #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200 1465 #define MII_EXT_STAT_LINK_STATUS 0x0100 1466 #define MII_EXT_STAT_CRC_ERROR 0x0080 1467 #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040 1468 #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020 1469 #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010 1470 #define MII_EXT_STAT_RECEIVE_ERROR 0x0008 1471 #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004 1472 #define MII_EXT_STAT_LOCK_ERROR 0x0002 1473 #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001 1474 1475 /* 1476 * The AUX CONTROL register is seriously weird! 1477 * 1478 * It hides (up to) eight 'shadow' registers. When writing, which one 1479 * of them is written is determined by the low-order bits of the data 1480 * written(!), but when reading, which one is read is determined by the 1481 * value previously written to (part of) one of the shadow registers!!! 1482 */ 1483 1484 /* 1485 * Shadow register numbers 1486 */ 1487 #define MII_AUX_CTRL_NORMAL 0 1488 #define MII_AUX_CTRL_10BASE_T 1 1489 #define MII_AUX_CTRL_POWER 2 1490 #define MII_AUX_CTRL_TEST_1 4 1491 #define MII_AUX_CTRL_MISC 7 1492 1493 /* 1494 * Selected bits in some of the shadow registers ... 1495 */ 1496 #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000 1497 #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000 1498 #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000 1499 #define MII_AUX_CTRL_NORM_TX_MODE 0x0400 1500 #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008 1501 1502 #define MII_AUX_CTRL_TEST_TX_HALF 0x0008 1503 1504 #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000 1505 #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010 1506 1507 /* 1508 * Write this value to the AUX control register 1509 * to select which shadow register will be read 1510 */ 1511 #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC) 1512 1513 /* 1514 * Bits in the MII_AUX_STATUS register 1515 */ 1516 #define MII_AUX_STATUS_MODE_MASK 0x0700 1517 #define MII_AUX_STATUS_MODE_1000_F 0x0700 1518 #define MII_AUX_STATUS_MODE_1000_H 0x0600 1519 #define MII_AUX_STATUS_MODE_100_F 0x0500 1520 #define MII_AUX_STATUS_MODE_100_4 0x0400 1521 #define MII_AUX_STATUS_MODE_100_H 0x0300 1522 #define MII_AUX_STATUS_MODE_10_F 0x0200 1523 #define MII_AUX_STATUS_MODE_10_H 0x0100 1524 #define MII_AUX_STATUS_MODE_NONE 0x0000 1525 #define MII_AUX_STATUS_MODE_SHIFT 8 1526 1527 #define MII_AUX_STATUS_PAR_FAULT 0x0080 1528 #define MII_AUX_STATUS_REM_FAULT 0x0040 1529 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 1530 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 1531 1532 #define MII_AUX_STATUS_LINKUP 0x0004 1533 #define MII_AUX_STATUS_RX_PAUSE 0x0002 1534 #define MII_AUX_STATUS_TX_PAUSE 0x0001 1535 1536 #define MII_AUX_STATUS_SPEED_IND_5906 0x0008 1537 #define MII_AUX_STATUS_NEG_ENABLED_5906 0x0002 1538 #define MII_AUX_STATUS_DUPLEX_IND_5906 0x0001 1539 1540 /* 1541 * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers 1542 */ 1543 #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020 1544 #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010 1545 #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008 1546 #define MII_INTR_LINK_SPEED_CHANGE 0x0004 1547 #define MII_INTR_LINK_STATUS_CHANGE 0x0002 1548 1549 1550 /* 1551 * Third section: 1552 * Hardware-defined data structures 1553 * 1554 * Note that the chip is naturally BIG-endian, so, for a big-endian 1555 * host, the structures defined below match those described in the PRM. 1556 * For little-endian hosts, some structures have to be swapped around. 1557 */ 1558 1559 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 1560 #error Host endianness not defined 1561 #endif 1562 1563 /* 1564 * Architectural constants: absolute maximum numbers of each type of ring 1565 */ 1566 #ifdef BGE_EXT_MEM 1567 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */ 1568 #else 1569 #define BGE_SEND_RINGS_MAX 4 1570 #endif 1571 #define BGE_SEND_RINGS_MAX_5705 1 1572 #define BGE_RECV_RINGS_MAX 16 1573 #define BGE_RECV_RINGS_MAX_5705 1 1574 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */ 1575 /* only with ext mem) */ 1576 1577 #define BGE_SEND_SLOTS_MAX 512 1578 #define BGE_STD_SLOTS_MAX 512 1579 #define BGE_JUMBO_SLOTS_MAX 256 1580 #define BGE_MINI_SLOTS_MAX 1024 1581 #define BGE_RECV_SLOTS_MAX 2048 1582 #define BGE_RECV_SLOTS_5705 512 1583 #define BGE_RECV_SLOTS_5782 512 1584 #define BGE_RECV_SLOTS_5721 512 1585 1586 /* 1587 * Hardware-defined Ring Control Block 1588 */ 1589 typedef struct { 1590 uint64_t host_ring_addr; 1591 #ifdef _BIG_ENDIAN 1592 uint16_t max_len; 1593 uint16_t flags; 1594 uint32_t nic_ring_addr; 1595 #else 1596 uint32_t nic_ring_addr; 1597 uint16_t flags; 1598 uint16_t max_len; 1599 #endif /* _BIG_ENDIAN */ 1600 } bge_rcb_t; 1601 1602 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001 1603 #define RCB_FLAG_RING_DISABLED 0x0002 1604 1605 /* 1606 * Hardware-defined Send Buffer Descriptor 1607 */ 1608 typedef struct { 1609 uint64_t host_buf_addr; 1610 #ifdef _BIG_ENDIAN 1611 uint16_t len; 1612 uint16_t flags; 1613 uint16_t reserved; 1614 uint16_t vlan_tci; 1615 #else 1616 uint16_t vlan_tci; 1617 uint16_t reserved; 1618 uint16_t flags; 1619 uint16_t len; 1620 #endif /* _BIG_ENDIAN */ 1621 } bge_sbd_t; 1622 1623 #define SBD_FLAG_TCP_UDP_CKSUM 0x0001 1624 #define SBD_FLAG_IP_CKSUM 0x0002 1625 #define SBD_FLAG_PACKET_END 0x0004 1626 #define SBD_FLAG_IP_FRAG 0x0008 1627 #define SBD_FLAG_IP_FRAG_END 0x0010 1628 1629 #define SBD_FLAG_VLAN_TAG 0x0040 1630 #define SBD_FLAG_COAL_NOW 0x0080 1631 #define SBD_FLAG_CPU_PRE_DMA 0x0100 1632 #define SBD_FLAG_CPU_POST_DMA 0x0200 1633 1634 #define SBD_FLAG_INSERT_SRC_ADDR 0x1000 1635 #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000 1636 #define SBD_FLAG_DONT_GEN_CRC 0x8000 1637 1638 /* 1639 * Hardware-defined Receive Buffer Descriptor 1640 */ 1641 typedef struct { 1642 uint64_t host_buf_addr; 1643 #ifdef _BIG_ENDIAN 1644 uint16_t index; 1645 uint16_t len; 1646 uint16_t type; 1647 uint16_t flags; 1648 uint16_t ip_cksum; 1649 uint16_t tcp_udp_cksum; 1650 uint16_t error_flag; 1651 uint16_t vlan_tci; 1652 uint32_t reserved; 1653 uint32_t opaque; 1654 #else 1655 uint16_t flags; 1656 uint16_t type; 1657 uint16_t len; 1658 uint16_t index; 1659 uint16_t vlan_tci; 1660 uint16_t error_flag; 1661 uint16_t tcp_udp_cksum; 1662 uint16_t ip_cksum; 1663 uint32_t opaque; 1664 uint32_t reserved; 1665 #endif /* _BIG_ENDIAN */ 1666 } bge_rbd_t; 1667 1668 #define RBD_FLAG_STD_RING 0x0000 1669 #define RBD_FLAG_PACKET_END 0x0004 1670 1671 #define RBD_FLAG_JUMBO_RING 0x0020 1672 #define RBD_FLAG_VLAN_TAG 0x0040 1673 1674 #define RBD_FLAG_FRAME_HAS_ERROR 0x0400 1675 #define RBD_FLAG_MINI_RING 0x0800 1676 #define RBD_FLAG_IP_CHECKSUM 0x1000 1677 #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000 1678 #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000 1679 1680 #define RBD_FLAG_DEFAULT 0x0000 1681 1682 #define RBD_ERROR_BAD_CRC 0x00010000 1683 #define RBD_ERROR_COLL_DETECT 0x00020000 1684 #define RBD_ERROR_LINK_LOST 0x00040000 1685 #define RBD_ERROR_PHY_DECODE_ERR 0x00080000 1686 #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000 1687 #define RBD_ERROR_MAC_ABORT 0x00200000 1688 #define RBD_ERROR_LEN_LESS_64 0x00400000 1689 #define RBD_ERROR_TRUNC_NO_RES 0x00800000 1690 #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000 1691 1692 /* 1693 * Hardware-defined Status Block,Size of status block 1694 * is actually 0x50 bytes.Use 0x80 bytes for cache line 1695 * alignment.For BCM5705/5788/5721/5751/5752/5714 1696 * and 5715,there is only 1 recv and send ring index,but 1697 * driver defined 16 indexs here,please pay attention only 1698 * one ring is enabled in these chipsets. 1699 */ 1700 typedef struct { 1701 uint64_t flags_n_tag; 1702 uint16_t buff_cons_index[4]; 1703 struct { 1704 #ifdef _BIG_ENDIAN 1705 uint16_t send_cons_index; 1706 uint16_t recv_prod_index; 1707 #else 1708 uint16_t recv_prod_index; 1709 uint16_t send_cons_index; 1710 #endif /* _BIG_ENDIAN */ 1711 } index[16]; 1712 } bge_status_t; 1713 1714 /* 1715 * Hardware-defined Receive BD Rule 1716 */ 1717 typedef struct { 1718 uint32_t control; 1719 uint32_t mask_value; 1720 } bge_recv_rule_t; 1721 1722 /* 1723 * This describes which sub-rule slots are used by a particular rule. 1724 */ 1725 typedef struct { 1726 int start; 1727 int count; 1728 } bge_rule_info_t; 1729 1730 /* 1731 * Indexes into the <buff_cons_index> array 1732 */ 1733 #ifdef _BIG_ENDIAN 1734 #define STATUS_STD_BUFF_CONS_INDEX 0 1735 #define STATUS_JUMBO_BUFF_CONS_INDEX 1 1736 #define STATUS_MINI_BUFF_CONS_INDEX 3 1737 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index) 1738 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index) 1739 #else 1740 #define STATUS_STD_BUFF_CONS_INDEX 3 1741 #define STATUS_JUMBO_BUFF_CONS_INDEX 2 1742 #define STATUS_MINI_BUFF_CONS_INDEX 0 1743 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index) 1744 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index) 1745 #endif /* _BIG_ENDIAN */ 1746 1747 /* 1748 * Bits in the <flags_n_tag> word 1749 */ 1750 #define STATUS_FLAG_UPDATED 0x0000000100000000ull 1751 #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull 1752 #define STATUS_FLAG_ERROR 0x0000000400000000ull 1753 #define STATUS_TAG_MASK 0x00000000000000FFull 1754 1755 /* 1756 * The tag from the status block is fed back to Interrupt Mailbox 0 1757 * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This 1758 * lets the chip know what updates have been processed, so it can 1759 * reassert its interrupt if more updates have occurred since. 1760 * 1761 * These macros extract the tag from the <flags_n_tag> word, shift 1762 * it to the proper position in the Mailbox register, and provide 1763 * the complete values to write to INTERRUPT_MBOX_0_REG to disable 1764 * or enable interrupts 1765 */ 1766 #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK) 1767 #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24) 1768 #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1) 1769 #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0) 1770 1771 /* 1772 * Hardware-defined Statistics Block Offsets 1773 * 1774 * These are given in the manual as addresses in NIC memory, starting 1775 * from the NIC statistics area base address of 0x300; but here we 1776 * convert them into indexes into an array of (uint64_t)s, so we can 1777 * use them directly for accessing the copy of the statistics block 1778 * that the chip DMAs into main memory ... 1779 */ 1780 1781 #define KS_BASE 0x300 1782 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t)) 1783 1784 typedef enum { 1785 KS_ifHCInOctets = KS_ADDR(0x400), 1786 KS_etherStatsFragments = KS_ADDR(0x410), 1787 KS_ifHCInUcastPkts, 1788 KS_ifHCInMulticastPkts, 1789 KS_ifHCInBroadcastPkts, 1790 KS_dot3StatsFCSErrors, 1791 KS_dot3StatsAlignmentErrors, 1792 KS_xonPauseFramesReceived, 1793 KS_xoffPauseFramesReceived, 1794 KS_macControlFramesReceived, 1795 KS_xoffStateEntered, 1796 KS_dot3StatsFrameTooLongs, 1797 KS_etherStatsJabbers, 1798 KS_etherStatsUndersizePkts, 1799 KS_inRangeLengthError, 1800 KS_outRangeLengthError, 1801 KS_etherStatsPkts64Octets, 1802 KS_etherStatsPkts65to127Octets, 1803 KS_etherStatsPkts128to255Octets, 1804 KS_etherStatsPkts256to511Octets, 1805 KS_etherStatsPkts512to1023Octets, 1806 KS_etherStatsPkts1024to1518Octets, 1807 KS_etherStatsPkts1519to2047Octets, 1808 KS_etherStatsPkts2048to4095Octets, 1809 KS_etherStatsPkts4096to8191Octets, 1810 KS_etherStatsPkts8192to9022Octets, 1811 1812 KS_ifHCOutOctets = KS_ADDR(0x600), 1813 KS_etherStatsCollisions = KS_ADDR(0x610), 1814 KS_outXonSent, 1815 KS_outXoffSent, 1816 KS_flowControlDone, 1817 KS_dot3StatsInternalMacTransmitErrors, 1818 KS_dot3StatsSingleCollisionFrames, 1819 KS_dot3StatsMultipleCollisionFrames, 1820 KS_dot3StatsDeferredTransmissions, 1821 KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658), 1822 KS_dot3StatsLateCollisions, 1823 KS_dot3Collided2Times, 1824 KS_dot3Collided3Times, 1825 KS_dot3Collided4Times, 1826 KS_dot3Collided5Times, 1827 KS_dot3Collided6Times, 1828 KS_dot3Collided7Times, 1829 KS_dot3Collided8Times, 1830 KS_dot3Collided9Times, 1831 KS_dot3Collided10Times, 1832 KS_dot3Collided11Times, 1833 KS_dot3Collided12Times, 1834 KS_dot3Collided13Times, 1835 KS_dot3Collided14Times, 1836 KS_dot3Collided15Times, 1837 KS_ifHCOutUcastPkts, 1838 KS_ifHCOutMulticastPkts, 1839 KS_ifHCOutBroadcastPkts, 1840 KS_dot3StatsCarrierSenseErrors, 1841 KS_ifOutDiscards, 1842 KS_ifOutErrors, 1843 1844 KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */ 1845 KS_COSIfHCInPkts_2, 1846 KS_COSIfHCInPkts_3, 1847 KS_COSIfHCInPkts_4, 1848 KS_COSIfHCInPkts_5, 1849 KS_COSIfHCInPkts_6, 1850 KS_COSIfHCInPkts_7, 1851 KS_COSIfHCInPkts_8, 1852 KS_COSIfHCInPkts_9, 1853 KS_COSIfHCInPkts_10, 1854 KS_COSIfHCInPkts_11, 1855 KS_COSIfHCInPkts_12, 1856 KS_COSIfHCInPkts_13, 1857 KS_COSIfHCInPkts_14, 1858 KS_COSIfHCInPkts_15, 1859 KS_COSIfHCInPkts_16, 1860 KS_COSFramesDroppedDueToFilters, 1861 KS_nicDmaWriteQueueFull, 1862 KS_nicDmaWriteHighPriQueueFull, 1863 KS_nicNoMoreRxBDs, 1864 KS_ifInDiscards, 1865 KS_ifInErrors, 1866 KS_nicRecvThresholdHit, 1867 1868 KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */ 1869 KS_COSIfHCOutPkts_2, 1870 KS_COSIfHCOutPkts_3, 1871 KS_COSIfHCOutPkts_4, 1872 KS_COSIfHCOutPkts_5, 1873 KS_COSIfHCOutPkts_6, 1874 KS_COSIfHCOutPkts_7, 1875 KS_COSIfHCOutPkts_8, 1876 KS_COSIfHCOutPkts_9, 1877 KS_COSIfHCOutPkts_10, 1878 KS_COSIfHCOutPkts_11, 1879 KS_COSIfHCOutPkts_12, 1880 KS_COSIfHCOutPkts_13, 1881 KS_COSIfHCOutPkts_14, 1882 KS_COSIfHCOutPkts_15, 1883 KS_COSIfHCOutPkts_16, 1884 KS_nicDmaReadQueueFull, 1885 KS_nicDmaReadHighPriQueueFull, 1886 KS_nicSendDataCompQueueFull, 1887 KS_nicRingSetSendProdIndex, 1888 KS_nicRingStatusUpdate, 1889 KS_nicInterrupts, 1890 KS_nicAvoidedInterrupts, 1891 KS_nicSendThresholdHit, 1892 1893 KS_STATS_SIZE = KS_ADDR(0xb00) 1894 } bge_stats_offset_t; 1895 1896 /* 1897 * Hardware-defined Statistics Block 1898 * 1899 * Another view of the statistic block, as a array and a structure ... 1900 */ 1901 1902 typedef union { 1903 uint64_t a[KS_STATS_SIZE]; 1904 struct { 1905 uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)]; 1906 1907 uint64_t ifHCInOctets; /* 0x0400 */ 1908 uint64_t spare2[1]; 1909 uint64_t etherStatsFragments; 1910 uint64_t ifHCInUcastPkts; 1911 uint64_t ifHCInMulticastPkts; 1912 uint64_t ifHCInBroadcastPkts; 1913 uint64_t dot3StatsFCSErrors; 1914 uint64_t dot3StatsAlignmentErrors; 1915 uint64_t xonPauseFramesReceived; 1916 uint64_t xoffPauseFramesReceived; 1917 uint64_t macControlFramesReceived; 1918 uint64_t xoffStateEntered; 1919 uint64_t dot3StatsFrameTooLongs; 1920 uint64_t etherStatsJabbers; 1921 uint64_t etherStatsUndersizePkts; 1922 uint64_t inRangeLengthError; 1923 uint64_t outRangeLengthError; 1924 uint64_t etherStatsPkts64Octets; 1925 uint64_t etherStatsPkts65to127Octets; 1926 uint64_t etherStatsPkts128to255Octets; 1927 uint64_t etherStatsPkts256to511Octets; 1928 uint64_t etherStatsPkts512to1023Octets; 1929 uint64_t etherStatsPkts1024to1518Octets; 1930 uint64_t etherStatsPkts1519to2047Octets; 1931 uint64_t etherStatsPkts2048to4095Octets; 1932 uint64_t etherStatsPkts4096to8191Octets; 1933 uint64_t etherStatsPkts8192to9022Octets; 1934 uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)]; 1935 1936 uint64_t ifHCOutOctets; /* 0x0600 */ 1937 uint64_t spare4[1]; 1938 uint64_t etherStatsCollisions; 1939 uint64_t outXonSent; 1940 uint64_t outXoffSent; 1941 uint64_t flowControlDone; 1942 uint64_t dot3StatsInternalMacTransmitErrors; 1943 uint64_t dot3StatsSingleCollisionFrames; 1944 uint64_t dot3StatsMultipleCollisionFrames; 1945 uint64_t dot3StatsDeferredTransmissions; 1946 uint64_t spare5[1]; 1947 uint64_t dot3StatsExcessiveCollisions; 1948 uint64_t dot3StatsLateCollisions; 1949 uint64_t dot3Collided2Times; 1950 uint64_t dot3Collided3Times; 1951 uint64_t dot3Collided4Times; 1952 uint64_t dot3Collided5Times; 1953 uint64_t dot3Collided6Times; 1954 uint64_t dot3Collided7Times; 1955 uint64_t dot3Collided8Times; 1956 uint64_t dot3Collided9Times; 1957 uint64_t dot3Collided10Times; 1958 uint64_t dot3Collided11Times; 1959 uint64_t dot3Collided12Times; 1960 uint64_t dot3Collided13Times; 1961 uint64_t dot3Collided14Times; 1962 uint64_t dot3Collided15Times; 1963 uint64_t ifHCOutUcastPkts; 1964 uint64_t ifHCOutMulticastPkts; 1965 uint64_t ifHCOutBroadcastPkts; 1966 uint64_t dot3StatsCarrierSenseErrors; 1967 uint64_t ifOutDiscards; 1968 uint64_t ifOutErrors; 1969 uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)]; 1970 1971 uint64_t COSIfHCInPkts[16]; /* 0x0800 */ 1972 uint64_t COSFramesDroppedDueToFilters; 1973 uint64_t nicDmaWriteQueueFull; 1974 uint64_t nicDmaWriteHighPriQueueFull; 1975 uint64_t nicNoMoreRxBDs; 1976 uint64_t ifInDiscards; 1977 uint64_t ifInErrors; 1978 uint64_t nicRecvThresholdHit; 1979 uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)]; 1980 1981 uint64_t COSIfHCOutPkts[16]; /* 0x0900 */ 1982 uint64_t nicDmaReadQueueFull; 1983 uint64_t nicDmaReadHighPriQueueFull; 1984 uint64_t nicSendDataCompQueueFull; 1985 uint64_t nicRingSetSendProdIndex; 1986 uint64_t nicRingStatusUpdate; 1987 uint64_t nicInterrupts; 1988 uint64_t nicAvoidedInterrupts; 1989 uint64_t nicSendThresholdHit; 1990 uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)]; 1991 } s; 1992 } bge_statistics_t; 1993 1994 #define KS_STAT_REG_SIZE (0x1B) 1995 #define KS_STAT_REG_BASE (0x800) 1996 1997 typedef struct { 1998 uint32_t ifHCOutOctets; 1999 uint32_t etherStatsCollisions; 2000 uint32_t outXonSent; 2001 uint32_t outXoffSent; 2002 uint32_t dot3StatsInternalMacTransmitErrors; 2003 uint32_t dot3StatsSingleCollisionFrames; 2004 uint32_t dot3StatsMultipleCollisionFrames; 2005 uint32_t dot3StatsDeferredTransmissions; 2006 uint32_t dot3StatsExcessiveCollisions; 2007 uint32_t dot3StatsLateCollisions; 2008 uint32_t ifHCOutUcastPkts; 2009 uint32_t ifHCOutMulticastPkts; 2010 uint32_t ifHCOutBroadcastPkts; 2011 uint32_t ifHCInOctets; 2012 uint32_t etherStatsFragments; 2013 uint32_t ifHCInUcastPkts; 2014 uint32_t ifHCInMulticastPkts; 2015 uint32_t ifHCInBroadcastPkts; 2016 uint32_t dot3StatsFCSErrors; 2017 uint32_t dot3StatsAlignmentErrors; 2018 uint32_t xonPauseFramesReceived; 2019 uint32_t xoffPauseFramesReceived; 2020 uint32_t macControlFramesReceived; 2021 uint32_t xoffStateEntered; 2022 uint32_t dot3StatsFrameTooLongs; 2023 uint32_t etherStatsJabbers; 2024 uint32_t etherStatsUndersizePkts; 2025 } bge_statistics_reg_t; 2026 2027 2028 #ifdef BGE_IPMI_ASF 2029 2030 /* 2031 * Device internal memory entries 2032 */ 2033 2034 #define BGE_FIRMWARE_MAILBOX 0x0b50 2035 #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654 2036 #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b 2037 2038 2039 #define BGE_NIC_DATA_SIG_ADDR 0x0b54 2040 #define BGE_NIC_DATA_SIG 0x4b657654 2041 2042 2043 #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58 2044 2045 #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004 2046 #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008 2047 #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004 2048 #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008 2049 #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c 2050 2051 #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000 2052 #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010 2053 #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020 2054 #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030 2055 2056 #define BGE_NIC_CFG_ENABLE_WOL 0x000040 2057 #define BGE_NIC_CFG_ENABLE_ASF 0x000080 2058 #define BGE_NIC_CFG_EEPROM_WP 0x000100 2059 #define BGE_NIC_CFG_POWER_SAVING 0x000200 2060 #define BGE_NIC_CFG_SWAP_PORT 0x000800 2061 #define BGE_NIC_CFG_MINI_PCI 0x001000 2062 #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000 2063 #define BGE_NIC_CFG_5753_12x12 0x100000 2064 2065 2066 #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c 2067 2068 2069 #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74 2070 #define BGE_NIC_PHY_ID1_MASK 0xffff0000 2071 #define BGE_NIC_PHY_ID2_MASK 0x0000ffff 2072 2073 2074 #define BGE_CMD_MAILBOX 0x0b78 2075 #define BGE_CMD_NICDRV_ALIVE 0x00000001 2076 #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002 2077 #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003 2078 #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004 2079 2080 2081 #define BGE_CMD_LENGTH_MAILBOX 0x0b7c 2082 #define BGE_CMD_DATA_MAILBOX 0x0b80 2083 #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00 2084 2085 #define BGE_DRV_STATE_MAILBOX 0x0c04 2086 #define BGE_DRV_STATE_START 0x00000001 2087 #define BGE_DRV_STATE_START_DONE 0x80000001 2088 #define BGE_DRV_STATE_UNLOAD 0x00000002 2089 #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002 2090 #define BGE_DRV_STATE_WOL 0x00000003 2091 #define BGE_DRV_STATE_SUSPEND 0x00000004 2092 2093 2094 #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08 2095 #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001 2096 #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002 2097 2098 2099 #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14 2100 #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18 2101 2102 2103 /* 2104 * RX-RISC event register 2105 */ 2106 #define RX_RISC_EVENT_REG 0x6810 2107 #define RRER_ASF_EVENT 0x4000 2108 2109 #endif /* BGE_IPMI_ASF */ 2110 2111 #ifdef __cplusplus 2112 } 2113 #endif 2114 2115 #endif /* _BGE_HW_H */ 2116