1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _BGE_HW_H 28 #define _BGE_HW_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 38 39 /* 40 * First section: 41 * Identification of the various Broadcom chips 42 * 43 * Note: the various ID values are *not* all unique ;-( 44 * 45 * Note: the presence of an ID here does *not* imply that the chip is 46 * supported. At this time, only the 5703C, 5704C, and 5704S devices 47 * used on the motherboards of certain Sun products are supported. 48 * 49 * Note: the revision-id values in the PCI revision ID register are 50 * *NOT* guaranteed correct. Use the chip ID from the MHCR instead. 51 */ 52 53 #define VENDOR_ID_BROADCOM 0x14e4 54 #define VENDOR_ID_SUN 0x108e 55 56 #define DEVICE_ID_5700 0x1644 57 #define DEVICE_ID_5700x 0x0003 58 #define DEVICE_ID_5701 0x1645 59 #define DEVICE_ID_5702 0x16a6 60 #define DEVICE_ID_5702fe 0x164d 61 #define DEVICE_ID_5703C 0x1647 62 #define DEVICE_ID_5703S 0x16a7 63 #define DEVICE_ID_5703 0x16c7 64 #define DEVICE_ID_5704C 0x1648 65 #define DEVICE_ID_5704S 0x16a8 66 #define DEVICE_ID_5704 0x1649 67 #define DEVICE_ID_5705C 0x1653 68 #define DEVICE_ID_5705_2 0x1654 69 #define DEVICE_ID_5705M 0x165d 70 #define DEVICE_ID_5705MA3 0x165e 71 #define DEVICE_ID_5705F 0x166e 72 #define DEVICE_ID_5706 0x164a 73 #define DEVICE_ID_5782 0x1696 74 #define DEVICE_ID_5788 0x169c 75 #define DEVICE_ID_5789 0x169d 76 #define DEVICE_ID_5751 0x1677 77 #define DEVICE_ID_5751M 0x167d 78 #define DEVICE_ID_5752 0x1600 79 #define DEVICE_ID_5752M 0x1601 80 #define DEVICE_ID_5753 0x16fd 81 #define DEVICE_ID_5754 0x167a 82 #define DEVICE_ID_5755 0x167b 83 #define DEVICE_ID_5755M 0x1673 84 #define DEVICE_ID_5721 0x1659 85 #define DEVICE_ID_5714C 0x1668 86 #define DEVICE_ID_5714S 0x1669 87 #define DEVICE_ID_5715C 0x1678 88 #define DEVICE_ID_5715S 0x1679 89 90 #define REVISION_ID_5700_B0 0x10 91 #define REVISION_ID_5700_B2 0x12 92 #define REVISION_ID_5700_B3 0x13 93 #define REVISION_ID_5700_C0 0x20 94 #define REVISION_ID_5700_C1 0x21 95 #define REVISION_ID_5700_C2 0x22 96 97 #define REVISION_ID_5701_A0 0x08 98 #define REVISION_ID_5701_A2 0x12 99 #define REVISION_ID_5701_A3 0x15 100 101 #define REVISION_ID_5702_A0 0x00 102 103 #define REVISION_ID_5703_A0 0x00 104 #define REVISION_ID_5703_A1 0x01 105 #define REVISION_ID_5703_A2 0x02 106 107 #define REVISION_ID_5704_A0 0x00 108 #define REVISION_ID_5704_A1 0x01 109 #define REVISION_ID_5704_A2 0x02 110 #define REVISION_ID_5704_A3 0x03 111 #define REVISION_ID_5704_B0 0x10 112 113 #define REVISION_ID_5705_A0 0x00 114 #define REVISION_ID_5705_A1 0x01 115 #define REVISION_ID_5705_A2 0x02 116 #define REVISION_ID_5705_A3 0x03 117 118 #define REVISION_ID_5721_A0 0x00 119 #define REVISION_ID_5721_A1 0x01 120 121 #define REVISION_ID_5751_A0 0x00 122 #define REVISION_ID_5751_A1 0x01 123 124 #define REVISION_ID_5714_A0 0x00 125 #define REVISION_ID_5714_A1 0x01 126 #define REVISION_ID_5714_A2 0xA2 127 #define REVISION_ID_5714_A3 0xA3 128 129 #define REVISION_ID_5715_A0 0x00 130 #define REVISION_ID_5715_A1 0x01 131 #define REVISION_ID_5715_A2 0xA2 132 133 #define REVISION_ID_5715S_A0 0x00 134 #define REVISION_ID_5715S_A1 0x01 135 136 #define REVISION_ID_5754_A0 0x00 137 #define REVISION_ID_5754_A1 0x01 138 139 #define DEVICE_5704_SERIES_CHIPSETS(bgep)\ 140 ((bgep->chipid.device == DEVICE_ID_5700) ||\ 141 (bgep->chipid.device == DEVICE_ID_5701) ||\ 142 (bgep->chipid.device == DEVICE_ID_5702) ||\ 143 (bgep->chipid.device == DEVICE_ID_5702fe)||\ 144 (bgep->chipid.device == DEVICE_ID_5703C) ||\ 145 (bgep->chipid.device == DEVICE_ID_5703S) ||\ 146 (bgep->chipid.device == DEVICE_ID_5703) ||\ 147 (bgep->chipid.device == DEVICE_ID_5704C) ||\ 148 (bgep->chipid.device == DEVICE_ID_5704S) ||\ 149 (bgep->chipid.device == DEVICE_ID_5704)) 150 151 #define DEVICE_5702_SERIES_CHIPSETS(bgep) \ 152 ((bgep->chipid.device == DEVICE_ID_5702) ||\ 153 (bgep->chipid.device == DEVICE_ID_5702fe)) 154 155 #define DEVICE_5705_SERIES_CHIPSETS(bgep) \ 156 ((bgep->chipid.device == DEVICE_ID_5705C) ||\ 157 (bgep->chipid.device == DEVICE_ID_5705M) ||\ 158 (bgep->chipid.device == DEVICE_ID_5705MA3) ||\ 159 (bgep->chipid.device == DEVICE_ID_5705F) ||\ 160 (bgep->chipid.device == DEVICE_ID_5782) ||\ 161 (bgep->chipid.device == DEVICE_ID_5788) ||\ 162 (bgep->chipid.device == DEVICE_ID_5705_2) ||\ 163 (bgep->chipid.device == DEVICE_ID_5754) ||\ 164 (bgep->chipid.device == DEVICE_ID_5755) ||\ 165 (bgep->chipid.device == DEVICE_ID_5753)) 166 167 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \ 168 ((bgep->chipid.device == DEVICE_ID_5721) ||\ 169 (bgep->chipid.device == DEVICE_ID_5751) ||\ 170 (bgep->chipid.device == DEVICE_ID_5751M) ||\ 171 (bgep->chipid.device == DEVICE_ID_5752) ||\ 172 (bgep->chipid.device == DEVICE_ID_5752M) ||\ 173 (bgep->chipid.device == DEVICE_ID_5789)) 174 175 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \ 176 ((bgep->chipid.device == DEVICE_ID_5714C) ||\ 177 (bgep->chipid.device == DEVICE_ID_5714S) ||\ 178 (bgep->chipid.device == DEVICE_ID_5715C) ||\ 179 (bgep->chipid.device == DEVICE_ID_5715S)) 180 181 /* 182 * Second section: 183 * Offsets of important registers & definitions for bits therein 184 */ 185 186 /* 187 * PCI-X registers & bits 188 */ 189 #define PCIX_CONF_COMM 0x42 190 #define PCIX_COMM_RELAXED 0x0002 191 192 /* 193 * Miscellaneous Host Control Register, in PCI config space 194 */ 195 #define PCI_CONF_BGE_MHCR 0x68 196 #define MHCR_CHIP_REV_MASK 0xffff0000 197 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200 198 #define MHCR_MASK_INTERRUPT_MODE 0x00000100 199 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080 200 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040 201 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020 202 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010 203 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008 204 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004 205 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002 206 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001 207 208 #define MHCR_CHIP_REV_5700_B0 0x71000000 209 #define MHCR_CHIP_REV_5700_B2 0x71020000 210 #define MHCR_CHIP_REV_5700_B3 0x71030000 211 #define MHCR_CHIP_REV_5700_C0 0x72000000 212 #define MHCR_CHIP_REV_5700_C1 0x72010000 213 #define MHCR_CHIP_REV_5700_C2 0x72020000 214 215 #define MHCR_CHIP_REV_5701_A0 0x00000000 216 #define MHCR_CHIP_REV_5701_A2 0x00020000 217 #define MHCR_CHIP_REV_5701_A3 0x00030000 218 #define MHCR_CHIP_REV_5701_A5 0x01050000 219 220 #define MHCR_CHIP_REV_5702_A0 0x10000000 221 #define MHCR_CHIP_REV_5702_A1 0x10010000 222 #define MHCR_CHIP_REV_5702_A2 0x10020000 223 224 #define MHCR_CHIP_REV_5703_A0 0x10000000 225 #define MHCR_CHIP_REV_5703_A1 0x10010000 226 #define MHCR_CHIP_REV_5703_A2 0x10020000 227 #define MHCR_CHIP_REV_5703_B0 0x11000000 228 #define MHCR_CHIP_REV_5703_B1 0x11010000 229 230 #define MHCR_CHIP_REV_5704_A0 0x20000000 231 #define MHCR_CHIP_REV_5704_A1 0x20010000 232 #define MHCR_CHIP_REV_5704_A2 0x20020000 233 #define MHCR_CHIP_REV_5704_A3 0x20030000 234 #define MHCR_CHIP_REV_5704_B0 0x21000000 235 236 #define MHCR_CHIP_REV_5705_A0 0x30000000 237 #define MHCR_CHIP_REV_5705_A1 0x30010000 238 #define MHCR_CHIP_REV_5705_A2 0x30020000 239 #define MHCR_CHIP_REV_5705_A3 0x30030000 240 #define MHCR_CHIP_REV_5705_A5 0x30050000 241 242 #define MHCR_CHIP_REV_5782_A0 0x30030000 243 #define MHCR_CHIP_REV_5782_A1 0x30030088 244 245 #define MHCR_CHIP_REV_5788_A1 0x30050000 246 247 #define MHCR_CHIP_REV_5751_A0 0x40000000 248 #define MHCR_CHIP_REV_5751_A1 0x40010000 249 250 #define MHCR_CHIP_REV_5721_A0 0x41000000 251 #define MHCR_CHIP_REV_5721_A1 0x41010000 252 253 #define MHCR_CHIP_REV_5714_A0 0x50000000 254 #define MHCR_CHIP_REV_5714_A1 0x90010000 255 256 #define MHCR_CHIP_REV_5715_A0 0x50000000 257 #define MHCR_CHIP_REV_5715_A1 0x90010000 258 259 #define MHCR_CHIP_REV_5715S_A0 0x50000000 260 #define MHCR_CHIP_REV_5715S_A1 0x90010000 261 262 #define MHCR_CHIP_REV_5754_A0 0xb0000000 263 #define MHCR_CHIP_REV_5754_A1 0xb0010000 264 265 #define MHCR_CHIP_REV_5755_A0 0xa0000000 266 #define MHCR_CHIP_REV_5755_A1 0xa0010000 267 268 #define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000) 269 #define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28) 270 #define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28) 271 #define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28) 272 #define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28) 273 #define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28) 274 #define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28) 275 #define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28) 276 #define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28) 277 #define MHCR_CHIP_ASIC_REV_5754 (0xb << 28) 278 #define MHCR_CHIP_ASIC_REV_5755 ((uint32_t)0xa << 28) 279 #define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28) 280 281 282 /* 283 * PCI DMA read/write Control Register, in PCI config space 284 * 285 * Note that several fields previously defined here have been deleted 286 * as they are not implemented in the 5703/4. 287 * 288 * Note: the value of this register is critical. It is possible to 289 * cause various unpleasant effects (DTOs, transaction deadlock, etc) 290 * by programming the wrong value. The value #defined below has been 291 * tested and shown to avoid all known problems. If it is to be changed, 292 * correct operation must be reverified on all supported platforms. 293 * 294 * In particular, we set both watermark fields to 2xCacheLineSize (128) 295 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions 296 * with Tomatillo's internal pipelines, that otherwise result in stalls, 297 * repeated retries, and DTOs. 298 */ 299 #define PCI_CONF_BGE_PDRWCR 0x6c 300 #define PDRWCR_RWCMD_MASK 0xFF000000 301 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000 302 #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000 303 #define PDRWCR_READ_WATERMARK_MASK 0x00070000 304 #define PDRWCR_CONCURRENCY_MASK 0x0000c000 305 #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000 306 #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000 307 #define PDRWCR_MIN_BEAT_MASK 0x000000ff 308 309 /* 310 * These are the actual values to be put into the fields shown above 311 */ 312 #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */ 313 #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */ 314 #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */ 315 #define PDRWCR_MIN_BEATS 0x00000000 316 317 #define PDRWCR_VAR_DEFAULT 0x761b0000 318 #define PDRWCR_VAR_5721 0x76180000 319 #define PDRWCR_VAR_5714 0x76148000 /* OR of above */ 320 #define PDRWCR_VAR_5715 0x76144000 /* OR of above */ 321 322 /* 323 * PCI State Register, in PCI config space 324 * 325 * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit 326 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW 327 */ 328 #define PCI_CONF_BGE_PCISTATE 0x70 329 #define PCISTATE_RETRY_SAME_DMA 0x00002000 330 #define PCISTATE_FLAT_VIEW 0x00000100 331 #define PCISTATE_EXT_ROM_RETRY 0x00000040 332 #define PCISTATE_EXT_ROM_ENABLE 0x00000020 333 #define PCISTATE_BUS_IS_32_BIT 0x00000010 334 #define PCISTATE_BUS_IS_FAST 0x00000008 335 #define PCISTATE_BUS_IS_PCI 0x00000004 336 #define PCISTATE_INTA_STATE 0x00000002 337 #define PCISTATE_FORCE_RESET 0x00000001 338 339 /* 340 * PCI Clock Control Register, in PCI config space 341 */ 342 #define PCI_CONF_BGE_CLKCTL 0x74 343 #define CLKCTL_PCIE_PLP_DISABLE 0x80000000 344 #define CLKCTL_PCIE_DLP_DISABLE 0x40000000 345 #define CLKCTL_PCIE_TLP_DISABLE 0x20000000 346 #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000 347 #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000 348 #define CLKCTL_PCIE_A0_FIX 0x00101000 349 350 /* 351 * Dual MAC Control Register, in PCI config space 352 */ 353 #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8 354 #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */ 355 #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */ 356 357 /* 358 * Register Indirect Access Address Register, 0x78 in PCI config 359 * space. Once this is set, accesses to the Register Indirect 360 * Access Data Register (0x80) refer to the register whose address 361 * is given by *this* register. This allows access to all the 362 * operating registers, while using only config space accesses. 363 * 364 * Note that the address written to the RIIAR should lie in one 365 * of the following ranges: 366 * 0x00000000 <= address < 0x00008000 (regular registers) 367 * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad) 368 * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad) 369 * 0x00038000 <= address < 0x00038800 (RxRISC ROM) 370 */ 371 #define PCI_CONF_BGE_RIAAR 0x78 372 #define PCI_CONF_BGE_RIADR 0x80 373 374 #define RIAAR_REGISTER_MIN 0x00000000 375 #define RIAAR_REGISTER_MAX 0x00008000 376 #define RIAAR_RX_SCRATCH_MIN 0x00030000 377 #define RIAAR_RX_SCRATCH_MAX 0x00034000 378 #define RIAAR_TX_SCRATCH_MIN 0x00034000 379 #define RIAAR_TX_SCRATCH_MAX 0x00038000 380 #define RIAAR_RXROM_MIN 0x00038000 381 #define RIAAR_RXROM_MAX 0x00038800 382 383 /* 384 * Memory Window Base Address Register, 0x7c in PCI config space 385 * Once this is set, accesses to the Memory Window Data Access Register 386 * (0x84) refer to the word of NIC-local memory whose address is given 387 * by this register. When used in this way, the whole of the address 388 * written to this register is significant. 389 * 390 * This register also provides the 32K-aligned base address for a 32K 391 * region of NIC-local memory that the host can directly address in 392 * the upper 32K of the 64K of PCI memory space allocated to the chip. 393 * In this case, the bottom 15 bits of the register are ignored. 394 * 395 * Note that the address written to the MWBAR should lie in the range 396 * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M 397 * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external 398 * memory were present, but it's only supported on the 5700, not the 399 * 5701/5703/5704. 400 */ 401 #define PCI_CONF_BGE_MWBAR 0x7c 402 #define PCI_CONF_BGE_MWDAR 0x84 403 #define MWBAR_GRANULARITY 0x00008000 /* 32k */ 404 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1) 405 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */ 406 407 /* 408 * The PCI express device control register and device status register 409 * which are only applicable on BCM5751 and BCM5721. 410 */ 411 #define PCI_CONF_DEV_CTRL 0xd8 412 #define READ_REQ_SIZE_MAX 0x5000 413 #define DEV_CTRL_NO_SNOOP 0x0800 414 #define DEV_CTRL_RELAXED 0x0010 415 416 #define PCI_CONF_DEV_STUS 0xda 417 #define DEVICE_ERROR_STUS 0xf 418 419 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */ 420 421 /* 422 * Where to find things in NIC-local (on-chip) memory 423 */ 424 #define NIC_MEM_SEND_RINGS 0x0100 425 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring)) 426 #define NIC_MEM_RECV_RINGS 0x0200 427 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring)) 428 #define NIC_MEM_STATISTICS 0x0300 429 #define NIC_MEM_STATISTICS_SIZE 0x0800 430 #define NIC_MEM_STATUS_BLOCK 0x0b00 431 #define NIC_MEM_STATUS_SIZE 0x0050 432 #define NIC_MEM_GENCOMM 0x0b50 433 434 435 /* 436 * Note: the (non-bogus) values below are appropriate for systems 437 * without external memory. They would be different on a 5700 with 438 * external memory. 439 * 440 * Note: The higher send ring addresses and the mini ring shadow 441 * buffer address are dummies - systems without external memory 442 * are limited to 4 send rings and no mini receive ring. 443 */ 444 #define NIC_MEM_SHADOW_DMA 0x2000 445 #define NIC_MEM_SHADOW_SEND_1_4 0x4000 446 #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */ 447 #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */ 448 #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */ 449 #define NIC_MEM_SHADOW_BUFF_STD 0x6000 450 #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000 451 #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */ 452 #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots)) 453 454 /* 455 * Put this in the GENCOMM port to tell the firmware not to run PXE 456 */ 457 #define T3_MAGIC_NUMBER 0x4b657654u 458 459 /* 460 * The remaining registers appear in the low 32K of regular 461 * PCI Memory Address Space 462 */ 463 464 /* 465 * All the state machine control registers below have at least a 466 * <RESET> bit and an <ENABLE> bit as defined below. Some also 467 * have an <ATTN_ENABLE> bit. 468 */ 469 #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004 470 #define STATE_MACHINE_ENABLE_BIT 0x00000002 471 #define STATE_MACHINE_RESET_BIT 0x00000001 472 473 #define TRANSMIT_MAC_MODE_REG 0x045c 474 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00 475 #define SEND_DATA_COMPLETION_MODE_REG 0x1000 476 #define SEND_BD_SELECTOR_MODE_REG 0x1400 477 #define SEND_BD_INITIATOR_MODE_REG 0x1800 478 #define SEND_BD_COMPLETION_MODE_REG 0x1c00 479 480 #define RECEIVE_MAC_MODE_REG 0x0468 481 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000 482 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400 483 #define RCV_DATA_COMPLETION_MODE_REG 0x2800 484 #define RCV_BD_INITIATOR_MODE_REG 0x2c00 485 #define RCV_BD_COMPLETION_MODE_REG 0x3000 486 #define RCV_LIST_SELECTOR_MODE_REG 0x3400 487 488 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800 489 #define HOST_COALESCE_MODE_REG 0x3c00 490 #define MEMORY_ARBITER_MODE_REG 0x4000 491 #define BUFFER_MANAGER_MODE_REG 0x4400 492 #define READ_DMA_MODE_REG 0x4800 493 #define WRITE_DMA_MODE_REG 0x4c00 494 #define DMA_COMPLETION_MODE_REG 0x6400 495 496 /* 497 * Other bits in some of the above state machine control registers 498 */ 499 500 /* 501 * Transmit MAC Mode Register 502 * (TRANSMIT_MAC_MODE_REG, 0x045c) 503 */ 504 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040 505 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020 506 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010 507 508 /* 509 * Receive MAC Mode Register 510 * (RECEIVE_MAC_MODE_REG, 0x0468) 511 */ 512 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400 513 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200 514 #define RECEIVE_MODE_PROMISCUOUS 0x00000100 515 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080 516 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040 517 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020 518 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010 519 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004 520 521 /* 522 * Receive BD Initiator Mode Register 523 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00) 524 * 525 * Each of these bits controls whether ATTN is asserted 526 * on a particular condition 527 */ 528 #define RCV_BD_DISABLED_RING_ATTN 0x00000004 529 530 /* 531 * Receive Data & Receive BD Initiator Mode Register 532 * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400) 533 * 534 * Each of these bits controls whether ATTN is asserted 535 * on a particular condition 536 */ 537 #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010 538 #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008 539 #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004 540 541 #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c 542 543 /* 544 * Host Coalescing Mode Control Register 545 * (HOST_COALESCE_MODE_REG, 0x3c00) 546 */ 547 #define COALESCE_64_BYTE_RINGS 12 548 #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000 549 #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800 550 #define COALESCE_CLR_TICKS_TX 0x00000400 551 #define COALESCE_CLR_TICKS_RX 0x00000200 552 #define COALESCE_32_BYTE_STATUS 0x00000100 553 #define COALESCE_64_BYTE_STATUS 0x00000080 554 #define COALESCE_NOW 0x00000008 555 556 /* 557 * Memory Arbiter Mode Register 558 * (MEMORY_ARBITER_MODE_REG, 0x4000) 559 */ 560 #define MEMORY_ARBITER_ENABLE 0x00000002 561 562 /* 563 * Buffer Manager Mode Register 564 * (BUFFER_MANAGER_MODE_REG, 0x4400) 565 * 566 * In addition to the usual error-attn common to most state machines 567 * this register has a separate bit for attn on running-low-on-mbufs 568 */ 569 #define BUFF_MGR_TEST_MODE 0x00000008 570 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010 571 572 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014 573 574 /* 575 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG, 576 * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00) 577 * 578 * These registers each contain a 2-bit priority field, which controls 579 * the relative priority of that type of DMA (read vs. write vs. MSI), 580 * and a set of bits that control whether ATTN is asserted on each 581 * particular condition 582 */ 583 #define DMA_PRIORITY_MASK 0xc0000000 584 #define DMA_PRIORITY_SHIFT 30 585 #define ALL_DMA_ATTN_BITS 0x000003fc 586 587 /* 588 * BCM5755, 5755M, 5906, 5906M only 589 * 1 - Enable Fix. Device will send out the status block before 590 * the interrupt message 591 * 0 - Disable fix. Device will send out the interrupt message 592 * before the status block 593 */ 594 #define DMA_STATUS_TAG_FIX_CQ12384 0x20000000 595 596 /* 597 * End of state machine control register definitions 598 */ 599 600 601 /* 602 * Mailbox Registers (8 bytes each, but high half unused) 603 */ 604 #define INTERRUPT_MBOX_0_REG 0x0200 605 #define INTERRUPT_MBOX_1_REG 0x0208 606 #define INTERRUPT_MBOX_2_REG 0x0210 607 #define INTERRUPT_MBOX_3_REG 0x0218 608 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n)) 609 610 /* 611 * Ring Producer/Consumer Index (Mailbox) Registers 612 */ 613 #define RECV_STD_PROD_INDEX_REG 0x0268 614 #define RECV_JUMBO_PROD_INDEX_REG 0x0270 615 #define RECV_MINI_PROD_INDEX_REG 0x0278 616 #define RECV_RING_CONS_INDEX_REGS 0x0280 617 #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300 618 #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380 619 620 #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring)) 621 #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring)) 622 #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring)) 623 624 /* 625 * Ethernet MAC Mode Register 626 */ 627 #define ETHERNET_MAC_MODE_REG 0x0400 628 #define ETHERNET_MODE_ENABLE_FHDE 0x00800000 629 #define ETHERNET_MODE_ENABLE_RDE 0x00400000 630 #define ETHERNET_MODE_ENABLE_TDE 0x00200000 631 #define ETHERNET_MODE_ENABLE_MIP 0x00100000 632 #define ETHERNET_MODE_ENABLE_ACPI 0x00080000 633 #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000 634 #define ETHERNET_MODE_SEND_CFGS 0x00020000 635 #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000 636 #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000 637 #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000 638 #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000 639 #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000 640 #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800 641 #define ETHERNET_MODE_LINK_POLARITY 0x00000400 642 #define ETHERNET_MODE_MAX_DEFER 0x00000200 643 #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100 644 #define ETHERNET_MODE_TAGGED_MODE 0x00000080 645 #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010 646 #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c 647 #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c 648 #define ETHERNET_MODE_PORTMODE_GMII 0x00000008 649 #define ETHERNET_MODE_PORTMODE_MII 0x00000004 650 #define ETHERNET_MODE_PORTMODE_NONE 0x00000000 651 #define ETHERNET_MODE_HALF_DUPLEX 0x00000002 652 #define ETHERNET_MODE_GLOBAL_RESET 0x00000001 653 654 /* 655 * Ethernet MAC Status & Event Registers 656 */ 657 #define ETHERNET_MAC_STATUS_REG 0x0404 658 #define ETHERNET_STATUS_MI_INT 0x00800000 659 #define ETHERNET_STATUS_MI_COMPLETE 0x00400000 660 #define ETHERNET_STATUS_LINK_CHANGED 0x00001000 661 #define ETHERNET_STATUS_PCS_ERROR 0x00000400 662 #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010 663 #define ETHERNET_STATUS_CFG_CHANGED 0x00000008 664 #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004 665 #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002 666 #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001 667 668 #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408 669 #define ETHERNET_EVENT_MI_INT 0x00800000 670 #define ETHERNET_EVENT_LINK_INT 0x00001000 671 #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400 672 673 /* 674 * Ethernet MAC LED Control Register 675 * 676 * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and 677 * the external LED driver circuitry is wired up to assume that this mode 678 * will always be selected. Software must not change it! 679 */ 680 #define ETHERNET_MAC_LED_CONTROL_REG 0x040c 681 #define LED_CONTROL_OVERRIDE_BLINK 0x80000000 682 #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000 683 #define LED_CONTROL_LED_MODE_MASK 0x00001800 684 #define LED_CONTROL_LED_MODE_5700 0x00000000 685 #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */ 686 #define LED_CONTROL_LED_MODE_PHY_2 0x00001000 687 #define LED_CONTROL_LED_MODE_RESERVED 0x00001800 688 #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400 689 #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200 690 #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100 691 #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080 692 #define LED_CONTROL_BLINK_TRAFFIC 0x00000040 693 #define LED_CONTROL_TRAFFIC_LED 0x00000020 694 #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010 695 #define LED_CONTROL_10MBPS_LED 0x00000008 696 #define LED_CONTROL_100MBPS_LED 0x00000004 697 #define LED_CONTROL_1000MBPS_LED 0x00000002 698 #define LED_CONTROL_OVERRIDE_LINK 0x00000001 699 #define LED_CONTROL_DEFAULT 0x02000800 700 701 /* 702 * MAC Address registers 703 * 704 * These four eight-byte registers each hold one unicast address 705 * (six bytes), right justified & zero-filled on the left. 706 * They will normally all be set to the same value, as a station 707 * usually only has one h/w address. The value in register 0 is 708 * used for pause packets; any of the four can be specified for 709 * substitution into other transmitted packets if required. 710 */ 711 #define MAC_ADDRESS_0_REG 0x0410 712 #define MAC_ADDRESS_1_REG 0x0418 713 #define MAC_ADDRESS_2_REG 0x0420 714 #define MAC_ADDRESS_3_REG 0x0428 715 716 #define MAC_ADDRESS_REG(n) (0x0410+8*(n)) 717 #define MAC_ADDRESS_REGS_MAX 4 718 719 /* 720 * More MAC Registers ... 721 */ 722 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438 723 #define MAC_RX_MTU_SIZE_REG 0x043c 724 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */ 725 #define MAC_TX_LENGTHS_REG 0x0464 726 #define MAC_TX_LENGTHS_DEFAULT 0x00002620 727 728 /* 729 * MII access registers 730 */ 731 #define MI_COMMS_REG 0x044c 732 #define MI_COMMS_START 0x20000000 733 #define MI_COMMS_READ_FAILED 0x10000000 734 #define MI_COMMS_COMMAND_MASK 0x0c000000 735 #define MI_COMMS_COMMAND_READ 0x08000000 736 #define MI_COMMS_COMMAND_WRITE 0x04000000 737 #define MI_COMMS_ADDRESS_MASK 0x03e00000 738 #define MI_COMMS_ADDRESS_SHIFT 21 739 #define MI_COMMS_REGISTER_MASK 0x001f0000 740 #define MI_COMMS_REGISTER_SHIFT 16 741 #define MI_COMMS_DATA_MASK 0x0000ffff 742 #define MI_COMMS_DATA_SHIFT 0 743 744 #define MI_STATUS_REG 0x0450 745 #define MI_STATUS_10MBPS 0x00000002 746 #define MI_STATUS_LINK 0x00000001 747 748 #define MI_MODE_REG 0x0454 749 #define MI_MODE_CLOCK_MASK 0x001f0000 750 #define MI_MODE_AUTOPOLL 0x00000010 751 #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002 752 #define MI_MODE_DEFAULT 0x000c0000 753 754 #define MI_AUTOPOLL_STATUS_REG 0x0458 755 #define MI_AUTOPOLL_ERROR 0x00000001 756 757 #define TRANSMIT_MAC_STATUS_REG 0x0460 758 #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020 759 #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010 760 #define TRANSMIT_STATUS_LINK_UP 0x00000008 761 #define TRANSMIT_STATUS_SENT_XON 0x00000004 762 #define TRANSMIT_STATUS_SENT_XOFF 0x00000002 763 #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001 764 765 #define RECEIVE_MAC_STATUS_REG 0x046c 766 #define RECEIVE_STATUS_RCVD_XON 0x00000004 767 #define RECEIVE_STATUS_RCVD_XOFF 0x00000002 768 #define RECEIVE_STATUS_SENT_XOFF 0x00000001 769 770 /* 771 * These four-byte registers constitute a hash table for deciding 772 * whether to accept incoming multicast packets. The bits are 773 * numbered in big-endian fashion, from hash 0 => the MSB of 774 * register 0 to hash 127 => the LSB of the highest-numbered 775 * register. 776 * 777 * NOTE: the 5704 can use a 256-bit table (registers 0-7) if 778 * enabled by setting the appropriate bit in the Rx MAC mode 779 * register. Otherwise, and on all earlier chips, the table 780 * is only 128 bits (registers 0-3). 781 */ 782 #define MAC_HASH_0_REG 0x0470 783 #define MAC_HASH_1_REG 0x0474 784 #define MAC_HASH_2_REG 0x0478 785 #define MAC_HASH_3_REG 0x047c 786 #define MAC_HASH_4_REG 0x???? 787 #define MAC_HASH_5_REG 0x???? 788 #define MAC_HASH_6_REG 0x???? 789 #define MAC_HASH_7_REG 0x???? 790 #define MAC_HASH_REG(n) (0x470+4*(n)) 791 792 /* 793 * Receive Rules Registers: 16 pairs of control+mask/value pairs 794 */ 795 #define RCV_RULES_CONTROL_0_REG 0x0480 796 #define RCV_RULES_MASK_0_REG 0x0484 797 #define RCV_RULES_CONTROL_15_REG 0x04f8 798 #define RCV_RULES_MASK_15_REG 0x04fc 799 #define RCV_RULES_CONFIG_REG 0x0500 800 #define RCV_RULES_CONFIG_DEFAULT 0x00000008 801 802 #define RECV_RULES_NUM_MAX 16 803 #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule)) 804 #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule)) 805 806 #define RECV_RULE_CTL_ENABLE 0x80000000 807 #define RECV_RULE_CTL_AND 0x40000000 808 #define RECV_RULE_CTL_P1 0x20000000 809 #define RECV_RULE_CTL_P2 0x10000000 810 #define RECV_RULE_CTL_P3 0x08000000 811 #define RECV_RULE_CTL_MASK 0x04000000 812 #define RECV_RULE_CTL_DISCARD 0x02000000 813 #define RECV_RULE_CTL_MAP 0x01000000 814 #define RECV_RULE_CTL_RESV_BITS 0x00fc0000 815 #define RECV_RULE_CTL_OP 0x00030000 816 #define RECV_RULE_CTL_OP_EQ 0x00000000 817 #define RECV_RULE_CTL_OP_NEQ 0x00010000 818 #define RECV_RULE_CTL_OP_GREAT 0x00020000 819 #define RECV_RULE_CTL_OP_LESS 0x00030000 820 #define RECV_RULE_CTL_HEADER 0x0000e000 821 #define RECV_RULE_CTL_HEADER_FRAME 0x00000000 822 #define RECV_RULE_CTL_HEADER_IP 0x00002000 823 #define RECV_RULE_CTL_HEADER_TCP 0x00004000 824 #define RECV_RULE_CTL_HEADER_UDP 0x00006000 825 #define RECV_RULE_CTL_HEADER_DATA 0x00008000 826 #define RECV_RULE_CTL_CLASS_BITS 0x00001f00 827 #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \ 828 RECV_RULE_CTL_CLASS_BITS) 829 #define RECV_RULE_CTL_OFFSET 0x000000ff 830 831 /* 832 * Receive Rules definition 833 */ 834 #define RULE_MATCH_TO_RING 2 835 /* ring that traffic will go into when recv rule matches. */ 836 /* value is between 1 and 16, not 0 and 15 */ 837 838 #define IPHEADER_PROTO_OFFSET 0x08 839 #define IPHEADER_SIP_OFFSET 0x0c 840 841 #define RULE_PROTO_CONTROL (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_MASK | \ 842 RECV_RULE_CTL_OP_EQ | \ 843 RECV_RULE_CTL_HEADER_IP | \ 844 RECV_RULE_CTL_CLASS(RULE_MATCH_TO_RING) | \ 845 IPHEADER_PROTO_OFFSET) 846 #define RULE_TCP_MASK_VALUE 0x00ff0006 847 #define RULE_UDP_MASK_VALUE 0x00ff0011 848 #define RULE_ICMP_MASK_VALUE 0x00ff0001 849 850 #define RULE_SIP_ADDR 0x0a000001 851 /* ip address in 32-bit integer,such as, 0x0a000001 is "10.0.0.1" */ 852 853 #define RULE_SIP_CONTROL (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \ 854 RECV_RULE_CTL_HEADER_IP | \ 855 RECV_RULE_CTL_CLASS(RULE_MATCH_TO_RING) | \ 856 IPHEADER_SIP_OFFSET) 857 #define RULE_SIP_MASK_VALUE RULE_SIP_ADDR 858 859 /* 860 * 1000BaseX low-level access registers 861 */ 862 #define MAC_GIGABIT_PCS_TEST_REG 0x0440 863 #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000 864 #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff 865 #define TX_1000BASEX_AUTONEG_REG 0x0444 866 #define RX_1000BASEX_AUTONEG_REG 0x0448 867 868 /* 869 * Autoneg code bits for the 1000BASE-X AUTONEG registers 870 */ 871 #define AUTONEG_CODE_PAUSE 0x00008000 872 #define AUTONEG_CODE_HALF_DUPLEX 0x00004000 873 #define AUTONEG_CODE_FULL_DUPLEX 0x00002000 874 #define AUTONEG_CODE_NEXT_PAGE 0x00000080 875 #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040 876 #define AUTONEG_CODE_FAULT_MASK 0x00000030 877 #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030 878 #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020 879 #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010 880 #define AUTONEG_CODE_ASYM_PAUSE 0x00000001 881 882 /* 883 * SerDes Registers (5703S/5704S only) 884 */ 885 #define SERDES_CONTROL_REG 0x0590 886 #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000 887 #define SERDES_CONTROL_COMMA_DETECT 0x00010000 888 #define SERDES_CONTROL_TX_DISABLE 0x00004000 889 #define SERDES_STATUS_REG 0x0594 890 #define SERDES_STATUS_COMMA_DETECTED 0x00000100 891 #define SERDES_STATUS_RXSTAT 0x000000ff 892 893 /* 894 * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only) 895 */ 896 #define STAT_IFHCOUT_OCTETS_REG 0x0800 897 #define STAT_ETHER_COLLIS_REG 0x0808 898 #define STAT_OUTXON_SENT_REG 0x080c 899 #define STAT_OUTXOFF_SENT_REG 0x0810 900 #define STAT_DOT3_INTMACTX_ERR_REG 0x0818 901 #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c 902 #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820 903 #define STAT_DOT3_DEFERED_TX_REG 0x0824 904 #define STAT_DOT3_EXCE_COLLI_REG 0x082c 905 #define STAT_DOT3_LATE_COLLI_REG 0x0830 906 #define STAT_IFHCOUT_UPKGS_REG 0x086c 907 #define STAT_IFHCOUT_MPKGS_REG 0x0870 908 #define STAT_IFHCOUT_BPKGS_REG 0x0874 909 910 #define STAT_IFHCIN_OCTETS_REG 0x0880 911 #define STAT_ETHER_FRAGMENT_REG 0x0888 912 #define STAT_IFHCIN_UPKGS_REG 0x088c 913 #define STAT_IFHCIN_MPKGS_REG 0x0890 914 #define STAT_IFHCIN_BPKGS_REG 0x0894 915 916 #define STAT_DOT3_FCS_ERR_REG 0x0898 917 #define STAT_DOT3_ALIGN_ERR_REG 0x089c 918 #define STAT_XON_PAUSE_RX_REG 0x08a0 919 #define STAT_XOFF_PAUSE_RX_REG 0x08a4 920 #define STAT_MAC_CTRL_RX_REG 0x08a8 921 #define STAT_XOFF_STATE_ENTER_REG 0x08ac 922 #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0 923 #define STAT_ETHER_JABBERS_REG 0x08b4 924 #define STAT_ETHER_UNDERSIZE_REG 0x08b8 925 #define SIZE_OF_STATISTIC_REG 0x1B 926 /* 927 * Send Data Initiator Registers 928 */ 929 #define SEND_INIT_STATS_CONTROL_REG 0x0c08 930 #define SEND_INIT_STATS_ZERO 0x00000010 931 #define SEND_INIT_STATS_FLUSH 0x00000008 932 #define SEND_INIT_STATS_CLEAR 0x00000004 933 #define SEND_INIT_STATS_FASTER 0x00000002 934 #define SEND_INIT_STATS_ENABLE 0x00000001 935 936 #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c 937 938 /* 939 * Send Buffer Descriptor Selector Control Registers 940 */ 941 #define SEND_BD_SELECTOR_STATUS_REG 0x1404 942 #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408 943 #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n)) 944 945 /* 946 * Receive List Placement Registers 947 */ 948 #define RCV_LP_CONFIG_REG 0x2010 949 #define RCV_LP_CONFIG_DEFAULT 0x00000009 950 #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1) 951 952 #define RCV_LP_STATS_CONTROL_REG 0x2014 953 #define RCV_LP_STATS_ZERO 0x00000010 954 #define RCV_LP_STATS_FLUSH 0x00000008 955 #define RCV_LP_STATS_CLEAR 0x00000004 956 #define RCV_LP_STATS_FASTER 0x00000002 957 #define RCV_LP_STATS_ENABLE 0x00000001 958 959 #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018 960 #define RCV_LP_STATS_DISABLE_MACTQ 0x040000 961 962 /* 963 * Receive Data & BD Initiator Registers 964 */ 965 #define RCV_INITIATOR_STATUS_REG 0x2404 966 967 /* 968 * Receive Buffer Descriptor Ring Control Block Registers 969 * NB: sixteen bytes (128 bits) each 970 */ 971 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440 972 #define STD_RCV_BD_RING_RCB_REG 0x2450 973 #define MINI_RCV_BD_RING_RCB_REG 0x2460 974 975 /* 976 * Receive Buffer Descriptor Ring Replenish Threshold Registers 977 */ 978 #define MINI_RCV_BD_REPLENISH_REG 0x2c14 979 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */ 980 #define STD_RCV_BD_REPLENISH_REG 0x2c18 981 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */ 982 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c 983 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */ 984 985 /* 986 * Host Coalescing Engine Control Registers 987 */ 988 #define RCV_COALESCE_TICKS_REG 0x3c08 989 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 990 #define SEND_COALESCE_TICKS_REG 0x3c0c 991 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 992 #define RCV_COALESCE_MAX_BD_REG 0x3c10 993 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 994 #define SEND_COALESCE_MAX_BD_REG 0x3c14 995 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 996 #define RCV_COALESCE_INT_TICKS_REG 0x3c18 997 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 998 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c 999 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1000 #define RCV_COALESCE_INT_BD_REG 0x3c20 1001 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1002 #define SEND_COALESCE_INT_BD_REG 0x3c24 1003 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1004 #define STATISTICS_TICKS_REG 0x3c28 1005 #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */ 1006 #define STATISTICS_HOST_ADDR_REG 0x3c30 1007 #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38 1008 #define STATISTICS_BASE_ADDR_REG 0x3c40 1009 #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44 1010 #define FLOW_ATTN_REG 0x3c48 1011 1012 #define NIC_JUMBO_RECV_INDEX_REG 0x3c50 1013 #define NIC_STD_RECV_INDEX_REG 0x3c54 1014 #define NIC_MINI_RECV_INDEX_REG 0x3c58 1015 #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n)) 1016 #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n)) 1017 1018 /* 1019 * Mbuf Pool Initialisation & Watermark Registers 1020 * 1021 * There are some conflicts in the PRM; compare the recommendations 1022 * on pp. 115, 236, and 339. The values here were recommended by 1023 * dkim@broadcom.com (and the PRM should be corrected soon ;-) 1024 */ 1025 #define BUFFER_MANAGER_STATUS_REG 0x4404 1026 #define MBUF_POOL_BASE_REG 0x4408 1027 #define MBUF_POOL_BASE_DEFAULT 0x00008000 1028 #define MBUF_POOL_BASE_5721 0x00010000 1029 #define MBUF_POOL_BASE_5704 0x00010000 1030 #define MBUF_POOL_BASE_5705 0x00010000 1031 #define MBUF_POOL_LENGTH_REG 0x440c 1032 #define MBUF_POOL_LENGTH_DEFAULT 0x00018000 1033 #define MBUF_POOL_LENGTH_5704 0x00010000 1034 #define MBUF_POOL_LENGTH_5705 0x00008000 1035 #define MBUF_POOL_LENGTH_5721 0x00008000 1036 #define RDMA_MBUF_LOWAT_REG 0x4410 1037 #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050 1038 #define RDMA_MBUF_LOWAT_5705 0x00000000 1039 #define RDMA_MBUF_LOWAT_JUMBO 0x00000130 1040 #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000 1041 #define MAC_RX_MBUF_LOWAT_REG 0x4414 1042 #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020 1043 #define MAC_RX_MBUF_LOWAT_5705 0x00000010 1044 #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098 1045 #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b 1046 #define MBUF_HIWAT_REG 0x4418 1047 #define MBUF_HIWAT_DEFAULT 0x00000060 1048 #define MBUF_HIWAT_5705 0x00000060 1049 #define MBUF_HIWAT_JUMBO 0x0000017c 1050 #define MBUF_HIWAT_5714_JUMBO 0x00000096 1051 1052 /* 1053 * DMA Descriptor Pool Initialisation & Watermark Registers 1054 */ 1055 #define DMAD_POOL_BASE_REG 0x442c 1056 #define DMAD_POOL_BASE_DEFAULT 0x00002000 1057 #define DMAD_POOL_LENGTH_REG 0x4430 1058 #define DMAD_POOL_LENGTH_DEFAULT 0x00002000 1059 #define DMAD_POOL_LOWAT_REG 0x4434 1060 #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */ 1061 #define DMAD_POOL_HIWAT_REG 0x4438 1062 #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */ 1063 1064 /* 1065 * More threshold/watermark registers ... 1066 */ 1067 #define RECV_FLOW_THRESHOLD_REG 0x4458 1068 #define LOWAT_MAX_RECV_FRAMES_REG 0x0504 1069 #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002 1070 1071 /* 1072 * Read/Write DMA Status Registers 1073 */ 1074 #define READ_DMA_STATUS_REG 0x4804 1075 #define WRITE_DMA_STATUS_REG 0x4c04 1076 1077 /* 1078 * RX/TX RISC Registers 1079 */ 1080 #define RX_RISC_MODE_REG 0x5000 1081 #define RX_RISC_STATE_REG 0x5004 1082 #define RX_RISC_PC_REG 0x501c 1083 #define TX_RISC_MODE_REG 0x5400 1084 #define TX_RISC_STATE_REG 0x5404 1085 #define TX_RISC_PC_REG 0x541c 1086 1087 #define FTQ_RESET_REG 0x5c00 1088 1089 #define MSI_MODE_REG 0x6000 1090 #define MSI_PRI_HIGHEST 0xc0000000 1091 #define MSI_MSI_ENABLE 0x00000002 1092 #define MSI_ERROR_ATTENTION 0x0000001c 1093 1094 #define MSI_STATUS_REG 0x6004 1095 1096 #define MODE_CONTROL_REG 0x6800 1097 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000 1098 #define MODE_4X_NIC_SEND_RINGS 0x20000000 1099 #define MODE_INT_ON_FLOW_ATTN 0x10000000 1100 #define MODE_INT_ON_DMA_ATTN 0x08000000 1101 #define MODE_INT_ON_MAC_ATTN 0x04000000 1102 #define MODE_INT_ON_RXRISC_ATTN 0x02000000 1103 #define MODE_INT_ON_TXRISC_ATTN 0x01000000 1104 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000 1105 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000 1106 #define MODE_HOST_SEND_BDS 0x00020000 1107 #define MODE_HOST_STACK_UP 0x00010000 1108 #define MODE_FORCE_32_BIT_PCI 0x00008000 1109 #define MODE_NO_INT_ON_RECV 0x00004000 1110 #define MODE_NO_INT_ON_SEND 0x00002000 1111 #define MODE_ALLOW_BAD_FRAMES 0x00000800 1112 #define MODE_NO_CRC 0x00000400 1113 #define MODE_NO_FRAME_CRACKING 0x00000200 1114 #define MODE_WORD_SWAP_FRAME 0x00000020 1115 #define MODE_BYTE_SWAP_FRAME 0x00000010 1116 #define MODE_WORD_SWAP_NONFRAME 0x00000004 1117 #define MODE_BYTE_SWAP_NONFRAME 0x00000002 1118 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001 1119 1120 /* 1121 * Miscellaneous Configuration Register 1122 * 1123 * This contains various bits relating to power control (which differ 1124 * among different members of the chip family), but the important bits 1125 * for our purposes are the RESET bit and the Timer Prescaler field. 1126 * 1127 * The RESET bit in this register serves to reset the whole chip, even 1128 * including the PCI interface(!) Once it's set, the chip will not 1129 * respond to ANY accesses -- not even CONFIG space -- until the reset 1130 * completes internally. According to the PRM, this should take less 1131 * than 100us. Any access during this period will get a bus error. 1132 * 1133 * The Timer Prescaler field must be programmed so that the timer period 1134 * is as near as possible to 1us. The value in this field should be 1135 * the Core Clock frequency in MHz minus 1. From my reading of the PRM, 1136 * the Core Clock should always be 66MHz (independently of the bus speed, 1137 * at least for PCI rather than PCI-X), so this register must be set to 1138 * the value 0x82 ((66-1) << 1). 1139 */ 1140 #define CORE_CLOCK_MHZ 66 1141 #define MISC_CONFIG_REG 0x6804 1142 #define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000 1143 #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000 1144 #define MISC_CONFIG_POWERDOWN 0x00100000 1145 #define MISC_CONFIG_POWER_STATE 0x00060000 1146 #define MISC_CONFIG_PRESCALE_MASK 0x000000fe 1147 #define MISC_CONFIG_RESET_BIT 0x00000001 1148 #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1) 1149 1150 /* 1151 * Miscellaneous Local Control Register (MLCR) 1152 */ 1153 #define MISC_LOCAL_CONTROL_REG 0x6808 1154 #define MLCR_PCI_CTRL_SELECT 0x10000000 1155 #define MLCR_LEGACY_PCI_MODE 0x08000000 1156 #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000 1157 #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000 1158 #define MLCR_SSRAM_TYPE 0x00400000 1159 #define MLCR_BANK_SELECT 0x00200000 1160 #define MLCR_SRAM_SIZE_MASK 0x001c0000 1161 #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000 1162 1163 #define MLCR_MISC_PINS_OUTPUT_2 0x00010000 1164 #define MLCR_MISC_PINS_OUTPUT_1 0x00008000 1165 #define MLCR_MISC_PINS_OUTPUT_0 0x00004000 1166 #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000 1167 #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000 1168 #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800 1169 #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */ 1170 #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */ 1171 #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */ 1172 1173 #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */ 1174 #define MLCR_SET_INT 0x00000004 /* W/O */ 1175 #define MLCR_CLR_INT 0x00000002 /* W/O */ 1176 #define MLCR_INTA_STATE 0x00000001 /* R/O */ 1177 1178 /* 1179 * This value defines all GPIO bits as INPUTS, but sets their default 1180 * values as outputs to HIGH, on the assumption that external circuits 1181 * (if any) will probably be active-LOW with passive pullups. 1182 * 1183 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in 1184 * just this fashion. It has to be set as an OUTPUT and driven LOW to 1185 * enable writing. Otherwise, the SEEPROM is protected. 1186 */ 1187 #define MLCR_DEFAULT 0x0101c000 1188 #define MLCR_DEFAULT_5714 0x1901c000 1189 1190 /* 1191 * Serial EEPROM Data/Address Registers (auto-access mode) 1192 */ 1193 #define SERIAL_EEPROM_DATA_REG 0x683c 1194 #define SERIAL_EEPROM_ADDRESS_REG 0x6838 1195 #define SEEPROM_ACCESS_READ 0x80000000 1196 #define SEEPROM_ACCESS_WRITE 0x00000000 1197 #define SEEPROM_ACCESS_COMPLETE 0x40000000 1198 #define SEEPROM_ACCESS_RESET 0x20000000 1199 #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000 1200 #define SEEPROM_ACCESS_START 0x02000000 1201 #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000 1202 #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc 1203 1204 #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */ 1205 #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */ 1206 #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */ 1207 1208 #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */ 1209 #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */ 1210 1211 /* 1212 * "Linearised" address mask, treating multiple devices as consecutive 1213 */ 1214 #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */ 1215 1216 /* 1217 * Non-Volatile Memory Interface Registers 1218 * Note: on chips that support the flash interface (5702+), flash is the 1219 * default and the legacy seeprom interface must be explicitly enabled 1220 * if required. On older chips (5700/01), SEEPROM is the default (and 1221 * only) non-volatile memory available, and these registers don't exist! 1222 */ 1223 #define NVM_FLASH_CMD_REG 0x7000 1224 #define NVM_FLASH_CMD_LAST 0x00000100 1225 #define NVM_FLASH_CMD_FIRST 0x00000080 1226 #define NVM_FLASH_CMD_RD 0x00000000 1227 #define NVM_FLASH_CMD_WR 0x00000020 1228 #define NVM_FLASH_CMD_DOIT 0x00000010 1229 #define NVM_FLASH_CMD_DONE 0x00000008 1230 1231 #define NVM_FLASH_WRITE_REG 0x7008 1232 #define NVM_FLASH_READ_REG 0x7010 1233 1234 #define NVM_FLASH_ADDR_REG 0x700c 1235 #define NVM_FLASH_ADDR_MASK 0x00fffffc 1236 1237 #define NVM_CONFIG1_REG 0x7014 1238 #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000 1239 #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800 1240 #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780 1241 #define NVM_CFG1_BUFFERED_MODE 0x00000002 1242 #define NVM_CFG1_FLASH_MODE 0x00000001 1243 1244 #define NVM_SW_ARBITRATION_REG 0x7020 1245 #define NVM_READ_REQ3 0X00008000 1246 #define NVM_READ_REQ2 0X00004000 1247 #define NVM_READ_REQ1 0X00002000 1248 #define NVM_READ_REQ0 0X00001000 1249 #define NVM_WON_REQ3 0X00000800 1250 #define NVM_WON_REQ2 0X00000400 1251 #define NVM_WON_REQ1 0X00000200 1252 #define NVM_WON_REQ0 0X00000100 1253 #define NVM_RESET_REQ3 0X00000080 1254 #define NVM_RESET_REQ2 0X00000040 1255 #define NVM_RESET_REQ1 0X00000020 1256 #define NVM_RESET_REQ0 0X00000010 1257 #define NVM_SET_REQ3 0X00000008 1258 #define NVM_SET_REQ2 0X00000004 1259 #define NVM_SET_REQ1 0X00000002 1260 #define NVM_SET_REQ0 0X00000001 1261 1262 /* 1263 * NVM access register 1264 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714 1265 * and BCM5715 only. 1266 */ 1267 #define NVM_ACCESS_REG 0X7024 1268 #define NVM_WRITE_ENABLE 0X00000002 1269 #define NVM_ACCESS_ENABLE 0X00000001 1270 1271 /* 1272 * TLP Control Register 1273 * Applicable to BCM5721 and BCM5751 only 1274 */ 1275 #define TLP_CONTROL_REG 0x7c00 1276 #define TLP_DATA_FIFO_PROTECT 0x02000000 1277 1278 /* 1279 * PHY Test Control Register 1280 * Applicable to BCM5721 and BCM5751 only 1281 */ 1282 #define PHY_TEST_CTRL_REG 0x7e2c 1283 #define PHY_PCIE_SCRAM_MODE 0x20 1284 #define PHY_PCIE_LTASS_MODE 0x40 1285 1286 /* 1287 * The internal firmware expects a certain layout of the non-volatile 1288 * memory (if fitted), and will check for it during startup, and use the 1289 * contents to initialise various internal parameters if it looks good. 1290 * 1291 * The offsets and field definitions below refer to where to find some 1292 * important values, and how to interpret them ... 1293 */ 1294 #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */ 1295 1296 /* 1297 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 1298 */ 1299 1300 #define MII_AN_LPNXTPG 8 1301 #define MII_1000BASE_T_CONTROL 9 1302 #define MII_1000BASE_T_STATUS 10 1303 #define MII_IEEE_EXT_STATUS 15 1304 1305 /* 1306 * New bits in the MII_CONTROL register 1307 */ 1308 #define MII_CONTROL_1000MB 0x0040 1309 1310 /* 1311 * New bits in the MII_AN_ADVERT register 1312 */ 1313 #define MII_ABILITY_ASYM_PAUSE 0x0800 1314 #define MII_ABILITY_PAUSE 0x0400 1315 1316 /* 1317 * Values for the <selector> field of the MII_AN_ADVERT register 1318 */ 1319 #define MII_AN_SELECTOR_8023 0x0001 1320 1321 /* 1322 * Bits in the MII_1000BASE_T_CONTROL register 1323 * 1324 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 1325 * (otherwise, roles are automatically negotiated). When this bit is set, 1326 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 1327 */ 1328 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 1329 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 1330 #define MII_1000BT_CTL_ADV_FDX 0x0200 1331 #define MII_1000BT_CTL_ADV_HDX 0x0100 1332 1333 /* 1334 * Bits in the MII_1000BASE_T_STATUS register 1335 */ 1336 #define MII_1000BT_STAT_MASTER_FAULT 0x8000 1337 #define MII_1000BT_STAT_MASTER_MODE 0x4000 /* shows role selected */ 1338 #define MII_1000BT_STAT_LCL_RCV_OK 0x2000 1339 #define MII_1000BT_STAT_RMT_RCV_OK 0x1000 1340 #define MII_1000BT_STAT_LP_FDX_CAP 0x0800 1341 #define MII_1000BT_STAT_LP_HDX_CAP 0x0400 1342 1343 /* 1344 * Vendor-specific MII registers 1345 */ 1346 #define MII_EXT_CONTROL MII_VENDOR(0) 1347 #define MII_EXT_STATUS MII_VENDOR(1) 1348 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 1349 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 1350 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 1351 #define MII_AUX_CONTROL MII_VENDOR(8) 1352 #define MII_AUX_STATUS MII_VENDOR(9) 1353 #define MII_INTR_STATUS MII_VENDOR(10) 1354 #define MII_INTR_MASK MII_VENDOR(11) 1355 #define MII_HCD_STATUS MII_VENDOR(13) 1356 1357 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 1358 1359 /* 1360 * Bits in the MII_EXT_CONTROL register 1361 */ 1362 #define MII_EXT_CTRL_INTERFACE_TBI 0x8000 1363 #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000 1364 #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000 1365 #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000 1366 #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800 1367 #define MII_EXT_CTRL_BYPASS_4B5B 0x0400 1368 #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200 1369 #define MII_EXT_CTRL_BYPASS_MLT3 0x0100 1370 #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080 1371 #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040 1372 #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020 1373 #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010 1374 #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008 1375 #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004 1376 #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002 1377 #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001 1378 1379 /* 1380 * Bits in the MII_EXT_STATUS register 1381 */ 1382 #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000 1383 #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000 1384 #define MII_EXT_STAT_MDIX_STATE 0x2000 1385 #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000 1386 #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800 1387 #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400 1388 #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200 1389 #define MII_EXT_STAT_LINK_STATUS 0x0100 1390 #define MII_EXT_STAT_CRC_ERROR 0x0080 1391 #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040 1392 #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020 1393 #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010 1394 #define MII_EXT_STAT_RECEIVE_ERROR 0x0008 1395 #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004 1396 #define MII_EXT_STAT_LOCK_ERROR 0x0002 1397 #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001 1398 1399 /* 1400 * The AUX CONTROL register is seriously weird! 1401 * 1402 * It hides (up to) eight 'shadow' registers. When writing, which one 1403 * of them is written is determined by the low-order bits of the data 1404 * written(!), but when reading, which one is read is determined by the 1405 * value previously written to (part of) one of the shadow registers!!! 1406 */ 1407 1408 /* 1409 * Shadow register numbers 1410 */ 1411 #define MII_AUX_CTRL_NORMAL 0 1412 #define MII_AUX_CTRL_10BASE_T 1 1413 #define MII_AUX_CTRL_POWER 2 1414 #define MII_AUX_CTRL_TEST_1 4 1415 #define MII_AUX_CTRL_MISC 7 1416 1417 /* 1418 * Selected bits in some of the shadow registers ... 1419 */ 1420 #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000 1421 #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000 1422 #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000 1423 #define MII_AUX_CTRL_NORM_TX_MODE 0x0400 1424 #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008 1425 1426 #define MII_AUX_CTRL_TEST_TX_HALF 0x0008 1427 1428 #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000 1429 #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010 1430 1431 /* 1432 * Write this value to the AUX control register 1433 * to select which shadow register will be read 1434 */ 1435 #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC) 1436 1437 /* 1438 * Bits in the MII_AUX_STATUS register 1439 */ 1440 #define MII_AUX_STATUS_MODE_MASK 0x0700 1441 #define MII_AUX_STATUS_MODE_1000_F 0x0700 1442 #define MII_AUX_STATUS_MODE_1000_H 0x0600 1443 #define MII_AUX_STATUS_MODE_100_F 0x0500 1444 #define MII_AUX_STATUS_MODE_100_4 0x0400 1445 #define MII_AUX_STATUS_MODE_100_H 0x0300 1446 #define MII_AUX_STATUS_MODE_10_F 0x0200 1447 #define MII_AUX_STATUS_MODE_10_H 0x0100 1448 #define MII_AUX_STATUS_MODE_NONE 0x0000 1449 #define MII_AUX_STATUS_MODE_SHIFT 8 1450 1451 #define MII_AUX_STATUS_PAR_FAULT 0x0080 1452 #define MII_AUX_STATUS_REM_FAULT 0x0040 1453 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 1454 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 1455 1456 #define MII_AUX_STATUS_LINKUP 0x0004 1457 #define MII_AUX_STATUS_RX_PAUSE 0x0002 1458 #define MII_AUX_STATUS_TX_PAUSE 0x0001 1459 1460 /* 1461 * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers 1462 */ 1463 #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020 1464 #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010 1465 #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008 1466 #define MII_INTR_LINK_SPEED_CHANGE 0x0004 1467 #define MII_INTR_LINK_STATUS_CHANGE 0x0002 1468 1469 1470 /* 1471 * Third section: 1472 * Hardware-defined data structures 1473 * 1474 * Note that the chip is naturally BIG-endian, so, for a big-endian 1475 * host, the structures defined below match those described in the PRM. 1476 * For little-endian hosts, some structures have to be swapped around. 1477 */ 1478 1479 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 1480 #error Host endianness not defined 1481 #endif 1482 1483 /* 1484 * Architectural constants: absolute maximum numbers of each type of ring 1485 */ 1486 #ifdef BGE_EXT_MEM 1487 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */ 1488 #else 1489 #define BGE_SEND_RINGS_MAX 4 1490 #endif 1491 #define BGE_SEND_RINGS_MAX_5705 1 1492 #define BGE_RECV_RINGS_MAX 16 1493 #define BGE_RECV_RINGS_MAX_5705 1 1494 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */ 1495 /* only with ext mem) */ 1496 1497 #define BGE_SEND_SLOTS_MAX 512 1498 #define BGE_STD_SLOTS_MAX 512 1499 #define BGE_JUMBO_SLOTS_MAX 256 1500 #define BGE_MINI_SLOTS_MAX 1024 1501 #define BGE_RECV_SLOTS_MAX 2048 1502 #define BGE_RECV_SLOTS_5705 512 1503 #define BGE_RECV_SLOTS_5782 512 1504 #define BGE_RECV_SLOTS_5721 512 1505 1506 /* 1507 * Hardware-defined Ring Control Block 1508 */ 1509 typedef struct { 1510 uint64_t host_ring_addr; 1511 #ifdef _BIG_ENDIAN 1512 uint16_t max_len; 1513 uint16_t flags; 1514 uint32_t nic_ring_addr; 1515 #else 1516 uint32_t nic_ring_addr; 1517 uint16_t flags; 1518 uint16_t max_len; 1519 #endif /* _BIG_ENDIAN */ 1520 } bge_rcb_t; 1521 1522 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001 1523 #define RCB_FLAG_RING_DISABLED 0x0002 1524 1525 /* 1526 * Hardware-defined Send Buffer Descriptor 1527 */ 1528 typedef struct { 1529 uint64_t host_buf_addr; 1530 #ifdef _BIG_ENDIAN 1531 uint16_t len; 1532 uint16_t flags; 1533 uint16_t reserved; 1534 uint16_t vlan_tci; 1535 #else 1536 uint16_t vlan_tci; 1537 uint16_t reserved; 1538 uint16_t flags; 1539 uint16_t len; 1540 #endif /* _BIG_ENDIAN */ 1541 } bge_sbd_t; 1542 1543 #define SBD_FLAG_TCP_UDP_CKSUM 0x0001 1544 #define SBD_FLAG_IP_CKSUM 0x0002 1545 #define SBD_FLAG_PACKET_END 0x0004 1546 #define SBD_FLAG_IP_FRAG 0x0008 1547 #define SBD_FLAG_IP_FRAG_END 0x0010 1548 1549 #define SBD_FLAG_VLAN_TAG 0x0040 1550 #define SBD_FLAG_COAL_NOW 0x0080 1551 #define SBD_FLAG_CPU_PRE_DMA 0x0100 1552 #define SBD_FLAG_CPU_POST_DMA 0x0200 1553 1554 #define SBD_FLAG_INSERT_SRC_ADDR 0x1000 1555 #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000 1556 #define SBD_FLAG_DONT_GEN_CRC 0x8000 1557 1558 /* 1559 * Hardware-defined Receive Buffer Descriptor 1560 */ 1561 typedef struct { 1562 uint64_t host_buf_addr; 1563 #ifdef _BIG_ENDIAN 1564 uint16_t index; 1565 uint16_t len; 1566 uint16_t type; 1567 uint16_t flags; 1568 uint16_t ip_cksum; 1569 uint16_t tcp_udp_cksum; 1570 uint16_t error_flag; 1571 uint16_t vlan_tci; 1572 uint32_t reserved; 1573 uint32_t opaque; 1574 #else 1575 uint16_t flags; 1576 uint16_t type; 1577 uint16_t len; 1578 uint16_t index; 1579 uint16_t vlan_tci; 1580 uint16_t error_flag; 1581 uint16_t tcp_udp_cksum; 1582 uint16_t ip_cksum; 1583 uint32_t opaque; 1584 uint32_t reserved; 1585 #endif /* _BIG_ENDIAN */ 1586 } bge_rbd_t; 1587 1588 #define RBD_FLAG_STD_RING 0x0000 1589 #define RBD_FLAG_PACKET_END 0x0004 1590 1591 #define RBD_FLAG_JUMBO_RING 0x0020 1592 #define RBD_FLAG_VLAN_TAG 0x0040 1593 1594 #define RBD_FLAG_FRAME_HAS_ERROR 0x0400 1595 #define RBD_FLAG_MINI_RING 0x0800 1596 #define RBD_FLAG_IP_CHECKSUM 0x1000 1597 #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000 1598 #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000 1599 1600 #define RBD_FLAG_DEFAULT 0x0000 1601 1602 #define RBD_ERROR_BAD_CRC 0x00010000 1603 #define RBD_ERROR_COLL_DETECT 0x00020000 1604 #define RBD_ERROR_LINK_LOST 0x00040000 1605 #define RBD_ERROR_PHY_DECODE_ERR 0x00080000 1606 #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000 1607 #define RBD_ERROR_MAC_ABORT 0x00200000 1608 #define RBD_ERROR_LEN_LESS_64 0x00400000 1609 #define RBD_ERROR_TRUNC_NO_RES 0x00800000 1610 #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000 1611 1612 /* 1613 * Hardware-defined Status Block,Size of status block 1614 * is actually 0x50 bytes.Use 0x80 bytes for cache line 1615 * alignment.For BCM5705/5788/5721/5751/5752/5714 1616 * and 5715,there is only 1 recv and send ring index,but 1617 * driver defined 16 indexs here,please pay attention only 1618 * one ring is enabled in these chipsets. 1619 */ 1620 typedef struct { 1621 uint64_t flags_n_tag; 1622 uint16_t buff_cons_index[4]; 1623 struct { 1624 #ifdef _BIG_ENDIAN 1625 uint16_t send_cons_index; 1626 uint16_t recv_prod_index; 1627 #else 1628 uint16_t recv_prod_index; 1629 uint16_t send_cons_index; 1630 #endif /* _BIG_ENDIAN */ 1631 } index[16]; 1632 } bge_status_t; 1633 1634 /* 1635 * Hardware-defined Receive BD Rule 1636 */ 1637 typedef struct { 1638 uint32_t control; 1639 uint32_t mask_value; 1640 } bge_recv_rule_t; 1641 1642 /* 1643 * Indexes into the <buff_cons_index> array 1644 */ 1645 #ifdef _BIG_ENDIAN 1646 #define STATUS_STD_BUFF_CONS_INDEX 0 1647 #define STATUS_JUMBO_BUFF_CONS_INDEX 1 1648 #define STATUS_MINI_BUFF_CONS_INDEX 3 1649 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index) 1650 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index) 1651 #else 1652 #define STATUS_STD_BUFF_CONS_INDEX 3 1653 #define STATUS_JUMBO_BUFF_CONS_INDEX 2 1654 #define STATUS_MINI_BUFF_CONS_INDEX 0 1655 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index) 1656 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index) 1657 #endif /* _BIG_ENDIAN */ 1658 1659 /* 1660 * Bits in the <flags_n_tag> word 1661 */ 1662 #define STATUS_FLAG_UPDATED 0x0000000100000000ull 1663 #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull 1664 #define STATUS_FLAG_ERROR 0x0000000400000000ull 1665 #define STATUS_TAG_MASK 0x00000000000000FFull 1666 1667 /* 1668 * The tag from the status block is fed back to Interrupt Mailbox 0 1669 * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This 1670 * lets the chip know what updates have been processed, so it can 1671 * reassert its interrupt if more updates have occurred since. 1672 * 1673 * These macros extract the tag from the <flags_n_tag> word, shift 1674 * it to the proper position in the Mailbox register, and provide 1675 * the complete values to write to INTERRUPT_MBOX_0_REG to disable 1676 * or enable interrupts 1677 */ 1678 #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK) 1679 #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24) 1680 #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1) 1681 #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0) 1682 1683 /* 1684 * Hardware-defined Statistics Block Offsets 1685 * 1686 * These are given in the manual as addresses in NIC memory, starting 1687 * from the NIC statistics area base address of 0x300; but here we 1688 * convert them into indexes into an array of (uint64_t)s, so we can 1689 * use them directly for accessing the copy of the statistics block 1690 * that the chip DMAs into main memory ... 1691 */ 1692 1693 #define KS_BASE 0x300 1694 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t)) 1695 1696 typedef enum { 1697 KS_ifHCInOctets = KS_ADDR(0x400), 1698 KS_etherStatsFragments = KS_ADDR(0x410), 1699 KS_ifHCInUcastPkts, 1700 KS_ifHCInMulticastPkts, 1701 KS_ifHCInBroadcastPkts, 1702 KS_dot3StatsFCSErrors, 1703 KS_dot3StatsAlignmentErrors, 1704 KS_xonPauseFramesReceived, 1705 KS_xoffPauseFramesReceived, 1706 KS_macControlFramesReceived, 1707 KS_xoffStateEntered, 1708 KS_dot3StatsFrameTooLongs, 1709 KS_etherStatsJabbers, 1710 KS_etherStatsUndersizePkts, 1711 KS_inRangeLengthError, 1712 KS_outRangeLengthError, 1713 KS_etherStatsPkts64Octets, 1714 KS_etherStatsPkts65to127Octets, 1715 KS_etherStatsPkts128to255Octets, 1716 KS_etherStatsPkts256to511Octets, 1717 KS_etherStatsPkts512to1023Octets, 1718 KS_etherStatsPkts1024to1518Octets, 1719 KS_etherStatsPkts1519to2047Octets, 1720 KS_etherStatsPkts2048to4095Octets, 1721 KS_etherStatsPkts4096to8191Octets, 1722 KS_etherStatsPkts8192to9022Octets, 1723 1724 KS_ifHCOutOctets = KS_ADDR(0x600), 1725 KS_etherStatsCollisions = KS_ADDR(0x610), 1726 KS_outXonSent, 1727 KS_outXoffSent, 1728 KS_flowControlDone, 1729 KS_dot3StatsInternalMacTransmitErrors, 1730 KS_dot3StatsSingleCollisionFrames, 1731 KS_dot3StatsMultipleCollisionFrames, 1732 KS_dot3StatsDeferredTransmissions, 1733 KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658), 1734 KS_dot3StatsLateCollisions, 1735 KS_dot3Collided2Times, 1736 KS_dot3Collided3Times, 1737 KS_dot3Collided4Times, 1738 KS_dot3Collided5Times, 1739 KS_dot3Collided6Times, 1740 KS_dot3Collided7Times, 1741 KS_dot3Collided8Times, 1742 KS_dot3Collided9Times, 1743 KS_dot3Collided10Times, 1744 KS_dot3Collided11Times, 1745 KS_dot3Collided12Times, 1746 KS_dot3Collided13Times, 1747 KS_dot3Collided14Times, 1748 KS_dot3Collided15Times, 1749 KS_ifHCOutUcastPkts, 1750 KS_ifHCOutMulticastPkts, 1751 KS_ifHCOutBroadcastPkts, 1752 KS_dot3StatsCarrierSenseErrors, 1753 KS_ifOutDiscards, 1754 KS_ifOutErrors, 1755 1756 KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */ 1757 KS_COSIfHCInPkts_2, 1758 KS_COSIfHCInPkts_3, 1759 KS_COSIfHCInPkts_4, 1760 KS_COSIfHCInPkts_5, 1761 KS_COSIfHCInPkts_6, 1762 KS_COSIfHCInPkts_7, 1763 KS_COSIfHCInPkts_8, 1764 KS_COSIfHCInPkts_9, 1765 KS_COSIfHCInPkts_10, 1766 KS_COSIfHCInPkts_11, 1767 KS_COSIfHCInPkts_12, 1768 KS_COSIfHCInPkts_13, 1769 KS_COSIfHCInPkts_14, 1770 KS_COSIfHCInPkts_15, 1771 KS_COSIfHCInPkts_16, 1772 KS_COSFramesDroppedDueToFilters, 1773 KS_nicDmaWriteQueueFull, 1774 KS_nicDmaWriteHighPriQueueFull, 1775 KS_nicNoMoreRxBDs, 1776 KS_ifInDiscards, 1777 KS_ifInErrors, 1778 KS_nicRecvThresholdHit, 1779 1780 KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */ 1781 KS_COSIfHCOutPkts_2, 1782 KS_COSIfHCOutPkts_3, 1783 KS_COSIfHCOutPkts_4, 1784 KS_COSIfHCOutPkts_5, 1785 KS_COSIfHCOutPkts_6, 1786 KS_COSIfHCOutPkts_7, 1787 KS_COSIfHCOutPkts_8, 1788 KS_COSIfHCOutPkts_9, 1789 KS_COSIfHCOutPkts_10, 1790 KS_COSIfHCOutPkts_11, 1791 KS_COSIfHCOutPkts_12, 1792 KS_COSIfHCOutPkts_13, 1793 KS_COSIfHCOutPkts_14, 1794 KS_COSIfHCOutPkts_15, 1795 KS_COSIfHCOutPkts_16, 1796 KS_nicDmaReadQueueFull, 1797 KS_nicDmaReadHighPriQueueFull, 1798 KS_nicSendDataCompQueueFull, 1799 KS_nicRingSetSendProdIndex, 1800 KS_nicRingStatusUpdate, 1801 KS_nicInterrupts, 1802 KS_nicAvoidedInterrupts, 1803 KS_nicSendThresholdHit, 1804 1805 KS_STATS_SIZE = KS_ADDR(0xb00) 1806 } bge_stats_offset_t; 1807 1808 /* 1809 * Hardware-defined Statistics Block 1810 * 1811 * Another view of the statistic block, as a array and a structure ... 1812 */ 1813 1814 typedef union { 1815 uint64_t a[KS_STATS_SIZE]; 1816 struct { 1817 uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)]; 1818 1819 uint64_t ifHCInOctets; /* 0x0400 */ 1820 uint64_t spare2[1]; 1821 uint64_t etherStatsFragments; 1822 uint64_t ifHCInUcastPkts; 1823 uint64_t ifHCInMulticastPkts; 1824 uint64_t ifHCInBroadcastPkts; 1825 uint64_t dot3StatsFCSErrors; 1826 uint64_t dot3StatsAlignmentErrors; 1827 uint64_t xonPauseFramesReceived; 1828 uint64_t xoffPauseFramesReceived; 1829 uint64_t macControlFramesReceived; 1830 uint64_t xoffStateEntered; 1831 uint64_t dot3StatsFrameTooLongs; 1832 uint64_t etherStatsJabbers; 1833 uint64_t etherStatsUndersizePkts; 1834 uint64_t inRangeLengthError; 1835 uint64_t outRangeLengthError; 1836 uint64_t etherStatsPkts64Octets; 1837 uint64_t etherStatsPkts65to127Octets; 1838 uint64_t etherStatsPkts128to255Octets; 1839 uint64_t etherStatsPkts256to511Octets; 1840 uint64_t etherStatsPkts512to1023Octets; 1841 uint64_t etherStatsPkts1024to1518Octets; 1842 uint64_t etherStatsPkts1519to2047Octets; 1843 uint64_t etherStatsPkts2048to4095Octets; 1844 uint64_t etherStatsPkts4096to8191Octets; 1845 uint64_t etherStatsPkts8192to9022Octets; 1846 uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)]; 1847 1848 uint64_t ifHCOutOctets; /* 0x0600 */ 1849 uint64_t spare4[1]; 1850 uint64_t etherStatsCollisions; 1851 uint64_t outXonSent; 1852 uint64_t outXoffSent; 1853 uint64_t flowControlDone; 1854 uint64_t dot3StatsInternalMacTransmitErrors; 1855 uint64_t dot3StatsSingleCollisionFrames; 1856 uint64_t dot3StatsMultipleCollisionFrames; 1857 uint64_t dot3StatsDeferredTransmissions; 1858 uint64_t spare5[1]; 1859 uint64_t dot3StatsExcessiveCollisions; 1860 uint64_t dot3StatsLateCollisions; 1861 uint64_t dot3Collided2Times; 1862 uint64_t dot3Collided3Times; 1863 uint64_t dot3Collided4Times; 1864 uint64_t dot3Collided5Times; 1865 uint64_t dot3Collided6Times; 1866 uint64_t dot3Collided7Times; 1867 uint64_t dot3Collided8Times; 1868 uint64_t dot3Collided9Times; 1869 uint64_t dot3Collided10Times; 1870 uint64_t dot3Collided11Times; 1871 uint64_t dot3Collided12Times; 1872 uint64_t dot3Collided13Times; 1873 uint64_t dot3Collided14Times; 1874 uint64_t dot3Collided15Times; 1875 uint64_t ifHCOutUcastPkts; 1876 uint64_t ifHCOutMulticastPkts; 1877 uint64_t ifHCOutBroadcastPkts; 1878 uint64_t dot3StatsCarrierSenseErrors; 1879 uint64_t ifOutDiscards; 1880 uint64_t ifOutErrors; 1881 uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)]; 1882 1883 uint64_t COSIfHCInPkts[16]; /* 0x0800 */ 1884 uint64_t COSFramesDroppedDueToFilters; 1885 uint64_t nicDmaWriteQueueFull; 1886 uint64_t nicDmaWriteHighPriQueueFull; 1887 uint64_t nicNoMoreRxBDs; 1888 uint64_t ifInDiscards; 1889 uint64_t ifInErrors; 1890 uint64_t nicRecvThresholdHit; 1891 uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)]; 1892 1893 uint64_t COSIfHCOutPkts[16]; /* 0x0900 */ 1894 uint64_t nicDmaReadQueueFull; 1895 uint64_t nicDmaReadHighPriQueueFull; 1896 uint64_t nicSendDataCompQueueFull; 1897 uint64_t nicRingSetSendProdIndex; 1898 uint64_t nicRingStatusUpdate; 1899 uint64_t nicInterrupts; 1900 uint64_t nicAvoidedInterrupts; 1901 uint64_t nicSendThresholdHit; 1902 uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)]; 1903 } s; 1904 } bge_statistics_t; 1905 1906 #define KS_STAT_REG_SIZE (0x1B) 1907 #define KS_STAT_REG_BASE (0x800) 1908 1909 typedef struct { 1910 uint32_t ifHCOutOctets; 1911 uint32_t etherStatsCollisions; 1912 uint32_t outXonSent; 1913 uint32_t outXoffSent; 1914 uint32_t dot3StatsInternalMacTransmitErrors; 1915 uint32_t dot3StatsSingleCollisionFrames; 1916 uint32_t dot3StatsMultipleCollisionFrames; 1917 uint32_t dot3StatsDeferredTransmissions; 1918 uint32_t dot3StatsExcessiveCollisions; 1919 uint32_t dot3StatsLateCollisions; 1920 uint32_t ifHCOutUcastPkts; 1921 uint32_t ifHCOutMulticastPkts; 1922 uint32_t ifHCOutBroadcastPkts; 1923 uint32_t ifHCInOctets; 1924 uint32_t etherStatsFragments; 1925 uint32_t ifHCInUcastPkts; 1926 uint32_t ifHCInMulticastPkts; 1927 uint32_t ifHCInBroadcastPkts; 1928 uint32_t dot3StatsFCSErrors; 1929 uint32_t dot3StatsAlignmentErrors; 1930 uint32_t xonPauseFramesReceived; 1931 uint32_t xoffPauseFramesReceived; 1932 uint32_t macControlFramesReceived; 1933 uint32_t xoffStateEntered; 1934 uint32_t dot3StatsFrameTooLongs; 1935 uint32_t etherStatsJabbers; 1936 uint32_t etherStatsUndersizePkts; 1937 } bge_statistics_reg_t; 1938 1939 1940 #ifdef BGE_IPMI_ASF 1941 1942 /* 1943 * Device internal memory entries 1944 */ 1945 1946 #define BGE_FIRMWARE_MAILBOX 0x0b50 1947 #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654 1948 #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b 1949 1950 1951 #define BGE_NIC_DATA_SIG_ADDR 0x0b54 1952 #define BGE_NIC_DATA_SIG 0x4b657654 1953 1954 1955 #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58 1956 1957 #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004 1958 #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008 1959 #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004 1960 #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008 1961 #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c 1962 1963 #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000 1964 #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010 1965 #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020 1966 #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030 1967 1968 #define BGE_NIC_CFG_ENABLE_WOL 0x000040 1969 #define BGE_NIC_CFG_ENABLE_ASF 0x000080 1970 #define BGE_NIC_CFG_EEPROM_WP 0x000100 1971 #define BGE_NIC_CFG_POWER_SAVING 0x000200 1972 #define BGE_NIC_CFG_SWAP_PORT 0x000800 1973 #define BGE_NIC_CFG_MINI_PCI 0x001000 1974 #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000 1975 #define BGE_NIC_CFG_5753_12x12 0x100000 1976 1977 1978 #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c 1979 1980 1981 #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74 1982 #define BGE_NIC_PHY_ID1_MASK 0xffff0000 1983 #define BGE_NIC_PHY_ID2_MASK 0x0000ffff 1984 1985 1986 #define BGE_CMD_MAILBOX 0x0b78 1987 #define BGE_CMD_NICDRV_ALIVE 0x00000001 1988 #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002 1989 #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003 1990 #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004 1991 1992 1993 #define BGE_CMD_LENGTH_MAILBOX 0x0b7c 1994 #define BGE_CMD_DATA_MAILBOX 0x0b80 1995 #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00 1996 1997 #define BGE_DRV_STATE_MAILBOX 0x0c04 1998 #define BGE_DRV_STATE_START 0x00000001 1999 #define BGE_DRV_STATE_START_DONE 0x80000001 2000 #define BGE_DRV_STATE_UNLOAD 0x00000002 2001 #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002 2002 #define BGE_DRV_STATE_WOL 0x00000003 2003 #define BGE_DRV_STATE_SUSPEND 0x00000004 2004 2005 2006 #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08 2007 #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001 2008 #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002 2009 2010 2011 #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14 2012 #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18 2013 2014 2015 /* 2016 * RX-RISC event register 2017 */ 2018 #define RX_RISC_EVENT_REG 0x6810 2019 #define RRER_ASF_EVENT 0x4000 2020 2021 #endif /* BGE_IPMI_ASF */ 2022 2023 #ifdef __cplusplus 2024 } 2025 #endif 2026 2027 #endif /* _BGE_HW_H */ 2028