1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_BGE_HW_H 28 #define _SYS_BGE_HW_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 38 39 /* 40 * First section: 41 * Identification of the various Broadcom chips 42 * 43 * Note: the various ID values are *not* all unique ;-( 44 * 45 * Note: the presence of an ID here does *not* imply that the chip is 46 * supported. At this time, only the 5703C, 5704C, and 5704S devices 47 * used on the motherboards of certain Sun products are supported. 48 * 49 * Note: the revision-id values in the PCI revision ID register are 50 * *NOT* guaranteed correct. Use the chip ID from the MHCR instead. 51 */ 52 53 #define VENDOR_ID_BROADCOM 0x14e4 54 #define VENDOR_ID_SUN 0x108e 55 56 #define DEVICE_ID_5700 0x1644 57 #define DEVICE_ID_5700x 0x0003 58 #define DEVICE_ID_5701 0x1645 59 #define DEVICE_ID_5702 0x16a6 60 #define DEVICE_ID_5702fe 0x164d 61 #define DEVICE_ID_5703C 0x1647 62 #define DEVICE_ID_5703S 0x16a7 63 #define DEVICE_ID_5703 0x16c7 64 #define DEVICE_ID_5704C 0x1648 65 #define DEVICE_ID_5704S 0x16a8 66 #define DEVICE_ID_5704 0x1649 67 #define DEVICE_ID_5705C 0x1653 68 #define DEVICE_ID_5705M 0x165d 69 #define DEVICE_ID_5705MA3 0x165e 70 #define DEVICE_ID_5705F 0x166e 71 #define DEVICE_ID_5706 0x164a 72 #define DEVICE_ID_5782 0x1696 73 #define DEVICE_ID_5788 0x169c 74 #define DEVICE_ID_5789 0x169d 75 #define DEVICE_ID_5751 0x1677 76 #define DEVICE_ID_5751M 0x167d 77 #define DEVICE_ID_5752 0x1600 78 #define DEVICE_ID_5752M 0x1601 79 #define DEVICE_ID_5721 0x1659 80 #define DEVICE_ID_5714C 0x1668 81 #define DEVICE_ID_5714S 0x1669 82 #define DEVICE_ID_5715C 0x1678 83 84 #define REVISION_ID_5700_B0 0x10 85 #define REVISION_ID_5700_B2 0x12 86 #define REVISION_ID_5700_B3 0x13 87 #define REVISION_ID_5700_C0 0x20 88 #define REVISION_ID_5700_C1 0x21 89 #define REVISION_ID_5700_C2 0x22 90 91 #define REVISION_ID_5701_A0 0x08 92 #define REVISION_ID_5701_A2 0x12 93 #define REVISION_ID_5701_A3 0x15 94 95 #define REVISION_ID_5702_A0 0x00 96 97 #define REVISION_ID_5703_A0 0x00 98 #define REVISION_ID_5703_A1 0x01 99 #define REVISION_ID_5703_A2 0x02 100 101 #define REVISION_ID_5704_A0 0x00 102 #define REVISION_ID_5704_A1 0x01 103 #define REVISION_ID_5704_A2 0x02 104 #define REVISION_ID_5704_A3 0x03 105 #define REVISION_ID_5704_B0 0x10 106 107 #define REVISION_ID_5705_A0 0x00 108 #define REVISION_ID_5705_A1 0x01 109 #define REVISION_ID_5705_A2 0x02 110 #define REVISION_ID_5705_A3 0x03 111 112 #define REVISION_ID_5721_A0 0x00 113 #define REVISION_ID_5721_A1 0x01 114 115 #define REVISION_ID_5751_A0 0x00 116 #define REVISION_ID_5751_A1 0x01 117 118 #define REVISION_ID_5714_A0 0x00 119 #define REVISION_ID_5714_A1 0x01 120 #define REVISION_ID_5714_A2 0xA2 121 #define REVISION_ID_5714_A3 0xA3 122 123 #define REVISION_ID_5715_A0 0x00 124 #define REVISION_ID_5715_A1 0x01 125 #define REVISION_ID_5715_A2 0xA2 126 127 #define DEVICE_5704_SERIES_CHIPSETS(bgep)\ 128 ((bgep->chipid.device == DEVICE_ID_5700) ||\ 129 (bgep->chipid.device == DEVICE_ID_5701) ||\ 130 (bgep->chipid.device == DEVICE_ID_5702) ||\ 131 (bgep->chipid.device == DEVICE_ID_5702fe)||\ 132 (bgep->chipid.device == DEVICE_ID_5703C) ||\ 133 (bgep->chipid.device == DEVICE_ID_5703S) ||\ 134 (bgep->chipid.device == DEVICE_ID_5703) ||\ 135 (bgep->chipid.device == DEVICE_ID_5704C) ||\ 136 (bgep->chipid.device == DEVICE_ID_5704S) ||\ 137 (bgep->chipid.device == DEVICE_ID_5704)) 138 139 #define DEVICE_5702_SERIES_CHIPSETS(bgep) \ 140 ((bgep->chipid.device == DEVICE_ID_5702) ||\ 141 (bgep->chipid.device == DEVICE_ID_5702fe)) 142 143 #define DEVICE_5705_SERIES_CHIPSETS(bgep) \ 144 ((bgep->chipid.device == DEVICE_ID_5705C) ||\ 145 (bgep->chipid.device == DEVICE_ID_5705M) ||\ 146 (bgep->chipid.device == DEVICE_ID_5705MA3) ||\ 147 (bgep->chipid.device == DEVICE_ID_5705F) ||\ 148 (bgep->chipid.device == DEVICE_ID_5782) ||\ 149 (bgep->chipid.device == DEVICE_ID_5788)) 150 151 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \ 152 ((bgep->chipid.device == DEVICE_ID_5721) ||\ 153 (bgep->chipid.device == DEVICE_ID_5751) ||\ 154 (bgep->chipid.device == DEVICE_ID_5751M) ||\ 155 (bgep->chipid.device == DEVICE_ID_5752) ||\ 156 (bgep->chipid.device == DEVICE_ID_5752M) ||\ 157 (bgep->chipid.device == DEVICE_ID_5789)) 158 159 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \ 160 ((bgep->chipid.device == DEVICE_ID_5714C) ||\ 161 (bgep->chipid.device == DEVICE_ID_5714S) ||\ 162 (bgep->chipid.device == DEVICE_ID_5715C)) 163 164 /* 165 * Second section: 166 * Offsets of important registers & definitions for bits therein 167 */ 168 169 /* 170 * PCI-X registers & bits 171 */ 172 #define PCIX_CONF_COMM 0x42 173 #define PCIX_COMM_RELAXED 0x0002 174 175 /* 176 * Miscellaneous Host Control Register, in PCI config space 177 */ 178 #define PCI_CONF_BGE_MHCR 0x68 179 #define MHCR_CHIP_REV_MASK 0xffff0000 180 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200 181 #define MHCR_MASK_INTERRUPT_MODE 0x00000100 182 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080 183 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040 184 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020 185 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010 186 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008 187 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004 188 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002 189 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001 190 191 #define MHCR_CHIP_REV_5700_B0 0x71000000 192 #define MHCR_CHIP_REV_5700_B2 0x71020000 193 #define MHCR_CHIP_REV_5700_B3 0x71030000 194 #define MHCR_CHIP_REV_5700_C0 0x72000000 195 #define MHCR_CHIP_REV_5700_C1 0x72010000 196 #define MHCR_CHIP_REV_5700_C2 0x72020000 197 198 #define MHCR_CHIP_REV_5701_A0 0x00000000 199 #define MHCR_CHIP_REV_5701_A2 0x00020000 200 #define MHCR_CHIP_REV_5701_A3 0x00030000 201 #define MHCR_CHIP_REV_5701_A5 0x01050000 202 203 #define MHCR_CHIP_REV_5702_A0 0x10000000 204 #define MHCR_CHIP_REV_5702_A1 0x10010000 205 #define MHCR_CHIP_REV_5702_A2 0x10020000 206 207 #define MHCR_CHIP_REV_5703_A0 0x10000000 208 #define MHCR_CHIP_REV_5703_A1 0x10010000 209 #define MHCR_CHIP_REV_5703_A2 0x10020000 210 #define MHCR_CHIP_REV_5703_B0 0x11000000 211 #define MHCR_CHIP_REV_5703_B1 0x11010000 212 213 #define MHCR_CHIP_REV_5704_A0 0x20000000 214 #define MHCR_CHIP_REV_5704_A1 0x20010000 215 #define MHCR_CHIP_REV_5704_A2 0x20020000 216 #define MHCR_CHIP_REV_5704_A3 0x20030000 217 #define MHCR_CHIP_REV_5704_B0 0x21000000 218 219 #define MHCR_CHIP_REV_5705_A0 0x30000000 220 #define MHCR_CHIP_REV_5705_A1 0x30010000 221 #define MHCR_CHIP_REV_5705_A2 0x30020000 222 #define MHCR_CHIP_REV_5705_A3 0x30030000 223 #define MHCR_CHIP_REV_5705_A5 0x30050000 224 225 #define MHCR_CHIP_REV_5782_A0 0x30030000 226 #define MHCR_CHIP_REV_5782_A1 0x30030088 227 228 #define MHCR_CHIP_REV_5788_A1 0x30050000 229 230 #define MHCR_CHIP_REV_5751_A0 0x40000000 231 #define MHCR_CHIP_REV_5751_A1 0x40010000 232 233 #define MHCR_CHIP_REV_5721_A0 0x41000000 234 #define MHCR_CHIP_REV_5721_A1 0x41010000 235 236 #define MHCR_CHIP_REV_5714_A0 0x50000000 237 #define MHCR_CHIP_REV_5714_A1 0x90010000 238 239 #define MHCR_CHIP_REV_5715_A0 0x50000000 240 #define MHCR_CHIP_REV_5715_A1 0x90010000 241 242 #define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000) 243 #define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28) 244 #define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28) 245 #define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28) 246 #define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28) 247 #define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28) 248 #define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28) 249 #define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28) 250 #define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28) 251 #define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28) 252 253 254 /* 255 * PCI DMA read/write Control Register, in PCI config space 256 * 257 * Note that several fields previously defined here have been deleted 258 * as they are not implemented in the 5703/4. 259 * 260 * Note: the value of this register is critical. It is possible to 261 * cause various unpleasant effects (DTOs, transaction deadlock, etc) 262 * by programming the wrong value. The value #defined below has been 263 * tested and shown to avoid all known problems. If it is to be changed, 264 * correct operation must be reverified on all supported platforms. 265 * 266 * In particular, we set both watermark fields to 2xCacheLineSize (128) 267 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions 268 * with Tomatillo's internal pipelines, that otherwise result in stalls, 269 * repeated retries, and DTOs. 270 */ 271 #define PCI_CONF_BGE_PDRWCR 0x6c 272 #define PDRWCR_RWCMD_MASK 0xFF000000 273 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000 274 #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000 275 #define PDRWCR_READ_WATERMARK_MASK 0x00070000 276 #define PDRWCR_CONCURRENCY_MASK 0x0000c000 277 #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000 278 #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000 279 #define PDRWCR_MIN_BEAT_MASK 0x000000ff 280 281 /* 282 * These are the actual values to be put into the fields shown above 283 */ 284 #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */ 285 #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */ 286 #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */ 287 #define PDRWCR_MIN_BEATS 0x00000000 288 289 #define PDRWCR_VAR_DEFAULT 0x761b0000 290 #define PDRWCR_VAR_5721 0x76180000 291 #define PDRWCR_VAR_5714 0x76148000 /* OR of above */ 292 #define PDRWCR_VAR_5715 0x76144000 /* OR of above */ 293 294 /* 295 * PCI State Register, in PCI config space 296 * 297 * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit 298 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW 299 */ 300 #define PCI_CONF_BGE_PCISTATE 0x70 301 #define PCISTATE_RETRY_SAME_DMA 0x00002000 302 #define PCISTATE_FLAT_VIEW 0x00000100 303 #define PCISTATE_EXT_ROM_RETRY 0x00000040 304 #define PCISTATE_EXT_ROM_ENABLE 0x00000020 305 #define PCISTATE_BUS_IS_32_BIT 0x00000010 306 #define PCISTATE_BUS_IS_FAST 0x00000008 307 #define PCISTATE_BUS_IS_PCI 0x00000004 308 #define PCISTATE_INTA_STATE 0x00000002 309 #define PCISTATE_FORCE_RESET 0x00000001 310 311 /* 312 * PCI Clock Control Register, in PCI config space 313 */ 314 #define PCI_CONF_BGE_CLKCTL 0x74 315 #define CLKCTL_PCIE_PLP_DISABLE 0x80000000 316 #define CLKCTL_PCIE_DLP_DISABLE 0x40000000 317 #define CLKCTL_PCIE_TLP_DISABLE 0x20000000 318 #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000 319 #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000 320 #define CLKCTL_PCIE_A0_FIX 0x00101000 321 322 /* 323 * Dual MAC Control Register, in PCI config space 324 */ 325 #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8 326 #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */ 327 #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */ 328 329 /* 330 * Register Indirect Access Address Register, 0x78 in PCI config 331 * space. Once this is set, accesses to the Register Indirect 332 * Access Data Register (0x80) refer to the register whose address 333 * is given by *this* register. This allows access to all the 334 * operating registers, while using only config space accesses. 335 * 336 * Note that the address written to the RIIAR should lie in one 337 * of the following ranges: 338 * 0x00000000 <= address < 0x00008000 (regular registers) 339 * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad) 340 * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad) 341 * 0x00038000 <= address < 0x00038800 (RxRISC ROM) 342 */ 343 #define PCI_CONF_BGE_RIAAR 0x78 344 #define PCI_CONF_BGE_RIADR 0x80 345 346 #define RIAAR_REGISTER_MIN 0x00000000 347 #define RIAAR_REGISTER_MAX 0x00008000 348 #define RIAAR_RX_SCRATCH_MIN 0x00030000 349 #define RIAAR_RX_SCRATCH_MAX 0x00034000 350 #define RIAAR_TX_SCRATCH_MIN 0x00034000 351 #define RIAAR_TX_SCRATCH_MAX 0x00038000 352 #define RIAAR_RXROM_MIN 0x00038000 353 #define RIAAR_RXROM_MAX 0x00038800 354 355 /* 356 * Memory Window Base Address Register, 0x7c in PCI config space 357 * Once this is set, accesses to the Memory Window Data Access Register 358 * (0x84) refer to the word of NIC-local memory whose address is given 359 * by this register. When used in this way, the whole of the address 360 * written to this register is significant. 361 * 362 * This register also provides the 32K-aligned base address for a 32K 363 * region of NIC-local memory that the host can directly address in 364 * the upper 32K of the 64K of PCI memory space allocated to the chip. 365 * In this case, the bottom 15 bits of the register are ignored. 366 * 367 * Note that the address written to the MWBAR should lie in the range 368 * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M 369 * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external 370 * memory were present, but it's only supported on the 5700, not the 371 * 5701/5703/5704. 372 */ 373 #define PCI_CONF_BGE_MWBAR 0x7c 374 #define PCI_CONF_BGE_MWDAR 0x84 375 #define MWBAR_GRANULARITY 0x00008000 /* 32k */ 376 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1) 377 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */ 378 379 /* 380 * The PCI express device control register and device status register 381 * which are only applicable on BCM5751 and BCM5721. 382 */ 383 #define PCI_CONF_DEV_CTRL 0xd8 384 #define READ_REQ_SIZE_MAX 0x5000 385 #define DEV_CTRL_NO_SNOOP 0x0800 386 #define DEV_CTRL_RELAXED 0x0010 387 388 #define PCI_CONF_DEV_STUS 0xda 389 #define DEVICE_ERROR_STUS 0xf 390 391 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */ 392 393 /* 394 * Where to find things in NIC-local (on-chip) memory 395 */ 396 #define NIC_MEM_SEND_RINGS 0x0100 397 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring)) 398 #define NIC_MEM_RECV_RINGS 0x0200 399 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring)) 400 #define NIC_MEM_STATISTICS 0x0300 401 #define NIC_MEM_STATISTICS_SIZE 0x0800 402 #define NIC_MEM_STATUS_BLOCK 0x0b00 403 #define NIC_MEM_STATUS_SIZE 0x0050 404 #define NIC_MEM_GENCOMM 0x0b50 405 406 407 /* 408 * Note: the (non-bogus) values below are appropriate for systems 409 * without external memory. They would be different on a 5700 with 410 * external memory. 411 * 412 * Note: The higher send ring addresses and the mini ring shadow 413 * buffer address are dummies - systems without external memory 414 * are limited to 4 send rings and no mini receive ring. 415 */ 416 #define NIC_MEM_SHADOW_DMA 0x2000 417 #define NIC_MEM_SHADOW_SEND_1_4 0x4000 418 #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */ 419 #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */ 420 #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */ 421 #define NIC_MEM_SHADOW_BUFF_STD 0x6000 422 #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000 423 #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */ 424 #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots)) 425 426 /* 427 * Put this in the GENCOMM port to tell the firmware not to run PXE 428 */ 429 #define T3_MAGIC_NUMBER 0x4b657654u 430 431 /* 432 * The remaining registers appear in the low 32K of regular 433 * PCI Memory Address Space 434 */ 435 436 /* 437 * All the state machine control registers below have at least a 438 * <RESET> bit and an <ENABLE> bit as defined below. Some also 439 * have an <ATTN_ENABLE> bit. 440 */ 441 #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004 442 #define STATE_MACHINE_ENABLE_BIT 0x00000002 443 #define STATE_MACHINE_RESET_BIT 0x00000001 444 445 #define TRANSMIT_MAC_MODE_REG 0x045c 446 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00 447 #define SEND_DATA_COMPLETION_MODE_REG 0x1000 448 #define SEND_BD_SELECTOR_MODE_REG 0x1400 449 #define SEND_BD_INITIATOR_MODE_REG 0x1800 450 #define SEND_BD_COMPLETION_MODE_REG 0x1c00 451 452 #define RECEIVE_MAC_MODE_REG 0x0468 453 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000 454 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400 455 #define RCV_DATA_COMPLETION_MODE_REG 0x2800 456 #define RCV_BD_INITIATOR_MODE_REG 0x2c00 457 #define RCV_BD_COMPLETION_MODE_REG 0x3000 458 #define RCV_LIST_SELECTOR_MODE_REG 0x3400 459 460 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800 461 #define HOST_COALESCE_MODE_REG 0x3c00 462 #define MEMORY_ARBITER_MODE_REG 0x4000 463 #define BUFFER_MANAGER_MODE_REG 0x4400 464 #define READ_DMA_MODE_REG 0x4800 465 #define WRITE_DMA_MODE_REG 0x4c00 466 #define DMA_COMPLETION_MODE_REG 0x6400 467 468 /* 469 * Other bits in some of the above state machine control registers 470 */ 471 472 /* 473 * Transmit MAC Mode Register 474 * (TRANSMIT_MAC_MODE_REG, 0x045c) 475 */ 476 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040 477 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020 478 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010 479 480 /* 481 * Receive MAC Mode Register 482 * (RECEIVE_MAC_MODE_REG, 0x0468) 483 */ 484 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400 485 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200 486 #define RECEIVE_MODE_PROMISCUOUS 0x00000100 487 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080 488 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040 489 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020 490 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010 491 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004 492 493 /* 494 * Receive BD Initiator Mode Register 495 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00) 496 * 497 * Each of these bits controls whether ATTN is asserted 498 * on a particular condition 499 */ 500 #define RCV_BD_DISABLED_RING_ATTN 0x00000004 501 502 /* 503 * Receive Data & Receive BD Initiator Mode Register 504 * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400) 505 * 506 * Each of these bits controls whether ATTN is asserted 507 * on a particular condition 508 */ 509 #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010 510 #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008 511 #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004 512 513 #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c 514 515 /* 516 * Host Coalescing Mode Control Register 517 * (HOST_COALESCE_MODE_REG, 0x3c00) 518 */ 519 #define COALESCE_64_BYTE_RINGS 12 520 #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000 521 #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800 522 #define COALESCE_CLR_TICKS_TX 0x00000400 523 #define COALESCE_CLR_TICKS_RX 0x00000200 524 #define COALESCE_32_BYTE_STATUS 0x00000100 525 #define COALESCE_64_BYTE_STATUS 0x00000080 526 #define COALESCE_NOW 0x00000008 527 528 /* 529 * Buffer Manager Mode Register 530 * (BUFFER_MANAGER_MODE_REG, 0x4400) 531 * 532 * In addition to the usual error-attn common to most state machines 533 * this register has a separate bit for attn on running-low-on-mbufs 534 */ 535 #define BUFF_MGR_TEST_MODE 0x00000008 536 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010 537 538 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014 539 540 /* 541 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG, 542 * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00) 543 * 544 * These registers each contain a 2-bit priority field, which controls 545 * the relative priority of that type of DMA (read vs. write vs. MSI), 546 * and a set of bits that control whether ATTN is asserted on each 547 * particular condition 548 */ 549 #define DMA_PRIORITY_MASK 0xc0000000 550 #define DMA_PRIORITY_SHIFT 30 551 #define ALL_DMA_ATTN_BITS 0x000003fc 552 553 /* 554 * End of state machine control register definitions 555 */ 556 557 558 /* 559 * Mailbox Registers (8 bytes each, but high half unused) 560 */ 561 #define INTERRUPT_MBOX_0_REG 0x0200 562 #define INTERRUPT_MBOX_1_REG 0x0208 563 #define INTERRUPT_MBOX_2_REG 0x0210 564 #define INTERRUPT_MBOX_3_REG 0x0218 565 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n)) 566 567 /* 568 * Ring Producer/Consumer Index (Mailbox) Registers 569 */ 570 #define RECV_STD_PROD_INDEX_REG 0x0268 571 #define RECV_JUMBO_PROD_INDEX_REG 0x0270 572 #define RECV_MINI_PROD_INDEX_REG 0x0278 573 #define RECV_RING_CONS_INDEX_REGS 0x0280 574 #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300 575 #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380 576 577 #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring)) 578 #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring)) 579 #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring)) 580 581 /* 582 * Ethernet MAC Mode Register 583 */ 584 #define ETHERNET_MAC_MODE_REG 0x0400 585 #define ETHERNET_MODE_ENABLE_FHDE 0x00800000 586 #define ETHERNET_MODE_ENABLE_RDE 0x00400000 587 #define ETHERNET_MODE_ENABLE_TDE 0x00200000 588 #define ETHERNET_MODE_ENABLE_MIP 0x00100000 589 #define ETHERNET_MODE_ENABLE_ACPI 0x00080000 590 #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000 591 #define ETHERNET_MODE_SEND_CFGS 0x00020000 592 #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000 593 #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000 594 #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000 595 #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000 596 #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000 597 #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800 598 #define ETHERNET_MODE_LINK_POLARITY 0x00000400 599 #define ETHERNET_MODE_MAX_DEFER 0x00000200 600 #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100 601 #define ETHERNET_MODE_TAGGED_MODE 0x00000080 602 #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010 603 #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c 604 #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c 605 #define ETHERNET_MODE_PORTMODE_GMII 0x00000008 606 #define ETHERNET_MODE_PORTMODE_MII 0x00000004 607 #define ETHERNET_MODE_PORTMODE_NONE 0x00000000 608 #define ETHERNET_MODE_HALF_DUPLEX 0x00000002 609 #define ETHERNET_MODE_GLOBAL_RESET 0x00000001 610 611 /* 612 * Ethernet MAC Status & Event Registers 613 */ 614 #define ETHERNET_MAC_STATUS_REG 0x0404 615 #define ETHERNET_STATUS_MI_INT 0x00800000 616 #define ETHERNET_STATUS_MI_COMPLETE 0x00400000 617 #define ETHERNET_STATUS_LINK_CHANGED 0x00001000 618 #define ETHERNET_STATUS_PCS_ERROR 0x00000400 619 #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010 620 #define ETHERNET_STATUS_CFG_CHANGED 0x00000008 621 #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004 622 #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002 623 #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001 624 625 #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408 626 #define ETHERNET_EVENT_MI_INT 0x00800000 627 #define ETHERNET_EVENT_LINK_INT 0x00001000 628 #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400 629 630 /* 631 * Ethernet MAC LED Control Register 632 * 633 * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and 634 * the external LED driver circuitry is wired up to assume that this mode 635 * will always be selected. Software must not change it! 636 */ 637 #define ETHERNET_MAC_LED_CONTROL_REG 0x040c 638 #define LED_CONTROL_OVERRIDE_BLINK 0x80000000 639 #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000 640 #define LED_CONTROL_LED_MODE_MASK 0x00001800 641 #define LED_CONTROL_LED_MODE_5700 0x00000000 642 #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */ 643 #define LED_CONTROL_LED_MODE_PHY_2 0x00001000 644 #define LED_CONTROL_LED_MODE_RESERVED 0x00001800 645 #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400 646 #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200 647 #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100 648 #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080 649 #define LED_CONTROL_BLINK_TRAFFIC 0x00000040 650 #define LED_CONTROL_TRAFFIC_LED 0x00000020 651 #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010 652 #define LED_CONTROL_10MBPS_LED 0x00000008 653 #define LED_CONTROL_100MBPS_LED 0x00000004 654 #define LED_CONTROL_1000MBPS_LED 0x00000002 655 #define LED_CONTROL_OVERRIDE_LINK 0x00000001 656 #define LED_CONTROL_DEFAULT 0x02000800 657 658 /* 659 * MAC Address registers 660 * 661 * These four eight-byte registers each hold one unicast address 662 * (six bytes), right justified & zero-filled on the left. 663 * They will normally all be set to the same value, as a station 664 * usually only has one h/w address. The value in register 0 is 665 * used for pause packets; any of the four can be specified for 666 * substitution into other transmitted packets if required. 667 */ 668 #define MAC_ADDRESS_0_REG 0x0410 669 #define MAC_ADDRESS_1_REG 0x0418 670 #define MAC_ADDRESS_2_REG 0x0420 671 #define MAC_ADDRESS_3_REG 0x0428 672 673 #define MAC_ADDRESS_REG(n) (0x0410+8*(n)) 674 #define MAC_ADDRESS_REGS_MAX 4 675 676 /* 677 * More MAC Registers ... 678 */ 679 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438 680 #define MAC_RX_MTU_SIZE_REG 0x043c 681 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */ 682 #define MAC_TX_LENGTHS_REG 0x0464 683 #define MAC_TX_LENGTHS_DEFAULT 0x00002620 684 685 /* 686 * MII access registers 687 */ 688 #define MI_COMMS_REG 0x044c 689 #define MI_COMMS_START 0x20000000 690 #define MI_COMMS_READ_FAILED 0x10000000 691 #define MI_COMMS_COMMAND_MASK 0x0c000000 692 #define MI_COMMS_COMMAND_READ 0x08000000 693 #define MI_COMMS_COMMAND_WRITE 0x04000000 694 #define MI_COMMS_ADDRESS_MASK 0x03e00000 695 #define MI_COMMS_ADDRESS_SHIFT 21 696 #define MI_COMMS_REGISTER_MASK 0x001f0000 697 #define MI_COMMS_REGISTER_SHIFT 16 698 #define MI_COMMS_DATA_MASK 0x0000ffff 699 #define MI_COMMS_DATA_SHIFT 0 700 701 #define MI_STATUS_REG 0x0450 702 #define MI_STATUS_10MBPS 0x00000002 703 #define MI_STATUS_LINK 0x00000001 704 705 #define MI_MODE_REG 0x0454 706 #define MI_MODE_CLOCK_MASK 0x001f0000 707 #define MI_MODE_AUTOPOLL 0x00000010 708 #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002 709 #define MI_MODE_DEFAULT 0x000c0000 710 711 #define MI_AUTOPOLL_STATUS_REG 0x0458 712 #define MI_AUTOPOLL_ERROR 0x00000001 713 714 #define TRANSMIT_MAC_STATUS_REG 0x0460 715 #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020 716 #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010 717 #define TRANSMIT_STATUS_LINK_UP 0x00000008 718 #define TRANSMIT_STATUS_SENT_XON 0x00000004 719 #define TRANSMIT_STATUS_SENT_XOFF 0x00000002 720 #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001 721 722 #define RECEIVE_MAC_STATUS_REG 0x046c 723 #define RECEIVE_STATUS_RCVD_XON 0x00000004 724 #define RECEIVE_STATUS_RCVD_XOFF 0x00000002 725 #define RECEIVE_STATUS_SENT_XOFF 0x00000001 726 727 /* 728 * These four-byte registers constitute a hash table for deciding 729 * whether to accept incoming multicast packets. The bits are 730 * numbered in big-endian fashion, from hash 0 => the MSB of 731 * register 0 to hash 127 => the LSB of the highest-numbered 732 * register. 733 * 734 * NOTE: the 5704 can use a 256-bit table (registers 0-7) if 735 * enabled by setting the appropriate bit in the Rx MAC mode 736 * register. Otherwise, and on all earlier chips, the table 737 * is only 128 bits (registers 0-3). 738 */ 739 #define MAC_HASH_0_REG 0x0470 740 #define MAC_HASH_1_REG 0x0474 741 #define MAC_HASH_2_REG 0x0478 742 #define MAC_HASH_3_REG 0x047c 743 #define MAC_HASH_4_REG 0x???? 744 #define MAC_HASH_5_REG 0x???? 745 #define MAC_HASH_6_REG 0x???? 746 #define MAC_HASH_7_REG 0x???? 747 #define MAC_HASH_REG(n) (0x470+4*(n)) 748 749 /* 750 * Receive Rules Registers: 16 pairs of control+mask/value pairs 751 */ 752 #define RCV_RULES_CONTROL_0_REG 0x0480 753 #define RCV_RULES_MASK_0_REG 0x0484 754 #define RCV_RULES_CONTROL_15_REG 0x04f8 755 #define RCV_RULES_MASK_15_REG 0x04fc 756 #define RCV_RULES_CONFIG_REG 0x0500 757 #define RCV_RULES_CONFIG_DEFAULT 0x00000008 758 759 #define RECV_RULES_NUM_MAX 16 760 #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule)) 761 #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule)) 762 763 #define RECV_RULE_CTL_ENABLE 0x80000000 764 #define RECV_RULE_CTL_AND 0x40000000 765 #define RECV_RULE_CTL_P1 0x20000000 766 #define RECV_RULE_CTL_P2 0x10000000 767 #define RECV_RULE_CTL_P3 0x08000000 768 #define RECV_RULE_CTL_MASK 0x04000000 769 #define RECV_RULE_CTL_DISCARD 0x02000000 770 #define RECV_RULE_CTL_MAP 0x01000000 771 #define RECV_RULE_CTL_RESV_BITS 0x00fc0000 772 #define RECV_RULE_CTL_OP 0x00030000 773 #define RECV_RULE_CTL_OP_EQ 0x00000000 774 #define RECV_RULE_CTL_OP_NEQ 0x00010000 775 #define RECV_RULE_CTL_OP_GREAT 0x00020000 776 #define RECV_RULE_CTL_OP_LESS 0x00030000 777 #define RECV_RULE_CTL_HEADER 0x0000e000 778 #define RECV_RULE_CTL_HEADER_FRAME 0x00000000 779 #define RECV_RULE_CTL_HEADER_IP 0x00002000 780 #define RECV_RULE_CTL_HEADER_TCP 0x00004000 781 #define RECV_RULE_CTL_HEADER_UDP 0x00006000 782 #define RECV_RULE_CTL_HEADER_DATA 0x00008000 783 #define RECV_RULE_CTL_CLASS_BITS 0x00001f00 784 #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \ 785 RECV_RULE_CTL_CLASS_BITS) 786 #define RECV_RULE_CTL_OFFSET 0x000000ff 787 788 /* 789 * Receive Rules definition 790 */ 791 #define RULE_MATCH_TO_RING 2 792 /* ring that traffic will go into when recv rule matches. */ 793 /* value is between 1 and 16, not 0 and 15 */ 794 795 #define IPHEADER_PROTO_OFFSET 0x08 796 #define IPHEADER_SIP_OFFSET 0x0c 797 798 #define RULE_PROTO_CONTROL (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_MASK | \ 799 RECV_RULE_CTL_OP_EQ | \ 800 RECV_RULE_CTL_HEADER_IP | \ 801 RECV_RULE_CTL_CLASS(RULE_MATCH_TO_RING) | \ 802 IPHEADER_PROTO_OFFSET) 803 #define RULE_TCP_MASK_VALUE 0x00ff0006 804 #define RULE_UDP_MASK_VALUE 0x00ff0011 805 #define RULE_ICMP_MASK_VALUE 0x00ff0001 806 807 #define RULE_SIP_ADDR 0x0a000001 808 /* ip address in 32-bit integer,such as, 0x0a000001 is "10.0.0.1" */ 809 810 #define RULE_SIP_CONTROL (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \ 811 RECV_RULE_CTL_HEADER_IP | \ 812 RECV_RULE_CTL_CLASS(RULE_MATCH_TO_RING) | \ 813 IPHEADER_SIP_OFFSET) 814 #define RULE_SIP_MASK_VALUE RULE_SIP_ADDR 815 816 /* 817 * 1000BaseX low-level access registers 818 */ 819 #define MAC_GIGABIT_PCS_TEST_REG 0x0440 820 #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000 821 #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff 822 #define TX_1000BASEX_AUTONEG_REG 0x0444 823 #define RX_1000BASEX_AUTONEG_REG 0x0448 824 825 /* 826 * Autoneg code bits for the 1000BASE-X AUTONEG registers 827 */ 828 #define AUTONEG_CODE_PAUSE 0x00008000 829 #define AUTONEG_CODE_HALF_DUPLEX 0x00004000 830 #define AUTONEG_CODE_FULL_DUPLEX 0x00002000 831 #define AUTONEG_CODE_NEXT_PAGE 0x00000080 832 #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040 833 #define AUTONEG_CODE_FAULT_MASK 0x00000030 834 #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030 835 #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020 836 #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010 837 #define AUTONEG_CODE_ASYM_PAUSE 0x00000001 838 839 /* 840 * SerDes Registers (5703S/5704S only) 841 */ 842 #define SERDES_CONTROL_REG 0x0590 843 #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000 844 #define SERDES_CONTROL_COMMA_DETECT 0x00010000 845 #define SERDES_CONTROL_TX_DISABLE 0x00004000 846 #define SERDES_STATUS_REG 0x0594 847 #define SERDES_STATUS_COMMA_DETECTED 0x00000100 848 #define SERDES_STATUS_RXSTAT 0x000000ff 849 850 /* 851 * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only) 852 */ 853 #define STAT_IFHCOUT_OCTETS_REG 0x0800 854 #define STAT_ETHER_COLLIS_REG 0x0808 855 #define STAT_OUTXON_SENT_REG 0x080c 856 #define STAT_OUTXOFF_SENT_REG 0x0810 857 #define STAT_DOT3_INTMACTX_ERR_REG 0x0818 858 #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c 859 #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820 860 #define STAT_DOT3_DEFERED_TX_REG 0x0824 861 #define STAT_DOT3_EXCE_COLLI_REG 0x082c 862 #define STAT_DOT3_LATE_COLLI_REG 0x0830 863 #define STAT_IFHCOUT_UPKGS_REG 0x086c 864 #define STAT_IFHCOUT_MPKGS_REG 0x0870 865 #define STAT_IFHCOUT_BPKGS_REG 0x0874 866 867 #define STAT_IFHCIN_OCTETS_REG 0x0880 868 #define STAT_ETHER_FRAGMENT_REG 0x0888 869 #define STAT_IFHCIN_UPKGS_REG 0x088c 870 #define STAT_IFHCIN_MPKGS_REG 0x0890 871 #define STAT_IFHCIN_BPKGS_REG 0x0894 872 873 #define STAT_DOT3_FCS_ERR_REG 0x0898 874 #define STAT_DOT3_ALIGN_ERR_REG 0x089c 875 #define STAT_XON_PAUSE_RX_REG 0x08a0 876 #define STAT_XOFF_PAUSE_RX_REG 0x08a4 877 #define STAT_MAC_CTRL_RX_REG 0x08a8 878 #define STAT_XOFF_STATE_ENTER_REG 0x08ac 879 #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0 880 #define STAT_ETHER_JABBERS_REG 0x08b4 881 #define STAT_ETHER_UNDERSIZE_REG 0x08b8 882 #define SIZE_OF_STATISTIC_REG 0x1B 883 /* 884 * Send Data Initiator Registers 885 */ 886 #define SEND_INIT_STATS_CONTROL_REG 0x0c08 887 #define SEND_INIT_STATS_ZERO 0x00000010 888 #define SEND_INIT_STATS_FLUSH 0x00000008 889 #define SEND_INIT_STATS_CLEAR 0x00000004 890 #define SEND_INIT_STATS_FASTER 0x00000002 891 #define SEND_INIT_STATS_ENABLE 0x00000001 892 893 #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c 894 895 /* 896 * Send Buffer Descriptor Selector Control Registers 897 */ 898 #define SEND_BD_SELECTOR_STATUS_REG 0x1404 899 #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408 900 #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n)) 901 902 /* 903 * Receive List Placement Registers 904 */ 905 #define RCV_LP_CONFIG_REG 0x2010 906 #define RCV_LP_CONFIG_DEFAULT 0x00000009 907 #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1) 908 909 #define RCV_LP_STATS_CONTROL_REG 0x2014 910 #define RCV_LP_STATS_ZERO 0x00000010 911 #define RCV_LP_STATS_FLUSH 0x00000008 912 #define RCV_LP_STATS_CLEAR 0x00000004 913 #define RCV_LP_STATS_FASTER 0x00000002 914 #define RCV_LP_STATS_ENABLE 0x00000001 915 916 #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018 917 918 /* 919 * Receive Data & BD Initiator Registers 920 */ 921 #define RCV_INITIATOR_STATUS_REG 0x2404 922 923 /* 924 * Receive Buffer Descriptor Ring Control Block Registers 925 * NB: sixteen bytes (128 bits) each 926 */ 927 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440 928 #define STD_RCV_BD_RING_RCB_REG 0x2450 929 #define MINI_RCV_BD_RING_RCB_REG 0x2460 930 931 /* 932 * Receive Buffer Descriptor Ring Replenish Threshold Registers 933 */ 934 #define MINI_RCV_BD_REPLENISH_REG 0x2c14 935 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */ 936 #define STD_RCV_BD_REPLENISH_REG 0x2c18 937 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */ 938 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c 939 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */ 940 941 /* 942 * Host Coalescing Engine Control Registers 943 */ 944 #define RCV_COALESCE_TICKS_REG 0x3c08 945 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 946 #define SEND_COALESCE_TICKS_REG 0x3c0c 947 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 948 #define RCV_COALESCE_MAX_BD_REG 0x3c10 949 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 950 #define SEND_COALESCE_MAX_BD_REG 0x3c14 951 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 952 #define RCV_COALESCE_INT_TICKS_REG 0x3c18 953 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 954 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c 955 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 956 #define RCV_COALESCE_INT_BD_REG 0x3c20 957 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 958 #define SEND_COALESCE_INT_BD_REG 0x3c24 959 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 960 #define STATISTICS_TICKS_REG 0x3c28 961 #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */ 962 #define STATISTICS_HOST_ADDR_REG 0x3c30 963 #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38 964 #define STATISTICS_BASE_ADDR_REG 0x3c40 965 #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44 966 #define FLOW_ATTN_REG 0x3c48 967 968 #define NIC_JUMBO_RECV_INDEX_REG 0x3c50 969 #define NIC_STD_RECV_INDEX_REG 0x3c54 970 #define NIC_MINI_RECV_INDEX_REG 0x3c58 971 #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n)) 972 #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n)) 973 974 /* 975 * Mbuf Pool Initialisation & Watermark Registers 976 * 977 * There are some conflicts in the PRM; compare the recommendations 978 * on pp. 115, 236, and 339. The values here were recommended by 979 * dkim@broadcom.com (and the PRM should be corrected soon ;-) 980 */ 981 #define BUFFER_MANAGER_STATUS_REG 0x4404 982 #define MBUF_POOL_BASE_REG 0x4408 983 #define MBUF_POOL_BASE_DEFAULT 0x00008000 984 #define MBUF_POOL_BASE_5721 0x00010000 985 #define MBUF_POOL_BASE_5704 0x00010000 986 #define MBUF_POOL_BASE_5705 0x00010000 987 #define MBUF_POOL_LENGTH_REG 0x440c 988 #define MBUF_POOL_LENGTH_DEFAULT 0x00018000 989 #define MBUF_POOL_LENGTH_5704 0x00010000 990 #define MBUF_POOL_LENGTH_5705 0x00008000 991 #define MBUF_POOL_LENGTH_5721 0x00008000 992 #define RDMA_MBUF_LOWAT_REG 0x4410 993 #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050 994 #define RDMA_MBUF_LOWAT_5705 0x00000000 995 #define RDMA_MBUF_LOWAT_JUMBO 0x00000130 996 #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000 997 #define MAC_RX_MBUF_LOWAT_REG 0x4414 998 #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020 999 #define MAC_RX_MBUF_LOWAT_5705 0x00000010 1000 #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098 1001 #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b 1002 #define MBUF_HIWAT_REG 0x4418 1003 #define MBUF_HIWAT_DEFAULT 0x00000060 1004 #define MBUF_HIWAT_5705 0x00000060 1005 #define MBUF_HIWAT_JUMBO 0x0000017c 1006 #define MBUF_HIWAT_5714_JUMBO 0x00000096 1007 1008 /* 1009 * DMA Descriptor Pool Initialisation & Watermark Registers 1010 */ 1011 #define DMAD_POOL_BASE_REG 0x442c 1012 #define DMAD_POOL_BASE_DEFAULT 0x00002000 1013 #define DMAD_POOL_LENGTH_REG 0x4430 1014 #define DMAD_POOL_LENGTH_DEFAULT 0x00002000 1015 #define DMAD_POOL_LOWAT_REG 0x4434 1016 #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */ 1017 #define DMAD_POOL_HIWAT_REG 0x4438 1018 #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */ 1019 1020 /* 1021 * More threshold/watermark registers ... 1022 */ 1023 #define RECV_FLOW_THRESHOLD_REG 0x4458 1024 #define LOWAT_MAX_RECV_FRAMES_REG 0x0504 1025 #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002 1026 1027 /* 1028 * Read/Write DMA Status Registers 1029 */ 1030 #define READ_DMA_STATUS_REG 0x4804 1031 #define WRITE_DMA_STATUS_REG 0x4c04 1032 1033 /* 1034 * RX/TX RISC Registers 1035 */ 1036 #define RX_RISC_MODE_REG 0x5000 1037 #define RX_RISC_STATE_REG 0x5004 1038 #define RX_RISC_PC_REG 0x501c 1039 #define TX_RISC_MODE_REG 0x5400 1040 #define TX_RISC_STATE_REG 0x5404 1041 #define TX_RISC_PC_REG 0x541c 1042 1043 #define FTQ_RESET_REG 0x5c00 1044 1045 #define MSI_MODE_REG 0x6000 1046 #define MSI_PRI_HIGHEST 0xc0000000 1047 #define MSI_MSI_ENABLE 0x00000002 1048 1049 #define MODE_CONTROL_REG 0x6800 1050 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000 1051 #define MODE_4X_NIC_SEND_RINGS 0x20000000 1052 #define MODE_INT_ON_FLOW_ATTN 0x10000000 1053 #define MODE_INT_ON_DMA_ATTN 0x08000000 1054 #define MODE_INT_ON_MAC_ATTN 0x04000000 1055 #define MODE_INT_ON_RXRISC_ATTN 0x02000000 1056 #define MODE_INT_ON_TXRISC_ATTN 0x01000000 1057 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000 1058 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000 1059 #define MODE_HOST_SEND_BDS 0x00020000 1060 #define MODE_HOST_STACK_UP 0x00010000 1061 #define MODE_FORCE_32_BIT_PCI 0x00008000 1062 #define MODE_NO_INT_ON_RECV 0x00004000 1063 #define MODE_NO_INT_ON_SEND 0x00002000 1064 #define MODE_ALLOW_BAD_FRAMES 0x00000800 1065 #define MODE_NO_CRC 0x00000400 1066 #define MODE_NO_FRAME_CRACKING 0x00000200 1067 #define MODE_WORD_SWAP_FRAME 0x00000020 1068 #define MODE_BYTE_SWAP_FRAME 0x00000010 1069 #define MODE_WORD_SWAP_NONFRAME 0x00000004 1070 #define MODE_BYTE_SWAP_NONFRAME 0x00000002 1071 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001 1072 1073 /* 1074 * Miscellaneous Configuration Register 1075 * 1076 * This contains various bits relating to power control (which differ 1077 * among different members of the chip family), but the important bits 1078 * for our purposes are the RESET bit and the Timer Prescaler field. 1079 * 1080 * The RESET bit in this register serves to reset the whole chip, even 1081 * including the PCI interface(!) Once it's set, the chip will not 1082 * respond to ANY accesses -- not even CONFIG space -- until the reset 1083 * completes internally. According to the PRM, this should take less 1084 * than 100us. Any access during this period will get a bus error. 1085 * 1086 * The Timer Prescaler field must be programmed so that the timer period 1087 * is as near as possible to 1us. The value in this field should be 1088 * the Core Clock frequency in MHz minus 1. From my reading of the PRM, 1089 * the Core Clock should always be 66MHz (independently of the bus speed, 1090 * at least for PCI rather than PCI-X), so this register must be set to 1091 * the value 0x82 ((66-1) << 1). 1092 */ 1093 #define CORE_CLOCK_MHZ 66 1094 #define MISC_CONFIG_REG 0x6804 1095 #define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000 1096 #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000 1097 #define MISC_CONFIG_POWERDOWN 0x00100000 1098 #define MISC_CONFIG_POWER_STATE 0x00060000 1099 #define MISC_CONFIG_PRESCALE_MASK 0x000000fe 1100 #define MISC_CONFIG_RESET_BIT 0x00000001 1101 #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1) 1102 1103 /* 1104 * Miscellaneous Local Control Register (MLCR) 1105 */ 1106 #define MISC_LOCAL_CONTROL_REG 0x6808 1107 #define MLCR_PCI_CTRL_SELECT 0x10000000 1108 #define MLCR_LEGACY_PCI_MODE 0x08000000 1109 #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000 1110 #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000 1111 #define MLCR_SSRAM_TYPE 0x00400000 1112 #define MLCR_BANK_SELECT 0x00200000 1113 #define MLCR_SRAM_SIZE_MASK 0x001c0000 1114 #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000 1115 1116 #define MLCR_MISC_PINS_OUTPUT_2 0x00010000 1117 #define MLCR_MISC_PINS_OUTPUT_1 0x00008000 1118 #define MLCR_MISC_PINS_OUTPUT_0 0x00004000 1119 #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000 1120 #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000 1121 #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800 1122 #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */ 1123 #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */ 1124 #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */ 1125 1126 #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */ 1127 #define MLCR_SET_INT 0x00000004 /* W/O */ 1128 #define MLCR_CLR_INT 0x00000002 /* W/O */ 1129 #define MLCR_INTA_STATE 0x00000001 /* R/O */ 1130 1131 /* 1132 * This value defines all GPIO bits as INPUTS, but sets their default 1133 * values as outputs to HIGH, on the assumption that external circuits 1134 * (if any) will probably be active-LOW with passive pullups. 1135 * 1136 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in 1137 * just this fashion. It has to be set as an OUTPUT and driven LOW to 1138 * enable writing. Otherwise, the SEEPROM is protected. 1139 */ 1140 #define MLCR_DEFAULT 0x0101c000 1141 #define MLCR_DEFAULT_5714 0x1901c000 1142 1143 /* 1144 * Serial EEPROM Data/Address Registers (auto-access mode) 1145 */ 1146 #define SERIAL_EEPROM_DATA_REG 0x683c 1147 #define SERIAL_EEPROM_ADDRESS_REG 0x6838 1148 #define SEEPROM_ACCESS_READ 0x80000000 1149 #define SEEPROM_ACCESS_WRITE 0x00000000 1150 #define SEEPROM_ACCESS_COMPLETE 0x40000000 1151 #define SEEPROM_ACCESS_RESET 0x20000000 1152 #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000 1153 #define SEEPROM_ACCESS_START 0x02000000 1154 #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000 1155 #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc 1156 1157 #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */ 1158 #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */ 1159 #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */ 1160 1161 #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */ 1162 #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */ 1163 1164 /* 1165 * "Linearised" address mask, treating multiple devices as consecutive 1166 */ 1167 #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */ 1168 1169 /* 1170 * Non-Volatile Memory Interface Registers 1171 * Note: on chips that support the flash interface (5702+), flash is the 1172 * default and the legacy seeprom interface must be explicitly enabled 1173 * if required. On older chips (5700/01), SEEPROM is the default (and 1174 * only) non-volatile memory available, and these registers don't exist! 1175 */ 1176 #define NVM_FLASH_CMD_REG 0x7000 1177 #define NVM_FLASH_CMD_LAST 0x00000100 1178 #define NVM_FLASH_CMD_FIRST 0x00000080 1179 #define NVM_FLASH_CMD_RD 0x00000000 1180 #define NVM_FLASH_CMD_WR 0x00000020 1181 #define NVM_FLASH_CMD_DOIT 0x00000010 1182 #define NVM_FLASH_CMD_DONE 0x00000008 1183 1184 #define NVM_FLASH_WRITE_REG 0x7008 1185 #define NVM_FLASH_READ_REG 0x7010 1186 1187 #define NVM_FLASH_ADDR_REG 0x700c 1188 #define NVM_FLASH_ADDR_MASK 0x00fffffc 1189 1190 #define NVM_CONFIG1_REG 0x7014 1191 #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000 1192 #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800 1193 #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780 1194 #define NVM_CFG1_BUFFERED_MODE 0x00000002 1195 #define NVM_CFG1_FLASH_MODE 0x00000001 1196 1197 #define NVM_SW_ARBITRATION_REG 0x7020 1198 #define NVM_READ_REQ3 0X00008000 1199 #define NVM_READ_REQ2 0X00004000 1200 #define NVM_READ_REQ1 0X00002000 1201 #define NVM_READ_REQ0 0X00001000 1202 #define NVM_WON_REQ3 0X00000800 1203 #define NVM_WON_REQ2 0X00000400 1204 #define NVM_WON_REQ1 0X00000200 1205 #define NVM_WON_REQ0 0X00000100 1206 #define NVM_RESET_REQ3 0X00000080 1207 #define NVM_RESET_REQ2 0X00000040 1208 #define NVM_RESET_REQ1 0X00000020 1209 #define NVM_RESET_REQ0 0X00000010 1210 #define NVM_SET_REQ3 0X00000008 1211 #define NVM_SET_REQ2 0X00000004 1212 #define NVM_SET_REQ1 0X00000002 1213 #define NVM_SET_REQ0 0X00000001 1214 1215 /* 1216 * NVM access register 1217 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714 1218 * and BCM5715 only. 1219 */ 1220 #define NVM_ACCESS_REG 0X7024 1221 #define NVM_WRITE_ENABLE 0X00000002 1222 #define NVM_ACCESS_ENABLE 0X00000001 1223 1224 /* 1225 * TLP Control Register 1226 * Applicable to BCM5721 and BCM5751 only 1227 */ 1228 #define TLP_CONTROL_REG 0x7c00 1229 #define TLP_DATA_FIFO_PROTECT 0x02000000 1230 1231 /* 1232 * PHY Test Control Register 1233 * Applicable to BCM5721 and BCM5751 only 1234 */ 1235 #define PHY_TEST_CTRL_REG 0x7e2c 1236 #define PHY_PCIE_SCRAM_MODE 0x20 1237 #define PHY_PCIE_LTASS_MODE 0x40 1238 1239 /* 1240 * The internal firmware expects a certain layout of the non-volatile 1241 * memory (if fitted), and will check for it during startup, and use the 1242 * contents to initialise various internal parameters if it looks good. 1243 * 1244 * The offsets and field definitions below refer to where to find some 1245 * important values, and how to interpret them ... 1246 */ 1247 #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */ 1248 1249 /* 1250 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 1251 */ 1252 1253 #define MII_AN_LPNXTPG 8 1254 #define MII_1000BASE_T_CONTROL 9 1255 #define MII_1000BASE_T_STATUS 10 1256 #define MII_IEEE_EXT_STATUS 15 1257 1258 /* 1259 * New bits in the MII_CONTROL register 1260 */ 1261 #define MII_CONTROL_1000MB 0x0040 1262 1263 /* 1264 * New bits in the MII_AN_ADVERT register 1265 */ 1266 #define MII_ABILITY_ASYM_PAUSE 0x0800 1267 #define MII_ABILITY_PAUSE 0x0400 1268 1269 /* 1270 * Values for the <selector> field of the MII_AN_ADVERT register 1271 */ 1272 #define MII_AN_SELECTOR_8023 0x0001 1273 1274 /* 1275 * Bits in the MII_1000BASE_T_CONTROL register 1276 * 1277 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 1278 * (otherwise, roles are automatically negotiated). When this bit is set, 1279 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 1280 */ 1281 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 1282 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 1283 #define MII_1000BT_CTL_ADV_FDX 0x0200 1284 #define MII_1000BT_CTL_ADV_HDX 0x0100 1285 1286 /* 1287 * Bits in the MII_1000BASE_T_STATUS register 1288 */ 1289 #define MII_1000BT_STAT_MASTER_FAULT 0x8000 1290 #define MII_1000BT_STAT_MASTER_MODE 0x4000 /* shows role selected */ 1291 #define MII_1000BT_STAT_LCL_RCV_OK 0x2000 1292 #define MII_1000BT_STAT_RMT_RCV_OK 0x1000 1293 #define MII_1000BT_STAT_LP_FDX_CAP 0x0800 1294 #define MII_1000BT_STAT_LP_HDX_CAP 0x0400 1295 1296 /* 1297 * Vendor-specific MII registers 1298 */ 1299 #define MII_EXT_CONTROL MII_VENDOR(0) 1300 #define MII_EXT_STATUS MII_VENDOR(1) 1301 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 1302 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 1303 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 1304 #define MII_AUX_CONTROL MII_VENDOR(8) 1305 #define MII_AUX_STATUS MII_VENDOR(9) 1306 #define MII_INTR_STATUS MII_VENDOR(10) 1307 #define MII_INTR_MASK MII_VENDOR(11) 1308 #define MII_HCD_STATUS MII_VENDOR(13) 1309 1310 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 1311 1312 /* 1313 * Bits in the MII_EXT_CONTROL register 1314 */ 1315 #define MII_EXT_CTRL_INTERFACE_TBI 0x8000 1316 #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000 1317 #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000 1318 #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000 1319 #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800 1320 #define MII_EXT_CTRL_BYPASS_4B5B 0x0400 1321 #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200 1322 #define MII_EXT_CTRL_BYPASS_MLT3 0x0100 1323 #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080 1324 #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040 1325 #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020 1326 #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010 1327 #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008 1328 #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004 1329 #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002 1330 #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001 1331 1332 /* 1333 * Bits in the MII_EXT_STATUS register 1334 */ 1335 #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000 1336 #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000 1337 #define MII_EXT_STAT_MDIX_STATE 0x2000 1338 #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000 1339 #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800 1340 #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400 1341 #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200 1342 #define MII_EXT_STAT_LINK_STATUS 0x0100 1343 #define MII_EXT_STAT_CRC_ERROR 0x0080 1344 #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040 1345 #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020 1346 #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010 1347 #define MII_EXT_STAT_RECEIVE_ERROR 0x0008 1348 #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004 1349 #define MII_EXT_STAT_LOCK_ERROR 0x0002 1350 #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001 1351 1352 /* 1353 * The AUX CONTROL register is seriously weird! 1354 * 1355 * It hides (up to) eight 'shadow' registers. When writing, which one 1356 * of them is written is determined by the low-order bits of the data 1357 * written(!), but when reading, which one is read is determined by the 1358 * value previously written to (part of) one of the shadow registers!!! 1359 */ 1360 1361 /* 1362 * Shadow register numbers 1363 */ 1364 #define MII_AUX_CTRL_NORMAL 0 1365 #define MII_AUX_CTRL_10BASE_T 1 1366 #define MII_AUX_CTRL_POWER 2 1367 #define MII_AUX_CTRL_TEST_1 4 1368 #define MII_AUX_CTRL_MISC 7 1369 1370 /* 1371 * Selected bits in some of the shadow registers ... 1372 */ 1373 #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000 1374 #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000 1375 #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000 1376 #define MII_AUX_CTRL_NORM_TX_MODE 0x0400 1377 #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008 1378 1379 #define MII_AUX_CTRL_TEST_TX_HALF 0x0008 1380 1381 #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000 1382 #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010 1383 1384 /* 1385 * Write this value to the AUX control register 1386 * to select which shadow register will be read 1387 */ 1388 #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC) 1389 1390 /* 1391 * Bits in the MII_AUX_STATUS register 1392 */ 1393 #define MII_AUX_STATUS_MODE_MASK 0x0700 1394 #define MII_AUX_STATUS_MODE_1000_F 0x0700 1395 #define MII_AUX_STATUS_MODE_1000_H 0x0600 1396 #define MII_AUX_STATUS_MODE_100_F 0x0500 1397 #define MII_AUX_STATUS_MODE_100_4 0x0400 1398 #define MII_AUX_STATUS_MODE_100_H 0x0300 1399 #define MII_AUX_STATUS_MODE_10_F 0x0200 1400 #define MII_AUX_STATUS_MODE_10_H 0x0100 1401 #define MII_AUX_STATUS_MODE_NONE 0x0000 1402 #define MII_AUX_STATUS_MODE_SHIFT 8 1403 1404 #define MII_AUX_STATUS_PAR_FAULT 0x0080 1405 #define MII_AUX_STATUS_REM_FAULT 0x0040 1406 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 1407 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 1408 1409 #define MII_AUX_STATUS_LINKUP 0x0004 1410 #define MII_AUX_STATUS_RX_PAUSE 0x0002 1411 #define MII_AUX_STATUS_TX_PAUSE 0x0001 1412 1413 /* 1414 * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers 1415 */ 1416 #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020 1417 #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010 1418 #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008 1419 #define MII_INTR_LINK_SPEED_CHANGE 0x0004 1420 #define MII_INTR_LINK_STATUS_CHANGE 0x0002 1421 1422 1423 /* 1424 * Third section: 1425 * Hardware-defined data structures 1426 * 1427 * Note that the chip is naturally BIG-endian, so, for a big-endian 1428 * host, the structures defined below match those described in the PRM. 1429 * For little-endian hosts, some structures have to be swapped around. 1430 */ 1431 1432 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 1433 #error Host endianness not defined 1434 #endif 1435 1436 /* 1437 * Architectural constants: absolute maximum numbers of each type of ring 1438 */ 1439 #ifdef BGE_EXT_MEM 1440 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */ 1441 #else 1442 #define BGE_SEND_RINGS_MAX 4 1443 #endif 1444 #define BGE_SEND_RINGS_MAX_5705 1 1445 #define BGE_RECV_RINGS_MAX 16 1446 #define BGE_RECV_RINGS_MAX_5705 1 1447 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */ 1448 /* only with ext mem) */ 1449 1450 #define BGE_SEND_SLOTS_MAX 512 1451 #define BGE_STD_SLOTS_MAX 512 1452 #define BGE_JUMBO_SLOTS_MAX 256 1453 #define BGE_MINI_SLOTS_MAX 1024 1454 #define BGE_RECV_SLOTS_MAX 2048 1455 #define BGE_RECV_SLOTS_5705 512 1456 #define BGE_RECV_SLOTS_5782 512 1457 #define BGE_RECV_SLOTS_5721 512 1458 1459 /* 1460 * Hardware-defined Ring Control Block 1461 */ 1462 typedef struct { 1463 uint64_t host_ring_addr; 1464 #ifdef _BIG_ENDIAN 1465 uint16_t max_len; 1466 uint16_t flags; 1467 uint32_t nic_ring_addr; 1468 #else 1469 uint32_t nic_ring_addr; 1470 uint16_t flags; 1471 uint16_t max_len; 1472 #endif /* _BIG_ENDIAN */ 1473 } bge_rcb_t; 1474 1475 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001 1476 #define RCB_FLAG_RING_DISABLED 0x0002 1477 1478 /* 1479 * Hardware-defined Send Buffer Descriptor 1480 */ 1481 typedef struct { 1482 uint64_t host_buf_addr; 1483 #ifdef _BIG_ENDIAN 1484 uint16_t len; 1485 uint16_t flags; 1486 uint16_t reserved; 1487 uint16_t vlan_tci; 1488 #else 1489 uint16_t vlan_tci; 1490 uint16_t reserved; 1491 uint16_t flags; 1492 uint16_t len; 1493 #endif /* _BIG_ENDIAN */ 1494 } bge_sbd_t; 1495 1496 #define SBD_FLAG_TCP_UDP_CKSUM 0x0001 1497 #define SBD_FLAG_IP_CKSUM 0x0002 1498 #define SBD_FLAG_PACKET_END 0x0004 1499 #define SBD_FLAG_IP_FRAG 0x0008 1500 #define SBD_FLAG_IP_FRAG_END 0x0010 1501 1502 #define SBD_FLAG_VLAN_TAG 0x0040 1503 #define SBD_FLAG_COAL_NOW 0x0080 1504 #define SBD_FLAG_CPU_PRE_DMA 0x0100 1505 #define SBD_FLAG_CPU_POST_DMA 0x0200 1506 1507 #define SBD_FLAG_INSERT_SRC_ADDR 0x1000 1508 #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000 1509 #define SBD_FLAG_DONT_GEN_CRC 0x8000 1510 1511 /* 1512 * Hardware-defined Receive Buffer Descriptor 1513 */ 1514 typedef struct { 1515 uint64_t host_buf_addr; 1516 #ifdef _BIG_ENDIAN 1517 uint16_t index; 1518 uint16_t len; 1519 uint16_t type; 1520 uint16_t flags; 1521 uint16_t ip_cksum; 1522 uint16_t tcp_udp_cksum; 1523 uint16_t error_flag; 1524 uint16_t vlan_tci; 1525 uint32_t reserved; 1526 uint32_t opaque; 1527 #else 1528 uint16_t flags; 1529 uint16_t type; 1530 uint16_t len; 1531 uint16_t index; 1532 uint16_t vlan_tci; 1533 uint16_t error_flag; 1534 uint16_t tcp_udp_cksum; 1535 uint16_t ip_cksum; 1536 uint32_t opaque; 1537 uint32_t reserved; 1538 #endif /* _BIG_ENDIAN */ 1539 } bge_rbd_t; 1540 1541 #define RBD_FLAG_STD_RING 0x0000 1542 #define RBD_FLAG_PACKET_END 0x0004 1543 1544 #define RBD_FLAG_JUMBO_RING 0x0020 1545 #define RBD_FLAG_VLAN_TAG 0x0040 1546 1547 #define RBD_FLAG_FRAME_HAS_ERROR 0x0400 1548 #define RBD_FLAG_MINI_RING 0x0800 1549 #define RBD_FLAG_IP_CHECKSUM 0x1000 1550 #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000 1551 #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000 1552 1553 #define RBD_FLAG_DEFAULT 0x0000 1554 1555 #define RBD_ERROR_BAD_CRC 0x00010000 1556 #define RBD_ERROR_COLL_DETECT 0x00020000 1557 #define RBD_ERROR_LINK_LOST 0x00040000 1558 #define RBD_ERROR_PHY_DECODE_ERR 0x00080000 1559 #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000 1560 #define RBD_ERROR_MAC_ABORT 0x00200000 1561 #define RBD_ERROR_LEN_LESS_64 0x00400000 1562 #define RBD_ERROR_TRUNC_NO_RES 0x00800000 1563 #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000 1564 1565 /* 1566 * Hardware-defined Status Block,Size of status block 1567 * is actually 0x50 bytes.Use 0x80 bytes for cache line 1568 * alignment.For BCM5705/5788/5721/5751/5752/5714 1569 * and 5715,there is only 1 recv and send ring index,but 1570 * driver defined 16 indexs here,please pay attention only 1571 * one ring is enabled in these chipsets. 1572 */ 1573 typedef struct { 1574 uint64_t flags_n_tag; 1575 uint16_t buff_cons_index[4]; 1576 struct { 1577 #ifdef _BIG_ENDIAN 1578 uint16_t send_cons_index; 1579 uint16_t recv_prod_index; 1580 #else 1581 uint16_t recv_prod_index; 1582 uint16_t send_cons_index; 1583 #endif /* _BIG_ENDIAN */ 1584 } index[16]; 1585 } bge_status_t; 1586 1587 /* 1588 * Hardware-defined Receive BD Rule 1589 */ 1590 typedef struct { 1591 uint32_t control; 1592 uint32_t mask_value; 1593 } bge_recv_rule_t; 1594 1595 /* 1596 * Indexes into the <buff_cons_index> array 1597 */ 1598 #ifdef _BIG_ENDIAN 1599 #define STATUS_STD_BUFF_CONS_INDEX 0 1600 #define STATUS_JUMBO_BUFF_CONS_INDEX 1 1601 #define STATUS_MINI_BUFF_CONS_INDEX 3 1602 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index) 1603 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index) 1604 #else 1605 #define STATUS_STD_BUFF_CONS_INDEX 3 1606 #define STATUS_JUMBO_BUFF_CONS_INDEX 2 1607 #define STATUS_MINI_BUFF_CONS_INDEX 0 1608 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index) 1609 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index) 1610 #endif /* _BIG_ENDIAN */ 1611 1612 /* 1613 * Bits in the <flags_n_tag> word 1614 */ 1615 #define STATUS_FLAG_UPDATED 0x0000000100000000ull 1616 #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull 1617 #define STATUS_FLAG_ERROR 0x0000000400000000ull 1618 #define STATUS_TAG_MASK 0x00000000000000FFull 1619 1620 /* 1621 * The tag from the status block is fed back to Interrupt Mailbox 0 1622 * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This 1623 * lets the chip know what updates have been processed, so it can 1624 * reassert its interrupt if more updates have occurred since. 1625 * 1626 * These macros extract the tag from the <flags_n_tag> word, shift 1627 * it to the proper position in the Mailbox register, and provide 1628 * the complete values to write to INTERRUPT_MBOX_0_REG to disable 1629 * or enable interrupts 1630 */ 1631 #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK) 1632 #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24) 1633 #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1) 1634 #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0) 1635 1636 /* 1637 * Hardware-defined Statistics Block Offsets 1638 * 1639 * These are given in the manual as addresses in NIC memory, starting 1640 * from the NIC statistics area base address of 0x300; but here we 1641 * convert them into indexes into an array of (uint64_t)s, so we can 1642 * use them directly for accessing the copy of the statistics block 1643 * that the chip DMAs into main memory ... 1644 */ 1645 1646 #define KS_BASE 0x300 1647 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t)) 1648 1649 typedef enum { 1650 KS_ifHCInOctets = KS_ADDR(0x400), 1651 KS_etherStatsFragments = KS_ADDR(0x410), 1652 KS_ifHCInUcastPkts, 1653 KS_ifHCInMulticastPkts, 1654 KS_ifHCInBroadcastPkts, 1655 KS_dot3StatsFCSErrors, 1656 KS_dot3StatsAlignmentErrors, 1657 KS_xonPauseFramesReceived, 1658 KS_xoffPauseFramesReceived, 1659 KS_macControlFramesReceived, 1660 KS_xoffStateEntered, 1661 KS_dot3StatsFrameTooLongs, 1662 KS_etherStatsJabbers, 1663 KS_etherStatsUndersizePkts, 1664 KS_inRangeLengthError, 1665 KS_outRangeLengthError, 1666 KS_etherStatsPkts64Octets, 1667 KS_etherStatsPkts65to127Octets, 1668 KS_etherStatsPkts128to255Octets, 1669 KS_etherStatsPkts256to511Octets, 1670 KS_etherStatsPkts512to1023Octets, 1671 KS_etherStatsPkts1024to1518Octets, 1672 KS_etherStatsPkts1519to2047Octets, 1673 KS_etherStatsPkts2048to4095Octets, 1674 KS_etherStatsPkts4096to8191Octets, 1675 KS_etherStatsPkts8192to9022Octets, 1676 1677 KS_ifHCOutOctets = KS_ADDR(0x600), 1678 KS_etherStatsCollisions = KS_ADDR(0x610), 1679 KS_outXonSent, 1680 KS_outXoffSent, 1681 KS_flowControlDone, 1682 KS_dot3StatsInternalMacTransmitErrors, 1683 KS_dot3StatsSingleCollisionFrames, 1684 KS_dot3StatsMultipleCollisionFrames, 1685 KS_dot3StatsDeferredTransmissions, 1686 KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658), 1687 KS_dot3StatsLateCollisions, 1688 KS_dot3Collided2Times, 1689 KS_dot3Collided3Times, 1690 KS_dot3Collided4Times, 1691 KS_dot3Collided5Times, 1692 KS_dot3Collided6Times, 1693 KS_dot3Collided7Times, 1694 KS_dot3Collided8Times, 1695 KS_dot3Collided9Times, 1696 KS_dot3Collided10Times, 1697 KS_dot3Collided11Times, 1698 KS_dot3Collided12Times, 1699 KS_dot3Collided13Times, 1700 KS_dot3Collided14Times, 1701 KS_dot3Collided15Times, 1702 KS_ifHCOutUcastPkts, 1703 KS_ifHCOutMulticastPkts, 1704 KS_ifHCOutBroadcastPkts, 1705 KS_dot3StatsCarrierSenseErrors, 1706 KS_ifOutDiscards, 1707 KS_ifOutErrors, 1708 1709 KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */ 1710 KS_COSIfHCInPkts_2, 1711 KS_COSIfHCInPkts_3, 1712 KS_COSIfHCInPkts_4, 1713 KS_COSIfHCInPkts_5, 1714 KS_COSIfHCInPkts_6, 1715 KS_COSIfHCInPkts_7, 1716 KS_COSIfHCInPkts_8, 1717 KS_COSIfHCInPkts_9, 1718 KS_COSIfHCInPkts_10, 1719 KS_COSIfHCInPkts_11, 1720 KS_COSIfHCInPkts_12, 1721 KS_COSIfHCInPkts_13, 1722 KS_COSIfHCInPkts_14, 1723 KS_COSIfHCInPkts_15, 1724 KS_COSIfHCInPkts_16, 1725 KS_COSFramesDroppedDueToFilters, 1726 KS_nicDmaWriteQueueFull, 1727 KS_nicDmaWriteHighPriQueueFull, 1728 KS_nicNoMoreRxBDs, 1729 KS_ifInDiscards, 1730 KS_ifInErrors, 1731 KS_nicRecvThresholdHit, 1732 1733 KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */ 1734 KS_COSIfHCOutPkts_2, 1735 KS_COSIfHCOutPkts_3, 1736 KS_COSIfHCOutPkts_4, 1737 KS_COSIfHCOutPkts_5, 1738 KS_COSIfHCOutPkts_6, 1739 KS_COSIfHCOutPkts_7, 1740 KS_COSIfHCOutPkts_8, 1741 KS_COSIfHCOutPkts_9, 1742 KS_COSIfHCOutPkts_10, 1743 KS_COSIfHCOutPkts_11, 1744 KS_COSIfHCOutPkts_12, 1745 KS_COSIfHCOutPkts_13, 1746 KS_COSIfHCOutPkts_14, 1747 KS_COSIfHCOutPkts_15, 1748 KS_COSIfHCOutPkts_16, 1749 KS_nicDmaReadQueueFull, 1750 KS_nicDmaReadHighPriQueueFull, 1751 KS_nicSendDataCompQueueFull, 1752 KS_nicRingSetSendProdIndex, 1753 KS_nicRingStatusUpdate, 1754 KS_nicInterrupts, 1755 KS_nicAvoidedInterrupts, 1756 KS_nicSendThresholdHit, 1757 1758 KS_STATS_SIZE = KS_ADDR(0xb00) 1759 } bge_stats_offset_t; 1760 1761 /* 1762 * Hardware-defined Statistics Block 1763 * 1764 * Another view of the statistic block, as a array and a structure ... 1765 */ 1766 1767 typedef union { 1768 uint64_t a[KS_STATS_SIZE]; 1769 struct { 1770 uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)]; 1771 1772 uint64_t ifHCInOctets; /* 0x0400 */ 1773 uint64_t spare2[1]; 1774 uint64_t etherStatsFragments; 1775 uint64_t ifHCInUcastPkts; 1776 uint64_t ifHCInMulticastPkts; 1777 uint64_t ifHCInBroadcastPkts; 1778 uint64_t dot3StatsFCSErrors; 1779 uint64_t dot3StatsAlignmentErrors; 1780 uint64_t xonPauseFramesReceived; 1781 uint64_t xoffPauseFramesReceived; 1782 uint64_t macControlFramesReceived; 1783 uint64_t xoffStateEntered; 1784 uint64_t dot3StatsFrameTooLongs; 1785 uint64_t etherStatsJabbers; 1786 uint64_t etherStatsUndersizePkts; 1787 uint64_t inRangeLengthError; 1788 uint64_t outRangeLengthError; 1789 uint64_t etherStatsPkts64Octets; 1790 uint64_t etherStatsPkts65to127Octets; 1791 uint64_t etherStatsPkts128to255Octets; 1792 uint64_t etherStatsPkts256to511Octets; 1793 uint64_t etherStatsPkts512to1023Octets; 1794 uint64_t etherStatsPkts1024to1518Octets; 1795 uint64_t etherStatsPkts1519to2047Octets; 1796 uint64_t etherStatsPkts2048to4095Octets; 1797 uint64_t etherStatsPkts4096to8191Octets; 1798 uint64_t etherStatsPkts8192to9022Octets; 1799 uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)]; 1800 1801 uint64_t ifHCOutOctets; /* 0x0600 */ 1802 uint64_t spare4[1]; 1803 uint64_t etherStatsCollisions; 1804 uint64_t outXonSent; 1805 uint64_t outXoffSent; 1806 uint64_t flowControlDone; 1807 uint64_t dot3StatsInternalMacTransmitErrors; 1808 uint64_t dot3StatsSingleCollisionFrames; 1809 uint64_t dot3StatsMultipleCollisionFrames; 1810 uint64_t dot3StatsDeferredTransmissions; 1811 uint64_t spare5[1]; 1812 uint64_t dot3StatsExcessiveCollisions; 1813 uint64_t dot3StatsLateCollisions; 1814 uint64_t dot3Collided2Times; 1815 uint64_t dot3Collided3Times; 1816 uint64_t dot3Collided4Times; 1817 uint64_t dot3Collided5Times; 1818 uint64_t dot3Collided6Times; 1819 uint64_t dot3Collided7Times; 1820 uint64_t dot3Collided8Times; 1821 uint64_t dot3Collided9Times; 1822 uint64_t dot3Collided10Times; 1823 uint64_t dot3Collided11Times; 1824 uint64_t dot3Collided12Times; 1825 uint64_t dot3Collided13Times; 1826 uint64_t dot3Collided14Times; 1827 uint64_t dot3Collided15Times; 1828 uint64_t ifHCOutUcastPkts; 1829 uint64_t ifHCOutMulticastPkts; 1830 uint64_t ifHCOutBroadcastPkts; 1831 uint64_t dot3StatsCarrierSenseErrors; 1832 uint64_t ifOutDiscards; 1833 uint64_t ifOutErrors; 1834 uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)]; 1835 1836 uint64_t COSIfHCInPkts[16]; /* 0x0800 */ 1837 uint64_t COSFramesDroppedDueToFilters; 1838 uint64_t nicDmaWriteQueueFull; 1839 uint64_t nicDmaWriteHighPriQueueFull; 1840 uint64_t nicNoMoreRxBDs; 1841 uint64_t ifInDiscards; 1842 uint64_t ifInErrors; 1843 uint64_t nicRecvThresholdHit; 1844 uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)]; 1845 1846 uint64_t COSIfHCOutPkts[16]; /* 0x0900 */ 1847 uint64_t nicDmaReadQueueFull; 1848 uint64_t nicDmaReadHighPriQueueFull; 1849 uint64_t nicSendDataCompQueueFull; 1850 uint64_t nicRingSetSendProdIndex; 1851 uint64_t nicRingStatusUpdate; 1852 uint64_t nicInterrupts; 1853 uint64_t nicAvoidedInterrupts; 1854 uint64_t nicSendThresholdHit; 1855 uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)]; 1856 } s; 1857 } bge_statistics_t; 1858 1859 #define KS_STAT_REG_SIZE (0x1B) 1860 #define KS_STAT_REG_BASE (0x800) 1861 1862 typedef struct { 1863 uint32_t ifHCOutOctets; 1864 uint32_t etherStatsCollisions; 1865 uint32_t outXonSent; 1866 uint32_t outXoffSent; 1867 uint32_t dot3StatsInternalMacTransmitErrors; 1868 uint32_t dot3StatsSingleCollisionFrames; 1869 uint32_t dot3StatsMultipleCollisionFrames; 1870 uint32_t dot3StatsDeferredTransmissions; 1871 uint32_t dot3StatsExcessiveCollisions; 1872 uint32_t dot3StatsLateCollisions; 1873 uint32_t ifHCOutUcastPkts; 1874 uint32_t ifHCOutMulticastPkts; 1875 uint32_t ifHCOutBroadcastPkts; 1876 uint32_t ifHCInOctets; 1877 uint32_t etherStatsFragments; 1878 uint32_t ifHCInUcastPkts; 1879 uint32_t ifHCInMulticastPkts; 1880 uint32_t ifHCInBroadcastPkts; 1881 uint32_t dot3StatsFCSErrors; 1882 uint32_t dot3StatsAlignmentErrors; 1883 uint32_t xonPauseFramesReceived; 1884 uint32_t xoffPauseFramesReceived; 1885 uint32_t macControlFramesReceived; 1886 uint32_t xoffStateEntered; 1887 uint32_t dot3StatsFrameTooLongs; 1888 uint32_t etherStatsJabbers; 1889 uint32_t etherStatsUndersizePkts; 1890 } bge_statistics_reg_t; 1891 1892 1893 #ifdef BGE_IPMI_ASF 1894 1895 /* 1896 * Device internal memory entries 1897 */ 1898 1899 #define BGE_FIRMWARE_MAILBOX 0x0b50 1900 #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654 1901 #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b 1902 1903 1904 #define BGE_NIC_DATA_SIG_ADDR 0x0b54 1905 #define BGE_NIC_DATA_SIG 0x4b657654 1906 1907 1908 #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58 1909 1910 #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004 1911 #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008 1912 #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004 1913 #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008 1914 #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c 1915 1916 #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000 1917 #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010 1918 #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020 1919 #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030 1920 1921 #define BGE_NIC_CFG_ENABLE_WOL 0x000040 1922 #define BGE_NIC_CFG_ENABLE_ASF 0x000080 1923 #define BGE_NIC_CFG_EEPROM_WP 0x000100 1924 #define BGE_NIC_CFG_POWER_SAVING 0x000200 1925 #define BGE_NIC_CFG_SWAP_PORT 0x000800 1926 #define BGE_NIC_CFG_MINI_PCI 0x001000 1927 #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000 1928 #define BGE_NIC_CFG_5753_12x12 0x100000 1929 1930 1931 #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c 1932 1933 1934 #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74 1935 #define BGE_NIC_PHY_ID1_MASK 0xffff0000 1936 #define BGE_NIC_PHY_ID2_MASK 0x0000ffff 1937 1938 1939 #define BGE_CMD_MAILBOX 0x0b78 1940 #define BGE_CMD_NICDRV_ALIVE 0x00000001 1941 #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002 1942 #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003 1943 #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004 1944 1945 1946 #define BGE_CMD_LENGTH_MAILBOX 0x0b7c 1947 #define BGE_CMD_DATA_MAILBOX 0x0b80 1948 #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00 1949 1950 #define BGE_DRV_STATE_MAILBOX 0x0c04 1951 #define BGE_DRV_STATE_START 0x00000001 1952 #define BGE_DRV_STATE_START_DONE 0x80000001 1953 #define BGE_DRV_STATE_UNLOAD 0x00000002 1954 #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002 1955 #define BGE_DRV_STATE_WOL 0x00000003 1956 #define BGE_DRV_STATE_SUSPEND 0x00000004 1957 1958 1959 #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08 1960 #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001 1961 #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002 1962 1963 1964 #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14 1965 #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18 1966 1967 1968 /* 1969 * RX-RISC event register 1970 */ 1971 #define RX_RISC_EVENT_REG 0x6810 1972 #define RRER_ASF_EVENT 0x4000 1973 1974 #endif /* BGE_IPMI_ASF */ 1975 1976 #ifdef __cplusplus 1977 } 1978 #endif 1979 1980 #endif /* _SYS_BGE_HW_H */ 1981