1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include "bge_impl.h" 28 29 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 30 31 /* 32 * Future features ... ? 33 */ 34 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 35 #define BGE_IND_IO32 1 /* indirect access code */ 36 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 37 #define BGE_FLASH_IO32 1 /* FLASH access code */ 38 39 /* 40 * BGE MSI tunable: 41 * 42 * By default MSI is enabled on all supported platforms but it is disabled 43 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 44 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 45 */ 46 boolean_t bge_enable_msi = B_TRUE; 47 48 /* 49 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 50 */ 51 boolean_t bge_relaxed_ordering = B_TRUE; 52 53 /* 54 * Property names 55 */ 56 static char knownids_propname[] = "bge-known-subsystems"; 57 58 /* 59 * Patchable globals: 60 * 61 * bge_autorecover 62 * Enables/disables automatic recovery after fault detection 63 * 64 * bge_mlcr_default 65 * Value to program into the MLCR; controls the chip's GPIO pins 66 * 67 * bge_dma_{rd,wr}prio 68 * Relative priorities of DMA reads & DMA writes respectively. 69 * These may each be patched to any value 0-3. Equal values 70 * will give "fair" (round-robin) arbitration for PCI access. 71 * Unequal values will give one or the other function priority. 72 * 73 * bge_dma_rwctrl 74 * Value to put in the Read/Write DMA control register. See 75 * the Broadcom PRM for things you can fiddle with in this 76 * register ... 77 * 78 * bge_{tx,rx}_{count,ticks}_{norm,intr} 79 * Send/receive interrupt coalescing parameters. Counts are 80 * #s of descriptors, ticks are in microseconds. *norm* values 81 * apply between status updates/interrupts; the *intr* values 82 * refer to the 'during-interrupt' versions - see the PRM. 83 * 84 * NOTE: these values have been determined by measurement. They 85 * differ significantly from the values recommended in the PRM. 86 */ 87 static uint32_t bge_autorecover = 1; 88 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 89 90 static uint32_t bge_dma_rdprio = 1; 91 static uint32_t bge_dma_wrprio = 0; 92 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 93 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 94 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 95 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 96 97 uint32_t bge_rx_ticks_norm = 128; 98 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 99 uint32_t bge_rx_count_norm = 8; 100 uint32_t bge_tx_count_norm = 128; 101 102 static uint32_t bge_rx_ticks_intr = 128; 103 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 104 static uint32_t bge_rx_count_intr = 2; 105 static uint32_t bge_tx_count_intr = 0; 106 107 /* 108 * Memory pool configuration parameters. 109 * 110 * These are generally specific to each member of the chip family, since 111 * each one may have a different memory size/configuration. 112 * 113 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 114 * the driver from programming the various registers; instead they are left 115 * at their hardware defaults. This is the preferred option for later chips 116 * (5705+), whereas the older chips *required* these registers to be set, 117 * since the h/w default was 0 ;-( 118 */ 119 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 120 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 121 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 122 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 123 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 124 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 125 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 126 static uint32_t bge_mbuf_pool_len_5721 = 0; 127 128 /* 129 * Various high and low water marks, thresholds, etc ... 130 * 131 * Note: these are taken from revision 7 of the PRM, and some are different 132 * from both the values in earlier PRMs *and* those determined experimentally 133 * and used in earlier versions of this driver ... 134 */ 135 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 136 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 137 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 138 139 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 140 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 141 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 142 143 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 144 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 145 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 146 147 static uint32_t bge_watchdog_count = 1 << 16; 148 static uint16_t bge_dma_miss_limit = 20; 149 150 static uint32_t bge_stop_start_on_sync = 0; 151 152 boolean_t bge_jumbo_enable = B_TRUE; 153 154 /* 155 * bge_intr_max_loop controls the maximum loop number within bge_intr. 156 * When loading NIC with heavy network traffic, it is useful. 157 * Increasing this value could have positive effect to throughput, 158 * but it might also increase ticks of a bge ISR stick on CPU, which might 159 * lead to bad UI interactive experience. So tune this with caution. 160 */ 161 static int bge_intr_max_loop = 1; 162 163 /* 164 * ========== Low-level chip & ring buffer manipulation ========== 165 */ 166 167 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 168 169 170 /* 171 * Config space read-modify-write routines 172 */ 173 174 #if BGE_CFG_IO8 175 176 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 177 #pragma inline(bge_cfg_clr16) 178 179 static void 180 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 181 { 182 uint16_t regval; 183 184 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 185 (void *)bgep, regno, bits)); 186 187 regval = pci_config_get16(bgep->cfg_handle, regno); 188 189 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 190 (void *)bgep, regno, bits, regval, regval & ~bits)); 191 192 regval &= ~bits; 193 pci_config_put16(bgep->cfg_handle, regno, regval); 194 } 195 196 #endif /* BGE_CFG_IO8 */ 197 198 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 199 #pragma inline(bge_cfg_clr32) 200 201 static void 202 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 203 { 204 uint32_t regval; 205 206 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 207 (void *)bgep, regno, bits)); 208 209 regval = pci_config_get32(bgep->cfg_handle, regno); 210 211 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 212 (void *)bgep, regno, bits, regval, regval & ~bits)); 213 214 regval &= ~bits; 215 pci_config_put32(bgep->cfg_handle, regno, regval); 216 } 217 218 #if BGE_IND_IO32 219 220 /* 221 * Indirect access to registers & RISC scratchpads, using config space 222 * accesses only. 223 * 224 * This isn't currently used, but someday we might want to use it for 225 * restoring the Subsystem Device/Vendor registers (which aren't directly 226 * writable in Config Space), or for downloading firmware into the RISCs 227 * 228 * In any case there are endian issues to be resolved before this code is 229 * enabled; the bizarre way that bytes get twisted by this chip AND by 230 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 231 * it's been thoroughly tested for all access sizes on all supported 232 * architectures (SPARC *and* x86!). 233 */ 234 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 235 #pragma inline(bge_ind_get32) 236 237 uint32_t 238 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 239 { 240 uint32_t val; 241 242 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 243 244 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 245 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 246 247 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 248 (void *)bgep, regno, val)); 249 250 val = LE_32(val); 251 252 return (val); 253 } 254 255 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 256 #pragma inline(bge_ind_put32) 257 258 void 259 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 260 { 261 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 262 (void *)bgep, regno, val)); 263 264 val = LE_32(val); 265 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 266 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 267 } 268 269 #endif /* BGE_IND_IO32 */ 270 271 #if BGE_DEBUGGING 272 273 static void bge_pci_check(bge_t *bgep); 274 #pragma no_inline(bge_pci_check) 275 276 static void 277 bge_pci_check(bge_t *bgep) 278 { 279 uint16_t pcistatus; 280 281 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 282 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 283 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 284 (void *)bgep, pcistatus)); 285 } 286 287 #endif /* BGE_DEBUGGING */ 288 289 /* 290 * Perform first-stage chip (re-)initialisation, using only config-space 291 * accesses: 292 * 293 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 294 * returning the data in the structure pointed to by <idp>. 295 * + Configure the target-mode endianness (swap) options. 296 * + Disable interrupts and enable Memory Space accesses. 297 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 298 * 299 * This sequence is adapted from Broadcom document 570X-PG102-R, 300 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 301 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 302 * 303 * This function MUST be called before any non-config-space accesses 304 * are made; on this first call <enable_dma> is B_FALSE, and it 305 * effectively performs steps 3-1(!) of the initialisation sequence 306 * (the rest are not required but should be harmless). 307 * 308 * It MUST also be called after a chip reset, as this disables 309 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 310 * it is effectively performing steps 6-8. 311 */ 312 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 313 #pragma no_inline(bge_chip_cfg_init) 314 315 void 316 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 317 { 318 ddi_acc_handle_t handle; 319 uint16_t command; 320 uint32_t mhcr; 321 uint16_t value16; 322 int i; 323 324 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 325 (void *)bgep, (void *)cidp, enable_dma)); 326 327 /* 328 * Step 3: save PCI cache line size and subsystem vendor ID 329 * 330 * Read all the config-space registers that characterise the 331 * chip, specifically vendor/device/revision/subsystem vendor 332 * and subsystem device id. We expect (but don't check) that 333 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 334 * 335 * Also save all bus-transaction related registers (cache-line 336 * size, bus-grant/latency parameters, etc). Some of these are 337 * cleared by reset, so we'll have to restore them later. This 338 * comes from the Broadcom document 570X-PG102-R ... 339 * 340 * Note: Broadcom document 570X-PG102-R seems to be in error 341 * here w.r.t. the offsets of the Subsystem Vendor ID and 342 * Subsystem (Device) ID registers, which are the opposite way 343 * round according to the PCI standard. For good measure, we 344 * save/restore both anyway. 345 */ 346 handle = bgep->cfg_handle; 347 348 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 349 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 350 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 351 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 352 353 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 354 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 355 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 356 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 357 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 358 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 359 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 360 361 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 362 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 363 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 364 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 365 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 366 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 367 cidp->vendor, cidp->device, cidp->revision)); 368 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 369 cidp->subven, cidp->subdev, cidp->asic_rev)); 370 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 371 cidp->clsize, cidp->latency, cidp->command)); 372 373 /* 374 * Step 2 (also step 6): disable and clear interrupts. 375 * Steps 11-13: configure PIO endianness options, and enable 376 * indirect register access. We'll also select any other 377 * options controlled by the MHCR (e.g. tagged status, mask 378 * interrupt mode) at this stage ... 379 * 380 * Note: internally, the chip is 64-bit and BIG-endian, but 381 * since it talks to the host over a (LITTLE-endian) PCI bus, 382 * it normally swaps bytes around at the PCI interface. 383 * However, the PCI host bridge on SPARC systems normally 384 * swaps the byte lanes around too, since SPARCs are also 385 * BIG-endian. So it turns out that on SPARC, the right 386 * option is to tell the chip to swap (and the host bridge 387 * will swap back again), whereas on x86 we ask the chip 388 * NOT to swap, so the natural little-endianness of the 389 * PCI bus is assumed. Then the only thing that doesn't 390 * automatically work right is access to an 8-byte register 391 * by a little-endian host; but we don't want to set the 392 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 393 * accesses don't go where expected ;-( So we live with 394 * that, and perform word-swaps in software in the few cases 395 * where a chip register is defined as an 8-byte value -- 396 * see the code below for details ... 397 * 398 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 399 * very clear in the register description in the PRM, but 400 * Broadcom document 570X-PG104-R page 248 explains a little 401 * more (under "Broadcom Mask Mode"). The bit changes the way 402 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 403 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 404 * way as the 5700 did, which isn't very convenient. Setting 405 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 406 * bit do just what its name says -- MASK the PCI #INTA output 407 * (i.e. deassert the signal at the pin) leaving all internal 408 * state unchanged. This is much more convenient for our 409 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 410 * 411 * Note: the inconvenient semantics of the interrupt mailbox 412 * (nonzero disables and acknowledges/clears the interrupt, 413 * zero enables AND CLEARS it) would make race conditions 414 * likely in the interrupt handler: 415 * 416 * (1) acknowledge & disable interrupts 417 * (2) while (more to do) 418 * process packets 419 * (3) enable interrupts -- also clears pending 420 * 421 * If the chip received more packets and internally generated 422 * an interrupt between the check at (2) and the mbox write 423 * at (3), this interrupt would be lost :-( 424 * 425 * The best way to avoid this is to use TAGGED STATUS mode, 426 * where the chip includes a unique tag in each status block 427 * update, and the host, when re-enabling interrupts, passes 428 * the last tag it saw back to the chip; then the chip can 429 * see whether the host is truly up to date, and regenerate 430 * its interrupt if not. 431 */ 432 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 433 MHCR_ENABLE_TAGGED_STATUS_MODE | 434 MHCR_MASK_INTERRUPT_MODE | 435 MHCR_CLEAR_INTERRUPT_INTA; 436 437 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 438 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 439 440 #ifdef _BIG_ENDIAN 441 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 442 #endif /* _BIG_ENDIAN */ 443 444 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 445 446 #ifdef BGE_IPMI_ASF 447 bgep->asf_wordswapped = B_FALSE; 448 #endif 449 /* 450 * Step 1 (also step 7): Enable PCI Memory Space accesses 451 * Disable Memory Write/Invalidate 452 * Enable or disable Bus Mastering 453 * 454 * Note that all other bits are taken from the original value saved 455 * the first time through here, rather than from the current register 456 * value, 'cos that will have been cleared by a soft RESET since. 457 * In this way we preserve the OBP/nexus-parent's preferred settings 458 * of the parity-error and system-error enable bits across multiple 459 * chip RESETs. 460 */ 461 command = bgep->chipid.command | PCI_COMM_MAE; 462 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 463 if (enable_dma) 464 command |= PCI_COMM_ME; 465 /* 466 * on BCM5714 revision A0, false parity error gets generated 467 * due to a logic bug. Provide a workaround by disabling parity 468 * error. 469 */ 470 if (((cidp->device == DEVICE_ID_5714C) || 471 (cidp->device == DEVICE_ID_5714S)) && 472 (cidp->revision == REVISION_ID_5714_A0)) { 473 command &= ~PCI_COMM_PARITY_DETECT; 474 } 475 pci_config_put16(handle, PCI_CONF_COMM, command); 476 477 /* 478 * On some PCI-E device, there were instances when 479 * the device was still link training. 480 */ 481 if (bgep->chipid.pci_type == BGE_PCI_E) { 482 i = 0; 483 value16 = pci_config_get16(handle, PCI_CONF_COMM); 484 while ((value16 != command) && (i < 100)) { 485 drv_usecwait(200); 486 value16 = pci_config_get16(handle, PCI_CONF_COMM); 487 ++i; 488 } 489 } 490 491 /* 492 * Clear any remaining error status bits 493 */ 494 pci_config_put16(handle, PCI_CONF_STAT, ~0); 495 496 /* 497 * Do following if and only if the device is NOT BCM5714C OR 498 * BCM5715C 499 */ 500 if (!((cidp->device == DEVICE_ID_5714C) || 501 (cidp->device == DEVICE_ID_5715C))) { 502 /* 503 * Make sure these indirect-access registers are sane 504 * rather than random after power-up or reset 505 */ 506 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 507 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 508 } 509 /* 510 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 511 */ 512 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 513 514 if (cidp->pci_type == BGE_PCI_E) { 515 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 516 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723, 517 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 518 } else 519 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 520 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 521 } 522 } 523 524 #ifdef __amd64 525 /* 526 * Distinguish CPU types 527 * 528 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 529 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 530 * for PCI-Express based network interface card. This is the work-around 531 * for those nics. 532 */ 533 static boolean_t bge_get_em64t_type(void); 534 #pragma inline(bge_get_em64t_type) 535 536 static boolean_t 537 bge_get_em64t_type(void) 538 { 539 540 return (x86_vendor == X86_VENDOR_Intel); 541 } 542 #endif 543 544 /* 545 * Operating register get/set access routines 546 */ 547 548 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 549 #pragma inline(bge_reg_get32) 550 551 uint32_t 552 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 553 { 554 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 555 (void *)bgep, regno)); 556 557 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 558 } 559 560 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 561 #pragma inline(bge_reg_put32) 562 563 void 564 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 565 { 566 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 567 (void *)bgep, regno, data)); 568 569 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 570 BGE_PCICHK(bgep); 571 } 572 573 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 574 #pragma inline(bge_reg_set32) 575 576 void 577 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 578 { 579 uint32_t regval; 580 581 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 582 (void *)bgep, regno, bits)); 583 584 regval = bge_reg_get32(bgep, regno); 585 regval |= bits; 586 bge_reg_put32(bgep, regno, regval); 587 } 588 589 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 590 #pragma inline(bge_reg_clr32) 591 592 void 593 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 594 { 595 uint32_t regval; 596 597 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 598 (void *)bgep, regno, bits)); 599 600 regval = bge_reg_get32(bgep, regno); 601 regval &= ~bits; 602 bge_reg_put32(bgep, regno, regval); 603 } 604 605 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 606 #pragma inline(bge_reg_get64) 607 608 static uint64_t 609 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 610 { 611 uint64_t regval; 612 613 #ifdef __amd64 614 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 615 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 616 regval <<= 32; 617 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 618 } else { 619 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 620 } 621 #elif defined(__sparc) 622 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 623 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 624 regval <<= 32; 625 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 626 } else { 627 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 628 } 629 #else 630 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 631 #endif 632 633 #ifdef _LITTLE_ENDIAN 634 regval = (regval >> 32) | (regval << 32); 635 #endif /* _LITTLE_ENDIAN */ 636 637 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 638 (void *)bgep, regno, regval)); 639 640 return (regval); 641 } 642 643 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 644 #pragma inline(bge_reg_put64) 645 646 static void 647 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 648 { 649 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 650 (void *)bgep, regno, data)); 651 652 #ifdef _LITTLE_ENDIAN 653 data = ((data >> 32) | (data << 32)); 654 #endif /* _LITTLE_ENDIAN */ 655 656 #ifdef __amd64 657 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 658 ddi_put32(bgep->io_handle, 659 PIO_ADDR(bgep, regno), (uint32_t)data); 660 BGE_PCICHK(bgep); 661 ddi_put32(bgep->io_handle, 662 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 663 664 } else { 665 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 666 } 667 #elif defined(__sparc) 668 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 669 ddi_put32(bgep->io_handle, 670 PIO_ADDR(bgep, regno + 4), (uint32_t)data); 671 BGE_PCICHK(bgep); 672 ddi_put32(bgep->io_handle, 673 PIO_ADDR(bgep, regno), (uint32_t)(data >> 32)); 674 } else { 675 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 676 } 677 #else 678 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 679 #endif 680 681 BGE_PCICHK(bgep); 682 } 683 684 /* 685 * The DDI doesn't provide get/put functions for 128 bit data 686 * so we put RCBs out as two 64-bit chunks instead. 687 */ 688 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 689 #pragma inline(bge_reg_putrcb) 690 691 static void 692 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 693 { 694 uint64_t *p; 695 696 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 697 (void *)bgep, addr, rcbp->host_ring_addr, 698 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 699 700 ASSERT((addr % sizeof (*rcbp)) == 0); 701 702 p = (void *)rcbp; 703 bge_reg_put64(bgep, addr, *p++); 704 bge_reg_put64(bgep, addr+8, *p); 705 } 706 707 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 708 #pragma inline(bge_mbx_put) 709 710 void 711 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 712 { 713 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 714 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 715 716 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 717 (void *)bgep, regno, data)); 718 719 /* 720 * Mailbox registers are nominally 64 bits on the 5701, but 721 * the MSW isn't used. On the 5703, they're only 32 bits 722 * anyway. So here we just write the lower(!) 32 bits - 723 * remembering that the chip is big-endian, even though the 724 * PCI bus is little-endian ... 725 */ 726 #ifdef _BIG_ENDIAN 727 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 728 #else 729 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 730 #endif /* _BIG_ENDIAN */ 731 BGE_PCICHK(bgep); 732 } 733 734 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 735 #pragma inline(bge_mbx_get) 736 737 uint32_t 738 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 739 { 740 uint32_t val32; 741 742 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 743 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 744 745 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 746 (void *)bgep, regno)); 747 748 #ifdef _BIG_ENDIAN 749 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 750 #else 751 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 752 #endif /* _BIG_ENDIAN */ 753 BGE_PCICHK(bgep); 754 755 return (val32); 756 } 757 758 759 #if BGE_DEBUGGING 760 761 void bge_led_mark(bge_t *bgep); 762 #pragma no_inline(bge_led_mark) 763 764 void 765 bge_led_mark(bge_t *bgep) 766 { 767 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 768 LED_CONTROL_1000MBPS_LED | 769 LED_CONTROL_100MBPS_LED | 770 LED_CONTROL_10MBPS_LED; 771 772 /* 773 * Blink all three LINK LEDs on simultaneously, then all off, 774 * then restore to automatic hardware control. This is used 775 * in laboratory testing to trigger a logic analyser or scope. 776 */ 777 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 778 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 779 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 780 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 781 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 782 } 783 784 #endif /* BGE_DEBUGGING */ 785 786 /* 787 * NIC on-chip memory access routines 788 * 789 * Only 32K of NIC memory is visible at a time, controlled by the 790 * Memory Window Base Address Register (in PCI config space). Once 791 * this is set, the 32K region of NIC-local memory that it refers 792 * to can be directly addressed in the upper 32K of the 64K of PCI 793 * memory space used for the device. 794 */ 795 796 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 797 #pragma inline(bge_nic_setwin) 798 799 static void 800 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 801 { 802 chip_id_t *cidp; 803 804 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 805 (void *)bgep, base)); 806 807 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 808 809 /* 810 * Don't do repeated zero data writes, 811 * if the device is BCM5714C/15C. 812 */ 813 cidp = &bgep->chipid; 814 if ((cidp->device == DEVICE_ID_5714C) || 815 (cidp->device == DEVICE_ID_5715C)) { 816 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 817 return; 818 /* Adjust lastWriteZeroData */ 819 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 820 B_TRUE : B_FALSE); 821 } 822 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 823 } 824 825 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 826 #pragma inline(bge_nic_get32) 827 828 static uint32_t 829 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 830 { 831 uint32_t data; 832 833 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 834 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 835 /* workaround for word swap error */ 836 if (addr & 4) 837 addr = addr - 4; 838 else 839 addr = addr + 4; 840 } 841 #endif 842 843 #ifdef __sparc 844 data = bge_nic_read32(bgep, addr); 845 #else 846 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 847 addr &= MWBAR_GRANULE_MASK; 848 addr += NIC_MEM_WINDOW_OFFSET; 849 850 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 851 #endif 852 853 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 854 (void *)bgep, addr, data)); 855 856 return (data); 857 } 858 859 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 860 #pragma inline(bge_nic_put32) 861 862 void 863 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 864 { 865 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 866 (void *)bgep, addr, data)); 867 868 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 869 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 870 /* workaround for word swap error */ 871 if (addr & 4) 872 addr = addr - 4; 873 else 874 addr = addr + 4; 875 } 876 #endif 877 878 #ifdef __sparc 879 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 880 data = LE_32(data); 881 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 882 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 883 #else 884 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 885 addr &= MWBAR_GRANULE_MASK; 886 addr += NIC_MEM_WINDOW_OFFSET; 887 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 888 BGE_PCICHK(bgep); 889 #endif 890 } 891 892 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 893 #pragma inline(bge_nic_get64) 894 895 static uint64_t 896 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 897 { 898 uint64_t data; 899 900 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 901 addr &= MWBAR_GRANULE_MASK; 902 addr += NIC_MEM_WINDOW_OFFSET; 903 904 #ifdef __amd64 905 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 906 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 907 data <<= 32; 908 data |= ddi_get32(bgep->io_handle, 909 PIO_ADDR(bgep, addr + 4)); 910 } else { 911 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 912 } 913 #elif defined(__sparc) 914 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 915 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 916 data <<= 32; 917 data |= ddi_get32(bgep->io_handle, 918 PIO_ADDR(bgep, addr + 4)); 919 } else { 920 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 921 } 922 #else 923 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 924 #endif 925 926 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 927 (void *)bgep, addr, data)); 928 929 return (data); 930 } 931 932 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 933 #pragma inline(bge_nic_put64) 934 935 static void 936 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 937 { 938 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 939 (void *)bgep, addr, data)); 940 941 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 942 addr &= MWBAR_GRANULE_MASK; 943 addr += NIC_MEM_WINDOW_OFFSET; 944 945 #ifdef __amd64 946 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 947 ddi_put32(bgep->io_handle, 948 PIO_ADDR(bgep, addr), (uint32_t)data); 949 BGE_PCICHK(bgep); 950 ddi_put32(bgep->io_handle, 951 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 952 } else { 953 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 954 } 955 #elif defined(__sparc) 956 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 957 ddi_put32(bgep->io_handle, 958 PIO_ADDR(bgep, addr + 4), (uint32_t)data); 959 BGE_PCICHK(bgep); 960 ddi_put32(bgep->io_handle, 961 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32)); 962 } else { 963 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 964 } 965 #else 966 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 967 #endif 968 969 BGE_PCICHK(bgep); 970 } 971 972 /* 973 * The DDI doesn't provide get/put functions for 128 bit data 974 * so we put RCBs out as two 64-bit chunks instead. 975 */ 976 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 977 #pragma inline(bge_nic_putrcb) 978 979 static void 980 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 981 { 982 uint64_t *p; 983 984 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 985 (void *)bgep, addr, rcbp->host_ring_addr, 986 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 987 988 ASSERT((addr % sizeof (*rcbp)) == 0); 989 990 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 991 addr &= MWBAR_GRANULE_MASK; 992 addr += NIC_MEM_WINDOW_OFFSET; 993 994 p = (void *)rcbp; 995 #ifdef __amd64 996 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 997 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 998 (uint32_t)(*p)); 999 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1000 (uint32_t)(*p >> 32)); 1001 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1002 (uint32_t)(*(p + 1))); 1003 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1004 (uint32_t)(*p >> 32)); 1005 1006 } else { 1007 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1008 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1009 } 1010 #elif defined(__sparc) 1011 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 1012 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1013 (uint32_t)(*p)); 1014 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1015 (uint32_t)(*p >> 32)); 1016 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1017 (uint32_t)(*(p + 1))); 1018 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1019 (uint32_t)(*p >> 32)); 1020 } else { 1021 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1022 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1023 } 1024 #else 1025 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1026 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1027 #endif 1028 1029 BGE_PCICHK(bgep); 1030 } 1031 1032 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1033 #pragma inline(bge_nic_zero) 1034 1035 static void 1036 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1037 { 1038 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1039 (void *)bgep, addr, nbytes)); 1040 1041 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1042 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1043 1044 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1045 addr &= MWBAR_GRANULE_MASK; 1046 addr += NIC_MEM_WINDOW_OFFSET; 1047 1048 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1049 nbytes, 1, DDI_DATA_SZ08_ACC); 1050 BGE_PCICHK(bgep); 1051 } 1052 1053 /* 1054 * MII (PHY) register get/set access routines 1055 * 1056 * These use the chip's MII auto-access method, controlled by the 1057 * MII Communication register at 0x044c, so the CPU doesn't have 1058 * to fiddle with the individual bits. 1059 */ 1060 1061 #undef BGE_DBG 1062 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1063 1064 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1065 uint16_t data, uint32_t cmd); 1066 #pragma no_inline(bge_mii_access) 1067 1068 static uint16_t 1069 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1070 { 1071 uint32_t timeout; 1072 uint32_t regval1; 1073 uint32_t regval2; 1074 1075 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1076 (void *)bgep, regno, data, cmd)); 1077 1078 ASSERT(mutex_owned(bgep->genlock)); 1079 1080 /* 1081 * Assemble the command ... 1082 */ 1083 cmd |= data << MI_COMMS_DATA_SHIFT; 1084 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1085 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1086 cmd |= MI_COMMS_START; 1087 1088 /* 1089 * Wait for any command already in progress ... 1090 * 1091 * Note: this *shouldn't* ever find that there is a command 1092 * in progress, because we already hold the <genlock> mutex. 1093 * Nonetheless, we have sometimes seen the MI_COMMS_START 1094 * bit set here -- it seems that the chip can initiate MII 1095 * accesses internally, even with polling OFF. 1096 */ 1097 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1098 for (timeout = 100; ; ) { 1099 if ((regval2 & MI_COMMS_START) == 0) { 1100 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1101 break; 1102 } 1103 if (--timeout == 0) 1104 break; 1105 drv_usecwait(10); 1106 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1107 } 1108 1109 if (timeout == 0) 1110 return ((uint16_t)~0u); 1111 1112 if (timeout != 100) 1113 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1114 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1115 cmd, 10*(100-timeout), regval1, regval2)); 1116 1117 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1118 for (timeout = 1000; ; ) { 1119 if ((regval1 & MI_COMMS_START) == 0) 1120 break; 1121 if (--timeout == 0) 1122 break; 1123 drv_usecwait(10); 1124 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1125 } 1126 1127 /* 1128 * Drop out early if the READ FAILED bit is set -- this chip 1129 * could be a 5703/4S, with a SerDes instead of a PHY! 1130 */ 1131 if (regval2 & MI_COMMS_READ_FAILED) 1132 return ((uint16_t)~0u); 1133 1134 if (timeout == 0) 1135 return ((uint16_t)~0u); 1136 1137 /* 1138 * The PRM says to wait 5us after seeing the START bit clear 1139 * and then re-read the register to get the final value of the 1140 * data field, in order to avoid a race condition where the 1141 * START bit is clear but the data field isn't yet valid. 1142 * 1143 * Note: we don't actually seem to be encounter this race; 1144 * except when the START bit is seen set again (see below), 1145 * the data field doesn't change during this 5us interval. 1146 */ 1147 drv_usecwait(5); 1148 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1149 1150 /* 1151 * Unfortunately, when following the PRMs instructions above, 1152 * we have occasionally seen the START bit set again(!) in the 1153 * value read after the 5us delay. This seems to be due to the 1154 * chip autonomously starting another MII access internally. 1155 * In such cases, the command/data/etc fields relate to the 1156 * internal command, rather than the one that we thought had 1157 * just finished. So in this case, we fall back to returning 1158 * the data from the original read that showed START clear. 1159 */ 1160 if (regval2 & MI_COMMS_START) { 1161 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1162 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1163 cmd, regval1, regval2)); 1164 regval2 = regval1; 1165 } 1166 1167 if (regval2 & MI_COMMS_START) 1168 return ((uint16_t)~0u); 1169 1170 if (regval2 & MI_COMMS_READ_FAILED) 1171 return ((uint16_t)~0u); 1172 1173 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1174 } 1175 1176 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1177 #pragma no_inline(bge_mii_get16) 1178 1179 uint16_t 1180 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1181 { 1182 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1183 (void *)bgep, regno)); 1184 1185 ASSERT(mutex_owned(bgep->genlock)); 1186 1187 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1188 (regno == MII_1000BASE_T_CONTROL))) 1189 return (0); 1190 1191 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1192 } 1193 1194 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1195 #pragma no_inline(bge_mii_put16) 1196 1197 void 1198 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1199 { 1200 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1201 (void *)bgep, regno, data)); 1202 1203 ASSERT(mutex_owned(bgep->genlock)); 1204 1205 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1206 (regno == MII_1000BASE_T_CONTROL))) 1207 return; 1208 1209 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1210 } 1211 1212 #undef BGE_DBG 1213 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1214 1215 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1216 1217 /* 1218 * Basic SEEPROM get/set access routine 1219 * 1220 * This uses the chip's SEEPROM auto-access method, controlled by the 1221 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1222 * doesn't have to fiddle with the individual bits. 1223 * 1224 * The caller should hold <genlock> and *also* have already acquired 1225 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1226 * 1227 * Return value: 1228 * 0 on success, 1229 * ENODATA on access timeout (maybe retryable: device may just be busy) 1230 * EPROTO on other h/w or s/w errors. 1231 * 1232 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1233 * from a (successful) SEEPROM_ACCESS_READ. 1234 */ 1235 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1236 uint32_t *dp); 1237 #pragma no_inline(bge_seeprom_access) 1238 1239 static int 1240 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1241 { 1242 uint32_t tries; 1243 uint32_t regval; 1244 1245 ASSERT(mutex_owned(bgep->genlock)); 1246 1247 /* 1248 * On the newer chips that support both SEEPROM & Flash, we need 1249 * to specifically enable SEEPROM access (Flash is the default). 1250 * On older chips, we don't; SEEPROM is the only NVtype supported, 1251 * and the NVM control registers don't exist ... 1252 */ 1253 switch (bgep->chipid.nvtype) { 1254 case BGE_NVTYPE_NONE: 1255 case BGE_NVTYPE_UNKNOWN: 1256 _NOTE(NOTREACHED) 1257 case BGE_NVTYPE_SEEPROM: 1258 break; 1259 1260 case BGE_NVTYPE_LEGACY_SEEPROM: 1261 case BGE_NVTYPE_UNBUFFERED_FLASH: 1262 case BGE_NVTYPE_BUFFERED_FLASH: 1263 default: 1264 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1265 NVM_CFG1_LEGACY_SEEPROM_MODE); 1266 break; 1267 } 1268 1269 /* 1270 * Check there's no command in progress. 1271 * 1272 * Note: this *shouldn't* ever find that there is a command 1273 * in progress, because we already hold the <genlock> mutex. 1274 * Also, to ensure we don't have a conflict with the chip's 1275 * internal firmware or a process accessing the same (shared) 1276 * SEEPROM through the other port of a 5704, we've already 1277 * been through the "software arbitration" protocol. 1278 * So this is just a final consistency check: we shouldn't 1279 * see EITHER the START bit (command started but not complete) 1280 * OR the COMPLETE bit (command completed but not cleared). 1281 */ 1282 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1283 if (regval & SEEPROM_ACCESS_START) 1284 return (EPROTO); 1285 if (regval & SEEPROM_ACCESS_COMPLETE) 1286 return (EPROTO); 1287 1288 /* 1289 * Assemble the command ... 1290 */ 1291 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1292 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1293 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1294 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1295 cmd |= SEEPROM_ACCESS_START; 1296 cmd |= SEEPROM_ACCESS_COMPLETE; 1297 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1298 1299 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1300 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1301 1302 /* 1303 * By observation, a successful access takes ~20us on a 5703/4, 1304 * but apparently much longer (up to 1000us) on the obsolescent 1305 * BCM5700/BCM5701. We want to be sure we don't get any false 1306 * timeouts here; but OTOH, we don't want a bogus access to lock 1307 * out interrupts for longer than necessary. So we'll allow up 1308 * to 1000us ... 1309 */ 1310 for (tries = 0; tries < 1000; ++tries) { 1311 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1312 if (regval & SEEPROM_ACCESS_COMPLETE) 1313 break; 1314 drv_usecwait(1); 1315 } 1316 1317 if (regval & SEEPROM_ACCESS_COMPLETE) { 1318 /* 1319 * All OK; read the SEEPROM data register, then write back 1320 * the value read from the address register in order to 1321 * clear the <complete> bit and leave the SEEPROM access 1322 * state machine idle, ready for the next access ... 1323 */ 1324 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1325 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1326 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1327 return (0); 1328 } 1329 1330 /* 1331 * Hmm ... what happened here? 1332 * 1333 * Most likely, the user addressed a non-existent SEEPROM. Or 1334 * maybe the SEEPROM was busy internally (e.g. processing a write) 1335 * and didn't respond to being addressed. Either way, it's left 1336 * the SEEPROM access state machine wedged. So we'll reset it 1337 * before we leave, so it's ready for next time ... 1338 */ 1339 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1340 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1341 return (ENODATA); 1342 } 1343 1344 /* 1345 * Basic Flash get/set access routine 1346 * 1347 * These use the chip's Flash auto-access method, controlled by the 1348 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1349 * fiddle with the individual bits. 1350 * 1351 * The caller should hold <genlock> and *also* have already acquired 1352 * the right to access the Flash, via bge_nvmem_acquire() above. 1353 * 1354 * Return value: 1355 * 0 on success, 1356 * ENODATA on access timeout (maybe retryable: device may just be busy) 1357 * ENODEV if the NVmem device is missing or otherwise unusable 1358 * 1359 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1360 * from a (successful) NVM_FLASH_CMD_RD. 1361 */ 1362 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1363 uint32_t *dp); 1364 #pragma no_inline(bge_flash_access) 1365 1366 static int 1367 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1368 { 1369 uint32_t tries; 1370 uint32_t regval; 1371 1372 ASSERT(mutex_owned(bgep->genlock)); 1373 1374 /* 1375 * On the newer chips that support both SEEPROM & Flash, we need 1376 * to specifically disable SEEPROM access while accessing Flash. 1377 * The older chips don't support Flash, and the NVM registers don't 1378 * exist, so we shouldn't be here at all! 1379 */ 1380 switch (bgep->chipid.nvtype) { 1381 case BGE_NVTYPE_NONE: 1382 case BGE_NVTYPE_UNKNOWN: 1383 _NOTE(NOTREACHED) 1384 case BGE_NVTYPE_SEEPROM: 1385 return (ENODEV); 1386 1387 case BGE_NVTYPE_LEGACY_SEEPROM: 1388 case BGE_NVTYPE_UNBUFFERED_FLASH: 1389 case BGE_NVTYPE_BUFFERED_FLASH: 1390 default: 1391 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1392 NVM_CFG1_LEGACY_SEEPROM_MODE); 1393 break; 1394 } 1395 1396 /* 1397 * Assemble the command ... 1398 */ 1399 addr &= NVM_FLASH_ADDR_MASK; 1400 cmd |= NVM_FLASH_CMD_DOIT; 1401 cmd |= NVM_FLASH_CMD_FIRST; 1402 cmd |= NVM_FLASH_CMD_LAST; 1403 cmd |= NVM_FLASH_CMD_DONE; 1404 1405 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1406 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1407 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1408 1409 /* 1410 * Allow up to 1000ms ... 1411 */ 1412 for (tries = 0; tries < 1000; ++tries) { 1413 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1414 if (regval & NVM_FLASH_CMD_DONE) 1415 break; 1416 drv_usecwait(1); 1417 } 1418 1419 if (regval & NVM_FLASH_CMD_DONE) { 1420 /* 1421 * All OK; read the data from the Flash read register 1422 */ 1423 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1424 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1425 return (0); 1426 } 1427 1428 /* 1429 * Hmm ... what happened here? 1430 * 1431 * Most likely, the user addressed a non-existent Flash. Or 1432 * maybe the Flash was busy internally (e.g. processing a write) 1433 * and didn't respond to being addressed. Either way, there's 1434 * nothing we can here ... 1435 */ 1436 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1437 return (ENODATA); 1438 } 1439 1440 /* 1441 * The next two functions regulate access to the NVram (if fitted). 1442 * 1443 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1444 * (SPI) interface, but they can be accessed through either port. These 1445 * are managed by different instance of this driver and have no software 1446 * state in common. 1447 * 1448 * In addition (and even on a single core chip) the chip's internal 1449 * firmware can access the SEEPROM/Flash, most notably after a RESET 1450 * when it may download code to run internally. 1451 * 1452 * So we need to arbitrate between these various software agents. For 1453 * this purpose, the chip provides the Software Arbitration Register, 1454 * which implements hardware(!) arbitration. 1455 * 1456 * This functionality didn't exist on older (5700/5701) chips, so there's 1457 * nothing we can do by way of arbitration on those; also, if there's no 1458 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1459 * nothing to do. 1460 * 1461 * The internal firmware appears to use Request 0, which is the highest 1462 * priority. So we'd like to use Request 2, leaving one higher and one 1463 * lower for any future developments ... but apparently this doesn't 1464 * always work. So for now, the code uses Request 1 ;-( 1465 */ 1466 1467 #define NVM_READ_REQ NVM_READ_REQ1 1468 #define NVM_RESET_REQ NVM_RESET_REQ1 1469 #define NVM_SET_REQ NVM_SET_REQ1 1470 1471 static void bge_nvmem_relinquish(bge_t *bgep); 1472 #pragma no_inline(bge_nvmem_relinquish) 1473 1474 static void 1475 bge_nvmem_relinquish(bge_t *bgep) 1476 { 1477 ASSERT(mutex_owned(bgep->genlock)); 1478 1479 switch (bgep->chipid.nvtype) { 1480 case BGE_NVTYPE_NONE: 1481 case BGE_NVTYPE_UNKNOWN: 1482 _NOTE(NOTREACHED) 1483 return; 1484 1485 case BGE_NVTYPE_SEEPROM: 1486 /* 1487 * No arbitration performed, no release needed 1488 */ 1489 return; 1490 1491 case BGE_NVTYPE_LEGACY_SEEPROM: 1492 case BGE_NVTYPE_UNBUFFERED_FLASH: 1493 case BGE_NVTYPE_BUFFERED_FLASH: 1494 default: 1495 break; 1496 } 1497 1498 /* 1499 * Our own request should be present (whether or not granted) ... 1500 */ 1501 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1502 1503 /* 1504 * ... this will make it go away. 1505 */ 1506 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1507 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1508 } 1509 1510 /* 1511 * Arbitrate for access to the NVmem, if necessary 1512 * 1513 * Return value: 1514 * 0 on success 1515 * EAGAIN if the device is in use (retryable) 1516 * ENODEV if the NVmem device is missing or otherwise unusable 1517 */ 1518 static int bge_nvmem_acquire(bge_t *bgep); 1519 #pragma no_inline(bge_nvmem_acquire) 1520 1521 static int 1522 bge_nvmem_acquire(bge_t *bgep) 1523 { 1524 uint32_t regval; 1525 uint32_t tries; 1526 1527 ASSERT(mutex_owned(bgep->genlock)); 1528 1529 switch (bgep->chipid.nvtype) { 1530 case BGE_NVTYPE_NONE: 1531 case BGE_NVTYPE_UNKNOWN: 1532 /* 1533 * Access denied: no (recognisable) device fitted 1534 */ 1535 return (ENODEV); 1536 1537 case BGE_NVTYPE_SEEPROM: 1538 /* 1539 * Access granted: no arbitration needed (or possible) 1540 */ 1541 return (0); 1542 1543 case BGE_NVTYPE_LEGACY_SEEPROM: 1544 case BGE_NVTYPE_UNBUFFERED_FLASH: 1545 case BGE_NVTYPE_BUFFERED_FLASH: 1546 default: 1547 /* 1548 * Access conditional: conduct arbitration protocol 1549 */ 1550 break; 1551 } 1552 1553 /* 1554 * We're holding the per-port mutex <genlock>, so no-one other 1555 * thread can be attempting to access the NVmem through *this* 1556 * port. But it could be in use by the *other* port (of a 5704), 1557 * or by the chip's internal firmware, so we have to go through 1558 * the full (hardware) arbitration protocol ... 1559 * 1560 * Note that *because* we're holding <genlock>, the interrupt handler 1561 * won't be able to progress. So we're only willing to spin for a 1562 * fairly short time. Specifically: 1563 * 1564 * We *must* wait long enough for the hardware to resolve all 1565 * requests and determine the winner. Fortunately, this is 1566 * "almost instantaneous", even as observed by GHz CPUs. 1567 * 1568 * A successful access by another Solaris thread (via either 1569 * port) typically takes ~20us. So waiting a bit longer than 1570 * that will give a good chance of success, if the other user 1571 * *is* another thread on the other port. 1572 * 1573 * However, the internal firmware can hold on to the NVmem 1574 * for *much* longer: at least 10 milliseconds just after a 1575 * RESET, and maybe even longer if the NVmem actually contains 1576 * code to download and run on the internal CPUs. 1577 * 1578 * So, we'll allow 50us; if that's not enough then it's up to the 1579 * caller to retry later (hence the choice of return code EAGAIN). 1580 */ 1581 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1582 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1583 1584 for (tries = 0; tries < 50; ++tries) { 1585 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1586 if (regval & NVM_WON_REQ1) 1587 break; 1588 drv_usecwait(1); 1589 } 1590 1591 if (regval & NVM_WON_REQ1) { 1592 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1593 return (0); 1594 } 1595 1596 /* 1597 * Somebody else must be accessing the NVmem, so abandon our 1598 * attempt take control of it. The caller can try again later ... 1599 */ 1600 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1601 bge_nvmem_relinquish(bgep); 1602 return (EAGAIN); 1603 } 1604 1605 /* 1606 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1607 * write protect line in such a way that the NVmem is protected when 1608 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1609 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1610 * 1611 * Note: there's only one set of GPIO pins on a 5704, even though they 1612 * can be accessed through either port. So the chip has to resolve what 1613 * happens if the two ports program a single pin differently ... the rule 1614 * it uses is that if the ports disagree about the *direction* of a pin, 1615 * "output" wins over "input", but if they disagree about its *value* as 1616 * an output, then the pin is TRISTATED instead! In such a case, no-one 1617 * wins, and the external signal does whatever the external circuitry 1618 * defines as the default -- which we've assumed is the PROTECTED state. 1619 * So, we always change GPIO1 back to being an *input* whenever we're not 1620 * specifically using it to unprotect the NVmem. This allows either port 1621 * to update the NVmem, although obviously only one at a time! 1622 * 1623 * The caller should hold <genlock> and *also* have already acquired the 1624 * right to access the NVmem, via bge_nvmem_acquire() above. 1625 */ 1626 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1627 #pragma inline(bge_nvmem_protect) 1628 1629 static void 1630 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1631 { 1632 uint32_t regval; 1633 1634 ASSERT(mutex_owned(bgep->genlock)); 1635 1636 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1637 if (protect) { 1638 regval |= MLCR_MISC_PINS_OUTPUT_1; 1639 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1640 } else { 1641 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1642 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1643 } 1644 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1645 } 1646 1647 /* 1648 * Now put it all together ... 1649 * 1650 * Try to acquire control of the NVmem; if successful, then: 1651 * unprotect it (if we want to write to it) 1652 * perform the requested access 1653 * reprotect it (after a write) 1654 * relinquish control 1655 * 1656 * Return value: 1657 * 0 on success, 1658 * EAGAIN if the device is in use (retryable) 1659 * ENODATA on access timeout (maybe retryable: device may just be busy) 1660 * ENODEV if the NVmem device is missing or otherwise unusable 1661 * EPROTO on other h/w or s/w errors. 1662 */ 1663 static int 1664 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1665 { 1666 int err; 1667 1668 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1669 switch (cmd) { 1670 case BGE_SEE_READ: 1671 err = bge_seeprom_access(bgep, 1672 SEEPROM_ACCESS_READ, addr, dp); 1673 break; 1674 1675 case BGE_SEE_WRITE: 1676 bge_nvmem_protect(bgep, B_FALSE); 1677 err = bge_seeprom_access(bgep, 1678 SEEPROM_ACCESS_WRITE, addr, dp); 1679 bge_nvmem_protect(bgep, B_TRUE); 1680 break; 1681 1682 case BGE_FLASH_READ: 1683 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1684 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1685 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1686 bge_reg_set32(bgep, NVM_ACCESS_REG, 1687 NVM_ACCESS_ENABLE); 1688 } 1689 err = bge_flash_access(bgep, 1690 NVM_FLASH_CMD_RD, addr, dp); 1691 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1692 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1693 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1694 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1695 NVM_ACCESS_ENABLE); 1696 } 1697 break; 1698 1699 case BGE_FLASH_WRITE: 1700 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1701 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1702 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1703 bge_reg_set32(bgep, NVM_ACCESS_REG, 1704 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1705 } 1706 bge_nvmem_protect(bgep, B_FALSE); 1707 err = bge_flash_access(bgep, 1708 NVM_FLASH_CMD_WR, addr, dp); 1709 bge_nvmem_protect(bgep, B_TRUE); 1710 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1711 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1712 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1713 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1714 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1715 } 1716 1717 break; 1718 1719 default: 1720 _NOTE(NOTREACHED) 1721 break; 1722 } 1723 bge_nvmem_relinquish(bgep); 1724 } 1725 1726 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1727 return (err); 1728 } 1729 1730 /* 1731 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1732 */ 1733 static uint64_t bge_get_nvmac(bge_t *bgep); 1734 #pragma no_inline(bge_get_nvmac) 1735 1736 static uint64_t 1737 bge_get_nvmac(bge_t *bgep) 1738 { 1739 uint32_t mac_high; 1740 uint32_t mac_low; 1741 uint32_t addr; 1742 uint32_t cmd; 1743 uint64_t mac; 1744 1745 BGE_TRACE(("bge_get_nvmac($%p)", 1746 (void *)bgep)); 1747 1748 switch (bgep->chipid.nvtype) { 1749 case BGE_NVTYPE_NONE: 1750 case BGE_NVTYPE_UNKNOWN: 1751 default: 1752 return (0ULL); 1753 1754 case BGE_NVTYPE_SEEPROM: 1755 case BGE_NVTYPE_LEGACY_SEEPROM: 1756 cmd = BGE_SEE_READ; 1757 break; 1758 1759 case BGE_NVTYPE_UNBUFFERED_FLASH: 1760 case BGE_NVTYPE_BUFFERED_FLASH: 1761 cmd = BGE_FLASH_READ; 1762 break; 1763 } 1764 1765 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 1766 addr = NVMEM_DATA_MAC_ADDRESS_5906; 1767 else 1768 addr = NVMEM_DATA_MAC_ADDRESS; 1769 1770 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1771 return (0ULL); 1772 addr += 4; 1773 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1774 return (0ULL); 1775 1776 /* 1777 * The Broadcom chip is natively BIG-endian, so that's how the 1778 * MAC address is represented in NVmem. We may need to swap it 1779 * around on a little-endian host ... 1780 */ 1781 #ifdef _BIG_ENDIAN 1782 mac = mac_high; 1783 mac = mac << 32; 1784 mac |= mac_low; 1785 #else 1786 mac = BGE_BSWAP_32(mac_high); 1787 mac = mac << 32; 1788 mac |= BGE_BSWAP_32(mac_low); 1789 #endif /* _BIG_ENDIAN */ 1790 1791 return (mac); 1792 } 1793 1794 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1795 1796 /* 1797 * Dummy version for when we're not supporting NVmem access 1798 */ 1799 static uint64_t bge_get_nvmac(bge_t *bgep); 1800 #pragma inline(bge_get_nvmac) 1801 1802 static uint64_t 1803 bge_get_nvmac(bge_t *bgep) 1804 { 1805 _NOTE(ARGUNUSED(bgep)) 1806 return (0ULL); 1807 } 1808 1809 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1810 1811 /* 1812 * Determine the type of NVmem that is (or may be) attached to this chip, 1813 */ 1814 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1815 #pragma no_inline(bge_nvmem_id) 1816 1817 static enum bge_nvmem_type 1818 bge_nvmem_id(bge_t *bgep) 1819 { 1820 enum bge_nvmem_type nvtype; 1821 uint32_t config1; 1822 1823 BGE_TRACE(("bge_nvmem_id($%p)", 1824 (void *)bgep)); 1825 1826 switch (bgep->chipid.device) { 1827 default: 1828 /* 1829 * We shouldn't get here; it means we don't recognise 1830 * the chip, which means we don't know how to determine 1831 * what sort of NVmem (if any) it has. So we'll say 1832 * NONE, to disable the NVmem access code ... 1833 */ 1834 nvtype = BGE_NVTYPE_NONE; 1835 break; 1836 1837 case DEVICE_ID_5700: 1838 case DEVICE_ID_5700x: 1839 case DEVICE_ID_5701: 1840 /* 1841 * These devices support *only* SEEPROMs 1842 */ 1843 nvtype = BGE_NVTYPE_SEEPROM; 1844 break; 1845 1846 case DEVICE_ID_5702: 1847 case DEVICE_ID_5702fe: 1848 case DEVICE_ID_5703C: 1849 case DEVICE_ID_5703S: 1850 case DEVICE_ID_5704C: 1851 case DEVICE_ID_5704S: 1852 case DEVICE_ID_5704: 1853 case DEVICE_ID_5705M: 1854 case DEVICE_ID_5705C: 1855 case DEVICE_ID_5705_2: 1856 case DEVICE_ID_5780: 1857 case DEVICE_ID_5782: 1858 case DEVICE_ID_5787: 1859 case DEVICE_ID_5787M: 1860 case DEVICE_ID_5788: 1861 case DEVICE_ID_5789: 1862 case DEVICE_ID_5751: 1863 case DEVICE_ID_5751M: 1864 case DEVICE_ID_5752: 1865 case DEVICE_ID_5752M: 1866 case DEVICE_ID_5754: 1867 case DEVICE_ID_5755: 1868 case DEVICE_ID_5755M: 1869 case DEVICE_ID_5756M: 1870 case DEVICE_ID_5721: 1871 case DEVICE_ID_5722: 1872 case DEVICE_ID_5723: 1873 case DEVICE_ID_5761: 1874 case DEVICE_ID_5761E: 1875 case DEVICE_ID_5714C: 1876 case DEVICE_ID_5714S: 1877 case DEVICE_ID_5715C: 1878 case DEVICE_ID_5715S: 1879 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1880 if (config1 & NVM_CFG1_FLASH_MODE) 1881 if (config1 & NVM_CFG1_BUFFERED_MODE) 1882 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1883 else 1884 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1885 else 1886 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1887 break; 1888 case DEVICE_ID_5906: 1889 case DEVICE_ID_5906M: 1890 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1891 break; 1892 } 1893 1894 return (nvtype); 1895 } 1896 1897 #undef BGE_DBG 1898 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1899 1900 static void 1901 bge_init_recv_rule(bge_t *bgep) 1902 { 1903 bge_recv_rule_t *rulep = bgep->recv_rules; 1904 uint32_t i; 1905 1906 /* 1907 * Initialize receive rule registers. 1908 * Note that rules may persist across each bge_m_start/stop() call. 1909 */ 1910 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1911 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1912 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1913 } 1914 } 1915 1916 /* 1917 * Using the values captured by bge_chip_cfg_init(), and additional probes 1918 * as required, characterise the chip fully: determine the label by which 1919 * to refer to this chip, the correct settings for various registers, and 1920 * of course whether the device and/or subsystem are supported! 1921 */ 1922 int bge_chip_id_init(bge_t *bgep); 1923 #pragma no_inline(bge_chip_id_init) 1924 1925 int 1926 bge_chip_id_init(bge_t *bgep) 1927 { 1928 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1929 boolean_t sys_ok; 1930 boolean_t dev_ok; 1931 chip_id_t *cidp; 1932 uint32_t subid; 1933 char *devname; 1934 char *sysname; 1935 int *ids; 1936 int err; 1937 uint_t i; 1938 1939 sys_ok = dev_ok = B_FALSE; 1940 cidp = &bgep->chipid; 1941 1942 /* 1943 * Check the PCI device ID to determine the generic chip type and 1944 * select parameters that depend on this. 1945 * 1946 * Note: because the SPARC platforms in general don't fit the 1947 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1948 * as zero - which is why we use <asic_rev> rather than <revision> 1949 * below ... 1950 * 1951 * Note: in general we can't distinguish between the Copper/SerDes 1952 * versions by ID alone, as some Copper devices (e.g. some but not 1953 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1954 * treat them the same here, and the MII code works out the media 1955 * type later on ... 1956 */ 1957 cidp->mbuf_base = bge_mbuf_pool_base; 1958 cidp->mbuf_length = bge_mbuf_pool_len; 1959 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1960 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1961 cidp->pci_type = BGE_PCI_X; 1962 cidp->statistic_type = BGE_STAT_BLK; 1963 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1964 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1965 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1966 cidp->rx_ticks_norm = bge_rx_ticks_norm; 1967 cidp->rx_count_norm = bge_rx_count_norm; 1968 1969 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1970 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1971 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1972 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1973 1974 cidp->msi_enabled = B_FALSE; 1975 1976 switch (cidp->device) { 1977 case DEVICE_ID_5700: 1978 case DEVICE_ID_5700x: 1979 cidp->chip_label = 5700; 1980 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1981 break; 1982 1983 case DEVICE_ID_5701: 1984 cidp->chip_label = 5701; 1985 dev_ok = B_TRUE; 1986 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1987 break; 1988 1989 case DEVICE_ID_5702: 1990 case DEVICE_ID_5702fe: 1991 cidp->chip_label = 5702; 1992 dev_ok = B_TRUE; 1993 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1994 cidp->pci_type = BGE_PCI; 1995 break; 1996 1997 case DEVICE_ID_5703C: 1998 case DEVICE_ID_5703S: 1999 case DEVICE_ID_5703: 2000 /* 2001 * Revision A0 of the 5703/5793 had various errata 2002 * that we can't or don't work around, so it's not 2003 * supported, but all later versions are 2004 */ 2005 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 2006 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 2007 dev_ok = B_TRUE; 2008 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2009 break; 2010 2011 case DEVICE_ID_5704C: 2012 case DEVICE_ID_5704S: 2013 case DEVICE_ID_5704: 2014 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 2015 cidp->mbuf_base = bge_mbuf_pool_base_5704; 2016 cidp->mbuf_length = bge_mbuf_pool_len_5704; 2017 dev_ok = B_TRUE; 2018 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2019 break; 2020 2021 case DEVICE_ID_5705C: 2022 case DEVICE_ID_5705M: 2023 case DEVICE_ID_5705MA3: 2024 case DEVICE_ID_5705F: 2025 case DEVICE_ID_5705_2: 2026 case DEVICE_ID_5754: 2027 if (cidp->device == DEVICE_ID_5754) { 2028 cidp->chip_label = 5754; 2029 cidp->pci_type = BGE_PCI_E; 2030 } else { 2031 cidp->chip_label = 5705; 2032 cidp->pci_type = BGE_PCI; 2033 } 2034 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2035 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2036 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2037 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2038 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2039 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2040 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2041 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2042 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2043 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2044 cidp->statistic_type = BGE_STAT_REG; 2045 dev_ok = B_TRUE; 2046 break; 2047 2048 case DEVICE_ID_5906: 2049 case DEVICE_ID_5906M: 2050 cidp->chip_label = 5906; 2051 cidp->pci_type = BGE_PCI_E; 2052 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906; 2053 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906; 2054 cidp->mbuf_hi_water = MBUF_HIWAT_5906; 2055 cidp->mbuf_base = bge_mbuf_pool_base; 2056 cidp->mbuf_length = bge_mbuf_pool_len; 2057 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2058 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2059 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2060 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2061 cidp->statistic_type = BGE_STAT_REG; 2062 dev_ok = B_TRUE; 2063 break; 2064 2065 case DEVICE_ID_5753: 2066 cidp->chip_label = 5753; 2067 cidp->pci_type = BGE_PCI_E; 2068 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2069 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2070 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2071 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2072 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2073 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2074 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2075 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2076 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2077 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2078 cidp->statistic_type = BGE_STAT_REG; 2079 dev_ok = B_TRUE; 2080 break; 2081 2082 case DEVICE_ID_5755: 2083 case DEVICE_ID_5755M: 2084 cidp->chip_label = 5755; 2085 cidp->pci_type = BGE_PCI_E; 2086 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2087 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2088 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2089 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2090 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2091 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2092 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2093 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2094 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2095 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2096 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2097 cidp->statistic_type = BGE_STAT_REG; 2098 dev_ok = B_TRUE; 2099 break; 2100 2101 case DEVICE_ID_5756M: 2102 /* 2103 * This is nearly identical to the 5755M. 2104 * (Actually reports the 5755 chip ID.) 2105 */ 2106 cidp->chip_label = 5756; 2107 cidp->pci_type = BGE_PCI_E; 2108 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2109 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2110 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2111 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2112 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2113 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2114 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2115 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2116 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2117 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2118 cidp->statistic_type = BGE_STAT_REG; 2119 dev_ok = B_TRUE; 2120 break; 2121 2122 case DEVICE_ID_5787: 2123 case DEVICE_ID_5787M: 2124 cidp->chip_label = 5787; 2125 cidp->pci_type = BGE_PCI_E; 2126 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2127 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2128 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2129 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2130 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2131 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2132 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2133 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2134 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2135 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2136 cidp->statistic_type = BGE_STAT_REG; 2137 dev_ok = B_TRUE; 2138 break; 2139 2140 case DEVICE_ID_5723: 2141 case DEVICE_ID_5761: 2142 case DEVICE_ID_5761E: 2143 cidp->chip_label = cidp->device == DEVICE_ID_5723 ? 5723: 5761; 2144 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2145 cidp->msi_enabled = bge_enable_msi; 2146 cidp->pci_type = BGE_PCI_E; 2147 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2148 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2149 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2150 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2151 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2152 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2153 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2154 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2155 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2156 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2157 cidp->statistic_type = BGE_STAT_REG; 2158 dev_ok = B_TRUE; 2159 break; 2160 2161 /* PCI-X device, identical to 5714 */ 2162 case DEVICE_ID_5780: 2163 cidp->chip_label = 5780; 2164 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2165 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2166 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2167 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2168 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2169 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2170 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2171 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2172 cidp->statistic_type = BGE_STAT_REG; 2173 dev_ok = B_TRUE; 2174 break; 2175 2176 case DEVICE_ID_5782: 2177 /* 2178 * Apart from the label, we treat this as a 5705(?) 2179 */ 2180 cidp->chip_label = 5782; 2181 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2182 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2183 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2184 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2185 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2186 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2187 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2188 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2189 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2190 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2191 cidp->statistic_type = BGE_STAT_REG; 2192 dev_ok = B_TRUE; 2193 break; 2194 2195 case DEVICE_ID_5788: 2196 /* 2197 * Apart from the label, we treat this as a 5705(?) 2198 */ 2199 cidp->chip_label = 5788; 2200 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2201 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2202 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2203 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2204 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2205 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2206 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2207 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2208 cidp->statistic_type = BGE_STAT_REG; 2209 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2210 dev_ok = B_TRUE; 2211 break; 2212 2213 case DEVICE_ID_5714C: 2214 if (cidp->revision >= REVISION_ID_5714_A2) 2215 cidp->msi_enabled = bge_enable_msi; 2216 /* FALLTHRU */ 2217 case DEVICE_ID_5714S: 2218 cidp->chip_label = 5714; 2219 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2220 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2221 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2222 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2223 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2224 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2225 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2226 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2227 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2228 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2229 cidp->pci_type = BGE_PCI_E; 2230 cidp->statistic_type = BGE_STAT_REG; 2231 dev_ok = B_TRUE; 2232 break; 2233 2234 case DEVICE_ID_5715C: 2235 case DEVICE_ID_5715S: 2236 cidp->chip_label = 5715; 2237 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2238 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2239 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2240 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2241 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2242 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2243 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2244 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2245 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2246 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2247 cidp->pci_type = BGE_PCI_E; 2248 cidp->statistic_type = BGE_STAT_REG; 2249 if (cidp->revision >= REVISION_ID_5715_A2) 2250 cidp->msi_enabled = bge_enable_msi; 2251 dev_ok = B_TRUE; 2252 break; 2253 2254 case DEVICE_ID_5721: 2255 cidp->chip_label = 5721; 2256 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2257 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2258 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2259 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2260 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2261 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2262 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2263 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2264 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2265 cidp->pci_type = BGE_PCI_E; 2266 cidp->statistic_type = BGE_STAT_REG; 2267 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2268 dev_ok = B_TRUE; 2269 break; 2270 2271 case DEVICE_ID_5722: 2272 cidp->chip_label = 5722; 2273 cidp->pci_type = BGE_PCI_E; 2274 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2275 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2276 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2277 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2278 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2279 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2280 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2281 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2282 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2283 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2284 cidp->statistic_type = BGE_STAT_REG; 2285 dev_ok = B_TRUE; 2286 break; 2287 2288 case DEVICE_ID_5751: 2289 case DEVICE_ID_5751M: 2290 cidp->chip_label = 5751; 2291 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2292 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2293 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2294 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2295 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2296 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2297 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2298 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2299 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2300 cidp->pci_type = BGE_PCI_E; 2301 cidp->statistic_type = BGE_STAT_REG; 2302 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2303 dev_ok = B_TRUE; 2304 break; 2305 2306 case DEVICE_ID_5752: 2307 case DEVICE_ID_5752M: 2308 cidp->chip_label = 5752; 2309 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2310 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2311 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2312 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2313 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2314 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2315 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2316 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2317 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2318 cidp->pci_type = BGE_PCI_E; 2319 cidp->statistic_type = BGE_STAT_REG; 2320 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2321 dev_ok = B_TRUE; 2322 break; 2323 2324 case DEVICE_ID_5789: 2325 cidp->chip_label = 5789; 2326 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2327 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2328 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2329 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2330 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2331 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2332 cidp->pci_type = BGE_PCI_E; 2333 cidp->statistic_type = BGE_STAT_REG; 2334 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2335 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2336 cidp->msi_enabled = B_TRUE; 2337 dev_ok = B_TRUE; 2338 break; 2339 2340 } 2341 2342 /* 2343 * Setup the default jumbo parameter. 2344 */ 2345 cidp->ethmax_size = ETHERMAX; 2346 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2347 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2348 2349 /* 2350 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2351 * setup below jumbo specific parameters. 2352 * 2353 * For BCM5714/5715, there is only one standard receive ring. So the 2354 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2355 * feature is enabled. 2356 */ 2357 if (bge_jumbo_enable && 2358 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2359 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2360 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2361 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2362 cidp->mbuf_lo_water_rdma = 2363 RDMA_MBUF_LOWAT_5714_JUMBO; 2364 cidp->mbuf_lo_water_rmac = 2365 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2366 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2367 cidp->jumbo_slots = 0; 2368 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2369 } else { 2370 cidp->mbuf_lo_water_rdma = 2371 RDMA_MBUF_LOWAT_JUMBO; 2372 cidp->mbuf_lo_water_rmac = 2373 MAC_RX_MBUF_LOWAT_JUMBO; 2374 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2375 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2376 } 2377 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2378 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2379 cidp->ethmax_size = cidp->default_mtu + 2380 sizeof (struct ether_header); 2381 } 2382 2383 /* 2384 * Identify the NV memory type: SEEPROM or Flash? 2385 */ 2386 cidp->nvtype = bge_nvmem_id(bgep); 2387 2388 /* 2389 * Now, we want to check whether this device is part of a 2390 * supported subsystem (e.g., on the motherboard of a Sun 2391 * branded platform). 2392 * 2393 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2394 */ 2395 if (cidp->subven == VENDOR_ID_SUN) 2396 sys_ok = B_TRUE; 2397 2398 /* 2399 * Rule 2: If it's on the list on known subsystems, then it's OK. 2400 * Note: 0x14e41647 should *not* appear in the list, but the code 2401 * doesn't enforce that. 2402 */ 2403 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2404 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2405 if (err == DDI_PROP_SUCCESS) { 2406 /* 2407 * Got the list; scan for a matching subsystem vendor/device 2408 */ 2409 subid = (cidp->subven << 16) | cidp->subdev; 2410 while (i--) 2411 if (ids[i] == subid) 2412 sys_ok = B_TRUE; 2413 ddi_prop_free(ids); 2414 } 2415 2416 /* 2417 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2418 * 2419 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2420 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2421 * we have to check specially for the exact device paths to the 2422 * motherboard devices on those platforms ;-( 2423 * 2424 * Note: we can't just use the "supported-subsystems" mechanism 2425 * above, because the entry would have to be 0x14e41647 -- which 2426 * would then accept *any* plugin card that *didn't* contain a 2427 * (valid) SEEPROM ;-( 2428 */ 2429 sysname = ddi_node_name(ddi_root_node()); 2430 devname = ddi_pathname(bgep->devinfo, buf); 2431 ASSERT(strlen(devname) > 0); 2432 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2433 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2434 sys_ok = B_TRUE; 2435 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2436 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2437 sys_ok = B_TRUE; 2438 2439 /* 2440 * Now check what we've discovered: is this truly a supported 2441 * chip on (the motherboard of) a supported platform? 2442 * 2443 * Possible problems here: 2444 * 1) it's a completely unheard-of chip 2445 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2446 * 3) it's a chip we would support if it were on the motherboard 2447 * of a Sun platform, but this one isn't ;-( 2448 */ 2449 if (cidp->chip_label == 0) 2450 bge_problem(bgep, 2451 "Device 'pci%04x,%04x' not recognized (%d?)", 2452 cidp->vendor, cidp->device, cidp->device); 2453 else if (!dev_ok) 2454 bge_problem(bgep, 2455 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2456 cidp->vendor, cidp->device, cidp->chip_label, 2457 cidp->revision); 2458 #if BGE_DEBUGGING 2459 else if (!sys_ok) 2460 bge_problem(bgep, 2461 "%d-based subsystem 'pci%04x,%04x' not validated", 2462 cidp->chip_label, cidp->subven, cidp->subdev); 2463 #endif 2464 else 2465 cidp->flags |= CHIP_FLAG_SUPPORTED; 2466 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2467 return (EIO); 2468 return (0); 2469 } 2470 2471 void 2472 bge_chip_msi_trig(bge_t *bgep) 2473 { 2474 uint32_t regval; 2475 2476 regval = bgep->param_msi_cnt<<4; 2477 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2478 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2479 } 2480 2481 /* 2482 * Various registers that control the chip's internal engines (state 2483 * machines) have a <reset> and <enable> bits (fortunately, in the 2484 * same place in each such register :-). 2485 * 2486 * To reset the state machine, the <reset> bit must be written with 1; 2487 * it will then read back as 1 while the reset is in progress, but 2488 * self-clear to 0 when the reset completes. 2489 * 2490 * To enable a state machine, one must set the <enable> bit, which 2491 * will continue to read back as 0 until the state machine is running. 2492 * 2493 * To disable a state machine, the <enable> bit must be cleared, but 2494 * it will continue to read back as 1 until the state machine actually 2495 * stops. 2496 * 2497 * This routine implements polling for completion of a reset, enable 2498 * or disable operation, returning B_TRUE on success (bit reached the 2499 * required state) or B_FALSE on timeout (200*100us == 20ms). 2500 */ 2501 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2502 uint32_t mask, uint32_t val); 2503 #pragma no_inline(bge_chip_poll_engine) 2504 2505 static boolean_t 2506 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2507 uint32_t mask, uint32_t val) 2508 { 2509 uint32_t regval; 2510 uint32_t n; 2511 2512 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2513 (void *)bgep, regno, mask, val)); 2514 2515 for (n = 200; n; --n) { 2516 regval = bge_reg_get32(bgep, regno); 2517 if ((regval & mask) == val) 2518 return (B_TRUE); 2519 drv_usecwait(100); 2520 } 2521 2522 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2523 return (B_FALSE); 2524 } 2525 2526 /* 2527 * Various registers that control the chip's internal engines (state 2528 * machines) have a <reset> bit (fortunately, in the same place in 2529 * each such register :-). To reset the state machine, this bit must 2530 * be written with 1; it will then read back as 1 while the reset is 2531 * in progress, but self-clear to 0 when the reset completes. 2532 * 2533 * This code sets the bit, then polls for it to read back as zero. 2534 * The return value is B_TRUE on success (reset bit cleared itself), 2535 * or B_FALSE if the state machine didn't recover :( 2536 * 2537 * NOTE: the Core reset is similar to other resets, except that we 2538 * can't poll for completion, since the Core reset disables memory 2539 * access! So we just have to assume that it will all complete in 2540 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2541 */ 2542 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2543 #pragma no_inline(bge_chip_reset_engine) 2544 2545 static boolean_t 2546 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2547 { 2548 uint32_t regval; 2549 uint32_t val32; 2550 2551 regval = bge_reg_get32(bgep, regno); 2552 2553 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2554 (void *)bgep, regno)); 2555 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2556 regno, regval)); 2557 2558 regval |= STATE_MACHINE_RESET_BIT; 2559 2560 switch (regno) { 2561 case MISC_CONFIG_REG: 2562 /* 2563 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2564 * resetting PCIE block and bringing PCIE link down, bit 29 2565 * in the register needs to be set first, and then set it again 2566 * while the reset bit is written. 2567 * See:P500 of 57xx-PG102-RDS.pdf. 2568 */ 2569 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2570 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2571 DEVICE_5723_SERIES_CHIPSETS(bgep)|| 2572 DEVICE_5714_SERIES_CHIPSETS(bgep)|| 2573 DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2574 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2575 if (bgep->chipid.pci_type == BGE_PCI_E) { 2576 if (bgep->chipid.asic_rev == 2577 MHCR_CHIP_REV_5751_A0 || 2578 bgep->chipid.asic_rev == 2579 MHCR_CHIP_REV_5721_A0 || 2580 bgep->chipid.asic_rev == 2581 MHCR_CHIP_REV_5755_A0) { 2582 val32 = bge_reg_get32(bgep, 2583 PHY_TEST_CTRL_REG); 2584 if (val32 == (PHY_PCIE_SCRAM_MODE | 2585 PHY_PCIE_LTASS_MODE)) 2586 bge_reg_put32(bgep, 2587 PHY_TEST_CTRL_REG, 2588 PHY_PCIE_SCRAM_MODE); 2589 val32 = pci_config_get32 2590 (bgep->cfg_handle, 2591 PCI_CONF_BGE_CLKCTL); 2592 val32 |= CLKCTL_PCIE_A0_FIX; 2593 pci_config_put32(bgep->cfg_handle, 2594 PCI_CONF_BGE_CLKCTL, val32); 2595 } 2596 bge_reg_set32(bgep, regno, 2597 MISC_CONFIG_GRC_RESET_DISABLE); 2598 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2599 } 2600 } 2601 2602 /* 2603 * Special case - causes Core reset 2604 * 2605 * On SPARC v9 we want to ensure that we don't start 2606 * timing until the I/O access has actually reached 2607 * the chip, otherwise we might make the next access 2608 * too early. And we can't just force the write out 2609 * by following it with a read (even to config space) 2610 * because that would cause the fault we're trying 2611 * to avoid. Hence the need for membar_sync() here. 2612 */ 2613 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2614 #ifdef __sparcv9 2615 membar_sync(); 2616 #endif /* __sparcv9 */ 2617 /* 2618 * On some platforms,system need about 300us for 2619 * link setup. 2620 */ 2621 drv_usecwait(300); 2622 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2623 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET); 2624 bge_reg_clr32( 2625 bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF); 2626 } 2627 2628 if (bgep->chipid.pci_type == BGE_PCI_E) { 2629 /* PCI-E device need more reset time */ 2630 drv_usecwait(120000); 2631 2632 /* Set PCIE max payload size and clear error status. */ 2633 if ((bgep->chipid.chip_label == 5721) || 2634 (bgep->chipid.chip_label == 5751) || 2635 (bgep->chipid.chip_label == 5752) || 2636 (bgep->chipid.chip_label == 5789) || 2637 (bgep->chipid.chip_label == 5906)) { 2638 pci_config_put16(bgep->cfg_handle, 2639 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2640 pci_config_put16(bgep->cfg_handle, 2641 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2642 } 2643 2644 if ((bgep->chipid.chip_label == 5723) || 2645 (bgep->chipid.chip_label == 5761)) { 2646 pci_config_put16(bgep->cfg_handle, 2647 PCI_CONF_DEV_CTRL_5723, READ_REQ_SIZE_MAX); 2648 pci_config_put16(bgep->cfg_handle, 2649 PCI_CONF_DEV_STUS_5723, DEVICE_ERROR_STUS); 2650 } 2651 } 2652 2653 BGE_PCICHK(bgep); 2654 return (B_TRUE); 2655 2656 default: 2657 bge_reg_put32(bgep, regno, regval); 2658 return (bge_chip_poll_engine(bgep, regno, 2659 STATE_MACHINE_RESET_BIT, 0)); 2660 } 2661 } 2662 2663 /* 2664 * Various registers that control the chip's internal engines (state 2665 * machines) have an <enable> bit (fortunately, in the same place in 2666 * each such register :-). To stop the state machine, this bit must 2667 * be written with 0, then polled to see when the state machine has 2668 * actually stopped. 2669 * 2670 * The return value is B_TRUE on success (enable bit cleared), or 2671 * B_FALSE if the state machine didn't stop :( 2672 */ 2673 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2674 uint32_t morebits); 2675 #pragma no_inline(bge_chip_disable_engine) 2676 2677 static boolean_t 2678 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2679 { 2680 uint32_t regval; 2681 2682 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2683 (void *)bgep, regno, morebits)); 2684 2685 switch (regno) { 2686 case FTQ_RESET_REG: 2687 /* 2688 * For Schumacher's bugfix CR6490108 2689 */ 2690 #ifdef BGE_IPMI_ASF 2691 #ifdef BGE_NETCONSOLE 2692 if (bgep->asf_enabled) 2693 return (B_TRUE); 2694 #endif 2695 #endif 2696 /* 2697 * Not quite like the others; it doesn't 2698 * have an <enable> bit, but instead we 2699 * have to set and then clear all the bits 2700 */ 2701 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2702 drv_usecwait(100); 2703 bge_reg_put32(bgep, regno, 0); 2704 return (B_TRUE); 2705 2706 default: 2707 regval = bge_reg_get32(bgep, regno); 2708 regval &= ~STATE_MACHINE_ENABLE_BIT; 2709 regval &= ~morebits; 2710 bge_reg_put32(bgep, regno, regval); 2711 return (bge_chip_poll_engine(bgep, regno, 2712 STATE_MACHINE_ENABLE_BIT, 0)); 2713 } 2714 } 2715 2716 /* 2717 * Various registers that control the chip's internal engines (state 2718 * machines) have an <enable> bit (fortunately, in the same place in 2719 * each such register :-). To start the state machine, this bit must 2720 * be written with 1, then polled to see when the state machine has 2721 * actually started. 2722 * 2723 * The return value is B_TRUE on success (enable bit set), or 2724 * B_FALSE if the state machine didn't start :( 2725 */ 2726 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2727 uint32_t morebits); 2728 #pragma no_inline(bge_chip_enable_engine) 2729 2730 static boolean_t 2731 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2732 { 2733 uint32_t regval; 2734 2735 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2736 (void *)bgep, regno, morebits)); 2737 2738 switch (regno) { 2739 case FTQ_RESET_REG: 2740 #ifdef BGE_IPMI_ASF 2741 #ifdef BGE_NETCONSOLE 2742 if (bgep->asf_enabled) 2743 return (B_TRUE); 2744 #endif 2745 #endif 2746 /* 2747 * Not quite like the others; it doesn't 2748 * have an <enable> bit, but instead we 2749 * have to set and then clear all the bits 2750 */ 2751 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2752 drv_usecwait(100); 2753 bge_reg_put32(bgep, regno, 0); 2754 return (B_TRUE); 2755 2756 default: 2757 regval = bge_reg_get32(bgep, regno); 2758 regval |= STATE_MACHINE_ENABLE_BIT; 2759 regval |= morebits; 2760 bge_reg_put32(bgep, regno, regval); 2761 return (bge_chip_poll_engine(bgep, regno, 2762 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2763 } 2764 } 2765 2766 /* 2767 * Reprogram the Ethernet, Transmit, and Receive MAC 2768 * modes to match the param_* variables 2769 */ 2770 void bge_sync_mac_modes(bge_t *bgep); 2771 #pragma no_inline(bge_sync_mac_modes) 2772 2773 void 2774 bge_sync_mac_modes(bge_t *bgep) 2775 { 2776 uint32_t macmode; 2777 uint32_t regval; 2778 2779 ASSERT(mutex_owned(bgep->genlock)); 2780 2781 /* 2782 * Reprogram the Ethernet MAC mode ... 2783 */ 2784 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2785 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2786 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2787 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2788 macmode |= ETHERNET_MODE_LINK_POLARITY; 2789 else 2790 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2791 else 2792 macmode |= ETHERNET_MODE_LINK_POLARITY; 2793 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2794 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2795 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) { 2796 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2797 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2798 else 2799 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2800 } else if (bgep->param_link_speed == 10 || 2801 bgep->param_link_speed == 100) 2802 macmode |= ETHERNET_MODE_PORTMODE_MII; 2803 else 2804 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2805 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2806 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2807 else 2808 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2809 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2810 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2811 else 2812 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2813 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2814 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2815 (void *)bgep, regval, macmode)); 2816 2817 /* 2818 * ... the Transmit MAC mode ... 2819 */ 2820 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2821 if (bgep->param_link_tx_pause) 2822 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2823 else 2824 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2825 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2826 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2827 (void *)bgep, regval, macmode)); 2828 2829 /* 2830 * ... and the Receive MAC mode 2831 */ 2832 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2833 if (bgep->param_link_rx_pause) 2834 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2835 else 2836 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2837 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2838 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2839 (void *)bgep, regval, macmode)); 2840 } 2841 2842 /* 2843 * bge_chip_sync() -- program the chip with the unicast MAC address, 2844 * the multicast hash table, the required level of promiscuity, and 2845 * the current loopback mode ... 2846 */ 2847 #ifdef BGE_IPMI_ASF 2848 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2849 #else 2850 int bge_chip_sync(bge_t *bgep); 2851 #endif 2852 #pragma no_inline(bge_chip_sync) 2853 2854 int 2855 #ifdef BGE_IPMI_ASF 2856 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2857 #else 2858 bge_chip_sync(bge_t *bgep) 2859 #endif 2860 { 2861 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2862 boolean_t promisc; 2863 uint64_t macaddr; 2864 uint32_t fill = 0; 2865 int i, j; 2866 int retval = DDI_SUCCESS; 2867 2868 BGE_TRACE(("bge_chip_sync($%p)", 2869 (void *)bgep)); 2870 2871 ASSERT(mutex_owned(bgep->genlock)); 2872 2873 promisc = B_FALSE; 2874 fill = ~(uint32_t)0; 2875 2876 if (bgep->promisc) 2877 promisc = B_TRUE; 2878 else 2879 fill = (uint32_t)0; 2880 2881 /* 2882 * If the TX/RX MAC engines are already running, we should stop 2883 * them (and reset the RX engine) before changing the parameters. 2884 * If they're not running, this will have no effect ... 2885 * 2886 * NOTE: this is currently disabled by default because stopping 2887 * and restarting the Tx engine may cause an outgoing packet in 2888 * transit to be truncated. Also, stopping and restarting the 2889 * Rx engine seems to not work correctly on the 5705. Testing 2890 * has not (yet!) revealed any problems with NOT stopping and 2891 * restarting these engines (and Broadcom say their drivers don't 2892 * do this), but if it is found to cause problems, this variable 2893 * can be patched to re-enable the old behaviour ... 2894 */ 2895 if (bge_stop_start_on_sync) { 2896 #ifdef BGE_IPMI_ASF 2897 if (!bgep->asf_enabled) { 2898 if (!bge_chip_disable_engine(bgep, 2899 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2900 retval = DDI_FAILURE; 2901 } else { 2902 if (!bge_chip_disable_engine(bgep, 2903 RECEIVE_MAC_MODE_REG, 0)) 2904 retval = DDI_FAILURE; 2905 } 2906 #else 2907 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2908 RECEIVE_MODE_KEEP_VLAN_TAG)) 2909 retval = DDI_FAILURE; 2910 #endif 2911 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2912 retval = DDI_FAILURE; 2913 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2914 retval = DDI_FAILURE; 2915 } 2916 2917 /* 2918 * Reprogram the hashed multicast address table ... 2919 */ 2920 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2921 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 2922 2923 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2924 bge_reg_put32(bgep, MAC_HASH_REG(i), 2925 bgep->mcast_hash[i] | fill); 2926 2927 #ifdef BGE_IPMI_ASF 2928 if (!bgep->asf_enabled || !asf_keeplive) { 2929 #endif 2930 /* 2931 * Transform the MAC address(es) from host to chip format, then 2932 * reprogram the transmit random backoff seed and the unicast 2933 * MAC address(es) ... 2934 */ 2935 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2936 for (i = 0, macaddr = 0ull; 2937 i < ETHERADDRL; ++i) { 2938 macaddr <<= 8; 2939 macaddr |= bgep->curr_addr[j].addr[i]; 2940 } 2941 fill += (macaddr >> 16) + (macaddr & 0xffffffff); 2942 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2943 2944 BGE_DEBUG(("bge_chip_sync($%p) " 2945 "setting MAC address %012llx", 2946 (void *)bgep, macaddr)); 2947 } 2948 #ifdef BGE_IPMI_ASF 2949 } 2950 #endif 2951 /* 2952 * Set random seed of backoff interval 2953 * - Writing zero means no backoff interval 2954 */ 2955 fill = ((fill >> 20) + (fill >> 10) + fill) & 0x3ff; 2956 if (fill == 0) 2957 fill = 1; 2958 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2959 2960 /* 2961 * Set or clear the PROMISCUOUS mode bit 2962 */ 2963 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2964 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2965 2966 /* 2967 * Sync the rest of the MAC modes too ... 2968 */ 2969 bge_sync_mac_modes(bgep); 2970 2971 /* 2972 * Restart RX/TX MAC engines if required ... 2973 */ 2974 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2975 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2976 retval = DDI_FAILURE; 2977 #ifdef BGE_IPMI_ASF 2978 if (!bgep->asf_enabled) { 2979 if (!bge_chip_enable_engine(bgep, 2980 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2981 retval = DDI_FAILURE; 2982 } else { 2983 if (!bge_chip_enable_engine(bgep, 2984 RECEIVE_MAC_MODE_REG, 0)) 2985 retval = DDI_FAILURE; 2986 } 2987 #else 2988 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2989 RECEIVE_MODE_KEEP_VLAN_TAG)) 2990 retval = DDI_FAILURE; 2991 #endif 2992 } 2993 return (retval); 2994 } 2995 2996 /* 2997 * This array defines the sequence of state machine control registers 2998 * in which the <enable> bit must be cleared to bring the chip to a 2999 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 3000 */ 3001 static bge_regno_t shutdown_engine_regs[] = { 3002 RECEIVE_MAC_MODE_REG, 3003 RCV_BD_INITIATOR_MODE_REG, 3004 RCV_LIST_PLACEMENT_MODE_REG, 3005 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 3006 RCV_DATA_BD_INITIATOR_MODE_REG, 3007 RCV_DATA_COMPLETION_MODE_REG, 3008 RCV_BD_COMPLETION_MODE_REG, 3009 3010 SEND_BD_SELECTOR_MODE_REG, 3011 SEND_BD_INITIATOR_MODE_REG, 3012 SEND_DATA_INITIATOR_MODE_REG, 3013 READ_DMA_MODE_REG, 3014 SEND_DATA_COMPLETION_MODE_REG, 3015 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 3016 SEND_BD_COMPLETION_MODE_REG, 3017 TRANSMIT_MAC_MODE_REG, 3018 3019 HOST_COALESCE_MODE_REG, 3020 WRITE_DMA_MODE_REG, 3021 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 3022 FTQ_RESET_REG, /* special - see code */ 3023 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 3024 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 3025 BGE_REGNO_NONE /* terminator */ 3026 }; 3027 3028 #ifndef __sparc 3029 static bge_regno_t quiesce_regs[] = { 3030 READ_DMA_MODE_REG, 3031 DMA_COMPLETION_MODE_REG, 3032 WRITE_DMA_MODE_REG, 3033 BGE_REGNO_NONE 3034 }; 3035 3036 void bge_chip_stop_nonblocking(bge_t *bgep); 3037 #pragma no_inline(bge_chip_stop_nonblocking) 3038 3039 /* 3040 * This function is called by bge_quiesce(). We 3041 * turn off all the DMA engines here. 3042 */ 3043 void 3044 bge_chip_stop_nonblocking(bge_t *bgep) 3045 { 3046 bge_regno_t *rbp; 3047 3048 /* 3049 * Flag that no more activity may be initiated 3050 */ 3051 bgep->progress &= ~PROGRESS_READY; 3052 3053 rbp = quiesce_regs; 3054 while (*rbp != BGE_REGNO_NONE) { 3055 (void) bge_chip_disable_engine(bgep, *rbp, 0); 3056 ++rbp; 3057 } 3058 3059 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3060 } 3061 3062 #endif 3063 3064 /* 3065 * bge_chip_stop() -- stop all chip processing 3066 * 3067 * If the <fault> parameter is B_TRUE, we're stopping the chip because 3068 * we've detected a problem internally; otherwise, this is a normal 3069 * (clean) stop (at user request i.e. the last STREAM has been closed). 3070 */ 3071 void bge_chip_stop(bge_t *bgep, boolean_t fault); 3072 #pragma no_inline(bge_chip_stop) 3073 3074 void 3075 bge_chip_stop(bge_t *bgep, boolean_t fault) 3076 { 3077 bge_regno_t regno; 3078 bge_regno_t *rbp; 3079 boolean_t ok; 3080 3081 BGE_TRACE(("bge_chip_stop($%p)", 3082 (void *)bgep)); 3083 3084 ASSERT(mutex_owned(bgep->genlock)); 3085 3086 rbp = shutdown_engine_regs; 3087 /* 3088 * When driver try to shutdown the BCM5705/5788/5721/5751/ 3089 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 3090 * -ory arbiter should not be disabled. 3091 */ 3092 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 3093 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3094 ok &= bge_chip_disable_engine(bgep, regno, 0); 3095 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 3096 (regno != DMA_COMPLETION_MODE_REG) && 3097 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 3098 (regno != BUFFER_MANAGER_MODE_REG) && 3099 (regno != MEMORY_ARBITER_MODE_REG)) 3100 ok &= bge_chip_disable_engine(bgep, 3101 regno, 0); 3102 } 3103 3104 if (!ok && !fault) 3105 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 3106 3107 /* 3108 * Finally, disable (all) MAC events & clear the MAC status 3109 */ 3110 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 3111 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 3112 3113 /* 3114 * if we're stopping the chip because of a detected fault then do 3115 * appropriate actions 3116 */ 3117 if (fault) { 3118 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 3119 bgep->bge_chip_state = BGE_CHIP_FAULT; 3120 if (!bgep->manual_reset) 3121 ddi_fm_service_impact(bgep->devinfo, 3122 DDI_SERVICE_LOST); 3123 if (bgep->bge_dma_error) { 3124 /* 3125 * need to free buffers in case the fault was 3126 * due to a memory error in a buffer - got to 3127 * do a fair bit of tidying first 3128 */ 3129 if (bgep->progress & PROGRESS_KSTATS) { 3130 bge_fini_kstats(bgep); 3131 bgep->progress &= ~PROGRESS_KSTATS; 3132 } 3133 if (bgep->progress & PROGRESS_INTR) { 3134 bge_intr_disable(bgep); 3135 rw_enter(bgep->errlock, RW_WRITER); 3136 bge_fini_rings(bgep); 3137 rw_exit(bgep->errlock); 3138 bgep->progress &= ~PROGRESS_INTR; 3139 } 3140 if (bgep->progress & PROGRESS_BUFS) { 3141 bge_free_bufs(bgep); 3142 bgep->progress &= ~PROGRESS_BUFS; 3143 } 3144 bgep->bge_dma_error = B_FALSE; 3145 } 3146 } 3147 } else 3148 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3149 } 3150 3151 /* 3152 * Poll for completion of chip's ROM firmware; also, at least on the 3153 * first time through, find and return the hardware MAC address, if any. 3154 */ 3155 static uint64_t bge_poll_firmware(bge_t *bgep); 3156 #pragma no_inline(bge_poll_firmware) 3157 3158 static uint64_t 3159 bge_poll_firmware(bge_t *bgep) 3160 { 3161 uint64_t magic; 3162 uint64_t mac; 3163 uint32_t gen, val; 3164 uint32_t i; 3165 3166 /* 3167 * Step 19: poll for firmware completion (GENCOMM port set 3168 * to the ones complement of T3_MAGIC_NUMBER). 3169 * 3170 * While we're at it, we also read the MAC address register; 3171 * at some stage the firmware will load this with the 3172 * factory-set value. 3173 * 3174 * When both the magic number and the MAC address are set, 3175 * we're done; but we impose a time limit of one second 3176 * (1000*1000us) in case the firmware fails in some fashion 3177 * or the SEEPROM that provides that MAC address isn't fitted. 3178 * 3179 * After the first time through (chip state != INITIAL), we 3180 * don't need the MAC address to be set (we've already got it 3181 * or not, from the first time), so we don't wait for it, but 3182 * we still have to wait for the T3_MAGIC_NUMBER. 3183 * 3184 * Note: the magic number is only a 32-bit quantity, but the NIC 3185 * memory is 64-bit (and big-endian) internally. Addressing the 3186 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3187 * it work correctly on both big- and little-endian hosts. 3188 */ 3189 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3190 MHCR_CHIP_ASIC_REV_5906) { 3191 for (i = 0; i < 1000; ++i) { 3192 drv_usecwait(1000); 3193 val = bge_reg_get32(bgep, VCPU_STATUS_REG); 3194 if (val & VCPU_INIT_DONE) 3195 break; 3196 } 3197 BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops", 3198 (void *)bgep, i)); 3199 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3200 } else { 3201 for (i = 0; i < 1000; ++i) { 3202 drv_usecwait(1000); 3203 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3204 if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep)) 3205 drv_usecwait(100000); 3206 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3207 #ifdef BGE_IPMI_ASF 3208 if (!bgep->asf_enabled) { 3209 #endif 3210 if (gen != ~T3_MAGIC_NUMBER) 3211 continue; 3212 #ifdef BGE_IPMI_ASF 3213 } 3214 #endif 3215 if (mac != 0ULL) 3216 break; 3217 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3218 break; 3219 } 3220 } 3221 3222 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3223 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3224 (void *)bgep, gen, i)); 3225 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3226 mac, magic)); 3227 3228 return (mac); 3229 } 3230 3231 /* 3232 * Maximum times of trying to get the NVRAM access lock 3233 * by calling bge_nvmem_acquire() 3234 */ 3235 #define MAX_TRY_NVMEM_ACQUIRE 10000 3236 3237 #ifdef BGE_IPMI_ASF 3238 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3239 #else 3240 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3241 #endif 3242 #pragma no_inline(bge_chip_reset) 3243 3244 int 3245 #ifdef BGE_IPMI_ASF 3246 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3247 #else 3248 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3249 #endif 3250 { 3251 chip_id_t chipid; 3252 uint64_t mac; 3253 uint64_t magic; 3254 uint32_t modeflags; 3255 uint32_t mhcr; 3256 uint32_t sx0; 3257 uint32_t i, tries; 3258 #ifdef BGE_IPMI_ASF 3259 uint32_t mailbox; 3260 #endif 3261 int retval = DDI_SUCCESS; 3262 3263 BGE_TRACE(("bge_chip_reset($%p, %d)", 3264 (void *)bgep, enable_dma)); 3265 3266 ASSERT(mutex_owned(bgep->genlock)); 3267 3268 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3269 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3270 3271 /* 3272 * Do we need to stop the chip cleanly before resetting? 3273 */ 3274 switch (bgep->bge_chip_state) { 3275 default: 3276 _NOTE(NOTREACHED) 3277 return (DDI_FAILURE); 3278 3279 case BGE_CHIP_INITIAL: 3280 case BGE_CHIP_STOPPED: 3281 case BGE_CHIP_RESET: 3282 break; 3283 3284 case BGE_CHIP_RUNNING: 3285 case BGE_CHIP_ERROR: 3286 case BGE_CHIP_FAULT: 3287 bge_chip_stop(bgep, B_FALSE); 3288 break; 3289 } 3290 3291 #ifdef BGE_IPMI_ASF 3292 if (bgep->asf_enabled) { 3293 #ifdef __sparc 3294 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3295 MHCR_ENABLE_TAGGED_STATUS_MODE | 3296 MHCR_MASK_INTERRUPT_MODE | 3297 MHCR_MASK_PCI_INT_OUTPUT | 3298 MHCR_CLEAR_INTERRUPT_INTA | 3299 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3300 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3301 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3302 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3303 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3304 MEMORY_ARBITER_ENABLE); 3305 #endif 3306 if (asf_mode == ASF_MODE_INIT) { 3307 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3308 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3309 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3310 } 3311 } 3312 #endif 3313 /* 3314 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3315 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3316 * 3317 * Before reset Core clock,it is 3318 * also required to initialize the Memory Arbiter as specified in step9 3319 * and Misc Host Control Register as specified in step-13 3320 * Step 4-5: reset Core clock & wait for completion 3321 * Steps 6-8: are done by bge_chip_cfg_init() 3322 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3323 */ 3324 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3325 retval = DDI_FAILURE; 3326 3327 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3328 MHCR_ENABLE_TAGGED_STATUS_MODE | 3329 MHCR_MASK_INTERRUPT_MODE | 3330 MHCR_MASK_PCI_INT_OUTPUT | 3331 MHCR_CLEAR_INTERRUPT_INTA; 3332 #ifdef _BIG_ENDIAN 3333 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3334 #endif /* _BIG_ENDIAN */ 3335 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3336 #ifdef BGE_IPMI_ASF 3337 if (bgep->asf_enabled) 3338 bgep->asf_wordswapped = B_FALSE; 3339 #endif 3340 /* 3341 * NVRAM Corruption Workaround 3342 */ 3343 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3344 if (bge_nvmem_acquire(bgep) != EAGAIN) 3345 break; 3346 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3347 BGE_DEBUG(("%s: fail to acquire nvram lock", 3348 bgep->ifname)); 3349 3350 #ifdef BGE_IPMI_ASF 3351 if (!bgep->asf_enabled) { 3352 #endif 3353 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3354 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3355 #ifdef BGE_IPMI_ASF 3356 } 3357 #endif 3358 3359 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3360 retval = DDI_FAILURE; 3361 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3362 3363 /* 3364 * Step 8a: This may belong elsewhere, but BCM5721 needs 3365 * a bit set to avoid a fifo overflow/underflow bug. 3366 */ 3367 if ((bgep->chipid.chip_label == 5721) || 3368 (bgep->chipid.chip_label == 5751) || 3369 (bgep->chipid.chip_label == 5752) || 3370 (bgep->chipid.chip_label == 5755) || 3371 (bgep->chipid.chip_label == 5756) || 3372 (bgep->chipid.chip_label == 5789) || 3373 (bgep->chipid.chip_label == 5906)) 3374 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3375 3376 3377 /* 3378 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3379 * not be changed. 3380 */ 3381 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3382 retval = DDI_FAILURE; 3383 3384 /* 3385 * Steps 10-11: configure PIO endianness options and 3386 * enable indirect register access -- already done 3387 * Steps 12-13: enable writing to the PCI state & clock 3388 * control registers -- not required; we aren't going to 3389 * use those features. 3390 * Steps 14-15: Configure DMA endianness options. See 3391 * the comments on the setting of the MHCR above. 3392 */ 3393 #ifdef _BIG_ENDIAN 3394 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3395 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3396 #else 3397 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3398 #endif /* _BIG_ENDIAN */ 3399 #ifdef BGE_IPMI_ASF 3400 if (bgep->asf_enabled) 3401 modeflags |= MODE_HOST_STACK_UP; 3402 #endif 3403 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3404 3405 #ifdef BGE_IPMI_ASF 3406 if (bgep->asf_enabled) { 3407 #ifdef __sparc 3408 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3409 MEMORY_ARBITER_ENABLE | 3410 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3411 #endif 3412 3413 #ifdef BGE_NETCONSOLE 3414 if (!bgep->asf_newhandshake) { 3415 if ((asf_mode == ASF_MODE_INIT) || 3416 (asf_mode == ASF_MODE_POST_INIT)) { 3417 bge_asf_post_reset_old_mode(bgep, 3418 BGE_INIT_RESET); 3419 } else { 3420 bge_asf_post_reset_old_mode(bgep, 3421 BGE_SHUTDOWN_RESET); 3422 } 3423 } 3424 #endif 3425 3426 /* Wait for NVRAM init */ 3427 i = 0; 3428 drv_usecwait(5000); 3429 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3430 3431 while ((mailbox != (uint32_t) 3432 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3433 (i < 10000)) { 3434 drv_usecwait(100); 3435 mailbox = bge_nic_get32(bgep, 3436 BGE_FIRMWARE_MAILBOX); 3437 i++; 3438 } 3439 3440 #ifndef BGE_NETCONSOLE 3441 if (!bgep->asf_newhandshake) { 3442 if ((asf_mode == ASF_MODE_INIT) || 3443 (asf_mode == ASF_MODE_POST_INIT)) { 3444 3445 bge_asf_post_reset_old_mode(bgep, 3446 BGE_INIT_RESET); 3447 } else { 3448 bge_asf_post_reset_old_mode(bgep, 3449 BGE_SHUTDOWN_RESET); 3450 } 3451 } 3452 #endif 3453 } 3454 #endif 3455 /* 3456 * Steps 16-17: poll for firmware completion 3457 */ 3458 mac = bge_poll_firmware(bgep); 3459 3460 /* 3461 * Step 18: enable external memory -- doesn't apply. 3462 * 3463 * However we take the opportunity to set the MLCR anyway, as 3464 * this register also controls the SEEPROM auto-access method 3465 * which we may want to use later ... 3466 * 3467 * The proper value here depends on the way the chip is wired 3468 * into the circuit board, as this register *also* controls which 3469 * of the "Miscellaneous I/O" pins are driven as outputs and the 3470 * values driven onto those pins! 3471 * 3472 * See also step 74 in the PRM ... 3473 */ 3474 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3475 bgep->chipid.bge_mlcr_default); 3476 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3477 3478 /* 3479 * Step 20: clear the Ethernet MAC mode register 3480 */ 3481 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3482 3483 /* 3484 * Step 21: restore cache-line-size, latency timer, and 3485 * subsystem ID registers to their original values (not 3486 * those read into the local structure <chipid>, 'cos 3487 * that was after they were cleared by the RESET). 3488 * 3489 * Note: the Subsystem Vendor/Device ID registers are not 3490 * directly writable in config space, so we use the shadow 3491 * copy in "Page Zero" of register space to restore them 3492 * both in one go ... 3493 */ 3494 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3495 bgep->chipid.clsize); 3496 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3497 bgep->chipid.latency); 3498 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3499 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3500 3501 /* 3502 * The SEND INDEX registers should be reset to zero by the 3503 * global chip reset; if they're not, there'll be trouble 3504 * later on. 3505 */ 3506 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3507 if (sx0 != 0) { 3508 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3509 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3510 retval = DDI_FAILURE; 3511 } 3512 3513 /* Enable MSI code */ 3514 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3515 bge_reg_set32(bgep, MSI_MODE_REG, 3516 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3517 3518 /* 3519 * On the first time through, save the factory-set MAC address 3520 * (if any). If bge_poll_firmware() above didn't return one 3521 * (from a chip register) consider looking in the attached NV 3522 * memory device, if any. Once we have it, we save it in both 3523 * register-image (64-bit) and byte-array forms. All-zero and 3524 * all-one addresses are not valid, and we refuse to stash those. 3525 */ 3526 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3527 if (mac == 0ULL) 3528 mac = bge_get_nvmac(bgep); 3529 if (mac != 0ULL && mac != ~0ULL) { 3530 bgep->chipid.hw_mac_addr = mac; 3531 for (i = ETHERADDRL; i-- != 0; ) { 3532 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3533 mac >>= 8; 3534 } 3535 bgep->chipid.vendor_addr.set = B_TRUE; 3536 } 3537 } 3538 3539 #ifdef BGE_IPMI_ASF 3540 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3541 if (asf_mode != ASF_MODE_NONE) { 3542 if ((asf_mode == ASF_MODE_INIT) || 3543 (asf_mode == ASF_MODE_POST_INIT)) { 3544 3545 bge_asf_post_reset_new_mode(bgep, 3546 BGE_INIT_RESET); 3547 } else { 3548 bge_asf_post_reset_new_mode(bgep, 3549 BGE_SHUTDOWN_RESET); 3550 } 3551 } 3552 } 3553 #endif 3554 3555 /* 3556 * Record the new state 3557 */ 3558 bgep->chip_resets += 1; 3559 bgep->bge_chip_state = BGE_CHIP_RESET; 3560 return (retval); 3561 } 3562 3563 /* 3564 * bge_chip_start() -- start the chip transmitting and/or receiving, 3565 * including enabling interrupts 3566 */ 3567 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3568 #pragma no_inline(bge_chip_start) 3569 3570 int 3571 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3572 { 3573 uint32_t coalmode; 3574 uint32_t ledctl; 3575 uint32_t mtu; 3576 uint32_t maxring; 3577 uint32_t stats_mask; 3578 uint32_t dma_wrprio; 3579 uint64_t ring; 3580 int retval = DDI_SUCCESS; 3581 3582 BGE_TRACE(("bge_chip_start($%p)", 3583 (void *)bgep)); 3584 3585 ASSERT(mutex_owned(bgep->genlock)); 3586 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3587 3588 /* 3589 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3590 * The document specifies 95 separate steps to fully 3591 * initialise the chip!!!! 3592 * 3593 * The reset code above has already got us as far as step 3594 * 21, so we continue with ... 3595 * 3596 * Step 22: clear the MAC statistics block 3597 * (0x0300-0x0aff in NIC-local memory) 3598 */ 3599 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3600 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3601 NIC_MEM_STATISTICS_SIZE); 3602 3603 /* 3604 * Step 23: clear the status block (in host memory) 3605 */ 3606 DMA_ZERO(bgep->status_block); 3607 3608 /* 3609 * Step 24: set DMA read/write control register 3610 */ 3611 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3612 bgep->chipid.bge_dma_rwctrl); 3613 3614 /* 3615 * Step 25: Configure DMA endianness -- already done (16/17) 3616 * Step 26: Configure Host-Based Send Rings 3617 * Step 27: Indicate Host Stack Up 3618 */ 3619 bge_reg_set32(bgep, MODE_CONTROL_REG, 3620 MODE_HOST_SEND_BDS | 3621 MODE_HOST_STACK_UP); 3622 3623 /* 3624 * Step 28: Configure checksum options: 3625 * Solaris supports the hardware default checksum options. 3626 * 3627 * Workaround for Incorrect pseudo-header checksum calculation. 3628 */ 3629 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3630 bge_reg_set32(bgep, MODE_CONTROL_REG, 3631 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3632 3633 /* 3634 * Step 29: configure Timer Prescaler. The value is always the 3635 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3636 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3637 * for the whole chip! 3638 */ 3639 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3640 3641 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 3642 drv_usecwait(40); 3643 /* put PHY into ready state */ 3644 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ); 3645 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */ 3646 drv_usecwait(40); 3647 } 3648 3649 /* 3650 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3651 * 3652 * If the mbuf_length is specified as 0, we just leave these at 3653 * their hardware defaults, rather than explicitly setting them. 3654 * As the Broadcom HRM,driver better not change the parameters 3655 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3656 */ 3657 if ((bgep->chipid.mbuf_length != 0) && 3658 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3659 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3660 bgep->chipid.mbuf_base); 3661 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3662 bgep->chipid.mbuf_length); 3663 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3664 DMAD_POOL_BASE_DEFAULT); 3665 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3666 DMAD_POOL_LENGTH_DEFAULT); 3667 } 3668 3669 /* 3670 * Step 32: configure MAC memory pool watermarks 3671 */ 3672 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3673 bgep->chipid.mbuf_lo_water_rdma); 3674 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3675 bgep->chipid.mbuf_lo_water_rmac); 3676 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3677 bgep->chipid.mbuf_hi_water); 3678 3679 /* 3680 * Step 33: configure DMA resource watermarks 3681 */ 3682 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3683 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3684 bge_dmad_lo_water); 3685 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3686 bge_dmad_hi_water); 3687 } 3688 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3689 3690 /* 3691 * Steps 34-36: enable buffer manager & internal h/w queues 3692 */ 3693 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3694 STATE_MACHINE_ATTN_ENABLE_BIT)) 3695 retval = DDI_FAILURE; 3696 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3697 retval = DDI_FAILURE; 3698 3699 /* 3700 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3701 */ 3702 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3703 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3704 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3705 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3706 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3707 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3708 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3709 } 3710 3711 /* 3712 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3713 */ 3714 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3715 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3716 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3717 bge_replenish_jumbo); 3718 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3719 bge_replenish_mini); 3720 } 3721 3722 /* 3723 * Steps 41-43: clear Send Ring Producer Indices and initialise 3724 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3725 */ 3726 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3727 maxring = BGE_SEND_RINGS_MAX; 3728 else 3729 maxring = BGE_SEND_RINGS_MAX_5705; 3730 for (ring = 0; ring < maxring; ++ring) { 3731 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3732 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3733 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3734 &bgep->send[ring].hw_rcb); 3735 } 3736 3737 /* 3738 * Steps 44-45: initialise Receive Return Rings 3739 * (0x0200-0x02ff in NIC-local memory) 3740 */ 3741 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3742 maxring = BGE_RECV_RINGS_MAX; 3743 else 3744 maxring = BGE_RECV_RINGS_MAX_5705; 3745 for (ring = 0; ring < maxring; ++ring) 3746 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3747 &bgep->recv[ring].hw_rcb); 3748 3749 /* 3750 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3751 */ 3752 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3753 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3754 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3755 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3756 } 3757 /* 3758 * Step 47: configure the MAC unicast address 3759 * Step 48: configure the random backoff seed 3760 * Step 96: set up multicast filters 3761 */ 3762 #ifdef BGE_IPMI_ASF 3763 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3764 #else 3765 if (bge_chip_sync(bgep) == DDI_FAILURE) 3766 #endif 3767 retval = DDI_FAILURE; 3768 3769 /* 3770 * Step 49: configure the MTU 3771 */ 3772 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3773 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3774 3775 /* 3776 * Step 50: configure the IPG et al 3777 */ 3778 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3779 3780 /* 3781 * Step 51: configure the default Rx Return Ring 3782 */ 3783 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3784 3785 /* 3786 * Steps 52-54: configure Receive List Placement, 3787 * and enable Receive List Placement Statistics 3788 */ 3789 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3790 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3791 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3792 case MHCR_CHIP_ASIC_REV_5700: 3793 case MHCR_CHIP_ASIC_REV_5701: 3794 case MHCR_CHIP_ASIC_REV_5703: 3795 case MHCR_CHIP_ASIC_REV_5704: 3796 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3797 break; 3798 case MHCR_CHIP_ASIC_REV_5705: 3799 break; 3800 default: 3801 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3802 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3803 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3804 break; 3805 } 3806 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3807 3808 if (bgep->chipid.rx_rings > 1) 3809 bge_init_recv_rule(bgep); 3810 3811 /* 3812 * Steps 55-56: enable Send Data Initiator Statistics 3813 */ 3814 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3815 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3816 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3817 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3818 } else { 3819 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3820 SEND_INIT_STATS_ENABLE); 3821 } 3822 /* 3823 * Steps 57-58: stop (?) the Host Coalescing Engine 3824 */ 3825 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3826 retval = DDI_FAILURE; 3827 3828 /* 3829 * Steps 59-62: initialise Host Coalescing parameters 3830 */ 3831 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3832 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3833 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3834 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3835 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3836 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3837 bge_tx_count_intr); 3838 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3839 bge_tx_ticks_intr); 3840 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3841 bge_rx_count_intr); 3842 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3843 bge_rx_ticks_intr); 3844 } 3845 3846 /* 3847 * Steps 63-64: initialise status block & statistics 3848 * host memory addresses 3849 * The statistic block does not exist in some chipsets 3850 * Step 65: initialise Statistics Coalescing Tick Counter 3851 */ 3852 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3853 bgep->status_block.cookie.dmac_laddress); 3854 3855 /* 3856 * Steps 66-67: initialise status block & statistics 3857 * NIC-local memory addresses 3858 */ 3859 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3860 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3861 bgep->statistics.cookie.dmac_laddress); 3862 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3863 STATISTICS_TICKS_DEFAULT); 3864 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3865 NIC_MEM_STATUS_BLOCK); 3866 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3867 NIC_MEM_STATISTICS); 3868 } 3869 3870 /* 3871 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3872 * Completion Engine, the Receive List Placement Engine, and the 3873 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3874 * and BCM5715. 3875 */ 3876 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3877 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3878 coalmode = COALESCE_64_BYTE_STATUS; 3879 else 3880 coalmode = 0; 3881 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3882 retval = DDI_FAILURE; 3883 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3884 STATE_MACHINE_ATTN_ENABLE_BIT)) 3885 retval = DDI_FAILURE; 3886 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3887 retval = DDI_FAILURE; 3888 3889 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3890 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3891 STATE_MACHINE_ATTN_ENABLE_BIT)) 3892 retval = DDI_FAILURE; 3893 3894 /* 3895 * Step 72: Enable MAC DMA engines 3896 * Step 73: Clear & enable MAC statistics 3897 */ 3898 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3899 ETHERNET_MODE_ENABLE_FHDE | 3900 ETHERNET_MODE_ENABLE_RDE | 3901 ETHERNET_MODE_ENABLE_TDE); 3902 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3903 ETHERNET_MODE_ENABLE_TX_STATS | 3904 ETHERNET_MODE_ENABLE_RX_STATS | 3905 ETHERNET_MODE_CLEAR_TX_STATS | 3906 ETHERNET_MODE_CLEAR_RX_STATS); 3907 3908 /* 3909 * Step 74: configure the MLCR (Miscellaneous Local Control 3910 * Register); not required, as we set up the MLCR in step 10 3911 * (part of the reset code) above. 3912 * 3913 * Step 75: clear Interrupt Mailbox 0 3914 */ 3915 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3916 3917 /* 3918 * Steps 76-87: Gentlemen, start your engines ... 3919 * 3920 * Enable the DMA Completion Engine, the Write DMA Engine, 3921 * the Read DMA Engine, Receive Data Completion Engine, 3922 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3923 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3924 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3925 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3926 * 3927 * Beware exhaust fumes? 3928 */ 3929 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3930 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3931 retval = DDI_FAILURE; 3932 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 3933 ALL_DMA_ATTN_BITS; 3934 if ((MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3935 MHCR_CHIP_ASIC_REV_5755) || 3936 (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3937 MHCR_CHIP_ASIC_REV_5906)) { 3938 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 3939 } 3940 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3941 dma_wrprio)) 3942 retval = DDI_FAILURE; 3943 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3944 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3945 retval = DDI_FAILURE; 3946 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3947 STATE_MACHINE_ATTN_ENABLE_BIT)) 3948 retval = DDI_FAILURE; 3949 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3950 if (!bge_chip_enable_engine(bgep, 3951 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3952 retval = DDI_FAILURE; 3953 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3954 retval = DDI_FAILURE; 3955 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3956 STATE_MACHINE_ATTN_ENABLE_BIT)) 3957 retval = DDI_FAILURE; 3958 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3959 RCV_BD_DISABLED_RING_ATTN)) 3960 retval = DDI_FAILURE; 3961 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3962 RCV_DATA_BD_ILL_RING_ATTN)) 3963 retval = DDI_FAILURE; 3964 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3965 retval = DDI_FAILURE; 3966 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3967 STATE_MACHINE_ATTN_ENABLE_BIT)) 3968 retval = DDI_FAILURE; 3969 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3970 STATE_MACHINE_ATTN_ENABLE_BIT)) 3971 retval = DDI_FAILURE; 3972 3973 /* 3974 * Step 88: download firmware -- doesn't apply 3975 * Steps 89-90: enable Transmit & Receive MAC Engines 3976 */ 3977 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3978 retval = DDI_FAILURE; 3979 #ifdef BGE_IPMI_ASF 3980 if (!bgep->asf_enabled) { 3981 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3982 RECEIVE_MODE_KEEP_VLAN_TAG)) 3983 retval = DDI_FAILURE; 3984 } else { 3985 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3986 retval = DDI_FAILURE; 3987 } 3988 #else 3989 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3990 RECEIVE_MODE_KEEP_VLAN_TAG)) 3991 retval = DDI_FAILURE; 3992 #endif 3993 3994 /* 3995 * Step 91: disable auto-polling of PHY status 3996 */ 3997 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3998 3999 /* 4000 * Step 92: configure D0 power state (not required) 4001 * Step 93: initialise LED control register () 4002 */ 4003 ledctl = LED_CONTROL_DEFAULT; 4004 switch (bgep->chipid.device) { 4005 case DEVICE_ID_5700: 4006 case DEVICE_ID_5700x: 4007 case DEVICE_ID_5701: 4008 /* 4009 * Switch to 5700 (MAC) mode on these older chips 4010 */ 4011 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 4012 ledctl |= LED_CONTROL_LED_MODE_5700; 4013 break; 4014 4015 default: 4016 break; 4017 } 4018 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 4019 4020 /* 4021 * Step 94: activate link 4022 */ 4023 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 4024 4025 /* 4026 * Step 95: set up physical layer (PHY/SerDes) 4027 * restart autoneg (if required) 4028 */ 4029 if (reset_phys) 4030 if (bge_phys_update(bgep) == DDI_FAILURE) 4031 retval = DDI_FAILURE; 4032 4033 /* 4034 * Extra step (DSG): hand over all the Receive Buffers to the chip 4035 */ 4036 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 4037 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 4038 bgep->buff[ring].rf_next); 4039 4040 /* 4041 * MSI bits:The least significant MSI 16-bit word. 4042 * ISR will be triggered different. 4043 */ 4044 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 4045 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 4046 4047 /* 4048 * Extra step (DSG): select which interrupts are enabled 4049 * 4050 * Program the Ethernet MAC engine to signal attention on 4051 * Link Change events, then enable interrupts on MAC, DMA, 4052 * and FLOW attention signals. 4053 */ 4054 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 4055 ETHERNET_EVENT_LINK_INT | 4056 ETHERNET_STATUS_PCS_ERROR_INT); 4057 #ifdef BGE_IPMI_ASF 4058 if (bgep->asf_enabled) { 4059 bge_reg_set32(bgep, MODE_CONTROL_REG, 4060 MODE_INT_ON_FLOW_ATTN | 4061 MODE_INT_ON_DMA_ATTN | 4062 MODE_HOST_STACK_UP| 4063 MODE_INT_ON_MAC_ATTN); 4064 } else { 4065 #endif 4066 bge_reg_set32(bgep, MODE_CONTROL_REG, 4067 MODE_INT_ON_FLOW_ATTN | 4068 MODE_INT_ON_DMA_ATTN | 4069 MODE_INT_ON_MAC_ATTN); 4070 #ifdef BGE_IPMI_ASF 4071 } 4072 #endif 4073 4074 /* 4075 * Step 97: enable PCI interrupts!!! 4076 */ 4077 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 4078 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 4079 MHCR_MASK_PCI_INT_OUTPUT); 4080 4081 /* 4082 * All done! 4083 */ 4084 bgep->bge_chip_state = BGE_CHIP_RUNNING; 4085 return (retval); 4086 } 4087 4088 4089 /* 4090 * ========== Hardware interrupt handler ========== 4091 */ 4092 4093 #undef BGE_DBG 4094 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 4095 4096 /* 4097 * Sync the status block, then atomically clear the specified bits in 4098 * the <flags-and-tag> field of the status block. 4099 * the <flags> word of the status block, returning the value of the 4100 * <tag> and the <flags> before the bits were cleared. 4101 */ 4102 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 4103 #pragma inline(bge_status_sync) 4104 4105 static int 4106 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 4107 { 4108 bge_status_t *bsp; 4109 int retval; 4110 4111 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 4112 (void *)bgep, bits)); 4113 4114 ASSERT(bgep->bge_guard == BGE_GUARD); 4115 4116 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 4117 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 4118 if (retval != DDI_FM_OK) 4119 return (retval); 4120 4121 bsp = DMA_VPTR(bgep->status_block); 4122 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 4123 4124 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 4125 (void *)bgep, bits, *flags)); 4126 4127 return (retval); 4128 } 4129 4130 void bge_wake_factotum(bge_t *bgep); 4131 #pragma inline(bge_wake_factotum) 4132 4133 void 4134 bge_wake_factotum(bge_t *bgep) 4135 { 4136 mutex_enter(bgep->softintrlock); 4137 if (bgep->factotum_flag == 0) { 4138 bgep->factotum_flag = 1; 4139 ddi_trigger_softintr(bgep->factotum_id); 4140 } 4141 mutex_exit(bgep->softintrlock); 4142 } 4143 4144 /* 4145 * bge_intr() -- handle chip interrupts 4146 */ 4147 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 4148 #pragma no_inline(bge_intr) 4149 4150 uint_t 4151 bge_intr(caddr_t arg1, caddr_t arg2) 4152 { 4153 bge_t *bgep = (void *)arg1; /* private device info */ 4154 bge_status_t *bsp; 4155 uint64_t flags; 4156 uint32_t regval; 4157 uint_t result; 4158 int retval, loop_cnt = 0; 4159 4160 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 4161 4162 /* 4163 * GLD v2 checks that s/w setup is complete before passing 4164 * interrupts to this routine, thus eliminating the old 4165 * (and well-known) race condition around ddi_add_intr() 4166 */ 4167 ASSERT(bgep->progress & PROGRESS_HWINT); 4168 4169 result = DDI_INTR_UNCLAIMED; 4170 mutex_enter(bgep->genlock); 4171 4172 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4173 /* 4174 * Check whether chip's says it's asserting #INTA; 4175 * if not, don't process or claim the interrupt. 4176 * 4177 * Note that the PCI signal is active low, so the 4178 * bit is *zero* when the interrupt is asserted. 4179 */ 4180 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 4181 if (regval & MLCR_INTA_STATE) { 4182 if (bge_check_acc_handle(bgep, bgep->io_handle) 4183 != DDI_FM_OK) 4184 goto chip_stop; 4185 mutex_exit(bgep->genlock); 4186 return (result); 4187 } 4188 4189 /* 4190 * Block further PCI interrupts ... 4191 */ 4192 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 4193 MHCR_MASK_PCI_INT_OUTPUT); 4194 4195 } else { 4196 /* 4197 * Check MSI status 4198 */ 4199 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 4200 if (regval & MSI_ERROR_ATTENTION) { 4201 BGE_REPORT((bgep, "msi error attention," 4202 " status=0x%x", regval)); 4203 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 4204 } 4205 } 4206 4207 result = DDI_INTR_CLAIMED; 4208 4209 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 4210 4211 /* 4212 * Sync the status block and grab the flags-n-tag from it. 4213 * We count the number of interrupts where there doesn't 4214 * seem to have been a DMA update of the status block; if 4215 * it *has* been updated, the counter will be cleared in 4216 * the while() loop below ... 4217 */ 4218 bgep->missed_dmas += 1; 4219 bsp = DMA_VPTR(bgep->status_block); 4220 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 4221 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 4222 /* 4223 * bge_chip_stop() may have freed dma area etc 4224 * while we were in this interrupt handler - 4225 * better not call bge_status_sync() 4226 */ 4227 (void) bge_check_acc_handle(bgep, 4228 bgep->io_handle); 4229 mutex_exit(bgep->genlock); 4230 return (DDI_INTR_CLAIMED); 4231 } 4232 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 4233 &flags); 4234 if (retval != DDI_FM_OK) { 4235 bgep->bge_dma_error = B_TRUE; 4236 goto chip_stop; 4237 } 4238 4239 if (!(flags & STATUS_FLAG_UPDATED)) 4240 break; 4241 4242 /* 4243 * Tell the chip that we're processing the interrupt 4244 */ 4245 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4246 INTERRUPT_MBOX_DISABLE(flags)); 4247 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4248 DDI_FM_OK) 4249 goto chip_stop; 4250 4251 /* 4252 * Drop the mutex while we: 4253 * Receive any newly-arrived packets 4254 * Recycle any newly-finished send buffers 4255 */ 4256 bgep->bge_intr_running = B_TRUE; 4257 mutex_exit(bgep->genlock); 4258 bge_receive(bgep, bsp); 4259 bge_recycle(bgep, bsp); 4260 mutex_enter(bgep->genlock); 4261 bgep->bge_intr_running = B_FALSE; 4262 4263 /* 4264 * Tell the chip we've finished processing, and 4265 * give it the tag that we got from the status 4266 * block earlier, so that it knows just how far 4267 * we've gone. If it's got more for us to do, 4268 * it will now update the status block and try 4269 * to assert an interrupt (but we've got the 4270 * #INTA blocked at present). If we see the 4271 * update, we'll loop around to do some more. 4272 * Eventually we'll get out of here ... 4273 */ 4274 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4275 INTERRUPT_MBOX_ENABLE(flags)); 4276 if (bgep->chipid.pci_type == BGE_PCI_E) 4277 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 4278 bgep->missed_dmas = 0; 4279 } 4280 4281 /* 4282 * Check for exceptional conditions that we need to handle 4283 * 4284 * Link status changed 4285 * Status block not updated 4286 */ 4287 if (flags & STATUS_FLAG_LINK_CHANGED) 4288 bge_wake_factotum(bgep); 4289 4290 if (bgep->missed_dmas) { 4291 /* 4292 * Probably due to the internal status tag not 4293 * being reset. Force a status block update now; 4294 * this should ensure that we get an update and 4295 * a new interrupt. After that, we should be in 4296 * sync again ... 4297 */ 4298 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4299 "not updated?", flags)); 4300 bgep->missed_updates++; 4301 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4302 COALESCE_NOW); 4303 4304 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4305 /* 4306 * If this happens multiple times in a row, 4307 * it means DMA is just not working. Maybe 4308 * the chip's failed, or maybe there's a 4309 * problem on the PCI bus or in the host-PCI 4310 * bridge (Tomatillo). 4311 * 4312 * At all events, we want to stop further 4313 * interrupts and let the recovery code take 4314 * over to see whether anything can be done 4315 * about it ... 4316 */ 4317 bge_fm_ereport(bgep, 4318 DDI_FM_DEVICE_BADINT_LIMIT); 4319 goto chip_stop; 4320 } 4321 } 4322 4323 /* 4324 * Reenable assertion of #INTA, unless there's a DMA fault 4325 */ 4326 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4327 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4328 MHCR_MASK_PCI_INT_OUTPUT); 4329 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4330 DDI_FM_OK) 4331 goto chip_stop; 4332 } 4333 4334 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4335 goto chip_stop; 4336 4337 mutex_exit(bgep->genlock); 4338 return (result); 4339 4340 chip_stop: 4341 #ifdef BGE_IPMI_ASF 4342 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4343 /* 4344 * We must stop ASF heart beat before 4345 * bge_chip_stop(), otherwise some 4346 * computers (ex. IBM HS20 blade 4347 * server) may crash. 4348 */ 4349 bge_asf_update_status(bgep); 4350 bge_asf_stop_timer(bgep); 4351 bgep->asf_status = ASF_STAT_STOP; 4352 4353 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4354 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4355 } 4356 #endif 4357 bge_chip_stop(bgep, B_TRUE); 4358 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4359 mutex_exit(bgep->genlock); 4360 return (result); 4361 } 4362 4363 /* 4364 * ========== Factotum, implemented as a softint handler ========== 4365 */ 4366 4367 #undef BGE_DBG 4368 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4369 4370 static void bge_factotum_error_handler(bge_t *bgep); 4371 #pragma no_inline(bge_factotum_error_handler) 4372 4373 static void 4374 bge_factotum_error_handler(bge_t *bgep) 4375 { 4376 uint32_t flow; 4377 uint32_t rdma; 4378 uint32_t wdma; 4379 uint32_t tmac; 4380 uint32_t rmac; 4381 uint32_t rxrs; 4382 uint32_t txrs = 0; 4383 4384 ASSERT(mutex_owned(bgep->genlock)); 4385 4386 /* 4387 * Read all the registers that show the possible 4388 * reasons for the ERROR bit to be asserted 4389 */ 4390 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4391 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4392 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4393 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4394 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4395 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4396 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4397 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4398 4399 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4400 (void *)bgep, flow, rdma, wdma)); 4401 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4402 (void *)bgep, tmac, rmac, rxrs, txrs)); 4403 4404 /* 4405 * For now, just clear all the errors ... 4406 */ 4407 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4408 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4409 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4410 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4411 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4412 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4413 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4414 } 4415 4416 /* 4417 * Handler for hardware link state change. 4418 * 4419 * When this routine is called, the hardware link state has changed 4420 * and the new state is reflected in the param_* variables. Here 4421 * we must update the softstate and reprogram the MAC to match. 4422 */ 4423 static void bge_factotum_link_handler(bge_t *bgep); 4424 #pragma no_inline(bge_factotum_link_handler) 4425 4426 static void 4427 bge_factotum_link_handler(bge_t *bgep) 4428 { 4429 ASSERT(mutex_owned(bgep->genlock)); 4430 4431 /* 4432 * Update the s/w link_state 4433 */ 4434 if (bgep->param_link_up) 4435 bgep->link_state = LINK_STATE_UP; 4436 else 4437 bgep->link_state = LINK_STATE_DOWN; 4438 4439 /* 4440 * Reprogram the MAC modes to match 4441 */ 4442 bge_sync_mac_modes(bgep); 4443 } 4444 4445 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4446 #pragma no_inline(bge_factotum_link_check) 4447 4448 static boolean_t 4449 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4450 { 4451 boolean_t check; 4452 uint64_t flags; 4453 uint32_t tmac_status; 4454 4455 ASSERT(mutex_owned(bgep->genlock)); 4456 4457 /* 4458 * Get & clear the writable status bits in the Tx status register 4459 * (some bits are write-1-to-clear, others are just readonly). 4460 */ 4461 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4462 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4463 4464 /* 4465 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4466 */ 4467 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4468 STATUS_FLAG_LINK_CHANGED, &flags); 4469 if (*dma_state != DDI_FM_OK) 4470 return (B_FALSE); 4471 4472 /* 4473 * Clear any errors flagged in the status block ... 4474 */ 4475 if (flags & STATUS_FLAG_ERROR) 4476 bge_factotum_error_handler(bgep); 4477 4478 /* 4479 * We need to check the link status if: 4480 * the status block says there's been a link change 4481 * or there's any discrepancy between the various 4482 * flags indicating the link state (link_state, 4483 * param_link_up, and the LINK STATE bit in the 4484 * Transmit MAC status register). 4485 */ 4486 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4487 switch (bgep->link_state) { 4488 case LINK_STATE_UP: 4489 check |= (bgep->param_link_up == B_FALSE); 4490 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4491 break; 4492 4493 case LINK_STATE_DOWN: 4494 check |= (bgep->param_link_up != B_FALSE); 4495 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4496 break; 4497 4498 default: 4499 check = B_TRUE; 4500 break; 4501 } 4502 4503 /* 4504 * If <check> is false, we're sure the link hasn't changed. 4505 * If true, however, it's not yet definitive; we have to call 4506 * bge_phys_check() to determine whether the link has settled 4507 * into a new state yet ... and if it has, then call the link 4508 * state change handler.But when the chip is 5700 in Dell 6650 4509 * ,even if check is false, the link may have changed.So we 4510 * have to call bge_phys_check() to determine the link state. 4511 */ 4512 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4513 check = bge_phys_check(bgep); 4514 if (check) 4515 bge_factotum_link_handler(bgep); 4516 } 4517 4518 return (check); 4519 } 4520 4521 /* 4522 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4523 */ 4524 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4525 #pragma no_inline(bge_factotum_stall_check) 4526 4527 static boolean_t 4528 bge_factotum_stall_check(bge_t *bgep) 4529 { 4530 uint32_t dogval; 4531 4532 ASSERT(mutex_owned(bgep->genlock)); 4533 4534 /* 4535 * Specific check for Tx stall ... 4536 * 4537 * The 'watchdog' counter is incremented whenever a packet 4538 * is queued, reset to 1 when some (but not all) buffers 4539 * are reclaimed, reset to 0 (disabled) when all buffers 4540 * are reclaimed, and shifted left here. If it exceeds the 4541 * threshold value, the chip is assumed to have stalled and 4542 * is put into the ERROR state. The factotum will then reset 4543 * it on the next pass. 4544 * 4545 * All of which should ensure that we don't get into a state 4546 * where packets are left pending indefinitely! 4547 */ 4548 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4549 if (dogval < bge_watchdog_count) 4550 return (B_FALSE); 4551 4552 #if !defined(BGE_NETCONSOLE) 4553 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4554 #endif 4555 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4556 return (B_TRUE); 4557 } 4558 4559 /* 4560 * The factotum is woken up when there's something to do that we'd rather 4561 * not do from inside a hardware interrupt handler or high-level cyclic. 4562 * Its two main tasks are: 4563 * reset & restart the chip after an error 4564 * check the link status whenever necessary 4565 */ 4566 uint_t bge_chip_factotum(caddr_t arg); 4567 #pragma no_inline(bge_chip_factotum) 4568 4569 uint_t 4570 bge_chip_factotum(caddr_t arg) 4571 { 4572 bge_t *bgep; 4573 uint_t result; 4574 boolean_t error; 4575 boolean_t linkchg; 4576 int dma_state; 4577 4578 bgep = (void *)arg; 4579 4580 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4581 4582 mutex_enter(bgep->softintrlock); 4583 if (bgep->factotum_flag == 0) { 4584 mutex_exit(bgep->softintrlock); 4585 return (DDI_INTR_UNCLAIMED); 4586 } 4587 bgep->factotum_flag = 0; 4588 mutex_exit(bgep->softintrlock); 4589 4590 result = DDI_INTR_CLAIMED; 4591 error = B_FALSE; 4592 linkchg = B_FALSE; 4593 4594 mutex_enter(bgep->genlock); 4595 switch (bgep->bge_chip_state) { 4596 default: 4597 break; 4598 4599 case BGE_CHIP_RUNNING: 4600 linkchg = bge_factotum_link_check(bgep, &dma_state); 4601 error = bge_factotum_stall_check(bgep); 4602 if (dma_state != DDI_FM_OK) { 4603 bgep->bge_dma_error = B_TRUE; 4604 error = B_TRUE; 4605 } 4606 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4607 error = B_TRUE; 4608 if (error) 4609 bgep->bge_chip_state = BGE_CHIP_ERROR; 4610 break; 4611 4612 case BGE_CHIP_ERROR: 4613 error = B_TRUE; 4614 break; 4615 4616 case BGE_CHIP_FAULT: 4617 /* 4618 * Fault detected, time to reset ... 4619 */ 4620 if (bge_autorecover) { 4621 if (!(bgep->progress & PROGRESS_BUFS)) { 4622 /* 4623 * if we can't allocate the ring buffers, 4624 * try later 4625 */ 4626 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4627 mutex_exit(bgep->genlock); 4628 return (result); 4629 } 4630 bgep->progress |= PROGRESS_BUFS; 4631 } 4632 if (!(bgep->progress & PROGRESS_INTR)) { 4633 bge_init_rings(bgep); 4634 bge_intr_enable(bgep); 4635 bgep->progress |= PROGRESS_INTR; 4636 } 4637 if (!(bgep->progress & PROGRESS_KSTATS)) { 4638 bge_init_kstats(bgep, 4639 ddi_get_instance(bgep->devinfo)); 4640 bgep->progress |= PROGRESS_KSTATS; 4641 } 4642 4643 BGE_REPORT((bgep, "automatic recovery activated")); 4644 4645 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4646 bgep->bge_chip_state = BGE_CHIP_ERROR; 4647 error = B_TRUE; 4648 } 4649 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4650 DDI_FM_OK) { 4651 bgep->bge_chip_state = BGE_CHIP_ERROR; 4652 error = B_TRUE; 4653 } 4654 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4655 DDI_FM_OK) { 4656 bgep->bge_chip_state = BGE_CHIP_ERROR; 4657 error = B_TRUE; 4658 } 4659 if (error == B_FALSE) { 4660 #ifdef BGE_IPMI_ASF 4661 if (bgep->asf_enabled && 4662 bgep->asf_status != ASF_STAT_RUN) { 4663 bgep->asf_timeout_id = timeout( 4664 bge_asf_heartbeat, (void *)bgep, 4665 drv_usectohz( 4666 BGE_ASF_HEARTBEAT_INTERVAL)); 4667 bgep->asf_status = ASF_STAT_RUN; 4668 } 4669 #endif 4670 if (!bgep->manual_reset) { 4671 ddi_fm_service_impact(bgep->devinfo, 4672 DDI_SERVICE_RESTORED); 4673 } 4674 } 4675 } 4676 break; 4677 } 4678 4679 4680 /* 4681 * If an error is detected, stop the chip now, marking it as 4682 * faulty, so that it will be reset next time through ... 4683 * 4684 * Note that if intr_running is set, then bge_intr() has dropped 4685 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4686 * this point so have to wait until the next time the factotum runs. 4687 */ 4688 if (error && !bgep->bge_intr_running) { 4689 #ifdef BGE_IPMI_ASF 4690 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4691 /* 4692 * We must stop ASF heart beat before bge_chip_stop(), 4693 * otherwise some computers (ex. IBM HS20 blade server) 4694 * may crash. 4695 */ 4696 bge_asf_update_status(bgep); 4697 bge_asf_stop_timer(bgep); 4698 bgep->asf_status = ASF_STAT_STOP; 4699 4700 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4701 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4702 } 4703 #endif 4704 bge_chip_stop(bgep, B_TRUE); 4705 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4706 } 4707 mutex_exit(bgep->genlock); 4708 4709 /* 4710 * If the link state changed, tell the world about it. 4711 * Note: can't do this while still holding the mutex. 4712 */ 4713 if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT && 4714 bgep->link_state != LINK_STATE_UNKNOWN) 4715 linkchg = B_TRUE; 4716 else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT && 4717 bgep->link_state == LINK_STATE_DOWN) 4718 linkchg = B_FALSE; 4719 4720 if (linkchg) { 4721 mac_link_update(bgep->mh, bgep->link_state); 4722 bgep->link_update_timer = BGE_LINK_UPDATE_DONE; 4723 } 4724 if (bgep->manual_reset) { 4725 bgep->manual_reset = B_FALSE; 4726 } 4727 4728 return (result); 4729 } 4730 4731 /* 4732 * High-level cyclic handler 4733 * 4734 * This routine schedules a (low-level) softint callback to the 4735 * factotum, and prods the chip to update the status block (which 4736 * will cause a hardware interrupt when complete). 4737 */ 4738 void bge_chip_cyclic(void *arg); 4739 #pragma no_inline(bge_chip_cyclic) 4740 4741 void 4742 bge_chip_cyclic(void *arg) 4743 { 4744 bge_t *bgep; 4745 4746 bgep = arg; 4747 4748 switch (bgep->bge_chip_state) { 4749 default: 4750 return; 4751 4752 case BGE_CHIP_RUNNING: 4753 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4754 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4755 ddi_fm_service_impact(bgep->devinfo, 4756 DDI_SERVICE_UNAFFECTED); 4757 4758 if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT) 4759 bgep->link_update_timer++; 4760 4761 break; 4762 4763 case BGE_CHIP_FAULT: 4764 case BGE_CHIP_ERROR: 4765 break; 4766 } 4767 4768 bge_wake_factotum(bgep); 4769 } 4770 4771 4772 /* 4773 * ========== Ioctl subfunctions ========== 4774 */ 4775 4776 #undef BGE_DBG 4777 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4778 4779 #if BGE_DEBUGGING || BGE_DO_PPIO 4780 4781 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4782 #pragma no_inline(bge_chip_peek_cfg) 4783 4784 static void 4785 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4786 { 4787 uint64_t regval; 4788 uint64_t regno; 4789 4790 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4791 (void *)bgep, (void *)ppd)); 4792 4793 regno = ppd->pp_acc_offset; 4794 4795 switch (ppd->pp_acc_size) { 4796 case 1: 4797 regval = pci_config_get8(bgep->cfg_handle, regno); 4798 break; 4799 4800 case 2: 4801 regval = pci_config_get16(bgep->cfg_handle, regno); 4802 break; 4803 4804 case 4: 4805 regval = pci_config_get32(bgep->cfg_handle, regno); 4806 break; 4807 4808 case 8: 4809 regval = pci_config_get64(bgep->cfg_handle, regno); 4810 break; 4811 } 4812 4813 ppd->pp_acc_data = regval; 4814 } 4815 4816 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4817 #pragma no_inline(bge_chip_poke_cfg) 4818 4819 static void 4820 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4821 { 4822 uint64_t regval; 4823 uint64_t regno; 4824 4825 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4826 (void *)bgep, (void *)ppd)); 4827 4828 regno = ppd->pp_acc_offset; 4829 regval = ppd->pp_acc_data; 4830 4831 switch (ppd->pp_acc_size) { 4832 case 1: 4833 pci_config_put8(bgep->cfg_handle, regno, regval); 4834 break; 4835 4836 case 2: 4837 pci_config_put16(bgep->cfg_handle, regno, regval); 4838 break; 4839 4840 case 4: 4841 pci_config_put32(bgep->cfg_handle, regno, regval); 4842 break; 4843 4844 case 8: 4845 pci_config_put64(bgep->cfg_handle, regno, regval); 4846 break; 4847 } 4848 } 4849 4850 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4851 #pragma no_inline(bge_chip_peek_reg) 4852 4853 static void 4854 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4855 { 4856 uint64_t regval; 4857 void *regaddr; 4858 4859 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4860 (void *)bgep, (void *)ppd)); 4861 4862 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4863 4864 switch (ppd->pp_acc_size) { 4865 case 1: 4866 regval = ddi_get8(bgep->io_handle, regaddr); 4867 break; 4868 4869 case 2: 4870 regval = ddi_get16(bgep->io_handle, regaddr); 4871 break; 4872 4873 case 4: 4874 regval = ddi_get32(bgep->io_handle, regaddr); 4875 break; 4876 4877 case 8: 4878 regval = ddi_get64(bgep->io_handle, regaddr); 4879 break; 4880 } 4881 4882 ppd->pp_acc_data = regval; 4883 } 4884 4885 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4886 #pragma no_inline(bge_chip_peek_reg) 4887 4888 static void 4889 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4890 { 4891 uint64_t regval; 4892 void *regaddr; 4893 4894 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4895 (void *)bgep, (void *)ppd)); 4896 4897 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4898 regval = ppd->pp_acc_data; 4899 4900 switch (ppd->pp_acc_size) { 4901 case 1: 4902 ddi_put8(bgep->io_handle, regaddr, regval); 4903 break; 4904 4905 case 2: 4906 ddi_put16(bgep->io_handle, regaddr, regval); 4907 break; 4908 4909 case 4: 4910 ddi_put32(bgep->io_handle, regaddr, regval); 4911 break; 4912 4913 case 8: 4914 ddi_put64(bgep->io_handle, regaddr, regval); 4915 break; 4916 } 4917 BGE_PCICHK(bgep); 4918 } 4919 4920 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4921 #pragma no_inline(bge_chip_peek_nic) 4922 4923 static void 4924 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4925 { 4926 uint64_t regoff; 4927 uint64_t regval; 4928 void *regaddr; 4929 4930 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4931 (void *)bgep, (void *)ppd)); 4932 4933 regoff = ppd->pp_acc_offset; 4934 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4935 regoff &= MWBAR_GRANULE_MASK; 4936 regoff += NIC_MEM_WINDOW_OFFSET; 4937 regaddr = PIO_ADDR(bgep, regoff); 4938 4939 switch (ppd->pp_acc_size) { 4940 case 1: 4941 regval = ddi_get8(bgep->io_handle, regaddr); 4942 break; 4943 4944 case 2: 4945 regval = ddi_get16(bgep->io_handle, regaddr); 4946 break; 4947 4948 case 4: 4949 regval = ddi_get32(bgep->io_handle, regaddr); 4950 break; 4951 4952 case 8: 4953 regval = ddi_get64(bgep->io_handle, regaddr); 4954 break; 4955 } 4956 4957 ppd->pp_acc_data = regval; 4958 } 4959 4960 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4961 #pragma no_inline(bge_chip_poke_nic) 4962 4963 static void 4964 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4965 { 4966 uint64_t regoff; 4967 uint64_t regval; 4968 void *regaddr; 4969 4970 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4971 (void *)bgep, (void *)ppd)); 4972 4973 regoff = ppd->pp_acc_offset; 4974 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4975 regoff &= MWBAR_GRANULE_MASK; 4976 regoff += NIC_MEM_WINDOW_OFFSET; 4977 regaddr = PIO_ADDR(bgep, regoff); 4978 regval = ppd->pp_acc_data; 4979 4980 switch (ppd->pp_acc_size) { 4981 case 1: 4982 ddi_put8(bgep->io_handle, regaddr, regval); 4983 break; 4984 4985 case 2: 4986 ddi_put16(bgep->io_handle, regaddr, regval); 4987 break; 4988 4989 case 4: 4990 ddi_put32(bgep->io_handle, regaddr, regval); 4991 break; 4992 4993 case 8: 4994 ddi_put64(bgep->io_handle, regaddr, regval); 4995 break; 4996 } 4997 BGE_PCICHK(bgep); 4998 } 4999 5000 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5001 #pragma no_inline(bge_chip_peek_mii) 5002 5003 static void 5004 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5005 { 5006 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 5007 (void *)bgep, (void *)ppd)); 5008 5009 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 5010 } 5011 5012 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5013 #pragma no_inline(bge_chip_poke_mii) 5014 5015 static void 5016 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5017 { 5018 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 5019 (void *)bgep, (void *)ppd)); 5020 5021 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 5022 } 5023 5024 #if BGE_SEE_IO32 5025 5026 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5027 #pragma no_inline(bge_chip_peek_seeprom) 5028 5029 static void 5030 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5031 { 5032 uint32_t data; 5033 int err; 5034 5035 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 5036 (void *)bgep, (void *)ppd)); 5037 5038 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 5039 ppd->pp_acc_data = err ? ~0ull : data; 5040 } 5041 5042 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5043 #pragma no_inline(bge_chip_poke_seeprom) 5044 5045 static void 5046 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5047 { 5048 uint32_t data; 5049 5050 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 5051 (void *)bgep, (void *)ppd)); 5052 5053 data = ppd->pp_acc_data; 5054 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 5055 } 5056 #endif /* BGE_SEE_IO32 */ 5057 5058 #if BGE_FLASH_IO32 5059 5060 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5061 #pragma no_inline(bge_chip_peek_flash) 5062 5063 static void 5064 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5065 { 5066 uint32_t data; 5067 int err; 5068 5069 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 5070 (void *)bgep, (void *)ppd)); 5071 5072 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 5073 ppd->pp_acc_data = err ? ~0ull : data; 5074 } 5075 5076 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5077 #pragma no_inline(bge_chip_poke_flash) 5078 5079 static void 5080 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5081 { 5082 uint32_t data; 5083 5084 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 5085 (void *)bgep, (void *)ppd)); 5086 5087 data = ppd->pp_acc_data; 5088 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 5089 ppd->pp_acc_offset, &data); 5090 } 5091 #endif /* BGE_FLASH_IO32 */ 5092 5093 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5094 #pragma no_inline(bge_chip_peek_mem) 5095 5096 static void 5097 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5098 { 5099 uint64_t regval; 5100 void *vaddr; 5101 5102 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 5103 (void *)bgep, (void *)ppd)); 5104 5105 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5106 5107 switch (ppd->pp_acc_size) { 5108 case 1: 5109 regval = *(uint8_t *)vaddr; 5110 break; 5111 5112 case 2: 5113 regval = *(uint16_t *)vaddr; 5114 break; 5115 5116 case 4: 5117 regval = *(uint32_t *)vaddr; 5118 break; 5119 5120 case 8: 5121 regval = *(uint64_t *)vaddr; 5122 break; 5123 } 5124 5125 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 5126 (void *)bgep, (void *)ppd, regval, vaddr)); 5127 5128 ppd->pp_acc_data = regval; 5129 } 5130 5131 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5132 #pragma no_inline(bge_chip_poke_mem) 5133 5134 static void 5135 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5136 { 5137 uint64_t regval; 5138 void *vaddr; 5139 5140 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 5141 (void *)bgep, (void *)ppd)); 5142 5143 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5144 regval = ppd->pp_acc_data; 5145 5146 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 5147 (void *)bgep, (void *)ppd, regval, vaddr)); 5148 5149 switch (ppd->pp_acc_size) { 5150 case 1: 5151 *(uint8_t *)vaddr = (uint8_t)regval; 5152 break; 5153 5154 case 2: 5155 *(uint16_t *)vaddr = (uint16_t)regval; 5156 break; 5157 5158 case 4: 5159 *(uint32_t *)vaddr = (uint32_t)regval; 5160 break; 5161 5162 case 8: 5163 *(uint64_t *)vaddr = (uint64_t)regval; 5164 break; 5165 } 5166 } 5167 5168 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5169 struct iocblk *iocp); 5170 #pragma no_inline(bge_pp_ioctl) 5171 5172 static enum ioc_reply 5173 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5174 { 5175 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 5176 bge_peekpoke_t *ppd; 5177 dma_area_t *areap; 5178 uint64_t sizemask; 5179 uint64_t mem_va; 5180 uint64_t maxoff; 5181 boolean_t peek; 5182 5183 switch (cmd) { 5184 default: 5185 /* NOTREACHED */ 5186 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 5187 return (IOC_INVAL); 5188 5189 case BGE_PEEK: 5190 peek = B_TRUE; 5191 break; 5192 5193 case BGE_POKE: 5194 peek = B_FALSE; 5195 break; 5196 } 5197 5198 /* 5199 * Validate format of ioctl 5200 */ 5201 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 5202 return (IOC_INVAL); 5203 if (mp->b_cont == NULL) 5204 return (IOC_INVAL); 5205 ppd = (void *)mp->b_cont->b_rptr; 5206 5207 /* 5208 * Validate request parameters 5209 */ 5210 switch (ppd->pp_acc_space) { 5211 default: 5212 return (IOC_INVAL); 5213 5214 case BGE_PP_SPACE_CFG: 5215 /* 5216 * Config space 5217 */ 5218 sizemask = 8|4|2|1; 5219 mem_va = 0; 5220 maxoff = PCI_CONF_HDR_SIZE; 5221 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 5222 break; 5223 5224 case BGE_PP_SPACE_REG: 5225 /* 5226 * Memory-mapped I/O space 5227 */ 5228 sizemask = 8|4|2|1; 5229 mem_va = 0; 5230 maxoff = RIAAR_REGISTER_MAX; 5231 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 5232 break; 5233 5234 case BGE_PP_SPACE_NIC: 5235 /* 5236 * NIC on-chip memory 5237 */ 5238 sizemask = 8|4|2|1; 5239 mem_va = 0; 5240 maxoff = MWBAR_ONCHIP_MAX; 5241 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 5242 break; 5243 5244 case BGE_PP_SPACE_MII: 5245 /* 5246 * PHY's MII registers 5247 * NB: all PHY registers are two bytes, but the 5248 * addresses increment in ones (word addressing). 5249 * So we scale the address here, then undo the 5250 * transformation inside the peek/poke functions. 5251 */ 5252 ppd->pp_acc_offset *= 2; 5253 sizemask = 2; 5254 mem_va = 0; 5255 maxoff = (MII_MAXREG+1)*2; 5256 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5257 break; 5258 5259 #if BGE_SEE_IO32 5260 case BGE_PP_SPACE_SEEPROM: 5261 /* 5262 * Attached SEEPROM(s), if any. 5263 * NB: we use the high-order bits of the 'address' as 5264 * a device select to accommodate multiple SEEPROMS, 5265 * If each one is the maximum size (64kbytes), this 5266 * makes them appear contiguous. Otherwise, there may 5267 * be holes in the mapping. ENxS doesn't have any 5268 * SEEPROMs anyway ... 5269 */ 5270 sizemask = 4; 5271 mem_va = 0; 5272 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5273 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5274 break; 5275 #endif /* BGE_SEE_IO32 */ 5276 5277 #if BGE_FLASH_IO32 5278 case BGE_PP_SPACE_FLASH: 5279 /* 5280 * Attached Flash device (if any); a maximum of one device 5281 * is currently supported. But it can be up to 1MB (unlike 5282 * the 64k limit on SEEPROMs) so why would you need more ;-) 5283 */ 5284 sizemask = 4; 5285 mem_va = 0; 5286 maxoff = NVM_FLASH_ADDR_MASK; 5287 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5288 break; 5289 #endif /* BGE_FLASH_IO32 */ 5290 5291 case BGE_PP_SPACE_BGE: 5292 /* 5293 * BGE data structure! 5294 */ 5295 sizemask = 8|4|2|1; 5296 mem_va = (uintptr_t)bgep; 5297 maxoff = sizeof (*bgep); 5298 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5299 break; 5300 5301 case BGE_PP_SPACE_STATUS: 5302 case BGE_PP_SPACE_STATISTICS: 5303 case BGE_PP_SPACE_TXDESC: 5304 case BGE_PP_SPACE_TXBUFF: 5305 case BGE_PP_SPACE_RXDESC: 5306 case BGE_PP_SPACE_RXBUFF: 5307 /* 5308 * Various DMA_AREAs 5309 */ 5310 switch (ppd->pp_acc_space) { 5311 case BGE_PP_SPACE_TXDESC: 5312 areap = &bgep->tx_desc; 5313 break; 5314 case BGE_PP_SPACE_TXBUFF: 5315 areap = &bgep->tx_buff[0]; 5316 break; 5317 case BGE_PP_SPACE_RXDESC: 5318 areap = &bgep->rx_desc[0]; 5319 break; 5320 case BGE_PP_SPACE_RXBUFF: 5321 areap = &bgep->rx_buff[0]; 5322 break; 5323 case BGE_PP_SPACE_STATUS: 5324 areap = &bgep->status_block; 5325 break; 5326 case BGE_PP_SPACE_STATISTICS: 5327 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5328 areap = &bgep->statistics; 5329 break; 5330 } 5331 5332 sizemask = 8|4|2|1; 5333 mem_va = (uintptr_t)areap->mem_va; 5334 maxoff = areap->alength; 5335 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5336 break; 5337 } 5338 5339 switch (ppd->pp_acc_size) { 5340 default: 5341 return (IOC_INVAL); 5342 5343 case 8: 5344 case 4: 5345 case 2: 5346 case 1: 5347 if ((ppd->pp_acc_size & sizemask) == 0) 5348 return (IOC_INVAL); 5349 break; 5350 } 5351 5352 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5353 return (IOC_INVAL); 5354 5355 if (ppd->pp_acc_offset >= maxoff) 5356 return (IOC_INVAL); 5357 5358 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5359 return (IOC_INVAL); 5360 5361 /* 5362 * All OK - go do it! 5363 */ 5364 ppd->pp_acc_offset += mem_va; 5365 (*ppfn)(bgep, ppd); 5366 return (peek ? IOC_REPLY : IOC_ACK); 5367 } 5368 5369 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5370 struct iocblk *iocp); 5371 #pragma no_inline(bge_diag_ioctl) 5372 5373 static enum ioc_reply 5374 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5375 { 5376 ASSERT(mutex_owned(bgep->genlock)); 5377 5378 switch (cmd) { 5379 default: 5380 /* NOTREACHED */ 5381 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5382 return (IOC_INVAL); 5383 5384 case BGE_DIAG: 5385 /* 5386 * Currently a no-op 5387 */ 5388 return (IOC_ACK); 5389 5390 case BGE_PEEK: 5391 case BGE_POKE: 5392 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5393 5394 case BGE_PHY_RESET: 5395 return (IOC_RESTART_ACK); 5396 5397 case BGE_SOFT_RESET: 5398 case BGE_HARD_RESET: 5399 /* 5400 * Reset and reinitialise the 570x hardware 5401 */ 5402 bgep->bge_chip_state = BGE_CHIP_FAULT; 5403 ddi_trigger_softintr(bgep->factotum_id); 5404 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5405 return (IOC_ACK); 5406 } 5407 5408 /* NOTREACHED */ 5409 } 5410 5411 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5412 5413 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5414 struct iocblk *iocp); 5415 #pragma no_inline(bge_mii_ioctl) 5416 5417 static enum ioc_reply 5418 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5419 { 5420 struct bge_mii_rw *miirwp; 5421 5422 /* 5423 * Validate format of ioctl 5424 */ 5425 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5426 return (IOC_INVAL); 5427 if (mp->b_cont == NULL) 5428 return (IOC_INVAL); 5429 miirwp = (void *)mp->b_cont->b_rptr; 5430 5431 /* 5432 * Validate request parameters ... 5433 */ 5434 if (miirwp->mii_reg > MII_MAXREG) 5435 return (IOC_INVAL); 5436 5437 switch (cmd) { 5438 default: 5439 /* NOTREACHED */ 5440 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5441 return (IOC_INVAL); 5442 5443 case BGE_MII_READ: 5444 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5445 return (IOC_REPLY); 5446 5447 case BGE_MII_WRITE: 5448 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5449 return (IOC_ACK); 5450 } 5451 5452 /* NOTREACHED */ 5453 } 5454 5455 #if BGE_SEE_IO32 5456 5457 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5458 struct iocblk *iocp); 5459 #pragma no_inline(bge_see_ioctl) 5460 5461 static enum ioc_reply 5462 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5463 { 5464 struct bge_see_rw *seerwp; 5465 5466 /* 5467 * Validate format of ioctl 5468 */ 5469 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5470 return (IOC_INVAL); 5471 if (mp->b_cont == NULL) 5472 return (IOC_INVAL); 5473 seerwp = (void *)mp->b_cont->b_rptr; 5474 5475 /* 5476 * Validate request parameters ... 5477 */ 5478 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5479 return (IOC_INVAL); 5480 5481 switch (cmd) { 5482 default: 5483 /* NOTREACHED */ 5484 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5485 return (IOC_INVAL); 5486 5487 case BGE_SEE_READ: 5488 case BGE_SEE_WRITE: 5489 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5490 seerwp->see_addr, &seerwp->see_data); 5491 return (IOC_REPLY); 5492 } 5493 5494 /* NOTREACHED */ 5495 } 5496 5497 #endif /* BGE_SEE_IO32 */ 5498 5499 #if BGE_FLASH_IO32 5500 5501 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5502 struct iocblk *iocp); 5503 #pragma no_inline(bge_flash_ioctl) 5504 5505 static enum ioc_reply 5506 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5507 { 5508 struct bge_flash_rw *flashrwp; 5509 5510 /* 5511 * Validate format of ioctl 5512 */ 5513 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5514 return (IOC_INVAL); 5515 if (mp->b_cont == NULL) 5516 return (IOC_INVAL); 5517 flashrwp = (void *)mp->b_cont->b_rptr; 5518 5519 /* 5520 * Validate request parameters ... 5521 */ 5522 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5523 return (IOC_INVAL); 5524 5525 switch (cmd) { 5526 default: 5527 /* NOTREACHED */ 5528 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5529 return (IOC_INVAL); 5530 5531 case BGE_FLASH_READ: 5532 case BGE_FLASH_WRITE: 5533 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5534 flashrwp->flash_addr, &flashrwp->flash_data); 5535 return (IOC_REPLY); 5536 } 5537 5538 /* NOTREACHED */ 5539 } 5540 5541 #endif /* BGE_FLASH_IO32 */ 5542 5543 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5544 struct iocblk *iocp); 5545 #pragma no_inline(bge_chip_ioctl) 5546 5547 enum ioc_reply 5548 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5549 { 5550 int cmd; 5551 5552 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5553 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5554 5555 ASSERT(mutex_owned(bgep->genlock)); 5556 5557 cmd = iocp->ioc_cmd; 5558 switch (cmd) { 5559 default: 5560 /* NOTREACHED */ 5561 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5562 return (IOC_INVAL); 5563 5564 case BGE_DIAG: 5565 case BGE_PEEK: 5566 case BGE_POKE: 5567 case BGE_PHY_RESET: 5568 case BGE_SOFT_RESET: 5569 case BGE_HARD_RESET: 5570 #if BGE_DEBUGGING || BGE_DO_PPIO 5571 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5572 #else 5573 return (IOC_INVAL); 5574 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5575 5576 case BGE_MII_READ: 5577 case BGE_MII_WRITE: 5578 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5579 5580 #if BGE_SEE_IO32 5581 case BGE_SEE_READ: 5582 case BGE_SEE_WRITE: 5583 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5584 #endif /* BGE_SEE_IO32 */ 5585 5586 #if BGE_FLASH_IO32 5587 case BGE_FLASH_READ: 5588 case BGE_FLASH_WRITE: 5589 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5590 #endif /* BGE_FLASH_IO32 */ 5591 } 5592 5593 /* NOTREACHED */ 5594 } 5595 5596 /* ARGSUSED */ 5597 void 5598 bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag) 5599 { 5600 recv_ring_t *rrp = arg; 5601 bge_t *bgep = rrp->bgep; 5602 5603 mutex_enter(bgep->genlock); 5604 rrp->poll_flag = flag; 5605 #ifdef NOT_YET 5606 /* 5607 * XXX-Sunay: Since most broadcom cards support only one 5608 * interrupt but multiple rx rings, we can't disable the 5609 * physical interrupt. This need to be done via capability 5610 * negotiation depending on the NIC. 5611 */ 5612 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5613 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5614 #endif 5615 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5616 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5617 mutex_exit(bgep->genlock); 5618 } 5619 5620 #ifdef BGE_IPMI_ASF 5621 5622 uint32_t 5623 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5624 { 5625 uint32_t data; 5626 5627 #ifndef __sparc 5628 if (!bgep->asf_wordswapped) { 5629 /* a workaround word swap error */ 5630 if (addr & 4) 5631 addr = addr - 4; 5632 else 5633 addr = addr + 4; 5634 } 5635 #endif 5636 5637 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5638 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5639 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5640 5641 data = LE_32(data); 5642 return (data); 5643 } 5644 5645 void 5646 bge_asf_update_status(bge_t *bgep) 5647 { 5648 uint32_t event; 5649 5650 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5651 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5652 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5653 5654 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5655 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5656 } 5657 5658 5659 /* 5660 * The driver is supposed to notify ASF that the OS is still running 5661 * every three seconds, otherwise the management server may attempt 5662 * to reboot the machine. If it hasn't actually failed, this is 5663 * not a desirable result. However, this isn't running as a real-time 5664 * thread, and even if it were, it might not be able to generate the 5665 * heartbeat in a timely manner due to system load. As it isn't a 5666 * significant strain on the machine, we will set the interval to half 5667 * of the required value. 5668 */ 5669 void 5670 bge_asf_heartbeat(void *arg) 5671 { 5672 bge_t *bgep = (bge_t *)arg; 5673 5674 mutex_enter(bgep->genlock); 5675 bge_asf_update_status((bge_t *)bgep); 5676 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5677 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5678 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5679 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5680 mutex_exit(bgep->genlock); 5681 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5682 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5683 } 5684 5685 5686 void 5687 bge_asf_stop_timer(bge_t *bgep) 5688 { 5689 timeout_id_t tmp_id = 0; 5690 5691 while ((bgep->asf_timeout_id != 0) && 5692 (tmp_id != bgep->asf_timeout_id)) { 5693 tmp_id = bgep->asf_timeout_id; 5694 (void) untimeout(tmp_id); 5695 } 5696 bgep->asf_timeout_id = 0; 5697 } 5698 5699 5700 5701 /* 5702 * This function should be placed at the earliest position of bge_attach(). 5703 */ 5704 void 5705 bge_asf_get_config(bge_t *bgep) 5706 { 5707 uint32_t nicsig; 5708 uint32_t niccfg; 5709 5710 bgep->asf_enabled = B_FALSE; 5711 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5712 if (nicsig == BGE_NIC_DATA_SIG) { 5713 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5714 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5715 /* 5716 * Here, we don't consider BAXTER, because BGE haven't 5717 * supported BAXTER (that is 5752). Also, as I know, 5718 * BAXTER doesn't support ASF feature. 5719 */ 5720 bgep->asf_enabled = B_TRUE; 5721 else 5722 bgep->asf_enabled = B_FALSE; 5723 } else 5724 bgep->asf_enabled = B_FALSE; 5725 } 5726 5727 5728 void 5729 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5730 { 5731 uint32_t tries; 5732 uint32_t event; 5733 5734 ASSERT(bgep->asf_enabled); 5735 5736 /* Issues "pause firmware" command and wait for ACK */ 5737 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5738 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5739 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5740 5741 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5742 tries = 0; 5743 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5744 drv_usecwait(1); 5745 tries ++; 5746 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5747 } 5748 5749 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5750 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5751 5752 if (bgep->asf_newhandshake) { 5753 switch (mode) { 5754 case BGE_INIT_RESET: 5755 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5756 BGE_DRV_STATE_START); 5757 break; 5758 case BGE_SHUTDOWN_RESET: 5759 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5760 BGE_DRV_STATE_UNLOAD); 5761 break; 5762 case BGE_SUSPEND_RESET: 5763 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5764 BGE_DRV_STATE_SUSPEND); 5765 break; 5766 default: 5767 break; 5768 } 5769 } 5770 } 5771 5772 5773 void 5774 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5775 { 5776 switch (mode) { 5777 case BGE_INIT_RESET: 5778 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5779 BGE_DRV_STATE_START); 5780 break; 5781 case BGE_SHUTDOWN_RESET: 5782 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5783 BGE_DRV_STATE_UNLOAD); 5784 break; 5785 case BGE_SUSPEND_RESET: 5786 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5787 BGE_DRV_STATE_SUSPEND); 5788 break; 5789 default: 5790 break; 5791 } 5792 } 5793 5794 5795 void 5796 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5797 { 5798 switch (mode) { 5799 case BGE_INIT_RESET: 5800 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5801 BGE_DRV_STATE_START_DONE); 5802 break; 5803 case BGE_SHUTDOWN_RESET: 5804 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5805 BGE_DRV_STATE_UNLOAD_DONE); 5806 break; 5807 default: 5808 break; 5809 } 5810 } 5811 5812 #endif /* BGE_IPMI_ASF */ 5813